1 files changed, 210 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B11A/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B11A/project_template/clock_config.c
new file mode 100644
index 000000000..844a3534c
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B11A/project_template/clock_config.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
+ *    and flash clock are in allowed range during clock mode switch.
+ *
+ * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
+ *
+ * 3. Call CLOCK_SetMcgliteConfig to set MCG_Lite configuration.
+ *
+ * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
+ */
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v6.0
+processor: K32L2B11xxxxA
+package_id: K32L2B11VLH0A
+mcu_data: ksdk2_0
+processor_version: 0.0.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+#include "fsl_smc.h"
+#include "clock_config.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define OSC_CAP0P 0U                   /*!< Oscillator 0pF capacitor load */
+#define OSC_ER_CLK_DISABLE 0U          /*!< Disable external reference clock */
+#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: Bus_clock.outFreq, value: 24 MHz}
+- {id: Core_clock.outFreq, value: 48 MHz}
+- {id: Flash_clock.outFreq, value: 24 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGIRCLK.outFreq, value: 8 MHz}
+- {id: MCGPCLK.outFreq, value: 48 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: MCGMode, value: HIRC}
+- {id: MCG.CLKS.sel, value: MCG.HIRC}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: Very_high}
+- {id: MCG_MC_HIRCEN_CFG, value: Enabled}
+- {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
+- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
+- {id: SIM.CLKOUTSEL.sel, value: MCG.MCGPCLK}
+- {id: SIM.COPCLKSEL.sel, value: OSC.OSCERCLK}
+- {id: SIM.FLEXIOSRCSEL.sel, value: MCG.MCGPCLK}
+- {id: SIM.LPUART0SRCSEL.sel, value: MCG.MCGPCLK}
+- {id: SIM.LPUART1SRCSEL.sel, value: MCG.MCGPCLK}
+- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
+- {id: SIM.TPMSRCSEL.sel, value: MCG.MCGPCLK}
+- {id: SIM.USBSRCSEL.sel, value: MCG.MCGPCLK}
+sources:
+- {id: MCG.HIRC.outFreq, value: 48 MHz}
+- {id: OSC.OSC.outFreq, value: 32 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN = {
+    .outSrc          = kMCGLITE_ClkSrcHirc,  /* MCGOUTCLK source is HIRC */
+    .irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+    .ircs            = kMCGLITE_Lirc8M,      /* Slow internal reference (LIRC) 8 MHz clock selected */
+    .fcrdiv          = kMCGLITE_LircDivBy1,  /* Low-frequency Internal Reference Clock Divider: divided by 1 */
+    .lircDiv2        = kMCGLITE_LircDivBy1,  /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
+    .hircEnableInNotHircMode = true,         /* HIRC source is enabled */
+};
+const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
+    .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
+    .clkdiv1  = 0x10000U,                    /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
+};
+const osc_config_t oscConfig_BOARD_BootClockRUN = {
+    .freq        = 0U,                   /* Oscillator frequency: 0Hz */
+    .capLoad     = (OSC_CAP0P),          /* Oscillator capacity load: 0pF */
+    .workMode    = kOSC_ModeOscLowPower, /* Oscillator low power */
+    .oscerConfig = {
+        .enableMode =
+            kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
+    }};
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Set MCG to HIRC mode. */
+    CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockVLPR
+outputs:
+- {id: Bus_clock.outFreq, value: 1 MHz}
+- {id: Core_clock.outFreq, value: 2 MHz}
+- {id: Flash_clock.outFreq, value: 1 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGIRCLK.outFreq, value: 2 MHz}
+- {id: System_clock.outFreq, value: 2 MHz}
+settings:
+- {id: MCGMode, value: LIRC2M}
+- {id: powerMode, value: VLPR}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: RTCCLKOUTConfig, value: 'yes'}
+- {id: SIM.OUTDIV4.scale, value: '2', locked: true}
+- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
+sources:
+- {id: MCG.LIRC.outFreq, value: 2 MHz}
+- {id: OSC.OSC.outFreq, value: 32.768 kHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR = {
+    .outSrc          = kMCGLITE_ClkSrcLirc,  /* MCGOUTCLK source is LIRC */
+    .irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+    .ircs            = kMCGLITE_Lirc2M,      /* Slow internal reference (LIRC) 2 MHz clock selected */
+    .fcrdiv          = kMCGLITE_LircDivBy1,  /* Low-frequency Internal Reference Clock Divider: divided by 1 */
+    .lircDiv2        = kMCGLITE_LircDivBy1,  /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
+    .hircEnableInNotHircMode = false,        /* HIRC source is not enabled */
+};
+const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
+    .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
+    .clkdiv1  = 0x10000U,                    /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
+};
+const osc_config_t oscConfig_BOARD_BootClockVLPR = {
+    .freq        = 0U,                   /* Oscillator frequency: 0Hz */
+    .capLoad     = (OSC_CAP0P),          /* Oscillator capacity load: 0pF */
+    .workMode    = kOSC_ModeOscLowPower, /* Oscillator low power */
+    .oscerConfig = {
+        .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+    }};
+/*******************************************************************************
+ * Code for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Set MCG to LIRC2M mode. */
+    CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockVLPR);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+    SMC_SetPowerModeVlpr(SMC, false);
+#else
+    SMC_SetPowerModeVlpr(SMC);
+#endif
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+    {
+    }
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
+}

diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B11A/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B11A/project_template/clock_config.c new file mode 100644 index 000000000..844a3534c --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B11A/project_template/clock_config.c
@@ -0,0 +1,210 @@
	1	/*
	2	* Copyright 2019 NXP
	3	* All rights reserved.
	4	*
	5	* SPDX-License-Identifier: BSD-3-Clause
	6	*/
	7
	8	/***********************************************************************************************************************
	9	* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
	10	* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
	11	**********************************************************************************************************************/
	12	/*
	13	* How to setup clock using clock driver functions:
	14	*
	15	* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
	16	* and flash clock are in allowed range during clock mode switch.
	17	*
	18	* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
	19	*
	20	* 3. Call CLOCK_SetMcgliteConfig to set MCG_Lite configuration.
	21	*
	22	* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
	23	*/
	24
	25	/* clang-format off */
	26	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	27	!!GlobalInfo
	28	product: Clocks v6.0
	29	processor: K32L2B11xxxxA
	30	package_id: K32L2B11VLH0A
	31	mcu_data: ksdk2_0
	32	processor_version: 0.0.0
	33	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	34	/* clang-format on */
	35
	36	#include "fsl_smc.h"
	37	#include "clock_config.h"
	38
	39	/*******************************************************************************
	40	* Definitions
	41	******************************************************************************/
	42	#define OSC_CAP0P 0U /!< Oscillator 0pF capacitor load /
	43	#define OSC_ER_CLK_DISABLE 0U /!< Disable external reference clock /
	44	#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /!< OSC32KSEL select: OSC32KCLK clock /
	45
	46	/*******************************************************************************
	47	* Variables
	48	******************************************************************************/
	49	/* System clock frequency. */
	50	extern uint32_t SystemCoreClock;
	51
	52	/*******************************************************************************
	53	********************** BOARD_InitBootClocks function **********************
	54	******************************************************************************/
	55	void BOARD_InitBootClocks(void)
	56	{
	57	BOARD_BootClockRUN();
	58	}
	59
	60	/*******************************************************************************
	61	******************** Configuration BOARD_BootClockRUN *********************
	62	******************************************************************************/
	63	/* clang-format off */
	64	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	65	!!Configuration
	66	name: BOARD_BootClockRUN
	67	called_from_default_init: true
	68	outputs:
	69	- {id: Bus_clock.outFreq, value: 24 MHz}
	70	- {id: Core_clock.outFreq, value: 48 MHz}
	71	- {id: Flash_clock.outFreq, value: 24 MHz}
	72	- {id: LPO_clock.outFreq, value: 1 kHz}
	73	- {id: MCGIRCLK.outFreq, value: 8 MHz}
	74	- {id: MCGPCLK.outFreq, value: 48 MHz}
	75	- {id: System_clock.outFreq, value: 48 MHz}
	76	settings:
	77	- {id: MCGMode, value: HIRC}
	78	- {id: MCG.CLKS.sel, value: MCG.HIRC}
	79	- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
	80	- {id: MCG_C2_RANGE0_CFG, value: Very_high}
	81	- {id: MCG_MC_HIRCEN_CFG, value: Enabled}
	82	- {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
	83	- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
	84	- {id: SIM.CLKOUTSEL.sel, value: MCG.MCGPCLK}
	85	- {id: SIM.COPCLKSEL.sel, value: OSC.OSCERCLK}
	86	- {id: SIM.FLEXIOSRCSEL.sel, value: MCG.MCGPCLK}
	87	- {id: SIM.LPUART0SRCSEL.sel, value: MCG.MCGPCLK}
	88	- {id: SIM.LPUART1SRCSEL.sel, value: MCG.MCGPCLK}
	89	- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
	90	- {id: SIM.TPMSRCSEL.sel, value: MCG.MCGPCLK}
	91	- {id: SIM.USBSRCSEL.sel, value: MCG.MCGPCLK}
	92	sources:
	93	- {id: MCG.HIRC.outFreq, value: 48 MHz}
	94	- {id: OSC.OSC.outFreq, value: 32 MHz}
	95	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	96	/* clang-format on */
	97
	98	/*******************************************************************************
	99	* Variables for BOARD_BootClockRUN configuration
	100	******************************************************************************/
	101	const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN = {
	102	.outSrc = kMCGLITE_ClkSrcHirc, /* MCGOUTCLK source is HIRC */
	103	.irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
	104	.ircs = kMCGLITE_Lirc8M, /* Slow internal reference (LIRC) 8 MHz clock selected */
	105	.fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
	106	.lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
	107	.hircEnableInNotHircMode = true, /* HIRC source is enabled */
	108	};
	109	const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
	110	.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
	111	.clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
	112	};
	113	const osc_config_t oscConfig_BOARD_BootClockRUN = {
	114	.freq = 0U, /* Oscillator frequency: 0Hz */
	115	.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
	116	.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
	117	.oscerConfig = {
	118	.enableMode =
	119	kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
	120	}};
	121
	122	/*******************************************************************************
	123	* Code for BOARD_BootClockRUN configuration
	124	******************************************************************************/
	125	void BOARD_BootClockRUN(void)
	126	{
	127	/* Set the system clock dividers in SIM to safe value. */
	128	CLOCK_SetSimSafeDivs();
	129	/* Set MCG to HIRC mode. */
	130	CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
	131	/* Set the clock configuration in SIM module. */
	132	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
	133	/* Set SystemCoreClock variable. */
	134	SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
	135	}
	136
	137	/*******************************************************************************
	138	******************* Configuration BOARD_BootClockVLPR *********************
	139	******************************************************************************/
	140	/* clang-format off */
	141	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	142	!!Configuration
	143	name: BOARD_BootClockVLPR
	144	outputs:
	145	- {id: Bus_clock.outFreq, value: 1 MHz}
	146	- {id: Core_clock.outFreq, value: 2 MHz}
	147	- {id: Flash_clock.outFreq, value: 1 MHz}
	148	- {id: LPO_clock.outFreq, value: 1 kHz}
	149	- {id: MCGIRCLK.outFreq, value: 2 MHz}
	150	- {id: System_clock.outFreq, value: 2 MHz}
	151	settings:
	152	- {id: MCGMode, value: LIRC2M}
	153	- {id: powerMode, value: VLPR}
	154	- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
	155	- {id: RTCCLKOUTConfig, value: 'yes'}
	156	- {id: SIM.OUTDIV4.scale, value: '2', locked: true}
	157	- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
	158	sources:
	159	- {id: MCG.LIRC.outFreq, value: 2 MHz}
	160	- {id: OSC.OSC.outFreq, value: 32.768 kHz}
	161	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	162	/* clang-format on */
	163
	164	/*******************************************************************************
	165	* Variables for BOARD_BootClockVLPR configuration
	166	******************************************************************************/
	167	const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR = {
	168	.outSrc = kMCGLITE_ClkSrcLirc, /* MCGOUTCLK source is LIRC */
	169	.irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
	170	.ircs = kMCGLITE_Lirc2M, /* Slow internal reference (LIRC) 2 MHz clock selected */
	171	.fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
	172	.lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
	173	.hircEnableInNotHircMode = false, /* HIRC source is not enabled */
	174	};
	175	const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
	176	.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
	177	.clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
	178	};
	179	const osc_config_t oscConfig_BOARD_BootClockVLPR = {
	180	.freq = 0U, /* Oscillator frequency: 0Hz */
	181	.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
	182	.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
	183	.oscerConfig = {
	184	.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
	185	}};
	186
	187	/*******************************************************************************
	188	* Code for BOARD_BootClockVLPR configuration
	189	******************************************************************************/
	190	void BOARD_BootClockVLPR(void)
	191	{
	192	/* Set the system clock dividers in SIM to safe value. */
	193	CLOCK_SetSimSafeDivs();
	194	/* Set MCG to LIRC2M mode. */
	195	CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockVLPR);
	196	/* Set the clock configuration in SIM module. */
	197	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
	198	/* Set VLPR power mode. */
	199	SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
	200	#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
	201	SMC_SetPowerModeVlpr(SMC, false);
	202	#else
	203	SMC_SetPowerModeVlpr(SMC);
	204	#endif
	205	while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
	206	{
	207	}
	208	/* Set SystemCoreClock variable. */
	209	SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
	210	}