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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/K32L3A60/K32L3A60_cm4.h b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L3A60/K32L3A60_cm4.h
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1/*
2** ###################################################################
3** Processor: K32L3A60VPJ1A_cm4
4** Compilers: GNU C Compiler
5** IAR ANSI C/C++ Compiler for ARM
6** Keil ARM C/C++ Compiler
7** MCUXpresso Compiler
8**
9** Reference manual: K32L3ARM, Rev. 0 , 05/2019
10** Version: rev. 1.0, 2019-04-22
11** Build: b190628
12**
13** Abstract:
14** CMSIS Peripheral Access Layer for K32L3A60_cm4
15**
16** Copyright 1997-2016 Freescale Semiconductor, Inc.
17** Copyright 2016-2019 NXP
18** All rights reserved.
19**
20** SPDX-License-Identifier: BSD-3-Clause
21**
22** http: www.nxp.com
23** mail: [email protected]
24**
25** Revisions:
26** - rev. 1.0 (2019-04-22)
27** Initial version.
28**
29** ###################################################################
30*/
31
32/*!
33 * @file K32L3A60_cm4.h
34 * @version 1.0
35 * @date 2019-04-22
36 * @brief CMSIS Peripheral Access Layer for K32L3A60_cm4
37 *
38 * CMSIS Peripheral Access Layer for K32L3A60_cm4
39 */
40
41#ifndef _K32L3A60_CM4_H_
42#define _K32L3A60_CM4_H_ /**< Symbol preventing repeated inclusion */
43
44/** Memory map major version (memory maps with equal major version number are
45 * compatible) */
46#define MCU_MEM_MAP_VERSION 0x0100U
47/** Memory map minor version */
48#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
49
50
51/* ----------------------------------------------------------------------------
52 -- Interrupt vector numbers
53 ---------------------------------------------------------------------------- */
54
55/*!
56 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
57 * @{
58 */
59
60/** Interrupt Number Definitions */
61#define NUMBER_OF_INT_VECTORS 82 /**< Number of interrupts in the Vector table */
62
63typedef enum IRQn {
64 /* Auxiliary constants */
65 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
66
67 /* Core interrupts */
68 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
69 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
70 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
71 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
72 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
73 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
74 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
75 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
76 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
77
78 /* Device specific interrupts */
79 CTI0_MCM0_IRQn = 0, /**< Cross Trigger Interface 0 / Miscellaneous Control Module */
80 DMA0_IRQn = 1, /**< DMA0 channel 0 transfer complete */
81 DMA1_IRQn = 2, /**< DMA0 channel 1 transfer complete */
82 DMA2_IRQn = 3, /**< DMA0 channel 2 transfer complete */
83 DMA3_IRQn = 4, /**< DMA0 channel 3 transfer complete */
84 DMA4_IRQn = 5, /**< DMA0 channel 4 transfer complete */
85 DMA5_IRQn = 6, /**< DMA0 channel 5 transfer complete */
86 DMA6_IRQn = 7, /**< DMA0 channel 6 transfer complete */
87 DMA7_IRQn = 8, /**< DMA0 channel 7 transfer complete */
88 DMA8_IRQn = 9, /**< DMA0 channel 8 transfer complete */
89 DMA9_IRQn = 10, /**< DMA0 channel 9 transfer complete */
90 DMA10_IRQn = 11, /**< DMA0 channel 10 transfer complete */
91 DMA11_IRQn = 12, /**< DMA0 channel 11 transfer complete */
92 DMA12_IRQn = 13, /**< DMA0 channel 12 transfer complete */
93 DMA13_IRQn = 14, /**< DMA0 channel 13 transfer complete */
94 DMA14_IRQn = 15, /**< DMA0 channel 14 transfer complete */
95 DMA15_IRQn = 16, /**< DMA0 channel 15 transfer complete */
96 DMA0_Error_IRQn = 17, /**< DMA0 channel 0-15 error interrupt */
97 MSMC_IRQn = 18, /**< MSMC (SMC0) interrupt */
98 EWM_IRQn = 19, /**< EWM interrupt */
99 FTFE_Command_Complete_IRQn = 20, /**< FTFE interrupt */
100 FTFE_Read_Collision_IRQn = 21, /**< FTFE interrupt */
101 LLWU0_IRQn = 22, /**< Low leakage wakeup 0 */
102 MUA_IRQn = 23, /**< MU Side A interrupt */
103 SPM_IRQn = 24, /**< SPM */
104 WDOG0_IRQn = 25, /**< WDOG0 interrupt */
105 SCG_IRQn = 26, /**< SCG interrupt */
106 LPIT0_IRQn = 27, /**< LPIT0 interrupt */
107 RTC_IRQn = 28, /**< RTC Alarm interrupt */
108 LPTMR0_IRQn = 29, /**< LPTMR0 interrupt */
109 LPTMR1_IRQn = 30, /**< LPTMR1 interrupt */
110 TPM0_IRQn = 31, /**< TPM0 single interrupt vector for all sources */
111 TPM1_IRQn = 32, /**< TPM1 single interrupt vector for all sources */
112 TPM2_IRQn = 33, /**< TPM2 single interrupt vector for all sources */
113 EMVSIM0_IRQn = 34, /**< EMVSIM0 interrupt */
114 FLEXIO0_IRQn = 35, /**< FLEXIO0 */
115 LPI2C0_IRQn = 36, /**< LPI2C0 interrupt */
116 LPI2C1_IRQn = 37, /**< LPI2C1 interrupt */
117 LPI2C2_IRQn = 38, /**< LPI2C2 interrupt */
118 I2S0_IRQn = 39, /**< I2S0 interrupt */
119 USDHC0_IRQn = 40, /**< SDHC0 interrupt */
120 LPSPI0_IRQn = 41, /**< LPSPI0 single interrupt vector for all sources */
121 LPSPI1_IRQn = 42, /**< LPSPI1 single interrupt vector for all sources */
122 LPSPI2_IRQn = 43, /**< LPSPI2 single interrupt vector for all sources */
123 LPUART0_IRQn = 44, /**< LPUART0 status and error */
124 LPUART1_IRQn = 45, /**< LPUART1 status and error */
125 LPUART2_IRQn = 46, /**< LPUART2 status and error */
126 USB0_IRQn = 47, /**< USB0 interrupt */
127 PORTA_IRQn = 48, /**< PORTA Pin detect */
128 PORTB_IRQn = 49, /**< PORTB Pin detect */
129 PORTC_IRQn = 50, /**< PORTC Pin detect */
130 PORTD_IRQn = 51, /**< PORTD Pin detect */
131 LPADC0_IRQn = 52, /**< LPADC0 interrupt */
132 LPCMP0_IRQn = 53, /**< LPCMP0 interrupt */
133 LPDAC0_IRQn = 54, /**< LPDAC0 interrupt */
134 CAU3_Task_Complete_IRQn = 55, /**< Cryptographic Acceleration Unit version 3 Task Complete */
135 CAU3_Security_Violation_IRQn = 56, /**< Cryptographic Acceleration Unit version 3 Security Violation */
136 TRNG_IRQn = 57, /**< TRNG interrupt */
137 LPIT1_IRQn = 58, /**< LPIT1 interrupt */
138 LPTMR2_IRQn = 59, /**< LPTMR2 interrupt */
139 TPM3_IRQn = 60, /**< TPM3 single interrupt vector for all sources */
140 LPI2C3_IRQn = 61, /**< LPI2C3 interrupt */
141 LPSPI3_IRQn = 62, /**< LPSPI3 single interrupt vector for all sources */
142 LPUART3_IRQn = 63, /**< LPUART3 status and error */
143 PORTE_IRQn = 64, /**< PORTE Pin detect */
144 LPCMP1_IRQn = 65 /**< LPCMP1 interrupt */
145} IRQn_Type;
146
147/*!
148 * @}
149 */ /* end of group Interrupt_vector_numbers */
150
151
152/* ----------------------------------------------------------------------------
153 -- Cortex M4 Core Configuration
154 ---------------------------------------------------------------------------- */
155
156/*!
157 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
158 * @{
159 */
160
161#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
162#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
163#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
164#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
165
166#include "core_cm4.h" /* Core Peripheral Access Layer */
167#include "system_K32L3A60_cm4.h" /* Device specific configuration file */
168
169/*!
170 * @}
171 */ /* end of group Cortex_Core_Configuration */
172
173
174/* ----------------------------------------------------------------------------
175 -- Mapping Information
176 ---------------------------------------------------------------------------- */
177
178/*!
179 * @addtogroup Mapping_Information Mapping Information
180 * @{
181 */
182
183/** Mapping Information */
184/*!
185 * @addtogroup edma_request
186 * @{ */
187
188/*******************************************************************************
189 * Definitions
190*******************************************************************************/
191
192/*!
193 * @brief Enumeration for the DMA hardware request
194 *
195 * Defines the enumeration for the DMA hardware request collections.
196 */
197typedef enum _dma_request_source
198{
199 kDmaRequestMux0LLWU0 = 0|0x100U, /**< LLWU0 Wakeup */
200 kDmaRequestMux0LPTMR0 = 1|0x100U, /**< LPTMR0 Trigger */
201 kDmaRequestMux0LPTMR1 = 2|0x100U, /**< LPTMR1 Trigger */
202 kDmaRequestMux0TPM0Channel0 = 3|0x100U, /**< TPM0 Channel 0 */
203 kDmaRequestMux0TPM0Channel1 = 4|0x100U, /**< TPM0 Channel 1 */
204 kDmaRequestMux0TPM0Channel2 = 5|0x100U, /**< TPM0 Channel 2 */
205 kDmaRequestMux0TPM0Channel3 = 6|0x100U, /**< TPM0 Channel 3 */
206 kDmaRequestMux0TPM0Channel4 = 7|0x100U, /**< TPM0 Channel 4 */
207 kDmaRequestMux0TPM0Channel5 = 8|0x100U, /**< TPM0 Channel 5 */
208 kDmaRequestMux0TPM0Overflow = 9|0x100U, /**< TPM0 Overflow */
209 kDmaRequestMux0TPM1Channel0 = 10|0x100U, /**< TPM1 Channel 0 */
210 kDmaRequestMux0TPM1Channel1 = 11|0x100U, /**< TPM1 Channel 1 */
211 kDmaRequestMux0TPM1Overflow = 12|0x100U, /**< TPM1 Overflow */
212 kDmaRequestMux0TPM2Channel0 = 13|0x100U, /**< TPM2 Channel 0 */
213 kDmaRequestMux0TPM2Channel1 = 14|0x100U, /**< TPM2 Channel 1 */
214 kDmaRequestMux0TPM2Channel2 = 15|0x100U, /**< TPM2 Channel 2 */
215 kDmaRequestMux0TPM2Channel3 = 16|0x100U, /**< TPM2 Channel 3 */
216 kDmaRequestMux0TPM2Channel4 = 17|0x100U, /**< TPM2 Channel 4 */
217 kDmaRequestMux0TPM2Channel5 = 18|0x100U, /**< TPM2 Channel 5 */
218 kDmaRequestMux0TPM2Overflow = 19|0x100U, /**< TPM2 Overflow */
219 kDmaRequestMux0EMVSIM0Rx = 20|0x100U, /**< EMVSIM0 Receive */
220 kDmaRequestMux0EMVSIM0Tx = 21|0x100U, /**< EMVSIM0 Transmit */
221 kDmaRequestMux0FLEXIO0Channel0 = 22|0x100U, /**< FLEXIO0 Channel 0 */
222 kDmaRequestMux0FLEXIO0Channel1 = 23|0x100U, /**< FLEXIO0 Channel 1 */
223 kDmaRequestMux0FLEXIO0Channel2 = 24|0x100U, /**< FLEXIO0 Channel 2 */
224 kDmaRequestMux0FLEXIO0Channel3 = 25|0x100U, /**< FLEXIO0 Channel 3 */
225 kDmaRequestMux0FLEXIO0Channel4 = 26|0x100U, /**< FLEXIO0 Channel 4 */
226 kDmaRequestMux0FLEXIO0Channel5 = 27|0x100U, /**< FLEXIO0 Channel 5 */
227 kDmaRequestMux0FLEXIO0Channel6 = 28|0x100U, /**< FLEXIO0 Channel 6 */
228 kDmaRequestMux0FLEXIO0Channel7 = 29|0x100U, /**< FLEXIO0 Channel 7 */
229 kDmaRequestMux0LPI2C0Rx = 30|0x100U, /**< LPI2C0 Receive */
230 kDmaRequestMux0LPI2C0Tx = 31|0x100U, /**< LPI2C0 Transmit */
231 kDmaRequestMux0LPI2C1Rx = 32|0x100U, /**< LPI2C1 Receive */
232 kDmaRequestMux0LPI2C1Tx = 33|0x100U, /**< LPI2C1 Transmit */
233 kDmaRequestMux0LPI2C2Rx = 34|0x100U, /**< LPI2C2 Receive */
234 kDmaRequestMux0LPI2C2Tx = 35|0x100U, /**< LPI2C2 Transmit */
235 kDmaRequestMux0I2S0Rx = 36|0x100U, /**< I2S0 Receive */
236 kDmaRequestMux0I2S0Tx = 37|0x100U, /**< I2S0 Transmit */
237 kDmaRequestMux0LPSPI0Rx = 38|0x100U, /**< LPSPI0 Receive */
238 kDmaRequestMux0LPSPI0Tx = 39|0x100U, /**< LPSPI0 Transmit */
239 kDmaRequestMux0LPSPI1Rx = 40|0x100U, /**< LPSPI1 Receive */
240 kDmaRequestMux0LPSPI1Tx = 41|0x100U, /**< LPSPI1 Transmit */
241 kDmaRequestMux0LPSPI2Rx = 42|0x100U, /**< LPSPI2 Receive */
242 kDmaRequestMux0LPSPI2Tx = 43|0x100U, /**< LPSPI2 Transmit */
243 kDmaRequestMux0LPUART0Rx = 44|0x100U, /**< LPUART0 Receive */
244 kDmaRequestMux0LPUART0Tx = 45|0x100U, /**< LPUART0 Transmit */
245 kDmaRequestMux0LPUART1Rx = 46|0x100U, /**< LPUART1 Receive */
246 kDmaRequestMux0LPUART1Tx = 47|0x100U, /**< LPUART1 Transmit */
247 kDmaRequestMux0LPUART2Rx = 48|0x100U, /**< LPUART2 Receive */
248 kDmaRequestMux0LPUART2Tx = 49|0x100U, /**< LPUART2 Transmit */
249 kDmaRequestMux0PORTA = 50|0x100U, /**< PORTA Pin Request */
250 kDmaRequestMux0PORTB = 51|0x100U, /**< PORTB Pin Request */
251 kDmaRequestMux0PORTC = 52|0x100U, /**< PORTC Pin Request */
252 kDmaRequestMux0PORTD = 53|0x100U, /**< PORTD Pin Request */
253 kDmaRequestMux0LPADC0 = 54|0x100U, /**< LPADC0 Conversion Complete */
254 kDmaRequestMux0LPCMP0 = 55|0x100U, /**< LPCMP0 Comparator Trigger */
255 kDmaRequestMux0DAC0 = 56|0x100U, /**< DAC0 Conversion Complete */
256 kDmaRequestMux0CAU3 = 57|0x100U, /**< CAU3 Data Request */
257 kDmaRequestMux0LPTMR2 = 58|0x100U, /**< LPTMR2 Trigger */
258 kDmaRequestMux0LPSPI3Rx = 59|0x100U, /**< LPSPI3 Receive */
259 kDmaRequestMux0LPSPI3Tx = 60|0x100U, /**< LPSPI3 Transmit */
260 kDmaRequestMux0LPUART3Rx = 61|0x100U, /**< LPUART3 Receive */
261 kDmaRequestMux0LPUART3Tx = 62|0x100U, /**< LPUART3 Transmit */
262 kDmaRequestMux0PORTE = 63|0x100U, /**< PORTE Pin Request */
263} dma_request_source_t;
264
265/* @} */
266
267/*!
268 * @addtogroup trgmux_source
269 * @{ */
270
271/*******************************************************************************
272 * Definitions
273*******************************************************************************/
274
275/*!
276 * @brief Enumeration for the TRGMUX source
277 *
278 * Defines the enumeration for the TRGMUX source collections.
279 */
280typedef enum _trgmux_source
281{
282 kTRGMUX_Source0Disabled = 0U, /**< Trigger function is disabled */
283 kTRGMUX_Source1Disabled = 0U, /**< Trigger function is disabled */
284 kTRGMUX_Source0Llwu0 = 1U, /**< LLWU0 trigger is selected */
285 kTRGMUX_Source1Llwu1 = 1U, /**< LLWU1 trigger is selected */
286 kTRGMUX_Source0Lpit0Channel0 = 2U, /**< LPIT0 Channel 0 is selected */
287 kTRGMUX_Source1Lpit1Channel0 = 2U, /**< LPIT1 Channel 0 is selected */
288 kTRGMUX_Source0Lpit0Channel1 = 3U, /**< LPIT0 Channel 1 is selected */
289 kTRGMUX_Source1Lpit1Channel1 = 3U, /**< LPIT1 Channel 1 is selected */
290 kTRGMUX_Source0Lpit0Channel2 = 4U, /**< LPIT0 Channel 2 is selected */
291 kTRGMUX_Source1Lpit1Channel2 = 4U, /**< LPIT1 Channel 2 is selected */
292 kTRGMUX_Source0Lpit0Channel3 = 5U, /**< LPIT0 Channel 3 is selected */
293 kTRGMUX_Source1Lpit1Channel3 = 5U, /**< LPIT1 Channel 3 is selected */
294 kTRGMUX_Source0RtcAlarm = 6U, /**< RTC Alarm is selected */
295 kTRGMUX_Source1Lptmr2Trigger = 6U, /**< LPTMR2 Trigger is selected */
296 kTRGMUX_Source0RtcSeconds = 7U, /**< RTC Seconds is selected */
297 kTRGMUX_Source1Tpm3ChannelEven = 7U, /**< TPM3 Channel Even is selected */
298 kTRGMUX_Source0Lptmr0Trigger = 8U, /**< LPTMR0 Trigger is selected */
299 kTRGMUX_Source1Tpm3ChannelOdd = 8U, /**< TPM3 Channel Odd is selected */
300 kTRGMUX_Source0Lptmr1Trigger = 9U, /**< LPTMR1 Trigger is selected */
301 kTRGMUX_Source1Tpm3Overflow = 9U, /**< TPM3 Overflow is selected */
302 kTRGMUX_Source0Tpm0ChannelEven = 10U, /**< TPM0 Channel Even is selected */
303 kTRGMUX_Source1Lpi2c3MasterStop = 10U, /**< LPI2C3 Master Stop is selected */
304 kTRGMUX_Source0Tpm0ChannelOdd = 11U, /**< TPM0 Channel Odd is selected */
305 kTRGMUX_Source1Lpi2c3SlaveStop = 11U, /**< LPI2C3 Slave Stop is selected */
306 kTRGMUX_Source0Tpm0Overflow = 12U, /**< TPM0 Overflow is selected */
307 kTRGMUX_Source1Lpspi3Frame = 12U, /**< LPSPI3 Frame is selected */
308 kTRGMUX_Source0Tpm1ChannelEven = 13U, /**< TPM1 Channel Even is selected */
309 kTRGMUX_Source1Lpspi3RX = 13U, /**< LPSPI3 Rx is selected */
310 kTRGMUX_Source0Tpm1ChannelOdd = 14U, /**< TPM1 Channel Odd is selected */
311 kTRGMUX_Source1Lpuart3RxData = 14U, /**< LPUART3 Rx Data is selected */
312 kTRGMUX_Source0Tpm1Overflow = 15U, /**< TPM1 Overflow is selected */
313 kTRGMUX_Source1Lpuart3RxIdle = 15U, /**< LPUART3 Rx Idle is selected */
314 kTRGMUX_Source0Tpm2ChannelEven = 16U, /**< TPM2 Channel Even is selected */
315 kTRGMUX_Source1Lpuart3TxData = 16U, /**< LPUART3 Tx Data is selected */
316 kTRGMUX_Source0Tpm2ChannelOdd = 17U, /**< TPM2 Channel Odd is selected */
317 kTRGMUX_Source1PortEPinTrigger = 17U, /**< PORTE Pin Trigger is selected */
318 kTRGMUX_Source0Tpm2Overflow = 18U, /**< TPM2 Overflow is selected */
319 kTRGMUX_Source1Lpcmp1Output = 18U, /**< LPCMP1 Output is selected */
320 kTRGMUX_Source0FlexIO0Timer0 = 19U, /**< FlexIO0 Timer 0 is selected */
321 kTRGMUX_Source1RtcAlarm = 19U, /**< RTC Alarm is selected */
322 kTRGMUX_Source0FlexIO0Timer1 = 20U, /**< FlexIO0 Timer 1 is selected */
323 kTRGMUX_Source1RtcSeconds = 20U, /**< RTC Seconds is selected */
324 kTRGMUX_Source0FlexIO0Timer2 = 21U, /**< FlexIO0 Timer 2 is selected */
325 kTRGMUX_Source1Lptmr0Trigger = 21U, /**< LPTMR0 Trigger is selected */
326 kTRGMUX_Source0FlexIO0Timer3 = 22U, /**< FlexIO0 Timer 3 is selected */
327 kTRGMUX_Source1Lptmr1Trigger = 22U, /**< LPTMR1 Trigger is selected */
328 kTRGMUX_Source0FlexIO0Timer4 = 23U, /**< FLexIO0 Timer 4 is selected */
329 kTRGMUX_Source1Tpm1ChannelEven = 23U, /**< TPM1 Channel Even is selected */
330 kTRGMUX_Source0FlexIO0Timer5 = 24U, /**< FlexIO0 Timer 5 is selected */
331 kTRGMUX_Source1Tpm1ChannelOdd = 24U, /**< TPM1 Channel Odd is selected */
332 kTRGMUX_Source0FlexIO0Timer6 = 25U, /**< FlexIO0 Timer 6 is selected */
333 kTRGMUX_Source1Tpm1Overflow = 25U, /**< TPM1 Overflow is selected */
334 kTRGMUX_Source0FlexIO0Timer7 = 26U, /**< FlexIO0 Timer 7 is selected */
335 kTRGMUX_Source1Tpm2ChannelEven = 26U, /**< TPM2 Channel Even is selected */
336 kTRGMUX_Source0Lpi2c0MasterStop = 27U, /**< LPI2C0 Master Stop is selected */
337 kTRGMUX_Source1Tpm2ChannelOdd = 27U, /**< TPM2 Channel Odd is selected */
338 kTRGMUX_Source0Lpi2c0SlaveStop = 28U, /**< LPI2C0 Slave Stop is selected */
339 kTRGMUX_Source1Tpm2Overflow = 28U, /**< TPM2 Overflow is selected */
340 kTRGMUX_Source0Lpi2c1MasterStop = 29U, /**< LPI2C1 Master Stop is selected */
341 kTRGMUX_Source1FlexIO0Timer0 = 29U, /**< FlexIO0 Timer 0 is selected */
342 kTRGMUX_Source0Lpi2c1SlaveStop = 30U, /**< LPI2C1 Slave Stop is selected */
343 kTRGMUX_Source1FlexIO0Timer1 = 30U, /**< FlexIO0 Timer 1 is selected */
344 kTRGMUX_Source0Lpi2c2MasterStop = 31U, /**< LPI2C2 Master Stop is selected */
345 kTRGMUX_Source1FlexIO0Timer2 = 31U, /**< FlexIO0 Timer 2 is selected */
346 kTRGMUX_Source0Lpi2c2SlaveStop = 32U, /**< LPI2C2 Slave Stop is selected */
347 kTRGMUX_Source1FlexIO0Timer3 = 32U, /**< FlexIO0 Timer 3 is selected */
348 kTRGMUX_Source0Sai0Rx = 33U, /**< SAI0 Rx Frame Sync is selected */
349 kTRGMUX_Source1FlexIO0Timer4 = 33U, /**< FLexIO0 Timer 4 is selected */
350 kTRGMUX_Source0Sai0Tx = 34U, /**< SAI0 Tx Frame Sync is selected */
351 kTRGMUX_Source1FlexIO0Timer5 = 34U, /**< FlexIO0 Timer 5 is selected */
352 kTRGMUX_Source0Lpspi0Frame = 35U, /**< LPSPI0 Frame is selected */
353 kTRGMUX_Source1FlexIO0Timer6 = 35U, /**< FlexIO0 Timer 6 is selected */
354 kTRGMUX_Source0Lpspi0Rx = 36U, /**< LPSPI0 Rx is selected */
355 kTRGMUX_Source1FlexIO0Timer7 = 36U, /**< FlexIO0 Timer 7 is selected */
356 kTRGMUX_Source0Lpspi1Frame = 37U, /**< LPSPI1 Frame is selected */
357 kTRGMUX_Source1Lpi2c0MasterStop = 37U, /**< LPI2C0 Master Stop is selected */
358 kTRGMUX_Source0Lpspi1Rx = 38U, /**< LPSPI1 Rx is selected */
359 kTRGMUX_Source1Lpi2c0SlaveStop = 38U, /**< LPI2C0 Slave Stop is selected */
360 kTRGMUX_Source0Lpspi2Frame = 39U, /**< LPSPI2 Frame is selected */
361 kTRGMUX_Source1Lpi2c1MasterStop = 39U, /**< LPI2C1 Master Stop is selected */
362 kTRGMUX_Source0Lpspi2RX = 40U, /**< LPSPI2 Rx is selected */
363 kTRGMUX_Source1Lpi2c1SlaveStop = 40U, /**< LPI2C1 Slave Stop is selected */
364 kTRGMUX_Source0Lpuart0RxData = 41U, /**< LPUART0 Rx Data is selected */
365 kTRGMUX_Source1Lpi2c2MasterStop = 41U, /**< LPI2C2 Master Stop is selected */
366 kTRGMUX_Source0Lpuart0RxIdle = 42U, /**< LPUART0 Rx Idle is selected */
367 kTRGMUX_Source1Lpi2c2SlaveStop = 42U, /**< LPI2C2 Slave Stop is selected */
368 kTRGMUX_Source0Lpuart0TxData = 43U, /**< LPUART0 Tx Data is selected */
369 kTRGMUX_Source1Sai0Rx = 43U, /**< SAI0 Rx Frame Sync is selected */
370 kTRGMUX_Source0Lpuart1RxData = 44U, /**< LPUART1 Rx Data is selected */
371 kTRGMUX_Source1Sai0Tx = 44U, /**< SAI0 Tx Frame Sync is selected */
372 kTRGMUX_Source0Lpuart1RxIdle = 45U, /**< LPUART1 Rx Idle is selected */
373 kTRGMUX_Source1Lpspi0Frame = 45U, /**< LPSPI0 Frame is selected */
374 kTRGMUX_Source0Lpuart1TxData = 46U, /**< LPUART1 TX Data is selected */
375 kTRGMUX_Source1Lpspi0Rx = 46U, /**< LPSPI0 Rx is selected */
376 kTRGMUX_Source0Lpuart2RxData = 47U, /**< LPUART2 RX Data is selected */
377 kTRGMUX_Source1Lpspi1Frame = 47U, /**< LPSPI1 Frame is selected */
378 kTRGMUX_Source0Lpuart2RxIdle = 48U, /**< LPUART2 RX Idle is selected */
379 kTRGMUX_Source1Lpspi1Rx = 48U, /**< LPSPI1 Rx is selected */
380 kTRGMUX_Source0Lpuart2TxData = 49U, /**< LPUART2 TX Data is selected */
381 kTRGMUX_Source1Lpspi2Frame = 49U, /**< LPSPI2 Frame is selected */
382 kTRGMUX_Source0Usb0Frame = 50U, /**< USB0 Start of Frame is selected */
383 kTRGMUX_Source1Lpspi2RX = 50U, /**< LPSPI2 Rx is selected */
384 kTRGMUX_Source0PortAPinTrigger = 51U, /**< PORTA Pin Trigger is selected */
385 kTRGMUX_Source1Lpuart0RxData = 51U, /**< LPUART0 Rx Data is selected */
386 kTRGMUX_Source0PortBPinTrigger = 52U, /**< PORTB Pin Trigger is selected */
387 kTRGMUX_Source1Lpuart0RxIdle = 52U, /**< LPUART0 Rx Idle is selected */
388 kTRGMUX_Source0PortCPinTrigger = 53U, /**< PORTC Pin Trigger is selected */
389 kTRGMUX_Source1Lpuart0TxData = 53U, /**< LPUART0 Tx Data is selected */
390 kTRGMUX_Source0PortDPinTrigger = 54U, /**< PORTD Pin Trigger is selected */
391 kTRGMUX_Source1Lpuart1RxData = 54U, /**< LPUART1 Rx Data is selected */
392 kTRGMUX_Source0Lpcmp0Output = 55U, /**< LPCMP0 Output is selected */
393 kTRGMUX_Source1Lpuart1RxIdle = 55U, /**< LPUART1 Rx Idle is selected */
394 kTRGMUX_Source0Lpi2c3MasterStop = 56U, /**< LPI2C3 Master Stop is selected */
395 kTRGMUX_Source1Lpuart1TxData = 56U, /**< LPUART1 TX Data is selected */
396 kTRGMUX_Source0Lpi2c3SlaveStop = 57U, /**< LPI2C3 Slave Stop is selected */
397 kTRGMUX_Source1Lpuart2RxData = 57U, /**< LPUART2 RX Data is selected */
398 kTRGMUX_Source0Lpspi3Frame = 58U, /**< LPSPI3 Frame is selected */
399 kTRGMUX_Source1Lpuart2RxIdle = 58U, /**< LPUART2 RX Idle is selected */
400 kTRGMUX_Source0Lpspi3Rx = 59U, /**< LPSPI3 Rx Data is selected */
401 kTRGMUX_Source1Lpuart2TxData = 59U, /**< LPUART2 TX Data is selected */
402 kTRGMUX_Source0Lpuart3RxData = 60U, /**< LPUART3 Rx Data is selected */
403 kTRGMUX_Source1PortAPinTrigger = 60U, /**< PORTA Pin Trigger is selected */
404 kTRGMUX_Source0Lpuart3RxIdle = 61U, /**< LPUART3 Rx Idle is selected */
405 kTRGMUX_Source1PortBPinTrigger = 61U, /**< PORTB Pin Trigger is selected */
406 kTRGMUX_Source0Lpuart3TxData = 62U, /**< LPUART3 Tx Data is selected */
407 kTRGMUX_Source1PortCPinTrigger = 62U, /**< PORTC Pin Trigger is selected */
408 kTRGMUX_Source0PortEPinTrigger = 63U, /**< PORTE Pin Trigger is selected */
409 kTRGMUX_Source1PortDPinTrigger = 63U, /**< PORTD Pin Trigger is selected */
410} trgmux_source_t;
411
412/* @} */
413
414/*!
415 * @brief Enumeration for the TRGMUX device
416 *
417 * Defines the enumeration for the TRGMUX device collections.
418 */
419typedef enum _trgmux_device
420{
421 kTRGMUX_Trgmux0Dmamux0 = 0U, /**< DMAMUX0 device trigger input */
422 kTRGMUX_Trgmux1Dmamux1 = 0U, /**< DMAMUX1 device trigger input */
423 kTRGMUX_Trgmux0Lpit0 = 1U, /**< LPIT0 device trigger input */
424 kTRGMUX_Trgmux1Lpit1 = 1U, /**< LPIT1 device trigger input */
425 kTRGMUX_Trgmux0Tpm0 = 2U, /**< TPM0 device trigger input */
426 kTRGMUX_Trgmux1Tpm3 = 2U, /**< TPM3 device trigger input */
427 kTRGMUX_Trgmux0Tpm1 = 3U, /**< TPM1 device trigger input */
428 kTRGMUX_Trgmux1Lpi2c3 = 3U, /**< LPI2C3 device trigger input */
429 kTRGMUX_Trgmux0Tpm2 = 4U, /**< TPM2 device trigger input */
430 kTRGMUX_Trgmux1Lpspi3 = 4U, /**< LPSPI3 device trigger input */
431 kTRGMUX_Trgmux0Flexio0 = 5U, /**< FLEXIO0 device trigger input */
432 kTRGMUX_Trgmux1Lpuart3 = 5U, /**< LPUART3 device trigger input */
433 kTRGMUX_Trgmux0Lpi2c0 = 6U, /**< LPI2C0 device trigger input */
434 kTRGMUX_Trgmux1Lpcmp1 = 6U, /**< LPCMP1 device trigger input */
435 kTRGMUX_Trgmux0Lpi2c1 = 7U, /**< LPI2C1 device trigger input */
436 kTRGMUX_Trgmux1Dmamux0 = 7U, /**< DMAMUX0 device trigger input */
437 kTRGMUX_Trgmux0Lpi2c2 = 8U, /**< LPI2C2 device trigger input */
438 kTRGMUX_Trgmux1Lpit0 = 8U, /**< LPIT0 device trigger input */
439 kTRGMUX_Trgmux0Lpspi0 = 9U, /**< LPSPI0 device trigger input */
440 kTRGMUX_Trgmux1Tpm0 = 9U, /**< TPM0 device trigger input */
441 kTRGMUX_Trgmux0Lpspi1 = 10U, /**< LPSPI1 device trigger input */
442 kTRGMUX_Trgmux1Tpm1 = 10U, /**< TPM1 device trigger input */
443 kTRGMUX_Trgmux0Lpspi2 = 11U, /**< LPSPI2 device trigger input */
444 kTRGMUX_Trgmux1Tpm2 = 11U, /**< TPM2 device trigger input */
445 kTRGMUX_Trgmux0Lpuart0 = 12U, /**< LPUART0 device trigger input */
446 kTRGMUX_Trgmux1Flexio0 = 12U, /**< FLEXIO0 device trigger input */
447 kTRGMUX_Trgmux0Lpuart1 = 13U, /**< LPUART1 device trigger input */
448 kTRGMUX_Trgmux1Lpi2c0 = 13U, /**< LPI2C0 device trigger input */
449 kTRGMUX_Trgmux0Lpuart2 = 14U, /**< LPUART2 device trigger input */
450 kTRGMUX_Trgmux1Lpi2c1 = 14U, /**< LPI2C1 device trigger input */
451 kTRGMUX_Trgmux0Lpadc0 = 15U, /**< LPADC0 device trigger input */
452 kTRGMUX_Trgmux1Lpi2c2 = 15U, /**< LPI2C2 device trigger input */
453 kTRGMUX_Trgmux0Lpcmp0 = 16U, /**< LPCMP0 device trigger input */
454 kTRGMUX_Trgmux1Lpspi0 = 16U, /**< LPSPI0 device trigger input */
455 kTRGMUX_Trgmux0Lpdac0 = 17U, /**< LPDAC0 device trigger input */
456 kTRGMUX_Trgmux1Lpspi1 = 17U, /**< LPSPI1 device trigger input */
457 kTRGMUX_Trgmux0Dmamux1 = 18U, /**< DMAMUX1 device trigger input */
458 kTRGMUX_Trgmux1Lpspi2 = 18U, /**< LPSPI2 device trigger input */
459 kTRGMUX_Trgmux0Lpit1 = 19U, /**< LPIT1 device trigger input */
460 kTRGMUX_Trgmux1Lpuart0 = 19U, /**< LPUART0 device trigger input */
461 kTRGMUX_Trgmux0Tpm3 = 20U, /**< TPM3 device trigger input */
462 kTRGMUX_Trgmux1Lpuart1 = 20U, /**< LPUART1 device trigger input */
463 kTRGMUX_Trgmux0Lpi2c3 = 21U, /**< LPI2C3 device trigger input */
464 kTRGMUX_Trgmux1Lpuart2 = 21U, /**< LPUART2 device trigger input */
465 kTRGMUX_Trgmux0Lpspi3 = 22U, /**< LPSPI3 device trigger input */
466 kTRGMUX_Trgmux1Lpadc0 = 22U, /**< LPADC0 device trigger input */
467 kTRGMUX_Trgmux0Lpuart3 = 23U, /**< LPUART3 device trigger input */
468 kTRGMUX_Trgmux1Lpcmp0 = 23U, /**< LPCMP0 device trigger input */
469 kTRGMUX_Trgmux0Lpcmp1 = 24U, /**< LPCMP1 device trigger input */
470 kTRGMUX_Trgmux1Lpdac0 = 24U, /**< LPDAC0 device trigger input */
471} trgmux_device_t;
472
473/* @} */
474
475/*!
476 * @addtogroup xrdc_mapping
477 * @{
478 */
479
480/*******************************************************************************
481 * Definitions
482 ******************************************************************************/
483
484/*!
485 * @brief Structure for the XRDC mapping
486 *
487 * Defines the structure for the XRDC resource collections.
488 */
489
490typedef enum _xrdc_master
491{
492 kXRDC_MasterCM4CodeBus = 0U, /**< CM4 C-BUS */
493 kXRDC_MasterCM4SystemBus = 1U, /**< CM4 S-BUS */
494 kXRDC_MasterEdma0 = 2U, /**< EDMA0 */
495 kXRDC_MasterUsdhc = 3U, /**< USDHC */
496 kXRDC_MasterUsb = 4U, /**< USB */
497 kXRDC_MasterCM0P = 32U, /**< CM0P */
498 kXRDC_MasterEdma1 = 33U, /**< EDMA1 */
499 kXRDC_MasterCau3 = 34U, /**< CAU3 */
500} xrdc_master_t;
501
502/* @} */
503
504typedef enum _xrdc_mem
505{
506 kXRDC_MemMrc0_0 = 0U, /**< MRC0 Memory 0 */
507 kXRDC_MemMrc0_1 = 1U, /**< MRC0 Memory 1 */
508 kXRDC_MemMrc0_2 = 2U, /**< MRC0 Memory 2 */
509 kXRDC_MemMrc0_3 = 3U, /**< MRC0 Memory 3 */
510 kXRDC_MemMrc0_4 = 4U, /**< MRC0 Memory 4 */
511 kXRDC_MemMrc0_5 = 5U, /**< MRC0 Memory 5 */
512 kXRDC_MemMrc0_6 = 6U, /**< MRC0 Memory 6 */
513 kXRDC_MemMrc0_7 = 7U, /**< MRC0 Memory 7 */
514 kXRDC_MemMrc1_0 = 16U, /**< MRC1 Memory 0 */
515 kXRDC_MemMrc1_1 = 17U, /**< MRC1 Memory 1 */
516 kXRDC_MemMrc1_2 = 18U, /**< MRC1 Memory 2 */
517 kXRDC_MemMrc1_3 = 19U, /**< MRC1 Memory 3 */
518 kXRDC_MemMrc1_4 = 20U, /**< MRC1 Memory 4 */
519 kXRDC_MemMrc1_5 = 21U, /**< MRC1 Memory 5 */
520 kXRDC_MemMrc1_6 = 22U, /**< MRC1 Memory 6 */
521 kXRDC_MemMrc1_7 = 23U, /**< MRC1 Memory 7 */
522} xrdc_mem_t;
523
524typedef enum _xrdc_periph
525{
526 kXRDC_PeriphMscm = 1U, /**< Miscellaneous System Control Module (MSCM) */
527 kXRDC_PeriphMaxcore = 4U, /**< MAX CORE */
528 kXRDC_PeriphDma0 = 8U, /**< Direct Memory Access 0 (DMA0) controller */
529 kXRDC_PeriphDma0Tcd = 9U, /**< Direct Memory Access 0 (DMA0) controller transfer control descriptors */
530 kXRDC_PeriphFlexBus = 12U, /**< External Bus Interface(FlexBus) */
531 kXRDC_PeriphXrdcMgr = 20U, /**< Extended Resource Domain Controller (XRDC) MGR */
532 kXRDC_PeriphXrdcMdac = 21U, /**< Extended Resource Domain Controller (XRDC) MDAC */
533 kXRDC_PeriphXrdcPac = 22U, /**< Extended Resource Domain Controller (XRDC) PAC */
534 kXRDC_PeriphXrdcMrc = 23U, /**< Extended Resource Domain Controller (XRDC) MRC */
535 kXRDC_PeriphSema420 = 27U, /**< Semaphore Unit 0 (SEMA420) */
536 kXRDC_PeriphSmc0 = 32U, /**< System Mode Controller 0 (SMC0) */
537 kXRDC_PeriphDmamux0 = 33U, /**< Direct Memory Access Multiplexer 0 (DMAMUX0) */
538 kXRDC_PeriphEwm = 34U, /**< External Watchdog Monitor (EWM) */
539 kXRDC_PeriphFtfe = 35U, /**< Flash Memory Module (FTFE) */
540 kXRDC_PeriphLlwu0 = 36U, /**< Low Leakage Wake-up Unit 0 (LLWU0) */
541 kXRDC_PeriphMua = 37U, /**< Message Unit Side A (MU-A) */
542 kXRDC_PeriphSim = 38U, /**< System Integration Module (SIM) */
543 kXRDC_PeriphUsbVreg = 39U, /**< USB Voltage Regulator (USBVREG) */
544 kXRDC_PeriphSpm = 40U, /**< System Power Management (SPM) */
545 kXRDC_PeriphTrgmux0 = 41U, /**< Tirgger Multiplexer 0 (TRGMUX0) */
546 kXRDC_PeriphWdog0 = 42U, /**< Watchdog 0 (WDOG0) */
547 kXRDC_PeriphPcc0 = 43U, /**< Peripheral Clock Controller 0 (PCC0) */
548 kXRDC_PeriphScg = 44U, /**< System Clock Generator (SCG) */
549 kXRDC_PeriphSrf = 45U, /**< System Register File */
550 kXRDC_PeriphVbat = 46U, /**< VBAT Register File */
551 kXRDC_PeriphCrc0 = 47U, /**< Cyclic Redundancy Check 0 (CRC0) */
552 kXRDC_PeriphLpit0 = 48U, /**< Low-Power Periodic Interrupt Timer 0 (LPIT0) */
553 kXRDC_PeriphRtc = 49U, /**< Real Time Clock (RTC) */
554 kXRDC_PeriphLptmr0 = 50U, /**< Low-Power Timer 0 (LPTMR0) */
555 kXRDC_PeriphLptmr1 = 51U, /**< Low-Power Timer 1 (LPTMR1) */
556 kXRDC_PeriphTstmra = 52U, /**< Time Stamp Timer A (TSTMRA) */
557 kXRDC_PeriphTpm0 = 53U, /**< Timer / Pulse Width Modulator Module 0 (TPM0) - 6 channel */
558 kXRDC_PeriphTpm1 = 54U, /**< Timer / Pulse Width Modulator Module 1 (TPM1) - 2 channel */
559 kXRDC_PeriphTpm2 = 55U, /**< Timer / Pulse Width Modulator Module 2 (TPM2) - 6 channel */
560 kXRDC_PeriphEmvsim0 = 56U, /**< Euro Mastercard Visa Secure Identity Module 0 (EMVSIM0) */
561 kXRDC_PeriphFlexio0 = 57U, /**< Flexible Input / Output 0 (FlexIO0) */
562 kXRDC_PeriphLpi2c0 = 58U, /**< Low-Power Inter-Integrated Circuit 0 (LPI2C0) */
563 kXRDC_PeriphLpi2c1 = 59U, /**< Low-Power Inter-Integrated Circuit 1 (LPI2C1) */
564 kXRDC_PeriphLpi2c2 = 60U, /**< Low-Power Inter-Integrated Circuit 2 (LPI2C2) */
565 kXRDC_PeriphI2s0 = 61U, /**< Serial Audio Interface 0 (I2S0) */
566 kXRDC_PeriphSdhc0 = 62U, /**< Secure Digital Host Controller 0 (SDHC0) */
567 kXRDC_PeriphLpspi0 = 63U, /**< Low-Power Serial Peripheral Interface 0 (LPSPI0) */
568 kXRDC_PeriphLpspi1 = 64U, /**< Low-Power Serial Peripheral Interface 1 (LPSPI1) */
569 kXRDC_PeriphLpspi2 = 65U, /**< Low-Power Serial Peripheral Interface 2 (LPSPI2) */
570 kXRDC_PeriphLpuart0 = 66U, /**< Low-Power Universal Asynchronous Receive / Transmit 0 (LPUART0) */
571 kXRDC_PeriphLpuart1 = 67U, /**< Low-Power Universal Asynchronous Receive / Transmit 1 (LPUART1) */
572 kXRDC_PeriphLpuart2 = 68U, /**< Low-Power Universal Asynchronous Receive / Transmit 2 (LPUART2) */
573 kXRDC_PeriphUsb0 = 69U, /**< Universal Serial Bus 0 (USB0) - Full Speed, Device Only */
574 kXRDC_PeriphPortA = 70U, /**< PORTA Multiplex Control */
575 kXRDC_PeriphPortB = 71U, /**< PORTB Multiplex Control */
576 kXRDC_PeriphPortC = 72U, /**< PORTC Multiplex Control */
577 kXRDC_PeriphPortD = 73U, /**< PORTD Multiplex Control */
578 kXRDC_PeriphLpadc0 = 74U, /**< Low-Power Analog-to-Digital Converter 0 (LPADC0) */
579 kXRDC_PeriphLpcmp0 = 75U, /**< Low-Power Comparator 0 (LPCMP0) */
580 kXRDC_PeriphLpdac0 = 76U, /**< Low-Power Digital-to-Analog Converter 0 (LPDAC0) */
581 kXRDC_PeriphVref = 77U, /**< Voltage Reference (VREF) */
582 kXRDC_PeriphDma1 = 136U, /**< Direct Memory Access 1 (DMA1) controller */
583 kXRDC_PeriphDma1Tcd = 137U, /**< Direct Memory Access 1 (DMA1) controller trasfer control descriptors */
584 kXRDC_PeriphFgpio1 = 143U, /**< IO Port Alias */
585 kXRDC_PeriphSema421 = 155U, /**< Semaphore Unit 1 (SEMA421) */
586 kXRDC_PeriphSmc1 = 160U, /**< System Mode Controller 1(SMC1) */
587 kXRDC_PeriphDmamux1 = 161U, /**< Direct Memory Access Mutiplexer 1 (DMAMUX1) */
588 kXRDC_PeriphIntmux0 = 162U, /**< Interrupt Multiplexer 0 (INTMUX0) */
589 kXRDC_Periphllwu1 = 163U, /**< Low Leakage Wake-up Unit 1 (LLWU1) */
590 kXRDC_PeriphMub = 164U, /**< Messaging Unit - Side B (MU-B) */
591 kXRDC_PeriphTrgmux1 = 165U, /**< Trigger Multiplexer 1 (TRGMUX1) */
592 kXRDC_PeriphWdog1 = 166U, /**< Watchdog 1 (WDOG1) */
593 kXRDC_PeriphPcc1 = 167U, /**< Peripheral Clock Controller 1 (PCC1) */
594 kXRDC_PeriphCau3 = 168U, /**< Cryptographic Acceleration Unit (CAU3) */
595 kXRDC_PeriphTrng = 169U, /**< True Random Number Generator (TRNG) */
596 kXRDC_PeriphLpit1 = 170U, /**< Low-Power Periodic Interrupt Timer 1 (LPIT1) */
597 kXRDC_PeriphLptmr2 = 171U, /**< Low-Power Timer 2 (LPTMR2) */
598 kXRDC_PeriphTstmrb = 172U, /**< Time Stamp Timer B (TSTMRB) */
599 kXRDC_PeriphTpm3 = 173U, /**< Timer / Pulse Width Modulation Module 3 (TPM3) - 2 channel */
600 kXRDC_PeriphLpi2c3 = 174U, /**< Low-Power Inter-Integrated Circuit 3 (LPI2C3) */
601 kXRDC_PeriphLpspi3 = 181U, /**< Low-Power Serial Peripheral Interface 3 (LPSPI3) */
602 kXRDC_PeriphLpuart3 = 182U, /**< Low-Power Universal Asynchronous Receive / Transmit 3 (LPUART3) */
603 kXRDC_PeriphPortE = 183U, /**< PORTE Multiplex Control */
604 kXRDC_PeriphLpcmp1 = 184U, /**< Low-Power Comparator 1 (LPCMP1) */
605 kXRDC_PeriphUsbRam = 272U, /**< USB SRAM */
606 kXRDC_PeriphRgpio = 288U, /**< Rapid GPIO */
607} xrdc_periph_t;
608
609
610/*!
611 * @}
612 */ /* end of group Mapping_Information */
613
614
615/* ----------------------------------------------------------------------------
616 -- Device Peripheral Access Layer
617 ---------------------------------------------------------------------------- */
618
619/*!
620 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
621 * @{
622 */
623
624
625/*
626** Start of section using anonymous unions
627*/
628
629#if defined(__ARMCC_VERSION)
630 #if (__ARMCC_VERSION >= 6010050)
631 #pragma clang diagnostic push
632 #else
633 #pragma push
634 #pragma anon_unions
635 #endif
636#elif defined(__GNUC__)
637 /* anonymous unions are enabled by default */
638#elif defined(__IAR_SYSTEMS_ICC__)
639 #pragma language=extended
640#else
641 #error Not supported compiler type
642#endif
643
644/* ----------------------------------------------------------------------------
645 -- ADC Peripheral Access Layer
646 ---------------------------------------------------------------------------- */
647
648/*!
649 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
650 * @{
651 */
652
653/** ADC - Register Layout Typedef */
654typedef struct {
655 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
656 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
657 uint8_t RESERVED_0[8];
658 __IO uint32_t CTRL; /**< LPADC Control Register, offset: 0x10 */
659 __IO uint32_t STAT; /**< LPADC Status Register, offset: 0x14 */
660 __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */
661 __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */
662 __IO uint32_t CFG; /**< LPADC Configuration Register, offset: 0x20 */
663 __IO uint32_t PAUSE; /**< LPADC Pause Register, offset: 0x24 */
664 uint8_t RESERVED_1[8];
665 __IO uint32_t FCTRL; /**< LPADC FIFO Control Register, offset: 0x30 */
666 __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
667 uint8_t RESERVED_2[8];
668 __IO uint32_t OFSTRIM; /**< LPADC Offset Trim Register, offset: 0x40 */
669 uint8_t RESERVED_3[124];
670 __IO uint32_t TCTRL[4]; /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */
671 uint8_t RESERVED_4[48];
672 struct { /* offset: 0x100, array step: 0x8 */
673 __IO uint32_t CMDL; /**< LPADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
674 __IO uint32_t CMDH; /**< LPADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
675 } CMD[15];
676 uint8_t RESERVED_5[136];
677 __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
678 uint8_t RESERVED_6[240];
679 __I uint32_t RESFIFO; /**< LPADC Data Result FIFO Register, offset: 0x300 */
680} ADC_Type;
681
682/* ----------------------------------------------------------------------------
683 -- ADC Register Masks
684 ---------------------------------------------------------------------------- */
685
686/*!
687 * @addtogroup ADC_Register_Masks ADC Register Masks
688 * @{
689 */
690
691/*! @name VERID - Version ID Register */
692/*! @{ */
693#define ADC_VERID_RES_MASK (0x1U)
694#define ADC_VERID_RES_SHIFT (0U)
695/*! RES - Resolution
696 * 0b0..Up to 13-bit differential/12-bit single ended resolution supported.
697 * 0b1..Up to 16-bit differential/15-bit single ended resolution supported.
698 */
699#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
700#define ADC_VERID_DIFFEN_MASK (0x2U)
701#define ADC_VERID_DIFFEN_SHIFT (1U)
702/*! DIFFEN - Differential Supported
703 * 0b0..Differential operation not supported.
704 * 0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
705 */
706#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
707#define ADC_VERID_MVI_MASK (0x8U)
708#define ADC_VERID_MVI_SHIFT (3U)
709/*! MVI - Multi Vref Implemented
710 * 0b0..Single voltage reference high (VREFH) input supported.
711 * 0b1..Multiple voltage reference high (VREFH) inputs supported.
712 */
713#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
714#define ADC_VERID_CSW_MASK (0x70U)
715#define ADC_VERID_CSW_SHIFT (4U)
716/*! CSW - Channel Scale Width
717 * 0b000..Channel scaling not supported.
718 * 0b001..Channel scaling supported. 1-bit CSCALE control field.
719 * 0b110..Channel scaling supported. 6-bit CSCALE control field.
720 */
721#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
722#define ADC_VERID_VR1RNGI_MASK (0x100U)
723#define ADC_VERID_VR1RNGI_SHIFT (8U)
724/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
725 * 0b0..Range control not required. CFG[VREF1RNG] is not implemented.
726 * 0b1..Range control required. CFG[VREF1RNG] is implemented.
727 */
728#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
729#define ADC_VERID_IADCKI_MASK (0x200U)
730#define ADC_VERID_IADCKI_SHIFT (9U)
731/*! IADCKI - Internal LPADC Clock implemented
732 * 0b0..Internal clock source not implemented.
733 * 0b1..Internal clock source (and CFG[ADCKEN]) implemented.
734 */
735#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
736#define ADC_VERID_CALOFSI_MASK (0x400U)
737#define ADC_VERID_CALOFSI_SHIFT (10U)
738/*! CALOFSI - Calibration Offset Function Implemented
739 * 0b0..Offset calibration and offset trimming not implemented.
740 * 0b1..Offset calibration and offset trimming implemented.
741 */
742#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
743#define ADC_VERID_MINOR_MASK (0xFF0000U)
744#define ADC_VERID_MINOR_SHIFT (16U)
745#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
746#define ADC_VERID_MAJOR_MASK (0xFF000000U)
747#define ADC_VERID_MAJOR_SHIFT (24U)
748#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
749/*! @} */
750
751/*! @name PARAM - Parameter Register */
752/*! @{ */
753#define ADC_PARAM_TRIG_NUM_MASK (0xFFU)
754#define ADC_PARAM_TRIG_NUM_SHIFT (0U)
755#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
756#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U)
757#define ADC_PARAM_FIFOSIZE_SHIFT (8U)
758/*! FIFOSIZE - Result FIFO Depth
759 * 0b00000001..Result FIFO depth = 1 dataword.
760 * 0b00000100..Result FIFO depth = 4 datawords.
761 * 0b00001000..Result FIFO depth = 8 datawords.
762 * 0b00010000..Result FIFO depth = 16 datawords.
763 * 0b00100000..Result FIFO depth = 32 datawords.
764 * 0b01000000..Result FIFO depth = 64 datawords.
765 */
766#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
767#define ADC_PARAM_CV_NUM_MASK (0xFF0000U)
768#define ADC_PARAM_CV_NUM_SHIFT (16U)
769#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
770#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U)
771#define ADC_PARAM_CMD_NUM_SHIFT (24U)
772#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
773/*! @} */
774
775/*! @name CTRL - LPADC Control Register */
776/*! @{ */
777#define ADC_CTRL_ADCEN_MASK (0x1U)
778#define ADC_CTRL_ADCEN_SHIFT (0U)
779/*! ADCEN - LPADC Enable
780 * 0b0..LPADC is disabled.
781 * 0b1..LPADC is enabled.
782 */
783#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
784#define ADC_CTRL_RST_MASK (0x2U)
785#define ADC_CTRL_RST_SHIFT (1U)
786/*! RST - Software Reset
787 * 0b0..LPADC logic is not reset.
788 * 0b1..LPADC logic is reset.
789 */
790#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
791#define ADC_CTRL_DOZEN_MASK (0x4U)
792#define ADC_CTRL_DOZEN_SHIFT (2U)
793/*! DOZEN - Doze Enable
794 * 0b0..LPADC is enabled in Doze mode.
795 * 0b1..LPADC is disabled in Doze mode.
796 */
797#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
798#define ADC_CTRL_RSTFIFO_MASK (0x100U)
799#define ADC_CTRL_RSTFIFO_SHIFT (8U)
800/*! RSTFIFO - Reset FIFO
801 * 0b0..No effect.
802 * 0b1..FIFO is reset.
803 */
804#define ADC_CTRL_RSTFIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)
805/*! @} */
806
807/*! @name STAT - LPADC Status Register */
808/*! @{ */
809#define ADC_STAT_RDY_MASK (0x1U)
810#define ADC_STAT_RDY_SHIFT (0U)
811/*! RDY - Result FIFO Ready Flag
812 * 0b0..Result FIFO data level not above watermark level.
813 * 0b1..Result FIFO holding data above watermark level.
814 */
815#define ADC_STAT_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
816#define ADC_STAT_FOF_MASK (0x2U)
817#define ADC_STAT_FOF_SHIFT (1U)
818/*! FOF - Result FIFO Overflow Flag
819 * 0b0..No result FIFO overflow has occurred since the last time the flag was cleared.
820 * 0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared.
821 */
822#define ADC_STAT_FOF(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
823#define ADC_STAT_TRGACT_MASK (0x30000U)
824#define ADC_STAT_TRGACT_SHIFT (16U)
825/*! TRGACT - Trigger Active
826 * 0b00..Command (sequence) associated with Trigger 0 currently being executed.
827 * 0b01..Command (sequence) associated with Trigger 1 currently being executed.
828 * 0b10..Command (sequence) associated with Trigger 2 currently being executed.
829 * 0b11..Command (sequence) associated with Trigger 3 currently being executed.
830 */
831#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
832#define ADC_STAT_CMDACT_MASK (0xF000000U)
833#define ADC_STAT_CMDACT_SHIFT (24U)
834/*! CMDACT - Command Active
835 * 0b0000..No command is currently in progress.
836 * 0b0001..Command 1 currently being executed.
837 * 0b0010..Command 2 currently being executed.
838 * 0b0011-0b1111..Associated command number is currently being executed.
839 */
840#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
841/*! @} */
842
843/*! @name IE - Interrupt Enable Register */
844/*! @{ */
845#define ADC_IE_FWMIE_MASK (0x1U)
846#define ADC_IE_FWMIE_SHIFT (0U)
847/*! FWMIE - FIFO Watermark Interrupt Enable
848 * 0b0..FIFO watermark interrupts are not enabled.
849 * 0b1..FIFO watermark interrupts are enabled.
850 */
851#define ADC_IE_FWMIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
852#define ADC_IE_FOFIE_MASK (0x2U)
853#define ADC_IE_FOFIE_SHIFT (1U)
854/*! FOFIE - Result FIFO Overflow Interrupt Enable
855 * 0b0..FIFO overflow interrupts are not enabled.
856 * 0b1..FIFO overflow interrupts are enabled.
857 */
858#define ADC_IE_FOFIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)
859/*! @} */
860
861/*! @name DE - DMA Enable Register */
862/*! @{ */
863#define ADC_DE_FWMDE_MASK (0x1U)
864#define ADC_DE_FWMDE_SHIFT (0U)
865/*! FWMDE - FIFO Watermark DMA Enable
866 * 0b0..DMA request disabled.
867 * 0b1..DMA request enabled.
868 */
869#define ADC_DE_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)
870/*! @} */
871
872/*! @name CFG - LPADC Configuration Register */
873/*! @{ */
874#define ADC_CFG_TPRICTRL_MASK (0x1U)
875#define ADC_CFG_TPRICTRL_SHIFT (0U)
876/*! TPRICTRL - LPADC trigger priority control
877 * 0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and
878 * the new command specified by the trigger is started.
879 * 0b1..If a higher priority trigger is received during command processing, the current conversion is completed
880 * (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority
881 * trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true
882 * conversion.
883 */
884#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
885#define ADC_CFG_PWRSEL_MASK (0x30U)
886#define ADC_CFG_PWRSEL_SHIFT (4U)
887/*! PWRSEL - Power Configuration Select
888 * 0b00..Level 1 (Lowest power setting)
889 * 0b01..Level 2
890 * 0b10..Level 3
891 * 0b11..Level 4 (Highest power setting)
892 */
893#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
894#define ADC_CFG_REFSEL_MASK (0xC0U)
895#define ADC_CFG_REFSEL_SHIFT (6U)
896/*! REFSEL - Voltage Reference Selection
897 * 0b00..(Default) Option 1 setting.
898 * 0b01..Option 2 setting.
899 * 0b10..Option 3 setting.
900 * 0b11..Reserved
901 */
902#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
903#define ADC_CFG_CALOFS_MASK (0x8000U)
904#define ADC_CFG_CALOFS_SHIFT (15U)
905/*! CALOFS - Configure for offset calibration function
906 * 0b0..Calibration function disabled
907 * 0b1..Configure for offset calibration function
908 */
909#define ADC_CFG_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_CALOFS_SHIFT)) & ADC_CFG_CALOFS_MASK)
910#define ADC_CFG_PUDLY_MASK (0xFF0000U)
911#define ADC_CFG_PUDLY_SHIFT (16U)
912#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
913#define ADC_CFG_PWREN_MASK (0x10000000U)
914#define ADC_CFG_PWREN_SHIFT (28U)
915/*! PWREN - LPADC Analog Pre-Enable
916 * 0b0..LPADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
917 * 0b1..LPADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the
918 * cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any
919 * detected trigger does not begin ADC operation until the power up delay time has passed.
920 */
921#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
922#define ADC_CFG_VREF1RNG_MASK (0x20000000U)
923#define ADC_CFG_VREF1RNG_SHIFT (29U)
924/*! VREF1RNG - Enable support for low voltage reference on Option 1 Reference
925 * 0b0..Configuration required when Voltage Reference Option 1 input is in high voltage range
926 * 0b1..Configuration required when Voltage Reference Option 1 input is in low voltage range
927 */
928#define ADC_CFG_VREF1RNG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_VREF1RNG_SHIFT)) & ADC_CFG_VREF1RNG_MASK)
929#define ADC_CFG_ADCKEN_MASK (0x80000000U)
930#define ADC_CFG_ADCKEN_SHIFT (31U)
931/*! ADCKEN - LPADC asynchronous clock enable
932 * 0b0..LPADC internal clock is disabled
933 * 0b1..LPADC internal clock is enabled
934 */
935#define ADC_CFG_ADCKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADCKEN_SHIFT)) & ADC_CFG_ADCKEN_MASK)
936/*! @} */
937
938/*! @name PAUSE - LPADC Pause Register */
939/*! @{ */
940#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU)
941#define ADC_PAUSE_PAUSEDLY_SHIFT (0U)
942#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
943#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U)
944#define ADC_PAUSE_PAUSEEN_SHIFT (31U)
945/*! PAUSEEN - PAUSE Option Enable
946 * 0b0..Pause operation disabled
947 * 0b1..Pause operation enabled
948 */
949#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
950/*! @} */
951
952/*! @name FCTRL - LPADC FIFO Control Register */
953/*! @{ */
954#define ADC_FCTRL_FCOUNT_MASK (0x1FU)
955#define ADC_FCTRL_FCOUNT_SHIFT (0U)
956#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
957#define ADC_FCTRL_FWMARK_MASK (0xF0000U)
958#define ADC_FCTRL_FWMARK_SHIFT (16U)
959#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
960/*! @} */
961
962/*! @name SWTRIG - Software Trigger Register */
963/*! @{ */
964#define ADC_SWTRIG_SWT0_MASK (0x1U)
965#define ADC_SWTRIG_SWT0_SHIFT (0U)
966/*! SWT0 - Software trigger 0 event
967 * 0b0..No trigger 0 event generated.
968 * 0b1..Trigger 0 event generated.
969 */
970#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
971#define ADC_SWTRIG_SWT1_MASK (0x2U)
972#define ADC_SWTRIG_SWT1_SHIFT (1U)
973/*! SWT1 - Software trigger 1 event
974 * 0b0..No trigger 1 event generated.
975 * 0b1..Trigger 1 event generated.
976 */
977#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
978#define ADC_SWTRIG_SWT2_MASK (0x4U)
979#define ADC_SWTRIG_SWT2_SHIFT (2U)
980/*! SWT2 - Software trigger 2 event
981 * 0b0..No trigger 2 event generated.
982 * 0b1..Trigger 2 event generated.
983 */
984#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
985#define ADC_SWTRIG_SWT3_MASK (0x8U)
986#define ADC_SWTRIG_SWT3_SHIFT (3U)
987/*! SWT3 - Software trigger 3 event
988 * 0b0..No trigger 3 event generated.
989 * 0b1..Trigger 3 event generated.
990 */
991#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
992/*! @} */
993
994/*! @name OFSTRIM - LPADC Offset Trim Register */
995/*! @{ */
996#define ADC_OFSTRIM_OFSTRIM_MASK (0x3FU)
997#define ADC_OFSTRIM_OFSTRIM_SHIFT (0U)
998#define ADC_OFSTRIM_OFSTRIM(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_SHIFT)) & ADC_OFSTRIM_OFSTRIM_MASK)
999/*! @} */
1000
1001/*! @name TCTRL - Trigger Control Register */
1002/*! @{ */
1003#define ADC_TCTRL_HTEN_MASK (0x1U)
1004#define ADC_TCTRL_HTEN_SHIFT (0U)
1005/*! HTEN - Trigger enable
1006 * 0b0..Hardware trigger source disabled
1007 * 0b1..Hardware trigger source enabled
1008 */
1009#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
1010#define ADC_TCTRL_TPRI_MASK (0x300U)
1011#define ADC_TCTRL_TPRI_SHIFT (8U)
1012/*! TPRI - Trigger priority setting
1013 * 0b00..Set to highest priority, Level 1
1014 * 0b01-0b10..Set to corresponding priority level
1015 * 0b11..Set to lowest priority, Level 4
1016 */
1017#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
1018#define ADC_TCTRL_TDLY_MASK (0xF0000U)
1019#define ADC_TCTRL_TDLY_SHIFT (16U)
1020#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
1021#define ADC_TCTRL_TCMD_MASK (0xF000000U)
1022#define ADC_TCTRL_TCMD_SHIFT (24U)
1023/*! TCMD - Trigger command select
1024 * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
1025 * 0b0001..CMD1 is executed
1026 * 0b0010-0b1110..Corresponding CMD is executed
1027 * 0b1111..CMD15 is executed
1028 */
1029#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
1030/*! @} */
1031
1032/* The count of ADC_TCTRL */
1033#define ADC_TCTRL_COUNT (4U)
1034
1035/*! @name CMDL - LPADC Command Low Buffer Register */
1036/*! @{ */
1037#define ADC_CMDL_ADCH_MASK (0x1FU)
1038#define ADC_CMDL_ADCH_SHIFT (0U)
1039/*! ADCH - Input channel select
1040 * 0b00000..Select CH0A or CH0B
1041 * 0b00001..Select CH1A or CH1B
1042 * 0b00010..Select CH2A or CH2B
1043 * 0b00011..Select CH3A or CH3B
1044 * 0b00100-0b11101..Select corresponding channel CHnA or CHnB
1045 * 0b11110..Select CH30A or CH30B
1046 * 0b11111..Select CH31A or CH31B
1047 */
1048#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
1049#define ADC_CMDL_ABSEL_MASK (0x20U)
1050#define ADC_CMDL_ABSEL_SHIFT (5U)
1051/*! ABSEL - A-side vs. B-side Select
1052 * 0b0..The associated A-side channel is converted.
1053 * 0b1..The associated B-side channel is converted.
1054 */
1055#define ADC_CMDL_ABSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
1056/*! @} */
1057
1058/* The count of ADC_CMDL */
1059#define ADC_CMDL_COUNT (15U)
1060
1061/*! @name CMDH - LPADC Command High Buffer Register */
1062/*! @{ */
1063#define ADC_CMDH_CMPEN_MASK (0x3U)
1064#define ADC_CMDH_CMPEN_SHIFT (0U)
1065/*! CMPEN - Compare Function Enable
1066 * 0b00..Compare disabled.
1067 * 0b01..Reserved
1068 * 0b10..Compare enabled. Store on true.
1069 * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
1070 */
1071#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
1072#define ADC_CMDH_LWI_MASK (0x80U)
1073#define ADC_CMDH_LWI_SHIFT (7U)
1074/*! LWI - Loop with Increment
1075 * 0b0..Auto channel increment disabled
1076 * 0b1..Auto channel increment enabled
1077 */
1078#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
1079#define ADC_CMDH_STS_MASK (0x700U)
1080#define ADC_CMDH_STS_SHIFT (8U)
1081/*! STS - Sample Time Select
1082 * 0b000..Minimum sample time of 3 ADCK cycles.
1083 * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
1084 * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
1085 * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
1086 * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
1087 * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
1088 * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
1089 * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
1090 */
1091#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
1092#define ADC_CMDH_AVGS_MASK (0x7000U)
1093#define ADC_CMDH_AVGS_SHIFT (12U)
1094/*! AVGS - Hardware Average Select
1095 * 0b000..Single conversion.
1096 * 0b001..2 conversions averaged.
1097 * 0b010..4 conversions averaged.
1098 * 0b011..8 conversions averaged.
1099 * 0b100..16 conversions averaged.
1100 * 0b101..32 conversions averaged.
1101 * 0b110..64 conversions averaged.
1102 * 0b111..128 conversions averaged.
1103 */
1104#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
1105#define ADC_CMDH_LOOP_MASK (0xF0000U)
1106#define ADC_CMDH_LOOP_SHIFT (16U)
1107/*! LOOP - Loop Count Select
1108 * 0b0000..Looping not enabled. Command executes 1 time.
1109 * 0b0001..Loop 1 time. Command executes 2 times.
1110 * 0b0010..Loop 2 times. Command executes 3 times.
1111 * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
1112 * 0b1111..Loop 15 times. Command executes 16 times.
1113 */
1114#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
1115#define ADC_CMDH_NEXT_MASK (0xF000000U)
1116#define ADC_CMDH_NEXT_SHIFT (24U)
1117/*! NEXT - Next Command Select
1118 * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
1119 * trigger pending, begin command associated with lower priority trigger.
1120 * 0b0001..Select CMD1 command buffer register as next command.
1121 * 0b0010-0b1110..Select corresponding CMD command buffer register as next command
1122 * 0b1111..Select CMD15 command buffer register as next command.
1123 */
1124#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
1125/*! @} */
1126
1127/* The count of ADC_CMDH */
1128#define ADC_CMDH_COUNT (15U)
1129
1130/*! @name CV - Compare Value Register */
1131/*! @{ */
1132#define ADC_CV_CVL_MASK (0xFFFFU)
1133#define ADC_CV_CVL_SHIFT (0U)
1134#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
1135#define ADC_CV_CVH_MASK (0xFFFF0000U)
1136#define ADC_CV_CVH_SHIFT (16U)
1137#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
1138/*! @} */
1139
1140/* The count of ADC_CV */
1141#define ADC_CV_COUNT (4U)
1142
1143/*! @name RESFIFO - LPADC Data Result FIFO Register */
1144/*! @{ */
1145#define ADC_RESFIFO_D_MASK (0xFFFFU)
1146#define ADC_RESFIFO_D_SHIFT (0U)
1147#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
1148#define ADC_RESFIFO_TSRC_MASK (0x30000U)
1149#define ADC_RESFIFO_TSRC_SHIFT (16U)
1150/*! TSRC - Trigger Source
1151 * 0b00..Trigger source 0 initiated this conversion.
1152 * 0b01..Trigger source 1 initiated this conversion.
1153 * 0b10..Trigger source 2 initiated this conversion.
1154 * 0b11..Trigger source 3 initiated this conversion.
1155 */
1156#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
1157#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U)
1158#define ADC_RESFIFO_LOOPCNT_SHIFT (20U)
1159/*! LOOPCNT - Loop count value
1160 * 0b0000..Result is from initial conversion in command.
1161 * 0b0001..Result is from second conversion in command.
1162 * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
1163 * 0b1111..Result is from 16th conversion in command.
1164 */
1165#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
1166#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U)
1167#define ADC_RESFIFO_CMDSRC_SHIFT (24U)
1168/*! CMDSRC - Command Buffer Source
1169 * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
1170 * prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
1171 * 0b0001..CMD1 buffer used as control settings for this conversion.
1172 * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
1173 * 0b1111..CMD15 buffer used as control settings for this conversion.
1174 */
1175#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
1176#define ADC_RESFIFO_VALID_MASK (0x80000000U)
1177#define ADC_RESFIFO_VALID_SHIFT (31U)
1178/*! VALID - FIFO entry is valid
1179 * 0b0..FIFO is empty. Discard any read from RESFIFO.
1180 * 0b1..FIFO record read from RESFIFO is valid.
1181 */
1182#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
1183/*! @} */
1184
1185
1186/*!
1187 * @}
1188 */ /* end of group ADC_Register_Masks */
1189
1190
1191/* ADC - Peripheral instance base addresses */
1192/** Peripheral LPADC0 base address */
1193#define LPADC0_BASE (0x4004A000u)
1194/** Peripheral LPADC0 base pointer */
1195#define LPADC0 ((ADC_Type *)LPADC0_BASE)
1196/** Array initializer of ADC peripheral base addresses */
1197#define ADC_BASE_ADDRS { LPADC0_BASE }
1198/** Array initializer of ADC peripheral base pointers */
1199#define ADC_BASE_PTRS { LPADC0 }
1200/** Interrupt vectors for the ADC peripheral type */
1201#define ADC_IRQS { LPADC0_IRQn }
1202
1203/*!
1204 * @}
1205 */ /* end of group ADC_Peripheral_Access_Layer */
1206
1207
1208/* ----------------------------------------------------------------------------
1209 -- AXBS Peripheral Access Layer
1210 ---------------------------------------------------------------------------- */
1211
1212/*!
1213 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
1214 * @{
1215 */
1216
1217/** AXBS - Register Layout Typedef */
1218typedef struct {
1219 struct { /* offset: 0x0, array step: 0x100 */
1220 __IO uint32_t PRS; /**< Priority Slave Registers, array offset: 0x0, array step: 0x100 */
1221 uint8_t RESERVED_0[12];
1222 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
1223 uint8_t RESERVED_1[236];
1224 } SLAVE[5];
1225 uint8_t RESERVED_0[768];
1226 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
1227 uint8_t RESERVED_1[252];
1228 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
1229 uint8_t RESERVED_2[252];
1230 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
1231 uint8_t RESERVED_3[252];
1232 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
1233 uint8_t RESERVED_4[252];
1234 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
1235 uint8_t RESERVED_5[252];
1236 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
1237} AXBS_Type;
1238
1239/* ----------------------------------------------------------------------------
1240 -- AXBS Register Masks
1241 ---------------------------------------------------------------------------- */
1242
1243/*!
1244 * @addtogroup AXBS_Register_Masks AXBS Register Masks
1245 * @{
1246 */
1247
1248/*! @name PRS - Priority Slave Registers */
1249/*! @{ */
1250#define AXBS_PRS_M0_MASK (0x7U)
1251#define AXBS_PRS_M0_SHIFT (0U)
1252/*! M0 - Master 0 Priority. Sets the arbitration priority for this port on the associated slave port.
1253 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
1254 * 0b001..This master has level 2 priority when accessing the slave port.
1255 * 0b010..This master has level 3 priority when accessing the slave port.
1256 * 0b011..This master has level 4 priority when accessing the slave port.
1257 * 0b100..This master has level 5 priority when accessing the slave port.
1258 * 0b101..This master has level 6 priority when accessing the slave port.
1259 * 0b110..This master has level 7 priority when accessing the slave port.
1260 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
1261 */
1262#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
1263#define AXBS_PRS_M1_MASK (0x70U)
1264#define AXBS_PRS_M1_SHIFT (4U)
1265/*! M1 - Master 1 Priority. Sets the arbitration priority for this port on the associated slave port.
1266 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
1267 * 0b001..This master has level 2 priority when accessing the slave port.
1268 * 0b010..This master has level 3 priority when accessing the slave port.
1269 * 0b011..This master has level 4 priority when accessing the slave port.
1270 * 0b100..This master has level 5 priority when accessing the slave port.
1271 * 0b101..This master has level 6 priority when accessing the slave port.
1272 * 0b110..This master has level 7 priority when accessing the slave port.
1273 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
1274 */
1275#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
1276#define AXBS_PRS_M2_MASK (0x700U)
1277#define AXBS_PRS_M2_SHIFT (8U)
1278/*! M2 - Master 2 Priority. Sets the arbitration priority for this port on the associated slave port.
1279 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
1280 * 0b001..This master has level 2 priority when accessing the slave port.
1281 * 0b010..This master has level 3 priority when accessing the slave port.
1282 * 0b011..This master has level 4 priority when accessing the slave port.
1283 * 0b100..This master has level 5 priority when accessing the slave port.
1284 * 0b101..This master has level 6 priority when accessing the slave port.
1285 * 0b110..This master has level 7 priority when accessing the slave port.
1286 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
1287 */
1288#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
1289#define AXBS_PRS_M3_MASK (0x7000U)
1290#define AXBS_PRS_M3_SHIFT (12U)
1291/*! M3 - Master 3 Priority. Sets the arbitration priority for this port on the associated slave port.
1292 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
1293 * 0b001..This master has level 2 priority when accessing the slave port.
1294 * 0b010..This master has level 3 priority when accessing the slave port.
1295 * 0b011..This master has level 4 priority when accessing the slave port.
1296 * 0b100..This master has level 5 priority when accessing the slave port.
1297 * 0b101..This master has level 6 priority when accessing the slave port.
1298 * 0b110..This master has level 7 priority when accessing the slave port.
1299 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
1300 */
1301#define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
1302#define AXBS_PRS_M4_MASK (0x70000U)
1303#define AXBS_PRS_M4_SHIFT (16U)
1304/*! M4 - Master 4 Priority. Sets the arbitration priority for this port on the associated slave port.
1305 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
1306 * 0b001..This master has level 2 priority when accessing the slave port.
1307 * 0b010..This master has level 3 priority when accessing the slave port.
1308 * 0b011..This master has level 4 priority when accessing the slave port.
1309 * 0b100..This master has level 5 priority when accessing the slave port.
1310 * 0b101..This master has level 6 priority when accessing the slave port.
1311 * 0b110..This master has level 7 priority when accessing the slave port.
1312 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
1313 */
1314#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
1315#define AXBS_PRS_M5_MASK (0x700000U)
1316#define AXBS_PRS_M5_SHIFT (20U)
1317/*! M5 - Master 5 Priority. Sets the arbitration priority for this port on the associated slave port.
1318 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
1319 * 0b001..This master has level 2 priority when accessing the slave port.
1320 * 0b010..This master has level 3 priority when accessing the slave port.
1321 * 0b011..This master has level 4 priority when accessing the slave port.
1322 * 0b100..This master has level 5 priority when accessing the slave port.
1323 * 0b101..This master has level 6 priority when accessing the slave port.
1324 * 0b110..This master has level 7 priority when accessing the slave port.
1325 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
1326 */
1327#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
1328/*! @} */
1329
1330/* The count of AXBS_PRS */
1331#define AXBS_PRS_COUNT (5U)
1332
1333/*! @name CRS - Control Register */
1334/*! @{ */
1335#define AXBS_CRS_PARK_MASK (0x7U)
1336#define AXBS_CRS_PARK_SHIFT (0U)
1337/*! PARK - Park
1338 * 0b000..Park on master port M0
1339 * 0b001..Park on master port M1
1340 * 0b010..Park on master port M2
1341 * 0b011..Park on master port M3
1342 * 0b100..Park on master port M4
1343 * 0b101..Park on master port M5
1344 * 0b110..Park on master port M6
1345 * 0b111..Park on master port M7
1346 */
1347#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
1348#define AXBS_CRS_PCTL_MASK (0x30U)
1349#define AXBS_CRS_PCTL_SHIFT (4U)
1350/*! PCTL - Parking Control
1351 * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field
1352 * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port
1353 * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state
1354 * 0b11..Reserved
1355 */
1356#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
1357#define AXBS_CRS_ARB_MASK (0x300U)
1358#define AXBS_CRS_ARB_SHIFT (8U)
1359/*! ARB - Arbitration Mode
1360 * 0b00..Fixed priority
1361 * 0b01..Round-robin, or rotating, priority
1362 * 0b10..Reserved
1363 * 0b11..Reserved
1364 */
1365#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
1366#define AXBS_CRS_HLP_MASK (0x40000000U)
1367#define AXBS_CRS_HLP_SHIFT (30U)
1368/*! HLP - Halt Low Priority
1369 * 0b0..The low power mode request has the highest priority for arbitration on this slave port
1370 * 0b1..The low power mode request has the lowest initial priority for arbitration on this slave port
1371 */
1372#define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
1373#define AXBS_CRS_RO_MASK (0x80000000U)
1374#define AXBS_CRS_RO_SHIFT (31U)
1375/*! RO - Read Only
1376 * 0b0..The slave port's registers are writeable
1377 * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the
1378 * registers and result in a bus error response.
1379 */
1380#define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
1381/*! @} */
1382
1383/* The count of AXBS_CRS */
1384#define AXBS_CRS_COUNT (5U)
1385
1386/*! @name MGPCR0 - Master General Purpose Control Register */
1387/*! @{ */
1388#define AXBS_MGPCR0_AULB_MASK (0x7U)
1389#define AXBS_MGPCR0_AULB_SHIFT (0U)
1390/*! AULB - Arbitrates On Undefined Length Bursts
1391 * 0b000..No arbitration is allowed during an undefined length burst
1392 * 0b001..Arbitration is allowed at any time during an undefined length burst
1393 * 0b010..Arbitration is allowed after four beats of an undefined length burst
1394 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
1395 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
1396 * 0b101..Reserved
1397 * 0b110..Reserved
1398 * 0b111..Reserved
1399 */
1400#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
1401/*! @} */
1402
1403/*! @name MGPCR1 - Master General Purpose Control Register */
1404/*! @{ */
1405#define AXBS_MGPCR1_AULB_MASK (0x7U)
1406#define AXBS_MGPCR1_AULB_SHIFT (0U)
1407/*! AULB - Arbitrates On Undefined Length Bursts
1408 * 0b000..No arbitration is allowed during an undefined length burst
1409 * 0b001..Arbitration is allowed at any time during an undefined length burst
1410 * 0b010..Arbitration is allowed after four beats of an undefined length burst
1411 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
1412 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
1413 * 0b101..Reserved
1414 * 0b110..Reserved
1415 * 0b111..Reserved
1416 */
1417#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
1418/*! @} */
1419
1420/*! @name MGPCR2 - Master General Purpose Control Register */
1421/*! @{ */
1422#define AXBS_MGPCR2_AULB_MASK (0x7U)
1423#define AXBS_MGPCR2_AULB_SHIFT (0U)
1424/*! AULB - Arbitrates On Undefined Length Bursts
1425 * 0b000..No arbitration is allowed during an undefined length burst
1426 * 0b001..Arbitration is allowed at any time during an undefined length burst
1427 * 0b010..Arbitration is allowed after four beats of an undefined length burst
1428 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
1429 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
1430 * 0b101..Reserved
1431 * 0b110..Reserved
1432 * 0b111..Reserved
1433 */
1434#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
1435/*! @} */
1436
1437/*! @name MGPCR3 - Master General Purpose Control Register */
1438/*! @{ */
1439#define AXBS_MGPCR3_AULB_MASK (0x7U)
1440#define AXBS_MGPCR3_AULB_SHIFT (0U)
1441/*! AULB - Arbitrates On Undefined Length Bursts
1442 * 0b000..No arbitration is allowed during an undefined length burst
1443 * 0b001..Arbitration is allowed at any time during an undefined length burst
1444 * 0b010..Arbitration is allowed after four beats of an undefined length burst
1445 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
1446 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
1447 * 0b101..Reserved
1448 * 0b110..Reserved
1449 * 0b111..Reserved
1450 */
1451#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
1452/*! @} */
1453
1454/*! @name MGPCR4 - Master General Purpose Control Register */
1455/*! @{ */
1456#define AXBS_MGPCR4_AULB_MASK (0x7U)
1457#define AXBS_MGPCR4_AULB_SHIFT (0U)
1458/*! AULB - Arbitrates On Undefined Length Bursts
1459 * 0b000..No arbitration is allowed during an undefined length burst
1460 * 0b001..Arbitration is allowed at any time during an undefined length burst
1461 * 0b010..Arbitration is allowed after four beats of an undefined length burst
1462 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
1463 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
1464 * 0b101..Reserved
1465 * 0b110..Reserved
1466 * 0b111..Reserved
1467 */
1468#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
1469/*! @} */
1470
1471/*! @name MGPCR5 - Master General Purpose Control Register */
1472/*! @{ */
1473#define AXBS_MGPCR5_AULB_MASK (0x7U)
1474#define AXBS_MGPCR5_AULB_SHIFT (0U)
1475/*! AULB - Arbitrates On Undefined Length Bursts
1476 * 0b000..No arbitration is allowed during an undefined length burst
1477 * 0b001..Arbitration is allowed at any time during an undefined length burst
1478 * 0b010..Arbitration is allowed after four beats of an undefined length burst
1479 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
1480 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
1481 * 0b101..Reserved
1482 * 0b110..Reserved
1483 * 0b111..Reserved
1484 */
1485#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
1486/*! @} */
1487
1488
1489/*!
1490 * @}
1491 */ /* end of group AXBS_Register_Masks */
1492
1493
1494/* AXBS - Peripheral instance base addresses */
1495/** Peripheral AXBS0 base address */
1496#define AXBS0_BASE (0x40004000u)
1497/** Peripheral AXBS0 base pointer */
1498#define AXBS0 ((AXBS_Type *)AXBS0_BASE)
1499/** Array initializer of AXBS peripheral base addresses */
1500#define AXBS_BASE_ADDRS { AXBS0_BASE }
1501/** Array initializer of AXBS peripheral base pointers */
1502#define AXBS_BASE_PTRS { AXBS0 }
1503
1504/*!
1505 * @}
1506 */ /* end of group AXBS_Peripheral_Access_Layer */
1507
1508
1509/* ----------------------------------------------------------------------------
1510 -- CAU3 Peripheral Access Layer
1511 ---------------------------------------------------------------------------- */
1512
1513/*!
1514 * @addtogroup CAU3_Peripheral_Access_Layer CAU3 Peripheral Access Layer
1515 * @{
1516 */
1517
1518/** CAU3 - Register Layout Typedef */
1519typedef struct {
1520 __I uint32_t PCT; /**< Processor Core Type, offset: 0x0 */
1521 __I uint32_t MCFG; /**< Memory Configuration, offset: 0x4 */
1522 uint8_t RESERVED_0[8];
1523 __IO uint32_t CR; /**< Control Register, offset: 0x10 */
1524 __IO uint32_t SR; /**< Status Register, offset: 0x14 */
1525 uint8_t RESERVED_1[8];
1526 __IO uint32_t DBGCSR; /**< Debug Control/Status Register, offset: 0x20 */
1527 __IO uint32_t DBGPBR; /**< Debug PC Breakpoint Register, offset: 0x24 */
1528 uint8_t RESERVED_2[8];
1529 __IO uint32_t DBGMCMD; /**< Debug Memory Command Register, offset: 0x30 */
1530 __IO uint32_t DBGMADR; /**< Debug Memory Address Register, offset: 0x34 */
1531 __IO uint32_t DBGMDR; /**< Debug Memory Data Register, offset: 0x38 */
1532 uint8_t RESERVED_3[180];
1533 __IO uint32_t SEMA4; /**< Semaphore Register, offset: 0xF0 */
1534 __I uint32_t SMOWNR; /**< Semaphore Ownership Register, offset: 0xF4 */
1535 uint8_t RESERVED_4[4];
1536 __IO uint32_t ARR; /**< Address Remap Register, offset: 0xFC */
1537 uint8_t RESERVED_5[128];
1538 __IO uint32_t CC_R[30]; /**< CryptoCore General Purpose Registers, array offset: 0x180, array step: 0x4 */
1539 __IO uint32_t CC_R30; /**< General Purpose R30, offset: 0x1F8 */
1540 __IO uint32_t CC_R31; /**< General Purpose R31, offset: 0x1FC */
1541 __IO uint32_t CC_PC; /**< Program Counter, offset: 0x200 */
1542 __O uint32_t CC_CMD; /**< Start Command Register, offset: 0x204 */
1543 __I uint32_t CC_CF; /**< Condition Flag, offset: 0x208 */
1544 uint8_t RESERVED_6[500];
1545 __IO uint32_t MDPK; /**< Mode Register (PublicKey), offset: 0x400 */
1546 uint8_t RESERVED_7[44];
1547 __O uint32_t COM; /**< Command Register, offset: 0x430 */
1548 __IO uint32_t CTL; /**< Control Register, offset: 0x434 */
1549 uint8_t RESERVED_8[8];
1550 __O uint32_t CW; /**< Clear Written Register, offset: 0x440 */
1551 uint8_t RESERVED_9[4];
1552 __IO uint32_t STA; /**< Status Register, offset: 0x448 */
1553 __I uint32_t ESTA; /**< Error Status Register, offset: 0x44C */
1554 uint8_t RESERVED_10[48];
1555 __IO uint32_t PKASZ; /**< PKHA A Size Register, offset: 0x480 */
1556 uint8_t RESERVED_11[4];
1557 __IO uint32_t PKBSZ; /**< PKHA B Size Register, offset: 0x488 */
1558 uint8_t RESERVED_12[4];
1559 __IO uint32_t PKNSZ; /**< PKHA N Size Register, offset: 0x490 */
1560 uint8_t RESERVED_13[4];
1561 __IO uint32_t PKESZ; /**< PKHA E Size Register, offset: 0x498 */
1562 uint8_t RESERVED_14[84];
1563 __I uint32_t PKHA_VID1; /**< PKHA Revision ID 1, offset: 0x4F0 */
1564 __I uint32_t PKHA_VID2; /**< PKHA Revision ID 2, offset: 0x4F4 */
1565 __I uint32_t CHA_VID; /**< CHA Revision ID, offset: 0x4F8 */
1566 uint8_t RESERVED_15[260];
1567 __IO uint32_t PKHA_CCR; /**< PKHA Clock Control Register, offset: 0x600 */
1568 __I uint32_t GSR; /**< Global Status Register, offset: 0x604 */
1569 __IO uint32_t CKLFSR; /**< Clock Linear Feedback Shift Register, offset: 0x608 */
1570 uint8_t RESERVED_16[500];
1571 __IO uint32_t PKA0[32]; /**< PKHA A0 Register, array offset: 0x800, array step: 0x4 */
1572 __IO uint32_t PKA1[32]; /**< PKHA A1 Register, array offset: 0x880, array step: 0x4 */
1573 __IO uint32_t PKA2[32]; /**< PKHA A2 Register, array offset: 0x900, array step: 0x4 */
1574 __IO uint32_t PKA3[32]; /**< PKHA A3 Register, array offset: 0x980, array step: 0x4 */
1575 __IO uint32_t PKB0[32]; /**< PKHA B0 Register, array offset: 0xA00, array step: 0x4 */
1576 __IO uint32_t PKB1[32]; /**< PKHA B1 Register, array offset: 0xA80, array step: 0x4 */
1577 __IO uint32_t PKB2[32]; /**< PKHA B2 Register, array offset: 0xB00, array step: 0x4 */
1578 __IO uint32_t PKB3[32]; /**< PKHA B3 Register, array offset: 0xB80, array step: 0x4 */
1579 __IO uint32_t PKN0[32]; /**< PKHA N0 Register, array offset: 0xC00, array step: 0x4 */
1580 __IO uint32_t PKN1[32]; /**< PKHA N1 Register, array offset: 0xC80, array step: 0x4 */
1581 __IO uint32_t PKN2[32]; /**< PKHA N2 Register, array offset: 0xD00, array step: 0x4 */
1582 __IO uint32_t PKN3[32]; /**< PKHA N3 Register, array offset: 0xD80, array step: 0x4 */
1583 __O uint32_t PKE[128]; /**< PKHA E Register, array offset: 0xE00, array step: 0x4 */
1584} CAU3_Type;
1585
1586/* ----------------------------------------------------------------------------
1587 -- CAU3 Register Masks
1588 ---------------------------------------------------------------------------- */
1589
1590/*!
1591 * @addtogroup CAU3_Register_Masks CAU3 Register Masks
1592 * @{
1593 */
1594
1595/*! @name PCT - Processor Core Type */
1596/*! @{ */
1597#define CAU3_PCT_Y_MASK (0xFU)
1598#define CAU3_PCT_Y_SHIFT (0U)
1599/*! Y - Minor version number
1600 * 0b0000..Minor version number
1601 */
1602#define CAU3_PCT_Y(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PCT_Y_SHIFT)) & CAU3_PCT_Y_MASK)
1603#define CAU3_PCT_X_MASK (0xF0U)
1604#define CAU3_PCT_X_SHIFT (4U)
1605/*! X - Major version number
1606 * 0b0000..Major version number
1607 */
1608#define CAU3_PCT_X(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PCT_X_SHIFT)) & CAU3_PCT_X_MASK)
1609#define CAU3_PCT_ID_MASK (0xFFFFFF00U)
1610#define CAU3_PCT_ID_SHIFT (8U)
1611/*! ID - Module ID number
1612 * 0b010010110100000101100000..ID number for basic configuration
1613 * 0b010010110100000101100001..ID number for PKHA configuration
1614 */
1615#define CAU3_PCT_ID(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PCT_ID_SHIFT)) & CAU3_PCT_ID_MASK)
1616/*! @} */
1617
1618/*! @name MCFG - Memory Configuration */
1619/*! @{ */
1620#define CAU3_MCFG_DRAM_SZ_MASK (0xF00U)
1621#define CAU3_MCFG_DRAM_SZ_SHIFT (8U)
1622/*! DRAM_SZ - Data RAM Size
1623 * 0b0000..No memory module
1624 * 0b0100..2K bytes
1625 * 0b0101..3K bytes
1626 * 0b0110..4K bytes
1627 * 0b0111..6K bytes
1628 * 0b1000..8K bytes
1629 * 0b1001..12K bytes
1630 * 0b1010..16K bytes
1631 * 0b1011..24K bytes
1632 * 0b1100..32K bytes
1633 * 0b1101..48K bytes
1634 * 0b1110..64K bytes
1635 * 0b1111..96K bytes
1636 */
1637#define CAU3_MCFG_DRAM_SZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_MCFG_DRAM_SZ_SHIFT)) & CAU3_MCFG_DRAM_SZ_MASK)
1638#define CAU3_MCFG_IROM_SZ_MASK (0xF0000U)
1639#define CAU3_MCFG_IROM_SZ_SHIFT (16U)
1640/*! IROM_SZ - Instruction ROM Size
1641 * 0b0000..No memory module
1642 * 0b0100..2K bytes
1643 * 0b0101..3K bytes
1644 * 0b0110..4K bytes
1645 * 0b0111..6K bytes
1646 * 0b1000..8K bytes
1647 * 0b1001..12K bytes
1648 * 0b1010..16K bytes
1649 * 0b1011..24K bytes
1650 * 0b1100..32K bytes
1651 * 0b1101..48K bytes
1652 * 0b1110..64K bytes
1653 * 0b1111..96K bytes
1654 */
1655#define CAU3_MCFG_IROM_SZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_MCFG_IROM_SZ_SHIFT)) & CAU3_MCFG_IROM_SZ_MASK)
1656#define CAU3_MCFG_IRAM_SZ_MASK (0xF000000U)
1657#define CAU3_MCFG_IRAM_SZ_SHIFT (24U)
1658/*! IRAM_SZ - Instruction RAM Size
1659 * 0b0000..No memory module
1660 * 0b0100..2K bytes
1661 * 0b0101..3K bytes
1662 * 0b0110..4K bytes
1663 * 0b0111..6K bytes
1664 * 0b1000..8K bytes
1665 * 0b1001..12K bytes
1666 * 0b1010..16K bytes
1667 * 0b1011..24K bytes
1668 * 0b1100..32K bytes
1669 * 0b1101..48K bytes
1670 * 0b1110..64K bytes
1671 * 0b1111..96K bytes
1672 */
1673#define CAU3_MCFG_IRAM_SZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_MCFG_IRAM_SZ_SHIFT)) & CAU3_MCFG_IRAM_SZ_MASK)
1674/*! @} */
1675
1676/*! @name CR - Control Register */
1677/*! @{ */
1678#define CAU3_CR_TCSEIE_MASK (0x1U)
1679#define CAU3_CR_TCSEIE_SHIFT (0U)
1680/*! TCSEIE - Task completion with software error interrupt enable
1681 * 0b0..Disables task completion with software error to generate an interrupt request
1682 * 0b1..Enables task completion with software error to generate an interrupt request
1683 */
1684#define CAU3_CR_TCSEIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_TCSEIE_SHIFT)) & CAU3_CR_TCSEIE_MASK)
1685#define CAU3_CR_ILLIE_MASK (0x2U)
1686#define CAU3_CR_ILLIE_SHIFT (1U)
1687/*! ILLIE - Illegal Instruction Interrupt Enable
1688 * 0b0..Illegal instruction interrupt requests are disabled
1689 * 0b1..illegal Instruction interrupt requests are enabled
1690 */
1691#define CAU3_CR_ILLIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_ILLIE_SHIFT)) & CAU3_CR_ILLIE_MASK)
1692#define CAU3_CR_ASREIE_MASK (0x8U)
1693#define CAU3_CR_ASREIE_SHIFT (3U)
1694/*! ASREIE - AHB Slave Response Error Interrupt Enable
1695 * 0b0..AHB slave response error interruption is not enabled
1696 * 0b1..AHB slave response error interruption is enabled
1697 */
1698#define CAU3_CR_ASREIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_ASREIE_SHIFT)) & CAU3_CR_ASREIE_MASK)
1699#define CAU3_CR_IIADIE_MASK (0x10U)
1700#define CAU3_CR_IIADIE_SHIFT (4U)
1701/*! IIADIE - IMEM Illegal Address Interrupt Enable
1702 * 0b0..IMEM illegal address interruption is not enabled
1703 * 0b1..IMEM illegal address interruption is enabled
1704 */
1705#define CAU3_CR_IIADIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_IIADIE_SHIFT)) & CAU3_CR_IIADIE_MASK)
1706#define CAU3_CR_DIADIE_MASK (0x20U)
1707#define CAU3_CR_DIADIE_SHIFT (5U)
1708/*! DIADIE - DMEM Illegal Address Interrupt Enable
1709 * 0b0..DMEM illegal address interruption is not enabled
1710 * 0b1..DMEM illegal address interruption is enabled
1711 */
1712#define CAU3_CR_DIADIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DIADIE_SHIFT)) & CAU3_CR_DIADIE_MASK)
1713#define CAU3_CR_SVIE_MASK (0x40U)
1714#define CAU3_CR_SVIE_SHIFT (6U)
1715/*! SVIE - Security Violation Interrupt Enable
1716 * 0b0..Security violation interruption is not enabled
1717 * 0b1..Security violation interruption is enabled
1718 */
1719#define CAU3_CR_SVIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_SVIE_SHIFT)) & CAU3_CR_SVIE_MASK)
1720#define CAU3_CR_TCIE_MASK (0x80U)
1721#define CAU3_CR_TCIE_SHIFT (7U)
1722/*! TCIE - Task completion with no error interrupt enable
1723 * 0b0..Disables task completion with no error to generate an interrupt request
1724 * 0b1..Enables task completion with no error to generate an interrupt request
1725 */
1726#define CAU3_CR_TCIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_TCIE_SHIFT)) & CAU3_CR_TCIE_MASK)
1727#define CAU3_CR_RSTSM4_MASK (0x3000U)
1728#define CAU3_CR_RSTSM4_SHIFT (12U)
1729/*! RSTSM4 - Reset Semaphore
1730 * 0b00..Idle state
1731 * 0b01..Wait for second write
1732 * 0b10..Clears semaphore if previous state was "01"
1733 * 0b11..Reserved
1734 */
1735#define CAU3_CR_RSTSM4(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_RSTSM4_SHIFT)) & CAU3_CR_RSTSM4_MASK)
1736#define CAU3_CR_MRST_MASK (0x8000U)
1737#define CAU3_CR_MRST_SHIFT (15U)
1738/*! MRST - Module Reset
1739 * 0b0..no action
1740 * 0b1..reset
1741 */
1742#define CAU3_CR_MRST(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_MRST_SHIFT)) & CAU3_CR_MRST_MASK)
1743#define CAU3_CR_FSV_MASK (0x10000U)
1744#define CAU3_CR_FSV_SHIFT (16U)
1745/*! FSV - Force Security Violation Test
1746 * 0b0..no violation is forced
1747 * 0b1..force security violation
1748 */
1749#define CAU3_CR_FSV(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_FSV_SHIFT)) & CAU3_CR_FSV_MASK)
1750#define CAU3_CR_DTCCFG_MASK (0x7000000U)
1751#define CAU3_CR_DTCCFG_SHIFT (24U)
1752/*! DTCCFG - Default Task Completion Configuration
1753 * 0b100..Issue a DMA request
1754 * 0b010..Assert Event Completion Signal
1755 * 0b001..Issue an Interrupt Request
1756 * 0b000..no explicit action
1757 */
1758#define CAU3_CR_DTCCFG(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DTCCFG_SHIFT)) & CAU3_CR_DTCCFG_MASK)
1759#define CAU3_CR_DSHFI_MASK (0x10000000U)
1760#define CAU3_CR_DSHFI_SHIFT (28U)
1761/*! DSHFI - Disable Secure Hash Function Instructions
1762 * 0b0..Secure Hash Functions are enabled
1763 * 0b1..Secure Hash Functions are disabled
1764 */
1765#define CAU3_CR_DSHFI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DSHFI_SHIFT)) & CAU3_CR_DSHFI_MASK)
1766#define CAU3_CR_DDESI_MASK (0x20000000U)
1767#define CAU3_CR_DDESI_SHIFT (29U)
1768/*! DDESI - Disable DES Instructions
1769 * 0b0..DES instructions are enabled
1770 * 0b1..DES instructions are disabled
1771 */
1772#define CAU3_CR_DDESI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DDESI_SHIFT)) & CAU3_CR_DDESI_MASK)
1773#define CAU3_CR_DAESI_MASK (0x40000000U)
1774#define CAU3_CR_DAESI_SHIFT (30U)
1775/*! DAESI - Disable AES Instructions
1776 * 0b0..AES instructions are enabled
1777 * 0b1..AES instructions are disabled
1778 */
1779#define CAU3_CR_DAESI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DAESI_SHIFT)) & CAU3_CR_DAESI_MASK)
1780#define CAU3_CR_MDIS_MASK (0x80000000U)
1781#define CAU3_CR_MDIS_SHIFT (31U)
1782/*! MDIS - Module Disable
1783 * 0b0..CAU3 exits from low power mode
1784 * 0b1..CAU3 enters low power mode
1785 */
1786#define CAU3_CR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_MDIS_SHIFT)) & CAU3_CR_MDIS_MASK)
1787/*! @} */
1788
1789/*! @name SR - Status Register */
1790/*! @{ */
1791#define CAU3_SR_TCSEIRQ_MASK (0x1U)
1792#define CAU3_SR_TCSEIRQ_SHIFT (0U)
1793/*! TCSEIRQ - Task completion with software error interrupt request
1794 * 0b0..Task not finished or finished with no software error
1795 * 0b1..Task execution finished with software error
1796 */
1797#define CAU3_SR_TCSEIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TCSEIRQ_SHIFT)) & CAU3_SR_TCSEIRQ_MASK)
1798#define CAU3_SR_ILLIRQ_MASK (0x2U)
1799#define CAU3_SR_ILLIRQ_SHIFT (1U)
1800/*! ILLIRQ - Illegal instruction interrupt request
1801 * 0b0..no error
1802 * 0b1..illegal instruction detected
1803 */
1804#define CAU3_SR_ILLIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_ILLIRQ_SHIFT)) & CAU3_SR_ILLIRQ_MASK)
1805#define CAU3_SR_ASREIRQ_MASK (0x8U)
1806#define CAU3_SR_ASREIRQ_SHIFT (3U)
1807/*! ASREIRQ - AHB slave response error interrupt Request
1808 * 0b0..no error
1809 * 0b1..AHB slave response error detected
1810 */
1811#define CAU3_SR_ASREIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_ASREIRQ_SHIFT)) & CAU3_SR_ASREIRQ_MASK)
1812#define CAU3_SR_IIADIRQ_MASK (0x10U)
1813#define CAU3_SR_IIADIRQ_SHIFT (4U)
1814/*! IIADIRQ - IMEM Illegal address interrupt request
1815 * 0b0..no error
1816 * 0b1..illegal IMEM address detected
1817 */
1818#define CAU3_SR_IIADIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_IIADIRQ_SHIFT)) & CAU3_SR_IIADIRQ_MASK)
1819#define CAU3_SR_DIADIRQ_MASK (0x20U)
1820#define CAU3_SR_DIADIRQ_SHIFT (5U)
1821/*! DIADIRQ - DMEM illegal access interrupt request
1822 * 0b0..no illegal address
1823 * 0b1..illegal address
1824 */
1825#define CAU3_SR_DIADIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_DIADIRQ_SHIFT)) & CAU3_SR_DIADIRQ_MASK)
1826#define CAU3_SR_SVIRQ_MASK (0x40U)
1827#define CAU3_SR_SVIRQ_SHIFT (6U)
1828/*! SVIRQ - Security violation interrupt request
1829 * 0b0..No security violation
1830 * 0b1..Security violation
1831 */
1832#define CAU3_SR_SVIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_SVIRQ_SHIFT)) & CAU3_SR_SVIRQ_MASK)
1833#define CAU3_SR_TCIRQ_MASK (0x80U)
1834#define CAU3_SR_TCIRQ_SHIFT (7U)
1835/*! TCIRQ - Task completion with no error interrupt request
1836 * 0b0..Task not finished or finished with error
1837 * 0b1..Task execution finished with no error
1838 */
1839#define CAU3_SR_TCIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TCIRQ_SHIFT)) & CAU3_SR_TCIRQ_MASK)
1840#define CAU3_SR_TKCS_MASK (0xF00U)
1841#define CAU3_SR_TKCS_SHIFT (8U)
1842/*! TKCS - Task completion status
1843 * 0b0000..Initialization RUN
1844 * 0b0001..Running
1845 * 0b0010..Debug Halted
1846 * 0b1001..Stop - Error Free
1847 * 0b1010..Stop - Error
1848 * 0b1110..Stop - Security Violation, assert security violation output signal and set SVIRQ
1849 * 0b1111..Stop - Security Violation and set SVIRQ
1850 */
1851#define CAU3_SR_TKCS(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TKCS_SHIFT)) & CAU3_SR_TKCS_MASK)
1852#define CAU3_SR_SVF_MASK (0x10000U)
1853#define CAU3_SR_SVF_SHIFT (16U)
1854/*! SVF - Security violation flag
1855 * 0b0..SoC security violation is not asserted
1856 * 0b1..SoC security violation was asserted
1857 */
1858#define CAU3_SR_SVF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_SVF_SHIFT)) & CAU3_SR_SVF_MASK)
1859#define CAU3_SR_DBG_MASK (0x20000U)
1860#define CAU3_SR_DBG_SHIFT (17U)
1861/*! DBG - Debug mode
1862 * 0b0..CAU3 is not in debug mode
1863 * 0b1..CAU3 is in debug mode
1864 */
1865#define CAU3_SR_DBG(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_DBG_SHIFT)) & CAU3_SR_DBG_MASK)
1866#define CAU3_SR_TCCFG_MASK (0x7000000U)
1867#define CAU3_SR_TCCFG_SHIFT (24U)
1868/*! TCCFG - Task completion configuration
1869 * 0b100..Issue a DMA request
1870 * 0b010..Assert the Event Completion Signal
1871 * 0b001..Assert an interrupt request
1872 * 0b000..No action
1873 */
1874#define CAU3_SR_TCCFG(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TCCFG_SHIFT)) & CAU3_SR_TCCFG_MASK)
1875#define CAU3_SR_MDISF_MASK (0x80000000U)
1876#define CAU3_SR_MDISF_SHIFT (31U)
1877/*! MDISF - Module disable flag
1878 * 0b0..CCore is not in low power mode
1879 * 0b1..CCore is in low power mode
1880 */
1881#define CAU3_SR_MDISF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_MDISF_SHIFT)) & CAU3_SR_MDISF_MASK)
1882/*! @} */
1883
1884/*! @name DBGCSR - Debug Control/Status Register */
1885/*! @{ */
1886#define CAU3_DBGCSR_DDBG_MASK (0x1U)
1887#define CAU3_DBGCSR_DDBG_SHIFT (0U)
1888/*! DDBG - Debug Disable
1889 * 0b0..debug is enabled
1890 * 0b1..debug is disabled
1891 */
1892#define CAU3_DBGCSR_DDBG(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_DDBG_SHIFT)) & CAU3_DBGCSR_DDBG_MASK)
1893#define CAU3_DBGCSR_DDBGMC_MASK (0x2U)
1894#define CAU3_DBGCSR_DDBGMC_SHIFT (1U)
1895/*! DDBGMC - Disable Debug Memory Commands
1896 * 0b0..IPS access to IMEM and DMEM are enabled
1897 * 0b1..IPS access to IMEM and DMEM are disabled
1898 */
1899#define CAU3_DBGCSR_DDBGMC(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_DDBGMC_SHIFT)) & CAU3_DBGCSR_DDBGMC_MASK)
1900#define CAU3_DBGCSR_PBREN_MASK (0x10U)
1901#define CAU3_DBGCSR_PBREN_SHIFT (4U)
1902/*! PBREN - PC Breakpoint Register Enable
1903 * 0b0..PC breakpoint register (DBGPBR) is disabled
1904 * 0b1..PC breakpoint register (DBGPBR) is enabled
1905 */
1906#define CAU3_DBGCSR_PBREN(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_PBREN_SHIFT)) & CAU3_DBGCSR_PBREN_MASK)
1907#define CAU3_DBGCSR_SIM_MASK (0x20U)
1908#define CAU3_DBGCSR_SIM_SHIFT (5U)
1909/*! SIM - Single Instruction Mode
1910 * 0b0..Single instruction mode is disabled
1911 * 0b1..Single instruction mode is enabled
1912 */
1913#define CAU3_DBGCSR_SIM(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_SIM_SHIFT)) & CAU3_DBGCSR_SIM_MASK)
1914#define CAU3_DBGCSR_FRCH_MASK (0x100U)
1915#define CAU3_DBGCSR_FRCH_SHIFT (8U)
1916/*! FRCH - Force Debug Halt
1917 * 0b0..Halt state not forced
1918 * 0b1..Force halt state
1919 */
1920#define CAU3_DBGCSR_FRCH(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_FRCH_SHIFT)) & CAU3_DBGCSR_FRCH_MASK)
1921#define CAU3_DBGCSR_DBGGO_MASK (0x1000U)
1922#define CAU3_DBGCSR_DBGGO_SHIFT (12U)
1923/*! DBGGO - Debug Go
1924 * 0b0..No action
1925 * 0b1..Resume program execution
1926 */
1927#define CAU3_DBGCSR_DBGGO(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_DBGGO_SHIFT)) & CAU3_DBGCSR_DBGGO_MASK)
1928#define CAU3_DBGCSR_PCBHF_MASK (0x10000U)
1929#define CAU3_DBGCSR_PCBHF_SHIFT (16U)
1930/*! PCBHF - CryptoCore is Halted due to Hardware Breakpoint
1931 * 0b0..CryptoCore is not halted due to a hardware breakpoint
1932 * 0b1..CryptoCore is halted due to a hardware breakpoint
1933 */
1934#define CAU3_DBGCSR_PCBHF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_PCBHF_SHIFT)) & CAU3_DBGCSR_PCBHF_MASK)
1935#define CAU3_DBGCSR_SIMHF_MASK (0x20000U)
1936#define CAU3_DBGCSR_SIMHF_SHIFT (17U)
1937/*! SIMHF - CryptoCore is Halted due to Single Instruction Step
1938 * 0b0..CryptoCore is not in a single step halt
1939 * 0b1..CryptoCore is in a single step halt
1940 */
1941#define CAU3_DBGCSR_SIMHF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_SIMHF_SHIFT)) & CAU3_DBGCSR_SIMHF_MASK)
1942#define CAU3_DBGCSR_HLTIF_MASK (0x40000U)
1943#define CAU3_DBGCSR_HLTIF_SHIFT (18U)
1944/*! HLTIF - CryptoCore is Halted due to HALT Instruction
1945 * 0b0..CryptoCore is not in software breakpoint
1946 * 0b1..CryptoCore is in software breakpoint
1947 */
1948#define CAU3_DBGCSR_HLTIF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_HLTIF_SHIFT)) & CAU3_DBGCSR_HLTIF_MASK)
1949#define CAU3_DBGCSR_CSTPF_MASK (0x40000000U)
1950#define CAU3_DBGCSR_CSTPF_SHIFT (30U)
1951/*! CSTPF - CryptoCore is Stopped Status Flag
1952 * 0b0..CryptoCore is not stopped
1953 * 0b1..CryptoCore is stopped
1954 */
1955#define CAU3_DBGCSR_CSTPF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_CSTPF_SHIFT)) & CAU3_DBGCSR_CSTPF_MASK)
1956#define CAU3_DBGCSR_CHLTF_MASK (0x80000000U)
1957#define CAU3_DBGCSR_CHLTF_SHIFT (31U)
1958/*! CHLTF - CryptoCore is Halted Status Flag
1959 * 0b0..CryptoCore is not halted
1960 * 0b1..CryptoCore is halted
1961 */
1962#define CAU3_DBGCSR_CHLTF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_CHLTF_SHIFT)) & CAU3_DBGCSR_CHLTF_MASK)
1963/*! @} */
1964
1965/*! @name DBGPBR - Debug PC Breakpoint Register */
1966/*! @{ */
1967#define CAU3_DBGPBR_PCBKPT_MASK (0xFFFFCU)
1968#define CAU3_DBGPBR_PCBKPT_SHIFT (2U)
1969#define CAU3_DBGPBR_PCBKPT(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGPBR_PCBKPT_SHIFT)) & CAU3_DBGPBR_PCBKPT_MASK)
1970/*! @} */
1971
1972/*! @name DBGMCMD - Debug Memory Command Register */
1973/*! @{ */
1974#define CAU3_DBGMCMD_DM_MASK (0x1000000U)
1975#define CAU3_DBGMCMD_DM_SHIFT (24U)
1976/*! DM - Instruction/Data Memory Selection
1977 * 0b0..IMEM is selected
1978 * 0b1..DMEM is selected
1979 */
1980#define CAU3_DBGMCMD_DM(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_DM_SHIFT)) & CAU3_DBGMCMD_DM_MASK)
1981#define CAU3_DBGMCMD_IA_MASK (0x4000000U)
1982#define CAU3_DBGMCMD_IA_SHIFT (26U)
1983/*! IA - Increment Address
1984 * 0b0..Address is not incremented
1985 * 0b1..Address is incremented after the access
1986 */
1987#define CAU3_DBGMCMD_IA(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_IA_SHIFT)) & CAU3_DBGMCMD_IA_MASK)
1988#define CAU3_DBGMCMD_Rb_1_MASK (0x8000000U)
1989#define CAU3_DBGMCMD_Rb_1_SHIFT (27U)
1990#define CAU3_DBGMCMD_Rb_1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_Rb_1_SHIFT)) & CAU3_DBGMCMD_Rb_1_MASK)
1991#define CAU3_DBGMCMD_BV_MASK (0x10000000U)
1992#define CAU3_DBGMCMD_BV_SHIFT (28U)
1993/*! BV - Byte Reversal Control
1994 * 0b0..DMEM bytes are not reversed
1995 * 0b1..DMEM bytes are reversed
1996 */
1997#define CAU3_DBGMCMD_BV(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_BV_SHIFT)) & CAU3_DBGMCMD_BV_MASK)
1998#define CAU3_DBGMCMD_R_0_MASK (0x40000000U)
1999#define CAU3_DBGMCMD_R_0_SHIFT (30U)
2000#define CAU3_DBGMCMD_R_0(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_R_0_SHIFT)) & CAU3_DBGMCMD_R_0_MASK)
2001#define CAU3_DBGMCMD_R_1_MASK (0x80000000U)
2002#define CAU3_DBGMCMD_R_1_SHIFT (31U)
2003#define CAU3_DBGMCMD_R_1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_R_1_SHIFT)) & CAU3_DBGMCMD_R_1_MASK)
2004/*! @} */
2005
2006/*! @name DBGMADR - Debug Memory Address Register */
2007/*! @{ */
2008#define CAU3_DBGMADR_DMADDR_MASK (0xFFFFFFFCU)
2009#define CAU3_DBGMADR_DMADDR_SHIFT (2U)
2010#define CAU3_DBGMADR_DMADDR(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMADR_DMADDR_SHIFT)) & CAU3_DBGMADR_DMADDR_MASK)
2011/*! @} */
2012
2013/*! @name DBGMDR - Debug Memory Data Register */
2014/*! @{ */
2015#define CAU3_DBGMDR_DMDATA_MASK (0xFFFFFFFFU)
2016#define CAU3_DBGMDR_DMDATA_SHIFT (0U)
2017#define CAU3_DBGMDR_DMDATA(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMDR_DMDATA_SHIFT)) & CAU3_DBGMDR_DMDATA_MASK)
2018/*! @} */
2019
2020/*! @name SEMA4 - Semaphore Register */
2021/*! @{ */
2022#define CAU3_SEMA4_DID_MASK (0xFU)
2023#define CAU3_SEMA4_DID_SHIFT (0U)
2024#define CAU3_SEMA4_DID(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_DID_SHIFT)) & CAU3_SEMA4_DID_MASK)
2025#define CAU3_SEMA4_PR_MASK (0x40U)
2026#define CAU3_SEMA4_PR_SHIFT (6U)
2027/*! PR - Privilege Attribute of Locked Semaphore Owner
2028 * 0b0..If semaphore is locked, then owner is operating in user mode
2029 * 0b1..If semaphore is locked, then owner is operating in privileged mode
2030 */
2031#define CAU3_SEMA4_PR(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_PR_SHIFT)) & CAU3_SEMA4_PR_MASK)
2032#define CAU3_SEMA4_NS_MASK (0x80U)
2033#define CAU3_SEMA4_NS_SHIFT (7U)
2034/*! NS - Non Secure Attribute of the Locked Semaphore Owner
2035 * 0b0..If semaphore is locked, owner is operating in secure mode
2036 * 0b1..If semaphore is locked, owner is operating in nonsecure mode
2037 */
2038#define CAU3_SEMA4_NS(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_NS_SHIFT)) & CAU3_SEMA4_NS_MASK)
2039#define CAU3_SEMA4_MSTRN_MASK (0x3F00U)
2040#define CAU3_SEMA4_MSTRN_SHIFT (8U)
2041#define CAU3_SEMA4_MSTRN(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_MSTRN_SHIFT)) & CAU3_SEMA4_MSTRN_MASK)
2042#define CAU3_SEMA4_LK_MASK (0x80000000U)
2043#define CAU3_SEMA4_LK_SHIFT (31U)
2044/*! LK - Semaphore Lock and Release Control
2045 * 0b0..Semaphore release
2046 * 0b1..Semaphore lock
2047 */
2048#define CAU3_SEMA4_LK(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_LK_SHIFT)) & CAU3_SEMA4_LK_MASK)
2049/*! @} */
2050
2051/*! @name SMOWNR - Semaphore Ownership Register */
2052/*! @{ */
2053#define CAU3_SMOWNR_LOCK_MASK (0x1U)
2054#define CAU3_SMOWNR_LOCK_SHIFT (0U)
2055/*! LOCK - Semaphore Locked
2056 * 0b0..Semaphore not locked
2057 * 0b1..Semaphore locked
2058 */
2059#define CAU3_SMOWNR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SMOWNR_LOCK_SHIFT)) & CAU3_SMOWNR_LOCK_MASK)
2060#define CAU3_SMOWNR_NOWNER_MASK (0x80000000U)
2061#define CAU3_SMOWNR_NOWNER_SHIFT (31U)
2062/*! NOWNER - Semaphore Ownership
2063 * 0b0..The host making the current read access is the semaphore owner
2064 * 0b1..The host making the current read access is NOT the semaphore owner
2065 */
2066#define CAU3_SMOWNR_NOWNER(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SMOWNR_NOWNER_SHIFT)) & CAU3_SMOWNR_NOWNER_MASK)
2067/*! @} */
2068
2069/*! @name ARR - Address Remap Register */
2070/*! @{ */
2071#define CAU3_ARR_ARRL_MASK (0xFFFFFFFFU)
2072#define CAU3_ARR_ARRL_SHIFT (0U)
2073#define CAU3_ARR_ARRL(x) (((uint32_t)(((uint32_t)(x)) << CAU3_ARR_ARRL_SHIFT)) & CAU3_ARR_ARRL_MASK)
2074/*! @} */
2075
2076/*! @name CC_R - CryptoCore General Purpose Registers */
2077/*! @{ */
2078#define CAU3_CC_R_R_MASK (0xFFFFFFFFU)
2079#define CAU3_CC_R_R_SHIFT (0U)
2080#define CAU3_CC_R_R(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_R_R_SHIFT)) & CAU3_CC_R_R_MASK)
2081/*! @} */
2082
2083/* The count of CAU3_CC_R */
2084#define CAU3_CC_R_COUNT (30U)
2085
2086/*! @name CC_R30 - General Purpose R30 */
2087/*! @{ */
2088#define CAU3_CC_R30_SP_MASK (0xFFFFFFFFU)
2089#define CAU3_CC_R30_SP_SHIFT (0U)
2090#define CAU3_CC_R30_SP(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_R30_SP_SHIFT)) & CAU3_CC_R30_SP_MASK)
2091/*! @} */
2092
2093/*! @name CC_R31 - General Purpose R31 */
2094/*! @{ */
2095#define CAU3_CC_R31_LR_MASK (0xFFFFFFFFU)
2096#define CAU3_CC_R31_LR_SHIFT (0U)
2097#define CAU3_CC_R31_LR(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_R31_LR_SHIFT)) & CAU3_CC_R31_LR_MASK)
2098/*! @} */
2099
2100/*! @name CC_PC - Program Counter */
2101/*! @{ */
2102#define CAU3_CC_PC_PC_MASK (0xFFFFFU)
2103#define CAU3_CC_PC_PC_SHIFT (0U)
2104#define CAU3_CC_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_PC_PC_SHIFT)) & CAU3_CC_PC_PC_MASK)
2105/*! @} */
2106
2107/*! @name CC_CMD - Start Command Register */
2108/*! @{ */
2109#define CAU3_CC_CMD_CMD_MASK (0x70000U)
2110#define CAU3_CC_CMD_CMD_SHIFT (16U)
2111/*! CMD - Command
2112 * 0b000..Use CR[DTCCFG] for task completion configuration
2113 * 0b100..Issue a DMA request
2114 * 0b010..Assert Event Completion Signal
2115 * 0b001..Issue an interrupt request
2116 */
2117#define CAU3_CC_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CMD_CMD_SHIFT)) & CAU3_CC_CMD_CMD_MASK)
2118/*! @} */
2119
2120/*! @name CC_CF - Condition Flag */
2121/*! @{ */
2122#define CAU3_CC_CF_C_MASK (0x1U)
2123#define CAU3_CC_CF_C_SHIFT (0U)
2124#define CAU3_CC_CF_C(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_C_SHIFT)) & CAU3_CC_CF_C_MASK)
2125#define CAU3_CC_CF_V_MASK (0x2U)
2126#define CAU3_CC_CF_V_SHIFT (1U)
2127#define CAU3_CC_CF_V(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_V_SHIFT)) & CAU3_CC_CF_V_MASK)
2128#define CAU3_CC_CF_Z_MASK (0x4U)
2129#define CAU3_CC_CF_Z_SHIFT (2U)
2130#define CAU3_CC_CF_Z(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_Z_SHIFT)) & CAU3_CC_CF_Z_MASK)
2131#define CAU3_CC_CF_N_MASK (0x8U)
2132#define CAU3_CC_CF_N_SHIFT (3U)
2133#define CAU3_CC_CF_N(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_N_SHIFT)) & CAU3_CC_CF_N_MASK)
2134/*! @} */
2135
2136/*! @name MDPK - Mode Register (PublicKey) */
2137/*! @{ */
2138#define CAU3_MDPK_PKHA_MODE_LS_MASK (0xFFFU)
2139#define CAU3_MDPK_PKHA_MODE_LS_SHIFT (0U)
2140#define CAU3_MDPK_PKHA_MODE_LS(x) (((uint32_t)(((uint32_t)(x)) << CAU3_MDPK_PKHA_MODE_LS_SHIFT)) & CAU3_MDPK_PKHA_MODE_LS_MASK)
2141#define CAU3_MDPK_PKHA_MODE_MS_MASK (0xF0000U)
2142#define CAU3_MDPK_PKHA_MODE_MS_SHIFT (16U)
2143#define CAU3_MDPK_PKHA_MODE_MS(x) (((uint32_t)(((uint32_t)(x)) << CAU3_MDPK_PKHA_MODE_MS_SHIFT)) & CAU3_MDPK_PKHA_MODE_MS_MASK)
2144#define CAU3_MDPK_ALG_MASK (0xF00000U)
2145#define CAU3_MDPK_ALG_SHIFT (20U)
2146/*! ALG - Algorithm
2147 * 0b1000..PKHA
2148 */
2149#define CAU3_MDPK_ALG(x) (((uint32_t)(((uint32_t)(x)) << CAU3_MDPK_ALG_SHIFT)) & CAU3_MDPK_ALG_MASK)
2150/*! @} */
2151
2152/*! @name COM - Command Register */
2153/*! @{ */
2154#define CAU3_COM_ALL_MASK (0x1U)
2155#define CAU3_COM_ALL_SHIFT (0U)
2156/*! ALL - Reset All Internal Logic
2157 * 0b0..Do Not Reset
2158 * 0b1..Reset PKHA engine and registers
2159 */
2160#define CAU3_COM_ALL(x) (((uint32_t)(((uint32_t)(x)) << CAU3_COM_ALL_SHIFT)) & CAU3_COM_ALL_MASK)
2161#define CAU3_COM_PK_MASK (0x40U)
2162#define CAU3_COM_PK_SHIFT (6U)
2163/*! PK - Reset PKHA
2164 * 0b0..Do Not Reset
2165 * 0b1..Reset Public Key Hardware Accelerator
2166 */
2167#define CAU3_COM_PK(x) (((uint32_t)(((uint32_t)(x)) << CAU3_COM_PK_SHIFT)) & CAU3_COM_PK_MASK)
2168/*! @} */
2169
2170/*! @name CTL - Control Register */
2171/*! @{ */
2172#define CAU3_CTL_IM_MASK (0x1U)
2173#define CAU3_CTL_IM_SHIFT (0U)
2174/*! IM - Interrupt Mask
2175 * 0b0..Interrupt not masked.
2176 * 0b1..Interrupt masked
2177 */
2178#define CAU3_CTL_IM(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CTL_IM_SHIFT)) & CAU3_CTL_IM_MASK)
2179#define CAU3_CTL_PDE_MASK (0x10U)
2180#define CAU3_CTL_PDE_SHIFT (4U)
2181/*! PDE - PKHA Register DMA Enable
2182 * 0b0..DMA Request and Done signals disabled for the PKHA Registers.
2183 * 0b1..DMA Request and Done signals enabled for the PKHA Registers.
2184 */
2185#define CAU3_CTL_PDE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CTL_PDE_SHIFT)) & CAU3_CTL_PDE_MASK)
2186/*! @} */
2187
2188/*! @name CW - Clear Written Register */
2189/*! @{ */
2190#define CAU3_CW_CM_MASK (0x1U)
2191#define CAU3_CW_CM_SHIFT (0U)
2192#define CAU3_CW_CM(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CM_SHIFT)) & CAU3_CW_CM_MASK)
2193#define CAU3_CW_CPKA_MASK (0x1000U)
2194#define CAU3_CW_CPKA_SHIFT (12U)
2195#define CAU3_CW_CPKA(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKA_SHIFT)) & CAU3_CW_CPKA_MASK)
2196#define CAU3_CW_CPKB_MASK (0x2000U)
2197#define CAU3_CW_CPKB_SHIFT (13U)
2198#define CAU3_CW_CPKB(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKB_SHIFT)) & CAU3_CW_CPKB_MASK)
2199#define CAU3_CW_CPKN_MASK (0x4000U)
2200#define CAU3_CW_CPKN_SHIFT (14U)
2201#define CAU3_CW_CPKN(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKN_SHIFT)) & CAU3_CW_CPKN_MASK)
2202#define CAU3_CW_CPKE_MASK (0x8000U)
2203#define CAU3_CW_CPKE_SHIFT (15U)
2204#define CAU3_CW_CPKE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKE_SHIFT)) & CAU3_CW_CPKE_MASK)
2205/*! @} */
2206
2207/*! @name STA - Status Register */
2208/*! @{ */
2209#define CAU3_STA_PB_MASK (0x40U)
2210#define CAU3_STA_PB_SHIFT (6U)
2211/*! PB - PKHA Busy
2212 * 0b0..PKHA Idle
2213 * 0b1..PKHA Busy.
2214 */
2215#define CAU3_STA_PB(x) (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PB_SHIFT)) & CAU3_STA_PB_MASK)
2216#define CAU3_STA_DI_MASK (0x10000U)
2217#define CAU3_STA_DI_SHIFT (16U)
2218#define CAU3_STA_DI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_STA_DI_SHIFT)) & CAU3_STA_DI_MASK)
2219#define CAU3_STA_EI_MASK (0x100000U)
2220#define CAU3_STA_EI_SHIFT (20U)
2221/*! EI - Error Interrupt
2222 * 0b0..Not Error.
2223 * 0b1..Error Interrupt.
2224 */
2225#define CAU3_STA_EI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_STA_EI_SHIFT)) & CAU3_STA_EI_MASK)
2226#define CAU3_STA_PKP_MASK (0x10000000U)
2227#define CAU3_STA_PKP_SHIFT (28U)
2228#define CAU3_STA_PKP(x) (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PKP_SHIFT)) & CAU3_STA_PKP_MASK)
2229#define CAU3_STA_PKO_MASK (0x20000000U)
2230#define CAU3_STA_PKO_SHIFT (29U)
2231#define CAU3_STA_PKO(x) (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PKO_SHIFT)) & CAU3_STA_PKO_MASK)
2232#define CAU3_STA_PKZ_MASK (0x40000000U)
2233#define CAU3_STA_PKZ_SHIFT (30U)
2234#define CAU3_STA_PKZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PKZ_SHIFT)) & CAU3_STA_PKZ_MASK)
2235/*! @} */
2236
2237/*! @name ESTA - Error Status Register */
2238/*! @{ */
2239#define CAU3_ESTA_ERRID1_MASK (0xFU)
2240#define CAU3_ESTA_ERRID1_SHIFT (0U)
2241/*! ERRID1 - Error ID 1
2242 * 0b0001..Mode Error
2243 * 0b0010..PKHA N Register Size Error
2244 * 0b0011..PKHA E Register Size Error
2245 * 0b0100..PKHA A Register Size Error
2246 * 0b0101..PKHA B Register Size Error
2247 * 0b0110..PKHA C input (as contained in the PKHA B0 quadrant) is Zero
2248 * 0b0111..PKHA Divide by Zero Error
2249 * 0b1000..PKHA Modulus Even Error
2250 * 0b1111..Invalid Crypto Engine Selected
2251 */
2252#define CAU3_ESTA_ERRID1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_ESTA_ERRID1_SHIFT)) & CAU3_ESTA_ERRID1_MASK)
2253#define CAU3_ESTA_CL1_MASK (0xF00U)
2254#define CAU3_ESTA_CL1_SHIFT (8U)
2255/*! CL1 - algorithms
2256 * 0b0000..General Error
2257 * 0b1000..Public Key
2258 */
2259#define CAU3_ESTA_CL1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_ESTA_CL1_SHIFT)) & CAU3_ESTA_CL1_MASK)
2260/*! @} */
2261
2262/*! @name PKASZ - PKHA A Size Register */
2263/*! @{ */
2264#define CAU3_PKASZ_PKASZ_MASK (0x1FFU)
2265#define CAU3_PKASZ_PKASZ_SHIFT (0U)
2266#define CAU3_PKASZ_PKASZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKASZ_PKASZ_SHIFT)) & CAU3_PKASZ_PKASZ_MASK)
2267/*! @} */
2268
2269/*! @name PKBSZ - PKHA B Size Register */
2270/*! @{ */
2271#define CAU3_PKBSZ_PKBSZ_MASK (0x1FFU)
2272#define CAU3_PKBSZ_PKBSZ_SHIFT (0U)
2273#define CAU3_PKBSZ_PKBSZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKBSZ_PKBSZ_SHIFT)) & CAU3_PKBSZ_PKBSZ_MASK)
2274/*! @} */
2275
2276/*! @name PKNSZ - PKHA N Size Register */
2277/*! @{ */
2278#define CAU3_PKNSZ_PKNSZ_MASK (0x1FFU)
2279#define CAU3_PKNSZ_PKNSZ_SHIFT (0U)
2280#define CAU3_PKNSZ_PKNSZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKNSZ_PKNSZ_SHIFT)) & CAU3_PKNSZ_PKNSZ_MASK)
2281/*! @} */
2282
2283/*! @name PKESZ - PKHA E Size Register */
2284/*! @{ */
2285#define CAU3_PKESZ_PKESZ_MASK (0x1FFU)
2286#define CAU3_PKESZ_PKESZ_SHIFT (0U)
2287#define CAU3_PKESZ_PKESZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKESZ_PKESZ_SHIFT)) & CAU3_PKESZ_PKESZ_MASK)
2288/*! @} */
2289
2290/*! @name PKHA_VID1 - PKHA Revision ID 1 */
2291/*! @{ */
2292#define CAU3_PKHA_VID1_MIN_REV_MASK (0xFFU)
2293#define CAU3_PKHA_VID1_MIN_REV_SHIFT (0U)
2294#define CAU3_PKHA_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID1_MIN_REV_SHIFT)) & CAU3_PKHA_VID1_MIN_REV_MASK)
2295#define CAU3_PKHA_VID1_MAJ_REV_MASK (0xFF00U)
2296#define CAU3_PKHA_VID1_MAJ_REV_SHIFT (8U)
2297#define CAU3_PKHA_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID1_MAJ_REV_SHIFT)) & CAU3_PKHA_VID1_MAJ_REV_MASK)
2298#define CAU3_PKHA_VID1_IP_ID_MASK (0xFFFF0000U)
2299#define CAU3_PKHA_VID1_IP_ID_SHIFT (16U)
2300#define CAU3_PKHA_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID1_IP_ID_SHIFT)) & CAU3_PKHA_VID1_IP_ID_MASK)
2301/*! @} */
2302
2303/*! @name PKHA_VID2 - PKHA Revision ID 2 */
2304/*! @{ */
2305#define CAU3_PKHA_VID2_ECO_REV_MASK (0xFFU)
2306#define CAU3_PKHA_VID2_ECO_REV_SHIFT (0U)
2307#define CAU3_PKHA_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID2_ECO_REV_SHIFT)) & CAU3_PKHA_VID2_ECO_REV_MASK)
2308#define CAU3_PKHA_VID2_ARCH_ERA_MASK (0xFF00U)
2309#define CAU3_PKHA_VID2_ARCH_ERA_SHIFT (8U)
2310#define CAU3_PKHA_VID2_ARCH_ERA(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID2_ARCH_ERA_SHIFT)) & CAU3_PKHA_VID2_ARCH_ERA_MASK)
2311/*! @} */
2312
2313/*! @name CHA_VID - CHA Revision ID */
2314/*! @{ */
2315#define CAU3_CHA_VID_PKHAREV_MASK (0xF0000U)
2316#define CAU3_CHA_VID_PKHAREV_SHIFT (16U)
2317#define CAU3_CHA_VID_PKHAREV(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CHA_VID_PKHAREV_SHIFT)) & CAU3_CHA_VID_PKHAREV_MASK)
2318#define CAU3_CHA_VID_PKHAVID_MASK (0xF00000U)
2319#define CAU3_CHA_VID_PKHAVID_SHIFT (20U)
2320#define CAU3_CHA_VID_PKHAVID(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CHA_VID_PKHAVID_SHIFT)) & CAU3_CHA_VID_PKHAVID_MASK)
2321/*! @} */
2322
2323/*! @name PKHA_CCR - PKHA Clock Control Register */
2324/*! @{ */
2325#define CAU3_PKHA_CCR_CKTHRT_MASK (0x7U)
2326#define CAU3_PKHA_CCR_CKTHRT_SHIFT (0U)
2327/*! CKTHRT - Clock Throttle selection
2328 * 0b000..PKHA clock division rate is 8/8 - full speed
2329 * 0b001..PKHA clock division rate is 1/8
2330 * 0b010..PKHA clock division rate is 2/8
2331 * 0b011..PKHA clock division rate is 3/8
2332 * 0b100..PKHA clock division rate is 4/8
2333 * 0b101..PKHA clock division rate is 5/8
2334 * 0b110..PKHA clock division rate is 6/8
2335 * 0b111..PKHA clock division rate is 7/8
2336 */
2337#define CAU3_PKHA_CCR_CKTHRT(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_CKTHRT_SHIFT)) & CAU3_PKHA_CCR_CKTHRT_MASK)
2338#define CAU3_PKHA_CCR_LK_MASK (0x1000000U)
2339#define CAU3_PKHA_CCR_LK_SHIFT (24U)
2340/*! LK - Register Lock
2341 * 0b0..Register is unlocked
2342 * 0b1..Register is locked
2343 */
2344#define CAU3_PKHA_CCR_LK(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_LK_SHIFT)) & CAU3_PKHA_CCR_LK_MASK)
2345#define CAU3_PKHA_CCR_ELFR_MASK (0x20000000U)
2346#define CAU3_PKHA_CCR_ELFR_SHIFT (29U)
2347/*! ELFR - Enable Linear Feedback Shift Register
2348 * 0b0..LFSR is only enabled if ECT = 1 and ECJ = 1
2349 * 0b1..LFSR is enabled independently of ECT and ECJ
2350 */
2351#define CAU3_PKHA_CCR_ELFR(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_ELFR_SHIFT)) & CAU3_PKHA_CCR_ELFR_MASK)
2352#define CAU3_PKHA_CCR_ECJ_MASK (0x40000000U)
2353#define CAU3_PKHA_CCR_ECJ_SHIFT (30U)
2354/*! ECJ - Enable Clock Jitter
2355 * 0b0..Clock Jitter is disabled
2356 * 0b1..Clock jitter is enabled
2357 */
2358#define CAU3_PKHA_CCR_ECJ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_ECJ_SHIFT)) & CAU3_PKHA_CCR_ECJ_MASK)
2359#define CAU3_PKHA_CCR_ECT_MASK (0x80000000U)
2360#define CAU3_PKHA_CCR_ECT_SHIFT (31U)
2361/*! ECT - Enable Clock Throttle
2362 * 0b0..PKHA clock throttle disabled meaning that PKHA is operatiing at full speed
2363 * 0b1..PKHA clock throttle enabled
2364 */
2365#define CAU3_PKHA_CCR_ECT(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_ECT_SHIFT)) & CAU3_PKHA_CCR_ECT_MASK)
2366/*! @} */
2367
2368/*! @name GSR - Global Status Register */
2369/*! @{ */
2370#define CAU3_GSR_CDI_MASK (0x400U)
2371#define CAU3_GSR_CDI_SHIFT (10U)
2372/*! CDI - CAU3 Done Interrupt occurred
2373 * 0b0..CAU3 Done Interrupt did not occur
2374 * 0b1..CAU3 Done Interrupt occurred
2375 */
2376#define CAU3_GSR_CDI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_CDI_SHIFT)) & CAU3_GSR_CDI_MASK)
2377#define CAU3_GSR_CEI_MASK (0x4000U)
2378#define CAU3_GSR_CEI_SHIFT (14U)
2379/*! CEI - CAU3 Error Interrupt
2380 * 0b0..CAU3 Error Interrupt did not occur
2381 * 0b1..CAU3 Error Interrupt occurred
2382 */
2383#define CAU3_GSR_CEI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_CEI_SHIFT)) & CAU3_GSR_CEI_MASK)
2384#define CAU3_GSR_PEI_MASK (0x8000U)
2385#define CAU3_GSR_PEI_SHIFT (15U)
2386/*! PEI - PKHA Done or Error Interrupt
2387 * 0b0..PKHA interrupt did not occur
2388 * 0b1..PKHA interrupt had occurred
2389 */
2390#define CAU3_GSR_PEI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_PEI_SHIFT)) & CAU3_GSR_PEI_MASK)
2391#define CAU3_GSR_PBSY_MASK (0x80000000U)
2392#define CAU3_GSR_PBSY_SHIFT (31U)
2393/*! PBSY - PKHA Busy
2394 * 0b0..PKHA not busy
2395 * 0b1..PKHA busy
2396 */
2397#define CAU3_GSR_PBSY(x) (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_PBSY_SHIFT)) & CAU3_GSR_PBSY_MASK)
2398/*! @} */
2399
2400/*! @name CKLFSR - Clock Linear Feedback Shift Register */
2401/*! @{ */
2402#define CAU3_CKLFSR_LFSR_MASK (0xFFFFFFFFU)
2403#define CAU3_CKLFSR_LFSR_SHIFT (0U)
2404#define CAU3_CKLFSR_LFSR(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CKLFSR_LFSR_SHIFT)) & CAU3_CKLFSR_LFSR_MASK)
2405/*! @} */
2406
2407/*! @name PKA0 - PKHA A0 Register */
2408/*! @{ */
2409#define CAU3_PKA0_PKHA_A0_MASK (0xFFFFFFFFU)
2410#define CAU3_PKA0_PKHA_A0_SHIFT (0U)
2411#define CAU3_PKA0_PKHA_A0(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKA0_PKHA_A0_SHIFT)) & CAU3_PKA0_PKHA_A0_MASK)
2412/*! @} */
2413
2414/* The count of CAU3_PKA0 */
2415#define CAU3_PKA0_COUNT (32U)
2416
2417/*! @name PKA1 - PKHA A1 Register */
2418/*! @{ */
2419#define CAU3_PKA1_PKHA_A1_MASK (0xFFFFFFFFU)
2420#define CAU3_PKA1_PKHA_A1_SHIFT (0U)
2421#define CAU3_PKA1_PKHA_A1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKA1_PKHA_A1_SHIFT)) & CAU3_PKA1_PKHA_A1_MASK)
2422/*! @} */
2423
2424/* The count of CAU3_PKA1 */
2425#define CAU3_PKA1_COUNT (32U)
2426
2427/*! @name PKA2 - PKHA A2 Register */
2428/*! @{ */
2429#define CAU3_PKA2_PKHA_A2_MASK (0xFFFFFFFFU)
2430#define CAU3_PKA2_PKHA_A2_SHIFT (0U)
2431#define CAU3_PKA2_PKHA_A2(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKA2_PKHA_A2_SHIFT)) & CAU3_PKA2_PKHA_A2_MASK)
2432/*! @} */
2433
2434/* The count of CAU3_PKA2 */
2435#define CAU3_PKA2_COUNT (32U)
2436
2437/*! @name PKA3 - PKHA A3 Register */
2438/*! @{ */
2439#define CAU3_PKA3_PKHA_A3_MASK (0xFFFFFFFFU)
2440#define CAU3_PKA3_PKHA_A3_SHIFT (0U)
2441#define CAU3_PKA3_PKHA_A3(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKA3_PKHA_A3_SHIFT)) & CAU3_PKA3_PKHA_A3_MASK)
2442/*! @} */
2443
2444/* The count of CAU3_PKA3 */
2445#define CAU3_PKA3_COUNT (32U)
2446
2447/*! @name PKB0 - PKHA B0 Register */
2448/*! @{ */
2449#define CAU3_PKB0_PKHA_B0_MASK (0xFFFFFFFFU)
2450#define CAU3_PKB0_PKHA_B0_SHIFT (0U)
2451#define CAU3_PKB0_PKHA_B0(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKB0_PKHA_B0_SHIFT)) & CAU3_PKB0_PKHA_B0_MASK)
2452/*! @} */
2453
2454/* The count of CAU3_PKB0 */
2455#define CAU3_PKB0_COUNT (32U)
2456
2457/*! @name PKB1 - PKHA B1 Register */
2458/*! @{ */
2459#define CAU3_PKB1_PKHA_B1_MASK (0xFFFFFFFFU)
2460#define CAU3_PKB1_PKHA_B1_SHIFT (0U)
2461#define CAU3_PKB1_PKHA_B1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKB1_PKHA_B1_SHIFT)) & CAU3_PKB1_PKHA_B1_MASK)
2462/*! @} */
2463
2464/* The count of CAU3_PKB1 */
2465#define CAU3_PKB1_COUNT (32U)
2466
2467/*! @name PKB2 - PKHA B2 Register */
2468/*! @{ */
2469#define CAU3_PKB2_PKHA_B2_MASK (0xFFFFFFFFU)
2470#define CAU3_PKB2_PKHA_B2_SHIFT (0U)
2471#define CAU3_PKB2_PKHA_B2(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKB2_PKHA_B2_SHIFT)) & CAU3_PKB2_PKHA_B2_MASK)
2472/*! @} */
2473
2474/* The count of CAU3_PKB2 */
2475#define CAU3_PKB2_COUNT (32U)
2476
2477/*! @name PKB3 - PKHA B3 Register */
2478/*! @{ */
2479#define CAU3_PKB3_PKHA_B3_MASK (0xFFFFFFFFU)
2480#define CAU3_PKB3_PKHA_B3_SHIFT (0U)
2481#define CAU3_PKB3_PKHA_B3(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKB3_PKHA_B3_SHIFT)) & CAU3_PKB3_PKHA_B3_MASK)
2482/*! @} */
2483
2484/* The count of CAU3_PKB3 */
2485#define CAU3_PKB3_COUNT (32U)
2486
2487/*! @name PKN0 - PKHA N0 Register */
2488/*! @{ */
2489#define CAU3_PKN0_PKHA_N0_MASK (0xFFFFFFFFU)
2490#define CAU3_PKN0_PKHA_N0_SHIFT (0U)
2491#define CAU3_PKN0_PKHA_N0(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKN0_PKHA_N0_SHIFT)) & CAU3_PKN0_PKHA_N0_MASK)
2492/*! @} */
2493
2494/* The count of CAU3_PKN0 */
2495#define CAU3_PKN0_COUNT (32U)
2496
2497/*! @name PKN1 - PKHA N1 Register */
2498/*! @{ */
2499#define CAU3_PKN1_PKHA_N1_MASK (0xFFFFFFFFU)
2500#define CAU3_PKN1_PKHA_N1_SHIFT (0U)
2501#define CAU3_PKN1_PKHA_N1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKN1_PKHA_N1_SHIFT)) & CAU3_PKN1_PKHA_N1_MASK)
2502/*! @} */
2503
2504/* The count of CAU3_PKN1 */
2505#define CAU3_PKN1_COUNT (32U)
2506
2507/*! @name PKN2 - PKHA N2 Register */
2508/*! @{ */
2509#define CAU3_PKN2_PKHA_N2_MASK (0xFFFFFFFFU)
2510#define CAU3_PKN2_PKHA_N2_SHIFT (0U)
2511#define CAU3_PKN2_PKHA_N2(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKN2_PKHA_N2_SHIFT)) & CAU3_PKN2_PKHA_N2_MASK)
2512/*! @} */
2513
2514/* The count of CAU3_PKN2 */
2515#define CAU3_PKN2_COUNT (32U)
2516
2517/*! @name PKN3 - PKHA N3 Register */
2518/*! @{ */
2519#define CAU3_PKN3_PKHA_N3_MASK (0xFFFFFFFFU)
2520#define CAU3_PKN3_PKHA_N3_SHIFT (0U)
2521#define CAU3_PKN3_PKHA_N3(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKN3_PKHA_N3_SHIFT)) & CAU3_PKN3_PKHA_N3_MASK)
2522/*! @} */
2523
2524/* The count of CAU3_PKN3 */
2525#define CAU3_PKN3_COUNT (32U)
2526
2527/*! @name PKE - PKHA E Register */
2528/*! @{ */
2529#define CAU3_PKE_PKHA_E_MASK (0xFFFFFFFFU)
2530#define CAU3_PKE_PKHA_E_SHIFT (0U)
2531#define CAU3_PKE_PKHA_E(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKE_PKHA_E_SHIFT)) & CAU3_PKE_PKHA_E_MASK)
2532/*! @} */
2533
2534/* The count of CAU3_PKE */
2535#define CAU3_PKE_COUNT (128U)
2536
2537
2538/*!
2539 * @}
2540 */ /* end of group CAU3_Register_Masks */
2541
2542
2543/* CAU3 - Peripheral instance base addresses */
2544/** Peripheral CAU3 base address */
2545#define CAU3_BASE (0x41028000u)
2546/** Peripheral CAU3 base pointer */
2547#define CAU3 ((CAU3_Type *)CAU3_BASE)
2548/** Array initializer of CAU3 peripheral base addresses */
2549#define CAU3_BASE_ADDRS { CAU3_BASE }
2550/** Array initializer of CAU3 peripheral base pointers */
2551#define CAU3_BASE_PTRS { CAU3 }
2552/** Interrupt vectors for the CAU3 peripheral type */
2553#define CAU3_TASK_COMPLETE_IRQS { CAU3_Task_Complete_IRQn }
2554#define CAU3_SECURITY_VIOLATION_IRQS { CAU3_Security_Violation_IRQn }
2555
2556/*!
2557 * @}
2558 */ /* end of group CAU3_Peripheral_Access_Layer */
2559
2560
2561/* ----------------------------------------------------------------------------
2562 -- CRC Peripheral Access Layer
2563 ---------------------------------------------------------------------------- */
2564
2565/*!
2566 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
2567 * @{
2568 */
2569
2570/** CRC - Register Layout Typedef */
2571typedef struct {
2572 union { /* offset: 0x0 */
2573 struct { /* offset: 0x0 */
2574 __IO uint8_t DATALL; /**< CRC_DATALL register, offset: 0x0 */
2575 __IO uint8_t DATALU; /**< CRC_DATALU register, offset: 0x1 */
2576 __IO uint8_t DATAHL; /**< CRC_DATAHL register, offset: 0x2 */
2577 __IO uint8_t DATAHU; /**< CRC_DATAHU register, offset: 0x3 */
2578 } ACCESS8BIT;
2579 struct { /* offset: 0x0 */
2580 __IO uint16_t DATAL; /**< CRC_DATAL register, offset: 0x0 */
2581 __IO uint16_t DATAH; /**< CRC_DATAH register, offset: 0x2 */
2582 } ACCESS16BIT;
2583 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
2584 };
2585 union { /* offset: 0x4 */
2586 struct { /* offset: 0x4 */
2587 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register, offset: 0x4 */
2588 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register, offset: 0x5 */
2589 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register, offset: 0x6 */
2590 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register, offset: 0x7 */
2591 } GPOLY_ACCESS8BIT;
2592 struct { /* offset: 0x4 */
2593 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register, offset: 0x4 */
2594 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register, offset: 0x6 */
2595 } GPOLY_ACCESS16BIT;
2596 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
2597 };
2598 union { /* offset: 0x8 */
2599 struct { /* offset: 0x8 */
2600 uint8_t RESERVED_0[3];
2601 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register, offset: 0xB */
2602 } CTRL_ACCESS8BIT;
2603 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
2604 };
2605} CRC_Type;
2606
2607/* ----------------------------------------------------------------------------
2608 -- CRC Register Masks
2609 ---------------------------------------------------------------------------- */
2610
2611/*!
2612 * @addtogroup CRC_Register_Masks CRC Register Masks
2613 * @{
2614 */
2615
2616/*! @name DATALL - CRC_DATALL register */
2617/*! @{ */
2618#define CRC_DATALL_DATALL_MASK (0xFFU)
2619#define CRC_DATALL_DATALL_SHIFT (0U)
2620#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
2621/*! @} */
2622
2623/*! @name DATALU - CRC_DATALU register */
2624/*! @{ */
2625#define CRC_DATALU_DATALU_MASK (0xFFU)
2626#define CRC_DATALU_DATALU_SHIFT (0U)
2627#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
2628/*! @} */
2629
2630/*! @name DATAHL - CRC_DATAHL register */
2631/*! @{ */
2632#define CRC_DATAHL_DATAHL_MASK (0xFFU)
2633#define CRC_DATAHL_DATAHL_SHIFT (0U)
2634#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
2635/*! @} */
2636
2637/*! @name DATAHU - CRC_DATAHU register */
2638/*! @{ */
2639#define CRC_DATAHU_DATAHU_MASK (0xFFU)
2640#define CRC_DATAHU_DATAHU_SHIFT (0U)
2641#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
2642/*! @} */
2643
2644/*! @name DATAL - CRC_DATAL register */
2645/*! @{ */
2646#define CRC_DATAL_DATAL_MASK (0xFFFFU)
2647#define CRC_DATAL_DATAL_SHIFT (0U)
2648#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
2649/*! @} */
2650
2651/*! @name DATAH - CRC_DATAH register */
2652/*! @{ */
2653#define CRC_DATAH_DATAH_MASK (0xFFFFU)
2654#define CRC_DATAH_DATAH_SHIFT (0U)
2655#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
2656/*! @} */
2657
2658/*! @name DATA - CRC Data register */
2659/*! @{ */
2660#define CRC_DATA_LL_MASK (0xFFU)
2661#define CRC_DATA_LL_SHIFT (0U)
2662#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
2663#define CRC_DATA_LU_MASK (0xFF00U)
2664#define CRC_DATA_LU_SHIFT (8U)
2665#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
2666#define CRC_DATA_HL_MASK (0xFF0000U)
2667#define CRC_DATA_HL_SHIFT (16U)
2668#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
2669#define CRC_DATA_HU_MASK (0xFF000000U)
2670#define CRC_DATA_HU_SHIFT (24U)
2671#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
2672/*! @} */
2673
2674/*! @name GPOLYLL - CRC_GPOLYLL register */
2675/*! @{ */
2676#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
2677#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
2678#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
2679/*! @} */
2680
2681/*! @name GPOLYLU - CRC_GPOLYLU register */
2682/*! @{ */
2683#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
2684#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
2685#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
2686/*! @} */
2687
2688/*! @name GPOLYHL - CRC_GPOLYHL register */
2689/*! @{ */
2690#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
2691#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
2692#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
2693/*! @} */
2694
2695/*! @name GPOLYHU - CRC_GPOLYHU register */
2696/*! @{ */
2697#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
2698#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
2699#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
2700/*! @} */
2701
2702/*! @name GPOLYL - CRC_GPOLYL register */
2703/*! @{ */
2704#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
2705#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
2706#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
2707/*! @} */
2708
2709/*! @name GPOLYH - CRC_GPOLYH register */
2710/*! @{ */
2711#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
2712#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
2713#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
2714/*! @} */
2715
2716/*! @name GPOLY - CRC Polynomial register */
2717/*! @{ */
2718#define CRC_GPOLY_LOW_MASK (0xFFFFU)
2719#define CRC_GPOLY_LOW_SHIFT (0U)
2720#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
2721#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
2722#define CRC_GPOLY_HIGH_SHIFT (16U)
2723#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
2724/*! @} */
2725
2726/*! @name CTRLHU - CRC_CTRLHU register */
2727/*! @{ */
2728#define CRC_CTRLHU_TCRC_MASK (0x1U)
2729#define CRC_CTRLHU_TCRC_SHIFT (0U)
2730/*! TCRC
2731 * 0b0..16-bit CRC protocol.
2732 * 0b1..32-bit CRC protocol.
2733 */
2734#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
2735#define CRC_CTRLHU_WAS_MASK (0x2U)
2736#define CRC_CTRLHU_WAS_SHIFT (1U)
2737/*! WAS
2738 * 0b0..Writes to the CRC data register are data values.
2739 * 0b1..Writes to the CRC data register are seed values.
2740 */
2741#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
2742#define CRC_CTRLHU_FXOR_MASK (0x4U)
2743#define CRC_CTRLHU_FXOR_SHIFT (2U)
2744/*! FXOR
2745 * 0b0..No XOR on reading.
2746 * 0b1..Invert or complement the read value of the CRC Data register.
2747 */
2748#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
2749#define CRC_CTRLHU_TOTR_MASK (0x30U)
2750#define CRC_CTRLHU_TOTR_SHIFT (4U)
2751/*! TOTR
2752 * 0b00..No transposition.
2753 * 0b01..Bits in bytes are transposed; bytes are not transposed.
2754 * 0b10..Both bits in bytes and bytes are transposed.
2755 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
2756 */
2757#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
2758#define CRC_CTRLHU_TOT_MASK (0xC0U)
2759#define CRC_CTRLHU_TOT_SHIFT (6U)
2760/*! TOT
2761 * 0b00..No transposition.
2762 * 0b01..Bits in bytes are transposed; bytes are not transposed.
2763 * 0b10..Both bits in bytes and bytes are transposed.
2764 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
2765 */
2766#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
2767/*! @} */
2768
2769/*! @name CTRL - CRC Control register */
2770/*! @{ */
2771#define CRC_CTRL_TCRC_MASK (0x1000000U)
2772#define CRC_CTRL_TCRC_SHIFT (24U)
2773/*! TCRC - TCRC
2774 * 0b0..16-bit CRC protocol.
2775 * 0b1..32-bit CRC protocol.
2776 */
2777#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
2778#define CRC_CTRL_WAS_MASK (0x2000000U)
2779#define CRC_CTRL_WAS_SHIFT (25U)
2780/*! WAS - Write CRC Data Register As Seed
2781 * 0b0..Writes to the CRC data register are data values.
2782 * 0b1..Writes to the CRC data register are seed values.
2783 */
2784#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
2785#define CRC_CTRL_FXOR_MASK (0x4000000U)
2786#define CRC_CTRL_FXOR_SHIFT (26U)
2787/*! FXOR - Complement Read Of CRC Data Register
2788 * 0b0..No XOR on reading.
2789 * 0b1..Invert or complement the read value of the CRC Data register.
2790 */
2791#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
2792#define CRC_CTRL_TOTR_MASK (0x30000000U)
2793#define CRC_CTRL_TOTR_SHIFT (28U)
2794/*! TOTR - Type Of Transpose For Read
2795 * 0b00..No transposition.
2796 * 0b01..Bits in bytes are transposed; bytes are not transposed.
2797 * 0b10..Both bits in bytes and bytes are transposed.
2798 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
2799 */
2800#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
2801#define CRC_CTRL_TOT_MASK (0xC0000000U)
2802#define CRC_CTRL_TOT_SHIFT (30U)
2803/*! TOT - Type Of Transpose For Writes
2804 * 0b00..No transposition.
2805 * 0b01..Bits in bytes are transposed; bytes are not transposed.
2806 * 0b10..Both bits in bytes and bytes are transposed.
2807 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
2808 */
2809#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
2810/*! @} */
2811
2812
2813/*!
2814 * @}
2815 */ /* end of group CRC_Register_Masks */
2816
2817
2818/* CRC - Peripheral instance base addresses */
2819/** Peripheral CRC base address */
2820#define CRC_BASE (0x4002F000u)
2821/** Peripheral CRC base pointer */
2822#define CRC0 ((CRC_Type *)CRC_BASE)
2823/** Array initializer of CRC peripheral base addresses */
2824#define CRC_BASE_ADDRS { CRC_BASE }
2825/** Array initializer of CRC peripheral base pointers */
2826#define CRC_BASE_PTRS { CRC0 }
2827
2828/*!
2829 * @}
2830 */ /* end of group CRC_Peripheral_Access_Layer */
2831
2832
2833/* ----------------------------------------------------------------------------
2834 -- DMA Peripheral Access Layer
2835 ---------------------------------------------------------------------------- */
2836
2837/*!
2838 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
2839 * @{
2840 */
2841
2842/** DMA - Register Layout Typedef */
2843typedef struct {
2844 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
2845 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
2846 uint8_t RESERVED_0[4];
2847 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
2848 uint8_t RESERVED_1[4];
2849 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
2850 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
2851 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
2852 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
2853 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
2854 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
2855 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
2856 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
2857 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
2858 uint8_t RESERVED_2[4];
2859 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
2860 uint8_t RESERVED_3[4];
2861 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
2862 uint8_t RESERVED_4[4];
2863 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
2864 uint8_t RESERVED_5[12];
2865 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
2866 uint8_t RESERVED_6[184];
2867 __IO uint8_t DCHPRI3; /**< Channel Priority Register, offset: 0x100 */
2868 __IO uint8_t DCHPRI2; /**< Channel Priority Register, offset: 0x101 */
2869 __IO uint8_t DCHPRI1; /**< Channel Priority Register, offset: 0x102 */
2870 __IO uint8_t DCHPRI0; /**< Channel Priority Register, offset: 0x103 */
2871 __IO uint8_t DCHPRI7; /**< Channel Priority Register, offset: 0x104 */
2872 __IO uint8_t DCHPRI6; /**< Channel Priority Register, offset: 0x105 */
2873 __IO uint8_t DCHPRI5; /**< Channel Priority Register, offset: 0x106 */
2874 __IO uint8_t DCHPRI4; /**< Channel Priority Register, offset: 0x107 */
2875 __IO uint8_t DCHPRI11; /**< Channel Priority Register, offset: 0x108 */
2876 __IO uint8_t DCHPRI10; /**< Channel Priority Register, offset: 0x109 */
2877 __IO uint8_t DCHPRI9; /**< Channel Priority Register, offset: 0x10A */
2878 __IO uint8_t DCHPRI8; /**< Channel Priority Register, offset: 0x10B */
2879 __IO uint8_t DCHPRI15; /**< Channel Priority Register, offset: 0x10C */
2880 __IO uint8_t DCHPRI14; /**< Channel Priority Register, offset: 0x10D */
2881 __IO uint8_t DCHPRI13; /**< Channel Priority Register, offset: 0x10E */
2882 __IO uint8_t DCHPRI12; /**< Channel Priority Register, offset: 0x10F */
2883 uint8_t RESERVED_7[3824];
2884 struct { /* offset: 0x1000, array step: 0x20 */
2885 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
2886 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
2887 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
2888 union { /* offset: 0x1008, array step: 0x20 */
2889 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
2890 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
2891 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
2892 };
2893 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
2894 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
2895 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
2896 union { /* offset: 0x1016, array step: 0x20 */
2897 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
2898 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
2899 };
2900 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
2901 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
2902 union { /* offset: 0x101E, array step: 0x20 */
2903 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
2904 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
2905 };
2906 } TCD[16];
2907} DMA_Type;
2908
2909/* ----------------------------------------------------------------------------
2910 -- DMA Register Masks
2911 ---------------------------------------------------------------------------- */
2912
2913/*!
2914 * @addtogroup DMA_Register_Masks DMA Register Masks
2915 * @{
2916 */
2917
2918/*! @name CR - Control Register */
2919/*! @{ */
2920#define DMA_CR_EDBG_MASK (0x2U)
2921#define DMA_CR_EDBG_SHIFT (1U)
2922/*! EDBG - Enable Debug
2923 * 0b0..When in debug mode, the DMA continues to operate.
2924 * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to
2925 * complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
2926 */
2927#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
2928#define DMA_CR_ERCA_MASK (0x4U)
2929#define DMA_CR_ERCA_SHIFT (2U)
2930/*! ERCA - Enable Round Robin Channel Arbitration
2931 * 0b0..Fixed priority arbitration is used for channel selection .
2932 * 0b1..Round robin arbitration is used for channel selection .
2933 */
2934#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
2935#define DMA_CR_HOE_MASK (0x10U)
2936#define DMA_CR_HOE_SHIFT (4U)
2937/*! HOE - Halt On Error
2938 * 0b0..Normal operation
2939 * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
2940 */
2941#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
2942#define DMA_CR_HALT_MASK (0x20U)
2943#define DMA_CR_HALT_SHIFT (5U)
2944/*! HALT - Halt DMA Operations
2945 * 0b0..Normal operation
2946 * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
2947 */
2948#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
2949#define DMA_CR_CLM_MASK (0x40U)
2950#define DMA_CR_CLM_SHIFT (6U)
2951/*! CLM - Continuous Link Mode
2952 * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again.
2953 * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated
2954 * again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel
2955 * link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the
2956 * next minor loop.
2957 */
2958#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
2959#define DMA_CR_EMLM_MASK (0x80U)
2960#define DMA_CR_EMLM_SHIFT (7U)
2961/*! EMLM - Enable Minor Loop Mapping
2962 * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
2963 * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES
2964 * field. The individual enable fields allow the minor loop offset to be applied to the source address, the
2965 * destination address, or both. The NBYTES field is reduced when either offset is enabled.
2966 */
2967#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
2968#define DMA_CR_ECX_MASK (0x10000U)
2969#define DMA_CR_ECX_SHIFT (16U)
2970/*! ECX - Error Cancel Transfer
2971 * 0b0..Normal operation
2972 * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and
2973 * force the minor loop to finish. The cancel takes effect after the last write of the current read/write
2974 * sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX
2975 * treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an
2976 * optional error interrupt.
2977 */
2978#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
2979#define DMA_CR_CX_MASK (0x20000U)
2980#define DMA_CR_CX_SHIFT (17U)
2981/*! CX - Cancel Transfer
2982 * 0b0..Normal operation
2983 * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The
2984 * cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after
2985 * the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
2986 */
2987#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
2988#define DMA_CR_ACTIVE_MASK (0x80000000U)
2989#define DMA_CR_ACTIVE_SHIFT (31U)
2990/*! ACTIVE - DMA Active Status
2991 * 0b0..eDMA is idle.
2992 * 0b1..eDMA is executing a channel.
2993 */
2994#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
2995/*! @} */
2996
2997/*! @name ES - Error Status Register */
2998/*! @{ */
2999#define DMA_ES_DBE_MASK (0x1U)
3000#define DMA_ES_DBE_SHIFT (0U)
3001/*! DBE - Destination Bus Error
3002 * 0b0..No destination bus error
3003 * 0b1..The last recorded error was a bus error on a destination write
3004 */
3005#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
3006#define DMA_ES_SBE_MASK (0x2U)
3007#define DMA_ES_SBE_SHIFT (1U)
3008/*! SBE - Source Bus Error
3009 * 0b0..No source bus error
3010 * 0b1..The last recorded error was a bus error on a source read
3011 */
3012#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
3013#define DMA_ES_SGE_MASK (0x4U)
3014#define DMA_ES_SGE_SHIFT (2U)
3015/*! SGE - Scatter/Gather Configuration Error
3016 * 0b0..No scatter/gather configuration error
3017 * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is
3018 * checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is
3019 * enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
3020 */
3021#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
3022#define DMA_ES_NCE_MASK (0x8U)
3023#define DMA_ES_NCE_SHIFT (3U)
3024/*! NCE - NBYTES/CITER Configuration Error
3025 * 0b0..No NBYTES/CITER configuration error
3026 * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields.
3027 * TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero,
3028 * or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
3029 */
3030#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
3031#define DMA_ES_DOE_MASK (0x10U)
3032#define DMA_ES_DOE_SHIFT (4U)
3033/*! DOE - Destination Offset Error
3034 * 0b0..No destination offset configuration error
3035 * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
3036 */
3037#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
3038#define DMA_ES_DAE_MASK (0x20U)
3039#define DMA_ES_DAE_SHIFT (5U)
3040/*! DAE - Destination Address Error
3041 * 0b0..No destination address configuration error
3042 * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
3043 */
3044#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
3045#define DMA_ES_SOE_MASK (0x40U)
3046#define DMA_ES_SOE_SHIFT (6U)
3047/*! SOE - Source Offset Error
3048 * 0b0..No source offset configuration error
3049 * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
3050 */
3051#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
3052#define DMA_ES_SAE_MASK (0x80U)
3053#define DMA_ES_SAE_SHIFT (7U)
3054/*! SAE - Source Address Error
3055 * 0b0..No source address configuration error.
3056 * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
3057 */
3058#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
3059#define DMA_ES_ERRCHN_MASK (0xF00U)
3060#define DMA_ES_ERRCHN_SHIFT (8U)
3061#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
3062#define DMA_ES_CPE_MASK (0x4000U)
3063#define DMA_ES_CPE_SHIFT (14U)
3064/*! CPE - Channel Priority Error
3065 * 0b0..No channel priority error
3066 * 0b1..The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique.
3067 */
3068#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
3069#define DMA_ES_ECX_MASK (0x10000U)
3070#define DMA_ES_ECX_SHIFT (16U)
3071/*! ECX - Transfer Canceled
3072 * 0b0..No canceled transfers
3073 * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input
3074 */
3075#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
3076#define DMA_ES_VLD_MASK (0x80000000U)
3077#define DMA_ES_VLD_SHIFT (31U)
3078/*! VLD - VLD
3079 * 0b0..No ERR bits are set.
3080 * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.
3081 */
3082#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
3083/*! @} */
3084
3085/*! @name ERQ - Enable Request Register */
3086/*! @{ */
3087#define DMA_ERQ_ERQ0_MASK (0x1U)
3088#define DMA_ERQ_ERQ0_SHIFT (0U)
3089/*! ERQ0 - Enable DMA Request 0
3090 * 0b0..The DMA request signal for the corresponding channel is disabled
3091 * 0b1..The DMA request signal for the corresponding channel is enabled
3092 */
3093#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
3094#define DMA_ERQ_ERQ1_MASK (0x2U)
3095#define DMA_ERQ_ERQ1_SHIFT (1U)
3096/*! ERQ1 - Enable DMA Request 1
3097 * 0b0..The DMA request signal for the corresponding channel is disabled
3098 * 0b1..The DMA request signal for the corresponding channel is enabled
3099 */
3100#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
3101#define DMA_ERQ_ERQ2_MASK (0x4U)
3102#define DMA_ERQ_ERQ2_SHIFT (2U)
3103/*! ERQ2 - Enable DMA Request 2
3104 * 0b0..The DMA request signal for the corresponding channel is disabled
3105 * 0b1..The DMA request signal for the corresponding channel is enabled
3106 */
3107#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
3108#define DMA_ERQ_ERQ3_MASK (0x8U)
3109#define DMA_ERQ_ERQ3_SHIFT (3U)
3110/*! ERQ3 - Enable DMA Request 3
3111 * 0b0..The DMA request signal for the corresponding channel is disabled
3112 * 0b1..The DMA request signal for the corresponding channel is enabled
3113 */
3114#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
3115#define DMA_ERQ_ERQ4_MASK (0x10U)
3116#define DMA_ERQ_ERQ4_SHIFT (4U)
3117/*! ERQ4 - Enable DMA Request 4
3118 * 0b0..The DMA request signal for the corresponding channel is disabled
3119 * 0b1..The DMA request signal for the corresponding channel is enabled
3120 */
3121#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
3122#define DMA_ERQ_ERQ5_MASK (0x20U)
3123#define DMA_ERQ_ERQ5_SHIFT (5U)
3124/*! ERQ5 - Enable DMA Request 5
3125 * 0b0..The DMA request signal for the corresponding channel is disabled
3126 * 0b1..The DMA request signal for the corresponding channel is enabled
3127 */
3128#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
3129#define DMA_ERQ_ERQ6_MASK (0x40U)
3130#define DMA_ERQ_ERQ6_SHIFT (6U)
3131/*! ERQ6 - Enable DMA Request 6
3132 * 0b0..The DMA request signal for the corresponding channel is disabled
3133 * 0b1..The DMA request signal for the corresponding channel is enabled
3134 */
3135#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
3136#define DMA_ERQ_ERQ7_MASK (0x80U)
3137#define DMA_ERQ_ERQ7_SHIFT (7U)
3138/*! ERQ7 - Enable DMA Request 7
3139 * 0b0..The DMA request signal for the corresponding channel is disabled
3140 * 0b1..The DMA request signal for the corresponding channel is enabled
3141 */
3142#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
3143#define DMA_ERQ_ERQ8_MASK (0x100U)
3144#define DMA_ERQ_ERQ8_SHIFT (8U)
3145/*! ERQ8 - Enable DMA Request 8
3146 * 0b0..The DMA request signal for the corresponding channel is disabled
3147 * 0b1..The DMA request signal for the corresponding channel is enabled
3148 */
3149#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
3150#define DMA_ERQ_ERQ9_MASK (0x200U)
3151#define DMA_ERQ_ERQ9_SHIFT (9U)
3152/*! ERQ9 - Enable DMA Request 9
3153 * 0b0..The DMA request signal for the corresponding channel is disabled
3154 * 0b1..The DMA request signal for the corresponding channel is enabled
3155 */
3156#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
3157#define DMA_ERQ_ERQ10_MASK (0x400U)
3158#define DMA_ERQ_ERQ10_SHIFT (10U)
3159/*! ERQ10 - Enable DMA Request 10
3160 * 0b0..The DMA request signal for the corresponding channel is disabled
3161 * 0b1..The DMA request signal for the corresponding channel is enabled
3162 */
3163#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
3164#define DMA_ERQ_ERQ11_MASK (0x800U)
3165#define DMA_ERQ_ERQ11_SHIFT (11U)
3166/*! ERQ11 - Enable DMA Request 11
3167 * 0b0..The DMA request signal for the corresponding channel is disabled
3168 * 0b1..The DMA request signal for the corresponding channel is enabled
3169 */
3170#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
3171#define DMA_ERQ_ERQ12_MASK (0x1000U)
3172#define DMA_ERQ_ERQ12_SHIFT (12U)
3173/*! ERQ12 - Enable DMA Request 12
3174 * 0b0..The DMA request signal for the corresponding channel is disabled
3175 * 0b1..The DMA request signal for the corresponding channel is enabled
3176 */
3177#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
3178#define DMA_ERQ_ERQ13_MASK (0x2000U)
3179#define DMA_ERQ_ERQ13_SHIFT (13U)
3180/*! ERQ13 - Enable DMA Request 13
3181 * 0b0..The DMA request signal for the corresponding channel is disabled
3182 * 0b1..The DMA request signal for the corresponding channel is enabled
3183 */
3184#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
3185#define DMA_ERQ_ERQ14_MASK (0x4000U)
3186#define DMA_ERQ_ERQ14_SHIFT (14U)
3187/*! ERQ14 - Enable DMA Request 14
3188 * 0b0..The DMA request signal for the corresponding channel is disabled
3189 * 0b1..The DMA request signal for the corresponding channel is enabled
3190 */
3191#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
3192#define DMA_ERQ_ERQ15_MASK (0x8000U)
3193#define DMA_ERQ_ERQ15_SHIFT (15U)
3194/*! ERQ15 - Enable DMA Request 15
3195 * 0b0..The DMA request signal for the corresponding channel is disabled
3196 * 0b1..The DMA request signal for the corresponding channel is enabled
3197 */
3198#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
3199/*! @} */
3200
3201/*! @name EEI - Enable Error Interrupt Register */
3202/*! @{ */
3203#define DMA_EEI_EEI0_MASK (0x1U)
3204#define DMA_EEI_EEI0_SHIFT (0U)
3205/*! EEI0 - Enable Error Interrupt 0
3206 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3207 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3208 */
3209#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
3210#define DMA_EEI_EEI1_MASK (0x2U)
3211#define DMA_EEI_EEI1_SHIFT (1U)
3212/*! EEI1 - Enable Error Interrupt 1
3213 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3214 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3215 */
3216#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
3217#define DMA_EEI_EEI2_MASK (0x4U)
3218#define DMA_EEI_EEI2_SHIFT (2U)
3219/*! EEI2 - Enable Error Interrupt 2
3220 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3221 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3222 */
3223#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
3224#define DMA_EEI_EEI3_MASK (0x8U)
3225#define DMA_EEI_EEI3_SHIFT (3U)
3226/*! EEI3 - Enable Error Interrupt 3
3227 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3228 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3229 */
3230#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
3231#define DMA_EEI_EEI4_MASK (0x10U)
3232#define DMA_EEI_EEI4_SHIFT (4U)
3233/*! EEI4 - Enable Error Interrupt 4
3234 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3235 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3236 */
3237#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
3238#define DMA_EEI_EEI5_MASK (0x20U)
3239#define DMA_EEI_EEI5_SHIFT (5U)
3240/*! EEI5 - Enable Error Interrupt 5
3241 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3242 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3243 */
3244#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
3245#define DMA_EEI_EEI6_MASK (0x40U)
3246#define DMA_EEI_EEI6_SHIFT (6U)
3247/*! EEI6 - Enable Error Interrupt 6
3248 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3249 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3250 */
3251#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
3252#define DMA_EEI_EEI7_MASK (0x80U)
3253#define DMA_EEI_EEI7_SHIFT (7U)
3254/*! EEI7 - Enable Error Interrupt 7
3255 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3256 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3257 */
3258#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
3259#define DMA_EEI_EEI8_MASK (0x100U)
3260#define DMA_EEI_EEI8_SHIFT (8U)
3261/*! EEI8 - Enable Error Interrupt 8
3262 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3263 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3264 */
3265#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
3266#define DMA_EEI_EEI9_MASK (0x200U)
3267#define DMA_EEI_EEI9_SHIFT (9U)
3268/*! EEI9 - Enable Error Interrupt 9
3269 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3270 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3271 */
3272#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
3273#define DMA_EEI_EEI10_MASK (0x400U)
3274#define DMA_EEI_EEI10_SHIFT (10U)
3275/*! EEI10 - Enable Error Interrupt 10
3276 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3277 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3278 */
3279#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
3280#define DMA_EEI_EEI11_MASK (0x800U)
3281#define DMA_EEI_EEI11_SHIFT (11U)
3282/*! EEI11 - Enable Error Interrupt 11
3283 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3284 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3285 */
3286#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
3287#define DMA_EEI_EEI12_MASK (0x1000U)
3288#define DMA_EEI_EEI12_SHIFT (12U)
3289/*! EEI12 - Enable Error Interrupt 12
3290 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3291 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3292 */
3293#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
3294#define DMA_EEI_EEI13_MASK (0x2000U)
3295#define DMA_EEI_EEI13_SHIFT (13U)
3296/*! EEI13 - Enable Error Interrupt 13
3297 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3298 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3299 */
3300#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
3301#define DMA_EEI_EEI14_MASK (0x4000U)
3302#define DMA_EEI_EEI14_SHIFT (14U)
3303/*! EEI14 - Enable Error Interrupt 14
3304 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3305 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3306 */
3307#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
3308#define DMA_EEI_EEI15_MASK (0x8000U)
3309#define DMA_EEI_EEI15_SHIFT (15U)
3310/*! EEI15 - Enable Error Interrupt 15
3311 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3312 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3313 */
3314#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
3315/*! @} */
3316
3317/*! @name CEEI - Clear Enable Error Interrupt Register */
3318/*! @{ */
3319#define DMA_CEEI_CEEI_MASK (0xFU)
3320#define DMA_CEEI_CEEI_SHIFT (0U)
3321#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
3322#define DMA_CEEI_CAEE_MASK (0x40U)
3323#define DMA_CEEI_CAEE_SHIFT (6U)
3324/*! CAEE - Clear All Enable Error Interrupts
3325 * 0b0..Clear only the EEI bit specified in the CEEI field
3326 * 0b1..Clear all bits in EEI
3327 */
3328#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
3329#define DMA_CEEI_NOP_MASK (0x80U)
3330#define DMA_CEEI_NOP_SHIFT (7U)
3331/*! NOP - No Op enable
3332 * 0b0..Normal operation
3333 * 0b1..No operation, ignore the other bits in this register
3334 */
3335#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
3336/*! @} */
3337
3338/*! @name SEEI - Set Enable Error Interrupt Register */
3339/*! @{ */
3340#define DMA_SEEI_SEEI_MASK (0xFU)
3341#define DMA_SEEI_SEEI_SHIFT (0U)
3342#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
3343#define DMA_SEEI_SAEE_MASK (0x40U)
3344#define DMA_SEEI_SAEE_SHIFT (6U)
3345/*! SAEE - Sets All Enable Error Interrupts
3346 * 0b0..Set only the EEI bit specified in the SEEI field.
3347 * 0b1..Sets all bits in EEI
3348 */
3349#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
3350#define DMA_SEEI_NOP_MASK (0x80U)
3351#define DMA_SEEI_NOP_SHIFT (7U)
3352/*! NOP - No Op enable
3353 * 0b0..Normal operation
3354 * 0b1..No operation, ignore the other bits in this register
3355 */
3356#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
3357/*! @} */
3358
3359/*! @name CERQ - Clear Enable Request Register */
3360/*! @{ */
3361#define DMA_CERQ_CERQ_MASK (0xFU)
3362#define DMA_CERQ_CERQ_SHIFT (0U)
3363#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
3364#define DMA_CERQ_CAER_MASK (0x40U)
3365#define DMA_CERQ_CAER_SHIFT (6U)
3366/*! CAER - Clear All Enable Requests
3367 * 0b0..Clear only the ERQ bit specified in the CERQ field
3368 * 0b1..Clear all bits in ERQ
3369 */
3370#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
3371#define DMA_CERQ_NOP_MASK (0x80U)
3372#define DMA_CERQ_NOP_SHIFT (7U)
3373/*! NOP - No Op enable
3374 * 0b0..Normal operation
3375 * 0b1..No operation, ignore the other bits in this register
3376 */
3377#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
3378/*! @} */
3379
3380/*! @name SERQ - Set Enable Request Register */
3381/*! @{ */
3382#define DMA_SERQ_SERQ_MASK (0xFU)
3383#define DMA_SERQ_SERQ_SHIFT (0U)
3384#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
3385#define DMA_SERQ_SAER_MASK (0x40U)
3386#define DMA_SERQ_SAER_SHIFT (6U)
3387/*! SAER - Set All Enable Requests
3388 * 0b0..Set only the ERQ bit specified in the SERQ field
3389 * 0b1..Set all bits in ERQ
3390 */
3391#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
3392#define DMA_SERQ_NOP_MASK (0x80U)
3393#define DMA_SERQ_NOP_SHIFT (7U)
3394/*! NOP - No Op enable
3395 * 0b0..Normal operation
3396 * 0b1..No operation, ignore the other bits in this register
3397 */
3398#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
3399/*! @} */
3400
3401/*! @name CDNE - Clear DONE Status Bit Register */
3402/*! @{ */
3403#define DMA_CDNE_CDNE_MASK (0xFU)
3404#define DMA_CDNE_CDNE_SHIFT (0U)
3405#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
3406#define DMA_CDNE_CADN_MASK (0x40U)
3407#define DMA_CDNE_CADN_SHIFT (6U)
3408/*! CADN - Clears All DONE Bits
3409 * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
3410 * 0b1..Clears all bits in TCDn_CSR[DONE]
3411 */
3412#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
3413#define DMA_CDNE_NOP_MASK (0x80U)
3414#define DMA_CDNE_NOP_SHIFT (7U)
3415/*! NOP - No Op enable
3416 * 0b0..Normal operation
3417 * 0b1..No operation, ignore the other bits in this register
3418 */
3419#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
3420/*! @} */
3421
3422/*! @name SSRT - Set START Bit Register */
3423/*! @{ */
3424#define DMA_SSRT_SSRT_MASK (0xFU)
3425#define DMA_SSRT_SSRT_SHIFT (0U)
3426#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
3427#define DMA_SSRT_SAST_MASK (0x40U)
3428#define DMA_SSRT_SAST_SHIFT (6U)
3429/*! SAST - Set All START Bits (activates all channels)
3430 * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field
3431 * 0b1..Set all bits in TCDn_CSR[START]
3432 */
3433#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
3434#define DMA_SSRT_NOP_MASK (0x80U)
3435#define DMA_SSRT_NOP_SHIFT (7U)
3436/*! NOP - No Op enable
3437 * 0b0..Normal operation
3438 * 0b1..No operation, ignore the other bits in this register
3439 */
3440#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
3441/*! @} */
3442
3443/*! @name CERR - Clear Error Register */
3444/*! @{ */
3445#define DMA_CERR_CERR_MASK (0xFU)
3446#define DMA_CERR_CERR_SHIFT (0U)
3447#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
3448#define DMA_CERR_CAEI_MASK (0x40U)
3449#define DMA_CERR_CAEI_SHIFT (6U)
3450/*! CAEI - Clear All Error Indicators
3451 * 0b0..Clear only the ERR bit specified in the CERR field
3452 * 0b1..Clear all bits in ERR
3453 */
3454#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
3455#define DMA_CERR_NOP_MASK (0x80U)
3456#define DMA_CERR_NOP_SHIFT (7U)
3457/*! NOP - No Op enable
3458 * 0b0..Normal operation
3459 * 0b1..No operation, ignore the other bits in this register
3460 */
3461#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
3462/*! @} */
3463
3464/*! @name CINT - Clear Interrupt Request Register */
3465/*! @{ */
3466#define DMA_CINT_CINT_MASK (0xFU)
3467#define DMA_CINT_CINT_SHIFT (0U)
3468#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
3469#define DMA_CINT_CAIR_MASK (0x40U)
3470#define DMA_CINT_CAIR_SHIFT (6U)
3471/*! CAIR - Clear All Interrupt Requests
3472 * 0b0..Clear only the INT bit specified in the CINT field
3473 * 0b1..Clear all bits in INT
3474 */
3475#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
3476#define DMA_CINT_NOP_MASK (0x80U)
3477#define DMA_CINT_NOP_SHIFT (7U)
3478/*! NOP - No Op enable
3479 * 0b0..Normal operation
3480 * 0b1..No operation, ignore the other bits in this register
3481 */
3482#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
3483/*! @} */
3484
3485/*! @name INT - Interrupt Request Register */
3486/*! @{ */
3487#define DMA_INT_INT0_MASK (0x1U)
3488#define DMA_INT_INT0_SHIFT (0U)
3489/*! INT0 - Interrupt Request 0
3490 * 0b0..The interrupt request for corresponding channel is cleared
3491 * 0b1..The interrupt request for corresponding channel is active
3492 */
3493#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
3494#define DMA_INT_INT1_MASK (0x2U)
3495#define DMA_INT_INT1_SHIFT (1U)
3496/*! INT1 - Interrupt Request 1
3497 * 0b0..The interrupt request for corresponding channel is cleared
3498 * 0b1..The interrupt request for corresponding channel is active
3499 */
3500#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
3501#define DMA_INT_INT2_MASK (0x4U)
3502#define DMA_INT_INT2_SHIFT (2U)
3503/*! INT2 - Interrupt Request 2
3504 * 0b0..The interrupt request for corresponding channel is cleared
3505 * 0b1..The interrupt request for corresponding channel is active
3506 */
3507#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
3508#define DMA_INT_INT3_MASK (0x8U)
3509#define DMA_INT_INT3_SHIFT (3U)
3510/*! INT3 - Interrupt Request 3
3511 * 0b0..The interrupt request for corresponding channel is cleared
3512 * 0b1..The interrupt request for corresponding channel is active
3513 */
3514#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
3515#define DMA_INT_INT4_MASK (0x10U)
3516#define DMA_INT_INT4_SHIFT (4U)
3517/*! INT4 - Interrupt Request 4
3518 * 0b0..The interrupt request for corresponding channel is cleared
3519 * 0b1..The interrupt request for corresponding channel is active
3520 */
3521#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
3522#define DMA_INT_INT5_MASK (0x20U)
3523#define DMA_INT_INT5_SHIFT (5U)
3524/*! INT5 - Interrupt Request 5
3525 * 0b0..The interrupt request for corresponding channel is cleared
3526 * 0b1..The interrupt request for corresponding channel is active
3527 */
3528#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
3529#define DMA_INT_INT6_MASK (0x40U)
3530#define DMA_INT_INT6_SHIFT (6U)
3531/*! INT6 - Interrupt Request 6
3532 * 0b0..The interrupt request for corresponding channel is cleared
3533 * 0b1..The interrupt request for corresponding channel is active
3534 */
3535#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
3536#define DMA_INT_INT7_MASK (0x80U)
3537#define DMA_INT_INT7_SHIFT (7U)
3538/*! INT7 - Interrupt Request 7
3539 * 0b0..The interrupt request for corresponding channel is cleared
3540 * 0b1..The interrupt request for corresponding channel is active
3541 */
3542#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
3543#define DMA_INT_INT8_MASK (0x100U)
3544#define DMA_INT_INT8_SHIFT (8U)
3545/*! INT8 - Interrupt Request 8
3546 * 0b0..The interrupt request for corresponding channel is cleared
3547 * 0b1..The interrupt request for corresponding channel is active
3548 */
3549#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
3550#define DMA_INT_INT9_MASK (0x200U)
3551#define DMA_INT_INT9_SHIFT (9U)
3552/*! INT9 - Interrupt Request 9
3553 * 0b0..The interrupt request for corresponding channel is cleared
3554 * 0b1..The interrupt request for corresponding channel is active
3555 */
3556#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
3557#define DMA_INT_INT10_MASK (0x400U)
3558#define DMA_INT_INT10_SHIFT (10U)
3559/*! INT10 - Interrupt Request 10
3560 * 0b0..The interrupt request for corresponding channel is cleared
3561 * 0b1..The interrupt request for corresponding channel is active
3562 */
3563#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
3564#define DMA_INT_INT11_MASK (0x800U)
3565#define DMA_INT_INT11_SHIFT (11U)
3566/*! INT11 - Interrupt Request 11
3567 * 0b0..The interrupt request for corresponding channel is cleared
3568 * 0b1..The interrupt request for corresponding channel is active
3569 */
3570#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
3571#define DMA_INT_INT12_MASK (0x1000U)
3572#define DMA_INT_INT12_SHIFT (12U)
3573/*! INT12 - Interrupt Request 12
3574 * 0b0..The interrupt request for corresponding channel is cleared
3575 * 0b1..The interrupt request for corresponding channel is active
3576 */
3577#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
3578#define DMA_INT_INT13_MASK (0x2000U)
3579#define DMA_INT_INT13_SHIFT (13U)
3580/*! INT13 - Interrupt Request 13
3581 * 0b0..The interrupt request for corresponding channel is cleared
3582 * 0b1..The interrupt request for corresponding channel is active
3583 */
3584#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
3585#define DMA_INT_INT14_MASK (0x4000U)
3586#define DMA_INT_INT14_SHIFT (14U)
3587/*! INT14 - Interrupt Request 14
3588 * 0b0..The interrupt request for corresponding channel is cleared
3589 * 0b1..The interrupt request for corresponding channel is active
3590 */
3591#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
3592#define DMA_INT_INT15_MASK (0x8000U)
3593#define DMA_INT_INT15_SHIFT (15U)
3594/*! INT15 - Interrupt Request 15
3595 * 0b0..The interrupt request for corresponding channel is cleared
3596 * 0b1..The interrupt request for corresponding channel is active
3597 */
3598#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
3599/*! @} */
3600
3601/*! @name ERR - Error Register */
3602/*! @{ */
3603#define DMA_ERR_ERR0_MASK (0x1U)
3604#define DMA_ERR_ERR0_SHIFT (0U)
3605/*! ERR0 - Error In Channel 0
3606 * 0b0..An error in this channel has not occurred
3607 * 0b1..An error in this channel has occurred
3608 */
3609#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
3610#define DMA_ERR_ERR1_MASK (0x2U)
3611#define DMA_ERR_ERR1_SHIFT (1U)
3612/*! ERR1 - Error In Channel 1
3613 * 0b0..An error in this channel has not occurred
3614 * 0b1..An error in this channel has occurred
3615 */
3616#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
3617#define DMA_ERR_ERR2_MASK (0x4U)
3618#define DMA_ERR_ERR2_SHIFT (2U)
3619/*! ERR2 - Error In Channel 2
3620 * 0b0..An error in this channel has not occurred
3621 * 0b1..An error in this channel has occurred
3622 */
3623#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
3624#define DMA_ERR_ERR3_MASK (0x8U)
3625#define DMA_ERR_ERR3_SHIFT (3U)
3626/*! ERR3 - Error In Channel 3
3627 * 0b0..An error in this channel has not occurred
3628 * 0b1..An error in this channel has occurred
3629 */
3630#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
3631#define DMA_ERR_ERR4_MASK (0x10U)
3632#define DMA_ERR_ERR4_SHIFT (4U)
3633/*! ERR4 - Error In Channel 4
3634 * 0b0..An error in this channel has not occurred
3635 * 0b1..An error in this channel has occurred
3636 */
3637#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
3638#define DMA_ERR_ERR5_MASK (0x20U)
3639#define DMA_ERR_ERR5_SHIFT (5U)
3640/*! ERR5 - Error In Channel 5
3641 * 0b0..An error in this channel has not occurred
3642 * 0b1..An error in this channel has occurred
3643 */
3644#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
3645#define DMA_ERR_ERR6_MASK (0x40U)
3646#define DMA_ERR_ERR6_SHIFT (6U)
3647/*! ERR6 - Error In Channel 6
3648 * 0b0..An error in this channel has not occurred
3649 * 0b1..An error in this channel has occurred
3650 */
3651#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
3652#define DMA_ERR_ERR7_MASK (0x80U)
3653#define DMA_ERR_ERR7_SHIFT (7U)
3654/*! ERR7 - Error In Channel 7
3655 * 0b0..An error in this channel has not occurred
3656 * 0b1..An error in this channel has occurred
3657 */
3658#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
3659#define DMA_ERR_ERR8_MASK (0x100U)
3660#define DMA_ERR_ERR8_SHIFT (8U)
3661/*! ERR8 - Error In Channel 8
3662 * 0b0..An error in this channel has not occurred
3663 * 0b1..An error in this channel has occurred
3664 */
3665#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
3666#define DMA_ERR_ERR9_MASK (0x200U)
3667#define DMA_ERR_ERR9_SHIFT (9U)
3668/*! ERR9 - Error In Channel 9
3669 * 0b0..An error in this channel has not occurred
3670 * 0b1..An error in this channel has occurred
3671 */
3672#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
3673#define DMA_ERR_ERR10_MASK (0x400U)
3674#define DMA_ERR_ERR10_SHIFT (10U)
3675/*! ERR10 - Error In Channel 10
3676 * 0b0..An error in this channel has not occurred
3677 * 0b1..An error in this channel has occurred
3678 */
3679#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
3680#define DMA_ERR_ERR11_MASK (0x800U)
3681#define DMA_ERR_ERR11_SHIFT (11U)
3682/*! ERR11 - Error In Channel 11
3683 * 0b0..An error in this channel has not occurred
3684 * 0b1..An error in this channel has occurred
3685 */
3686#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
3687#define DMA_ERR_ERR12_MASK (0x1000U)
3688#define DMA_ERR_ERR12_SHIFT (12U)
3689/*! ERR12 - Error In Channel 12
3690 * 0b0..An error in this channel has not occurred
3691 * 0b1..An error in this channel has occurred
3692 */
3693#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
3694#define DMA_ERR_ERR13_MASK (0x2000U)
3695#define DMA_ERR_ERR13_SHIFT (13U)
3696/*! ERR13 - Error In Channel 13
3697 * 0b0..An error in this channel has not occurred
3698 * 0b1..An error in this channel has occurred
3699 */
3700#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
3701#define DMA_ERR_ERR14_MASK (0x4000U)
3702#define DMA_ERR_ERR14_SHIFT (14U)
3703/*! ERR14 - Error In Channel 14
3704 * 0b0..An error in this channel has not occurred
3705 * 0b1..An error in this channel has occurred
3706 */
3707#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
3708#define DMA_ERR_ERR15_MASK (0x8000U)
3709#define DMA_ERR_ERR15_SHIFT (15U)
3710/*! ERR15 - Error In Channel 15
3711 * 0b0..An error in this channel has not occurred
3712 * 0b1..An error in this channel has occurred
3713 */
3714#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
3715/*! @} */
3716
3717/*! @name HRS - Hardware Request Status Register */
3718/*! @{ */
3719#define DMA_HRS_HRS0_MASK (0x1U)
3720#define DMA_HRS_HRS0_SHIFT (0U)
3721/*! HRS0 - Hardware Request Status Channel 0
3722 * 0b0..A hardware service request for channel 0 is not present
3723 * 0b1..A hardware service request for channel 0 is present
3724 */
3725#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
3726#define DMA_HRS_HRS1_MASK (0x2U)
3727#define DMA_HRS_HRS1_SHIFT (1U)
3728/*! HRS1 - Hardware Request Status Channel 1
3729 * 0b0..A hardware service request for channel 1 is not present
3730 * 0b1..A hardware service request for channel 1 is present
3731 */
3732#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
3733#define DMA_HRS_HRS2_MASK (0x4U)
3734#define DMA_HRS_HRS2_SHIFT (2U)
3735/*! HRS2 - Hardware Request Status Channel 2
3736 * 0b0..A hardware service request for channel 2 is not present
3737 * 0b1..A hardware service request for channel 2 is present
3738 */
3739#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
3740#define DMA_HRS_HRS3_MASK (0x8U)
3741#define DMA_HRS_HRS3_SHIFT (3U)
3742/*! HRS3 - Hardware Request Status Channel 3
3743 * 0b0..A hardware service request for channel 3 is not present
3744 * 0b1..A hardware service request for channel 3 is present
3745 */
3746#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
3747#define DMA_HRS_HRS4_MASK (0x10U)
3748#define DMA_HRS_HRS4_SHIFT (4U)
3749/*! HRS4 - Hardware Request Status Channel 4
3750 * 0b0..A hardware service request for channel 4 is not present
3751 * 0b1..A hardware service request for channel 4 is present
3752 */
3753#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
3754#define DMA_HRS_HRS5_MASK (0x20U)
3755#define DMA_HRS_HRS5_SHIFT (5U)
3756/*! HRS5 - Hardware Request Status Channel 5
3757 * 0b0..A hardware service request for channel 5 is not present
3758 * 0b1..A hardware service request for channel 5 is present
3759 */
3760#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
3761#define DMA_HRS_HRS6_MASK (0x40U)
3762#define DMA_HRS_HRS6_SHIFT (6U)
3763/*! HRS6 - Hardware Request Status Channel 6
3764 * 0b0..A hardware service request for channel 6 is not present
3765 * 0b1..A hardware service request for channel 6 is present
3766 */
3767#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
3768#define DMA_HRS_HRS7_MASK (0x80U)
3769#define DMA_HRS_HRS7_SHIFT (7U)
3770/*! HRS7 - Hardware Request Status Channel 7
3771 * 0b0..A hardware service request for channel 7 is not present
3772 * 0b1..A hardware service request for channel 7 is present
3773 */
3774#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
3775#define DMA_HRS_HRS8_MASK (0x100U)
3776#define DMA_HRS_HRS8_SHIFT (8U)
3777/*! HRS8 - Hardware Request Status Channel 8
3778 * 0b0..A hardware service request for channel 8 is not present
3779 * 0b1..A hardware service request for channel 8 is present
3780 */
3781#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
3782#define DMA_HRS_HRS9_MASK (0x200U)
3783#define DMA_HRS_HRS9_SHIFT (9U)
3784/*! HRS9 - Hardware Request Status Channel 9
3785 * 0b0..A hardware service request for channel 9 is not present
3786 * 0b1..A hardware service request for channel 9 is present
3787 */
3788#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
3789#define DMA_HRS_HRS10_MASK (0x400U)
3790#define DMA_HRS_HRS10_SHIFT (10U)
3791/*! HRS10 - Hardware Request Status Channel 10
3792 * 0b0..A hardware service request for channel 10 is not present
3793 * 0b1..A hardware service request for channel 10 is present
3794 */
3795#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
3796#define DMA_HRS_HRS11_MASK (0x800U)
3797#define DMA_HRS_HRS11_SHIFT (11U)
3798/*! HRS11 - Hardware Request Status Channel 11
3799 * 0b0..A hardware service request for channel 11 is not present
3800 * 0b1..A hardware service request for channel 11 is present
3801 */
3802#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
3803#define DMA_HRS_HRS12_MASK (0x1000U)
3804#define DMA_HRS_HRS12_SHIFT (12U)
3805/*! HRS12 - Hardware Request Status Channel 12
3806 * 0b0..A hardware service request for channel 12 is not present
3807 * 0b1..A hardware service request for channel 12 is present
3808 */
3809#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
3810#define DMA_HRS_HRS13_MASK (0x2000U)
3811#define DMA_HRS_HRS13_SHIFT (13U)
3812/*! HRS13 - Hardware Request Status Channel 13
3813 * 0b0..A hardware service request for channel 13 is not present
3814 * 0b1..A hardware service request for channel 13 is present
3815 */
3816#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
3817#define DMA_HRS_HRS14_MASK (0x4000U)
3818#define DMA_HRS_HRS14_SHIFT (14U)
3819/*! HRS14 - Hardware Request Status Channel 14
3820 * 0b0..A hardware service request for channel 14 is not present
3821 * 0b1..A hardware service request for channel 14 is present
3822 */
3823#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
3824#define DMA_HRS_HRS15_MASK (0x8000U)
3825#define DMA_HRS_HRS15_SHIFT (15U)
3826/*! HRS15 - Hardware Request Status Channel 15
3827 * 0b0..A hardware service request for channel 15 is not present
3828 * 0b1..A hardware service request for channel 15 is present
3829 */
3830#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
3831/*! @} */
3832
3833/*! @name EARS - Enable Asynchronous Request in Stop Register */
3834/*! @{ */
3835#define DMA_EARS_EDREQ_0_MASK (0x1U)
3836#define DMA_EARS_EDREQ_0_SHIFT (0U)
3837/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0.
3838 * 0b0..Disable asynchronous DMA request for channel 0.
3839 * 0b1..Enable asynchronous DMA request for channel 0.
3840 */
3841#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
3842#define DMA_EARS_EDREQ_1_MASK (0x2U)
3843#define DMA_EARS_EDREQ_1_SHIFT (1U)
3844/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1.
3845 * 0b0..Disable asynchronous DMA request for channel 1
3846 * 0b1..Enable asynchronous DMA request for channel 1.
3847 */
3848#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
3849#define DMA_EARS_EDREQ_2_MASK (0x4U)
3850#define DMA_EARS_EDREQ_2_SHIFT (2U)
3851/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2.
3852 * 0b0..Disable asynchronous DMA request for channel 2.
3853 * 0b1..Enable asynchronous DMA request for channel 2.
3854 */
3855#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
3856#define DMA_EARS_EDREQ_3_MASK (0x8U)
3857#define DMA_EARS_EDREQ_3_SHIFT (3U)
3858/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3.
3859 * 0b0..Disable asynchronous DMA request for channel 3.
3860 * 0b1..Enable asynchronous DMA request for channel 3.
3861 */
3862#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
3863#define DMA_EARS_EDREQ_4_MASK (0x10U)
3864#define DMA_EARS_EDREQ_4_SHIFT (4U)
3865/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4
3866 * 0b0..Disable asynchronous DMA request for channel 4.
3867 * 0b1..Enable asynchronous DMA request for channel 4.
3868 */
3869#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
3870#define DMA_EARS_EDREQ_5_MASK (0x20U)
3871#define DMA_EARS_EDREQ_5_SHIFT (5U)
3872/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5
3873 * 0b0..Disable asynchronous DMA request for channel 5.
3874 * 0b1..Enable asynchronous DMA request for channel 5.
3875 */
3876#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
3877#define DMA_EARS_EDREQ_6_MASK (0x40U)
3878#define DMA_EARS_EDREQ_6_SHIFT (6U)
3879/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6
3880 * 0b0..Disable asynchronous DMA request for channel 6.
3881 * 0b1..Enable asynchronous DMA request for channel 6.
3882 */
3883#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
3884#define DMA_EARS_EDREQ_7_MASK (0x80U)
3885#define DMA_EARS_EDREQ_7_SHIFT (7U)
3886/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7
3887 * 0b0..Disable asynchronous DMA request for channel 7.
3888 * 0b1..Enable asynchronous DMA request for channel 7.
3889 */
3890#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
3891#define DMA_EARS_EDREQ_8_MASK (0x100U)
3892#define DMA_EARS_EDREQ_8_SHIFT (8U)
3893/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8
3894 * 0b0..Disable asynchronous DMA request for channel 8.
3895 * 0b1..Enable asynchronous DMA request for channel 8.
3896 */
3897#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
3898#define DMA_EARS_EDREQ_9_MASK (0x200U)
3899#define DMA_EARS_EDREQ_9_SHIFT (9U)
3900/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9
3901 * 0b0..Disable asynchronous DMA request for channel 9.
3902 * 0b1..Enable asynchronous DMA request for channel 9.
3903 */
3904#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
3905#define DMA_EARS_EDREQ_10_MASK (0x400U)
3906#define DMA_EARS_EDREQ_10_SHIFT (10U)
3907/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10
3908 * 0b0..Disable asynchronous DMA request for channel 10.
3909 * 0b1..Enable asynchronous DMA request for channel 10.
3910 */
3911#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
3912#define DMA_EARS_EDREQ_11_MASK (0x800U)
3913#define DMA_EARS_EDREQ_11_SHIFT (11U)
3914/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11
3915 * 0b0..Disable asynchronous DMA request for channel 11.
3916 * 0b1..Enable asynchronous DMA request for channel 11.
3917 */
3918#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
3919#define DMA_EARS_EDREQ_12_MASK (0x1000U)
3920#define DMA_EARS_EDREQ_12_SHIFT (12U)
3921/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12
3922 * 0b0..Disable asynchronous DMA request for channel 12.
3923 * 0b1..Enable asynchronous DMA request for channel 12.
3924 */
3925#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
3926#define DMA_EARS_EDREQ_13_MASK (0x2000U)
3927#define DMA_EARS_EDREQ_13_SHIFT (13U)
3928/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13
3929 * 0b0..Disable asynchronous DMA request for channel 13.
3930 * 0b1..Enable asynchronous DMA request for channel 13.
3931 */
3932#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
3933#define DMA_EARS_EDREQ_14_MASK (0x4000U)
3934#define DMA_EARS_EDREQ_14_SHIFT (14U)
3935/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14
3936 * 0b0..Disable asynchronous DMA request for channel 14.
3937 * 0b1..Enable asynchronous DMA request for channel 14.
3938 */
3939#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
3940#define DMA_EARS_EDREQ_15_MASK (0x8000U)
3941#define DMA_EARS_EDREQ_15_SHIFT (15U)
3942/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15
3943 * 0b0..Disable asynchronous DMA request for channel 15.
3944 * 0b1..Enable asynchronous DMA request for channel 15.
3945 */
3946#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
3947/*! @} */
3948
3949/*! @name DCHPRI3 - Channel Priority Register */
3950/*! @{ */
3951#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
3952#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
3953#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
3954#define DMA_DCHPRI3_DPA_MASK (0x40U)
3955#define DMA_DCHPRI3_DPA_SHIFT (6U)
3956/*! DPA - Disable Preempt Ability. This field resets to 0.
3957 * 0b0..Channel n can suspend a lower priority channel.
3958 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
3959 */
3960#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
3961#define DMA_DCHPRI3_ECP_MASK (0x80U)
3962#define DMA_DCHPRI3_ECP_SHIFT (7U)
3963/*! ECP - Enable Channel Preemption. This field resets to 0.
3964 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
3965 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
3966 */
3967#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
3968/*! @} */
3969
3970/*! @name DCHPRI2 - Channel Priority Register */
3971/*! @{ */
3972#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
3973#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
3974#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
3975#define DMA_DCHPRI2_DPA_MASK (0x40U)
3976#define DMA_DCHPRI2_DPA_SHIFT (6U)
3977/*! DPA - Disable Preempt Ability. This field resets to 0.
3978 * 0b0..Channel n can suspend a lower priority channel.
3979 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
3980 */
3981#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
3982#define DMA_DCHPRI2_ECP_MASK (0x80U)
3983#define DMA_DCHPRI2_ECP_SHIFT (7U)
3984/*! ECP - Enable Channel Preemption. This field resets to 0.
3985 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
3986 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
3987 */
3988#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
3989/*! @} */
3990
3991/*! @name DCHPRI1 - Channel Priority Register */
3992/*! @{ */
3993#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
3994#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
3995#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
3996#define DMA_DCHPRI1_DPA_MASK (0x40U)
3997#define DMA_DCHPRI1_DPA_SHIFT (6U)
3998/*! DPA - Disable Preempt Ability. This field resets to 0.
3999 * 0b0..Channel n can suspend a lower priority channel.
4000 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4001 */
4002#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
4003#define DMA_DCHPRI1_ECP_MASK (0x80U)
4004#define DMA_DCHPRI1_ECP_SHIFT (7U)
4005/*! ECP - Enable Channel Preemption. This field resets to 0.
4006 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4007 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4008 */
4009#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
4010/*! @} */
4011
4012/*! @name DCHPRI0 - Channel Priority Register */
4013/*! @{ */
4014#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
4015#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
4016#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
4017#define DMA_DCHPRI0_DPA_MASK (0x40U)
4018#define DMA_DCHPRI0_DPA_SHIFT (6U)
4019/*! DPA - Disable Preempt Ability. This field resets to 0.
4020 * 0b0..Channel n can suspend a lower priority channel.
4021 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4022 */
4023#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
4024#define DMA_DCHPRI0_ECP_MASK (0x80U)
4025#define DMA_DCHPRI0_ECP_SHIFT (7U)
4026/*! ECP - Enable Channel Preemption. This field resets to 0.
4027 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4028 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4029 */
4030#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
4031/*! @} */
4032
4033/*! @name DCHPRI7 - Channel Priority Register */
4034/*! @{ */
4035#define DMA_DCHPRI7_CHPRI_MASK (0xFU)
4036#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
4037#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
4038#define DMA_DCHPRI7_DPA_MASK (0x40U)
4039#define DMA_DCHPRI7_DPA_SHIFT (6U)
4040/*! DPA - Disable Preempt Ability. This field resets to 0.
4041 * 0b0..Channel n can suspend a lower priority channel.
4042 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4043 */
4044#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
4045#define DMA_DCHPRI7_ECP_MASK (0x80U)
4046#define DMA_DCHPRI7_ECP_SHIFT (7U)
4047/*! ECP - Enable Channel Preemption. This field resets to 0.
4048 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4049 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4050 */
4051#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
4052/*! @} */
4053
4054/*! @name DCHPRI6 - Channel Priority Register */
4055/*! @{ */
4056#define DMA_DCHPRI6_CHPRI_MASK (0xFU)
4057#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
4058#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
4059#define DMA_DCHPRI6_DPA_MASK (0x40U)
4060#define DMA_DCHPRI6_DPA_SHIFT (6U)
4061/*! DPA - Disable Preempt Ability. This field resets to 0.
4062 * 0b0..Channel n can suspend a lower priority channel.
4063 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4064 */
4065#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
4066#define DMA_DCHPRI6_ECP_MASK (0x80U)
4067#define DMA_DCHPRI6_ECP_SHIFT (7U)
4068/*! ECP - Enable Channel Preemption. This field resets to 0.
4069 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4070 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4071 */
4072#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
4073/*! @} */
4074
4075/*! @name DCHPRI5 - Channel Priority Register */
4076/*! @{ */
4077#define DMA_DCHPRI5_CHPRI_MASK (0xFU)
4078#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
4079#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
4080#define DMA_DCHPRI5_DPA_MASK (0x40U)
4081#define DMA_DCHPRI5_DPA_SHIFT (6U)
4082/*! DPA - Disable Preempt Ability. This field resets to 0.
4083 * 0b0..Channel n can suspend a lower priority channel.
4084 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4085 */
4086#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
4087#define DMA_DCHPRI5_ECP_MASK (0x80U)
4088#define DMA_DCHPRI5_ECP_SHIFT (7U)
4089/*! ECP - Enable Channel Preemption. This field resets to 0.
4090 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4091 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4092 */
4093#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
4094/*! @} */
4095
4096/*! @name DCHPRI4 - Channel Priority Register */
4097/*! @{ */
4098#define DMA_DCHPRI4_CHPRI_MASK (0xFU)
4099#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
4100#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
4101#define DMA_DCHPRI4_DPA_MASK (0x40U)
4102#define DMA_DCHPRI4_DPA_SHIFT (6U)
4103/*! DPA - Disable Preempt Ability. This field resets to 0.
4104 * 0b0..Channel n can suspend a lower priority channel.
4105 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4106 */
4107#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
4108#define DMA_DCHPRI4_ECP_MASK (0x80U)
4109#define DMA_DCHPRI4_ECP_SHIFT (7U)
4110/*! ECP - Enable Channel Preemption. This field resets to 0.
4111 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4112 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4113 */
4114#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
4115/*! @} */
4116
4117/*! @name DCHPRI11 - Channel Priority Register */
4118/*! @{ */
4119#define DMA_DCHPRI11_CHPRI_MASK (0xFU)
4120#define DMA_DCHPRI11_CHPRI_SHIFT (0U)
4121#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
4122#define DMA_DCHPRI11_DPA_MASK (0x40U)
4123#define DMA_DCHPRI11_DPA_SHIFT (6U)
4124/*! DPA - Disable Preempt Ability. This field resets to 0.
4125 * 0b0..Channel n can suspend a lower priority channel.
4126 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4127 */
4128#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
4129#define DMA_DCHPRI11_ECP_MASK (0x80U)
4130#define DMA_DCHPRI11_ECP_SHIFT (7U)
4131/*! ECP - Enable Channel Preemption. This field resets to 0.
4132 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4133 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4134 */
4135#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
4136/*! @} */
4137
4138/*! @name DCHPRI10 - Channel Priority Register */
4139/*! @{ */
4140#define DMA_DCHPRI10_CHPRI_MASK (0xFU)
4141#define DMA_DCHPRI10_CHPRI_SHIFT (0U)
4142#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
4143#define DMA_DCHPRI10_DPA_MASK (0x40U)
4144#define DMA_DCHPRI10_DPA_SHIFT (6U)
4145/*! DPA - Disable Preempt Ability. This field resets to 0.
4146 * 0b0..Channel n can suspend a lower priority channel.
4147 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4148 */
4149#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
4150#define DMA_DCHPRI10_ECP_MASK (0x80U)
4151#define DMA_DCHPRI10_ECP_SHIFT (7U)
4152/*! ECP - Enable Channel Preemption. This field resets to 0.
4153 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4154 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4155 */
4156#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
4157/*! @} */
4158
4159/*! @name DCHPRI9 - Channel Priority Register */
4160/*! @{ */
4161#define DMA_DCHPRI9_CHPRI_MASK (0xFU)
4162#define DMA_DCHPRI9_CHPRI_SHIFT (0U)
4163#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
4164#define DMA_DCHPRI9_DPA_MASK (0x40U)
4165#define DMA_DCHPRI9_DPA_SHIFT (6U)
4166/*! DPA - Disable Preempt Ability. This field resets to 0.
4167 * 0b0..Channel n can suspend a lower priority channel.
4168 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4169 */
4170#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
4171#define DMA_DCHPRI9_ECP_MASK (0x80U)
4172#define DMA_DCHPRI9_ECP_SHIFT (7U)
4173/*! ECP - Enable Channel Preemption. This field resets to 0.
4174 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4175 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4176 */
4177#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
4178/*! @} */
4179
4180/*! @name DCHPRI8 - Channel Priority Register */
4181/*! @{ */
4182#define DMA_DCHPRI8_CHPRI_MASK (0xFU)
4183#define DMA_DCHPRI8_CHPRI_SHIFT (0U)
4184#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
4185#define DMA_DCHPRI8_DPA_MASK (0x40U)
4186#define DMA_DCHPRI8_DPA_SHIFT (6U)
4187/*! DPA - Disable Preempt Ability. This field resets to 0.
4188 * 0b0..Channel n can suspend a lower priority channel.
4189 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4190 */
4191#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
4192#define DMA_DCHPRI8_ECP_MASK (0x80U)
4193#define DMA_DCHPRI8_ECP_SHIFT (7U)
4194/*! ECP - Enable Channel Preemption. This field resets to 0.
4195 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4196 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4197 */
4198#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
4199/*! @} */
4200
4201/*! @name DCHPRI15 - Channel Priority Register */
4202/*! @{ */
4203#define DMA_DCHPRI15_CHPRI_MASK (0xFU)
4204#define DMA_DCHPRI15_CHPRI_SHIFT (0U)
4205#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
4206#define DMA_DCHPRI15_DPA_MASK (0x40U)
4207#define DMA_DCHPRI15_DPA_SHIFT (6U)
4208/*! DPA - Disable Preempt Ability. This field resets to 0.
4209 * 0b0..Channel n can suspend a lower priority channel.
4210 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4211 */
4212#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
4213#define DMA_DCHPRI15_ECP_MASK (0x80U)
4214#define DMA_DCHPRI15_ECP_SHIFT (7U)
4215/*! ECP - Enable Channel Preemption. This field resets to 0.
4216 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4217 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4218 */
4219#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
4220/*! @} */
4221
4222/*! @name DCHPRI14 - Channel Priority Register */
4223/*! @{ */
4224#define DMA_DCHPRI14_CHPRI_MASK (0xFU)
4225#define DMA_DCHPRI14_CHPRI_SHIFT (0U)
4226#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
4227#define DMA_DCHPRI14_DPA_MASK (0x40U)
4228#define DMA_DCHPRI14_DPA_SHIFT (6U)
4229/*! DPA - Disable Preempt Ability. This field resets to 0.
4230 * 0b0..Channel n can suspend a lower priority channel.
4231 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4232 */
4233#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
4234#define DMA_DCHPRI14_ECP_MASK (0x80U)
4235#define DMA_DCHPRI14_ECP_SHIFT (7U)
4236/*! ECP - Enable Channel Preemption. This field resets to 0.
4237 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4238 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4239 */
4240#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
4241/*! @} */
4242
4243/*! @name DCHPRI13 - Channel Priority Register */
4244/*! @{ */
4245#define DMA_DCHPRI13_CHPRI_MASK (0xFU)
4246#define DMA_DCHPRI13_CHPRI_SHIFT (0U)
4247#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
4248#define DMA_DCHPRI13_DPA_MASK (0x40U)
4249#define DMA_DCHPRI13_DPA_SHIFT (6U)
4250/*! DPA - Disable Preempt Ability. This field resets to 0.
4251 * 0b0..Channel n can suspend a lower priority channel.
4252 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4253 */
4254#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
4255#define DMA_DCHPRI13_ECP_MASK (0x80U)
4256#define DMA_DCHPRI13_ECP_SHIFT (7U)
4257/*! ECP - Enable Channel Preemption. This field resets to 0.
4258 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4259 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4260 */
4261#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
4262/*! @} */
4263
4264/*! @name DCHPRI12 - Channel Priority Register */
4265/*! @{ */
4266#define DMA_DCHPRI12_CHPRI_MASK (0xFU)
4267#define DMA_DCHPRI12_CHPRI_SHIFT (0U)
4268#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
4269#define DMA_DCHPRI12_DPA_MASK (0x40U)
4270#define DMA_DCHPRI12_DPA_SHIFT (6U)
4271/*! DPA - Disable Preempt Ability. This field resets to 0.
4272 * 0b0..Channel n can suspend a lower priority channel.
4273 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4274 */
4275#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
4276#define DMA_DCHPRI12_ECP_MASK (0x80U)
4277#define DMA_DCHPRI12_ECP_SHIFT (7U)
4278/*! ECP - Enable Channel Preemption. This field resets to 0.
4279 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4280 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4281 */
4282#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
4283/*! @} */
4284
4285/*! @name SADDR - TCD Source Address */
4286/*! @{ */
4287#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
4288#define DMA_SADDR_SADDR_SHIFT (0U)
4289#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
4290/*! @} */
4291
4292/* The count of DMA_SADDR */
4293#define DMA_SADDR_COUNT (16U)
4294
4295/*! @name SOFF - TCD Signed Source Address Offset */
4296/*! @{ */
4297#define DMA_SOFF_SOFF_MASK (0xFFFFU)
4298#define DMA_SOFF_SOFF_SHIFT (0U)
4299#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
4300/*! @} */
4301
4302/* The count of DMA_SOFF */
4303#define DMA_SOFF_COUNT (16U)
4304
4305/*! @name ATTR - TCD Transfer Attributes */
4306/*! @{ */
4307#define DMA_ATTR_DSIZE_MASK (0x7U)
4308#define DMA_ATTR_DSIZE_SHIFT (0U)
4309#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
4310#define DMA_ATTR_DMOD_MASK (0xF8U)
4311#define DMA_ATTR_DMOD_SHIFT (3U)
4312#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
4313#define DMA_ATTR_SSIZE_MASK (0x700U)
4314#define DMA_ATTR_SSIZE_SHIFT (8U)
4315/*! SSIZE - Source data transfer size
4316 * 0b000..8-bit
4317 * 0b001..16-bit
4318 * 0b010..32-bit
4319 * 0b011..Reserved
4320 * 0b100..16-byte burst
4321 * 0b101..32-byte burst
4322 * 0b110..Reserved
4323 * 0b111..Reserved
4324 */
4325#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
4326#define DMA_ATTR_SMOD_MASK (0xF800U)
4327#define DMA_ATTR_SMOD_SHIFT (11U)
4328/*! SMOD - Source Address Modulo
4329 * 0b00000..Source address modulo feature is disabled
4330 * 0b00001-0b11111..This value defines a specific address range specified to be the value after SADDR + SOFF
4331 * calculation is performed on the original register value. Setting this field provides the ability
4332 * to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the
4333 * queue should start at a 0-modulo-size address and the SMOD field should be set to the
4334 * appropriate value for the queue, freezing the desired number of upper address bits. The value
4335 * programmed into this field specifies the number of lower address bits allowed to change. For a
4336 * circular queue application, the SOFF is typically set to the transfer size to implement
4337 * post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
4338 */
4339#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
4340/*! @} */
4341
4342/* The count of DMA_ATTR */
4343#define DMA_ATTR_COUNT (16U)
4344
4345/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
4346/*! @{ */
4347#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
4348#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
4349#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
4350/*! @} */
4351
4352/* The count of DMA_NBYTES_MLNO */
4353#define DMA_NBYTES_MLNO_COUNT (16U)
4354
4355/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
4356/*! @{ */
4357#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
4358#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
4359#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
4360#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
4361#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
4362/*! DMLOE - Destination Minor Loop Offset enable
4363 * 0b0..The minor loop offset is not applied to the DADDR
4364 * 0b1..The minor loop offset is applied to the DADDR
4365 */
4366#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
4367#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
4368#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
4369/*! SMLOE - Source Minor Loop Offset Enable
4370 * 0b0..The minor loop offset is not applied to the SADDR
4371 * 0b1..The minor loop offset is applied to the SADDR
4372 */
4373#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
4374/*! @} */
4375
4376/* The count of DMA_NBYTES_MLOFFNO */
4377#define DMA_NBYTES_MLOFFNO_COUNT (16U)
4378
4379/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
4380/*! @{ */
4381#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
4382#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
4383#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
4384#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
4385#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
4386#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
4387#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
4388#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
4389/*! DMLOE - Destination Minor Loop Offset enable
4390 * 0b0..The minor loop offset is not applied to the DADDR
4391 * 0b1..The minor loop offset is applied to the DADDR
4392 */
4393#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
4394#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
4395#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
4396/*! SMLOE - Source Minor Loop Offset Enable
4397 * 0b0..The minor loop offset is not applied to the SADDR
4398 * 0b1..The minor loop offset is applied to the SADDR
4399 */
4400#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
4401/*! @} */
4402
4403/* The count of DMA_NBYTES_MLOFFYES */
4404#define DMA_NBYTES_MLOFFYES_COUNT (16U)
4405
4406/*! @name SLAST - TCD Last Source Address Adjustment */
4407/*! @{ */
4408#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
4409#define DMA_SLAST_SLAST_SHIFT (0U)
4410#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
4411/*! @} */
4412
4413/* The count of DMA_SLAST */
4414#define DMA_SLAST_COUNT (16U)
4415
4416/*! @name DADDR - TCD Destination Address */
4417/*! @{ */
4418#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
4419#define DMA_DADDR_DADDR_SHIFT (0U)
4420#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
4421/*! @} */
4422
4423/* The count of DMA_DADDR */
4424#define DMA_DADDR_COUNT (16U)
4425
4426/*! @name DOFF - TCD Signed Destination Address Offset */
4427/*! @{ */
4428#define DMA_DOFF_DOFF_MASK (0xFFFFU)
4429#define DMA_DOFF_DOFF_SHIFT (0U)
4430#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
4431/*! @} */
4432
4433/* The count of DMA_DOFF */
4434#define DMA_DOFF_COUNT (16U)
4435
4436/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
4437/*! @{ */
4438#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
4439#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
4440#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
4441#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
4442#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
4443/*! ELINK - Enable channel-to-channel linking on minor-loop complete
4444 * 0b0..The channel-to-channel linking is disabled
4445 * 0b1..The channel-to-channel linking is enabled
4446 */
4447#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
4448/*! @} */
4449
4450/* The count of DMA_CITER_ELINKNO */
4451#define DMA_CITER_ELINKNO_COUNT (16U)
4452
4453/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
4454/*! @{ */
4455#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
4456#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
4457#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
4458#define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U)
4459#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
4460#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
4461#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
4462#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
4463/*! ELINK - Enable channel-to-channel linking on minor-loop complete
4464 * 0b0..The channel-to-channel linking is disabled
4465 * 0b1..The channel-to-channel linking is enabled
4466 */
4467#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
4468/*! @} */
4469
4470/* The count of DMA_CITER_ELINKYES */
4471#define DMA_CITER_ELINKYES_COUNT (16U)
4472
4473/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
4474/*! @{ */
4475#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
4476#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
4477#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
4478/*! @} */
4479
4480/* The count of DMA_DLAST_SGA */
4481#define DMA_DLAST_SGA_COUNT (16U)
4482
4483/*! @name CSR - TCD Control and Status */
4484/*! @{ */
4485#define DMA_CSR_START_MASK (0x1U)
4486#define DMA_CSR_START_SHIFT (0U)
4487/*! START - Channel Start
4488 * 0b0..The channel is not explicitly started.
4489 * 0b1..The channel is explicitly started via a software initiated service request.
4490 */
4491#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
4492#define DMA_CSR_INTMAJOR_MASK (0x2U)
4493#define DMA_CSR_INTMAJOR_SHIFT (1U)
4494/*! INTMAJOR - Enable an interrupt when major iteration count completes.
4495 * 0b0..The end-of-major loop interrupt is disabled.
4496 * 0b1..The end-of-major loop interrupt is enabled.
4497 */
4498#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
4499#define DMA_CSR_INTHALF_MASK (0x4U)
4500#define DMA_CSR_INTHALF_SHIFT (2U)
4501/*! INTHALF - Enable an interrupt when major counter is half complete.
4502 * 0b0..The half-point interrupt is disabled.
4503 * 0b1..The half-point interrupt is enabled.
4504 */
4505#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
4506#define DMA_CSR_DREQ_MASK (0x8U)
4507#define DMA_CSR_DREQ_SHIFT (3U)
4508/*! DREQ - Disable Request
4509 * 0b0..The channel's ERQ bit is not affected.
4510 * 0b1..The channel's ERQ bit is cleared when the major loop is complete.
4511 */
4512#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
4513#define DMA_CSR_ESG_MASK (0x10U)
4514#define DMA_CSR_ESG_SHIFT (4U)
4515/*! ESG - Enable Scatter/Gather Processing
4516 * 0b0..The current channel's TCD is normal format.
4517 * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer
4518 * to the next TCD to be loaded into this channel after the major loop completes its execution.
4519 */
4520#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
4521#define DMA_CSR_MAJORELINK_MASK (0x20U)
4522#define DMA_CSR_MAJORELINK_SHIFT (5U)
4523/*! MAJORELINK - Enable channel-to-channel linking on major loop complete
4524 * 0b0..The channel-to-channel linking is disabled.
4525 * 0b1..The channel-to-channel linking is enabled.
4526 */
4527#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
4528#define DMA_CSR_ACTIVE_MASK (0x40U)
4529#define DMA_CSR_ACTIVE_SHIFT (6U)
4530#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
4531#define DMA_CSR_DONE_MASK (0x80U)
4532#define DMA_CSR_DONE_SHIFT (7U)
4533#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
4534#define DMA_CSR_MAJORLINKCH_MASK (0xF00U)
4535#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
4536#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
4537#define DMA_CSR_BWC_MASK (0xC000U)
4538#define DMA_CSR_BWC_SHIFT (14U)
4539/*! BWC - Bandwidth Control
4540 * 0b00..No eDMA engine stalls.
4541 * 0b01..Reserved
4542 * 0b10..eDMA engine stalls for 4 cycles after each R/W.
4543 * 0b11..eDMA engine stalls for 8 cycles after each R/W.
4544 */
4545#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
4546/*! @} */
4547
4548/* The count of DMA_CSR */
4549#define DMA_CSR_COUNT (16U)
4550
4551/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
4552/*! @{ */
4553#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
4554#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
4555#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
4556#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
4557#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
4558/*! ELINK - Enables channel-to-channel linking on minor loop complete
4559 * 0b0..The channel-to-channel linking is disabled
4560 * 0b1..The channel-to-channel linking is enabled
4561 */
4562#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
4563/*! @} */
4564
4565/* The count of DMA_BITER_ELINKNO */
4566#define DMA_BITER_ELINKNO_COUNT (16U)
4567
4568/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
4569/*! @{ */
4570#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
4571#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
4572#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
4573#define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U)
4574#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
4575#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
4576#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
4577#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
4578/*! ELINK - Enables channel-to-channel linking on minor loop complete
4579 * 0b0..The channel-to-channel linking is disabled
4580 * 0b1..The channel-to-channel linking is enabled
4581 */
4582#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
4583/*! @} */
4584
4585/* The count of DMA_BITER_ELINKYES */
4586#define DMA_BITER_ELINKYES_COUNT (16U)
4587
4588
4589/*!
4590 * @}
4591 */ /* end of group DMA_Register_Masks */
4592
4593
4594/* DMA - Peripheral instance base addresses */
4595/** Peripheral DMA0 base address */
4596#define DMA0_BASE (0x40008000u)
4597/** Peripheral DMA0 base pointer */
4598#define DMA0 ((DMA_Type *)DMA0_BASE)
4599/** Array initializer of DMA peripheral base addresses */
4600#define DMA_BASE_ADDRS { DMA0_BASE }
4601/** Array initializer of DMA peripheral base pointers */
4602#define DMA_BASE_PTRS { DMA0 }
4603/** Interrupt vectors for the DMA peripheral type */
4604#define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } }
4605#define DMA_ERROR_IRQS { DMA0_Error_IRQn }
4606
4607/*!
4608 * @}
4609 */ /* end of group DMA_Peripheral_Access_Layer */
4610
4611
4612/* ----------------------------------------------------------------------------
4613 -- DMAMUX Peripheral Access Layer
4614 ---------------------------------------------------------------------------- */
4615
4616/*!
4617 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
4618 * @{
4619 */
4620
4621/** DMAMUX - Register Layout Typedef */
4622typedef struct {
4623 __IO uint32_t CHCFG[16]; /**< Channel 0 Configuration Register..Channel 15 Configuration Register, array offset: 0x0, array step: 0x4 */
4624} DMAMUX_Type;
4625
4626/* ----------------------------------------------------------------------------
4627 -- DMAMUX Register Masks
4628 ---------------------------------------------------------------------------- */
4629
4630/*!
4631 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
4632 * @{
4633 */
4634
4635/*! @name CHCFG - Channel 0 Configuration Register..Channel 15 Configuration Register */
4636/*! @{ */
4637#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
4638#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
4639#define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
4640#define DMAMUX_CHCFG_A_ON_MASK (0x20000000U)
4641#define DMAMUX_CHCFG_A_ON_SHIFT (29U)
4642/*! A_ON - DMA Channel Always Enable
4643 * 0b0..DMA Channel Always ON function is disabled
4644 * 0b1..DMA Channel Always ON function is enabled
4645 */
4646#define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
4647#define DMAMUX_CHCFG_TRIG_MASK (0x40000000U)
4648#define DMAMUX_CHCFG_TRIG_SHIFT (30U)
4649/*! TRIG - DMA Channel Trigger Enable
4650 * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the
4651 * specified source to the DMA channel. (Normal mode)
4652 * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
4653 */
4654#define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
4655#define DMAMUX_CHCFG_ENBL_MASK (0x80000000U)
4656#define DMAMUX_CHCFG_ENBL_SHIFT (31U)
4657/*! ENBL - DMA Mux Channel Enable
4658 * 0b0..DMA Mux channel is disabled
4659 * 0b1..DMA Mux channel is enabled
4660 */
4661#define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
4662/*! @} */
4663
4664/* The count of DMAMUX_CHCFG */
4665#define DMAMUX_CHCFG_COUNT (16U)
4666
4667
4668/*!
4669 * @}
4670 */ /* end of group DMAMUX_Register_Masks */
4671
4672
4673/* DMAMUX - Peripheral instance base addresses */
4674/** Peripheral DMAMUX0 base address */
4675#define DMAMUX0_BASE (0x40021000u)
4676/** Peripheral DMAMUX0 base pointer */
4677#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
4678/** Array initializer of DMAMUX peripheral base addresses */
4679#define DMAMUX_BASE_ADDRS { DMAMUX0_BASE }
4680/** Array initializer of DMAMUX peripheral base pointers */
4681#define DMAMUX_BASE_PTRS { DMAMUX0 }
4682
4683/*!
4684 * @}
4685 */ /* end of group DMAMUX_Peripheral_Access_Layer */
4686
4687
4688/* ----------------------------------------------------------------------------
4689 -- EMVSIM Peripheral Access Layer
4690 ---------------------------------------------------------------------------- */
4691
4692/*!
4693 * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer
4694 * @{
4695 */
4696
4697/** EMVSIM - Register Layout Typedef */
4698typedef struct {
4699 __I uint32_t VER_ID; /**< Version ID Register, offset: 0x0 */
4700 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
4701 __IO uint32_t CLKCFG; /**< Clock Configuration Register, offset: 0x8 */
4702 __IO uint32_t DIVISOR; /**< Baud Rate Divisor Register, offset: 0xC */
4703 __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */
4704 __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */
4705 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */
4706 __IO uint32_t TX_THD; /**< Transmitter Threshold Register, offset: 0x1C */
4707 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */
4708 __IO uint32_t TX_STATUS; /**< Transmitter Status Register, offset: 0x24 */
4709 __IO uint32_t PCSR; /**< Port Control and Status Register, offset: 0x28 */
4710 __I uint32_t RX_BUF; /**< Receive Data Read Buffer, offset: 0x2C */
4711 __O uint32_t TX_BUF; /**< Transmit Data Buffer, offset: 0x30 */
4712 __IO uint32_t TX_GETU; /**< Transmitter Guard ETU Value Register, offset: 0x34 */
4713 __IO uint32_t CWT_VAL; /**< Character Wait Time Value Register, offset: 0x38 */
4714 __IO uint32_t BWT_VAL; /**< Block Wait Time Value Register, offset: 0x3C */
4715 __IO uint32_t BGT_VAL; /**< Block Guard Time Value Register, offset: 0x40 */
4716 __IO uint32_t GPCNT0_VAL; /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */
4717 __IO uint32_t GPCNT1_VAL; /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */
4718} EMVSIM_Type;
4719
4720/* ----------------------------------------------------------------------------
4721 -- EMVSIM Register Masks
4722 ---------------------------------------------------------------------------- */
4723
4724/*!
4725 * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks
4726 * @{
4727 */
4728
4729/*! @name VER_ID - Version ID Register */
4730/*! @{ */
4731#define EMVSIM_VER_ID_VER_MASK (0xFFFFFFFFU)
4732#define EMVSIM_VER_ID_VER_SHIFT (0U)
4733#define EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)
4734/*! @} */
4735
4736/*! @name PARAM - Parameter Register */
4737/*! @{ */
4738#define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK (0xFFU)
4739#define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT (0U)
4740#define EMVSIM_PARAM_RX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
4741#define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK (0xFF00U)
4742#define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT (8U)
4743#define EMVSIM_PARAM_TX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
4744/*! @} */
4745
4746/*! @name CLKCFG - Clock Configuration Register */
4747/*! @{ */
4748#define EMVSIM_CLKCFG_CLK_PRSC_MASK (0xFFU)
4749#define EMVSIM_CLKCFG_CLK_PRSC_SHIFT (0U)
4750/*! CLK_PRSC - Clock Prescaler Value
4751 * 0b00000010..Divide by 2
4752 */
4753#define EMVSIM_CLKCFG_CLK_PRSC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)
4754#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK (0x300U)
4755#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT (8U)
4756/*! GPCNT1_CLK_SEL - General Purpose Counter 1 Clock Select
4757 * 0b00..Disabled / Reset (default)
4758 * 0b01..Card Clock
4759 * 0b10..Receive Clock
4760 * 0b11..ETU Clock (transmit clock)
4761 */
4762#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
4763#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK (0xC00U)
4764#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT (10U)
4765/*! GPCNT0_CLK_SEL - General Purpose Counter 0 Clock Select
4766 * 0b00..Disabled / Reset (default)
4767 * 0b01..Card Clock
4768 * 0b10..Receive Clock
4769 * 0b11..ETU Clock (transmit clock)
4770 */
4771#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)
4772/*! @} */
4773
4774/*! @name DIVISOR - Baud Rate Divisor Register */
4775/*! @{ */
4776#define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK (0x1FFU)
4777#define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT (0U)
4778/*! DIVISOR_VALUE - Divisor (F/D) Value
4779 * 0b000000000-0b000000100..Invalid. As per ISO 7816 specification, minimum value of F/D is 5
4780 * 0b101110100..Divisor value for F = 372 and D = 1 (default)
4781 */
4782#define EMVSIM_DIVISOR_DIVISOR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)
4783/*! @} */
4784
4785/*! @name CTRL - Control Register */
4786/*! @{ */
4787#define EMVSIM_CTRL_IC_MASK (0x1U)
4788#define EMVSIM_CTRL_IC_SHIFT (0U)
4789/*! IC - Inverse Convention
4790 * 0b0..Direction convention transfers enabled (default)
4791 * 0b1..Inverse convention transfers enabled
4792 */
4793#define EMVSIM_CTRL_IC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)
4794#define EMVSIM_CTRL_ICM_MASK (0x2U)
4795#define EMVSIM_CTRL_ICM_SHIFT (1U)
4796/*! ICM - Initial Character Mode
4797 * 0b0..Initial Character Mode disabled
4798 * 0b1..Initial Character Mode enabled (default)
4799 */
4800#define EMVSIM_CTRL_ICM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)
4801#define EMVSIM_CTRL_ANACK_MASK (0x4U)
4802#define EMVSIM_CTRL_ANACK_SHIFT (2U)
4803/*! ANACK - Auto NACK Enable
4804 * 0b0..NACK generation on errors disabled
4805 * 0b1..NACK generation on errors enabled (default)
4806 */
4807#define EMVSIM_CTRL_ANACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)
4808#define EMVSIM_CTRL_ONACK_MASK (0x8U)
4809#define EMVSIM_CTRL_ONACK_SHIFT (3U)
4810/*! ONACK - Overrun NACK Enable
4811 * 0b0..NACK generation on overrun is disabled (default)
4812 * 0b1..NACK generation on overrun is enabled
4813 */
4814#define EMVSIM_CTRL_ONACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)
4815#define EMVSIM_CTRL_FLSH_RX_MASK (0x100U)
4816#define EMVSIM_CTRL_FLSH_RX_SHIFT (8U)
4817/*! FLSH_RX - Flush Receiver Bit
4818 * 0b0..EMV SIM Receiver normal operation (default)
4819 * 0b1..EMV SIM Receiver held in Reset
4820 */
4821#define EMVSIM_CTRL_FLSH_RX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)
4822#define EMVSIM_CTRL_FLSH_TX_MASK (0x200U)
4823#define EMVSIM_CTRL_FLSH_TX_SHIFT (9U)
4824/*! FLSH_TX - Flush Transmitter Bit
4825 * 0b0..EMV SIM Transmitter normal operation (default)
4826 * 0b1..EMV SIM Transmitter held in Reset
4827 */
4828#define EMVSIM_CTRL_FLSH_TX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
4829#define EMVSIM_CTRL_SW_RST_MASK (0x400U)
4830#define EMVSIM_CTRL_SW_RST_SHIFT (10U)
4831/*! SW_RST - Software Reset Bit
4832 * 0b0..EMV SIM Normal operation (default)
4833 * 0b1..EMV SIM held in Reset
4834 */
4835#define EMVSIM_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)
4836#define EMVSIM_CTRL_KILL_CLOCKS_MASK (0x800U)
4837#define EMVSIM_CTRL_KILL_CLOCKS_SHIFT (11U)
4838/*! KILL_CLOCKS - Kill all internal clocks
4839 * 0b0..EMV SIM input clock enabled (default)
4840 * 0b1..EMV SIM input clock is disabled
4841 */
4842#define EMVSIM_CTRL_KILL_CLOCKS(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)
4843#define EMVSIM_CTRL_DOZE_EN_MASK (0x1000U)
4844#define EMVSIM_CTRL_DOZE_EN_SHIFT (12U)
4845/*! DOZE_EN - Doze Enable
4846 * 0b0..DOZE instruction will gate all internal EMV SIM clocks as well as the Smart Card clock when the transmit FIFO is empty (default)
4847 * 0b1..DOZE instruction has no effect on EMV SIM module
4848 */
4849#define EMVSIM_CTRL_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)
4850#define EMVSIM_CTRL_STOP_EN_MASK (0x2000U)
4851#define EMVSIM_CTRL_STOP_EN_SHIFT (13U)
4852/*! STOP_EN - STOP Enable
4853 * 0b0..STOP instruction shuts down all EMV SIM clocks (default)
4854 * 0b1..STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card)
4855 */
4856#define EMVSIM_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)
4857#define EMVSIM_CTRL_RCV_EN_MASK (0x10000U)
4858#define EMVSIM_CTRL_RCV_EN_SHIFT (16U)
4859/*! RCV_EN - Receiver Enable
4860 * 0b0..EMV SIM Receiver disabled (default)
4861 * 0b1..EMV SIM Receiver enabled
4862 */
4863#define EMVSIM_CTRL_RCV_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)
4864#define EMVSIM_CTRL_XMT_EN_MASK (0x20000U)
4865#define EMVSIM_CTRL_XMT_EN_SHIFT (17U)
4866/*! XMT_EN - Transmitter Enable
4867 * 0b0..EMV SIM Transmitter disabled (default)
4868 * 0b1..EMV SIM Transmitter enabled
4869 */
4870#define EMVSIM_CTRL_XMT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)
4871#define EMVSIM_CTRL_RCVR_11_MASK (0x40000U)
4872#define EMVSIM_CTRL_RCVR_11_SHIFT (18U)
4873/*! RCVR_11 - Receiver 11 ETU Mode Enable
4874 * 0b0..Receiver configured for 12 ETU operation mode (default)
4875 * 0b1..Receiver configured for 11 ETU operation mode
4876 */
4877#define EMVSIM_CTRL_RCVR_11(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
4878#define EMVSIM_CTRL_RX_DMA_EN_MASK (0x80000U)
4879#define EMVSIM_CTRL_RX_DMA_EN_SHIFT (19U)
4880/*! RX_DMA_EN - Receive DMA Enable
4881 * 0b0..No DMA Read Request asserted for Receiver (default)
4882 * 0b1..DMA Read Request asserted for Receiver
4883 */
4884#define EMVSIM_CTRL_RX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)
4885#define EMVSIM_CTRL_TX_DMA_EN_MASK (0x100000U)
4886#define EMVSIM_CTRL_TX_DMA_EN_SHIFT (20U)
4887/*! TX_DMA_EN - Transmit DMA Enable
4888 * 0b0..No DMA Write Request asserted for Transmitter (default)
4889 * 0b1..DMA Write Request asserted for Transmitter
4890 */
4891#define EMVSIM_CTRL_TX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)
4892#define EMVSIM_CTRL_INV_CRC_VAL_MASK (0x1000000U)
4893#define EMVSIM_CTRL_INV_CRC_VAL_SHIFT (24U)
4894/*! INV_CRC_VAL - Invert bits in the CRC Output Value
4895 * 0b0..Bits in CRC Output value will not be inverted.
4896 * 0b1..Bits in CRC Output value will be inverted. (default)
4897 */
4898#define EMVSIM_CTRL_INV_CRC_VAL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)
4899#define EMVSIM_CTRL_CRC_OUT_FLIP_MASK (0x2000000U)
4900#define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT (25U)
4901/*! CRC_OUT_FLIP - CRC Output Value Bit Reversal or Flip
4902 * 0b0..Bits within the CRC output bytes will not be reversed i.e. 15:0 will remain 15:0 (default)
4903 * 0b1..Bits within the CRC output bytes will be reversed i.e. 15:0 will become {8:15,0:7}
4904 */
4905#define EMVSIM_CTRL_CRC_OUT_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
4906#define EMVSIM_CTRL_CRC_IN_FLIP_MASK (0x4000000U)
4907#define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT (26U)
4908/*! CRC_IN_FLIP - CRC Input Byte's Bit Reversal or Flip Control
4909 * 0b0..Bits in the input byte will not be reversed (i.e. 7:0 will remain 7:0) before the CRC calculation (default)
4910 * 0b1..Bits in the input byte will be reversed (i.e. 7:0 will become 0:7) before CRC calculation
4911 */
4912#define EMVSIM_CTRL_CRC_IN_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)
4913#define EMVSIM_CTRL_CWT_EN_MASK (0x8000000U)
4914#define EMVSIM_CTRL_CWT_EN_SHIFT (27U)
4915/*! CWT_EN - Character Wait Time Counter Enable
4916 * 0b0..Character Wait time Counter is disabled (default)
4917 * 0b1..Character Wait time counter is enabled
4918 */
4919#define EMVSIM_CTRL_CWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)
4920#define EMVSIM_CTRL_LRC_EN_MASK (0x10000000U)
4921#define EMVSIM_CTRL_LRC_EN_SHIFT (28U)
4922/*! LRC_EN - LRC Enable
4923 * 0b0..8-bit Linear Redundancy Checking disabled (default)
4924 * 0b1..8-bit Linear Redundancy Checking enabled
4925 */
4926#define EMVSIM_CTRL_LRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
4927#define EMVSIM_CTRL_CRC_EN_MASK (0x20000000U)
4928#define EMVSIM_CTRL_CRC_EN_SHIFT (29U)
4929/*! CRC_EN - CRC Enable
4930 * 0b0..16-bit Cyclic Redundancy Checking disabled (default)
4931 * 0b1..16-bit Cyclic Redundancy Checking enabled
4932 */
4933#define EMVSIM_CTRL_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)
4934#define EMVSIM_CTRL_XMT_CRC_LRC_MASK (0x40000000U)
4935#define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT (30U)
4936/*! XMT_CRC_LRC - Transmit CRC or LRC Enable
4937 * 0b0..No CRC or LRC value is transmitted (default)
4938 * 0b1..Transmit LRC or CRC info when FIFO empties (whichever is enabled)
4939 */
4940#define EMVSIM_CTRL_XMT_CRC_LRC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)
4941#define EMVSIM_CTRL_BWT_EN_MASK (0x80000000U)
4942#define EMVSIM_CTRL_BWT_EN_SHIFT (31U)
4943/*! BWT_EN - Block Wait Time Counter Enable
4944 * 0b0..Disable BWT, BGT Counters (default)
4945 * 0b1..Enable BWT, BGT Counters
4946 */
4947#define EMVSIM_CTRL_BWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)
4948/*! @} */
4949
4950/*! @name INT_MASK - Interrupt Mask Register */
4951/*! @{ */
4952#define EMVSIM_INT_MASK_RDT_IM_MASK (0x1U)
4953#define EMVSIM_INT_MASK_RDT_IM_SHIFT (0U)
4954/*! RDT_IM - Receive Data Threshold Interrupt Mask
4955 * 0b0..RDTF interrupt enabled
4956 * 0b1..RDTF interrupt masked (default)
4957 */
4958#define EMVSIM_INT_MASK_RDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)
4959#define EMVSIM_INT_MASK_TC_IM_MASK (0x2U)
4960#define EMVSIM_INT_MASK_TC_IM_SHIFT (1U)
4961/*! TC_IM - Transmit Complete Interrupt Mask
4962 * 0b0..TCF interrupt enabled
4963 * 0b1..TCF interrupt masked (default)
4964 */
4965#define EMVSIM_INT_MASK_TC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)
4966#define EMVSIM_INT_MASK_RFO_IM_MASK (0x4U)
4967#define EMVSIM_INT_MASK_RFO_IM_SHIFT (2U)
4968/*! RFO_IM - Receive FIFO Overflow Interrupt Mask
4969 * 0b0..RFO interrupt enabled
4970 * 0b1..RFO interrupt masked (default)
4971 */
4972#define EMVSIM_INT_MASK_RFO_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)
4973#define EMVSIM_INT_MASK_ETC_IM_MASK (0x8U)
4974#define EMVSIM_INT_MASK_ETC_IM_SHIFT (3U)
4975/*! ETC_IM - Early Transmit Complete Interrupt Mask
4976 * 0b0..ETC interrupt enabled
4977 * 0b1..ETC interrupt masked (default)
4978 */
4979#define EMVSIM_INT_MASK_ETC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)
4980#define EMVSIM_INT_MASK_TFE_IM_MASK (0x10U)
4981#define EMVSIM_INT_MASK_TFE_IM_SHIFT (4U)
4982/*! TFE_IM - Transmit FIFO Empty Interrupt Mask
4983 * 0b0..TFE interrupt enabled
4984 * 0b1..TFE interrupt masked (default)
4985 */
4986#define EMVSIM_INT_MASK_TFE_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)
4987#define EMVSIM_INT_MASK_TNACK_IM_MASK (0x20U)
4988#define EMVSIM_INT_MASK_TNACK_IM_SHIFT (5U)
4989/*! TNACK_IM - Transmit NACK Threshold Interrupt Mask
4990 * 0b0..TNTE interrupt enabled
4991 * 0b1..TNTE interrupt masked (default)
4992 */
4993#define EMVSIM_INT_MASK_TNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)
4994#define EMVSIM_INT_MASK_TFF_IM_MASK (0x40U)
4995#define EMVSIM_INT_MASK_TFF_IM_SHIFT (6U)
4996/*! TFF_IM - Transmit FIFO Full Interrupt Mask
4997 * 0b0..TFF interrupt enabled
4998 * 0b1..TFF interrupt masked (default)
4999 */
5000#define EMVSIM_INT_MASK_TFF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)
5001#define EMVSIM_INT_MASK_TDT_IM_MASK (0x80U)
5002#define EMVSIM_INT_MASK_TDT_IM_SHIFT (7U)
5003/*! TDT_IM - Transmit Data Threshold Interrupt Mask
5004 * 0b0..TDTF interrupt enabled
5005 * 0b1..TDTF interrupt masked (default)
5006 */
5007#define EMVSIM_INT_MASK_TDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)
5008#define EMVSIM_INT_MASK_GPCNT0_IM_MASK (0x100U)
5009#define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT (8U)
5010/*! GPCNT0_IM - General Purpose Timer 0 Timeout Interrupt Mask
5011 * 0b0..GPCNT0_TO interrupt enabled
5012 * 0b1..GPCNT0_TO interrupt masked (default)
5013 */
5014#define EMVSIM_INT_MASK_GPCNT0_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)
5015#define EMVSIM_INT_MASK_CWT_ERR_IM_MASK (0x200U)
5016#define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT (9U)
5017/*! CWT_ERR_IM - Character Wait Time Error Interrupt Mask
5018 * 0b0..CWT_ERR interrupt enabled
5019 * 0b1..CWT_ERR interrupt masked (default)
5020 */
5021#define EMVSIM_INT_MASK_CWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
5022#define EMVSIM_INT_MASK_RNACK_IM_MASK (0x400U)
5023#define EMVSIM_INT_MASK_RNACK_IM_SHIFT (10U)
5024/*! RNACK_IM - Receiver NACK Threshold Interrupt Mask
5025 * 0b0..RTE interrupt enabled
5026 * 0b1..RTE interrupt masked (default)
5027 */
5028#define EMVSIM_INT_MASK_RNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)
5029#define EMVSIM_INT_MASK_BWT_ERR_IM_MASK (0x800U)
5030#define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT (11U)
5031/*! BWT_ERR_IM - Block Wait Time Error Interrupt Mask
5032 * 0b0..BWT_ERR interrupt enabled
5033 * 0b1..BWT_ERR interrupt masked (default)
5034 */
5035#define EMVSIM_INT_MASK_BWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)
5036#define EMVSIM_INT_MASK_BGT_ERR_IM_MASK (0x1000U)
5037#define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT (12U)
5038/*! BGT_ERR_IM - Block Guard Time Error Interrupt
5039 * 0b0..BGT_ERR interrupt enabled
5040 * 0b1..BGT_ERR interrupt masked (default)
5041 */
5042#define EMVSIM_INT_MASK_BGT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)
5043#define EMVSIM_INT_MASK_GPCNT1_IM_MASK (0x2000U)
5044#define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT (13U)
5045/*! GPCNT1_IM - General Purpose Counter 1 Timeout Interrupt Mask
5046 * 0b0..GPCNT1_TO interrupt enabled
5047 * 0b1..GPCNT1_TO interrupt masked (default)
5048 */
5049#define EMVSIM_INT_MASK_GPCNT1_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)
5050#define EMVSIM_INT_MASK_RX_DATA_IM_MASK (0x4000U)
5051#define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT (14U)
5052/*! RX_DATA_IM - Receive Data Interrupt Mask
5053 * 0b0..RX_DATA interrupt enabled
5054 * 0b1..RX_DATA interrupt masked (default)
5055 */
5056#define EMVSIM_INT_MASK_RX_DATA_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)
5057#define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U)
5058#define EMVSIM_INT_MASK_PEF_IM_SHIFT (15U)
5059/*! PEF_IM - Parity Error Interrupt Mask
5060 * 0b0..PEF interrupt enabled
5061 * 0b1..PEF interrupt masked (default)
5062 */
5063#define EMVSIM_INT_MASK_PEF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
5064/*! @} */
5065
5066/*! @name RX_THD - Receiver Threshold Register */
5067/*! @{ */
5068#define EMVSIM_RX_THD_RDT_MASK (0xFU)
5069#define EMVSIM_RX_THD_RDT_SHIFT (0U)
5070#define EMVSIM_RX_THD_RDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
5071#define EMVSIM_RX_THD_RNCK_THD_MASK (0xF00U)
5072#define EMVSIM_RX_THD_RNCK_THD_SHIFT (8U)
5073/*! RNCK_THD - Receiver NACK Threshold Value
5074 * 0b0000..Zero Threshold. RTE will not be set
5075 */
5076#define EMVSIM_RX_THD_RNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)
5077/*! @} */
5078
5079/*! @name TX_THD - Transmitter Threshold Register */
5080/*! @{ */
5081#define EMVSIM_TX_THD_TDT_MASK (0xFU)
5082#define EMVSIM_TX_THD_TDT_SHIFT (0U)
5083#define EMVSIM_TX_THD_TDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)
5084#define EMVSIM_TX_THD_TNCK_THD_MASK (0xF00U)
5085#define EMVSIM_TX_THD_TNCK_THD_SHIFT (8U)
5086/*! TNCK_THD - Transmitter NACK Threshold Value
5087 * 0b0000..TNTE will never be set; retransmission after NACK reception is disabled.
5088 * 0b0001..TNTE will be set after 1 nack is received; 0 retransmissions occurs.
5089 * 0b0010..TNTE will be set after 2 nacks are received; at most 1 retransmission occurs.
5090 * 0b0011..TNTE will be set after 3 nacks are received; at most 2 retransmissions occurs.
5091 * 0b1111..TNTE will be set after 15 nacks are received; at most 14 retransmissions occurs.
5092 */
5093#define EMVSIM_TX_THD_TNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)
5094/*! @} */
5095
5096/*! @name RX_STATUS - Receive Status Register */
5097/*! @{ */
5098#define EMVSIM_RX_STATUS_RFO_MASK (0x1U)
5099#define EMVSIM_RX_STATUS_RFO_SHIFT (0U)
5100/*! RFO - Receive FIFO Overflow Flag
5101 * 0b0..No overrun error has occurred (default)
5102 * 0b1..A byte was received when the received FIFO was already full
5103 */
5104#define EMVSIM_RX_STATUS_RFO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)
5105#define EMVSIM_RX_STATUS_RX_DATA_MASK (0x10U)
5106#define EMVSIM_RX_STATUS_RX_DATA_SHIFT (4U)
5107/*! RX_DATA - Receive Data Interrupt Flag
5108 * 0b0..No new byte is received
5109 * 0b1..New byte is received ans stored in Receive FIFO
5110 */
5111#define EMVSIM_RX_STATUS_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)
5112#define EMVSIM_RX_STATUS_RDTF_MASK (0x20U)
5113#define EMVSIM_RX_STATUS_RDTF_SHIFT (5U)
5114/*! RDTF - Receive Data Threshold Interrupt Flag
5115 * 0b0..Number of unread bytes in receive FIFO less than the value set by RDT[3:0] (default).
5116 * 0b1..Number of unread bytes in receive FIFO greater or than equal to value set by RDT[3:0].
5117 */
5118#define EMVSIM_RX_STATUS_RDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)
5119#define EMVSIM_RX_STATUS_LRC_OK_MASK (0x40U)
5120#define EMVSIM_RX_STATUS_LRC_OK_SHIFT (6U)
5121/*! LRC_OK - LRC Check OK Flag
5122 * 0b0..Current LRC value does not match remainder.
5123 * 0b1..Current calculated LRC value matches the expected result (i.e. zero).
5124 */
5125#define EMVSIM_RX_STATUS_LRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)
5126#define EMVSIM_RX_STATUS_CRC_OK_MASK (0x80U)
5127#define EMVSIM_RX_STATUS_CRC_OK_SHIFT (7U)
5128/*! CRC_OK - CRC Check OK Flag
5129 * 0b0..Current CRC value does not match remainder.
5130 * 0b1..Current calculated CRC value matches the expected result.
5131 */
5132#define EMVSIM_RX_STATUS_CRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)
5133#define EMVSIM_RX_STATUS_CWT_ERR_MASK (0x100U)
5134#define EMVSIM_RX_STATUS_CWT_ERR_SHIFT (8U)
5135/*! CWT_ERR - Character Wait Time Error Flag
5136 * 0b0..No CWT violation has occurred (default).
5137 * 0b1..Time between two consecutive characters has exceeded the value in CHAR_WAIT.
5138 */
5139#define EMVSIM_RX_STATUS_CWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)
5140#define EMVSIM_RX_STATUS_RTE_MASK (0x200U)
5141#define EMVSIM_RX_STATUS_RTE_SHIFT (9U)
5142/*! RTE - Received NACK Threshold Error Flag
5143 * 0b0..Number of NACKs generated by the receiver is less than the value programmed in RTH[3:0]
5144 * 0b1..Number of NACKs generated by the receiver is equal to the value programmed in RTH[3:0]
5145 */
5146#define EMVSIM_RX_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)
5147#define EMVSIM_RX_STATUS_BWT_ERR_MASK (0x400U)
5148#define EMVSIM_RX_STATUS_BWT_ERR_SHIFT (10U)
5149/*! BWT_ERR - Block Wait Time Error Flag
5150 * 0b0..Block wait time not exceeded
5151 * 0b1..Block wait time was exceeded
5152 */
5153#define EMVSIM_RX_STATUS_BWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)
5154#define EMVSIM_RX_STATUS_BGT_ERR_MASK (0x800U)
5155#define EMVSIM_RX_STATUS_BGT_ERR_SHIFT (11U)
5156/*! BGT_ERR - Block Guard Time Error Flag
5157 * 0b0..Block guard time was sufficient
5158 * 0b1..Block guard time was too small
5159 */
5160#define EMVSIM_RX_STATUS_BGT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)
5161#define EMVSIM_RX_STATUS_PEF_MASK (0x1000U)
5162#define EMVSIM_RX_STATUS_PEF_SHIFT (12U)
5163/*! PEF - Parity Error Flag
5164 * 0b0..No parity error detected
5165 * 0b1..Parity error detected
5166 */
5167#define EMVSIM_RX_STATUS_PEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)
5168#define EMVSIM_RX_STATUS_FEF_MASK (0x2000U)
5169#define EMVSIM_RX_STATUS_FEF_SHIFT (13U)
5170/*! FEF - Frame Error Flag
5171 * 0b0..No frame error detected
5172 * 0b1..Frame error detected
5173 */
5174#define EMVSIM_RX_STATUS_FEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)
5175#define EMVSIM_RX_STATUS_RX_WPTR_MASK (0xF0000U)
5176#define EMVSIM_RX_STATUS_RX_WPTR_SHIFT (16U)
5177#define EMVSIM_RX_STATUS_RX_WPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)
5178#define EMVSIM_RX_STATUS_RX_CNT_MASK (0xF000000U)
5179#define EMVSIM_RX_STATUS_RX_CNT_SHIFT (24U)
5180/*! RX_CNT - Receive FIFO Byte Count
5181 * 0b0000..FIFO is emtpy
5182 */
5183#define EMVSIM_RX_STATUS_RX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)
5184/*! @} */
5185
5186/*! @name TX_STATUS - Transmitter Status Register */
5187/*! @{ */
5188#define EMVSIM_TX_STATUS_TNTE_MASK (0x1U)
5189#define EMVSIM_TX_STATUS_TNTE_SHIFT (0U)
5190/*! TNTE - Transmit NACK Threshold Error Flag
5191 * 0b0..Transmit NACK threshold has not been reached (default)
5192 * 0b1..Transmit NACK threshold reached; transmitter frozen
5193 */
5194#define EMVSIM_TX_STATUS_TNTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)
5195#define EMVSIM_TX_STATUS_TFE_MASK (0x8U)
5196#define EMVSIM_TX_STATUS_TFE_SHIFT (3U)
5197/*! TFE - Transmit FIFO Empty Flag
5198 * 0b0..Transmit FIFO is not empty
5199 * 0b1..Transmit FIFO is empty (default)
5200 */
5201#define EMVSIM_TX_STATUS_TFE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)
5202#define EMVSIM_TX_STATUS_ETCF_MASK (0x10U)
5203#define EMVSIM_TX_STATUS_ETCF_SHIFT (4U)
5204/*! ETCF - Early Transmit Complete Flag
5205 * 0b0..Transmit pending or in progress
5206 * 0b1..Transmit complete (default)
5207 */
5208#define EMVSIM_TX_STATUS_ETCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)
5209#define EMVSIM_TX_STATUS_TCF_MASK (0x20U)
5210#define EMVSIM_TX_STATUS_TCF_SHIFT (5U)
5211/*! TCF - Transmit Complete Flag
5212 * 0b0..Transmit pending or in progress
5213 * 0b1..Transmit complete (default)
5214 */
5215#define EMVSIM_TX_STATUS_TCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)
5216#define EMVSIM_TX_STATUS_TFF_MASK (0x40U)
5217#define EMVSIM_TX_STATUS_TFF_SHIFT (6U)
5218/*! TFF - Transmit FIFO Full Flag
5219 * 0b0..Transmit FIFO Full condition has not occurred (default)
5220 * 0b1..A Transmit FIFO Full condition has occurred
5221 */
5222#define EMVSIM_TX_STATUS_TFF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)
5223#define EMVSIM_TX_STATUS_TDTF_MASK (0x80U)
5224#define EMVSIM_TX_STATUS_TDTF_SHIFT (7U)
5225/*! TDTF - Transmit Data Threshold Flag
5226 * 0b0..Number of bytes in FIFO is greater than TDT[3:0], or bit has been cleared
5227 * 0b1..Number of bytes in FIFO is less than or equal to TDT[3:0] (default)
5228 */
5229#define EMVSIM_TX_STATUS_TDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)
5230#define EMVSIM_TX_STATUS_GPCNT0_TO_MASK (0x100U)
5231#define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT (8U)
5232/*! GPCNT0_TO - General Purpose Counter 0 Timeout Flag
5233 * 0b0..GPCNT0_VAL time not reached, or bit has been cleared. (default)
5234 * 0b1..General Purpose counter has reached the GPCNT0_VAL value
5235 */
5236#define EMVSIM_TX_STATUS_GPCNT0_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)
5237#define EMVSIM_TX_STATUS_GPCNT1_TO_MASK (0x200U)
5238#define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT (9U)
5239/*! GPCNT1_TO - General Purpose Counter 1 Timeout Flag
5240 * 0b0..GPCNT1_VAL time not reached, or bit has been cleared. (default)
5241 * 0b1..General Purpose counter has reached the GPCNT1_VAL value
5242 */
5243#define EMVSIM_TX_STATUS_GPCNT1_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)
5244#define EMVSIM_TX_STATUS_TX_RPTR_MASK (0xF0000U)
5245#define EMVSIM_TX_STATUS_TX_RPTR_SHIFT (16U)
5246#define EMVSIM_TX_STATUS_TX_RPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)
5247#define EMVSIM_TX_STATUS_TX_CNT_MASK (0xF000000U)
5248#define EMVSIM_TX_STATUS_TX_CNT_SHIFT (24U)
5249/*! TX_CNT - Transmit FIFO Byte Count
5250 * 0b0000..FIFO is emtpy
5251 */
5252#define EMVSIM_TX_STATUS_TX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)
5253/*! @} */
5254
5255/*! @name PCSR - Port Control and Status Register */
5256/*! @{ */
5257#define EMVSIM_PCSR_SAPD_MASK (0x1U)
5258#define EMVSIM_PCSR_SAPD_SHIFT (0U)
5259/*! SAPD - Auto Power Down Enable
5260 * 0b0..Auto power down disabled (default)
5261 * 0b1..Auto power down enabled
5262 */
5263#define EMVSIM_PCSR_SAPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)
5264#define EMVSIM_PCSR_SVCC_EN_MASK (0x2U)
5265#define EMVSIM_PCSR_SVCC_EN_SHIFT (1U)
5266/*! SVCC_EN - Vcc Enable for Smart Card
5267 * 0b0..Smart Card Voltage disabled (default)
5268 * 0b1..Smart Card Voltage enabled
5269 */
5270#define EMVSIM_PCSR_SVCC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)
5271#define EMVSIM_PCSR_VCCENP_MASK (0x4U)
5272#define EMVSIM_PCSR_VCCENP_SHIFT (2U)
5273/*! VCCENP - VCC Enable Polarity Control
5274 * 0b0..VCC_EN is active high. Polarity of SVCC_EN is unchanged.
5275 * 0b1..VCC_EN is active low. Polarity of SVCC_EN is inverted.
5276 */
5277#define EMVSIM_PCSR_VCCENP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)
5278#define EMVSIM_PCSR_SRST_MASK (0x8U)
5279#define EMVSIM_PCSR_SRST_SHIFT (3U)
5280/*! SRST - Reset to Smart Card
5281 * 0b0..Smart Card Reset is asserted (default)
5282 * 0b1..Smart Card Reset is de-asserted
5283 */
5284#define EMVSIM_PCSR_SRST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)
5285#define EMVSIM_PCSR_SCEN_MASK (0x10U)
5286#define EMVSIM_PCSR_SCEN_SHIFT (4U)
5287/*! SCEN - Clock Enable for Smart Card
5288 * 0b0..Smart Card Clock Disabled
5289 * 0b1..Smart Card Clock Enabled
5290 */
5291#define EMVSIM_PCSR_SCEN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)
5292#define EMVSIM_PCSR_SCSP_MASK (0x20U)
5293#define EMVSIM_PCSR_SCSP_SHIFT (5U)
5294/*! SCSP - Smart Card Clock Stop Polarity
5295 * 0b0..Clock is logic 0 when stopped by SCEN
5296 * 0b1..Clock is logic 1 when stopped by SCEN
5297 */
5298#define EMVSIM_PCSR_SCSP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)
5299#define EMVSIM_PCSR_SPD_MASK (0x80U)
5300#define EMVSIM_PCSR_SPD_SHIFT (7U)
5301/*! SPD - Auto Power Down Control
5302 * 0b0..No effect (default)
5303 * 0b1..Start Auto Powerdown or Power Down is in progress
5304 */
5305#define EMVSIM_PCSR_SPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)
5306#define EMVSIM_PCSR_SPDIM_MASK (0x1000000U)
5307#define EMVSIM_PCSR_SPDIM_SHIFT (24U)
5308/*! SPDIM - Smart Card Presence Detect Interrupt Mask
5309 * 0b0..SIM presence detect interrupt is enabled
5310 * 0b1..SIM presence detect interrupt is masked (default)
5311 */
5312#define EMVSIM_PCSR_SPDIM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)
5313#define EMVSIM_PCSR_SPDIF_MASK (0x2000000U)
5314#define EMVSIM_PCSR_SPDIF_SHIFT (25U)
5315/*! SPDIF - Smart Card Presence Detect Interrupt Flag
5316 * 0b0..No insertion or removal of Smart Card detected on Port (default)
5317 * 0b1..Insertion or removal of Smart Card detected on Port
5318 */
5319#define EMVSIM_PCSR_SPDIF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)
5320#define EMVSIM_PCSR_SPDP_MASK (0x4000000U)
5321#define EMVSIM_PCSR_SPDP_SHIFT (26U)
5322/*! SPDP - Smart Card Presence Detect Pin Status
5323 * 0b0..SIM Presence Detect pin is logic low
5324 * 0b1..SIM Presence Detectpin is logic high
5325 */
5326#define EMVSIM_PCSR_SPDP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)
5327#define EMVSIM_PCSR_SPDES_MASK (0x8000000U)
5328#define EMVSIM_PCSR_SPDES_SHIFT (27U)
5329/*! SPDES - SIM Presence Detect Edge Select
5330 * 0b0..Falling edge on the pin (default)
5331 * 0b1..Rising edge on the pin
5332 */
5333#define EMVSIM_PCSR_SPDES(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)
5334/*! @} */
5335
5336/*! @name RX_BUF - Receive Data Read Buffer */
5337/*! @{ */
5338#define EMVSIM_RX_BUF_RX_BYTE_MASK (0xFFU)
5339#define EMVSIM_RX_BUF_RX_BYTE_SHIFT (0U)
5340#define EMVSIM_RX_BUF_RX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)
5341/*! @} */
5342
5343/*! @name TX_BUF - Transmit Data Buffer */
5344/*! @{ */
5345#define EMVSIM_TX_BUF_TX_BYTE_MASK (0xFFU)
5346#define EMVSIM_TX_BUF_TX_BYTE_SHIFT (0U)
5347#define EMVSIM_TX_BUF_TX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)
5348/*! @} */
5349
5350/*! @name TX_GETU - Transmitter Guard ETU Value Register */
5351/*! @{ */
5352#define EMVSIM_TX_GETU_GETU_MASK (0xFFU)
5353#define EMVSIM_TX_GETU_GETU_SHIFT (0U)
5354/*! GETU - Transmitter Guard Time Value in ETU
5355 * 0b00000000..no additional ETUs inserted (default)
5356 * 0b00000001..1 additional ETU inserted
5357 * 0b11111110..254 additional ETUs inserted
5358 * 0b11111111..Subtracts one ETU by reducing the number of STOP bits from two to one
5359 */
5360#define EMVSIM_TX_GETU_GETU(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
5361/*! @} */
5362
5363/*! @name CWT_VAL - Character Wait Time Value Register */
5364/*! @{ */
5365#define EMVSIM_CWT_VAL_CWT_MASK (0xFFFFU)
5366#define EMVSIM_CWT_VAL_CWT_SHIFT (0U)
5367#define EMVSIM_CWT_VAL_CWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)
5368/*! @} */
5369
5370/*! @name BWT_VAL - Block Wait Time Value Register */
5371/*! @{ */
5372#define EMVSIM_BWT_VAL_BWT_MASK (0xFFFFFFFFU)
5373#define EMVSIM_BWT_VAL_BWT_SHIFT (0U)
5374#define EMVSIM_BWT_VAL_BWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)
5375/*! @} */
5376
5377/*! @name BGT_VAL - Block Guard Time Value Register */
5378/*! @{ */
5379#define EMVSIM_BGT_VAL_BGT_MASK (0xFFFFU)
5380#define EMVSIM_BGT_VAL_BGT_SHIFT (0U)
5381#define EMVSIM_BGT_VAL_BGT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)
5382/*! @} */
5383
5384/*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */
5385/*! @{ */
5386#define EMVSIM_GPCNT0_VAL_GPCNT0_MASK (0xFFFFU)
5387#define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT (0U)
5388#define EMVSIM_GPCNT0_VAL_GPCNT0(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)
5389/*! @} */
5390
5391/*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */
5392/*! @{ */
5393#define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU)
5394#define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT (0U)
5395#define EMVSIM_GPCNT1_VAL_GPCNT1(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
5396/*! @} */
5397
5398
5399/*!
5400 * @}
5401 */ /* end of group EMVSIM_Register_Masks */
5402
5403
5404/* EMVSIM - Peripheral instance base addresses */
5405/** Peripheral EMVSIM0 base address */
5406#define EMVSIM0_BASE (0x40038000u)
5407/** Peripheral EMVSIM0 base pointer */
5408#define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE)
5409/** Array initializer of EMVSIM peripheral base addresses */
5410#define EMVSIM_BASE_ADDRS { EMVSIM0_BASE }
5411/** Array initializer of EMVSIM peripheral base pointers */
5412#define EMVSIM_BASE_PTRS { EMVSIM0 }
5413/** Interrupt vectors for the EMVSIM peripheral type */
5414#define EMVSIM_IRQS { EMVSIM0_IRQn }
5415
5416/*!
5417 * @}
5418 */ /* end of group EMVSIM_Peripheral_Access_Layer */
5419
5420
5421/* ----------------------------------------------------------------------------
5422 -- EWM Peripheral Access Layer
5423 ---------------------------------------------------------------------------- */
5424
5425/*!
5426 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
5427 * @{
5428 */
5429
5430/** EWM - Register Layout Typedef */
5431typedef struct {
5432 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
5433 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
5434 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
5435 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
5436 uint8_t RESERVED_0[1];
5437 __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
5438} EWM_Type;
5439
5440/* ----------------------------------------------------------------------------
5441 -- EWM Register Masks
5442 ---------------------------------------------------------------------------- */
5443
5444/*!
5445 * @addtogroup EWM_Register_Masks EWM Register Masks
5446 * @{
5447 */
5448
5449/*! @name CTRL - Control Register */
5450/*! @{ */
5451#define EWM_CTRL_EWMEN_MASK (0x1U)
5452#define EWM_CTRL_EWMEN_SHIFT (0U)
5453#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
5454#define EWM_CTRL_ASSIN_MASK (0x2U)
5455#define EWM_CTRL_ASSIN_SHIFT (1U)
5456#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
5457#define EWM_CTRL_INEN_MASK (0x4U)
5458#define EWM_CTRL_INEN_SHIFT (2U)
5459#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
5460#define EWM_CTRL_INTEN_MASK (0x8U)
5461#define EWM_CTRL_INTEN_SHIFT (3U)
5462#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
5463/*! @} */
5464
5465/*! @name SERV - Service Register */
5466/*! @{ */
5467#define EWM_SERV_SERVICE_MASK (0xFFU)
5468#define EWM_SERV_SERVICE_SHIFT (0U)
5469#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
5470/*! @} */
5471
5472/*! @name CMPL - Compare Low Register */
5473/*! @{ */
5474#define EWM_CMPL_COMPAREL_MASK (0xFFU)
5475#define EWM_CMPL_COMPAREL_SHIFT (0U)
5476#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
5477/*! @} */
5478
5479/*! @name CMPH - Compare High Register */
5480/*! @{ */
5481#define EWM_CMPH_COMPAREH_MASK (0xFFU)
5482#define EWM_CMPH_COMPAREH_SHIFT (0U)
5483#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
5484/*! @} */
5485
5486/*! @name CLKPRESCALER - Clock Prescaler Register */
5487/*! @{ */
5488#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
5489#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
5490#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
5491/*! @} */
5492
5493
5494/*!
5495 * @}
5496 */ /* end of group EWM_Register_Masks */
5497
5498
5499/* EWM - Peripheral instance base addresses */
5500/** Peripheral EWM base address */
5501#define EWM_BASE (0x40022000u)
5502/** Peripheral EWM base pointer */
5503#define EWM ((EWM_Type *)EWM_BASE)
5504/** Array initializer of EWM peripheral base addresses */
5505#define EWM_BASE_ADDRS { EWM_BASE }
5506/** Array initializer of EWM peripheral base pointers */
5507#define EWM_BASE_PTRS { EWM }
5508/** Interrupt vectors for the EWM peripheral type */
5509#define EWM_IRQS { EWM_IRQn }
5510
5511/*!
5512 * @}
5513 */ /* end of group EWM_Peripheral_Access_Layer */
5514
5515
5516/* ----------------------------------------------------------------------------
5517 -- FB Peripheral Access Layer
5518 ---------------------------------------------------------------------------- */
5519
5520/*!
5521 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
5522 * @{
5523 */
5524
5525/** FB - Register Layout Typedef */
5526typedef struct {
5527 struct { /* offset: 0x0, array step: 0xC */
5528 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
5529 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
5530 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
5531 } CS[6];
5532 uint8_t RESERVED_0[24];
5533 __IO uint32_t CSPMCR; /**< Chip Select Port Multiplexing Control Register, offset: 0x60 */
5534} FB_Type;
5535
5536/* ----------------------------------------------------------------------------
5537 -- FB Register Masks
5538 ---------------------------------------------------------------------------- */
5539
5540/*!
5541 * @addtogroup FB_Register_Masks FB Register Masks
5542 * @{
5543 */
5544
5545/*! @name CSAR - Chip Select Address Register */
5546/*! @{ */
5547#define FB_CSAR_BA_MASK (0xFFFF0000U)
5548#define FB_CSAR_BA_SHIFT (16U)
5549#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
5550/*! @} */
5551
5552/* The count of FB_CSAR */
5553#define FB_CSAR_COUNT (6U)
5554
5555/*! @name CSMR - Chip Select Mask Register */
5556/*! @{ */
5557#define FB_CSMR_V_MASK (0x1U)
5558#define FB_CSMR_V_SHIFT (0U)
5559/*! V - Valid
5560 * 0b0..Chip-select is invalid.
5561 * 0b1..Chip-select is valid.
5562 */
5563#define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
5564#define FB_CSMR_WP_MASK (0x100U)
5565#define FB_CSMR_WP_SHIFT (8U)
5566/*! WP - Write Protect
5567 * 0b0..Write accesses are allowed.
5568 * 0b1..Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set
5569 * results in a bus error termination of the internal cycle and no external cycle.
5570 */
5571#define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
5572#define FB_CSMR_BAM_MASK (0xFFFF0000U)
5573#define FB_CSMR_BAM_SHIFT (16U)
5574/*! BAM - Base Address Mask
5575 * 0b0000000000000000..The corresponding address bit in CSAR is used in the chip-select decode.
5576 * 0b0000000000000001..The corresponding address bit in CSAR is a don't care in the chip-select decode.
5577 */
5578#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
5579/*! @} */
5580
5581/* The count of FB_CSMR */
5582#define FB_CSMR_COUNT (6U)
5583
5584/*! @name CSCR - Chip Select Control Register */
5585/*! @{ */
5586#define FB_CSCR_BSTW_MASK (0x8U)
5587#define FB_CSCR_BSTW_SHIFT (3U)
5588/*! BSTW - Burst-Write Enable
5589 * 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes.
5590 * For example, a 32-bit write to an 8-bit port takes four byte writes.
5591 * 0b1..Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8-
5592 * and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
5593 */
5594#define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
5595#define FB_CSCR_BSTR_MASK (0x10U)
5596#define FB_CSCR_BSTR_SHIFT (4U)
5597/*! BSTR - Burst-Read Enable
5598 * 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads.
5599 * For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
5600 * 0b1..Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and
5601 * 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
5602 */
5603#define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
5604#define FB_CSCR_BEM_MASK (0x20U)
5605#define FB_CSCR_BEM_SHIFT (5U)
5606/*! BEM - Byte-Enable Mode
5607 * 0b0..FB_BE_B is asserted for data write only.
5608 * 0b1..FB_BE_B is asserted for data read and write accesses.
5609 */
5610#define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
5611#define FB_CSCR_PS_MASK (0xC0U)
5612#define FB_CSCR_PS_SHIFT (6U)
5613/*! PS - Port Size
5614 * 0b00..32-bit port size. Valid data is sampled and driven on FB_D[31:0].
5615 * 0b01..8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b.
5616 * 0b1x..16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.
5617 */
5618#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
5619#define FB_CSCR_AA_MASK (0x100U)
5620#define FB_CSCR_AA_SHIFT (8U)
5621/*! AA - Auto-Acknowledge Enable
5622 * 0b0..Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
5623 * 0b1..Enabled. Internal transfer acknowledge is asserted as specified by WS.
5624 */
5625#define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
5626#define FB_CSCR_BLS_MASK (0x200U)
5627#define FB_CSCR_BLS_SHIFT (9U)
5628/*! BLS - Byte-Lane Shift
5629 * 0b0..Not shifted. Data is left-aligned on FB_AD.
5630 * 0b1..Shifted. Data is right-aligned on FB_AD.
5631 */
5632#define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
5633#define FB_CSCR_WS_MASK (0xFC00U)
5634#define FB_CSCR_WS_SHIFT (10U)
5635#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
5636#define FB_CSCR_WRAH_MASK (0x30000U)
5637#define FB_CSCR_WRAH_SHIFT (16U)
5638/*! WRAH - Write Address Hold or Deselect
5639 * 0b00..1 cycle (default for all but FB_CS0_B)
5640 * 0b01..2 cycles
5641 * 0b10..3 cycles
5642 * 0b11..4 cycles (default for FB_CS0_B)
5643 */
5644#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
5645#define FB_CSCR_RDAH_MASK (0xC0000U)
5646#define FB_CSCR_RDAH_SHIFT (18U)
5647/*! RDAH - Read Address Hold or Deselect
5648 * 0b00..When AA is 1b, 1 cycle. When AA is 0b, 0 cycles.
5649 * 0b01..When AA is 1b, 2 cycles. When AA is 0b, 1 cycle.
5650 * 0b10..When AA is 1b, 3 cycles. When AA is 0b, 2 cycles.
5651 * 0b11..When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.
5652 */
5653#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
5654#define FB_CSCR_ASET_MASK (0x300000U)
5655#define FB_CSCR_ASET_SHIFT (20U)
5656/*! ASET - Address Setup
5657 * 0b00..Assert FB_CSn_B on the first rising clock edge after the address is asserted (default for all but FB_CS0_B).
5658 * 0b01..Assert FB_CSn_B on the second rising clock edge after the address is asserted.
5659 * 0b10..Assert FB_CSn_B on the third rising clock edge after the address is asserted.
5660 * 0b11..Assert FB_CSn_B on the fourth rising clock edge after the address is asserted (default for FB_CS0_B ).
5661 */
5662#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
5663#define FB_CSCR_EXTS_MASK (0x400000U)
5664#define FB_CSCR_EXTS_SHIFT (22U)
5665/*! EXTS - EXTS
5666 * 0b0..Disabled. FB_TS_B/FB_ALE asserts for one bus clock cycle.
5667 * 0b1..Enabled. FB_TS_B/FB_ALE remains asserted until the first positive clock edge after FB_CSn_B asserts.
5668 */
5669#define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
5670#define FB_CSCR_SWSEN_MASK (0x800000U)
5671#define FB_CSCR_SWSEN_SHIFT (23U)
5672/*! SWSEN - Secondary Wait State Enable
5673 * 0b0..Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers.
5674 * 0b1..Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge
5675 * is generated for burst transfer secondary terminations.
5676 */
5677#define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
5678#define FB_CSCR_SWS_MASK (0xFC000000U)
5679#define FB_CSCR_SWS_SHIFT (26U)
5680#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
5681/*! @} */
5682
5683/* The count of FB_CSCR */
5684#define FB_CSCR_COUNT (6U)
5685
5686/*! @name CSPMCR - Chip Select Port Multiplexing Control Register */
5687/*! @{ */
5688#define FB_CSPMCR_GROUP5_MASK (0xF000U)
5689#define FB_CSPMCR_GROUP5_SHIFT (12U)
5690/*! GROUP5 - FlexBus Signal Group 5 Multiplex control
5691 * 0b0000..FB_TA_B
5692 * 0b0001..FB_CS3_B. You must also write 1b to CSCR[AA].
5693 * 0b0010..FB_BE_7_0_B. You must also write 1b to CSCR[AA].
5694 */
5695#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
5696#define FB_CSPMCR_GROUP4_MASK (0xF0000U)
5697#define FB_CSPMCR_GROUP4_SHIFT (16U)
5698/*! GROUP4 - FlexBus Signal Group 4 Multiplex control
5699 * 0b0000..FB_TBST_B
5700 * 0b0001..FB_CS2_B
5701 * 0b0010..FB_BE_15_8_B
5702 */
5703#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
5704#define FB_CSPMCR_GROUP3_MASK (0xF00000U)
5705#define FB_CSPMCR_GROUP3_SHIFT (20U)
5706/*! GROUP3 - FlexBus Signal Group 3 Multiplex control
5707 * 0b0000..FB_CS5_B
5708 * 0b0001..FB_TSIZ1
5709 * 0b0010..FB_BE_23_16_B
5710 */
5711#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
5712#define FB_CSPMCR_GROUP2_MASK (0xF000000U)
5713#define FB_CSPMCR_GROUP2_SHIFT (24U)
5714/*! GROUP2 - FlexBus Signal Group 2 Multiplex control
5715 * 0b0000..FB_CS4_B
5716 * 0b0001..FB_TSIZ0
5717 * 0b0010..FB_BE_31_24_B
5718 */
5719#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
5720#define FB_CSPMCR_GROUP1_MASK (0xF0000000U)
5721#define FB_CSPMCR_GROUP1_SHIFT (28U)
5722/*! GROUP1 - FlexBus Signal Group 1 Multiplex control
5723 * 0b0000..FB_ALE
5724 * 0b0001..FB_CS1_B
5725 * 0b0010..FB_TS_B
5726 */
5727#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
5728/*! @} */
5729
5730
5731/*!
5732 * @}
5733 */ /* end of group FB_Register_Masks */
5734
5735
5736/* FB - Peripheral instance base addresses */
5737/** Peripheral FB base address */
5738#define FB_BASE (0x4000C000u)
5739/** Peripheral FB base pointer */
5740#define FB ((FB_Type *)FB_BASE)
5741/** Array initializer of FB peripheral base addresses */
5742#define FB_BASE_ADDRS { FB_BASE }
5743/** Array initializer of FB peripheral base pointers */
5744#define FB_BASE_PTRS { FB }
5745
5746/*!
5747 * @}
5748 */ /* end of group FB_Peripheral_Access_Layer */
5749
5750
5751/* ----------------------------------------------------------------------------
5752 -- FLEXIO Peripheral Access Layer
5753 ---------------------------------------------------------------------------- */
5754
5755/*!
5756 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
5757 * @{
5758 */
5759
5760/** FLEXIO - Register Layout Typedef */
5761typedef struct {
5762 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
5763 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
5764 __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
5765 __I uint32_t PIN; /**< Pin State Register, offset: 0xC */
5766 __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
5767 __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
5768 __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
5769 uint8_t RESERVED_0[4];
5770 __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
5771 __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
5772 __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
5773 uint8_t RESERVED_1[4];
5774 __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
5775 uint8_t RESERVED_2[12];
5776 __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */
5777 uint8_t RESERVED_3[60];
5778 __IO uint32_t SHIFTCTL[8]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
5779 uint8_t RESERVED_4[96];
5780 __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
5781 uint8_t RESERVED_5[224];
5782 __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
5783 uint8_t RESERVED_6[96];
5784 __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
5785 uint8_t RESERVED_7[96];
5786 __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
5787 uint8_t RESERVED_8[96];
5788 __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
5789 uint8_t RESERVED_9[96];
5790 __IO uint32_t TIMCTL[8]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
5791 uint8_t RESERVED_10[96];
5792 __IO uint32_t TIMCFG[8]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
5793 uint8_t RESERVED_11[96];
5794 __IO uint32_t TIMCMP[8]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
5795 uint8_t RESERVED_12[352];
5796 __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
5797 uint8_t RESERVED_13[96];
5798 __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
5799 uint8_t RESERVED_14[96];
5800 __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
5801} FLEXIO_Type;
5802
5803/* ----------------------------------------------------------------------------
5804 -- FLEXIO Register Masks
5805 ---------------------------------------------------------------------------- */
5806
5807/*!
5808 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
5809 * @{
5810 */
5811
5812/*! @name VERID - Version ID Register */
5813/*! @{ */
5814#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
5815#define FLEXIO_VERID_FEATURE_SHIFT (0U)
5816/*! FEATURE - Feature Specification Number
5817 * 0b0000000000000000..Standard features implemented.
5818 * 0b0000000000000001..Supports state, logic and parallel modes.
5819 */
5820#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
5821#define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
5822#define FLEXIO_VERID_MINOR_SHIFT (16U)
5823#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
5824#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
5825#define FLEXIO_VERID_MAJOR_SHIFT (24U)
5826#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
5827/*! @} */
5828
5829/*! @name PARAM - Parameter Register */
5830/*! @{ */
5831#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
5832#define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
5833#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
5834#define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
5835#define FLEXIO_PARAM_TIMER_SHIFT (8U)
5836#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
5837#define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
5838#define FLEXIO_PARAM_PIN_SHIFT (16U)
5839#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
5840#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
5841#define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
5842#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
5843/*! @} */
5844
5845/*! @name CTRL - FlexIO Control Register */
5846/*! @{ */
5847#define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
5848#define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
5849/*! FLEXEN - FlexIO Enable
5850 * 0b0..FlexIO module is disabled.
5851 * 0b1..FlexIO module is enabled.
5852 */
5853#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
5854#define FLEXIO_CTRL_SWRST_MASK (0x2U)
5855#define FLEXIO_CTRL_SWRST_SHIFT (1U)
5856/*! SWRST - Software Reset
5857 * 0b0..Software reset is disabled
5858 * 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
5859 */
5860#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
5861#define FLEXIO_CTRL_FASTACC_MASK (0x4U)
5862#define FLEXIO_CTRL_FASTACC_SHIFT (2U)
5863/*! FASTACC - Fast Access
5864 * 0b0..Configures for normal register accesses to FlexIO
5865 * 0b1..Configures for fast register accesses to FlexIO
5866 */
5867#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
5868#define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
5869#define FLEXIO_CTRL_DBGE_SHIFT (30U)
5870/*! DBGE - Debug Enable
5871 * 0b0..FlexIO is disabled in debug modes.
5872 * 0b1..FlexIO is enabled in debug modes
5873 */
5874#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
5875#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
5876#define FLEXIO_CTRL_DOZEN_SHIFT (31U)
5877/*! DOZEN - Doze Enable
5878 * 0b0..FlexIO enabled in Doze modes.
5879 * 0b1..FlexIO disabled in Doze modes.
5880 */
5881#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
5882/*! @} */
5883
5884/*! @name PIN - Pin State Register */
5885/*! @{ */
5886#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU)
5887#define FLEXIO_PIN_PDI_SHIFT (0U)
5888#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
5889/*! @} */
5890
5891/*! @name SHIFTSTAT - Shifter Status Register */
5892/*! @{ */
5893#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU)
5894#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
5895#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
5896/*! @} */
5897
5898/*! @name SHIFTERR - Shifter Error Register */
5899/*! @{ */
5900#define FLEXIO_SHIFTERR_SEF_MASK (0xFFU)
5901#define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
5902#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
5903/*! @} */
5904
5905/*! @name TIMSTAT - Timer Status Register */
5906/*! @{ */
5907#define FLEXIO_TIMSTAT_TSF_MASK (0xFFU)
5908#define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
5909#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
5910/*! @} */
5911
5912/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
5913/*! @{ */
5914#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU)
5915#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
5916#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
5917/*! @} */
5918
5919/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
5920/*! @{ */
5921#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU)
5922#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
5923#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
5924/*! @} */
5925
5926/*! @name TIMIEN - Timer Interrupt Enable Register */
5927/*! @{ */
5928#define FLEXIO_TIMIEN_TEIE_MASK (0xFFU)
5929#define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
5930#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
5931/*! @} */
5932
5933/*! @name SHIFTSDEN - Shifter Status DMA Enable */
5934/*! @{ */
5935#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU)
5936#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
5937#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
5938/*! @} */
5939
5940/*! @name SHIFTSTATE - Shifter State Register */
5941/*! @{ */
5942#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U)
5943#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U)
5944#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
5945/*! @} */
5946
5947/*! @name SHIFTCTL - Shifter Control N Register */
5948/*! @{ */
5949#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
5950#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
5951/*! SMOD - Shifter Mode
5952 * 0b000..Disabled.
5953 * 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
5954 * 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
5955 * 0b011..Reserved.
5956 * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
5957 * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
5958 * 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes.
5959 * 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
5960 */
5961#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
5962#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
5963#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
5964/*! PINPOL - Shifter Pin Polarity
5965 * 0b0..Pin is active high
5966 * 0b1..Pin is active low
5967 */
5968#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
5969#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U)
5970#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
5971#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
5972#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
5973#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
5974/*! PINCFG - Shifter Pin Configuration
5975 * 0b00..Shifter pin output disabled
5976 * 0b01..Shifter pin open drain or bidirectional output enable
5977 * 0b10..Shifter pin bidirectional output data
5978 * 0b11..Shifter pin output
5979 */
5980#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
5981#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
5982#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
5983/*! TIMPOL - Timer Polarity
5984 * 0b0..Shift on posedge of Shift clock
5985 * 0b1..Shift on negedge of Shift clock
5986 */
5987#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
5988#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U)
5989#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
5990#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
5991/*! @} */
5992
5993/* The count of FLEXIO_SHIFTCTL */
5994#define FLEXIO_SHIFTCTL_COUNT (8U)
5995
5996/*! @name SHIFTCFG - Shifter Configuration N Register */
5997/*! @{ */
5998#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
5999#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
6000/*! SSTART - Shifter Start bit
6001 * 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
6002 * 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
6003 * 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
6004 * 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
6005 */
6006#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
6007#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
6008#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
6009/*! SSTOP - Shifter Stop bit
6010 * 0b00..Stop bit disabled for transmitter/receiver/match store
6011 * 0b01..Reserved for transmitter/receiver/match store
6012 * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
6013 * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
6014 */
6015#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
6016#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
6017#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
6018/*! INSRC - Input Source
6019 * 0b0..Pin
6020 * 0b1..Shifter N+1 Output
6021 */
6022#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
6023#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U)
6024#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)
6025#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
6026/*! @} */
6027
6028/* The count of FLEXIO_SHIFTCFG */
6029#define FLEXIO_SHIFTCFG_COUNT (8U)
6030
6031/*! @name SHIFTBUF - Shifter Buffer N Register */
6032/*! @{ */
6033#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
6034#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
6035#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
6036/*! @} */
6037
6038/* The count of FLEXIO_SHIFTBUF */
6039#define FLEXIO_SHIFTBUF_COUNT (8U)
6040
6041/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
6042/*! @{ */
6043#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
6044#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
6045#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
6046/*! @} */
6047
6048/* The count of FLEXIO_SHIFTBUFBIS */
6049#define FLEXIO_SHIFTBUFBIS_COUNT (8U)
6050
6051/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
6052/*! @{ */
6053#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
6054#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
6055#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
6056/*! @} */
6057
6058/* The count of FLEXIO_SHIFTBUFBYS */
6059#define FLEXIO_SHIFTBUFBYS_COUNT (8U)
6060
6061/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
6062/*! @{ */
6063#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
6064#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
6065#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
6066/*! @} */
6067
6068/* The count of FLEXIO_SHIFTBUFBBS */
6069#define FLEXIO_SHIFTBUFBBS_COUNT (8U)
6070
6071/*! @name TIMCTL - Timer Control N Register */
6072/*! @{ */
6073#define FLEXIO_TIMCTL_TIMOD_MASK (0x3U)
6074#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
6075/*! TIMOD - Timer Mode
6076 * 0b00..Timer Disabled.
6077 * 0b01..Dual 8-bit counters baud mode.
6078 * 0b10..Dual 8-bit counters PWM high mode.
6079 * 0b11..Single 16-bit counter mode.
6080 */
6081#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
6082#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
6083#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
6084/*! PINPOL - Timer Pin Polarity
6085 * 0b0..Pin is active high
6086 * 0b1..Pin is active low
6087 */
6088#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
6089#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U)
6090#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
6091#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
6092#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
6093#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
6094/*! PINCFG - Timer Pin Configuration
6095 * 0b00..Timer pin output disabled
6096 * 0b01..Timer pin open drain or bidirectional output enable
6097 * 0b10..Timer pin bidirectional output data
6098 * 0b11..Timer pin output
6099 */
6100#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
6101#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
6102#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
6103/*! TRGSRC - Trigger Source
6104 * 0b0..External trigger selected
6105 * 0b1..Internal trigger selected
6106 */
6107#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
6108#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
6109#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
6110/*! TRGPOL - Trigger Polarity
6111 * 0b0..Trigger active high
6112 * 0b1..Trigger active low
6113 */
6114#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
6115#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U)
6116#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
6117#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
6118/*! @} */
6119
6120/* The count of FLEXIO_TIMCTL */
6121#define FLEXIO_TIMCTL_COUNT (8U)
6122
6123/*! @name TIMCFG - Timer Configuration N Register */
6124/*! @{ */
6125#define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
6126#define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
6127/*! TSTART - Timer Start Bit
6128 * 0b0..Start bit disabled
6129 * 0b1..Start bit enabled
6130 */
6131#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
6132#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
6133#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
6134/*! TSTOP - Timer Stop Bit
6135 * 0b00..Stop bit disabled
6136 * 0b01..Stop bit is enabled on timer compare
6137 * 0b10..Stop bit is enabled on timer disable
6138 * 0b11..Stop bit is enabled on timer compare and timer disable
6139 */
6140#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
6141#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
6142#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
6143/*! TIMENA - Timer Enable
6144 * 0b000..Timer always enabled
6145 * 0b001..Timer enabled on Timer N-1 enable
6146 * 0b010..Timer enabled on Trigger high
6147 * 0b011..Timer enabled on Trigger high and Pin high
6148 * 0b100..Timer enabled on Pin rising edge
6149 * 0b101..Timer enabled on Pin rising edge and Trigger high
6150 * 0b110..Timer enabled on Trigger rising edge
6151 * 0b111..Timer enabled on Trigger rising or falling edge
6152 */
6153#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
6154#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
6155#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
6156/*! TIMDIS - Timer Disable
6157 * 0b000..Timer never disabled
6158 * 0b001..Timer disabled on Timer N-1 disable
6159 * 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement)
6160 * 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
6161 * 0b100..Timer disabled on Pin rising or falling edge
6162 * 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
6163 * 0b110..Timer disabled on Trigger falling edge
6164 * 0b111..Reserved
6165 */
6166#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
6167#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
6168#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
6169/*! TIMRST - Timer Reset
6170 * 0b000..Timer never reset
6171 * 0b001..Reserved
6172 * 0b010..Timer reset on Timer Pin equal to Timer Output
6173 * 0b011..Timer reset on Timer Trigger equal to Timer Output
6174 * 0b100..Timer reset on Timer Pin rising edge
6175 * 0b101..Reserved
6176 * 0b110..Timer reset on Trigger rising edge
6177 * 0b111..Timer reset on Trigger rising or falling edge
6178 */
6179#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
6180#define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)
6181#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
6182/*! TIMDEC - Timer Decrement
6183 * 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output.
6184 * 0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
6185 * 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
6186 * 0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
6187 */
6188#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
6189#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
6190#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
6191/*! TIMOUT - Timer Output
6192 * 0b00..Timer output is logic one when enabled and is not affected by timer reset
6193 * 0b01..Timer output is logic zero when enabled and is not affected by timer reset
6194 * 0b10..Timer output is logic one when enabled and on timer reset
6195 * 0b11..Timer output is logic zero when enabled and on timer reset
6196 */
6197#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
6198/*! @} */
6199
6200/* The count of FLEXIO_TIMCFG */
6201#define FLEXIO_TIMCFG_COUNT (8U)
6202
6203/*! @name TIMCMP - Timer Compare N Register */
6204/*! @{ */
6205#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
6206#define FLEXIO_TIMCMP_CMP_SHIFT (0U)
6207#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
6208/*! @} */
6209
6210/* The count of FLEXIO_TIMCMP */
6211#define FLEXIO_TIMCMP_COUNT (8U)
6212
6213/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
6214/*! @{ */
6215#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)
6216#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)
6217#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
6218/*! @} */
6219
6220/* The count of FLEXIO_SHIFTBUFNBS */
6221#define FLEXIO_SHIFTBUFNBS_COUNT (8U)
6222
6223/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
6224/*! @{ */
6225#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)
6226#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)
6227#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
6228/*! @} */
6229
6230/* The count of FLEXIO_SHIFTBUFHWS */
6231#define FLEXIO_SHIFTBUFHWS_COUNT (8U)
6232
6233/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
6234/*! @{ */
6235#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)
6236#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)
6237#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
6238/*! @} */
6239
6240/* The count of FLEXIO_SHIFTBUFNIS */
6241#define FLEXIO_SHIFTBUFNIS_COUNT (8U)
6242
6243
6244/*!
6245 * @}
6246 */ /* end of group FLEXIO_Register_Masks */
6247
6248
6249/* FLEXIO - Peripheral instance base addresses */
6250/** Peripheral FLEXIO0 base address */
6251#define FLEXIO0_BASE (0x40039000u)
6252/** Peripheral FLEXIO0 base pointer */
6253#define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE)
6254/** Array initializer of FLEXIO peripheral base addresses */
6255#define FLEXIO_BASE_ADDRS { FLEXIO0_BASE }
6256/** Array initializer of FLEXIO peripheral base pointers */
6257#define FLEXIO_BASE_PTRS { FLEXIO0 }
6258/** Interrupt vectors for the FLEXIO peripheral type */
6259#define FLEXIO_IRQS { FLEXIO0_IRQn }
6260
6261/*!
6262 * @}
6263 */ /* end of group FLEXIO_Peripheral_Access_Layer */
6264
6265
6266/* ----------------------------------------------------------------------------
6267 -- FTFE Peripheral Access Layer
6268 ---------------------------------------------------------------------------- */
6269
6270/*!
6271 * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
6272 * @{
6273 */
6274
6275/** FTFE - Register Layout Typedef */
6276typedef struct {
6277 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
6278 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
6279 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
6280 uint8_t RESERVED_0[1];
6281 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
6282 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
6283 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
6284 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
6285 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
6286 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
6287 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
6288 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
6289 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
6290 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
6291 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
6292 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
6293 __I uint8_t FOPT3; /**< Flash Option Registers, offset: 0x10 */
6294 __I uint8_t FOPT2; /**< Flash Option Registers, offset: 0x11 */
6295 __I uint8_t FOPT1; /**< Flash Option Registers, offset: 0x12 */
6296 __I uint8_t FOPT0; /**< Flash Option Registers, offset: 0x13 */
6297 uint8_t RESERVED_1[4];
6298 __IO uint8_t FPROTH3; /**< Primary Program Flash Protection Registers, offset: 0x18 */
6299 __IO uint8_t FPROTH2; /**< Primary Program Flash Protection Registers, offset: 0x19 */
6300 __IO uint8_t FPROTH1; /**< Primary Program Flash Protection Registers, offset: 0x1A */
6301 __IO uint8_t FPROTH0; /**< Primary Program Flash Protection Registers, offset: 0x1B */
6302 __IO uint8_t FPROTL3; /**< Primary Program Flash Protection Registers, offset: 0x1C */
6303 __IO uint8_t FPROTL2; /**< Primary Program Flash Protection Registers, offset: 0x1D */
6304 __IO uint8_t FPROTL1; /**< Primary Program Flash Protection Registers, offset: 0x1E */
6305 __IO uint8_t FPROTL0; /**< Primary Program Flash Protection Registers, offset: 0x1F */
6306 uint8_t RESERVED_2[4];
6307 __IO uint8_t FPROTSL; /**< Secondary Program Flash Protection Registers, offset: 0x24 */
6308 __IO uint8_t FPROTSH; /**< Secondary Program Flash Protection Registers, offset: 0x25 */
6309 uint8_t RESERVED_3[6];
6310 __I uint8_t FACSS; /**< Primary Flash Access Segment Size Register, offset: 0x2C */
6311 __I uint8_t FACSN; /**< Primary Flash Access Segment Number Register, offset: 0x2D */
6312 __I uint8_t FACSSS; /**< Secondary Flash Access Segment Size Register, offset: 0x2E */
6313 __I uint8_t FACSNS; /**< Secondary Flash Access Segment Number Register, offset: 0x2F */
6314 __I uint8_t XACCH3; /**< Primary Execute-only Access Registers, offset: 0x30 */
6315 __I uint8_t XACCH2; /**< Primary Execute-only Access Registers, offset: 0x31 */
6316 __I uint8_t XACCH1; /**< Primary Execute-only Access Registers, offset: 0x32 */
6317 __I uint8_t XACCH0; /**< Primary Execute-only Access Registers, offset: 0x33 */
6318 __I uint8_t XACCL3; /**< Primary Execute-only Access Registers, offset: 0x34 */
6319 __I uint8_t XACCL2; /**< Primary Execute-only Access Registers, offset: 0x35 */
6320 __I uint8_t XACCL1; /**< Primary Execute-only Access Registers, offset: 0x36 */
6321 __I uint8_t XACCL0; /**< Primary Execute-only Access Registers, offset: 0x37 */
6322 __I uint8_t SACCH3; /**< Primary Supervisor-only Access Registers, offset: 0x38 */
6323 __I uint8_t SACCH2; /**< Primary Supervisor-only Access Registers, offset: 0x39 */
6324 __I uint8_t SACCH1; /**< Primary Supervisor-only Access Registers, offset: 0x3A */
6325 __I uint8_t SACCH0; /**< Primary Supervisor-only Access Registers, offset: 0x3B */
6326 __I uint8_t SACCL3; /**< Primary Supervisor-only Access Registers, offset: 0x3C */
6327 __I uint8_t SACCL2; /**< Primary Supervisor-only Access Registers, offset: 0x3D */
6328 __I uint8_t SACCL1; /**< Primary Supervisor-only Access Registers, offset: 0x3E */
6329 __I uint8_t SACCL0; /**< Primary Supervisor-only Access Registers, offset: 0x3F */
6330 uint8_t RESERVED_4[4];
6331 __I uint8_t XACCSL; /**< Secondary Execute-only Access Registers, offset: 0x44 */
6332 __I uint8_t XACCSH; /**< Secondary Execute-only Access Registers, offset: 0x45 */
6333 uint8_t RESERVED_5[6];
6334 __I uint8_t SACCSL; /**< Secondary Supervisor-only Access Registers, offset: 0x4C */
6335 __I uint8_t SACCSH; /**< Secondary Supervisor-only Access Registers, offset: 0x4D */
6336 uint8_t RESERVED_6[4];
6337 __I uint8_t FSTDBYCTL; /**< Flash Standby Control Register, offset: 0x52 */
6338 __IO uint8_t FSTDBY; /**< Flash Standby Register, offset: 0x53 */
6339} FTFE_Type;
6340
6341/* ----------------------------------------------------------------------------
6342 -- FTFE Register Masks
6343 ---------------------------------------------------------------------------- */
6344
6345/*!
6346 * @addtogroup FTFE_Register_Masks FTFE Register Masks
6347 * @{
6348 */
6349
6350/*! @name FSTAT - Flash Status Register */
6351/*! @{ */
6352#define FTFE_FSTAT_MGSTAT0_MASK (0x1U)
6353#define FTFE_FSTAT_MGSTAT0_SHIFT (0U)
6354#define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)
6355#define FTFE_FSTAT_FPVIOL_MASK (0x10U)
6356#define FTFE_FSTAT_FPVIOL_SHIFT (4U)
6357/*! FPVIOL - Flash Protection Violation Flag
6358 * 0b0..No protection violation detected
6359 * 0b1..Protection violation detected
6360 */
6361#define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)
6362#define FTFE_FSTAT_ACCERR_MASK (0x20U)
6363#define FTFE_FSTAT_ACCERR_SHIFT (5U)
6364/*! ACCERR - Flash Access Error Flag
6365 * 0b0..No access error detected
6366 * 0b1..Access error detected
6367 */
6368#define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)
6369#define FTFE_FSTAT_RDCOLERR_MASK (0x40U)
6370#define FTFE_FSTAT_RDCOLERR_SHIFT (6U)
6371/*! RDCOLERR - Flash Read Collision Error Flag
6372 * 0b0..No collision error detected
6373 * 0b1..Collision error detected
6374 */
6375#define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)
6376#define FTFE_FSTAT_CCIF_MASK (0x80U)
6377#define FTFE_FSTAT_CCIF_SHIFT (7U)
6378/*! CCIF - Command Complete Interrupt Flag
6379 * 0b0..Flash command in progress
6380 * 0b1..Flash command has completed
6381 */
6382#define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)
6383/*! @} */
6384
6385/*! @name FCNFG - Flash Configuration Register */
6386/*! @{ */
6387#define FTFE_FCNFG_RAMRDY_MASK (0x2U)
6388#define FTFE_FCNFG_RAMRDY_SHIFT (1U)
6389/*! RAMRDY - RAM Ready
6390 * 0b0..Programming acceleration RAM is not available
6391 * 0b1..Programming acceleration RAM is available
6392 */
6393#define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)
6394#define FTFE_FCNFG_CRCRDY_MASK (0x4U)
6395#define FTFE_FCNFG_CRCRDY_SHIFT (2U)
6396/*! CRCRDY - CRC Ready
6397 * 0b0..Programming acceleration RAM is not available for CRC operations
6398 * 0b1..Programming acceleration RAM is available for CRC operations
6399 */
6400#define FTFE_FCNFG_CRCRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CRCRDY_SHIFT)) & FTFE_FCNFG_CRCRDY_MASK)
6401#define FTFE_FCNFG_SWAP_MASK (0x8U)
6402#define FTFE_FCNFG_SWAP_SHIFT (3U)
6403/*! SWAP - Swap
6404 * 0b0..Program flash 0 block is located at relative address 0x0000
6405 * 0b1..Program flash 1 block is located at relative address 0x0000
6406 */
6407#define FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)
6408#define FTFE_FCNFG_ERSSUSP_MASK (0x10U)
6409#define FTFE_FCNFG_ERSSUSP_SHIFT (4U)
6410/*! ERSSUSP - Erase Suspend
6411 * 0b0..No suspend requested
6412 * 0b1..Suspend the current Erase Flash Sector command execution
6413 */
6414#define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)
6415#define FTFE_FCNFG_ERSAREQ_MASK (0x20U)
6416#define FTFE_FCNFG_ERSAREQ_SHIFT (5U)
6417/*! ERSAREQ - Erase All Request
6418 * 0b0..No request or request complete
6419 * 0b1..Request to: (1) run the Erase All Blocks command, (2) verify the erased state, (3) program the security
6420 * byte in the Flash Configuration Field to the unsecure state, and (4) release MCU security by setting the
6421 * FSEC[SEC] field to the unsecure state.
6422 */
6423#define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)
6424#define FTFE_FCNFG_RDCOLLIE_MASK (0x40U)
6425#define FTFE_FCNFG_RDCOLLIE_SHIFT (6U)
6426/*! RDCOLLIE - Read Collision Error Interrupt Enable
6427 * 0b0..Read collision error interrupt disabled
6428 * 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever a flash read collision
6429 * error is detected (see the description of FSTAT[RDCOLERR]).
6430 */
6431#define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)
6432#define FTFE_FCNFG_CCIE_MASK (0x80U)
6433#define FTFE_FCNFG_CCIE_SHIFT (7U)
6434/*! CCIE - Command Complete Interrupt Enable
6435 * 0b0..Command complete interrupt disabled
6436 * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
6437 */
6438#define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)
6439/*! @} */
6440
6441/*! @name FSEC - Flash Security Register */
6442/*! @{ */
6443#define FTFE_FSEC_SEC_MASK (0x3U)
6444#define FTFE_FSEC_SEC_SHIFT (0U)
6445/*! SEC - Flash Security
6446 * 0b00..MCU security status is secure
6447 * 0b01..MCU security status is secure
6448 * 0b10..MCU security status is unsecure (The standard shipping condition of the flash module is unsecure.)
6449 * 0b11..MCU security status is secure
6450 */
6451#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
6452#define FTFE_FSEC_FSLACC_MASK (0xCU)
6453#define FTFE_FSEC_FSLACC_SHIFT (2U)
6454/*! FSLACC - Factory Security Level Access Code
6455 * 0b00..Factory access granted
6456 * 0b01..Factory access denied
6457 * 0b10..Factory access denied
6458 * 0b11..Factory access granted
6459 */
6460#define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
6461#define FTFE_FSEC_MEEN_MASK (0x30U)
6462#define FTFE_FSEC_MEEN_SHIFT (4U)
6463/*! MEEN - Mass Erase Enable Bits
6464 * 0b00..Mass erase is enabled
6465 * 0b01..Mass erase is enabled
6466 * 0b10..Mass erase is disabled
6467 * 0b11..Mass erase is enabled
6468 */
6469#define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
6470#define FTFE_FSEC_KEYEN_MASK (0xC0U)
6471#define FTFE_FSEC_KEYEN_SHIFT (6U)
6472/*! KEYEN - Backdoor Key Security Enable
6473 * 0b00..Backdoor key access disabled
6474 * 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
6475 * 0b10..Backdoor key access enabled
6476 * 0b11..Backdoor key access disabled
6477 */
6478#define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
6479/*! @} */
6480
6481/*! @name FCCOB3 - Flash Common Command Object Registers */
6482/*! @{ */
6483#define FTFE_FCCOB3_CCOBn_MASK (0xFFU)
6484#define FTFE_FCCOB3_CCOBn_SHIFT (0U)
6485#define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
6486/*! @} */
6487
6488/*! @name FCCOB2 - Flash Common Command Object Registers */
6489/*! @{ */
6490#define FTFE_FCCOB2_CCOBn_MASK (0xFFU)
6491#define FTFE_FCCOB2_CCOBn_SHIFT (0U)
6492#define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
6493/*! @} */
6494
6495/*! @name FCCOB1 - Flash Common Command Object Registers */
6496/*! @{ */
6497#define FTFE_FCCOB1_CCOBn_MASK (0xFFU)
6498#define FTFE_FCCOB1_CCOBn_SHIFT (0U)
6499#define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
6500/*! @} */
6501
6502/*! @name FCCOB0 - Flash Common Command Object Registers */
6503/*! @{ */
6504#define FTFE_FCCOB0_CCOBn_MASK (0xFFU)
6505#define FTFE_FCCOB0_CCOBn_SHIFT (0U)
6506#define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
6507/*! @} */
6508
6509/*! @name FCCOB7 - Flash Common Command Object Registers */
6510/*! @{ */
6511#define FTFE_FCCOB7_CCOBn_MASK (0xFFU)
6512#define FTFE_FCCOB7_CCOBn_SHIFT (0U)
6513#define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
6514/*! @} */
6515
6516/*! @name FCCOB6 - Flash Common Command Object Registers */
6517/*! @{ */
6518#define FTFE_FCCOB6_CCOBn_MASK (0xFFU)
6519#define FTFE_FCCOB6_CCOBn_SHIFT (0U)
6520#define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
6521/*! @} */
6522
6523/*! @name FCCOB5 - Flash Common Command Object Registers */
6524/*! @{ */
6525#define FTFE_FCCOB5_CCOBn_MASK (0xFFU)
6526#define FTFE_FCCOB5_CCOBn_SHIFT (0U)
6527#define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
6528/*! @} */
6529
6530/*! @name FCCOB4 - Flash Common Command Object Registers */
6531/*! @{ */
6532#define FTFE_FCCOB4_CCOBn_MASK (0xFFU)
6533#define FTFE_FCCOB4_CCOBn_SHIFT (0U)
6534#define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
6535/*! @} */
6536
6537/*! @name FCCOBB - Flash Common Command Object Registers */
6538/*! @{ */
6539#define FTFE_FCCOBB_CCOBn_MASK (0xFFU)
6540#define FTFE_FCCOBB_CCOBn_SHIFT (0U)
6541#define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
6542/*! @} */
6543
6544/*! @name FCCOBA - Flash Common Command Object Registers */
6545/*! @{ */
6546#define FTFE_FCCOBA_CCOBn_MASK (0xFFU)
6547#define FTFE_FCCOBA_CCOBn_SHIFT (0U)
6548#define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
6549/*! @} */
6550
6551/*! @name FCCOB9 - Flash Common Command Object Registers */
6552/*! @{ */
6553#define FTFE_FCCOB9_CCOBn_MASK (0xFFU)
6554#define FTFE_FCCOB9_CCOBn_SHIFT (0U)
6555#define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
6556/*! @} */
6557
6558/*! @name FCCOB8 - Flash Common Command Object Registers */
6559/*! @{ */
6560#define FTFE_FCCOB8_CCOBn_MASK (0xFFU)
6561#define FTFE_FCCOB8_CCOBn_SHIFT (0U)
6562#define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
6563/*! @} */
6564
6565/*! @name FOPT3 - Flash Option Registers */
6566/*! @{ */
6567#define FTFE_FOPT3_OPT_MASK (0xFFU)
6568#define FTFE_FOPT3_OPT_SHIFT (0U)
6569#define FTFE_FOPT3_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT3_OPT_SHIFT)) & FTFE_FOPT3_OPT_MASK)
6570/*! @} */
6571
6572/*! @name FOPT2 - Flash Option Registers */
6573/*! @{ */
6574#define FTFE_FOPT2_OPT_MASK (0xFFU)
6575#define FTFE_FOPT2_OPT_SHIFT (0U)
6576#define FTFE_FOPT2_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT2_OPT_SHIFT)) & FTFE_FOPT2_OPT_MASK)
6577/*! @} */
6578
6579/*! @name FOPT1 - Flash Option Registers */
6580/*! @{ */
6581#define FTFE_FOPT1_OPT_MASK (0xFFU)
6582#define FTFE_FOPT1_OPT_SHIFT (0U)
6583#define FTFE_FOPT1_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT1_OPT_SHIFT)) & FTFE_FOPT1_OPT_MASK)
6584/*! @} */
6585
6586/*! @name FOPT0 - Flash Option Registers */
6587/*! @{ */
6588#define FTFE_FOPT0_OPT_MASK (0xFFU)
6589#define FTFE_FOPT0_OPT_SHIFT (0U)
6590#define FTFE_FOPT0_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT0_OPT_SHIFT)) & FTFE_FOPT0_OPT_MASK)
6591/*! @} */
6592
6593/*! @name FPROTH3 - Primary Program Flash Protection Registers */
6594/*! @{ */
6595#define FTFE_FPROTH3_PROT_MASK (0xFFU)
6596#define FTFE_FPROTH3_PROT_SHIFT (0U)
6597#define FTFE_FPROTH3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH3_PROT_SHIFT)) & FTFE_FPROTH3_PROT_MASK)
6598/*! @} */
6599
6600/*! @name FPROTH2 - Primary Program Flash Protection Registers */
6601/*! @{ */
6602#define FTFE_FPROTH2_PROT_MASK (0xFFU)
6603#define FTFE_FPROTH2_PROT_SHIFT (0U)
6604#define FTFE_FPROTH2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH2_PROT_SHIFT)) & FTFE_FPROTH2_PROT_MASK)
6605/*! @} */
6606
6607/*! @name FPROTH1 - Primary Program Flash Protection Registers */
6608/*! @{ */
6609#define FTFE_FPROTH1_PROT_MASK (0xFFU)
6610#define FTFE_FPROTH1_PROT_SHIFT (0U)
6611#define FTFE_FPROTH1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH1_PROT_SHIFT)) & FTFE_FPROTH1_PROT_MASK)
6612/*! @} */
6613
6614/*! @name FPROTH0 - Primary Program Flash Protection Registers */
6615/*! @{ */
6616#define FTFE_FPROTH0_PROT_MASK (0xFFU)
6617#define FTFE_FPROTH0_PROT_SHIFT (0U)
6618#define FTFE_FPROTH0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH0_PROT_SHIFT)) & FTFE_FPROTH0_PROT_MASK)
6619/*! @} */
6620
6621/*! @name FPROTL3 - Primary Program Flash Protection Registers */
6622/*! @{ */
6623#define FTFE_FPROTL3_PROT_MASK (0xFFU)
6624#define FTFE_FPROTL3_PROT_SHIFT (0U)
6625#define FTFE_FPROTL3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL3_PROT_SHIFT)) & FTFE_FPROTL3_PROT_MASK)
6626/*! @} */
6627
6628/*! @name FPROTL2 - Primary Program Flash Protection Registers */
6629/*! @{ */
6630#define FTFE_FPROTL2_PROT_MASK (0xFFU)
6631#define FTFE_FPROTL2_PROT_SHIFT (0U)
6632#define FTFE_FPROTL2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL2_PROT_SHIFT)) & FTFE_FPROTL2_PROT_MASK)
6633/*! @} */
6634
6635/*! @name FPROTL1 - Primary Program Flash Protection Registers */
6636/*! @{ */
6637#define FTFE_FPROTL1_PROT_MASK (0xFFU)
6638#define FTFE_FPROTL1_PROT_SHIFT (0U)
6639#define FTFE_FPROTL1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL1_PROT_SHIFT)) & FTFE_FPROTL1_PROT_MASK)
6640/*! @} */
6641
6642/*! @name FPROTL0 - Primary Program Flash Protection Registers */
6643/*! @{ */
6644#define FTFE_FPROTL0_PROT_MASK (0xFFU)
6645#define FTFE_FPROTL0_PROT_SHIFT (0U)
6646#define FTFE_FPROTL0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL0_PROT_SHIFT)) & FTFE_FPROTL0_PROT_MASK)
6647/*! @} */
6648
6649/*! @name FPROTSL - Secondary Program Flash Protection Registers */
6650/*! @{ */
6651#define FTFE_FPROTSL_PROTS_MASK (0xFFU)
6652#define FTFE_FPROTSL_PROTS_SHIFT (0U)
6653#define FTFE_FPROTSL_PROTS(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTSL_PROTS_SHIFT)) & FTFE_FPROTSL_PROTS_MASK)
6654/*! @} */
6655
6656/*! @name FPROTSH - Secondary Program Flash Protection Registers */
6657/*! @{ */
6658#define FTFE_FPROTSH_PROTS_MASK (0xFFU)
6659#define FTFE_FPROTSH_PROTS_SHIFT (0U)
6660#define FTFE_FPROTSH_PROTS(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTSH_PROTS_SHIFT)) & FTFE_FPROTSH_PROTS_MASK)
6661/*! @} */
6662
6663/*! @name FACSS - Primary Flash Access Segment Size Register */
6664/*! @{ */
6665#define FTFE_FACSS_SGSIZE_MASK (0xFFU)
6666#define FTFE_FACSS_SGSIZE_SHIFT (0U)
6667#define FTFE_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSS_SGSIZE_SHIFT)) & FTFE_FACSS_SGSIZE_MASK)
6668/*! @} */
6669
6670/*! @name FACSN - Primary Flash Access Segment Number Register */
6671/*! @{ */
6672#define FTFE_FACSN_NUMSG_MASK (0xFFU)
6673#define FTFE_FACSN_NUMSG_SHIFT (0U)
6674/*! NUMSG - Number of Segments Indicator
6675 * 0b00110000..Primary Program flash memory is divided into 48 segments (768 Kbytes, 1.5 Mbytes)
6676 * 0b01000000..Primary Program flash memory is divided into 64 segments (512 Kbytes, 1 Mbyte, 2 Mbytes)
6677 */
6678#define FTFE_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSN_NUMSG_SHIFT)) & FTFE_FACSN_NUMSG_MASK)
6679/*! @} */
6680
6681/*! @name FACSSS - Secondary Flash Access Segment Size Register */
6682/*! @{ */
6683#define FTFE_FACSSS_SGSIZE_S_MASK (0xFFU)
6684#define FTFE_FACSSS_SGSIZE_S_SHIFT (0U)
6685#define FTFE_FACSSS_SGSIZE_S(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSSS_SGSIZE_S_SHIFT)) & FTFE_FACSSS_SGSIZE_S_MASK)
6686/*! @} */
6687
6688/*! @name FACSNS - Secondary Flash Access Segment Number Register */
6689/*! @{ */
6690#define FTFE_FACSNS_NUMSG_S_MASK (0xFFU)
6691#define FTFE_FACSNS_NUMSG_S_SHIFT (0U)
6692/*! NUMSG_S - Number of Segments Indicator
6693 * 0b00010000..Secondary Program flash memory is divided into 16 segments
6694 */
6695#define FTFE_FACSNS_NUMSG_S(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSNS_NUMSG_S_SHIFT)) & FTFE_FACSNS_NUMSG_S_MASK)
6696/*! @} */
6697
6698/*! @name XACCH3 - Primary Execute-only Access Registers */
6699/*! @{ */
6700#define FTFE_XACCH3_XA_MASK (0xFFU)
6701#define FTFE_XACCH3_XA_SHIFT (0U)
6702#define FTFE_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH3_XA_SHIFT)) & FTFE_XACCH3_XA_MASK)
6703/*! @} */
6704
6705/*! @name XACCH2 - Primary Execute-only Access Registers */
6706/*! @{ */
6707#define FTFE_XACCH2_XA_MASK (0xFFU)
6708#define FTFE_XACCH2_XA_SHIFT (0U)
6709#define FTFE_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH2_XA_SHIFT)) & FTFE_XACCH2_XA_MASK)
6710/*! @} */
6711
6712/*! @name XACCH1 - Primary Execute-only Access Registers */
6713/*! @{ */
6714#define FTFE_XACCH1_XA_MASK (0xFFU)
6715#define FTFE_XACCH1_XA_SHIFT (0U)
6716#define FTFE_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH1_XA_SHIFT)) & FTFE_XACCH1_XA_MASK)
6717/*! @} */
6718
6719/*! @name XACCH0 - Primary Execute-only Access Registers */
6720/*! @{ */
6721#define FTFE_XACCH0_XA_MASK (0xFFU)
6722#define FTFE_XACCH0_XA_SHIFT (0U)
6723#define FTFE_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH0_XA_SHIFT)) & FTFE_XACCH0_XA_MASK)
6724/*! @} */
6725
6726/*! @name XACCL3 - Primary Execute-only Access Registers */
6727/*! @{ */
6728#define FTFE_XACCL3_XA_MASK (0xFFU)
6729#define FTFE_XACCL3_XA_SHIFT (0U)
6730#define FTFE_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL3_XA_SHIFT)) & FTFE_XACCL3_XA_MASK)
6731/*! @} */
6732
6733/*! @name XACCL2 - Primary Execute-only Access Registers */
6734/*! @{ */
6735#define FTFE_XACCL2_XA_MASK (0xFFU)
6736#define FTFE_XACCL2_XA_SHIFT (0U)
6737#define FTFE_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL2_XA_SHIFT)) & FTFE_XACCL2_XA_MASK)
6738/*! @} */
6739
6740/*! @name XACCL1 - Primary Execute-only Access Registers */
6741/*! @{ */
6742#define FTFE_XACCL1_XA_MASK (0xFFU)
6743#define FTFE_XACCL1_XA_SHIFT (0U)
6744#define FTFE_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL1_XA_SHIFT)) & FTFE_XACCL1_XA_MASK)
6745/*! @} */
6746
6747/*! @name XACCL0 - Primary Execute-only Access Registers */
6748/*! @{ */
6749#define FTFE_XACCL0_XA_MASK (0xFFU)
6750#define FTFE_XACCL0_XA_SHIFT (0U)
6751#define FTFE_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL0_XA_SHIFT)) & FTFE_XACCL0_XA_MASK)
6752/*! @} */
6753
6754/*! @name SACCH3 - Primary Supervisor-only Access Registers */
6755/*! @{ */
6756#define FTFE_SACCH3_SA_MASK (0xFFU)
6757#define FTFE_SACCH3_SA_SHIFT (0U)
6758#define FTFE_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH3_SA_SHIFT)) & FTFE_SACCH3_SA_MASK)
6759/*! @} */
6760
6761/*! @name SACCH2 - Primary Supervisor-only Access Registers */
6762/*! @{ */
6763#define FTFE_SACCH2_SA_MASK (0xFFU)
6764#define FTFE_SACCH2_SA_SHIFT (0U)
6765#define FTFE_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH2_SA_SHIFT)) & FTFE_SACCH2_SA_MASK)
6766/*! @} */
6767
6768/*! @name SACCH1 - Primary Supervisor-only Access Registers */
6769/*! @{ */
6770#define FTFE_SACCH1_SA_MASK (0xFFU)
6771#define FTFE_SACCH1_SA_SHIFT (0U)
6772#define FTFE_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH1_SA_SHIFT)) & FTFE_SACCH1_SA_MASK)
6773/*! @} */
6774
6775/*! @name SACCH0 - Primary Supervisor-only Access Registers */
6776/*! @{ */
6777#define FTFE_SACCH0_SA_MASK (0xFFU)
6778#define FTFE_SACCH0_SA_SHIFT (0U)
6779#define FTFE_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK)
6780/*! @} */
6781
6782/*! @name SACCL3 - Primary Supervisor-only Access Registers */
6783/*! @{ */
6784#define FTFE_SACCL3_SA_MASK (0xFFU)
6785#define FTFE_SACCL3_SA_SHIFT (0U)
6786#define FTFE_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL3_SA_SHIFT)) & FTFE_SACCL3_SA_MASK)
6787/*! @} */
6788
6789/*! @name SACCL2 - Primary Supervisor-only Access Registers */
6790/*! @{ */
6791#define FTFE_SACCL2_SA_MASK (0xFFU)
6792#define FTFE_SACCL2_SA_SHIFT (0U)
6793#define FTFE_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL2_SA_SHIFT)) & FTFE_SACCL2_SA_MASK)
6794/*! @} */
6795
6796/*! @name SACCL1 - Primary Supervisor-only Access Registers */
6797/*! @{ */
6798#define FTFE_SACCL1_SA_MASK (0xFFU)
6799#define FTFE_SACCL1_SA_SHIFT (0U)
6800#define FTFE_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL1_SA_SHIFT)) & FTFE_SACCL1_SA_MASK)
6801/*! @} */
6802
6803/*! @name SACCL0 - Primary Supervisor-only Access Registers */
6804/*! @{ */
6805#define FTFE_SACCL0_SA_MASK (0xFFU)
6806#define FTFE_SACCL0_SA_SHIFT (0U)
6807#define FTFE_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL0_SA_SHIFT)) & FTFE_SACCL0_SA_MASK)
6808/*! @} */
6809
6810/*! @name XACCSL - Secondary Execute-only Access Registers */
6811/*! @{ */
6812#define FTFE_XACCSL_XA_S_MASK (0xFFU)
6813#define FTFE_XACCSL_XA_S_SHIFT (0U)
6814#define FTFE_XACCSL_XA_S(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCSL_XA_S_SHIFT)) & FTFE_XACCSL_XA_S_MASK)
6815/*! @} */
6816
6817/*! @name XACCSH - Secondary Execute-only Access Registers */
6818/*! @{ */
6819#define FTFE_XACCSH_XA_S_MASK (0xFFU)
6820#define FTFE_XACCSH_XA_S_SHIFT (0U)
6821#define FTFE_XACCSH_XA_S(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCSH_XA_S_SHIFT)) & FTFE_XACCSH_XA_S_MASK)
6822/*! @} */
6823
6824/*! @name SACCSL - Secondary Supervisor-only Access Registers */
6825/*! @{ */
6826#define FTFE_SACCSL_SA_S_MASK (0xFFU)
6827#define FTFE_SACCSL_SA_S_SHIFT (0U)
6828#define FTFE_SACCSL_SA_S(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCSL_SA_S_SHIFT)) & FTFE_SACCSL_SA_S_MASK)
6829/*! @} */
6830
6831/*! @name SACCSH - Secondary Supervisor-only Access Registers */
6832/*! @{ */
6833#define FTFE_SACCSH_SA_S_MASK (0xFFU)
6834#define FTFE_SACCSH_SA_S_SHIFT (0U)
6835#define FTFE_SACCSH_SA_S(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCSH_SA_S_SHIFT)) & FTFE_SACCSH_SA_S_MASK)
6836/*! @} */
6837
6838/*! @name FSTDBYCTL - Flash Standby Control Register */
6839/*! @{ */
6840#define FTFE_FSTDBYCTL_STDBYDIS_MASK (0x1U)
6841#define FTFE_FSTDBYCTL_STDBYDIS_SHIFT (0U)
6842/*! STDBYDIS - Standy Mode Disable
6843 * 0b0..Standby mode enabled for flash blocks selected by STDBYx
6844 * 0b1..Standby mode disabled (STDBYx ignored)
6845 */
6846#define FTFE_FSTDBYCTL_STDBYDIS(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBYCTL_STDBYDIS_SHIFT)) & FTFE_FSTDBYCTL_STDBYDIS_MASK)
6847/*! @} */
6848
6849/*! @name FSTDBY - Flash Standby Register */
6850/*! @{ */
6851#define FTFE_FSTDBY_STDBY0_MASK (0x1U)
6852#define FTFE_FSTDBY_STDBY0_SHIFT (0U)
6853/*! STDBY0 - Standy Mode for Flash Block 0
6854 * 0b0..Standby mode not enabled for flash block 0
6855 * 0b1..If STDBYDIS is clear, standby mode is enabled for flash block 0 (when SWAP=0/1, flash block 1/0 is the inactive block)
6856 */
6857#define FTFE_FSTDBY_STDBY0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBY_STDBY0_SHIFT)) & FTFE_FSTDBY_STDBY0_MASK)
6858#define FTFE_FSTDBY_STDBY1_MASK (0x2U)
6859#define FTFE_FSTDBY_STDBY1_SHIFT (1U)
6860/*! STDBY1 - Standy Mode for Flash Block 1
6861 * 0b0..Standby mode not enabled for flash block 1
6862 * 0b1..If STDBYDIS is clear, standby mode is enabled for flash block 1 (when SWAP=0/1, flash block 1/0 is the inactive block)
6863 */
6864#define FTFE_FSTDBY_STDBY1(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBY_STDBY1_SHIFT)) & FTFE_FSTDBY_STDBY1_MASK)
6865#define FTFE_FSTDBY_STDBY2_MASK (0x4U)
6866#define FTFE_FSTDBY_STDBY2_SHIFT (2U)
6867/*! STDBY2 - Standy Mode for Flash Block 2
6868 * 0b0..Standby mode not enabled for flash block 2
6869 * 0b1..If STDBYDIS is clear, standby mode is enabled for flash block 2
6870 */
6871#define FTFE_FSTDBY_STDBY2(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBY_STDBY2_SHIFT)) & FTFE_FSTDBY_STDBY2_MASK)
6872/*! @} */
6873
6874
6875/*!
6876 * @}
6877 */ /* end of group FTFE_Register_Masks */
6878
6879
6880/* FTFE - Peripheral instance base addresses */
6881/** Peripheral FTFE base address */
6882#define FTFE_BASE (0x40023000u)
6883/** Peripheral FTFE base pointer */
6884#define FTFE ((FTFE_Type *)FTFE_BASE)
6885/** Array initializer of FTFE peripheral base addresses */
6886#define FTFE_BASE_ADDRS { FTFE_BASE }
6887/** Array initializer of FTFE peripheral base pointers */
6888#define FTFE_BASE_PTRS { FTFE }
6889/** Interrupt vectors for the FTFE peripheral type */
6890#define FTFE_COMMAND_COMPLETE_IRQS { FTFE_Command_Complete_IRQn }
6891#define FTFE_READ_COLLISION_IRQS { FTFE_Read_Collision_IRQn }
6892
6893/*!
6894 * @}
6895 */ /* end of group FTFE_Peripheral_Access_Layer */
6896
6897
6898/* ----------------------------------------------------------------------------
6899 -- GPIO Peripheral Access Layer
6900 ---------------------------------------------------------------------------- */
6901
6902/*!
6903 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
6904 * @{
6905 */
6906
6907/** GPIO - Register Layout Typedef */
6908typedef struct {
6909 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
6910 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
6911 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
6912 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
6913 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
6914 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
6915} GPIO_Type;
6916
6917/* ----------------------------------------------------------------------------
6918 -- GPIO Register Masks
6919 ---------------------------------------------------------------------------- */
6920
6921/*!
6922 * @addtogroup GPIO_Register_Masks GPIO Register Masks
6923 * @{
6924 */
6925
6926/*! @name PDOR - Port Data Output Register */
6927/*! @{ */
6928#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
6929#define GPIO_PDOR_PDO_SHIFT (0U)
6930#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
6931/*! @} */
6932
6933/*! @name PSOR - Port Set Output Register */
6934/*! @{ */
6935#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
6936#define GPIO_PSOR_PTSO_SHIFT (0U)
6937#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
6938/*! @} */
6939
6940/*! @name PCOR - Port Clear Output Register */
6941/*! @{ */
6942#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
6943#define GPIO_PCOR_PTCO_SHIFT (0U)
6944#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
6945/*! @} */
6946
6947/*! @name PTOR - Port Toggle Output Register */
6948/*! @{ */
6949#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
6950#define GPIO_PTOR_PTTO_SHIFT (0U)
6951#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
6952/*! @} */
6953
6954/*! @name PDIR - Port Data Input Register */
6955/*! @{ */
6956#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
6957#define GPIO_PDIR_PDI_SHIFT (0U)
6958#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
6959/*! @} */
6960
6961/*! @name PDDR - Port Data Direction Register */
6962/*! @{ */
6963#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
6964#define GPIO_PDDR_PDD_SHIFT (0U)
6965#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
6966/*! @} */
6967
6968
6969/*!
6970 * @}
6971 */ /* end of group GPIO_Register_Masks */
6972
6973
6974/* GPIO - Peripheral instance base addresses */
6975/** Peripheral GPIOA base address */
6976#define GPIOA_BASE (0x48020000u)
6977/** Peripheral GPIOA base pointer */
6978#define GPIOA ((GPIO_Type *)GPIOA_BASE)
6979/** Peripheral GPIOB base address */
6980#define GPIOB_BASE (0x48020040u)
6981/** Peripheral GPIOB base pointer */
6982#define GPIOB ((GPIO_Type *)GPIOB_BASE)
6983/** Peripheral GPIOC base address */
6984#define GPIOC_BASE (0x48020080u)
6985/** Peripheral GPIOC base pointer */
6986#define GPIOC ((GPIO_Type *)GPIOC_BASE)
6987/** Peripheral GPIOD base address */
6988#define GPIOD_BASE (0x480200C0u)
6989/** Peripheral GPIOD base pointer */
6990#define GPIOD ((GPIO_Type *)GPIOD_BASE)
6991/** Peripheral GPIOE base address */
6992#define GPIOE_BASE (0x4100F000u)
6993/** Peripheral GPIOE base pointer */
6994#define GPIOE ((GPIO_Type *)GPIOE_BASE)
6995/** Array initializer of GPIO peripheral base addresses */
6996#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
6997/** Array initializer of GPIO peripheral base pointers */
6998#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
6999
7000/*!
7001 * @}
7002 */ /* end of group GPIO_Peripheral_Access_Layer */
7003
7004
7005/* ----------------------------------------------------------------------------
7006 -- I2S Peripheral Access Layer
7007 ---------------------------------------------------------------------------- */
7008
7009/*!
7010 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
7011 * @{
7012 */
7013
7014/** I2S - Register Layout Typedef */
7015typedef struct {
7016 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
7017 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
7018 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */
7019 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */
7020 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */
7021 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */
7022 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */
7023 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */
7024 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
7025 uint8_t RESERVED_0[24];
7026 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
7027 uint8_t RESERVED_1[24];
7028 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
7029 uint8_t RESERVED_2[36];
7030 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */
7031 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */
7032 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */
7033 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */
7034 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */
7035 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */
7036 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
7037 uint8_t RESERVED_3[24];
7038 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
7039 uint8_t RESERVED_4[24];
7040 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
7041} I2S_Type;
7042
7043/* ----------------------------------------------------------------------------
7044 -- I2S Register Masks
7045 ---------------------------------------------------------------------------- */
7046
7047/*!
7048 * @addtogroup I2S_Register_Masks I2S Register Masks
7049 * @{
7050 */
7051
7052/*! @name VERID - Version ID Register */
7053/*! @{ */
7054#define I2S_VERID_FEATURE_MASK (0xFFFFU)
7055#define I2S_VERID_FEATURE_SHIFT (0U)
7056/*! FEATURE - Feature Specification Number
7057 * 0b0000000000000000..Standard feature set.
7058 */
7059#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
7060#define I2S_VERID_MINOR_MASK (0xFF0000U)
7061#define I2S_VERID_MINOR_SHIFT (16U)
7062#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
7063#define I2S_VERID_MAJOR_MASK (0xFF000000U)
7064#define I2S_VERID_MAJOR_SHIFT (24U)
7065#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
7066/*! @} */
7067
7068/*! @name PARAM - Parameter Register */
7069/*! @{ */
7070#define I2S_PARAM_DATALINE_MASK (0xFU)
7071#define I2S_PARAM_DATALINE_SHIFT (0U)
7072#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
7073#define I2S_PARAM_FIFO_MASK (0xF00U)
7074#define I2S_PARAM_FIFO_SHIFT (8U)
7075#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
7076#define I2S_PARAM_FRAME_MASK (0xF0000U)
7077#define I2S_PARAM_FRAME_SHIFT (16U)
7078#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
7079/*! @} */
7080
7081/*! @name TCSR - SAI Transmit Control Register */
7082/*! @{ */
7083#define I2S_TCSR_FRDE_MASK (0x1U)
7084#define I2S_TCSR_FRDE_SHIFT (0U)
7085/*! FRDE - FIFO Request DMA Enable
7086 * 0b0..Disables the DMA request.
7087 * 0b1..Enables the DMA request.
7088 */
7089#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
7090#define I2S_TCSR_FWDE_MASK (0x2U)
7091#define I2S_TCSR_FWDE_SHIFT (1U)
7092/*! FWDE - FIFO Warning DMA Enable
7093 * 0b0..Disables the DMA request.
7094 * 0b1..Enables the DMA request.
7095 */
7096#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
7097#define I2S_TCSR_FRIE_MASK (0x100U)
7098#define I2S_TCSR_FRIE_SHIFT (8U)
7099/*! FRIE - FIFO Request Interrupt Enable
7100 * 0b0..Disables the interrupt.
7101 * 0b1..Enables the interrupt.
7102 */
7103#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
7104#define I2S_TCSR_FWIE_MASK (0x200U)
7105#define I2S_TCSR_FWIE_SHIFT (9U)
7106/*! FWIE - FIFO Warning Interrupt Enable
7107 * 0b0..Disables the interrupt.
7108 * 0b1..Enables the interrupt.
7109 */
7110#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
7111#define I2S_TCSR_FEIE_MASK (0x400U)
7112#define I2S_TCSR_FEIE_SHIFT (10U)
7113/*! FEIE - FIFO Error Interrupt Enable
7114 * 0b0..Disables the interrupt.
7115 * 0b1..Enables the interrupt.
7116 */
7117#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
7118#define I2S_TCSR_SEIE_MASK (0x800U)
7119#define I2S_TCSR_SEIE_SHIFT (11U)
7120/*! SEIE - Sync Error Interrupt Enable
7121 * 0b0..Disables interrupt.
7122 * 0b1..Enables interrupt.
7123 */
7124#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
7125#define I2S_TCSR_WSIE_MASK (0x1000U)
7126#define I2S_TCSR_WSIE_SHIFT (12U)
7127/*! WSIE - Word Start Interrupt Enable
7128 * 0b0..Disables interrupt.
7129 * 0b1..Enables interrupt.
7130 */
7131#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
7132#define I2S_TCSR_FRF_MASK (0x10000U)
7133#define I2S_TCSR_FRF_SHIFT (16U)
7134/*! FRF - FIFO Request Flag
7135 * 0b0..Transmit FIFO watermark has not been reached.
7136 * 0b1..Transmit FIFO watermark has been reached.
7137 */
7138#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
7139#define I2S_TCSR_FWF_MASK (0x20000U)
7140#define I2S_TCSR_FWF_SHIFT (17U)
7141/*! FWF - FIFO Warning Flag
7142 * 0b0..No enabled transmit FIFO is empty.
7143 * 0b1..Enabled transmit FIFO is empty.
7144 */
7145#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
7146#define I2S_TCSR_FEF_MASK (0x40000U)
7147#define I2S_TCSR_FEF_SHIFT (18U)
7148/*! FEF - FIFO Error Flag
7149 * 0b0..Transmit underrun not detected.
7150 * 0b1..Transmit underrun detected.
7151 */
7152#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
7153#define I2S_TCSR_SEF_MASK (0x80000U)
7154#define I2S_TCSR_SEF_SHIFT (19U)
7155/*! SEF - Sync Error Flag
7156 * 0b0..Sync error not detected.
7157 * 0b1..Frame sync error detected.
7158 */
7159#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
7160#define I2S_TCSR_WSF_MASK (0x100000U)
7161#define I2S_TCSR_WSF_SHIFT (20U)
7162/*! WSF - Word Start Flag
7163 * 0b0..Start of word not detected.
7164 * 0b1..Start of word detected.
7165 */
7166#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
7167#define I2S_TCSR_SR_MASK (0x1000000U)
7168#define I2S_TCSR_SR_SHIFT (24U)
7169/*! SR - Software Reset
7170 * 0b0..No effect.
7171 * 0b1..Software reset.
7172 */
7173#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
7174#define I2S_TCSR_FR_MASK (0x2000000U)
7175#define I2S_TCSR_FR_SHIFT (25U)
7176/*! FR - FIFO Reset
7177 * 0b0..No effect.
7178 * 0b1..FIFO reset.
7179 */
7180#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
7181#define I2S_TCSR_BCE_MASK (0x10000000U)
7182#define I2S_TCSR_BCE_SHIFT (28U)
7183/*! BCE - Bit Clock Enable
7184 * 0b0..Transmit bit clock is disabled.
7185 * 0b1..Transmit bit clock is enabled.
7186 */
7187#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
7188#define I2S_TCSR_DBGE_MASK (0x20000000U)
7189#define I2S_TCSR_DBGE_SHIFT (29U)
7190/*! DBGE - Debug Enable
7191 * 0b0..Transmitter is disabled in Debug mode, after completing the current frame.
7192 * 0b1..Transmitter is enabled in Debug mode.
7193 */
7194#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
7195#define I2S_TCSR_STOPE_MASK (0x40000000U)
7196#define I2S_TCSR_STOPE_SHIFT (30U)
7197/*! STOPE - Stop Enable
7198 * 0b0..Transmitter disabled in Stop mode.
7199 * 0b1..Transmitter enabled in Stop mode.
7200 */
7201#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
7202#define I2S_TCSR_TE_MASK (0x80000000U)
7203#define I2S_TCSR_TE_SHIFT (31U)
7204/*! TE - Transmitter Enable
7205 * 0b0..Transmitter is disabled.
7206 * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
7207 */
7208#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
7209/*! @} */
7210
7211/*! @name TCR1 - SAI Transmit Configuration 1 Register */
7212/*! @{ */
7213#define I2S_TCR1_TFW_MASK (0x7U)
7214#define I2S_TCR1_TFW_SHIFT (0U)
7215#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
7216/*! @} */
7217
7218/*! @name TCR2 - SAI Transmit Configuration 2 Register */
7219/*! @{ */
7220#define I2S_TCR2_DIV_MASK (0xFFU)
7221#define I2S_TCR2_DIV_SHIFT (0U)
7222#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
7223#define I2S_TCR2_BCD_MASK (0x1000000U)
7224#define I2S_TCR2_BCD_SHIFT (24U)
7225/*! BCD - Bit Clock Direction
7226 * 0b0..Bit clock is generated externally in Slave mode.
7227 * 0b1..Bit clock is generated internally in Master mode.
7228 */
7229#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
7230#define I2S_TCR2_BCP_MASK (0x2000000U)
7231#define I2S_TCR2_BCP_SHIFT (25U)
7232/*! BCP - Bit Clock Polarity
7233 * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
7234 * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
7235 */
7236#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
7237#define I2S_TCR2_MSEL_MASK (0xC000000U)
7238#define I2S_TCR2_MSEL_SHIFT (26U)
7239/*! MSEL - MCLK Select
7240 * 0b00..Bus Clock selected.
7241 * 0b01..Master Clock (MCLK) 1 option selected.
7242 * 0b10..Master Clock (MCLK) 2 option selected.
7243 * 0b11..Master Clock (MCLK) 3 option selected.
7244 */
7245#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
7246#define I2S_TCR2_BCI_MASK (0x10000000U)
7247#define I2S_TCR2_BCI_SHIFT (28U)
7248/*! BCI - Bit Clock Input
7249 * 0b0..No effect.
7250 * 0b1..Internal logic is clocked as if bit clock was externally generated.
7251 */
7252#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
7253#define I2S_TCR2_BCS_MASK (0x20000000U)
7254#define I2S_TCR2_BCS_SHIFT (29U)
7255/*! BCS - Bit Clock Swap
7256 * 0b0..Use the normal bit clock source.
7257 * 0b1..Swap the bit clock source.
7258 */
7259#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
7260#define I2S_TCR2_SYNC_MASK (0xC0000000U)
7261#define I2S_TCR2_SYNC_SHIFT (30U)
7262/*! SYNC - Synchronous Mode
7263 * 0b00..Asynchronous mode.
7264 * 0b01..Synchronous with receiver.
7265 * 0b10..Synchronous with another SAI transmitter.
7266 * 0b11..Synchronous with another SAI receiver.
7267 */
7268#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
7269/*! @} */
7270
7271/*! @name TCR3 - SAI Transmit Configuration 3 Register */
7272/*! @{ */
7273#define I2S_TCR3_WDFL_MASK (0x1FU)
7274#define I2S_TCR3_WDFL_SHIFT (0U)
7275#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
7276#define I2S_TCR3_TCE_MASK (0x30000U)
7277#define I2S_TCR3_TCE_SHIFT (16U)
7278#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
7279#define I2S_TCR3_CFR_MASK (0x3000000U)
7280#define I2S_TCR3_CFR_SHIFT (24U)
7281#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
7282/*! @} */
7283
7284/*! @name TCR4 - SAI Transmit Configuration 4 Register */
7285/*! @{ */
7286#define I2S_TCR4_FSD_MASK (0x1U)
7287#define I2S_TCR4_FSD_SHIFT (0U)
7288/*! FSD - Frame Sync Direction
7289 * 0b0..Frame sync is generated externally in Slave mode.
7290 * 0b1..Frame sync is generated internally in Master mode.
7291 */
7292#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
7293#define I2S_TCR4_FSP_MASK (0x2U)
7294#define I2S_TCR4_FSP_SHIFT (1U)
7295/*! FSP - Frame Sync Polarity
7296 * 0b0..Frame sync is active high.
7297 * 0b1..Frame sync is active low.
7298 */
7299#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
7300#define I2S_TCR4_ONDEM_MASK (0x4U)
7301#define I2S_TCR4_ONDEM_SHIFT (2U)
7302/*! ONDEM - On Demand Mode
7303 * 0b0..Internal frame sync is generated continuously.
7304 * 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
7305 */
7306#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
7307#define I2S_TCR4_FSE_MASK (0x8U)
7308#define I2S_TCR4_FSE_SHIFT (3U)
7309/*! FSE - Frame Sync Early
7310 * 0b0..Frame sync asserts with the first bit of the frame.
7311 * 0b1..Frame sync asserts one bit before the first bit of the frame.
7312 */
7313#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
7314#define I2S_TCR4_MF_MASK (0x10U)
7315#define I2S_TCR4_MF_SHIFT (4U)
7316/*! MF - MSB First
7317 * 0b0..LSB is transmitted first.
7318 * 0b1..MSB is transmitted first.
7319 */
7320#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
7321#define I2S_TCR4_CHMOD_MASK (0x20U)
7322#define I2S_TCR4_CHMOD_SHIFT (5U)
7323/*! CHMOD - Channel Mode
7324 * 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.
7325 * 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.
7326 */
7327#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
7328#define I2S_TCR4_SYWD_MASK (0x1F00U)
7329#define I2S_TCR4_SYWD_SHIFT (8U)
7330#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
7331#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
7332#define I2S_TCR4_FRSZ_SHIFT (16U)
7333#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
7334#define I2S_TCR4_FPACK_MASK (0x3000000U)
7335#define I2S_TCR4_FPACK_SHIFT (24U)
7336/*! FPACK - FIFO Packing Mode
7337 * 0b00..FIFO packing is disabled
7338 * 0b01..Reserved
7339 * 0b10..8-bit FIFO packing is enabled
7340 * 0b11..16-bit FIFO packing is enabled
7341 */
7342#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
7343#define I2S_TCR4_FCOMB_MASK (0xC000000U)
7344#define I2S_TCR4_FCOMB_SHIFT (26U)
7345/*! FCOMB - FIFO Combine Mode
7346 * 0b00..FIFO combine mode disabled.
7347 * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
7348 * 0b10..FIFO combine mode enabled on FIFO writes (by software).
7349 * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
7350 */
7351#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
7352#define I2S_TCR4_FCONT_MASK (0x10000000U)
7353#define I2S_TCR4_FCONT_SHIFT (28U)
7354/*! FCONT - FIFO Continue on Error
7355 * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
7356 * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
7357 */
7358#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
7359/*! @} */
7360
7361/*! @name TCR5 - SAI Transmit Configuration 5 Register */
7362/*! @{ */
7363#define I2S_TCR5_FBT_MASK (0x1F00U)
7364#define I2S_TCR5_FBT_SHIFT (8U)
7365#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
7366#define I2S_TCR5_W0W_MASK (0x1F0000U)
7367#define I2S_TCR5_W0W_SHIFT (16U)
7368#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
7369#define I2S_TCR5_WNW_MASK (0x1F000000U)
7370#define I2S_TCR5_WNW_SHIFT (24U)
7371#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
7372/*! @} */
7373
7374/*! @name TDR - SAI Transmit Data Register */
7375/*! @{ */
7376#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
7377#define I2S_TDR_TDR_SHIFT (0U)
7378#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
7379/*! @} */
7380
7381/* The count of I2S_TDR */
7382#define I2S_TDR_COUNT (2U)
7383
7384/*! @name TFR - SAI Transmit FIFO Register */
7385/*! @{ */
7386#define I2S_TFR_RFP_MASK (0xFU)
7387#define I2S_TFR_RFP_SHIFT (0U)
7388#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
7389#define I2S_TFR_WFP_MASK (0xF0000U)
7390#define I2S_TFR_WFP_SHIFT (16U)
7391#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
7392#define I2S_TFR_WCP_MASK (0x80000000U)
7393#define I2S_TFR_WCP_SHIFT (31U)
7394/*! WCP - Write Channel Pointer
7395 * 0b0..No effect.
7396 * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
7397 */
7398#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
7399/*! @} */
7400
7401/* The count of I2S_TFR */
7402#define I2S_TFR_COUNT (2U)
7403
7404/*! @name TMR - SAI Transmit Mask Register */
7405/*! @{ */
7406#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
7407#define I2S_TMR_TWM_SHIFT (0U)
7408/*! TWM - Transmit Word Mask
7409 * 0b00000000000000000000000000000000..Word N is enabled.
7410 * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.
7411 */
7412#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
7413/*! @} */
7414
7415/*! @name RCSR - SAI Receive Control Register */
7416/*! @{ */
7417#define I2S_RCSR_FRDE_MASK (0x1U)
7418#define I2S_RCSR_FRDE_SHIFT (0U)
7419/*! FRDE - FIFO Request DMA Enable
7420 * 0b0..Disables the DMA request.
7421 * 0b1..Enables the DMA request.
7422 */
7423#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
7424#define I2S_RCSR_FWDE_MASK (0x2U)
7425#define I2S_RCSR_FWDE_SHIFT (1U)
7426/*! FWDE - FIFO Warning DMA Enable
7427 * 0b0..Disables the DMA request.
7428 * 0b1..Enables the DMA request.
7429 */
7430#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
7431#define I2S_RCSR_FRIE_MASK (0x100U)
7432#define I2S_RCSR_FRIE_SHIFT (8U)
7433/*! FRIE - FIFO Request Interrupt Enable
7434 * 0b0..Disables the interrupt.
7435 * 0b1..Enables the interrupt.
7436 */
7437#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
7438#define I2S_RCSR_FWIE_MASK (0x200U)
7439#define I2S_RCSR_FWIE_SHIFT (9U)
7440/*! FWIE - FIFO Warning Interrupt Enable
7441 * 0b0..Disables the interrupt.
7442 * 0b1..Enables the interrupt.
7443 */
7444#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
7445#define I2S_RCSR_FEIE_MASK (0x400U)
7446#define I2S_RCSR_FEIE_SHIFT (10U)
7447/*! FEIE - FIFO Error Interrupt Enable
7448 * 0b0..Disables the interrupt.
7449 * 0b1..Enables the interrupt.
7450 */
7451#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
7452#define I2S_RCSR_SEIE_MASK (0x800U)
7453#define I2S_RCSR_SEIE_SHIFT (11U)
7454/*! SEIE - Sync Error Interrupt Enable
7455 * 0b0..Disables interrupt.
7456 * 0b1..Enables interrupt.
7457 */
7458#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
7459#define I2S_RCSR_WSIE_MASK (0x1000U)
7460#define I2S_RCSR_WSIE_SHIFT (12U)
7461/*! WSIE - Word Start Interrupt Enable
7462 * 0b0..Disables interrupt.
7463 * 0b1..Enables interrupt.
7464 */
7465#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
7466#define I2S_RCSR_FRF_MASK (0x10000U)
7467#define I2S_RCSR_FRF_SHIFT (16U)
7468/*! FRF - FIFO Request Flag
7469 * 0b0..Receive FIFO watermark not reached.
7470 * 0b1..Receive FIFO watermark has been reached.
7471 */
7472#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
7473#define I2S_RCSR_FWF_MASK (0x20000U)
7474#define I2S_RCSR_FWF_SHIFT (17U)
7475/*! FWF - FIFO Warning Flag
7476 * 0b0..No enabled receive FIFO is full.
7477 * 0b1..Enabled receive FIFO is full.
7478 */
7479#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
7480#define I2S_RCSR_FEF_MASK (0x40000U)
7481#define I2S_RCSR_FEF_SHIFT (18U)
7482/*! FEF - FIFO Error Flag
7483 * 0b0..Receive overflow not detected.
7484 * 0b1..Receive overflow detected.
7485 */
7486#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
7487#define I2S_RCSR_SEF_MASK (0x80000U)
7488#define I2S_RCSR_SEF_SHIFT (19U)
7489/*! SEF - Sync Error Flag
7490 * 0b0..Sync error not detected.
7491 * 0b1..Frame sync error detected.
7492 */
7493#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
7494#define I2S_RCSR_WSF_MASK (0x100000U)
7495#define I2S_RCSR_WSF_SHIFT (20U)
7496/*! WSF - Word Start Flag
7497 * 0b0..Start of word not detected.
7498 * 0b1..Start of word detected.
7499 */
7500#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
7501#define I2S_RCSR_SR_MASK (0x1000000U)
7502#define I2S_RCSR_SR_SHIFT (24U)
7503/*! SR - Software Reset
7504 * 0b0..No effect.
7505 * 0b1..Software reset.
7506 */
7507#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
7508#define I2S_RCSR_FR_MASK (0x2000000U)
7509#define I2S_RCSR_FR_SHIFT (25U)
7510/*! FR - FIFO Reset
7511 * 0b0..No effect.
7512 * 0b1..FIFO reset.
7513 */
7514#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
7515#define I2S_RCSR_BCE_MASK (0x10000000U)
7516#define I2S_RCSR_BCE_SHIFT (28U)
7517/*! BCE - Bit Clock Enable
7518 * 0b0..Receive bit clock is disabled.
7519 * 0b1..Receive bit clock is enabled.
7520 */
7521#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
7522#define I2S_RCSR_DBGE_MASK (0x20000000U)
7523#define I2S_RCSR_DBGE_SHIFT (29U)
7524/*! DBGE - Debug Enable
7525 * 0b0..Receiver is disabled in Debug mode, after completing the current frame.
7526 * 0b1..Receiver is enabled in Debug mode.
7527 */
7528#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
7529#define I2S_RCSR_STOPE_MASK (0x40000000U)
7530#define I2S_RCSR_STOPE_SHIFT (30U)
7531/*! STOPE - Stop Enable
7532 * 0b0..Receiver disabled in Stop mode.
7533 * 0b1..Receiver enabled in Stop mode.
7534 */
7535#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
7536#define I2S_RCSR_RE_MASK (0x80000000U)
7537#define I2S_RCSR_RE_SHIFT (31U)
7538/*! RE - Receiver Enable
7539 * 0b0..Receiver is disabled.
7540 * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
7541 */
7542#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
7543/*! @} */
7544
7545/*! @name RCR1 - SAI Receive Configuration 1 Register */
7546/*! @{ */
7547#define I2S_RCR1_RFW_MASK (0x7U)
7548#define I2S_RCR1_RFW_SHIFT (0U)
7549#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
7550/*! @} */
7551
7552/*! @name RCR2 - SAI Receive Configuration 2 Register */
7553/*! @{ */
7554#define I2S_RCR2_DIV_MASK (0xFFU)
7555#define I2S_RCR2_DIV_SHIFT (0U)
7556#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
7557#define I2S_RCR2_BCD_MASK (0x1000000U)
7558#define I2S_RCR2_BCD_SHIFT (24U)
7559/*! BCD - Bit Clock Direction
7560 * 0b0..Bit clock is generated externally in Slave mode.
7561 * 0b1..Bit clock is generated internally in Master mode.
7562 */
7563#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
7564#define I2S_RCR2_BCP_MASK (0x2000000U)
7565#define I2S_RCR2_BCP_SHIFT (25U)
7566/*! BCP - Bit Clock Polarity
7567 * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
7568 * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
7569 */
7570#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
7571#define I2S_RCR2_MSEL_MASK (0xC000000U)
7572#define I2S_RCR2_MSEL_SHIFT (26U)
7573/*! MSEL - MCLK Select
7574 * 0b00..Bus Clock selected.
7575 * 0b01..Master Clock (MCLK) 1 option selected.
7576 * 0b10..Master Clock (MCLK) 2 option selected.
7577 * 0b11..Master Clock (MCLK) 3 option selected.
7578 */
7579#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
7580#define I2S_RCR2_BCI_MASK (0x10000000U)
7581#define I2S_RCR2_BCI_SHIFT (28U)
7582/*! BCI - Bit Clock Input
7583 * 0b0..No effect.
7584 * 0b1..Internal logic is clocked as if bit clock was externally generated.
7585 */
7586#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
7587#define I2S_RCR2_BCS_MASK (0x20000000U)
7588#define I2S_RCR2_BCS_SHIFT (29U)
7589/*! BCS - Bit Clock Swap
7590 * 0b0..Use the normal bit clock source.
7591 * 0b1..Swap the bit clock source.
7592 */
7593#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
7594#define I2S_RCR2_SYNC_MASK (0xC0000000U)
7595#define I2S_RCR2_SYNC_SHIFT (30U)
7596/*! SYNC - Synchronous Mode
7597 * 0b00..Asynchronous mode.
7598 * 0b01..Synchronous with transmitter.
7599 * 0b10..Synchronous with another SAI receiver.
7600 * 0b11..Synchronous with another SAI transmitter.
7601 */
7602#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
7603/*! @} */
7604
7605/*! @name RCR3 - SAI Receive Configuration 3 Register */
7606/*! @{ */
7607#define I2S_RCR3_WDFL_MASK (0x1FU)
7608#define I2S_RCR3_WDFL_SHIFT (0U)
7609#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
7610#define I2S_RCR3_RCE_MASK (0x30000U)
7611#define I2S_RCR3_RCE_SHIFT (16U)
7612#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
7613#define I2S_RCR3_CFR_MASK (0x3000000U)
7614#define I2S_RCR3_CFR_SHIFT (24U)
7615#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
7616/*! @} */
7617
7618/*! @name RCR4 - SAI Receive Configuration 4 Register */
7619/*! @{ */
7620#define I2S_RCR4_FSD_MASK (0x1U)
7621#define I2S_RCR4_FSD_SHIFT (0U)
7622/*! FSD - Frame Sync Direction
7623 * 0b0..Frame Sync is generated externally in Slave mode.
7624 * 0b1..Frame Sync is generated internally in Master mode.
7625 */
7626#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
7627#define I2S_RCR4_FSP_MASK (0x2U)
7628#define I2S_RCR4_FSP_SHIFT (1U)
7629/*! FSP - Frame Sync Polarity
7630 * 0b0..Frame sync is active high.
7631 * 0b1..Frame sync is active low.
7632 */
7633#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
7634#define I2S_RCR4_ONDEM_MASK (0x4U)
7635#define I2S_RCR4_ONDEM_SHIFT (2U)
7636/*! ONDEM - On Demand Mode
7637 * 0b0..Internal frame sync is generated continuously.
7638 * 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
7639 */
7640#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
7641#define I2S_RCR4_FSE_MASK (0x8U)
7642#define I2S_RCR4_FSE_SHIFT (3U)
7643/*! FSE - Frame Sync Early
7644 * 0b0..Frame sync asserts with the first bit of the frame.
7645 * 0b1..Frame sync asserts one bit before the first bit of the frame.
7646 */
7647#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
7648#define I2S_RCR4_MF_MASK (0x10U)
7649#define I2S_RCR4_MF_SHIFT (4U)
7650/*! MF - MSB First
7651 * 0b0..LSB is received first.
7652 * 0b1..MSB is received first.
7653 */
7654#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
7655#define I2S_RCR4_SYWD_MASK (0x1F00U)
7656#define I2S_RCR4_SYWD_SHIFT (8U)
7657#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
7658#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
7659#define I2S_RCR4_FRSZ_SHIFT (16U)
7660#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
7661#define I2S_RCR4_FPACK_MASK (0x3000000U)
7662#define I2S_RCR4_FPACK_SHIFT (24U)
7663/*! FPACK - FIFO Packing Mode
7664 * 0b00..FIFO packing is disabled
7665 * 0b01..Reserved.
7666 * 0b10..8-bit FIFO packing is enabled
7667 * 0b11..16-bit FIFO packing is enabled
7668 */
7669#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
7670#define I2S_RCR4_FCOMB_MASK (0xC000000U)
7671#define I2S_RCR4_FCOMB_SHIFT (26U)
7672/*! FCOMB - FIFO Combine Mode
7673 * 0b00..FIFO combine mode disabled.
7674 * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
7675 * 0b10..FIFO combine mode enabled on FIFO reads (by software).
7676 * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
7677 */
7678#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
7679#define I2S_RCR4_FCONT_MASK (0x10000000U)
7680#define I2S_RCR4_FCONT_SHIFT (28U)
7681/*! FCONT - FIFO Continue on Error
7682 * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
7683 * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
7684 */
7685#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
7686/*! @} */
7687
7688/*! @name RCR5 - SAI Receive Configuration 5 Register */
7689/*! @{ */
7690#define I2S_RCR5_FBT_MASK (0x1F00U)
7691#define I2S_RCR5_FBT_SHIFT (8U)
7692#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
7693#define I2S_RCR5_W0W_MASK (0x1F0000U)
7694#define I2S_RCR5_W0W_SHIFT (16U)
7695#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
7696#define I2S_RCR5_WNW_MASK (0x1F000000U)
7697#define I2S_RCR5_WNW_SHIFT (24U)
7698#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
7699/*! @} */
7700
7701/*! @name RDR - SAI Receive Data Register */
7702/*! @{ */
7703#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
7704#define I2S_RDR_RDR_SHIFT (0U)
7705#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
7706/*! @} */
7707
7708/* The count of I2S_RDR */
7709#define I2S_RDR_COUNT (2U)
7710
7711/*! @name RFR - SAI Receive FIFO Register */
7712/*! @{ */
7713#define I2S_RFR_RFP_MASK (0xFU)
7714#define I2S_RFR_RFP_SHIFT (0U)
7715#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
7716#define I2S_RFR_RCP_MASK (0x8000U)
7717#define I2S_RFR_RCP_SHIFT (15U)
7718/*! RCP - Receive Channel Pointer
7719 * 0b0..No effect.
7720 * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
7721 */
7722#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
7723#define I2S_RFR_WFP_MASK (0xF0000U)
7724#define I2S_RFR_WFP_SHIFT (16U)
7725#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
7726/*! @} */
7727
7728/* The count of I2S_RFR */
7729#define I2S_RFR_COUNT (2U)
7730
7731/*! @name RMR - SAI Receive Mask Register */
7732/*! @{ */
7733#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
7734#define I2S_RMR_RWM_SHIFT (0U)
7735/*! RWM - Receive Word Mask
7736 * 0b00000000000000000000000000000000..Word N is enabled.
7737 * 0b00000000000000000000000000000001..Word N is masked.
7738 */
7739#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
7740/*! @} */
7741
7742
7743/*!
7744 * @}
7745 */ /* end of group I2S_Register_Masks */
7746
7747
7748/* I2S - Peripheral instance base addresses */
7749/** Peripheral I2S0 base address */
7750#define I2S0_BASE (0x4003D000u)
7751/** Peripheral I2S0 base pointer */
7752#define I2S0 ((I2S_Type *)I2S0_BASE)
7753/** Array initializer of I2S peripheral base addresses */
7754#define I2S_BASE_ADDRS { I2S0_BASE }
7755/** Array initializer of I2S peripheral base pointers */
7756#define I2S_BASE_PTRS { I2S0 }
7757/** Interrupt vectors for the I2S peripheral type */
7758#define I2S_RX_IRQS { I2S0_IRQn }
7759#define I2S_TX_IRQS { I2S0_IRQn }
7760
7761/*!
7762 * @}
7763 */ /* end of group I2S_Peripheral_Access_Layer */
7764
7765
7766/* ----------------------------------------------------------------------------
7767 -- LLWU Peripheral Access Layer
7768 ---------------------------------------------------------------------------- */
7769
7770/*!
7771 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
7772 * @{
7773 */
7774
7775/** LLWU - Register Layout Typedef */
7776typedef struct {
7777 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
7778 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
7779 __IO uint32_t PE1; /**< Pin Enable 1 register, offset: 0x8 */
7780 __IO uint32_t PE2; /**< Pin Enable 2 register, offset: 0xC */
7781 uint8_t RESERVED_0[8];
7782 __IO uint32_t ME; /**< Module Interrupt Enable register, offset: 0x18 */
7783 __IO uint32_t DE; /**< Module DMA/Trigger Enable register, offset: 0x1C */
7784 __IO uint32_t PF; /**< Pin Flag register, offset: 0x20 */
7785 uint8_t RESERVED_1[12];
7786 __IO uint32_t FILT; /**< Pin Filter register, offset: 0x30 */
7787 uint8_t RESERVED_2[4];
7788 __IO uint32_t PDC1; /**< Pin DMA/Trigger Configuration 1 register, offset: 0x38 */
7789 __IO uint32_t PDC2; /**< Pin DMA/Trigger Configuration 2 register, offset: 0x3C */
7790 uint8_t RESERVED_3[8];
7791 __IO uint32_t FDC; /**< Pin Filter DMA/Trigger Configuration register, offset: 0x48 */
7792 uint8_t RESERVED_4[4];
7793 __IO uint32_t PMC; /**< Pin Mode Configuration register, offset: 0x50 */
7794 uint8_t RESERVED_5[4];
7795 __IO uint32_t FMC; /**< Pin Filter Mode Configuration register, offset: 0x58 */
7796} LLWU_Type;
7797
7798/* ----------------------------------------------------------------------------
7799 -- LLWU Register Masks
7800 ---------------------------------------------------------------------------- */
7801
7802/*!
7803 * @addtogroup LLWU_Register_Masks LLWU Register Masks
7804 * @{
7805 */
7806
7807/*! @name VERID - Version ID Register */
7808/*! @{ */
7809#define LLWU_VERID_FEATURE_MASK (0xFFFFU)
7810#define LLWU_VERID_FEATURE_SHIFT (0U)
7811/*! FEATURE - Feature Specification Number
7812 * 0b0000000000000000..Standard features implemented
7813 * 0b0000000000000001..Support for DMA/Trigger generation from wakeup pins and filters enabled. Support for
7814 * external pin/filter detection during all power modes enabled.
7815 */
7816#define LLWU_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_FEATURE_SHIFT)) & LLWU_VERID_FEATURE_MASK)
7817#define LLWU_VERID_MINOR_MASK (0xFF0000U)
7818#define LLWU_VERID_MINOR_SHIFT (16U)
7819#define LLWU_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_MINOR_SHIFT)) & LLWU_VERID_MINOR_MASK)
7820#define LLWU_VERID_MAJOR_MASK (0xFF000000U)
7821#define LLWU_VERID_MAJOR_SHIFT (24U)
7822#define LLWU_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_MAJOR_SHIFT)) & LLWU_VERID_MAJOR_MASK)
7823/*! @} */
7824
7825/*! @name PARAM - Parameter Register */
7826/*! @{ */
7827#define LLWU_PARAM_FILTERS_MASK (0xFFU)
7828#define LLWU_PARAM_FILTERS_SHIFT (0U)
7829#define LLWU_PARAM_FILTERS(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_FILTERS_SHIFT)) & LLWU_PARAM_FILTERS_MASK)
7830#define LLWU_PARAM_DMAS_MASK (0xFF00U)
7831#define LLWU_PARAM_DMAS_SHIFT (8U)
7832#define LLWU_PARAM_DMAS(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_DMAS_SHIFT)) & LLWU_PARAM_DMAS_MASK)
7833#define LLWU_PARAM_MODULES_MASK (0xFF0000U)
7834#define LLWU_PARAM_MODULES_SHIFT (16U)
7835#define LLWU_PARAM_MODULES(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_MODULES_SHIFT)) & LLWU_PARAM_MODULES_MASK)
7836#define LLWU_PARAM_PINS_MASK (0xFF000000U)
7837#define LLWU_PARAM_PINS_SHIFT (24U)
7838#define LLWU_PARAM_PINS(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_PINS_SHIFT)) & LLWU_PARAM_PINS_MASK)
7839/*! @} */
7840
7841/*! @name PE1 - Pin Enable 1 register */
7842/*! @{ */
7843#define LLWU_PE1_WUPE0_MASK (0x3U)
7844#define LLWU_PE1_WUPE0_SHIFT (0U)
7845/*! WUPE0 - Wakeup pin enable for LLWU_Pn
7846 * 0b00..External input pin disabled as wakeup input
7847 * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high
7848 * level detection when configured as trigger request
7849 * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low
7850 * level detection when configured as trigger request
7851 * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
7852 */
7853#define LLWU_PE1_WUPE0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
7854#define LLWU_PE1_WUPE1_MASK (0xCU)
7855#define LLWU_PE1_WUPE1_SHIFT (2U)
7856/*! WUPE1 - Wakeup pin enable for LLWU_Pn
7857 * 0b00..External input pin disabled as wakeup input
7858 * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high
7859 * level detection when configured as trigger request
7860 * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low
7861 * level detection when configured as trigger request
7862 * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
7863 */
7864#define LLWU_PE1_WUPE1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
7865#define LLWU_PE1_WUPE2_MASK (0x30U)
7866#define LLWU_PE1_WUPE2_SHIFT (4U)
7867/*! WUPE2 - Wakeup pin enable for LLWU_Pn
7868 * 0b00..External input pin disabled as wakeup input
7869 * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high
7870 * level detection when configured as trigger request