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1/*
2** ###################################################################
3** Version: rev. 1.0, 2019-04-22
4** Build: b200927
5**
6** Abstract:
7** Chip specific module features.
8**
9** Copyright 2016 Freescale Semiconductor, Inc.
10** Copyright 2016-2020 NXP
11** All rights reserved.
12**
13** SPDX-License-Identifier: BSD-3-Clause
14**
15** http: www.nxp.com
16** mail: [email protected]
17**
18** Revisions:
19** - rev. 1.0 (2019-04-22)
20** Initial version.
21**
22** ###################################################################
23*/
24
25#ifndef _K32L3A60_cm4_FEATURES_H_
26#define _K32L3A60_cm4_FEATURES_H_
27
28/* SOC module features */
29
30/* @brief AXBS availability on the SoC. */
31#define FSL_FEATURE_SOC_AXBS_COUNT (1)
32/* @brief CAU3 availability on the SoC. */
33#define FSL_FEATURE_SOC_CAU3_COUNT (1)
34/* @brief CRC availability on the SoC. */
35#define FSL_FEATURE_SOC_CRC_COUNT (1)
36/* @brief DMAMUX availability on the SoC. */
37#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
38/* @brief EDMA availability on the SoC. */
39#define FSL_FEATURE_SOC_EDMA_COUNT (1)
40/* @brief EMVSIM availability on the SoC. */
41#define FSL_FEATURE_SOC_EMVSIM_COUNT (1)
42/* @brief EWM availability on the SoC. */
43#define FSL_FEATURE_SOC_EWM_COUNT (1)
44/* @brief FB availability on the SoC. */
45#define FSL_FEATURE_SOC_FB_COUNT (1)
46/* @brief FLASH availability on the SoC. */
47#define FSL_FEATURE_SOC_FLASH_COUNT (1)
48/* @brief FLEXIO availability on the SoC. */
49#define FSL_FEATURE_SOC_FLEXIO_COUNT (1)
50/* @brief GPIO availability on the SoC. */
51#define FSL_FEATURE_SOC_GPIO_COUNT (5)
52/* @brief I2S availability on the SoC. */
53#define FSL_FEATURE_SOC_I2S_COUNT (1)
54/* @brief LLWU availability on the SoC. */
55#define FSL_FEATURE_SOC_LLWU_COUNT (2)
56/* @brief LPADC availability on the SoC. */
57#define FSL_FEATURE_SOC_LPADC_COUNT (1)
58/* @brief LPCMP availability on the SoC. */
59#define FSL_FEATURE_SOC_LPCMP_COUNT (2)
60/* @brief LPDAC availability on the SoC. */
61#define FSL_FEATURE_SOC_LPDAC_COUNT (1)
62/* @brief LPI2C availability on the SoC. */
63#define FSL_FEATURE_SOC_LPI2C_COUNT (4)
64/* @brief LPIT availability on the SoC. */
65#define FSL_FEATURE_SOC_LPIT_COUNT (2)
66/* @brief LPSPI availability on the SoC. */
67#define FSL_FEATURE_SOC_LPSPI_COUNT (4)
68/* @brief LPTMR availability on the SoC. */
69#define FSL_FEATURE_SOC_LPTMR_COUNT (3)
70/* @brief LPUART availability on the SoC. */
71#define FSL_FEATURE_SOC_LPUART_COUNT (4)
72/* @brief MCM availability on the SoC. */
73#define FSL_FEATURE_SOC_MCM_COUNT (1)
74/* @brief MSCM availability on the SoC. */
75#define FSL_FEATURE_SOC_MSCM_COUNT (1)
76/* @brief MU availability on the SoC. */
77#define FSL_FEATURE_SOC_MU_COUNT (1)
78/* @brief PCC availability on the SoC. */
79#define FSL_FEATURE_SOC_PCC_COUNT (2)
80/* @brief PORT availability on the SoC. */
81#define FSL_FEATURE_SOC_PORT_COUNT (5)
82/* @brief RTC availability on the SoC. */
83#define FSL_FEATURE_SOC_RTC_COUNT (1)
84/* @brief SCG availability on the SoC. */
85#define FSL_FEATURE_SOC_SCG_COUNT (1)
86/* @brief SEMA42 availability on the SoC. */
87#define FSL_FEATURE_SOC_SEMA42_COUNT (2)
88/* @brief SIM availability on the SoC. */
89#define FSL_FEATURE_SOC_SIM_COUNT (1)
90/* @brief SMC availability on the SoC. */
91#define FSL_FEATURE_SOC_SMC_COUNT (2)
92/* @brief SPM availability on the SoC. */
93#define FSL_FEATURE_SOC_SPM_COUNT (1)
94/* @brief TPM availability on the SoC. */
95#define FSL_FEATURE_SOC_TPM_COUNT (4)
96/* @brief TRGMUX availability on the SoC. */
97#define FSL_FEATURE_SOC_TRGMUX_COUNT (2)
98/* @brief TRNG availability on the SoC. */
99#define FSL_FEATURE_SOC_TRNG_COUNT (1)
100/* @brief TSTMR availability on the SoC. */
101#define FSL_FEATURE_SOC_TSTMR_COUNT (1)
102/* @brief USB availability on the SoC. */
103#define FSL_FEATURE_SOC_USB_COUNT (1)
104/* @brief USBVREG availability on the SoC. */
105#define FSL_FEATURE_SOC_USBVREG_COUNT (1)
106/* @brief USDHC availability on the SoC. */
107#define FSL_FEATURE_SOC_USDHC_COUNT (1)
108/* @brief VREF availability on the SoC. */
109#define FSL_FEATURE_SOC_VREF_COUNT (1)
110/* @brief WDOG availability on the SoC. */
111#define FSL_FEATURE_SOC_WDOG_COUNT (2)
112/* @brief XRDC availability on the SoC. */
113#define FSL_FEATURE_SOC_XRDC_COUNT (1)
114
115/* AXBS module features */
116
117/* No feature definitions */
118
119/* CRC module features */
120
121/* @brief Has data register with name CRC */
122#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
123
124/* EDMA module features */
125
126/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
127#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16)
128/* @brief Total number of DMA channels on all modules. */
129#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (16)
130/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
131#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
132/* @brief Has DMA_Error interrupt vector. */
133#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
134/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
135#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16)
136/* @brief Channel IRQ entry shared offset. */
137#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (0)
138/* @brief If 8 bytes transfer supported. */
139#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0)
140/* @brief If 16 bytes transfer supported. */
141#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1)
142/* @brief If 32 bytes transfer supported. */
143#define FSL_FEATURE_EDMA_SUPPORT_32_BYTES_TRANSFER (1)
144
145/* DMAMUX module features */
146
147/* @brief Number of DMA channels (related to number of register CHCFGn). */
148#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16)
149/* @brief Total number of DMA channels on all modules. */
150#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (32)
151/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
152#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
153/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */
154#define FSL_FEATURE_DMAMUX_HAS_A_ON (1)
155/* @brief Register CHCFGn width. */
156#define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (32)
157
158/* EWM module features */
159
160/* @brief Has clock select (register CLKCTRL). */
161#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0)
162/* @brief Has clock prescaler (register CLKPRESCALER). */
163#define FSL_FEATURE_EWM_HAS_PRESCALER (1)
164
165/* FB module features */
166
167/* No feature definitions */
168
169/* FLEXIO module features */
170
171/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
172#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
173/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
174#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
175/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
176#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
177/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
178#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1)
179/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
180#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1)
181/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
182#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1)
183/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
184#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1)
185/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
186#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1)
187/* @brief Reset value of the FLEXIO_VERID register */
188#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001)
189/* @brief Reset value of the FLEXIO_PARAM register */
190#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808)
191/* @brief Flexio DMA request base channel */
192#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0)
193
194/* FLASH module features */
195
196/* @brief Current core ID. */
197#define FSL_FEATURE_FLASH_CURRENT_CORE_ID (0)
198/* @brief Is of type FTFA. */
199#define FSL_FEATURE_FLASH_IS_FTFA (0)
200/* @brief Is of type FTFE. */
201#define FSL_FEATURE_FLASH_IS_FTFE (1)
202/* @brief Is of type FTFL. */
203#define FSL_FEATURE_FLASH_IS_FTFL (0)
204/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
205#define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
206/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
207#define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
208/* @brief Has EEPROM region protection (register FEPROT). */
209#define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
210/* @brief Has data flash region protection (register FDPROT). */
211#define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
212/* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
213#define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
214/* @brief Has flash cache control in FMC module. */
215#define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
216/* @brief Has flash cache control in MCM module. */
217#define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
218/* @brief Has flash cache control in MSCM module. */
219#define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (1)
220/* @brief Has prefetch speculation control in flash, such as kv5x. */
221#define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
222/* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for others. */
223#define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (1)
224/* @brief P-Flash start address. */
225#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
226/* @brief P-Flash block count. */
227#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
228/* @brief P-Flash block size. */
229#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
230/* @brief P-Flash sector size. */
231#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
232/* @brief P-Flash write unit size. */
233#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
234/* @brief P-Flash data path width. */
235#define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
236/* @brief P-Flash block swap feature. */
237#define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
238/* @brief P-Flash protection region count. */
239#define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (64)
240/* @brief Has multiple flash. */
241#define FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH (1)
242/* @brief Flash memory count. */
243#define FSL_FEATURE_FLASH_MEMORY_COUNT (2)
244/* @brief P-Flash start address. */
245#define FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS (0x01000000)
246/* @brief P-Flash block count. */
247#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT (1)
248/* @brief P-Flash block size. */
249#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE (262144)
250/* @brief P-Flash sector size. */
251#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE (2048)
252/* @brief P-Flash write unit size. */
253#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE (8)
254/* @brief P-Flash data path width. */
255#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_DATA_PATH_WIDTH (8)
256/* @brief P-Flash protection region count. */
257#define FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT (16)
258/* @brief P-Flash block swap feature. */
259#define FSL_FEATURE_FLASH_HAS_1_PFLASH_BLOCK_SWAP (0)
260/* @brief Has FlexNVM memory. */
261#define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
262/* @brief Has FlexNVM alias. */
263#define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0)
264/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
265#define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
266/* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */
267#define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000)
268/* @brief FlexNVM block count. */
269#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
270/* @brief FlexNVM block size. */
271#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
272/* @brief FlexNVM sector size. */
273#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
274/* @brief FlexNVM write unit size. */
275#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
276/* @brief FlexNVM data path width. */
277#define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
278/* @brief Has FlexRAM memory. */
279#define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
280/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
281#define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x48000000)
282/* @brief FlexRAM size. */
283#define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
284/* @brief Has 0x00 Read 1s Block command. */
285#define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
286/* @brief Flash 1 has 0x00 Read 1s Block command. */
287#define FSL_FEATURE_FLASH_HAS_1_READ_1S_BLOCK_CMD (0)
288/* @brief Has 0x01 Read 1s Section command. */
289#define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
290/* @brief Has 0x02 Program Check command. */
291#define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
292/* @brief Has 0x03 Read Resource command. */
293#define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (0)
294/* @brief Has 0x06 Program Longword command. */
295#define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
296/* @brief Has 0x07 Program Phrase command. */
297#define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
298/* @brief Has 0x08 Erase Flash Block command. */
299#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
300/* @brief Flash 1 has 0x08 Erase Flash Block command. */
301#define FSL_FEATURE_FLASH_HAS_1_ERASE_FLASH_BLOCK_CMD (0)
302/* @brief Has 0x09 Erase Flash Sector command. */
303#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
304/* @brief Has 0x0B Program Section command. */
305#define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
306/* @brief Has 0x0C Generate CRC signature for selected program flash sectors. */
307#define FSL_FEATURE_FLASH_HAS_GENERATE_CRC_CMD (1)
308/* @brief Has 0x40 Read 1s All Blocks command. */
309#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
310/* @brief Has 0x41 Read Once command. */
311#define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
312/* @brief Has 0x43 Program Once command. */
313#define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
314/* @brief Has 0x44 Erase All Blocks command. */
315#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
316/* @brief Has 0x45 Verify Backdoor Access Key command. */
317#define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
318/* @brief Has 0x46 Swap Control command. */
319#define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
320/* @brief Flash 1 has 0x46 Swap Control command. */
321#define FSL_FEATURE_FLASH_HAS_1_SWAP_CONTROL_CMD (0)
322/* @brief Has 0x49 Erase All Blocks Unsecure command. */
323#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
324/* @brief Has 0x4A Read 1s All Execute-only Segments command. */
325#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
326/* @brief Has 0x4B Erase All Execute-only Segments command. */
327#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
328/* @brief Has 0x80 Program Partition command. */
329#define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
330/* @brief Has 0x81 Set FlexRAM Function command. */
331#define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
332/* @brief P-Flash Erase/Read 1st all block command address alignment. */
333#define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
334/* @brief P-Flash Erase sector command address alignment. */
335#define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
336/* @brief P-Flash Erase sector command address alignment. */
337#define FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT (8)
338/* @brief P-Flash Program/Verify section command address alignment. */
339#define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
340/* @brief P-Flash Program/Verify section command address alignment. */
341#define FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT (8)
342/* @brief P-Flash Read resource command address alignment. */
343#define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
344/* @brief P-Flash Program check command address alignment. */
345#define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
346/* @brief P-Flash Program check command address alignment. */
347#define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16)
348/* @brief P-Flash 1 Program check command address alignment. */
349#define FSL_FEATURE_FLASH_PFLASH_1_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
350/* @brief FlexNVM Erase/Read 1st all block command address alignment. */
351#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
352/* @brief FlexNVM Erase sector command address alignment. */
353#define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
354/* @brief FlexNVM Rrogram/Verify section command address alignment. */
355#define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
356/* @brief FlexNVM Read resource command address alignment. */
357#define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
358/* @brief FlexNVM Program check command address alignment. */
359#define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
360/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
361#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU)
362/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
363#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU)
364/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
365#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU)
366/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
367#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU)
368/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
369#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU)
370/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
371#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU)
372/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
373#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU)
374/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
375#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU)
376/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
377#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU)
378/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
379#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU)
380/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
381#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU)
382/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
383#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU)
384/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
385#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU)
386/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
387#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU)
388/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
389#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU)
390/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
391#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU)
392/* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
393#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
394/* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
395#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
396/* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
397#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
398/* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
399#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
400/* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
401#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
402/* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
403#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
404/* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
405#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
406/* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
407#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
408/* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
409#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
410/* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
411#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
412/* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
413#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
414/* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
415#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
416/* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
417#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
418/* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
419#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
420/* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
421#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
422/* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
423#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
424
425/* GPIO module features */
426
427/* @brief Has GPIO attribute checker register (GACR). */
428#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0)
429
430/* SAI module features */
431
432/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
433#define FSL_FEATURE_SAI_FIFO_COUNT (8)
434/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
435#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2)
436/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
437#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
438/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
439#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
440/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
441#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
442/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
443#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
444/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
445#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
446/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
447#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
448/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
449#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
450/* @brief Interrupt source number */
451#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1)
452/* @brief Has register of MCR. */
453#define FSL_FEATURE_SAI_HAS_MCR (0)
454/* @brief Has bit field MICS of the MCR register. */
455#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1)
456/* @brief Has register of MDR */
457#define FSL_FEATURE_SAI_HAS_MDR (0)
458/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
459#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0)
460/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */
461#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0)
462/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */
463#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1)
464
465/* LLWU module features */
466
467/* @brief Maximum number of pins connected to LLWU device. */
468#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (32)
469/* @brief Maximum number of internal modules connected to LLWU device. */
470#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
471/* @brief Number of digital filters. */
472#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
473/* @brief Has MF register. */
474#define FSL_FEATURE_LLWU_HAS_MF (0)
475/* @brief Has PF register. */
476#define FSL_FEATURE_LLWU_HAS_PF (1)
477/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
478#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
479/* @brief Has no internal module wakeup flag register. */
480#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (1)
481/* @brief Has external pin 0 connected to LLWU device. */
482#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
483/* @brief Index of port of external pin. */
484#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOA_IDX)
485/* @brief Number of external pin port on specified port. */
486#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
487/* @brief Has external pin 1 connected to LLWU device. */
488#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
489/* @brief Index of port of external pin. */
490#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOA_IDX)
491/* @brief Number of external pin port on specified port. */
492#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
493/* @brief Has external pin 2 connected to LLWU device. */
494#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
495/* @brief Index of port of external pin. */
496#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOA_IDX)
497/* @brief Number of external pin port on specified port. */
498#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (22)
499/* @brief Has external pin 3 connected to LLWU device. */
500#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
501/* @brief Index of port of external pin. */
502#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
503/* @brief Number of external pin port on specified port. */
504#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (30)
505/* @brief Has external pin 4 connected to LLWU device. */
506#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
507/* @brief Index of port of external pin. */
508#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOB_IDX)
509/* @brief Number of external pin port on specified port. */
510#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (1)
511/* @brief Has external pin 5 connected to LLWU device. */
512#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
513/* @brief Index of port of external pin. */
514#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
515/* @brief Number of external pin port on specified port. */
516#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (2)
517/* @brief Has external pin 6 connected to LLWU device. */
518#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
519/* @brief Index of port of external pin. */
520#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOB_IDX)
521/* @brief Number of external pin port on specified port. */
522#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (4)
523/* @brief Has external pin 7 connected to LLWU device. */
524#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
525/* @brief Index of port of external pin. */
526#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOB_IDX)
527/* @brief Number of external pin port on specified port. */
528#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (6)
529/* @brief Has external pin 8 connected to LLWU device. */
530#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
531/* @brief Index of port of external pin. */
532#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX)
533/* @brief Number of external pin port on specified port. */
534#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (7)
535/* @brief Has external pin 9 connected to LLWU device. */
536#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
537/* @brief Index of port of external pin. */
538#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOB_IDX)
539/* @brief Number of external pin port on specified port. */
540#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (8)
541/* @brief Has external pin 10 connected to LLWU device. */
542#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
543/* @brief Index of port of external pin. */
544#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOB_IDX)
545/* @brief Number of external pin port on specified port. */
546#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (16)
547/* @brief Has external pin 11 connected to LLWU device. */
548#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
549/* @brief Index of port of external pin. */
550#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOB_IDX)
551/* @brief Number of external pin port on specified port. */
552#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (20)
553/* @brief Has external pin 12 connected to LLWU device. */
554#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
555/* @brief Index of port of external pin. */
556#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOB_IDX)
557/* @brief Number of external pin port on specified port. */
558#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (22)
559/* @brief Has external pin 13 connected to LLWU device. */
560#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
561/* @brief Index of port of external pin. */
562#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOB_IDX)
563/* @brief Number of external pin port on specified port. */
564#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (25)
565/* @brief Has external pin 14 connected to LLWU device. */
566#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
567/* @brief Index of port of external pin. */
568#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOB_IDX)
569/* @brief Number of external pin port on specified port. */
570#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (28)
571/* @brief Has external pin 15 connected to LLWU device. */
572#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
573/* @brief Index of port of external pin. */
574#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX)
575/* @brief Number of external pin port on specified port. */
576#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7)
577/* @brief Has external pin 16 connected to LLWU device. */
578#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1)
579/* @brief Index of port of external pin. */
580#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOC_IDX)
581/* @brief Number of external pin port on specified port. */
582#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (9)
583/* @brief Has external pin 17 connected to LLWU device. */
584#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1)
585/* @brief Index of port of external pin. */
586#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOC_IDX)
587/* @brief Number of external pin port on specified port. */
588#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (11)
589/* @brief Has external pin 18 connected to LLWU device. */
590#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1)
591/* @brief Index of port of external pin. */
592#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOC_IDX)
593/* @brief Number of external pin port on specified port. */
594#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (12)
595/* @brief Has external pin 19 connected to LLWU device. */
596#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1)
597/* @brief Index of port of external pin. */
598#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOD_IDX)
599/* @brief Number of external pin port on specified port. */
600#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (8)
601/* @brief Has external pin 20 connected to LLWU device. */
602#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1)
603/* @brief Index of port of external pin. */
604#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOD_IDX)
605/* @brief Number of external pin port on specified port. */
606#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (10)
607/* @brief Has external pin 21 connected to LLWU device. */
608#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1)
609/* @brief Index of port of external pin. */
610#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX)
611/* @brief Number of external pin port on specified port. */
612#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (1)
613/* @brief Has external pin 22 connected to LLWU device. */
614#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1)
615/* @brief Index of port of external pin. */
616#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOE_IDX)
617/* @brief Number of external pin port on specified port. */
618#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (3)
619/* @brief Has external pin 23 connected to LLWU device. */
620#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1)
621/* @brief Index of port of external pin. */
622#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOE_IDX)
623/* @brief Number of external pin port on specified port. */
624#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (8)
625/* @brief Has external pin 24 connected to LLWU device. */
626#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1)
627/* @brief Index of port of external pin. */
628#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOE_IDX)
629/* @brief Number of external pin port on specified port. */
630#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (9)
631/* @brief Has external pin 25 connected to LLWU device. */
632#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1)
633/* @brief Index of port of external pin. */
634#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOE_IDX)
635/* @brief Number of external pin port on specified port. */
636#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (10)
637/* @brief Has external pin 26 connected to LLWU device. */
638#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (1)
639/* @brief Index of port of external pin. */
640#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (GPIOE_IDX)
641/* @brief Number of external pin port on specified port. */
642#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (12)
643/* @brief Has external pin 27 connected to LLWU device. */
644#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
645/* @brief Index of port of external pin. */
646#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
647/* @brief Number of external pin port on specified port. */
648#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
649/* @brief Has external pin 28 connected to LLWU device. */
650#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
651/* @brief Index of port of external pin. */
652#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
653/* @brief Number of external pin port on specified port. */
654#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
655/* @brief Has external pin 29 connected to LLWU device. */
656#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
657/* @brief Index of port of external pin. */
658#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
659/* @brief Number of external pin port on specified port. */
660#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
661/* @brief Has external pin 30 connected to LLWU device. */
662#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
663/* @brief Index of port of external pin. */
664#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
665/* @brief Number of external pin port on specified port. */
666#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
667/* @brief Has external pin 31 connected to LLWU device. */
668#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
669/* @brief Index of port of external pin. */
670#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
671/* @brief Number of external pin port on specified port. */
672#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
673/* @brief Has internal module 0 connected to LLWU device. */
674#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
675/* @brief Has internal module 1 connected to LLWU device. */
676#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
677/* @brief Has internal module 2 connected to LLWU device. */
678#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
679/* @brief Has internal module 3 connected to LLWU device. */
680#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
681/* @brief Has internal module 4 connected to LLWU device. */
682#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
683/* @brief Has internal module 5 connected to LLWU device. */
684#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
685/* @brief Has internal module 6 connected to LLWU device. */
686#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (1)
687/* @brief Has internal module 7 connected to LLWU device. */
688#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
689/* @brief Has LLWU_VERID. */
690#define FSL_FEATURE_LLWU_HAS_VERID (1)
691/* @brief Has LLWU_PARAM. */
692#define FSL_FEATURE_LLWU_HAS_PARAM (1)
693/* @brief LLWU register bit width. */
694#define FSL_FEATURE_LLWU_REG_BITWIDTH (32)
695/* @brief Has DMA Enable register LLWU_DE. */
696#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (1)
697
698/* LPADC module features */
699
700/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */
701#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1)
702/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
703#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
704/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
705#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
706/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
707#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (0)
708/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */
709#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (0)
710/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
711#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (0)
712/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
713#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (0)
714/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
715#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (0)
716/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
717#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (0)
718/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
719#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (1)
720/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
721#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (1)
722/* @brief Has calibration (bitfield CFG[CALOFS]). */
723#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (1)
724/* @brief Has offset trim (register OFSTRIM). */
725#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
726
727/* LPDAC module features */
728
729/* @brief FIFO size. */
730#define FSL_FEATURE_LPDAC_FIFO_SIZE (16)
731
732/* LPI2C module features */
733
734/* @brief Has separate DMA RX and TX requests. */
735#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
736/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
737#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
738
739/* LPIT module features */
740
741/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
742#define FSL_FEATURE_LPIT_TIMER_COUNT (4)
743/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
744#define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0)
745/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
746#define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (0)
747
748/* LPSPI module features */
749
750/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
751#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4)
752/* @brief Has separate DMA RX and TX requests. */
753#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
754
755/* LPTMR module features */
756
757/* @brief Has shared interrupt handler with another LPTMR module. */
758#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
759/* @brief Whether LPTMR counter is 32 bits width. */
760#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1)
761/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
762#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1)
763/* @brief Do not has prescaler clock source 1. */
764#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0)
765
766/* LPUART module features */
767
768/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
769#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
770/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
771#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
772/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
773#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
774/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
775#define FSL_FEATURE_LPUART_HAS_FIFO (1)
776/* @brief Has 32-bit register MODIR */
777#define FSL_FEATURE_LPUART_HAS_MODIR (1)
778/* @brief Hardware flow control (RTS, CTS) is supported. */
779#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
780/* @brief Infrared (modulation) is supported. */
781#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
782/* @brief 2 bits long stop bit is available. */
783#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
784/* @brief If 10-bit mode is supported. */
785#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
786/* @brief If 7-bit mode is supported. */
787#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
788/* @brief Baud rate fine adjustment is available. */
789#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
790/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
791#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
792/* @brief Baud rate oversampling is available. */
793#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
794/* @brief Baud rate oversampling is available. */
795#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
796/* @brief Peripheral type. */
797#define FSL_FEATURE_LPUART_IS_SCI (1)
798/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
799#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8)
800/* @brief Supports two match addresses to filter incoming frames. */
801#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
802/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
803#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
804/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
805#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
806/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
807#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
808/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
809#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
810/* @brief Has improved smart card (ISO7816 protocol) support. */
811#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
812/* @brief Has local operation network (CEA709.1-B protocol) support. */
813#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
814/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
815#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
816/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
817#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
818/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
819#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
820/* @brief Has separate DMA RX and TX requests. */
821#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
822/* @brief Has separate RX and TX interrupts. */
823#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
824/* @brief Has LPAURT_PARAM. */
825#define FSL_FEATURE_LPUART_HAS_PARAM (1)
826/* @brief Has LPUART_VERID. */
827#define FSL_FEATURE_LPUART_HAS_VERID (1)
828/* @brief Has LPUART_GLOBAL. */
829#define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
830/* @brief Has LPUART_PINCFG. */
831#define FSL_FEATURE_LPUART_HAS_PINCFG (1)
832
833/* MCM module features */
834
835/* @brief Has L1 cache. */
836#define FSL_FEATURE_HAS_L1CACHE (1)
837
838/* MSCM module features */
839
840/* @brief Number of configuration information for processors. */
841#define FSL_FEATURE_MSCM_HAS_CP_COUNT (2)
842/* @brief Has data cache. */
843#define FSL_FEATURE_MSCM_HAS_DATACACHE (0)
844
845/* MU module features */
846
847/* @brief MU side for current core */
848#define FSL_FEATURE_MU_SIDE_A (1)
849/* @brief MU Has register CCR */
850#define FSL_FEATURE_MU_HAS_CCR (1)
851/* @brief MU Has register SR[RS], BSR[ARS] */
852#define FSL_FEATURE_MU_HAS_SR_RS (0)
853/* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */
854#define FSL_FEATURE_MU_HAS_RESET_INT (1)
855/* @brief MU Has register SR[MURIP] */
856#define FSL_FEATURE_MU_HAS_SR_MURIP (1)
857/* @brief MU Has register SR[HRIP] */
858#define FSL_FEATURE_MU_HAS_SR_HRIP (1)
859/* @brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */
860#define FSL_FEATURE_MU_NO_CLKE (0)
861/* @brief MU does not support NMI, CR[NMI]. */
862#define FSL_FEATURE_MU_NO_NMI (0)
863/* @brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */
864#define FSL_FEATURE_MU_NO_RSTH (0)
865/* @brief MU does not supports MU reset, CR[MUR]. */
866#define FSL_FEATURE_MU_NO_MUR (0)
867/* @brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */
868#define FSL_FEATURE_MU_NO_HR (0)
869/* @brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */
870#define FSL_FEATURE_MU_HAS_HRM (1)
871/* @brief MU does not support check the other core power mode. SR[PM]. */
872#define FSL_FEATURE_MU_NO_PM (0)
873/* @brief MU supports reset assert interrupt. CR[RAIE] or BCR[RAIE]. */
874#define FSL_FEATURE_MU_HAS_RESET_ASSERT_INT (1)
875/* @brief MU supports reset de-assert interrupt. CR[RDIE] or BCR[RDIE]. */
876#define FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT (1)
877
878/* interrupt module features */
879
880/* @brief Lowest interrupt request number. */
881#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
882/* @brief Highest interrupt request number. */
883#define FSL_FEATURE_INTERRUPT_IRQ_MAX (65)
884
885/* PCC module features */
886
887/* @brief Has CLOCK GATE CONTROL bit (e.g PCC_CGC) */
888#define FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL (1)
889
890/* PORT module features */
891
892/* @brief Has control lock (register bit PCR[LK]). */
893#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
894/* @brief Has open drain control (register bit PCR[ODE]). */
895#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
896/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
897#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
898/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */
899#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
900/* @brief Has pull resistor selection available. */
901#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
902/* @brief Has pull resistor enable (register bit PCR[PE]). */
903#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
904/* @brief Has slew rate control (register bit PCR[SRE]). */
905#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
906/* @brief Has passive filter (register bit field PCR[PFE]). */
907#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
908/* @brief Has drive strength control (register bit PCR[DSE]). */
909#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
910/* @brief Defines width of PCR[MUX] field. */
911#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
912/* @brief Has dedicated interrupt vector. */
913#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
914/* @brief Has independent interrupt control(register ICR). */
915#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0)
916/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
917#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (1)
918/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
919#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (1)
920/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
921#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (1)
922
923/* RTC module features */
924
925/* @brief Has wakeup pin. */
926#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
927/* @brief Has wakeup pin selection (bit field CR[WPS]). */
928#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
929/* @brief Has low power features (registers MER, MCLR and MCHR). */
930#define FSL_FEATURE_RTC_HAS_MONOTONIC (1)
931/* @brief Has read/write access control (registers WAR and RAR). */
932#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
933/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
934#define FSL_FEATURE_RTC_HAS_SECURITY (1)
935/* @brief Has RTC_CLKIN available. */
936#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
937/* @brief Has prescaler adjust for LPO. */
938#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1)
939/* @brief Has Clock Pin Enable field. */
940#define FSL_FEATURE_RTC_HAS_CPE (1)
941/* @brief Has Timer Seconds Interrupt Configuration field. */
942#define FSL_FEATURE_RTC_HAS_TSIC (1)
943/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
944#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
945/* @brief Has Tamper Interrupt Register (register TIR). */
946#define FSL_FEATURE_RTC_HAS_TIR (1)
947/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
948#define FSL_FEATURE_RTC_HAS_TIR_TPIE (1)
949/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
950#define FSL_FEATURE_RTC_HAS_TIR_SIE (1)
951/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
952#define FSL_FEATURE_RTC_HAS_TIR_LCIE (1)
953/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
954#define FSL_FEATURE_RTC_HAS_SR_TIDF (1)
955/* @brief Has Tamper Detect Register (register TDR). */
956#define FSL_FEATURE_RTC_HAS_TDR (1)
957/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
958#define FSL_FEATURE_RTC_HAS_TDR_TPF (1)
959/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
960#define FSL_FEATURE_RTC_HAS_TDR_STF (1)
961/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
962#define FSL_FEATURE_RTC_HAS_TDR_LCTF (1)
963/* @brief Has Tamper Time Seconds Register (register TTSR). */
964#define FSL_FEATURE_RTC_HAS_TTSR (1)
965/* @brief Has Pin Configuration Register (register PCR). */
966#define FSL_FEATURE_RTC_HAS_PCR (1)
967/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */
968#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0)
969
970/* SCG module features */
971
972/* @brief Has platform clock divider SCG_CSR[DIVPLAT]. */
973#define FSL_FEATURE_SCG_HAS_DIVPLAT (0)
974/* @brief Has bus clock divider SCG_CSR[DIVBUS]. */
975#define FSL_FEATURE_SCG_HAS_DIVBUS (1)
976/* @brief Has external clock divide ratio SCG_CSR[DIVEXT]. */
977#define FSL_FEATURE_SCG_HAS_DIVEXT (1)
978/* @brief Has OSC capacitor setting SOSCCFG[SC2P ~ SC16P]. */
979#define FSL_FEATURE_SCG_HAS_OSC_SCXP (0)
980/* @brief Has SOSCCSR[SOSCERCLKEN]. */
981#define FSL_FEATURE_SCG_HAS_OSC_ERCLK (0)
982/* @brief Has OSC freq range SOSCCFG[RANGE]. */
983#define FSL_FEATURE_SCG_HAS_SOSC_RANGE (0)
984/* @brief Has CLKOUT configure register SCG_CLKOUTCNFG. */
985#define FSL_FEATURE_SCG_HAS_CLKOUTCNFG (1)
986/* @brief Has SCG_SOSCDIV[SOSCDIV1]. */
987#define FSL_FEATURE_SCG_HAS_SOSCDIV1 (0)
988/* @brief Has SCG_SOSCDIV[SOSCDIV3]. */
989#define FSL_FEATURE_SCG_HAS_SOSCDIV3 (0)
990/* @brief Has SCG_SIRCDIV[SIRCDIV1]. */
991#define FSL_FEATURE_SCG_HAS_SIRCDIV1 (1)
992/* @brief Has SCG_SIRCDIV[SIRCDIV3]. */
993#define FSL_FEATURE_SCG_HAS_SIRCDIV3 (1)
994/* @brief Has SCG_SIRCCSR[LPOPO]. */
995#define FSL_FEATURE_SCG_HAS_SIRC_LPOPO (0)
996/* @brief Has SCG_FIRCDIV[FIRCDIV1]. */
997#define FSL_FEATURE_SCG_HAS_FIRCDIV1 (1)
998/* @brief Has SCG_FIRCDIV[FIRCDIV3]. */
999#define FSL_FEATURE_SCG_HAS_FIRCDIV3 (1)
1000/* @brief Has SCG_FIRCCSR[FIRCLPEN]. */
1001#define FSL_FEATURE_SCG_HAS_FIRCLPEN (1)
1002/* @brief Has SCG_FIRCCSR[FIRCREGOFF]. */
1003#define FSL_FEATURE_SCG_HAS_FIRCREGOFF (1)
1004/* @brief Has SCG_SPLLDIV[SPLLDIV1]. */
1005#define FSL_FEATURE_SCG_HAS_SPLLDIV1 (0)
1006/* @brief Has SCG_SPLLDIV[SPLLDIV3]. */
1007#define FSL_FEATURE_SCG_HAS_SPLLDIV3 (0)
1008/* @brief Has SCG_SPLLCFG[PLLPOSTDIV1]. */
1009#define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV1 (0)
1010/* @brief Has SCG_SPLLCFG[PLLPOSTDIV2]. */
1011#define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV2 (0)
1012/* @brief Has SCG_SPLLCFG[PLLS]. */
1013#define FSL_FEATURE_SCG_HAS_SPLL_PLLS (0)
1014/* @brief Has SCG_SPLLCFG[BYPASS]. */
1015#define FSL_FEATURE_SCG_HAS_SPLL_BYPASS (0)
1016/* @brief Has SCG_SPLLCFG[PFDSEL]. */
1017#define FSL_FEATURE_SCG_HAS_SPLL_PFDSEL (0)
1018/* @brief Has SCG_SPLLCSR[SPLLCM]. */
1019#define FSL_FEATURE_SCG_HAS_SPLL_MONITOR (0)
1020/* @brief Has SCG_LPFLLDIV[FLLDIV1]. */
1021#define FSL_FEATURE_SCG_HAS_FLLDIV1 (1)
1022/* @brief Has SCG_LPFLLDIV[FLLDIV3]. */
1023#define FSL_FEATURE_SCG_HAS_FLLDIV3 (1)
1024/* @brief Has low power FLL, SCG_LPFLLCSR. */
1025#define FSL_FEATURE_SCG_HAS_LPFLL (1)
1026/* @brief Has system PLL, SCG_SPLLCSR. */
1027#define FSL_FEATURE_SCG_HAS_SPLL (0)
1028/* @brief Has system PLL PFD, SCG_SPLLPFD. */
1029#define FSL_FEATURE_SCG_HAS_SPLLPFD (0)
1030/* @brief Has auxiliary PLL, SCG_APLLCSR. */
1031#define FSL_FEATURE_SCG_HAS_APLL (0)
1032/* @brief Has RTC OSC control, SCG_ROSCCSR. */
1033#define FSL_FEATURE_SCG_HAS_ROSC (1)
1034/* @brief Has RTC OSC clock source. */
1035#define FSL_FEATURE_SCG_HAS_ROSC_SYS_CLK_SRC (1)
1036/* @brief Has RTC OSC clock out select. */
1037#define FSL_FEATURE_SCG_HAS_ROSC_CLKOUT (1)
1038/* @brief Has EXTERNAL clock out select. */
1039#define FSL_FEATURE_SCG_HAS_EXT_CLKOUT (1)
1040/* @brief Has no System OSC configuration register, SCG_SOSCCFG. */
1041#define FSL_FEATURE_SCG_HAS_NO_SOSCCFG (1)
1042/* @brief Has no SCG_SOSCCSR[SOSCEN]. */
1043#define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCEN (1)
1044/* @brief Has no SCG_SOSCCSR[SOSCSTEN]. */
1045#define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCSTEN (1)
1046/* @brief Has no SCG_SOSCCSR[SOSCLPEN]. */
1047#define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCLPEN (1)
1048/* @brief Has no FIRC trim configuration register, SCG_FIRCTCFG. */
1049#define FSL_FEATURE_SCG_HAS_NO_FIRCTCFG (0)
1050/* @brief Has FIRC trim source USB0 Start of Frame. */
1051#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB0 (0)
1052/* @brief Has FIRC trim source USB1 Start of Frame. */
1053#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB1 (0)
1054/* @brief Has FIRC trim source system OSC. */
1055#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_SOSC (0)
1056/* @brief Has FIRC trim source RTC OSC. */
1057#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_RTCOSC (1)
1058
1059/* SEMA42 module features */
1060
1061/* @brief Gate counts */
1062#define FSL_FEATURE_SEMA42_GATE_COUNT (16)
1063
1064/* SIM module features */
1065
1066/* @brief Has USB FS divider. */
1067#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
1068/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
1069#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
1070/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
1071#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
1072/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
1073#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
1074/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
1075#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (0)
1076/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
1077#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (0)
1078/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
1079#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
1080/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
1081#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
1082/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
1083#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
1084/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
1085#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
1086/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
1087#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
1088/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
1089#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
1090/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
1091#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
1092/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
1093#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
1094/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
1095#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
1096/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
1097#define FSL_FEATURE_SIM_OPT_UART_COUNT (0)
1098/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
1099#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
1100/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
1101#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
1102/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
1103#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
1104/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
1105#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
1106/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
1107#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
1108/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
1109#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
1110/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
1111#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
1112/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
1113#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
1114/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
1115#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
1116/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
1117#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
1118/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
1119#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
1120/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
1121#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
1122/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
1123#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
1124/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
1125#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
1126/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
1127#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
1128/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
1129#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
1130/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
1131#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
1132/* @brief Has FTM module(s) configuration. */
1133#define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
1134/* @brief Number of FTM modules. */
1135#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
1136/* @brief Number of FTM triggers with selectable source. */
1137#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
1138/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
1139#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
1140/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
1141#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
1142/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
1143#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
1144/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
1145#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
1146/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
1147#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
1148/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
1149#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
1150/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
1151#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
1152/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
1153#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
1154/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
1155#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
1156/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
1157#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
1158/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
1159#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
1160/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
1161#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
1162/* @brief Has TPM module(s) configuration. */
1163#define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
1164/* @brief The highest TPM module index. */
1165#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
1166/* @brief Has TPM module with index 0. */
1167#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
1168/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
1169#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
1170/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
1171#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
1172/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1173#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
1174/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
1175#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
1176/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1177#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
1178/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
1179#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
1180/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
1181#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
1182/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
1183#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
1184/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
1185#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
1186/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
1187#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
1188/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
1189#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
1190/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
1191#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
1192/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
1193#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
1194/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
1195#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
1196/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
1197#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
1198/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
1199#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
1200/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
1201#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
1202/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
1203#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
1204/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
1205#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
1206/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
1207#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
1208/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
1209#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
1210/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
1211#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
1212/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
1213#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
1214/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
1215#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
1216/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
1217#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
1218/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
1219#define FSL_FEATURE_SIM_OPT_ADC_COUNT (0)
1220/* @brief ADC module has alternate trigger (register bit SOPT7[ADC0ALTTRGEN]). */
1221#define FSL_FEATURE_SIM_OPT_ADC_HAS_ALTERNATE_TRIGGER (0)
1222/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
1223#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (0)
1224/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
1225#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0)
1226/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
1227#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
1228/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
1229#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
1230/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
1231#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
1232/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
1233#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
1234/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
1235#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
1236/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
1237#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
1238/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
1239#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
1240/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
1241#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
1242/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
1243#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
1244/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
1245#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
1246/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
1247#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (0)
1248/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
1249#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (0)
1250/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
1251#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
1252/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
1253#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
1254/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
1255#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
1256/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
1257#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
1258/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
1259#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
1260/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
1261#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
1262/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
1263#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
1264/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
1265#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
1266/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
1267#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
1268/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
1269#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
1270/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
1271#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
1272/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
1273#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
1274/* @brief Has device die ID (register bit field SDID[DIEID]). */
1275#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
1276/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
1277#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
1278/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
1279#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
1280/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
1281#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
1282/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
1283#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
1284/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
1285#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
1286/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
1287#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
1288/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
1289#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
1290/* @brief Has flash for core0(CM4) (register bit field FCFG1[CORE0_PFSIZE]). */
1291#define FSL_FEATURE_SIM_FCFG_HAS_CORE0_PFSIZE (1)
1292/* @brief Has flash for core1(CM0) (register bit field FCFG1[CORE1_PFSIZE]). */
1293#define FSL_FEATURE_SIM_FCFG_HAS_CORE1_PFSIZE (1)
1294/* @brief Has sram for core0(CM4) (register bit field FCFG1[CORE0_SRAMSIZE]). */
1295#define FSL_FEATURE_SIM_FCFG_HAS_CORE0_SRAMSIZE (1)
1296/* @brief Has sram for core1(CM0) (register bit field FCFG1[CORE1_SRAMSIZE]). */
1297#define FSL_FEATURE_SIM_FCFG_HAS_CORE1_SRAMSIZE (1)
1298/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
1299#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (0)
1300/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
1301#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
1302/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
1303#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (1)
1304/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
1305#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
1306/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
1307#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
1308/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
1309#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
1310/* @brief Has miscellanious control register (register MCR). */
1311#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
1312/* @brief Has COP watchdog (registers COPC and SRVCOP). */
1313#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
1314/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
1315#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
1316/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
1317#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
1318/* @brief Has MISCCTRL reg. */
1319#define FSL_FEATURE_SIM_HAS_MISCCTRL (0)
1320/* @brief Has LTCEN bit (e.g SIM_MISCCTRL). */
1321#define FSL_FEATURE_SIM_HAS_MISCCTRL_LTCEN (0)
1322/* @brief Has DMAINTSEL0 bit (e.g SIM_MISCCTRL). */
1323#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL0 (0)
1324/* @brief Has DMAINTSEL1 bit (e.g SIM_MISCCTRL). */
1325#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL1 (0)
1326/* @brief Has DMAINTSEL2 bit (e.g SIM_MISCCTRL). */
1327#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL2 (0)
1328/* @brief Has DMAINTSEL3 bit (e.g SIM_MISCCTRL). */
1329#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL3 (0)
1330/* @brief Has SECKEY0 reg. */
1331#define FSL_FEATURE_SIM_HAS_SECKEY0 (0)
1332/* @brief Has SECKEY bit (e.g SIM_SECKEY0). */
1333#define FSL_FEATURE_SIM_HAS_SECKEY0_SECKEY (0)
1334/* @brief Has SECKEY1 reg. */
1335#define FSL_FEATURE_SIM_HAS_SECKEY1 (0)
1336/* @brief Has SECKEY bit (e.g SIM_SECKEY1). */
1337#define FSL_FEATURE_SIM_HAS_SECKEY1_SECKEY (0)
1338/* @brief Has SECKEY2 reg. */
1339#define FSL_FEATURE_SIM_HAS_SECKEY2 (0)
1340/* @brief Has SECKEY bit (e.g SIM_SECKEY2). */
1341#define FSL_FEATURE_SIM_HAS_SECKEY2_SECKEY (0)
1342/* @brief Has SECKEY3 reg. */
1343#define FSL_FEATURE_SIM_HAS_SECKEY3 (0)
1344/* @brief Has SECKEY bit (e.g SIM_SECKEY3). */
1345#define FSL_FEATURE_SIM_HAS_SECKEY3_SECKEY (0)
1346/* @brief Has no SDID reg. */
1347#define FSL_FEATURE_SIM_HAS_NO_SDID (0)
1348/* @brief Has no UID reg. */
1349#define FSL_FEATURE_SIM_HAS_NO_UID (0)
1350/* @brief Has RFADDRL and RFADDRH registers. */
1351#define FSL_FEATURE_SIM_HAS_RF_MAC_ADDR (0)
1352/* @brief Has SYSTICK_CLK_EN bit in SIM_MISC2 register. */
1353#define FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN (1)
1354/* @brief Has UIDM registers. */
1355#define FSL_FEATURE_SIM_HAS_UIDM (1)
1356
1357/* SMC module features */
1358
1359/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
1360#define FSL_FEATURE_SMC_HAS_PSTOPO (0)
1361/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
1362#define FSL_FEATURE_SMC_HAS_LPOPO (0)
1363/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
1364#define FSL_FEATURE_SMC_HAS_PORPO (0)
1365/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
1366#define FSL_FEATURE_SMC_HAS_LPWUI (0)
1367/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
1368#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
1369/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
1370#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
1371/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
1372#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
1373/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
1374#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
1375/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
1376#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
1377/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
1378#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
1379/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
1380#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
1381/* @brief Has stop submode. */
1382#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
1383/* @brief Has stop submode 0(VLLS0). */
1384#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
1385/* @brief Has stop submode 2(VLLS2). */
1386#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
1387/* @brief Has SMC_PARAM. */
1388#define FSL_FEATURE_SMC_HAS_PARAM (1)
1389/* @brief Has SMC_VERID. */
1390#define FSL_FEATURE_SMC_HAS_VERID (1)
1391/* @brief Has SMC_CSRE. */
1392#define FSL_FEATURE_SMC_HAS_CSRE (0)
1393/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
1394#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (0)
1395/* @brief Has tamper reset (register bit SRS[TAMPER]). */
1396#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
1397/* @brief Has security violation reset (register bit SRS[SECVIO]). */
1398#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
1399/* @brief Has security violation reset (register bit SRS[VBAT]). */
1400#define FSL_FEATURE_SMC_HAS_SRS_VBAT (0)
1401/* @brief Has security violation reset (register bit SRS[CORE0]). */
1402#define FSL_FEATURE_SMC_HAS_SRS_CORE0 (1)
1403/* @brief Has security violation reset (register bit SRS[CORE1]). */
1404#define FSL_FEATURE_SMC_HAS_SRS_CORE1 (1)
1405/* @brief Has security violation reset (register bit SRIE[VBAT]). */
1406#define FSL_FEATURE_SMC_HAS_SRIE_VBAT (0)
1407/* @brief Has security violation reset (register bit SRIE[CORE0]). */
1408#define FSL_FEATURE_SMC_HAS_SRIE_CORE0 (1)
1409/* @brief Has security violation reset (register bit SRIE[CORE1]). */
1410#define FSL_FEATURE_SMC_HAS_SRIE_CORE1 (1)
1411/* @brief Width of SMC registers. */
1412#define FSL_FEATURE_SMC_REG_WIDTH (32)
1413
1414/* SysTick module features */
1415
1416/* @brief Systick has external reference clock. */
1417#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1)
1418/* @brief Systick external reference clock is core clock divided by this value. */
1419#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16)
1420
1421/* TPM module features */
1422
1423/* @brief Number of channels. */
1424#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
1425 (((x) == TPM0) ? (6) : \
1426 (((x) == TPM1) ? (2) : \
1427 (((x) == TPM2) ? (6) : \
1428 (((x) == TPM3) ? (2) : (-1)))))
1429/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
1430#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
1431/* @brief Has TPM_PARAM. */
1432#define FSL_FEATURE_TPM_HAS_PARAM (1)
1433/* @brief Has TPM_VERID. */
1434#define FSL_FEATURE_TPM_HAS_VERID (1)
1435/* @brief Has TPM_GLOBAL. */
1436#define FSL_FEATURE_TPM_HAS_GLOBAL (1)
1437/* @brief Has TPM_TRIG. */
1438#define FSL_FEATURE_TPM_HAS_TRIG (1)
1439/* @brief Has counter pause on trigger. */
1440#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
1441/* @brief Has external trigger selection. */
1442#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
1443/* @brief Has TPM_COMBINE register. */
1444#define FSL_FEATURE_TPM_HAS_COMBINE (1)
1445/* @brief Whether COMBINE register has effect. */
1446#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1)
1447/* @brief Has TPM_POL. */
1448#define FSL_FEATURE_TPM_HAS_POL (1)
1449/* @brief Has TPM_FILTER register. */
1450#define FSL_FEATURE_TPM_HAS_FILTER (1)
1451/* @brief Whether FILTER register has effect. */
1452#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1)
1453/* @brief Has TPM_QDCTRL register. */
1454#define FSL_FEATURE_TPM_HAS_QDCTRL (1)
1455/* @brief Whether QDCTRL register has effect. */
1456#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1)
1457
1458/* TRGMUX module features */
1459
1460/* No feature definitions */
1461
1462/* TRNG module features */
1463
1464/* No feature definitions */
1465
1466/* TSTMR module features */
1467
1468/* @brief TSTMR clock frequency is 1MHZ. */
1469#define FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ (1)
1470
1471/* USB module features */
1472
1473/* @brief KHCI module instance count */
1474#define FSL_FEATURE_USB_KHCI_COUNT (1)
1475/* @brief HOST mode enabled */
1476#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (0)
1477/* @brief OTG mode enabled */
1478#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (0)
1479/* @brief Size of the USB dedicated RAM */
1480#define FSL_FEATURE_USB_KHCI_USB_RAM (2048)
1481/* @brief Base address of the USB dedicated RAM */
1482#define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1208025088)
1483/* @brief Has KEEP_ALIVE_CTRL register */
1484#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (1)
1485/* @brief Mode control of the USB Keep Alive */
1486#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_MODE_CONTROL (USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK)
1487/* @brief Has the Dynamic SOF threshold compare support */
1488#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1)
1489/* @brief Has the VBUS detect support */
1490#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1)
1491/* @brief Has the IRC48M module clock support */
1492#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
1493/* @brief Number of endpoints supported */
1494#define FSL_FEATURE_USB_ENDPT_COUNT (16)
1495/* @brief Has STALL_IL/OL_DIS registers */
1496#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1)
1497/* @brief Has STALL_IH/OH_DIS registers */
1498#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1)
1499
1500/* USDHC module features */
1501
1502/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
1503#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0)
1504/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */
1505#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0)
1506/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */
1507#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (0)
1508/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
1509#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (0)
1510/* @brief USDHC has reset control */
1511#define FSL_FEATURE_USDHC_HAS_RESET (0)
1512/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */
1513#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0)
1514/* @brief If USDHC instance support 8 bit width */
1515#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1)
1516/* @brief If USDHC instance support HS400 mode */
1517#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0)
1518/* @brief If USDHC instance support 1v8 signal */
1519#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1)
1520
1521/* VREF module features */
1522
1523/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
1524#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
1525/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
1526#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
1527/* @brief If high/low buffer mode supported */
1528#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
1529/* @brief Module has also low reference (registers VREFL/VREFH) */
1530#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
1531/* @brief Has VREF_TRM4. */
1532#define FSL_FEATURE_VREF_HAS_TRM4 (1)
1533
1534/* WDOG module features */
1535
1536/* @brief Watchdog is available. */
1537#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
1538/* @brief WDOG_CNT can be 32-bit written. */
1539#define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1)
1540
1541/* XRDC module features */
1542
1543/* @brief Does not have global valid (register bit CR[GVLD]). */
1544#define FSL_FEATURE_XRDC_HAS_NO_CR_GVLD (1)
1545/* @brief Has domain ID of faulted access (register bit FDID[FDID]). */
1546#define FSL_FEATURE_XRDC_HAS_FDID (1)
1547/* @brief Has special 4-state model option (register bit PID[SP4SM]). */
1548#define FSL_FEATURE_XRDC_PID_SP4SM (1)
1549/* @brief Does not have logical partition identifier (register bit MDA_W[LPID]). */
1550#define FSL_FEATURE_XRDC_NO_MDA_LPID (1)
1551/* @brief Does not have logical partition enable option (register bit MDA_W[LPE]). */
1552#define FSL_FEATURE_XRDC_NO_MDA_LPE (1)
1553/* @brief Does not have peripheral semaphore enable option (register bit PDAC_W0[SE]). */
1554#define FSL_FEATURE_XRDC_NO_PDAC_SE (1)
1555/* @brief Does not have peripheral semaphore number (register bit PDAC_W0[SNUM]). */
1556#define FSL_FEATURE_XRDC_NO_PDAC_SNUM (1)
1557/* @brief Has peripheral excessive access lock owner (register bit PDAC_W0[EALO]). */
1558#define FSL_FEATURE_XRDC_HAS_PDAC_EALO (1)
1559/* @brief Has peripheral excessive access lock option (register bit PDAC_W1[EAL]). */
1560#define FSL_FEATURE_XRDC_HAS_PDAC_EAL (1)
1561/* @brief Has memory region end address (register bit MRGD_W1[ENDADDR]). */
1562#define FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR (1)
1563/* @brief Does not have memory region semaphore enable option (register bit MRGD_W2[SE]). */
1564#define FSL_FEATURE_XRDC_NO_MRGD_SE (1)
1565/* @brief Does not have memory region semaphore number (register bit MRGD_W2[SNUM]). */
1566#define FSL_FEATURE_XRDC_NO_MRGD_SNUM (1)
1567/* @brief Does not domain x access control policy option (register bit MRGD_W2[DxACP]). */
1568#define FSL_FEATURE_XRDC_NO_MRGD_DXACP (1)
1569/* @brief Does not have region size configuration (register bit MRGD_W2[SZ]). */
1570#define FSL_FEATURE_XRDC_NO_MRGD_SZ (1)
1571/* @brief Does not have subregion disable option (register bit MRGD_W2[SRD]). */
1572#define FSL_FEATURE_XRDC_NO_MRGD_SRD (1)
1573/* @brief Has memory region excessive access lock owner (register bit MRGD_W2[EALO]). */
1574#define FSL_FEATURE_XRDC_HAS_MRGD_EALO (1)
1575/* @brief Has domain x access policy select option (register bit MRGD_W2[DxSEL]). */
1576#define FSL_FEATURE_XRDC_HAS_MRGD_DXSEL (1)
1577/* @brief Has memory region excessive access lock option (register bit MRGD_W3[EAL]). */
1578#define FSL_FEATURE_XRDC_HAS_MRGD_EAL (1)
1579/* @brief Does not have lock option in MRGD_W3 register (register bit MRGD_W3[LK2]). */
1580#define FSL_FEATURE_XRDC_NO_MRGD_W3_LK2 (1)
1581/* @brief Does not have valid option in MRGD_W3 register (register bit MRGD_W3[VLD]). */
1582#define FSL_FEATURE_XRDC_NO_MRGD_W3_VLD (1)
1583/* @brief Has code region indicator select option (register bit MRGD_W3[CR]). */
1584#define FSL_FEATURE_XRDC_HAS_MRGD_CR (1)
1585/* @brief Has ASSSET lock option (register bit MRGD_W4[LKAS1]/[LKAS2]). */
1586#define FSL_FEATURE_XRDC_HAS_MRGD_LKAS (1)
1587/* @brief Has programmable access flags (register bit MRGD_W4[ACCSET1]/[ACCSET2]). */
1588#define FSL_FEATURE_XRDC_HAS_MRGD_ACCSET (1)
1589/* @brief Has lock option in MRGD_W4 register (register bit MRGD_W4[LK2]). */
1590#define FSL_FEATURE_XRDC_HAS_MRGD_W4_LK2 (1)
1591/* @brief Has valid option in MRGD_W4 register (register bit MRGD_W4[VLD]). */
1592#define FSL_FEATURE_XRDC_HAS_MRGD_W4_VLD (1)
1593/* @brief XRDC domain number (reset value of HWCFG0[NDID] plus 1). */
1594#define FSL_FEATURE_XRDC_DOMAIN_COUNT (3)
1595
1596#endif /* _K32L3A60_cm4_FEATURES_H_ */
1597
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