1 files changed, 182 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/K32L3A60/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L3A60/project_template/clock_config.c
new file mode 100644
index 000000000..04e9093f2
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L3A60/project_template/clock_config.c
@@ -0,0 +1,182 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
+ *    Note: The clock could not be set when it is being used as system clock.
+ *    In default out of reset, the CPU is clocked from FIRC(IRC48M),
+ *    so before setting FIRC, change to use another avaliable clock source.
+ *
+ * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
+ *
+ * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
+ *    Wait until the system clock source is changed to target source.
+ *
+ * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
+ *    corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
+ *    Supported run mode and clock restrictions could be found in Reference Manual.
+ */
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v5.0
+processor: K32L3A60xxx
+mcu_data: ksdk2_0
+processor_version: 0.0.1
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+#include "clock_config.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define SCG_LPFLL_DISABLE                                 0U  /*!< LPFLL clock disabled */
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#ifndef SDK_SECONDARY_CORE
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_FircSafeConfig
+ * Description   : This function is used to safely configure FIRC clock.
+ *                 In default out of reset, the CPU is clocked from FIRC(IRC48M).
+ *                 Before setting FIRC, change to use SIRC as system clock,
+ *                 then configure FIRC. 
+ * Param fircConfig  : FIRC configuration.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
+{
+    scg_sys_clk_config_t curConfig;
+    const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
+                                             .div1 = kSCG_AsyncClkDisable,
+                                             .div2 = kSCG_AsyncClkDivBy2,
+                                             .range = kSCG_SircRangeHigh};
+    scg_sys_clk_config_t sysClkSafeConfigSource = {
+         .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider. */
+         .divCore = kSCG_SysClkDivBy1, /* Core clock divider. */
+         .src = kSCG_SysClkSrcSirc     /* System clock source. */
+    };
+    /* Init Sirc */
+    CLOCK_InitSirc(&scgSircConfig);
+    /* Change to use SIRC as system clock source to prepare to change FIRCCFG register */
+    CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
+    /* Wait for clock source switch finished */
+    do
+    {
+        CLOCK_GetCurSysClkConfig(&curConfig);
+    } while (curConfig.src != sysClkSafeConfigSource.src);
+    /* Init Firc */
+    CLOCK_InitFirc(fircConfig);
+}
+#endif
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: Bus_clock.outFreq, value: 48 MHz}
+- {id: Core_clock.outFreq, value: 48 MHz}
+- {id: LPO_CLK.outFreq, value: 1 kHz}
+- {id: Platform_clock.outFreq, value: 48 MHz}
+- {id: Slow_clock.outFreq, value: 24 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
+    {
+        .divSlow = kSCG_SysClkDivBy2,             /* Slow Clock Divider: divided by 2 */
+        .divBus = kSCG_SysClkDivBy1,              /* Bus Clock Divider: divided by 1 */
+        .divExt = kSCG_SysClkDivBy1,              /* External Clock Divider: divided by 1 */
+        .divCore = kSCG_SysClkDivBy1,             /* Core Clock Divider: divided by 1 */
+        .src = kSCG_SysClkSrcFirc,                /* Fast IRC is selected as System Clock Source */
+    };
+const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
+    {
+        .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
+        .div1 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 1: Clock output is disabled */
+        .div2 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 3: Clock output is disabled */
+        .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
+    };
+const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
+    {
+        .enableMode = kSCG_FircEnable,            /* Enable FIRC clock */
+        .div1 = kSCG_AsyncClkDisable,             /* Fast IRC Clock Divider 1: Clock output is disabled */
+        .div2 = kSCG_AsyncClkDisable,             /* Fast IRC Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* Fast IRC Clock Divider 3: Clock output is disabled */
+        .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
+        .trimConfig = NULL,
+    };
+const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN =
+    {
+        .enableMode = SCG_LPFLL_DISABLE,          /* LPFLL clock disabled */
+        .div1 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 1: Clock output is disabled */
+        .div2 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 3: Clock output is disabled */
+        .range = kSCG_LpFllRange48M,              /* LPFLL is trimmed to 48MHz */
+        .trimConfig = NULL,
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    scg_sys_clk_config_t curConfig;
+    /* Init FIRC */
+    CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
+    /* Set SCG to FIRC mode. */
+    CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
+    /* Wait for clock source switch finished */
+    do
+    {
+        CLOCK_GetCurSysClkConfig(&curConfig);
+    } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
+    /* Init SIRC */
+    CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
+    /* Init LPFLL */
+    CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+#endif
+}

diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/K32L3A60/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L3A60/project_template/clock_config.c new file mode 100644 index 000000000..04e9093f2 --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L3A60/project_template/clock_config.c
@@ -0,0 +1,182 @@
	1	/*
	2	* Copyright 2019 NXP
	3	* All rights reserved.
	4	*
	5	* SPDX-License-Identifier: BSD-3-Clause
	6	*/
	7
	8	/***********************************************************************************************************************
	9	* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
	10	* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
	11	**********************************************************************************************************************/
	12	/*
	13	* How to setup clock using clock driver functions:
	14	*
	15	* 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
	16	* Note: The clock could not be set when it is being used as system clock.
	17	* In default out of reset, the CPU is clocked from FIRC(IRC48M),
	18	* so before setting FIRC, change to use another avaliable clock source.
	19	*
	20	* 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
	21	*
	22	* 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
	23	* Wait until the system clock source is changed to target source.
	24	*
	25	* 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
	26	* corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
	27	* Supported run mode and clock restrictions could be found in Reference Manual.
	28	*/
	29
	30	/* clang-format off */
	31	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	32	!!GlobalInfo
	33	product: Clocks v5.0
	34	processor: K32L3A60xxx
	35	mcu_data: ksdk2_0
	36	processor_version: 0.0.1
	37	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	38	/* clang-format on */
	39
	40	#include "clock_config.h"
	41
	42	/*******************************************************************************
	43	* Definitions
	44	******************************************************************************/
	45	#define SCG_LPFLL_DISABLE 0U /!< LPFLL clock disabled /
	46
	47	/*******************************************************************************
	48	* Variables
	49	******************************************************************************/
	50	/* System clock frequency. */
	51	extern uint32_t SystemCoreClock;
	52
	53	/*******************************************************************************
	54	* Code
	55	******************************************************************************/
	56	#ifndef SDK_SECONDARY_CORE
	57	/FUNCTION*********************************************************************
	58	*
	59	* Function Name : CLOCK_CONFIG_FircSafeConfig
	60	* Description : This function is used to safely configure FIRC clock.
	61	* In default out of reset, the CPU is clocked from FIRC(IRC48M).
	62	* Before setting FIRC, change to use SIRC as system clock,
	63	* then configure FIRC.
	64	* Param fircConfig : FIRC configuration.
	65	*
	66	END*************************************************************************/
	67	static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
	68	{
	69	scg_sys_clk_config_t curConfig;
	70	const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
	71	.div1 = kSCG_AsyncClkDisable,
	72	.div2 = kSCG_AsyncClkDivBy2,
	73	.range = kSCG_SircRangeHigh};
	74	scg_sys_clk_config_t sysClkSafeConfigSource = {
	75	.divSlow = kSCG_SysClkDivBy4, /* Slow clock divider. */
	76	.divCore = kSCG_SysClkDivBy1, /* Core clock divider. */
	77	.src = kSCG_SysClkSrcSirc /* System clock source. */
	78	};
	79	/* Init Sirc */
	80	CLOCK_InitSirc(&scgSircConfig);
	81	/* Change to use SIRC as system clock source to prepare to change FIRCCFG register */
	82	CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
	83	/* Wait for clock source switch finished */
	84	do
	85	{
	86	CLOCK_GetCurSysClkConfig(&curConfig);
	87	} while (curConfig.src != sysClkSafeConfigSource.src);
	88
	89	/* Init Firc */
	90	CLOCK_InitFirc(fircConfig);
	91	}
	92	#endif
	93
	94	/*******************************************************************************
	95	********************** BOARD_InitBootClocks function **********************
	96	******************************************************************************/
	97	void BOARD_InitBootClocks(void)
	98	{
	99	BOARD_BootClockRUN();
	100	}
	101
	102	/*******************************************************************************
	103	******************** Configuration BOARD_BootClockRUN *********************
	104	******************************************************************************/
	105	/* clang-format off */
	106	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	107	!!Configuration
	108	name: BOARD_BootClockRUN
	109	called_from_default_init: true
	110	outputs:
	111	- {id: Bus_clock.outFreq, value: 48 MHz}
	112	- {id: Core_clock.outFreq, value: 48 MHz}
	113	- {id: LPO_CLK.outFreq, value: 1 kHz}
	114	- {id: Platform_clock.outFreq, value: 48 MHz}
	115	- {id: Slow_clock.outFreq, value: 24 MHz}
	116	- {id: System_clock.outFreq, value: 48 MHz}
	117	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	118	/* clang-format on */
	119
	120	/*******************************************************************************
	121	* Variables for BOARD_BootClockRUN configuration
	122	******************************************************************************/
	123	const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
	124	{
	125	.divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
	126	.divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
	127	.divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
	128	.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
	129	.src = kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */
	130	};
	131	const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
	132	{
	133	.enableMode = kSCG_SircEnable \| kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
	134	.div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
	135	.div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
	136	.div3 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 3: Clock output is disabled */
	137	.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
	138	};
	139	const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
	140	{
	141	.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
	142	.div1 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 1: Clock output is disabled */
	143	.div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
	144	.div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock output is disabled */
	145	.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
	146	.trimConfig = NULL,
	147	};
	148	const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN =
	149	{
	150	.enableMode = SCG_LPFLL_DISABLE, /* LPFLL clock disabled */
	151	.div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabled */
	152	.div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
	153	.div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
	154	.range = kSCG_LpFllRange48M, /* LPFLL is trimmed to 48MHz */
	155	.trimConfig = NULL,
	156	};
	157	/*******************************************************************************
	158	* Code for BOARD_BootClockRUN configuration
	159	******************************************************************************/
	160	void BOARD_BootClockRUN(void)
	161	{
	162	#ifndef SDK_SECONDARY_CORE
	163	scg_sys_clk_config_t curConfig;
	164
	165	/* Init FIRC */
	166	CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
	167	/* Set SCG to FIRC mode. */
	168	CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
	169	/* Wait for clock source switch finished */
	170	do
	171	{
	172	CLOCK_GetCurSysClkConfig(&curConfig);
	173	} while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
	174	/* Init SIRC */
	175	CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
	176	/* Init LPFLL */
	177	CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockRUN);
	178	/* Set SystemCoreClock variable. */
	179	SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
	180	#endif
	181	}
	182