1 files changed, 143 insertions, 0 deletions

diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/K32L3A60/system_K32L3A60_cm4.c b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L3A60/system_K32L3A60_cm4.c
new file mode 100644
index 000000000..6a7ddb0ad
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L3A60/system_K32L3A60_cm4.c
@@ -0,0 +1,143 @@
+/*
+** ###################################################################
+**     Processor:           K32L3A60VPJ1A_cm4
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    K32L3ARM, Rev. 0 , 05/2019
+**     Version:             rev. 1.0, 2019-04-22
+**     Build:               b201013
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2020 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2019-04-22)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file K32L3A60_cm4
+ * @version 1.0
+ * @date 2019-04-22
+ * @brief Device specific configuration file for K32L3A60_cm4 (implementation
+ *        file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+#if (DISABLE_WDOG)
+  if ((WDOG0->CS & WDOG_CS_CMD32EN_MASK) != 0U)
+  {
+      WDOG0->CNT = 0xD928C520U;
+  }
+  else
+  {
+      WDOG0->CNT = 0xC520U;
+      WDOG0->CNT = 0xD928U;
+  }
+  WDOG0->TOVAL = 0xFFFFU;
+  WDOG0->CS = (uint32_t) ((WDOG0->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
+#endif /* (DISABLE_WDOG) */
+
+/* Boot ROM on K32_L3 does not properly restore the registers (LPTMR0->CSR, LPTMR0->PSR, SCB->AIRCR) upon exiting. This can cause
+ * an unrecoverable hard fault when SVC calls are executed. SVC calls are needed by operating systems when starting tasks.
+ * Add following codes to the end of the SystemInit function which is called before any application is started. This operation
+ * will be done only when current core is boot core. */
+  if (((FTFE->FOPT3 & 0x40U) >> 6U) != 0U)
+  {
+    if (LPTMR0->CSR != 0U)
+    {
+        LPTMR0->CSR = 0;
+    }
+    if (LPTMR0->PSR != 0U)
+    {
+        LPTMR0->PSR = 0;
+    }
+    if ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) != 0x0U)
+    {
+        SCB->AIRCR = 0x05FA0000;
+    }
+  }
+
+  SystemInitHook();
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+
+  uint32_t SCGOUTClock;                                 /* Variable to store output clock frequency of the SCG module */
+  uint16_t Divider;
+  Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U);
+
+  switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
+    case 0x1:
+      /* System OSC */
+      SCGOUTClock = CPU_XTAL_CLK_HZ;
+      break;
+    case 0x2:
+      /* Slow IRC */
+      SCGOUTClock = ((((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) != 0U) ? 8000000U : 2000000U);
+      break;
+    case 0x3:
+      /* Fast IRC */
+      SCGOUTClock = 48000000U + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000U;
+      break;
+    case 0x5:
+      /* Low Power FLL */
+      SCGOUTClock = 48000000U + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000U;
+      break;
+    default:
+      SCGOUTClock = 0U;
+      break;
+  }
+  SystemCoreClock = (SCGOUTClock / Divider);
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInitHook()
+   ---------------------------------------------------------------------------- */
+
+__attribute__ ((weak)) void SystemInitHook (void) {
+  /* Void implementation of the weak function. */
+}