aboutsummaryrefslogtreecommitdiff
path: root/lib/chibios-contrib/ext/mcux-sdk/devices/LPC51U68/drivers/fsl_clock.h
diff options
context:
space:
mode:
Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/LPC51U68/drivers/fsl_clock.h')
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC51U68/drivers/fsl_clock.h835
1 files changed, 835 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC51U68/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC51U68/drivers/fsl_clock.h
new file mode 100644
index 000000000..12c9936c4
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC51U68/drivers/fsl_clock.h
@@ -0,0 +1,835 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2019 , NXP
4 * All rights reserved.
5 *
6 *
7 * SPDX-License-Identifier: BSD-3-Clause
8 */
9
10#ifndef _FSL_CLOCK_H_
11#define _FSL_CLOCK_H_
12
13#include "fsl_common.h"
14
15/*! @addtogroup clock */
16/*! @{ */
17
18/*! @file */
19
20/*******************************************************************************
21 * Definitions
22 *****************************************************************************/
23
24/*! @name Driver version */
25/*@{*/
26/*! @brief CLOCK driver version 2.4.1. */
27#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
28/*@}*/
29
30/* Definition for delay API in clock driver, users can redefine it to the real application. */
31#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
32#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (150000000UL)
33#endif
34
35/*!
36 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
37 *
38 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
39 * would cache the recent calulation and accelerate the execution to get the
40 * right settings.
41 */
42#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
43#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
44#endif
45
46/*! @brief Clock ip name array for FLEXCOMM. */
47#define FLEXCOMM_CLOCKS \
48 { \
49 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
50 kCLOCK_FlexComm6, kCLOCK_FlexComm7 \
51 }
52/*! @brief Clock ip name array for LPUART. */
53#define LPUART_CLOCKS \
54 { \
55 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
56 kCLOCK_MinUart6, kCLOCK_MinUart7 \
57 }
58
59/*! @brief Clock ip name array for BI2C. */
60#define BI2C_CLOCKS \
61 { \
62 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \
63 }
64/*! @brief Clock ip name array for LSPI. */
65#define LPSI_CLOCKS \
66 { \
67 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \
68 }
69/*! @brief Clock ip name array for FLEXI2S. */
70#define FLEXI2S_CLOCKS \
71 { \
72 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
73 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \
74 }
75/*! @brief Clock ip name array for UTICK. */
76#define UTICK_CLOCKS \
77 { \
78 kCLOCK_Utick \
79 }
80/*! @brief Clock ip name array for DMA. */
81#define DMA_CLOCKS \
82 { \
83 kCLOCK_Dma \
84 }
85/*! @brief Clock ip name array for CT32B. */
86#define CTIMER_CLOCKS \
87 { \
88 kCLOCK_Ctimer0, kCLOCK_Ctimer1, kCLOCK_Ctimer3 \
89 }
90
91/*! @brief Clock ip name array for GPIO. */
92#define GPIO_CLOCKS \
93 { \
94 kCLOCK_Gpio0, kCLOCK_Gpio1 \
95 }
96/*! @brief Clock ip name array for ADC. */
97#define ADC_CLOCKS \
98 { \
99 kCLOCK_Adc0 \
100 }
101/*! @brief Clock ip name array for MRT. */
102#define MRT_CLOCKS \
103 { \
104 kCLOCK_Mrt \
105 }
106/*! @brief Clock ip name array for MRT. */
107#define SCT_CLOCKS \
108 { \
109 kCLOCK_Sct0 \
110 }
111/*! @brief Clock ip name array for RTC. */
112#define RTC_CLOCKS \
113 { \
114 kCLOCK_Rtc \
115 }
116/*! @brief Clock ip name array for WWDT. */
117#define WWDT_CLOCKS \
118 { \
119 kCLOCK_Wwdt \
120 }
121/*! @brief Clock ip name array for CRC. */
122#define CRC_CLOCKS \
123 { \
124 kCLOCK_Crc \
125 }
126/*! @brief Clock ip name array for USBD. */
127#define USBD_CLOCKS \
128 { \
129 kCLOCK_Usbd0 \
130 }
131
132/*! @brief Clock ip name array for GINT. GINT0 & GINT1 share same slot */
133#define GINT_CLOCKS \
134 { \
135 kCLOCK_Gint, kCLOCK_Gint \
136 }
137
138/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
139/*------------------------------------------------------------------------------
140 clock_ip_name_t definition:
141------------------------------------------------------------------------------*/
142
143#define CLK_GATE_REG_OFFSET_SHIFT 8U
144#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
145#define CLK_GATE_BIT_SHIFT_SHIFT 0U
146#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
147
148#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
149 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
150 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
151
152#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
153#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
154
155#define AHB_CLK_CTRL0 0
156#define AHB_CLK_CTRL1 1
157#define ASYNC_CLK_CTRL0 2
158
159/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
160typedef enum _clock_ip_name
161{
162 kCLOCK_IpInvalid = 0U,
163 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
164 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),
165 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),
166 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
167 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
168 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
169 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
170 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
171 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /* GPIO_GLOBALINT0 and GPIO_GLOBALINT1 share the same slot */
172 kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
173 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
174 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
175 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
176 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
177 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
178 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
179 kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
180 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
181 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
182 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
183 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
184 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
185 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
186 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
187 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
188 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
189 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
190 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
191 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
192 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
193 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
194 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
195 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
196 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
197 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
198 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
199 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
200 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
201 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
202 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
203 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
204 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
205 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
206 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
207 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
208 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
209 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
210 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
211 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
212 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
213 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
214 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
215 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
216 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
217 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
218 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
219 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
220 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
221 kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
222 kCLOCK_Ctimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
223 kCLOCK_Ctimer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
224
225 kCLOCK_Ctimer3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13),
226} clock_ip_name_t;
227
228/*! @brief Clock name used to get clock frequency. */
229typedef enum _clock_name
230{
231 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
232 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
233 kCLOCK_ClockOut, /*!< CLOCKOUT */
234 kCLOCK_FroHf, /*!< FRO48/96 */
235 kCLOCK_Fro12M, /*!< FRO12M */
236 kCLOCK_ExtClk, /*!< External Clock */
237 kCLOCK_PllOut, /*!< PLL Output */
238 kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
239 kCLOCK_Frg, /*!< Frg Clock */
240 kCLOCK_AsyncApbClk, /*!< Async APB clock */
241 kCLOCK_FlexI2S, /*!< FlexI2S clock */
242} clock_name_t;
243
244/**
245 * Clock source selections for the asynchronous APB clock
246 */
247typedef enum _async_clock_src
248{
249 kCLOCK_AsyncMainClk = 0, /*!< Main System clock */
250 kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */
251} async_clock_src_t;
252
253/*! @brief Clock Mux Switches
254 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
255 * starting from LSB upwards
256 *
257 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
258 *
259 */
260
261#define CLK_ATTACH_ID(mux, sel, pos) ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((pos)*12U))
262#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
263#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
264
265#define GET_ID_ITEM(connection) ((connection)&0xFFFU)
266#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
267#define GET_ID_ITEM_MUX(connection) ((uint8_t)((connection)&0xFFU))
268#define GET_ID_ITEM_SEL(connection) ((uint8_t)(((connection)&0xF00U) >> 8U) - 1U)
269#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
270
271#define CM_MAINCLKSELA 0
272#define CM_MAINCLKSELB 1
273#define CM_CLKOUTCLKSELA 2
274#define CM_CLKOUTCLKSELB 3
275#define CM_SYSPLLCLKSEL 4
276#define CM_USBPLLCLKSEL 5
277#define CM_AUDPLLCLKSEL 6
278#define CM_SCTPLLCLKSEL 7
279#define CM_ADCASYNCCLKSEL 9
280#define CM_USBCLKSEL 10
281#define CM_USB1CLKSEL 11
282#define CM_FXCOMCLKSEL0 12
283#define CM_FXCOMCLKSEL1 13
284#define CM_FXCOMCLKSEL2 14
285#define CM_FXCOMCLKSEL3 15
286#define CM_FXCOMCLKSEL4 16
287#define CM_FXCOMCLKSEL5 17
288#define CM_FXCOMCLKSEL6 18
289#define CM_FXCOMCLKSEL7 19
290#define CM_FXCOMCLKSEL8 20
291#define CM_FXCOMCLKSEL9 21
292#define CM_FXCOMCLKSEL10 22
293#define CM_FXCOMCLKSEL11 23
294#define CM_FXI2S0MCLKCLKSEL 24
295#define CM_FXI2S1MCLKCLKSEL 25
296#define CM_FRGCLKSEL 26
297
298#define CM_ASYNCAPB 28U
299
300typedef enum _clock_attach_id
301{
302
303 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),
304 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),
305 kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),
306 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),
307 kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),
308 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),
309
310 kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0),
311 kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),
312 kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2),
313 kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3),
314 kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7),
315
316 kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0),
317 kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1),
318
319 kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
320 kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
321 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
322 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
323
324 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
325 kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
326 kSYS_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
327 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
328 kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
329 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
330
331 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
332 kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
333 kSYS_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
334 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
335 kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
336 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
337
338 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
339 kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
340 kSYS_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
341 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
342 kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
343 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
344
345 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
346 kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
347 kSYS_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
348 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
349 kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
350 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
351
352 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
353 kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
354 kSYS_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
355 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
356 kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
357 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
358
359 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
360 kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
361 kSYS_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
362 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
363 kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
364 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
365
366 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
367 kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
368 kSYS_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
369 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
370 kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
371 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
372
373 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
374 kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
375 kSYS_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
376 kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
377 kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
378 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
379
380 kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0),
381 kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1),
382 kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2),
383 kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3),
384 kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7),
385
386 kFRO_HF_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 0),
387 kSYS_PLL_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 1),
388 kMAIN_CLK_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 2),
389 kNONE_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 7),
390
391 kFRO_HF_to_USB_CLK = MUX_A(CM_USBCLKSEL, 0),
392 kSYS_PLL_to_USB_CLK = MUX_A(CM_USBCLKSEL, 1),
393 kMAIN_CLK_to_USB_CLK = MUX_A(CM_USBCLKSEL, 2),
394 kNONE_to_USB_CLK = MUX_A(CM_USBCLKSEL, 7),
395
396 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0),
397 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1),
398 kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2),
399 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3),
400 kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4),
401 kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5),
402 kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6),
403 kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7),
404 kNONE_to_NONE = (int)0x80000000U,
405} clock_attach_id_t;
406
407/* Clock dividers */
408typedef enum _clock_div_name
409{
410 kCLOCK_DivSystickClk = 0,
411 kCLOCK_DivTraceClk = 1,
412 kCLOCK_DivAhbClk = 32,
413 kCLOCK_DivClkOut = 33,
414 kCLOCK_DivAdcAsyncClk = 37,
415 kCLOCK_DivUsbClk = 38,
416 kCLOCK_DivFrg = 40,
417 kCLOCK_DivFxI2s0MClk = 43
418} clock_div_name_t;
419
420/*******************************************************************************
421 * API
422 ******************************************************************************/
423
424#if defined(__cplusplus)
425extern "C" {
426#endif /* __cplusplus */
427
428static inline void CLOCK_EnableClock(clock_ip_name_t clk)
429{
430 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
431 if (index < 2UL)
432 {
433 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
434 }
435 else
436 {
437 ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
438 }
439}
440
441static inline void CLOCK_DisableClock(clock_ip_name_t clk)
442{
443 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
444 if (index < 2UL)
445 {
446 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
447 }
448 else
449 {
450 ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
451 }
452}
453/**
454 * @brief FLASH Access time definitions
455 */
456typedef enum _clock_flashtim
457{
458 kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clock */
459 kCLOCK_Flash2Cycle, /*!< Flash accesses use 2 CPU clocks */
460 kCLOCK_Flash3Cycle, /*!< Flash accesses use 3 CPU clocks */
461 kCLOCK_Flash4Cycle, /*!< Flash accesses use 4 CPU clocks */
462 kCLOCK_Flash5Cycle, /*!< Flash accesses use 5 CPU clocks */
463 kCLOCK_Flash6Cycle, /*!< Flash accesses use 6 CPU clocks */
464 kCLOCK_Flash7Cycle, /*!< Flash accesses use 7 CPU clocks */
465} clock_flashtim_t;
466
467/**
468 * @brief Set FLASH memory access time in clocks
469 * @param clks : Clock cycles for FLASH access
470 * @return Nothing
471 */
472static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks)
473{
474 uint32_t tmp;
475
476 tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK);
477
478 /* Don't alter lower bits */
479 SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT);
480}
481
482/**
483 * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
484 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
485 * enabled.
486 * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)
487 * @return returns success or fail status.
488 */
489status_t CLOCK_SetupFROClocking(uint32_t iFreq);
490/**
491 * @brief Configure the clock selection muxes.
492 * @param connection : Clock to be configured.
493 * @return Nothing
494 */
495void CLOCK_AttachClk(clock_attach_id_t connection);
496/**
497 * @brief Get the actual clock attach id.
498 * This fuction uses the offset in input attach id, then it reads the actual source value in
499 * the register and combine the offset to obtain an actual attach id.
500 * @param attachId : Clock attach id to get.
501 * @return Clock source value.
502 */
503clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
504/**
505 * @brief Setup peripheral clock dividers.
506 * @param div_name : Clock divider name
507 * @param divided_by_value: Value to be divided
508 * @param reset : Whether to reset the divider counter.
509 * @return Nothing
510 */
511void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
512/**
513 * @brief Set the flash wait states for the input freuqency.
514 * @param iFreq : Input frequency
515 * @return Nothing
516 */
517void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);
518/*! @brief Return Frequency of selected clock
519 * @return Frequency of selected clock
520 */
521uint32_t CLOCK_GetFreq(clock_name_t clockName);
522
523/*! @brief Return Input frequency for the Fractional baud rate generator
524 * @return Input Frequency for FRG
525 */
526uint32_t CLOCK_GetFRGInputClock(void);
527
528/*! @brief Set output of the Fractional baud rate generator
529 * @param freq : Desired output frequency
530 * @return Error Code 0 - fail 1 - success
531 */
532uint32_t CLOCK_SetFRGClock(uint32_t freq);
533
534/*! @brief Return Frequency of FRO 12MHz
535 * @return Frequency of FRO 12MHz
536 */
537uint32_t CLOCK_GetFro12MFreq(void);
538/*! @brief Return Frequency of External Clock
539 * @return Frequency of External Clock. If no external clock is used returns 0.
540 */
541uint32_t CLOCK_GetExtClkFreq(void);
542/*! @brief Return Frequency of Watchdog Oscillator
543 * @return Frequency of Watchdog Oscillator
544 */
545uint32_t CLOCK_GetWdtOscFreq(void);
546/*! @brief Return Frequency of High-Freq output of FRO
547 * @return Frequency of High-Freq output of FRO
548 */
549uint32_t CLOCK_GetFroHfFreq(void);
550/*! @brief Return Frequency of PLL
551 * @return Frequency of PLL
552 */
553uint32_t CLOCK_GetPllOutFreq(void);
554/*! @brief Return Frequency of 32kHz osc
555 * @return Frequency of 32kHz osc
556 */
557uint32_t CLOCK_GetOsc32KFreq(void);
558/*! @brief Return Frequency of Core System
559 * @return Frequency of Core System
560 */
561uint32_t CLOCK_GetCoreSysClkFreq(void);
562/*! @brief Return Frequency of I2S MCLK Clock
563 * @return Frequency of I2S MCLK Clock
564 */
565uint32_t CLOCK_GetI2SMClkFreq(void);
566/*! @brief Return Frequency of Flexcomm functional Clock
567 * @return Frequency of Flexcomm functional Clock
568 */
569uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
570/*! brief Return Frequency of Usb Clock
571 * return Frequency of Usb Clock.
572 */
573uint32_t CLOCK_GetUsbClkFreq(void);
574/*! @brief Return Frequency of Adc Clock
575 * @return Frequency of Adc Clock.
576 */
577uint32_t CLOCK_GetAdcClkFreq(void);
578/*! @brief Return Frequency of ClockOut
579 * @return Frequency of ClockOut
580 */
581uint32_t CLOCK_GetClockOutClkFreq(void);
582/*! @brief Return Asynchronous APB Clock source
583 * @return Asynchronous APB CLock source
584 */
585__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)
586{
587 return (async_clock_src_t)(uint32_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3UL);
588}
589/*! @brief Return Frequency of Asynchronous APB Clock
590 * @return Frequency of Asynchronous APB Clock Clock
591 */
592uint32_t CLOCK_GetAsyncApbClkFreq(void);
593/*! @brief Return System PLL input clock rate
594 * @return System PLL input clock rate
595 */
596uint32_t CLOCK_GetSystemPLLInClockRate(void);
597
598/*! @brief Return System PLL output clock rate
599 * @param recompute : Forces a PLL rate recomputation if true
600 * @return System PLL output clock rate
601 * @note The PLL rate is cached in the driver in a variable as
602 * the rate computation function can take some time to perform. It
603 * is recommended to use 'false' with the 'recompute' parameter.
604 */
605uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);
606
607/*! @brief Enables and disables PLL bypass mode
608 * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass
609 * @return System PLL output clock rate
610 */
611__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)
612{
613 if (bypass)
614 {
615 SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
616 }
617 else
618 {
619 SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
620 }
621}
622
623/*! @brief Check if PLL is locked or not
624 * @return true if the PLL is locked, false if not locked
625 */
626__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)
627{
628 return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0UL);
629}
630
631/*! @brief Store the current PLL rate
632 * @param rate: Current rate of the PLL
633 * @return Nothing
634 **/
635void CLOCK_SetStoredPLLClockRate(uint32_t rate);
636
637/*! @brief PLL configuration structure flags for 'flags' field
638 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
639 *
640 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
641 * configuration structure must be assigned with the expected PLL frequency. If the
642 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
643 * function and the driver will determine the PLL rate from the currently selected
644 * PLL source. This flag might be used to configure the PLL input clock more accurately
645 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
646 *
647 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
648 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
649 * are not used.<br>
650 */
651#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
652#define PLL_CONFIGFLAG_FORCENOFRACT \
653 (1U << 2U) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or \
654 SS hardware */
655
656/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency
657 * See (MF) field in the SYSPLLSSCTRL1 register in the UM.
658 */
659typedef enum _ss_progmodfm
660{
661 kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */
662 kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */
663 kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */
664 kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */
665 kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */
666 kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */
667 kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */
668 kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */
669} ss_progmodfm_t;
670
671/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth
672 * See (MR) field in the SYSPLLSSCTRL1 register in the UM.
673 */
674typedef enum _ss_progmoddp
675{
676 kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */
677 kSS_MR_K1 = (1 << 23), /*!< k = 1 */
678 kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */
679 kSS_MR_K2 = (3 << 23), /*!< k = 2 */
680 kSS_MR_K3 = (4 << 23), /*!< k = 3 */
681 kSS_MR_K4 = (5 << 23), /*!< k = 4 */
682 kSS_MR_K6 = (6 << 23), /*!< k = 6 */
683 kSS_MR_K8 = (7 << 23) /*!< k = 8 */
684} ss_progmoddp_t;
685
686/*! @brief PLL Spread Spectrum (SS) Modulation waveform control
687 * See (MC) field in the SYSPLLSSCTRL1 register in the UM.<br>
688 * Compensation for low pass filtering of the PLL to get a triangular
689 * modulation at the output of the PLL, giving a flat frequency spectrum.
690 */
691typedef enum _ss_modwvctrl
692{
693 kSS_MC_NOC = (0 << 26), /*!< no compensation */
694 kSS_MC_RECC = (2 << 26), /*!< recommended setting */
695 kSS_MC_MAXC = (3 << 26), /*!< max. compensation */
696} ss_modwvctrl_t;
697
698/*! @brief PLL configuration structure
699 *
700 * This structure can be used to configure the settings for a PLL
701 * setup structure. Fill in the desired configuration for the PLL
702 * and call the PLL setup function to fill in a PLL setup structure.
703 */
704typedef struct _pll_config
705{
706 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
707 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
708 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
709 ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using
710 PLL_CONFIGFLAG_FORCENOFRACT flag */
711 ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using
712 PLL_CONFIGFLAG_FORCENOFRACT flag */
713 ss_modwvctrl_t
714 ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
715 bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using
716 PLL_CONFIGFLAG_FORCENOFRACT flag */
717
718} pll_config_t;
719
720/*! @brief PLL setup structure flags for 'flags' field
721 * These flags control how the PLL setup function sets up the PLL
722 */
723#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */
724#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
725#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */
726#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */
727
728/*! @brief PLL setup structure
729 * This structure can be used to pre-build a PLL setup configuration
730 * at run-time and quickly set the PLL to the configuration. It can be
731 * populated with the PLL setup function. If powering up or waiting
732 * for PLL lock, the PLL input clock source should be configured prior
733 * to PLL setup.
734 */
735typedef struct _pll_setup
736{
737 uint32_t syspllctrl; /*!< PLL control register SYSPLLCTRL */
738 uint32_t syspllndec; /*!< PLL NDEC register SYSPLLNDEC */
739 uint32_t syspllpdec; /*!< PLL PDEC register SYSPLLPDEC */
740 uint32_t syspllssctrl[2]; /*!< PLL SSCTL registers SYSPLLSSCTRL */
741 uint32_t pllRate; /*!< Acutal PLL rate */
742 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
743} pll_setup_t;
744
745/*! @brief PLL status definitions
746 */
747typedef enum _pll_error
748{
749 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
750 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
751 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
752 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
753 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
754 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5) /*!< Requested output rate isn't possible */
755} pll_error_t;
756
757/*! @brief USB clock source definition. */
758typedef enum _clock_usb_src
759{
760 kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */
761 kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */
762 kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
763 kCLOCK_UsbSrcNone = SYSCON_USBCLKSEL_SEL(
764 7) /*!< Use None, this may be selected in order to reduce power when no output is needed. */
765} clock_usb_src_t;
766
767/*! @brief Return System PLL output clock rate from setup structure
768 * @param pSetup : Pointer to a PLL setup structure
769 * @return System PLL output clock rate calculated from the setup structure
770 */
771uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);
772
773/*! @brief Set PLL output based on the passed PLL setup data
774 * @param pControl : Pointer to populated PLL control structure to generate setup with
775 * @param pSetup : Pointer to PLL setup structure to be filled
776 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
777 * @note Actual frequency for setup may vary from the desired frequency based on the
778 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
779 */
780pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
781
782/*! @brief Set PLL output from PLL setup structure (precise frequency)
783 * @param pSetup : Pointer to populated PLL setup structure
784 * @param flagcfg : Flag configuration for PLL config structure
785 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
786 * @note This function will power off the PLL, setup the PLL with the
787 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
788 * and adjust system voltages to the new PLL rate. The function will not
789 * alter any source clocks (ie, main systen clock) that may use the PLL,
790 * so these should be setup prior to and after exiting the function.
791 */
792pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
793
794/**
795 * @brief Set PLL output from PLL setup structure (precise frequency)
796 * @param pSetup : Pointer to populated PLL setup structure
797 * @return kStatus_PLL_Success on success, or PLL setup error code
798 * @note This function will power off the PLL, setup the PLL with the
799 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
800 * and adjust system voltages to the new PLL rate. The function will not
801 * alter any source clocks (ie, main systen clock) that may use the PLL,
802 * so these should be setup prior to and after exiting the function.
803 */
804pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);
805
806/*! @brief Set PLL output based on the multiplier and input frequency
807 * @param multiply_by : multiplier
808 * @param input_freq : Clock input frequency of the PLL
809 * @return Nothing
810 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
811 * function does not disable or enable PLL power, wait for PLL lock,
812 * or adjust system voltages. These must be done in the application.
813 * The function will not alter any source clocks (ie, main systen clock)
814 * that may use the PLL, so these should be setup prior to and after
815 * exiting the function.
816 */
817void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);
818
819/*! @brief Disable USB FS clock.
820 *
821 * Disable USB FS clock.
822 */
823static inline void CLOCK_DisableUsbfs0Clock(void)
824{
825 CLOCK_DisableClock(kCLOCK_Usbd0);
826}
827bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
828
829#if defined(__cplusplus)
830}
831#endif /* __cplusplus */
832
833/*! @} */
834
835#endif /* _FSL_CLOCK_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 21:12:39 +0100