aboutsummaryrefslogtreecommitdiff
path: root/lib/chibios-contrib/ext/mcux-sdk/devices/LPC51U68/system_LPC51U68.c
diff options
context:
space:
mode:
Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/LPC51U68/system_LPC51U68.c')
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC51U68/system_LPC51U68.c367
1 files changed, 367 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC51U68/system_LPC51U68.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC51U68/system_LPC51U68.c
new file mode 100644
index 000000000..6ef77978e
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC51U68/system_LPC51U68.c
@@ -0,0 +1,367 @@
1/*
2** ###################################################################
3** Processors: LPC51U68JBD48
4** LPC51U68JBD64
5**
6** Compilers: GNU C Compiler
7** IAR ANSI C/C++ Compiler for ARM
8** Keil ARM C/C++ Compiler
9** MCUXpresso Compiler
10**
11** Reference manual: LPC51U68 User manual User manual Rev. 1.0 13 Dec 2017
12** Version: rev. 1.0, 2017-12-15
13** Build: b201015
14**
15** Abstract:
16** Provides a system configuration function and a global variable that
17** contains the system frequency. It configures the device and initializes
18** the oscillator (PLL) that is part of the microcontroller device.
19**
20** Copyright 2016 Freescale Semiconductor, Inc.
21** Copyright 2016-2020 NXP
22** All rights reserved.
23**
24** SPDX-License-Identifier: BSD-3-Clause
25**
26** http: www.nxp.com
27** mail: [email protected]
28**
29** Revisions:
30** - rev. 1.0 (2017-12-15)
31** Initial version.
32**
33** ###################################################################
34*/
35
36/*!
37 * @file LPC51U68
38 * @version 1.0
39 * @date 2017-12-15
40 * @brief Device specific configuration file for LPC51U68 (implementation file)
41 *
42 * Provides a system configuration function and a global variable that contains
43 * the system frequency. It configures the device and initializes the oscillator
44 * (PLL) that is part of the microcontroller device.
45 */
46
47#include <stdint.h>
48#include "fsl_device_registers.h"
49
50#define NVALMAX (0x100)
51#define PVALMAX (0x20U)
52#define MVALMAX (0x8000U)
53#define PLL_SSCG0_MDEC_VAL_P (0U) /* MDEC is in bits 16 downto 0 */
54#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */
55#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */
56#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
57#define PLL_PDEC_VAL_P (0U) /* PDEC is in bits 6:0 */
58#define PLL_PDEC_VAL_M (0x3FFUL << PLL_PDEC_VAL_P)
59
60/* ----------------------------------------------------------------------------
61 -- Core clock
62 ---------------------------------------------------------------------------- */
63
64
65static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
66 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
67
68static uint32_t GetWdtOscFreq(void)
69{
70 uint8_t freq_sel, div_sel;
71 div_sel = (uint8_t)((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1UL) << 1UL;
72 freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
73 return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
74}
75
76/* Find decoded N value for raw NDEC value */
77static uint32_t pllDecodeN(uint32_t NDEC)
78{
79 uint32_t n, x, i;
80
81 /* Find NDec */
82 switch (NDEC)
83 {
84 case 0xFFFU:
85 n = 0UL;
86 break;
87 case 0x302U:
88 n = 1UL;
89 break;
90 case 0x202U:
91 n = 2UL;
92 break;
93 default:
94 x = 0x080UL;
95 n = 0xFFFFFFFFUL;
96 for (i = NVALMAX; i >= 3UL; i--)
97 {
98 x = (((x ^ (x >> 2UL) ^ (x >> 3UL) ^ (x >> 4UL)) & 1UL) << 7UL) | ((x >> 1UL) & 0x7FUL);
99 if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
100 {
101 /* Decoded value of NDEC */
102 n = i;
103 }
104 if (n != 0xFFFFFFFFUL)
105 {
106 break;
107 }
108 }
109 break;
110 }
111 return n;
112}
113
114/* Find decoded P value for raw PDEC value */
115static uint32_t pllDecodeP(uint32_t PDEC)
116{
117 uint32_t p, x, i;
118 /* Find PDec */
119 switch (PDEC)
120 {
121 case 0xFFU:
122 p = 0UL;
123 break;
124 case 0x62U:
125 p = 1UL;
126 break;
127 case 0x42U:
128 p = 2UL;
129 break;
130 default:
131 x = 0x10UL;
132 p = 0xFFFFFFFFUL;
133 for (i = PVALMAX; i >= 3UL; i--)
134 {
135 x = (((x ^ (x >> 2UL)) & 1UL) << 4UL) | ((x >> 1UL) & 0xFUL);
136 if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
137 {
138 /* Decoded value of PDEC */
139 p = i;
140 }
141 if (p != 0xFFFFFFFFUL)
142 {
143 break;
144 }
145 }
146 break;
147 }
148 return p;
149}
150
151/* Find decoded M value for raw MDEC value */
152static uint32_t pllDecodeM(uint32_t MDEC)
153{
154 uint32_t m, i, x;
155
156 /* Find MDec */
157 switch (MDEC)
158 {
159 case 0xFFFFFU:
160 m = 0UL;
161 break;
162 case 0x18003U:
163 m = 1UL;
164 break;
165 case 0x10003U:
166 m = 2UL;
167 break;
168 default:
169 x = 0x04000UL;
170 m = 0xFFFFFFFFUL;
171 for (i = MVALMAX; i >= 3UL; i--)
172 {
173 x = (((x ^ (x >> 1UL)) & 1UL) << 14UL) | ((x >> 1UL) & 0x3FFFUL);
174 if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC)
175 {
176 /* Decoded value of MDEC */
177 m = i;
178 }
179 if (m != 0xFFFFFFFFUL)
180 {
181 break;
182 }
183 }
184 break;
185 }
186 return m;
187}
188
189/* Get predivider (N) from PLL NDEC setting */
190static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
191{
192 uint32_t preDiv = 1U;
193
194 /* Direct input is not used? */
195 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0UL)
196 {
197 /* Decode NDEC value to get (N) pre divider */
198 preDiv = pllDecodeN(nDecReg & 0x3FFUL);
199 if (preDiv == 0UL)
200 {
201 preDiv = 1U;
202 }
203 }
204 /* Adjusted by 1, directi is used to bypass */
205 return preDiv;
206}
207
208/* Get postdivider (P) from PLL PDEC setting */
209static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
210{
211 uint32_t postDiv = 1U;
212
213 /* Direct input is not used? */
214 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0UL)
215 {
216 /* Decode PDEC value to get (P) post divider */
217 postDiv = 2UL * pllDecodeP(pDecReg & 0x7FUL);
218 if (postDiv == 0UL)
219 {
220 postDiv = 2U;
221 }
222 }
223 /* Adjusted by 1, directo is used to bypass */
224 return postDiv;
225}
226
227/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
228static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
229{
230 uint32_t mMult = 1U;
231
232 /* Decode MDEC value to get (M) multiplier */
233 mMult = pllDecodeM(mDecReg & 0x1FFFFUL);
234 /* Extra multiply by 2 needed? */
235 if ((ctrlReg & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) == 0UL)
236 {
237 mMult = mMult << 1;
238 }
239 if (mMult == 0UL)
240 {
241 mMult = 1U;
242 }
243 return mMult;
244}
245
246
247
248/* ----------------------------------------------------------------------------
249 -- Core clock
250 ---------------------------------------------------------------------------- */
251
252uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
253
254/* ----------------------------------------------------------------------------
255 -- SystemInit()
256 ---------------------------------------------------------------------------- */
257
258void SystemInit (void) {
259
260#if defined(__CODE_RED)
261 extern void(*const g_pfnVectors[]) (void);
262 SCB->VTOR = (uint32_t) &g_pfnVectors;
263#else
264 extern void *__Vectors;
265 SCB->VTOR = (uint32_t) &__Vectors;
266#endif
267
268 SystemInitHook();
269}
270
271/* ----------------------------------------------------------------------------
272 -- SystemCoreClockUpdate()
273 ---------------------------------------------------------------------------- */
274
275void SystemCoreClockUpdate (void) {
276 uint32_t clkRate = 0U;
277 uint32_t prediv, postdiv;
278 uint32_t bypassccodiv2;
279 uint64_t workRate;
280
281 switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
282 {
283 case 0x00U: /* MAINCLKSELA clock (main_clk_a)*/
284 switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
285 {
286 case 0x00U: /* FRO 12 MHz (fro_12m) */
287 clkRate = CLK_FRO_12MHZ;
288 break;
289 case 0x01U: /* CLKIN source (clk_in) */
290 clkRate = CLK_CLK_IN;
291 break;
292 case 0x02U: /* Watchdog oscillator (wdt_clk) */
293 clkRate = GetWdtOscFreq();
294 break;
295 default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
296 if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) == SYSCON_FROCTRL_SEL_MASK)
297 {
298 clkRate = CLK_FRO_96MHZ;
299 }
300 else
301 {
302 clkRate = CLK_FRO_48MHZ;
303 }
304 break;
305 }
306 break;
307 case 0x02U: /* System PLL clock (pll_clk)*/
308 switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
309 {
310 case 0x00U: /* FRO 12 MHz (fro_12m) */
311 clkRate = CLK_FRO_12MHZ;
312 break;
313 case 0x01U: /* CLKIN source (clk_in) */
314 clkRate = CLK_CLK_IN;
315 break;
316 case 0x02U: /* Watchdog oscillator (wdt_clk) */
317 clkRate = GetWdtOscFreq();
318 break;
319 case 0x03U: /* RTC oscillator 32 kHz output (32k_clk) */
320 clkRate = CLK_RTC_32K_CLK;
321 break;
322 default:
323 clkRate = 0U;
324 break;
325 }
326 if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0U)
327 {
328 /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
329 prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
330 postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
331 /* Adjust input clock */
332 clkRate = clkRate / prediv;
333 /* If using the SS, use the multiplier */
334 if ((SYSCON->SYSPLLSSCTRL0 & SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK) == SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK)
335 {
336 /* MDEC used for rate */
337 workRate = (uint64_t)(clkRate) * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLSSCTRL0);
338 }
339 else
340 {
341 /* SS multipler used for rate */
342 workRate = 0UL;
343 /* Adjust by fractional */
344 bypassccodiv2 = (uint32_t)((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) >> SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT);
345 workRate = ((2U - bypassccodiv2) * (uint64_t)clkRate) * ((SYSCON->SYSPLLSSCTRL1 & 0x7FFFFUL) >> 11UL);
346 }
347 clkRate = (uint32_t)workRate / postdiv;
348 }
349 break;
350 case 0x03U: /* RTC oscillator 32 kHz output (32k_clk) */
351 clkRate = CLK_RTC_32K_CLK;
352 break;
353 default:
354 clkRate = 0U;
355 break;
356 }
357 SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL);
358
359}
360
361/* ----------------------------------------------------------------------------
362 -- SystemInitHook()
363 ---------------------------------------------------------------------------- */
364
365__attribute__ ((weak)) void SystemInitHook (void) {
366 /* Void implementation of the weak function. */
367}
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 20:22:57 +0100