37 files changed, 28379 insertions, 0 deletions

diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/LPC54005.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/LPC54005.h
new file mode 100644
index 000000000..2e7faec90
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/LPC54005.h
@@ -0,0 +1,17145 @@
+/*
+** ###################################################################
+**     Processors:          LPC54005JBD100
+**                          LPC54005JET100
+**
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
+**     Version:             rev. 1.2, 2017-06-08
+**     Build:               b200304
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for LPC54005
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2020 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**     - rev. 1.2 (2017-06-08)
+**         Remove RTC_CTRL_RTC_OSC_BYPASS.
+**         SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
+**         Remove RESET and HALT from SYSCON_AHBCLKDIV.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54005.h
+ * @version 1.2
+ * @date 2017-06-08
+ * @brief CMSIS Peripheral Access Layer for LPC54005
+ *
+ * CMSIS Peripheral Access Layer for LPC54005
+ */
+
+#ifndef _LPC54005_H_
+#define _LPC54005_H_                             /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0002U
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 73                 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  WDT_BOD_IRQn                 = 0,                /**< Windowed watchdog timer, Brownout detect */
+  DMA0_IRQn                    = 1,                /**< DMA controller */
+  GINT0_IRQn                   = 2,                /**< GPIO group 0 */
+  GINT1_IRQn                   = 3,                /**< GPIO group 1 */
+  PIN_INT0_IRQn                = 4,                /**< Pin interrupt 0 or pattern match engine slice 0 */
+  PIN_INT1_IRQn                = 5,                /**< Pin interrupt 1or pattern match engine slice 1 */
+  PIN_INT2_IRQn                = 6,                /**< Pin interrupt 2 or pattern match engine slice 2 */
+  PIN_INT3_IRQn                = 7,                /**< Pin interrupt 3 or pattern match engine slice 3 */
+  UTICK0_IRQn                  = 8,                /**< Micro-tick Timer */
+  MRT0_IRQn                    = 9,                /**< Multi-rate timer */
+  CTIMER0_IRQn                 = 10,               /**< Standard counter/timer CTIMER0 */
+  CTIMER1_IRQn                 = 11,               /**< Standard counter/timer CTIMER1 */
+  SCT0_IRQn                    = 12,               /**< SCTimer/PWM */
+  CTIMER3_IRQn                 = 13,               /**< Standard counter/timer CTIMER3 */
+  FLEXCOMM0_IRQn               = 14,               /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM1_IRQn               = 15,               /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM2_IRQn               = 16,               /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM3_IRQn               = 17,               /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM4_IRQn               = 18,               /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM5_IRQn               = 19,               /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
+  FLEXCOMM6_IRQn               = 20,               /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+  FLEXCOMM7_IRQn               = 21,               /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+  ADC0_SEQA_IRQn               = 22,               /**< ADC0 sequence A completion. */
+  ADC0_SEQB_IRQn               = 23,               /**< ADC0 sequence B completion. */
+  ADC0_THCMP_IRQn              = 24,               /**< ADC0 threshold compare and error. */
+  DMIC0_IRQn                   = 25,               /**< Digital microphone and DMIC subsystem */
+  HWVAD0_IRQn                  = 26,               /**< Hardware Voice Activity Detector */
+  USB0_NEEDCLK_IRQn            = 27,               /**< USB Activity Wake-up Interrupt */
+  USB0_IRQn                    = 28,               /**< USB device */
+  RTC_IRQn                     = 29,               /**< RTC alarm and wake-up interrupts */
+  FLEXCOMM10_IRQn              = 30,               /**< Flexcomm Interface 10 (SPI, FLEXCOMM) */
+  Reserved47_IRQn              = 31,               /**< Reserved interrupt */
+  PIN_INT4_IRQn                = 32,               /**< Pin interrupt 4 or pattern match engine slice 4 int */
+  PIN_INT5_IRQn                = 33,               /**< Pin interrupt 5 or pattern match engine slice 5 int */
+  PIN_INT6_IRQn                = 34,               /**< Pin interrupt 6 or pattern match engine slice 6 int */
+  PIN_INT7_IRQn                = 35,               /**< Pin interrupt 7 or pattern match engine slice 7 int */
+  CTIMER2_IRQn                 = 36,               /**< Standard counter/timer CTIMER2 */
+  CTIMER4_IRQn                 = 37,               /**< Standard counter/timer CTIMER4 */
+  RIT_IRQn                     = 38,               /**< Repetitive Interrupt Timer */
+  SPIFI0_IRQn                  = 39,               /**< SPI flash interface */
+  FLEXCOMM8_IRQn               = 40,               /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM9_IRQn               = 41,               /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
+  SDIO_IRQn                    = 42,               /**< SD/MMC  */
+  CAN0_IRQ0_IRQn               = 43,               /**< CAN0 interrupt0 */
+  CAN0_IRQ1_IRQn               = 44,               /**< CAN0 interrupt1 */
+  CAN1_IRQ0_IRQn               = 45,               /**< CAN1 interrupt0 */
+  CAN1_IRQ1_IRQn               = 46,               /**< CAN1 interrupt1 */
+  USB1_IRQn                    = 47,               /**< USB1 interrupt */
+  USB1_NEEDCLK_IRQn            = 48,               /**< USB1 activity */
+  ETHERNET_IRQn                = 49,               /**< Ethernet */
+  ETHERNET_PMT_IRQn            = 50,               /**< Ethernet power management interrupt */
+  ETHERNET_MACLP_IRQn          = 51,               /**< Ethernet MAC interrupt */
+  Reserved68_IRQn              = 52,               /**< Reserved interrupt */
+  LCD_IRQn                     = 53,               /**< LCD interrupt */
+  SHA_IRQn                     = 54,               /**< SHA interrupt */
+  SMARTCARD0_IRQn              = 55,               /**< Smart card 0 interrupt */
+  SMARTCARD1_IRQn              = 56                /**< Smart card 1 interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               3         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_LPC54005.h"           /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup dma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according  to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+    kDmaRequestFlexcomm0Rx          = 0U,          /**< Flexcomm Interface 0 RX/I2C Slave */
+    kDmaRequestFlexcomm0Tx          = 1U,          /**< Flexcomm Interface 0 TX/I2C Master */
+    kDmaRequestFlexcomm1Rx          = 2U,          /**< Flexcomm Interface 1 RX/I2C Slave */
+    kDmaRequestFlexcomm1Tx          = 3U,          /**< Flexcomm Interface 1 TX/I2C Master */
+    kDmaRequestFlexcomm2Rx          = 4U,          /**< Flexcomm Interface 2 RX/I2C Slave */
+    kDmaRequestFlexcomm2Tx          = 5U,          /**< Flexcomm Interface 2 TX/I2C Master */
+    kDmaRequestFlexcomm3Rx          = 6U,          /**< Flexcomm Interface 3 RX/I2C Slave */
+    kDmaRequestFlexcomm3Tx          = 7U,          /**< Flexcomm Interface 3 TX/I2C Master */
+    kDmaRequestFlexcomm4Rx          = 8U,          /**< Flexcomm Interface 4 RX/I2C Slave */
+    kDmaRequestFlexcomm4Tx          = 9U,          /**< Flexcomm Interface 4 TX/I2C Master */
+    kDmaRequestFlexcomm5Rx          = 10U,         /**< Flexcomm Interface 5 RX/I2C Slave */
+    kDmaRequestFlexcomm5Tx          = 11U,         /**< Flexcomm Interface 5 TX/I2C Master */
+    kDmaRequestFlexcomm6Rx          = 12U,         /**< Flexcomm Interface 6 RX/I2C Slave */
+    kDmaRequestFlexcomm6Tx          = 13U,         /**< Flexcomm Interface 6 TX/I2C Master */
+    kDmaRequestFlexcomm7Rx          = 14U,         /**< Flexcomm Interface 7 RX/I2C Slave */
+    kDmaRequestFlexcomm7Tx          = 15U,         /**< Flexcomm Interface 7 TX/I2C Master */
+    kDmaRequestDMIC0                = 16U,         /**< Digital microphone interface 0 channel 0 */
+    kDmaRequestDMIC1                = 17U,         /**< Digital microphone interface 0 channel 1 */
+    kDmaRequestSPIFI                = 18U,         /**< SPI Flash Interface */
+    kDmaRequestSHA                  = 19U,         /**< Secure Hash Algorithm */
+    kDmaRequestFlexcomm8Rx          = 20U,         /**< Flexcomm Interface 8 RX/I2C Slave */
+    kDmaRequestFlexcomm8Tx          = 21U,         /**< Flexcomm Interface 8 TX/I2C Slave */
+    kDmaRequestFlexcomm9Rx          = 22U,         /**< Flexcomm Interface 9 RX/I2C Slave */
+    kDmaRequestFlexcomm9Tx          = 23U,         /**< Flexcomm Interface 9 TX/I2C Slave */
+    kDmaRequestSMARTCARD0_RX        = 24U,         /**< SMARTCARD0 RX */
+    kDmaRequestSMARTCARD0_TX        = 25U,         /**< SMARTCARD0 TX */
+    kDmaRequestSMARTCARD1_RX        = 26U,         /**< SMARTCARD1 RX */
+    kDmaRequestSMARTCARD1_TX        = 27U,         /**< SMARTCARD1 TX */
+    kDmaRequestFlexcomm10Rx         = 28U,         /**< Flexcomm Interface 10 RX */
+    kDmaRequestFlexcomm10Tx         = 29U,         /**< Flexcomm Interface 10 TX */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
+  __IO uint32_t INSEL;                             /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
+  __IO uint32_t SEQ_CTRL[2];                       /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
+  __I  uint32_t SEQ_GDAT[2];                       /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
+       uint8_t RESERVED_0[8];
+  __I  uint32_t DAT[12];                           /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
+  __IO uint32_t THR0_LOW;                          /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
+  __IO uint32_t THR1_LOW;                          /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
+  __IO uint32_t THR0_HIGH;                         /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
+  __IO uint32_t THR1_HIGH;                         /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
+  __IO uint32_t CHAN_THRSEL;                       /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
+  __IO uint32_t INTEN;                             /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
+  __IO uint32_t FLAGS;                             /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
+  __IO uint32_t STARTUP;                           /**< ADC Startup register., offset: 0x6C */
+  __IO uint32_t CALIB;                             /**< ADC Calibration register., offset: 0x70 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
+/*! @{ */
+#define ADC_CTRL_CLKDIV_MASK                     (0xFFU)
+#define ADC_CTRL_CLKDIV_SHIFT                    (0U)
+/*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce
+ *    the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically,
+ *    software should program the smallest value in this field that yields this maximum clock rate or
+ *    slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may
+ *    be desirable. This field is ignored in the asynchronous operating mode.
+ */
+#define ADC_CTRL_CLKDIV(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
+#define ADC_CTRL_ASYNMODE_MASK                   (0x100U)
+#define ADC_CTRL_ASYNMODE_SHIFT                  (8U)
+/*! ASYNMODE - Select clock mode.
+ *  0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in
+ *       the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to
+ *       eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger.
+ *       In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC
+ *       input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger
+ *       pulse.
+ *  0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
+ */
+#define ADC_CTRL_ASYNMODE(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
+#define ADC_CTRL_RESOL_MASK                      (0x600U)
+#define ADC_CTRL_RESOL_SHIFT                     (9U)
+/*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher
+ *    conversion rates. A single conversion (including one conversion in a burst or sequence) requires the
+ *    selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when
+ *    the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable
+ *    results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate
+ *    for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system
+ *    clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution
+ *  0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field.
+ *  0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field.
+ *  0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field.
+ *  0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field.
+ */
+#define ADC_CTRL_RESOL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
+#define ADC_CTRL_BYPASSCAL_MASK                  (0x800U)
+#define ADC_CTRL_BYPASSCAL_SHIFT                 (11U)
+/*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset
+ *    error is not a concern in the application.
+ *  0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for
+ *       offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may
+ *       be warranted periodically - especially if operating conditions have changed.
+ *  0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC -
+ *       particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set.
+ */
+#define ADC_CTRL_BYPASSCAL(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
+#define ADC_CTRL_TSAMP_MASK                      (0x7000U)
+#define ADC_CTRL_TSAMP_SHIFT                     (12U)
+/*! TSAMP - Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion
+ *    is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions
+ *    and the output impedance of the analog source, longer sampling times may be required. See
+ *    Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to
+ *    seven, by which the sample period will be extended. The total conversion time will increase by
+ *    the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A
+ *    complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will
+ *    be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will
+ *    require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock
+ *    cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be
+ *    extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require
+ *    22 ADC clocks.
+ */
+#define ADC_CTRL_TSAMP(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
+/*! @} */
+
+/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
+/*! @{ */
+#define ADC_INSEL_SEL_MASK                       (0x3U)
+#define ADC_INSEL_SEL_SHIFT                      (0U)
+/*! SEL - Selects the input source for channel 0. All other values are reserved.
+ *  0b00..ADC0_IN0 function.
+ *  0b11..Internal temperature sensor.
+ */
+#define ADC_INSEL_SEL(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
+/*! @{ */
+#define ADC_SEQ_CTRL_CHANNELS_MASK               (0xFFFU)
+#define ADC_SEQ_CTRL_CHANNELS_SHIFT              (0U)
+/*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this
+ *    sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be
+ *    included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1
+ *    and so forth. When this conversion sequence is triggered, either by a hardware trigger or via
+ *    software command, ADC conversions will be performed on each enabled channel, in sequence,
+ *    beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31)
+ *    is LOW. It is allowed to change this field and set bit 31 in the same write.
+ */
+#define ADC_SEQ_CTRL_CHANNELS(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
+#define ADC_SEQ_CTRL_TRIGGER_MASK                (0x3F000U)
+#define ADC_SEQ_CTRL_TRIGGER_SHIFT               (12U)
+/*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion
+ *    sequence to be initiated. Program the trigger input number in this field. See Table 476. In order
+ *    to avoid generating a spurious trigger, it is recommended writing to this field only when
+ *    SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
+ */
+#define ADC_SEQ_CTRL_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
+#define ADC_SEQ_CTRL_TRIGPOL_MASK                (0x40000U)
+#define ADC_SEQ_CTRL_TRIGPOL_SHIFT               (18U)
+/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In
+ *    order to avoid generating a spurious trigger, it is recommended writing to this field only when
+ *    SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
+ *  0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
+ *  0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
+ */
+#define ADC_SEQ_CTRL_TRIGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
+#define ADC_SEQ_CTRL_SYNCBYPASS_MASK             (0x80000U)
+#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT            (19U)
+/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization
+ *    flip-flop stages and therefore shorten the time between the trigger input signal and the start of a
+ *    conversion. There are slightly different criteria for whether or not this bit can be set
+ *    depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0):
+ *    Synchronization may be bypassed (this bit may be set) if the selected trigger source is already
+ *    synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer).
+ *    Whether this bit is set or not, a trigger pulse must be maintained for at least one system
+ *    clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be
+ *    bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse
+ *    will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and
+ *    on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be
+ *    maintained for one system clock period.
+ *  0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled.
+ *  0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled.
+ */
+#define ADC_SEQ_CTRL_SYNCBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
+#define ADC_SEQ_CTRL_START_MASK                  (0x4000000U)
+#define ADC_SEQ_CTRL_START_SHIFT                 (26U)
+/*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The
+ *    behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this
+ *    bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a
+ *    conversion sequence. It will consequently always read back as a zero.
+ */
+#define ADC_SEQ_CTRL_START(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
+#define ADC_SEQ_CTRL_BURST_MASK                  (0x8000000U)
+#define ADC_SEQ_CTRL_BURST_SHIFT                 (27U)
+/*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled
+ *    through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions
+ *    can be halted by clearing this bit. The sequence currently in progress will be completed before
+ *    conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
+ */
+#define ADC_SEQ_CTRL_BURST(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
+#define ADC_SEQ_CTRL_SINGLESTEP_MASK             (0x10000000U)
+#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT            (28U)
+/*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a
+ *    single conversion on the next channel in the sequence instead of the default response of
+ *    launching an entire sequence of conversions. Once all of the channels comprising a sequence have
+ *    been converted, a subsequent trigger will repeat the sequence beginning with the first enabled
+ *    channel. Interrupt generation will still occur either after each individual conversion or at
+ *    the end of the entire sequence, depending on the state of the MODE bit.
+ */
+#define ADC_SEQ_CTRL_SINGLESTEP(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
+#define ADC_SEQ_CTRL_LOWPRIO_MASK                (0x20000000U)
+#define ADC_SEQ_CTRL_LOWPRIO_SHIFT               (29U)
+/*! LOWPRIO - Set priority for sequence A.
+ *  0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
+ *  0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence
+ *       software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion
+ *       currently in progress will be terminated. The A sequence that was interrupted will automatically resume
+ *       after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the
+ *       conversion sequence will resume from that point.
+ */
+#define ADC_SEQ_CTRL_LOWPRIO(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
+#define ADC_SEQ_CTRL_MODE_MASK                   (0x40000000U)
+#define ADC_SEQ_CTRL_MODE_SHIFT                  (30U)
+/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence
+ *    will be accomplished via reading the global data register (SEQA_GDAT) at the end of each
+ *    conversion, or the individual channel result registers at the end of the entire sequence. Impacts
+ *    when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which
+ *    overrun conditions contribute to an overrun interrupt as described below.
+ *  0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC
+ *       conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The
+ *       OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger
+ *       if enabled.
+ *  0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A
+ *       conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in
+ *       this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun
+ *       interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
+ */
+#define ADC_SEQ_CTRL_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
+#define ADC_SEQ_CTRL_SEQ_ENA_MASK                (0x80000000U)
+#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT               (31U)
+/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be
+ *    taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state
+ *    (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered
+ *    immediately upon being enabled. In order to avoid spuriously triggering the sequence, care
+ *    should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE
+ *    state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be
+ *    triggered immediately upon being enabled.
+ *  0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence
+ *       n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is
+ *       re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
+ *  0b1..Enabled. Sequence n is enabled.
+ */
+#define ADC_SEQ_CTRL_SEQ_ENA(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
+/*! @} */
+
+/* The count of ADC_SEQ_CTRL */
+#define ADC_SEQ_CTRL_COUNT                       (2U)
+
+/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
+/*! @{ */
+#define ADC_SEQ_GDAT_RESULT_MASK                 (0xFFF0U)
+#define ADC_SEQ_GDAT_RESULT_SHIFT                (4U)
+/*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion
+ *    performed under conversion sequence associated with this register. The result is a binary
+ *    fraction representing the voltage on the currently-selected input channel as it falls within the
+ *    range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less
+ *    than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input
+ *    was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this
+ *    result has not yet been read.
+ */
+#define ADC_SEQ_GDAT_RESULT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
+#define ADC_SEQ_GDAT_THCMPRANGE_MASK             (0x30000U)
+#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT            (16U)
+/*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or
+ *    within the range established by the designated threshold comparison registers (THRn_LOW and
+ *    THRn_HIGH).
+ */
+#define ADC_SEQ_GDAT_THCMPRANGE(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
+#define ADC_SEQ_GDAT_THCMPCROSS_MASK             (0xC0000U)
+#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT            (18U)
+/*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a
+ *    crossing of the threshold level established by the designated LOW threshold comparison register
+ *    (THRn_LOW) and, if so, in what direction the crossing occurred.
+ */
+#define ADC_SEQ_GDAT_THCMPCROSS(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
+#define ADC_SEQ_GDAT_CHN_MASK                    (0x3C000000U)
+#define ADC_SEQ_GDAT_CHN_SHIFT                   (26U)
+/*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000
+ *    identifies channel 0, 0001 channel 1, etc.).
+ */
+#define ADC_SEQ_GDAT_CHN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
+#define ADC_SEQ_GDAT_OVERRUN_MASK                (0x40000000U)
+#define ADC_SEQ_GDAT_OVERRUN_SHIFT               (30U)
+/*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a
+ *    previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along
+ *    with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun
+ *    interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set
+ *    to '0' (and if the overrun interrupt is enabled).
+ */
+#define ADC_SEQ_GDAT_OVERRUN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
+#define ADC_SEQ_GDAT_DATAVALID_MASK              (0x80000000U)
+#define ADC_SEQ_GDAT_DATAVALID_SHIFT             (31U)
+/*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded
+ *    into the RESULT field. It is cleared whenever this register is read. This bit will cause a
+ *    conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that
+ *    sequence is set to 0 (and if the interrupt is enabled).
+ */
+#define ADC_SEQ_GDAT_DATAVALID(x)                (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
+/*! @} */
+
+/* The count of ADC_SEQ_GDAT */
+#define ADC_SEQ_GDAT_COUNT                       (2U)
+
+/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
+/*! @{ */
+#define ADC_DAT_RESULT_MASK                      (0xFFF0U)
+#define ADC_DAT_RESULT_SHIFT                     (4U)
+/*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed
+ *    on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin,
+ *    as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on
+ *    the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that
+ *    the voltage on the input was close to, equal to, or greater than that on VREFP.
+ */
+#define ADC_DAT_RESULT(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
+#define ADC_DAT_THCMPRANGE_MASK                  (0x30000U)
+#define ADC_DAT_THCMPRANGE_SHIFT                 (16U)
+/*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion
+ *    was greater than or equal to the value programmed into the designated LOW threshold register
+ *    (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold
+ *    register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value
+ *    programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last
+ *    completed conversion was greater than the value programmed into the designated HIGH threshold
+ *    register (THRn_HIGH). 0x3 = Reserved.
+ */
+#define ADC_DAT_THCMPRANGE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
+#define ADC_DAT_THCMPCROSS_MASK                  (0xC0000U)
+#define ADC_DAT_THCMPCROSS_SHIFT                 (18U)
+/*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The
+ *    most recent completed conversion on this channel had the same relationship (above or below) to
+ *    the threshold value established by the designated LOW threshold register (THRn_LOW) as did the
+ *    previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing
+ *    Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the
+ *    previous sample on this channel was above the threshold value established by the designated LOW
+ *    threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward
+ *    Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred
+ *    - i.e. the previous sample on this channel was below the threshold value established by the
+ *    designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
+ */
+#define ADC_DAT_THCMPCROSS(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
+#define ADC_DAT_CHANNEL_MASK                     (0x3C000000U)
+#define ADC_DAT_CHANNEL_SHIFT                    (26U)
+/*! CHANNEL - This field is hard-coded to contain the channel number that this particular register
+ *    relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1
+ *    register, etc)
+ */
+#define ADC_DAT_CHANNEL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
+#define ADC_DAT_OVERRUN_MASK                     (0x40000000U)
+#define ADC_DAT_OVERRUN_SHIFT                    (30U)
+/*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and
+ *    overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit
+ *    is set. This bit is cleared, along with the DONE bit, whenever this register is read or when
+ *    the data related to this channel is read from either of the global SEQn_GDAT registers. This
+ *    bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if
+ *    the overrun interrupt is enabled. While it is allowed to include the same channels in both
+ *    conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the
+ *    data registers associated with any of the channels that are shared between the two sequences. Any
+ *    erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
+ */
+#define ADC_DAT_OVERRUN(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
+#define ADC_DAT_DATAVALID_MASK                   (0x80000000U)
+#define ADC_DAT_DATAVALID_SHIFT                  (31U)
+/*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is
+ *    cleared whenever this register is read or when the data related to this channel is read from
+ *    either of the global SEQn_GDAT registers. While it is allowed to include the same channels in
+ *    both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in
+ *    the data registers associated with any of the channels that are shared between the two
+ *    sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
+ */
+#define ADC_DAT_DATAVALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
+/*! @} */
+
+/* The count of ADC_DAT */
+#define ADC_DAT_COUNT                            (12U)
+
+/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
+/*! @{ */
+#define ADC_THR0_LOW_THRLOW_MASK                 (0xFFF0U)
+#define ADC_THR0_LOW_THRLOW_SHIFT                (4U)
+/*! THRLOW - Low threshold value against which ADC results will be compared
+ */
+#define ADC_THR0_LOW_THRLOW(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
+/*! @} */
+
+/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
+/*! @{ */
+#define ADC_THR1_LOW_THRLOW_MASK                 (0xFFF0U)
+#define ADC_THR1_LOW_THRLOW_SHIFT                (4U)
+/*! THRLOW - Low threshold value against which ADC results will be compared
+ */
+#define ADC_THR1_LOW_THRLOW(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
+/*! @} */
+
+/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
+/*! @{ */
+#define ADC_THR0_HIGH_THRHIGH_MASK               (0xFFF0U)
+#define ADC_THR0_HIGH_THRHIGH_SHIFT              (4U)
+/*! THRHIGH - High threshold value against which ADC results will be compared
+ */
+#define ADC_THR0_HIGH_THRHIGH(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
+/*! @} */
+
+/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
+/*! @{ */
+#define ADC_THR1_HIGH_THRHIGH_MASK               (0xFFF0U)
+#define ADC_THR1_HIGH_THRHIGH_SHIFT              (4U)
+/*! THRHIGH - High threshold value against which ADC results will be compared
+ */
+#define ADC_THR1_HIGH_THRHIGH(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
+/*! @} */
+
+/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
+/*! @{ */
+#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK          (0x1U)
+#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT         (0U)
+/*! CH0_THRSEL - Threshold select for channel 0.
+ *  0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
+ *  0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
+ */
+#define ADC_CHAN_THRSEL_CH0_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK          (0x2U)
+#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT         (1U)
+/*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH1_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK          (0x4U)
+#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT         (2U)
+/*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH2_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK          (0x8U)
+#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT         (3U)
+/*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH3_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK          (0x10U)
+#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT         (4U)
+/*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH4_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK          (0x20U)
+#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT         (5U)
+/*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH5_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK          (0x40U)
+#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT         (6U)
+/*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH6_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK          (0x80U)
+#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT         (7U)
+/*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH7_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK          (0x100U)
+#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT         (8U)
+/*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH8_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK          (0x200U)
+#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT         (9U)
+/*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH9_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK         (0x400U)
+#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT        (10U)
+/*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH10_THRSEL(x)           (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK         (0x800U)
+#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT        (11U)
+/*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH11_THRSEL(x)           (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
+/*! @} */
+
+/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
+/*! @{ */
+#define ADC_INTEN_SEQA_INTEN_MASK                (0x1U)
+#define ADC_INTEN_SEQA_INTEN_SHIFT               (0U)
+/*! SEQA_INTEN - Sequence A interrupt enable.
+ *  0b0..Disabled. The sequence A interrupt/DMA trigger is disabled.
+ *  0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of
+ *       each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of
+ *       conversions, depending on the MODE bit in the SEQA_CTRL register.
+ */
+#define ADC_INTEN_SEQA_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
+#define ADC_INTEN_SEQB_INTEN_MASK                (0x2U)
+#define ADC_INTEN_SEQB_INTEN_SHIFT               (1U)
+/*! SEQB_INTEN - Sequence B interrupt enable.
+ *  0b0..Disabled. The sequence B interrupt/DMA trigger is disabled.
+ *  0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of
+ *       each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of
+ *       conversions, depending on the MODE bit in the SEQB_CTRL register.
+ */
+#define ADC_INTEN_SEQB_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
+#define ADC_INTEN_OVR_INTEN_MASK                 (0x4U)
+#define ADC_INTEN_OVR_INTEN_SHIFT                (2U)
+/*! OVR_INTEN - Overrun interrupt enable.
+ *  0b0..Disabled. The overrun interrupt is disabled.
+ *  0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel
+ *       data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular
+ *       sequence is 0, then an overrun in the global data register for that sequence will also cause this
+ *       interrupt/DMA trigger to be asserted.
+ */
+#define ADC_INTEN_OVR_INTEN(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
+#define ADC_INTEN_ADCMPINTEN0_MASK               (0x18U)
+#define ADC_INTEN_ADCMPINTEN0_SHIFT              (3U)
+/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0.
+ *  0b00..Disabled.
+ *  0b01..Outside threshold.
+ *  0b10..Crossing threshold.
+ *  0b11..Reserved
+ */
+#define ADC_INTEN_ADCMPINTEN0(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
+#define ADC_INTEN_ADCMPINTEN1_MASK               (0x60U)
+#define ADC_INTEN_ADCMPINTEN1_SHIFT              (5U)
+/*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN1(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
+#define ADC_INTEN_ADCMPINTEN2_MASK               (0x180U)
+#define ADC_INTEN_ADCMPINTEN2_SHIFT              (7U)
+/*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN2(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
+#define ADC_INTEN_ADCMPINTEN3_MASK               (0x600U)
+#define ADC_INTEN_ADCMPINTEN3_SHIFT              (9U)
+/*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN3(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
+#define ADC_INTEN_ADCMPINTEN4_MASK               (0x1800U)
+#define ADC_INTEN_ADCMPINTEN4_SHIFT              (11U)
+/*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN4(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
+#define ADC_INTEN_ADCMPINTEN5_MASK               (0x6000U)
+#define ADC_INTEN_ADCMPINTEN5_SHIFT              (13U)
+/*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN5(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
+#define ADC_INTEN_ADCMPINTEN6_MASK               (0x18000U)
+#define ADC_INTEN_ADCMPINTEN6_SHIFT              (15U)
+/*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN6(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
+#define ADC_INTEN_ADCMPINTEN7_MASK               (0x60000U)
+#define ADC_INTEN_ADCMPINTEN7_SHIFT              (17U)
+/*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN7(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
+#define ADC_INTEN_ADCMPINTEN8_MASK               (0x180000U)
+#define ADC_INTEN_ADCMPINTEN8_SHIFT              (19U)
+/*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN8(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
+#define ADC_INTEN_ADCMPINTEN9_MASK               (0x600000U)
+#define ADC_INTEN_ADCMPINTEN9_SHIFT              (21U)
+/*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN9(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
+#define ADC_INTEN_ADCMPINTEN10_MASK              (0x1800000U)
+#define ADC_INTEN_ADCMPINTEN10_SHIFT             (23U)
+/*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN10(x)                (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
+#define ADC_INTEN_ADCMPINTEN11_MASK              (0x6000000U)
+#define ADC_INTEN_ADCMPINTEN11_SHIFT             (25U)
+/*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN11(x)                (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
+/*! @} */
+
+/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
+/*! @{ */
+#define ADC_FLAGS_THCMP0_MASK                    (0x1U)
+#define ADC_FLAGS_THCMP0_SHIFT                   (0U)
+/*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or
+ *    a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by
+ *    writing a 1.
+ */
+#define ADC_FLAGS_THCMP0(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
+#define ADC_FLAGS_THCMP1_MASK                    (0x2U)
+#define ADC_FLAGS_THCMP1_SHIFT                   (1U)
+/*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP1(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
+#define ADC_FLAGS_THCMP2_MASK                    (0x4U)
+#define ADC_FLAGS_THCMP2_SHIFT                   (2U)
+/*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP2(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
+#define ADC_FLAGS_THCMP3_MASK                    (0x8U)
+#define ADC_FLAGS_THCMP3_SHIFT                   (3U)
+/*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP3(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
+#define ADC_FLAGS_THCMP4_MASK                    (0x10U)
+#define ADC_FLAGS_THCMP4_SHIFT                   (4U)
+/*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP4(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
+#define ADC_FLAGS_THCMP5_MASK                    (0x20U)
+#define ADC_FLAGS_THCMP5_SHIFT                   (5U)
+/*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP5(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
+#define ADC_FLAGS_THCMP6_MASK                    (0x40U)
+#define ADC_FLAGS_THCMP6_SHIFT                   (6U)
+/*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP6(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
+#define ADC_FLAGS_THCMP7_MASK                    (0x80U)
+#define ADC_FLAGS_THCMP7_SHIFT                   (7U)
+/*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP7(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
+#define ADC_FLAGS_THCMP8_MASK                    (0x100U)
+#define ADC_FLAGS_THCMP8_SHIFT                   (8U)
+/*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP8(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
+#define ADC_FLAGS_THCMP9_MASK                    (0x200U)
+#define ADC_FLAGS_THCMP9_SHIFT                   (9U)
+/*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP9(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
+#define ADC_FLAGS_THCMP10_MASK                   (0x400U)
+#define ADC_FLAGS_THCMP10_SHIFT                  (10U)
+/*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP10(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
+#define ADC_FLAGS_THCMP11_MASK                   (0x800U)
+#define ADC_FLAGS_THCMP11_SHIFT                  (11U)
+/*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP11(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
+#define ADC_FLAGS_OVERRUN0_MASK                  (0x1000U)
+#define ADC_FLAGS_OVERRUN0_SHIFT                 (12U)
+/*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0
+ */
+#define ADC_FLAGS_OVERRUN0(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
+#define ADC_FLAGS_OVERRUN1_MASK                  (0x2000U)
+#define ADC_FLAGS_OVERRUN1_SHIFT                 (13U)
+/*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1
+ */
+#define ADC_FLAGS_OVERRUN1(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
+#define ADC_FLAGS_OVERRUN2_MASK                  (0x4000U)
+#define ADC_FLAGS_OVERRUN2_SHIFT                 (14U)
+/*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2
+ */
+#define ADC_FLAGS_OVERRUN2(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
+#define ADC_FLAGS_OVERRUN3_MASK                  (0x8000U)
+#define ADC_FLAGS_OVERRUN3_SHIFT                 (15U)
+/*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3
+ */
+#define ADC_FLAGS_OVERRUN3(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
+#define ADC_FLAGS_OVERRUN4_MASK                  (0x10000U)
+#define ADC_FLAGS_OVERRUN4_SHIFT                 (16U)
+/*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4
+ */
+#define ADC_FLAGS_OVERRUN4(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
+#define ADC_FLAGS_OVERRUN5_MASK                  (0x20000U)
+#define ADC_FLAGS_OVERRUN5_SHIFT                 (17U)
+/*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5
+ */
+#define ADC_FLAGS_OVERRUN5(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
+#define ADC_FLAGS_OVERRUN6_MASK                  (0x40000U)
+#define ADC_FLAGS_OVERRUN6_SHIFT                 (18U)
+/*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6
+ */
+#define ADC_FLAGS_OVERRUN6(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
+#define ADC_FLAGS_OVERRUN7_MASK                  (0x80000U)
+#define ADC_FLAGS_OVERRUN7_SHIFT                 (19U)
+/*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7
+ */
+#define ADC_FLAGS_OVERRUN7(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
+#define ADC_FLAGS_OVERRUN8_MASK                  (0x100000U)
+#define ADC_FLAGS_OVERRUN8_SHIFT                 (20U)
+/*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8
+ */
+#define ADC_FLAGS_OVERRUN8(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
+#define ADC_FLAGS_OVERRUN9_MASK                  (0x200000U)
+#define ADC_FLAGS_OVERRUN9_SHIFT                 (21U)
+/*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9
+ */
+#define ADC_FLAGS_OVERRUN9(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
+#define ADC_FLAGS_OVERRUN10_MASK                 (0x400000U)
+#define ADC_FLAGS_OVERRUN10_SHIFT                (22U)
+/*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10
+ */
+#define ADC_FLAGS_OVERRUN10(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
+#define ADC_FLAGS_OVERRUN11_MASK                 (0x800000U)
+#define ADC_FLAGS_OVERRUN11_SHIFT                (23U)
+/*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11
+ */
+#define ADC_FLAGS_OVERRUN11(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
+#define ADC_FLAGS_SEQA_OVR_MASK                  (0x1000000U)
+#define ADC_FLAGS_SEQA_OVR_SHIFT                 (24U)
+/*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register
+ */
+#define ADC_FLAGS_SEQA_OVR(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
+#define ADC_FLAGS_SEQB_OVR_MASK                  (0x2000000U)
+#define ADC_FLAGS_SEQB_OVR_SHIFT                 (25U)
+/*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register
+ */
+#define ADC_FLAGS_SEQB_OVR(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
+#define ADC_FLAGS_SEQA_INT_MASK                  (0x10000000U)
+#define ADC_FLAGS_SEQA_INT_SHIFT                 (28U)
+/*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0,
+ *    this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which
+ *    is set at the end of every ADC conversion performed as part of sequence A. It will be cleared
+ *    automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register
+ *    is 1, this flag will be set upon completion of an entire A sequence. In this case it must be
+ *    cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN
+ *    register.
+ */
+#define ADC_FLAGS_SEQA_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
+#define ADC_FLAGS_SEQB_INT_MASK                  (0x20000000U)
+#define ADC_FLAGS_SEQB_INT_SHIFT                 (29U)
+/*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0,
+ *    this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which
+ *    is set at the end of every ADC conversion performed as part of sequence B. It will be cleared
+ *    automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register
+ *    is 1, this flag will be set upon completion of an entire B sequence. In this case it must be
+ *    cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN
+ *    register.
+ */
+#define ADC_FLAGS_SEQB_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
+#define ADC_FLAGS_THCMP_INT_MASK                 (0x40000000U)
+#define ADC_FLAGS_THCMP_INT_SHIFT                (30U)
+/*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in
+ *    the lower bits of this register are set to 1 (due to an enabled out-of-range or
+ *    threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be
+ *    individually enabled in the INTEN register to cause this interrupt. This bit will be cleared
+ *    when all of the individual threshold flags are cleared via writing 1s to those bits.
+ */
+#define ADC_FLAGS_THCMP_INT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
+#define ADC_FLAGS_OVR_INT_MASK                   (0x80000000U)
+#define ADC_FLAGS_OVR_INT_SHIFT                  (31U)
+/*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data
+ *    registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers
+ *    is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this
+ *    interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all
+ *    of the individual overrun bits have been cleared via reading the corresponding data registers.
+ */
+#define ADC_FLAGS_OVR_INT(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
+/*! @} */
+
+/*! @name STARTUP - ADC Startup register. */
+/*! @{ */
+#define ADC_STARTUP_ADC_ENA_MASK                 (0x1U)
+#define ADC_STARTUP_ADC_ENA_SHIFT                (0U)
+/*! ADC_ENA - ADC Enable bit. This bit can only be set to a 1 by software. It is cleared
+ *    automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds
+ *    after the ADC is powered up (typically by altering a system-level ADC power control bit).
+ */
+#define ADC_STARTUP_ADC_ENA(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
+#define ADC_STARTUP_ADC_INIT_MASK                (0x2U)
+#define ADC_STARTUP_ADC_INIT_SHIFT               (1U)
+/*! ADC_INIT - ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine
+ *    will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not
+ *    calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is
+ *    required if a calibration is not performed. It will also reload the stored calibration value from
+ *    a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the
+ *    ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or
+ *    an ADC dummy conversion cycle is required. It should not be set during the same write that
+ *    sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically
+ *    when the 'dummy' conversion cycle completes.
+ */
+#define ADC_STARTUP_ADC_INIT(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
+/*! @} */
+
+/*! @name CALIB - ADC Calibration register. */
+/*! @{ */
+#define ADC_CALIB_CALIB_MASK                     (0x1U)
+#define ADC_CALIB_CALIB_SHIFT                    (0U)
+/*! CALIB - Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can
+ *    only be set to a '1' by software. It is cleared automatically when the calibration cycle
+ *    completes.
+ */
+#define ADC_CALIB_CALIB(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
+#define ADC_CALIB_CALREQD_MASK                   (0x2U)
+#define ADC_CALIB_CALREQD_SHIFT                  (1U)
+/*! CALREQD - Calibration required. This read-only bit indicates if calibration is required when
+ *    enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was
+ *    powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to
+ *    determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP
+ *    register) to launch the ADC initialization process which includes a 'dummy' conversion cycle.
+ *    Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks
+ *    required for calibration.
+ */
+#define ADC_CALIB_CALREQD(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
+#define ADC_CALIB_CALVALUE_MASK                  (0x1FCU)
+#define ADC_CALIB_CALVALUE_SHIFT                 (2U)
+/*! CALVALUE - Calibration Value. This read-only field displays the calibration value established
+ *    during last calibration cycle. This value is not typically of any use to the user.
+ */
+#define ADC_CALIB_CALVALUE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x400A0000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_SEQ_IRQS                             { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
+#define ADC_THCMP_IRQS                           { ADC0_THCMP_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ASYNC_SYSCON Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
+ * @{
+ */
+
+/** ASYNC_SYSCON - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t ASYNCPRESETCTRL;                   /**< Async peripheral reset control, offset: 0x0 */
+  __O  uint32_t ASYNCPRESETCTRLSET;                /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
+  __O  uint32_t ASYNCPRESETCTRLCLR;                /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ASYNCAPBCLKCTRL;                   /**< Async peripheral clock control, offset: 0x10 */
+  __O  uint32_t ASYNCAPBCLKCTRLSET;                /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
+  __O  uint32_t ASYNCAPBCLKCTRLCLR;                /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t ASYNCAPBCLKSELA;                   /**< Async APB clock source select A, offset: 0x20 */
+} ASYNC_SYSCON_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ASYNC_SYSCON Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
+ * @{
+ */
+
+/*! @name ASYNCPRESETCTRL - Async peripheral reset control */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
+/*! CTIMER3 - Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
+/*! CTIMER4 - Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
+/*! @} */
+
+/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
+/*! ARST_SET - Writing ones to this register sets the corresponding bit or bits in the
+ *    ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ *    ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
+/*! @} */
+
+/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
+/*! ARST_CLR - Writing ones to this register clears the corresponding bit or bits in the
+ *    ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ *    ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
+/*! CTIMER3 - Controls the clock for CTIMER3. 0 = Disable; 1 = Enable.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
+/*! CTIMER4 - Controls the clock for CTIMER4. 0 = Disable; 1 = Enable.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
+/*! ACLK_SET - Writing ones to this register sets the corresponding bit or bits in the
+ *    ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ *    ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
+/*! ACLK_CLR - Writing ones to this register clears the corresponding bit or bits in the
+ *    ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ *    ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK    (0x3U)
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT   (0U)
+/*! SEL - Clock source for asynchronous clock source selector A
+ *  0b00..Main clock (main_clk)
+ *  0b01..FRO 12 MHz (fro_12m)
+ *  0b10..Audio PLL clock.(AUDPLL_BYPASS)
+ *  0b11..fc6 fclk (fc6_fclk)
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x)      (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ASYNC_SYSCON_Register_Masks */
+
+
+/* ASYNC_SYSCON - Peripheral instance base addresses */
+/** Peripheral ASYNC_SYSCON base address */
+#define ASYNC_SYSCON_BASE                        (0x40040000u)
+/** Peripheral ASYNC_SYSCON base pointer */
+#define ASYNC_SYSCON                             ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
+/** Array initializer of ASYNC_SYSCON peripheral base addresses */
+#define ASYNC_SYSCON_BASE_ADDRS                  { ASYNC_SYSCON_BASE }
+/** Array initializer of ASYNC_SYSCON peripheral base pointers */
+#define ASYNC_SYSCON_BASE_PTRS                   { ASYNC_SYSCON }
+
+/*!
+ * @}
+ */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MODE;                              /**< CRC mode register, offset: 0x0 */
+  __IO uint32_t SEED;                              /**< CRC seed register, offset: 0x4 */
+  union {                                          /* offset: 0x8 */
+    __I  uint32_t SUM;                               /**< CRC checksum register, offset: 0x8 */
+    __O  uint32_t WR_DATA;                           /**< CRC data register, offset: 0x8 */
+  };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name MODE - CRC mode register */
+/*! @{ */
+#define CRC_MODE_CRC_POLY_MASK                   (0x3U)
+#define CRC_MODE_CRC_POLY_SHIFT                  (0U)
+/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
+ */
+#define CRC_MODE_CRC_POLY(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
+#define CRC_MODE_BIT_RVS_WR_MASK                 (0x4U)
+#define CRC_MODE_BIT_RVS_WR_SHIFT                (2U)
+/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
+ */
+#define CRC_MODE_BIT_RVS_WR(x)                   (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
+#define CRC_MODE_CMPL_WR_MASK                    (0x8U)
+#define CRC_MODE_CMPL_WR_SHIFT                   (3U)
+/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
+ */
+#define CRC_MODE_CMPL_WR(x)                      (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
+#define CRC_MODE_BIT_RVS_SUM_MASK                (0x10U)
+#define CRC_MODE_BIT_RVS_SUM_SHIFT               (4U)
+/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
+ */
+#define CRC_MODE_BIT_RVS_SUM(x)                  (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
+#define CRC_MODE_CMPL_SUM_MASK                   (0x20U)
+#define CRC_MODE_CMPL_SUM_SHIFT                  (5U)
+/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
+ */
+#define CRC_MODE_CMPL_SUM(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
+/*! @} */
+
+/*! @name SEED - CRC seed register */
+/*! @{ */
+#define CRC_SEED_CRC_SEED_MASK                   (0xFFFFFFFFU)
+#define CRC_SEED_CRC_SEED_SHIFT                  (0U)
+/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
+ *    selected bit order and 1's complement pre-processes. A write access to this register will
+ *    overrule the CRC calculation in progresses.
+ */
+#define CRC_SEED_CRC_SEED(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
+/*! @} */
+
+/*! @name SUM - CRC checksum register */
+/*! @{ */
+#define CRC_SUM_CRC_SUM_MASK                     (0xFFFFFFFFU)
+#define CRC_SUM_CRC_SUM_SHIFT                    (0U)
+/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
+ */
+#define CRC_SUM_CRC_SUM(x)                       (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
+/*! @} */
+
+/*! @name WR_DATA - CRC data register */
+/*! @{ */
+#define CRC_WR_DATA_CRC_WR_DATA_MASK             (0xFFFFFFFFU)
+#define CRC_WR_DATA_CRC_WR_DATA_SHIFT            (0U)
+/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
+ *    selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
+ *    accept back-to-back transactions.
+ */
+#define CRC_WR_DATA_CRC_WR_DATA(x)               (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC_ENGINE base address */
+#define CRC_ENGINE_BASE                          (0x40095000u)
+/** Peripheral CRC_ENGINE base pointer */
+#define CRC_ENGINE                               ((CRC_Type *)CRC_ENGINE_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC_ENGINE_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC_ENGINE }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CTIMER Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
+ * @{
+ */
+
+/** CTIMER - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t IR;                                /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
+  __IO uint32_t TCR;                               /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
+  __IO uint32_t TC;                                /**< Timer Counter, offset: 0x8 */
+  __IO uint32_t PR;                                /**< Prescale Register, offset: 0xC */
+  __IO uint32_t PC;                                /**< Prescale Counter, offset: 0x10 */
+  __IO uint32_t MCR;                               /**< Match Control Register, offset: 0x14 */
+  __IO uint32_t MR[4];                             /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
+  __IO uint32_t CCR;                               /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
+  __I  uint32_t CR[4];                             /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
+  __IO uint32_t EMR;                               /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
+       uint8_t RESERVED_0[48];
+  __IO uint32_t CTCR;                              /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
+  __IO uint32_t PWMC;                              /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
+  __IO uint32_t MSR[4];                            /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
+} CTIMER_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CTIMER Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
+ * @{
+ */
+
+/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+/*! @{ */
+#define CTIMER_IR_MR0INT_MASK                    (0x1U)
+#define CTIMER_IR_MR0INT_SHIFT                   (0U)
+/*! MR0INT - Interrupt flag for match channel 0.
+ */
+#define CTIMER_IR_MR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
+#define CTIMER_IR_MR1INT_MASK                    (0x2U)
+#define CTIMER_IR_MR1INT_SHIFT                   (1U)
+/*! MR1INT - Interrupt flag for match channel 1.
+ */
+#define CTIMER_IR_MR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
+#define CTIMER_IR_MR2INT_MASK                    (0x4U)
+#define CTIMER_IR_MR2INT_SHIFT                   (2U)
+/*! MR2INT - Interrupt flag for match channel 2.
+ */
+#define CTIMER_IR_MR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
+#define CTIMER_IR_MR3INT_MASK                    (0x8U)
+#define CTIMER_IR_MR3INT_SHIFT                   (3U)
+/*! MR3INT - Interrupt flag for match channel 3.
+ */
+#define CTIMER_IR_MR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
+#define CTIMER_IR_CR0INT_MASK                    (0x10U)
+#define CTIMER_IR_CR0INT_SHIFT                   (4U)
+/*! CR0INT - Interrupt flag for capture channel 0 event.
+ */
+#define CTIMER_IR_CR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
+#define CTIMER_IR_CR1INT_MASK                    (0x20U)
+#define CTIMER_IR_CR1INT_SHIFT                   (5U)
+/*! CR1INT - Interrupt flag for capture channel 1 event.
+ */
+#define CTIMER_IR_CR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
+#define CTIMER_IR_CR2INT_MASK                    (0x40U)
+#define CTIMER_IR_CR2INT_SHIFT                   (6U)
+/*! CR2INT - Interrupt flag for capture channel 2 event.
+ */
+#define CTIMER_IR_CR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
+#define CTIMER_IR_CR3INT_MASK                    (0x80U)
+#define CTIMER_IR_CR3INT_SHIFT                   (7U)
+/*! CR3INT - Interrupt flag for capture channel 3 event.
+ */
+#define CTIMER_IR_CR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
+/*! @} */
+
+/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+/*! @{ */
+#define CTIMER_TCR_CEN_MASK                      (0x1U)
+#define CTIMER_TCR_CEN_SHIFT                     (0U)
+/*! CEN - Counter enable.
+ *  0b0..Disabled.The counters are disabled.
+ *  0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
+ */
+#define CTIMER_TCR_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
+#define CTIMER_TCR_CRST_MASK                     (0x2U)
+#define CTIMER_TCR_CRST_SHIFT                    (1U)
+/*! CRST - Counter reset.
+ *  0b0..Disabled. Do nothing.
+ *  0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
+ *       the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
+ */
+#define CTIMER_TCR_CRST(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
+/*! @} */
+
+/*! @name TC - Timer Counter */
+/*! @{ */
+#define CTIMER_TC_TCVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_TC_TCVAL_SHIFT                    (0U)
+/*! TCVAL - Timer counter value.
+ */
+#define CTIMER_TC_TCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
+/*! @} */
+
+/*! @name PR - Prescale Register */
+/*! @{ */
+#define CTIMER_PR_PRVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_PR_PRVAL_SHIFT                    (0U)
+/*! PRVAL - Prescale counter value.
+ */
+#define CTIMER_PR_PRVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
+/*! @} */
+
+/*! @name PC - Prescale Counter */
+/*! @{ */
+#define CTIMER_PC_PCVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_PC_PCVAL_SHIFT                    (0U)
+/*! PCVAL - Prescale counter value.
+ */
+#define CTIMER_PC_PCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
+/*! @} */
+
+/*! @name MCR - Match Control Register */
+/*! @{ */
+#define CTIMER_MCR_MR0I_MASK                     (0x1U)
+#define CTIMER_MCR_MR0I_SHIFT                    (0U)
+/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR0I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
+#define CTIMER_MCR_MR0R_MASK                     (0x2U)
+#define CTIMER_MCR_MR0R_SHIFT                    (1U)
+/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it.
+ */
+#define CTIMER_MCR_MR0R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
+#define CTIMER_MCR_MR0S_MASK                     (0x4U)
+#define CTIMER_MCR_MR0S_SHIFT                    (2U)
+/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
+ */
+#define CTIMER_MCR_MR0S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
+#define CTIMER_MCR_MR1I_MASK                     (0x8U)
+#define CTIMER_MCR_MR1I_SHIFT                    (3U)
+/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR1I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
+#define CTIMER_MCR_MR1R_MASK                     (0x10U)
+#define CTIMER_MCR_MR1R_SHIFT                    (4U)
+/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it.
+ */
+#define CTIMER_MCR_MR1R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
+#define CTIMER_MCR_MR1S_MASK                     (0x20U)
+#define CTIMER_MCR_MR1S_SHIFT                    (5U)
+/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
+ */
+#define CTIMER_MCR_MR1S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
+#define CTIMER_MCR_MR2I_MASK                     (0x40U)
+#define CTIMER_MCR_MR2I_SHIFT                    (6U)
+/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR2I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
+#define CTIMER_MCR_MR2R_MASK                     (0x80U)
+#define CTIMER_MCR_MR2R_SHIFT                    (7U)
+/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it.
+ */
+#define CTIMER_MCR_MR2R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
+#define CTIMER_MCR_MR2S_MASK                     (0x100U)
+#define CTIMER_MCR_MR2S_SHIFT                    (8U)
+/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
+ */
+#define CTIMER_MCR_MR2S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
+#define CTIMER_MCR_MR3I_MASK                     (0x200U)
+#define CTIMER_MCR_MR3I_SHIFT                    (9U)
+/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR3I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
+#define CTIMER_MCR_MR3R_MASK                     (0x400U)
+#define CTIMER_MCR_MR3R_SHIFT                    (10U)
+/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it.
+ */
+#define CTIMER_MCR_MR3R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
+#define CTIMER_MCR_MR3S_MASK                     (0x800U)
+#define CTIMER_MCR_MR3S_SHIFT                    (11U)
+/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
+ */
+#define CTIMER_MCR_MR3S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
+#define CTIMER_MCR_MR0RL_MASK                    (0x1000000U)
+#define CTIMER_MCR_MR0RL_SHIFT                   (24U)
+/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
+ *    (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR0RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
+#define CTIMER_MCR_MR1RL_MASK                    (0x2000000U)
+#define CTIMER_MCR_MR1RL_SHIFT                   (25U)
+/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
+ *    (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR1RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
+#define CTIMER_MCR_MR2RL_MASK                    (0x4000000U)
+#define CTIMER_MCR_MR2RL_SHIFT                   (26U)
+/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
+ *    (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR2RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
+#define CTIMER_MCR_MR3RL_MASK                    (0x8000000U)
+#define CTIMER_MCR_MR3RL_SHIFT                   (27U)
+/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
+ *    (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR3RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
+/*! @} */
+
+/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+/*! @{ */
+#define CTIMER_MR_MATCH_MASK                     (0xFFFFFFFFU)
+#define CTIMER_MR_MATCH_SHIFT                    (0U)
+/*! MATCH - Timer counter match value.
+ */
+#define CTIMER_MR_MATCH(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
+/*! @} */
+
+/* The count of CTIMER_MR */
+#define CTIMER_MR_COUNT                          (4U)
+
+/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+/*! @{ */
+#define CTIMER_CCR_CAP0RE_MASK                   (0x1U)
+#define CTIMER_CCR_CAP0RE_SHIFT                  (0U)
+/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP0RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
+#define CTIMER_CCR_CAP0FE_MASK                   (0x2U)
+#define CTIMER_CCR_CAP0FE_SHIFT                  (1U)
+/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP0FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
+#define CTIMER_CCR_CAP0I_MASK                    (0x4U)
+#define CTIMER_CCR_CAP0I_SHIFT                   (2U)
+/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP0I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
+#define CTIMER_CCR_CAP1RE_MASK                   (0x8U)
+#define CTIMER_CCR_CAP1RE_SHIFT                  (3U)
+/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP1RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
+#define CTIMER_CCR_CAP1FE_MASK                   (0x10U)
+#define CTIMER_CCR_CAP1FE_SHIFT                  (4U)
+/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP1FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
+#define CTIMER_CCR_CAP1I_MASK                    (0x20U)
+#define CTIMER_CCR_CAP1I_SHIFT                   (5U)
+/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP1I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
+#define CTIMER_CCR_CAP2RE_MASK                   (0x40U)
+#define CTIMER_CCR_CAP2RE_SHIFT                  (6U)
+/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP2RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
+#define CTIMER_CCR_CAP2FE_MASK                   (0x80U)
+#define CTIMER_CCR_CAP2FE_SHIFT                  (7U)
+/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP2FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
+#define CTIMER_CCR_CAP2I_MASK                    (0x100U)
+#define CTIMER_CCR_CAP2I_SHIFT                   (8U)
+/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP2I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
+#define CTIMER_CCR_CAP3RE_MASK                   (0x200U)
+#define CTIMER_CCR_CAP3RE_SHIFT                  (9U)
+/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP3RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
+#define CTIMER_CCR_CAP3FE_MASK                   (0x400U)
+#define CTIMER_CCR_CAP3FE_SHIFT                  (10U)
+/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP3FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
+#define CTIMER_CCR_CAP3I_MASK                    (0x800U)
+#define CTIMER_CCR_CAP3I_SHIFT                   (11U)
+/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP3I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
+/*! @} */
+
+/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
+/*! @{ */
+#define CTIMER_CR_CAP_MASK                       (0xFFFFFFFFU)
+#define CTIMER_CR_CAP_SHIFT                      (0U)
+/*! CAP - Timer counter capture value.
+ */
+#define CTIMER_CR_CAP(x)                         (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
+/*! @} */
+
+/* The count of CTIMER_CR */
+#define CTIMER_CR_COUNT                          (4U)
+
+/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
+/*! @{ */
+#define CTIMER_EMR_EM0_MASK                      (0x1U)
+#define CTIMER_EMR_EM0_SHIFT                     (0U)
+/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
+ *    is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
+ *    go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
+ *    the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM0(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
+#define CTIMER_EMR_EM1_MASK                      (0x2U)
+#define CTIMER_EMR_EM1_SHIFT                     (1U)
+/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
+ *    is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
+ *    go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
+ *    the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM1(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
+#define CTIMER_EMR_EM2_MASK                      (0x4U)
+#define CTIMER_EMR_EM2_SHIFT                     (2U)
+/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
+ *    is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
+ *    go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
+ *    the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM2(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
+#define CTIMER_EMR_EM3_MASK                      (0x8U)
+#define CTIMER_EMR_EM3_SHIFT                     (3U)
+/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
+ *    is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
+ *    go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
+ *    if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM3(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
+#define CTIMER_EMR_EMC0_MASK                     (0x30U)
+#define CTIMER_EMR_EMC0_SHIFT                    (4U)
+/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC0(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
+#define CTIMER_EMR_EMC1_MASK                     (0xC0U)
+#define CTIMER_EMR_EMC1_SHIFT                    (6U)
+/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC1(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
+#define CTIMER_EMR_EMC2_MASK                     (0x300U)
+#define CTIMER_EMR_EMC2_SHIFT                    (8U)
+/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC2(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
+#define CTIMER_EMR_EMC3_MASK                     (0xC00U)
+#define CTIMER_EMR_EMC3_SHIFT                    (10U)
+/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC3(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
+/*! @} */
+
+/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+/*! @{ */
+#define CTIMER_CTCR_CTMODE_MASK                  (0x3U)
+#define CTIMER_CTCR_CTMODE_SHIFT                 (0U)
+/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
+ *    Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
+ *    is incremented when the Prescale Counter matches the Prescale Register.
+ *  0b00..Timer Mode. Incremented every rising APB bus clock edge.
+ *  0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
+ *  0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
+ *  0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
+ */
+#define CTIMER_CTCR_CTMODE(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
+#define CTIMER_CTCR_CINSEL_MASK                  (0xCU)
+#define CTIMER_CTCR_CINSEL_SHIFT                 (2U)
+/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
+ *    CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
+ *    in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
+ *    programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
+ *    same timer.
+ *  0b00..Channel 0. CAPn.0 for CTIMERn
+ *  0b01..Channel 1. CAPn.1 for CTIMERn
+ *  0b10..Channel 2. CAPn.2 for CTIMERn
+ *  0b11..Channel 3. CAPn.3 for CTIMERn
+ */
+#define CTIMER_CTCR_CINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
+#define CTIMER_CTCR_ENCC_MASK                    (0x10U)
+#define CTIMER_CTCR_ENCC_SHIFT                   (4U)
+/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
+ *    capture-edge event specified in bits 7:5 occurs.
+ */
+#define CTIMER_CTCR_ENCC(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
+#define CTIMER_CTCR_SELCC_MASK                   (0xE0U)
+#define CTIMER_CTCR_SELCC_SHIFT                  (5U)
+/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
+ *    timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
+ *    0x3 and 0x6 to 0x7 are reserved.
+ *  0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
+ *  0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
+ *  0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
+ *  0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
+ *  0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
+ *  0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
+ */
+#define CTIMER_CTCR_SELCC(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
+/*! @} */
+
+/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
+/*! @{ */
+#define CTIMER_PWMC_PWMEN0_MASK                  (0x1U)
+#define CTIMER_PWMC_PWMEN0_SHIFT                 (0U)
+/*! PWMEN0 - PWM mode enable for channel0.
+ *  0b0..Match. CTIMERn_MAT0 is controlled by EM0.
+ *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
+ */
+#define CTIMER_PWMC_PWMEN0(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
+#define CTIMER_PWMC_PWMEN1_MASK                  (0x2U)
+#define CTIMER_PWMC_PWMEN1_SHIFT                 (1U)
+/*! PWMEN1 - PWM mode enable for channel1.
+ *  0b0..Match. CTIMERn_MAT01 is controlled by EM1.
+ *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
+ */
+#define CTIMER_PWMC_PWMEN1(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
+#define CTIMER_PWMC_PWMEN2_MASK                  (0x4U)
+#define CTIMER_PWMC_PWMEN2_SHIFT                 (2U)
+/*! PWMEN2 - PWM mode enable for channel2.
+ *  0b0..Match. CTIMERn_MAT2 is controlled by EM2.
+ *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
+ */
+#define CTIMER_PWMC_PWMEN2(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
+#define CTIMER_PWMC_PWMEN3_MASK                  (0x8U)
+#define CTIMER_PWMC_PWMEN3_SHIFT                 (3U)
+/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
+ *  0b0..Match. CTIMERn_MAT3 is controlled by EM3.
+ *  0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
+ */
+#define CTIMER_PWMC_PWMEN3(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
+/*! @} */
+
+/*! @name MSR - Match Shadow Register */
+/*! @{ */
+#define CTIMER_MSR_SHADOWW_MASK                  (0xFFFFFFFFU)
+#define CTIMER_MSR_SHADOWW_SHIFT                 (0U)
+/*! SHADOWW - Timer counter match shadow value.
+ */
+#define CTIMER_MSR_SHADOWW(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)
+/*! @} */
+
+/* The count of CTIMER_MSR */
+#define CTIMER_MSR_COUNT                         (4U)
+
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Register_Masks */
+
+
+/* CTIMER - Peripheral instance base addresses */
+/** Peripheral CTIMER0 base address */
+#define CTIMER0_BASE                             (0x40008000u)
+/** Peripheral CTIMER0 base pointer */
+#define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
+/** Peripheral CTIMER1 base address */
+#define CTIMER1_BASE                             (0x40009000u)
+/** Peripheral CTIMER1 base pointer */
+#define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
+/** Peripheral CTIMER2 base address */
+#define CTIMER2_BASE                             (0x40028000u)
+/** Peripheral CTIMER2 base pointer */
+#define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
+/** Peripheral CTIMER3 base address */
+#define CTIMER3_BASE                             (0x40048000u)
+/** Peripheral CTIMER3 base pointer */
+#define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
+/** Peripheral CTIMER4 base address */
+#define CTIMER4_BASE                             (0x40049000u)
+/** Peripheral CTIMER4 base pointer */
+#define CTIMER4                                  ((CTIMER_Type *)CTIMER4_BASE)
+/** Array initializer of CTIMER peripheral base addresses */
+#define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
+/** Array initializer of CTIMER peripheral base pointers */
+#define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
+/** Interrupt vectors for the CTIMER peripheral type */
+#define CTIMER_IRQS                              { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< DMA control., offset: 0x0 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt status., offset: 0x4 */
+  __IO uint32_t SRAMBASE;                          /**< SRAM address of the channel configuration table., offset: 0x8 */
+       uint8_t RESERVED_0[20];
+  struct {                                         /* offset: 0x20, array step: 0x5C */
+    __IO uint32_t ENABLESET;                         /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
+         uint8_t RESERVED_0[4];
+    __O  uint32_t ENABLECLR;                         /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
+         uint8_t RESERVED_1[4];
+    __I  uint32_t ACTIVE;                            /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
+         uint8_t RESERVED_2[4];
+    __I  uint32_t BUSY;                              /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
+         uint8_t RESERVED_3[4];
+    __IO uint32_t ERRINT;                            /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
+         uint8_t RESERVED_4[4];
+    __IO uint32_t INTENSET;                          /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
+         uint8_t RESERVED_5[4];
+    __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
+         uint8_t RESERVED_6[4];
+    __IO uint32_t INTA;                              /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
+         uint8_t RESERVED_7[4];
+    __IO uint32_t INTB;                              /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
+         uint8_t RESERVED_8[4];
+    __O  uint32_t SETVALID;                          /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
+         uint8_t RESERVED_9[4];
+    __O  uint32_t SETTRIG;                           /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
+         uint8_t RESERVED_10[4];
+    __O  uint32_t ABORT;                             /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
+  } COMMON[1];
+       uint8_t RESERVED_1[900];
+  struct {                                         /* offset: 0x400, array step: 0x10 */
+    __IO uint32_t CFG;                               /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
+    __I  uint32_t CTLSTAT;                           /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
+    __IO uint32_t XFERCFG;                           /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
+         uint8_t RESERVED_0[4];
+  } CHANNEL[32];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name CTRL - DMA control. */
+/*! @{ */
+#define DMA_CTRL_ENABLE_MASK                     (0x1U)
+#define DMA_CTRL_ENABLE_SHIFT                    (0U)
+/*! ENABLE - DMA controller master enable.
+ *  0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
+ *       disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
+ *  0b1..Enabled. The DMA controller is enabled.
+ */
+#define DMA_CTRL_ENABLE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt status. */
+/*! @{ */
+#define DMA_INTSTAT_ACTIVEINT_MASK               (0x2U)
+#define DMA_INTSTAT_ACTIVEINT_SHIFT              (1U)
+/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
+ *  0b0..Not pending. No enabled interrupts are pending.
+ *  0b1..Pending. At least one enabled interrupt is pending.
+ */
+#define DMA_INTSTAT_ACTIVEINT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
+#define DMA_INTSTAT_ACTIVEERRINT_MASK            (0x4U)
+#define DMA_INTSTAT_ACTIVEERRINT_SHIFT           (2U)
+/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
+ *  0b0..Not pending. No error interrupts are pending.
+ *  0b1..Pending. At least one error interrupt is pending.
+ */
+#define DMA_INTSTAT_ACTIVEERRINT(x)              (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
+/*! @} */
+
+/*! @name SRAMBASE - SRAM address of the channel configuration table. */
+/*! @{ */
+#define DMA_SRAMBASE_OFFSET_MASK                 (0xFFFFFE00U)
+#define DMA_SRAMBASE_OFFSET_SHIFT                (9U)
+/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
+ *    table must begin on a 512 byte boundary.
+ */
+#define DMA_SRAMBASE_OFFSET(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
+/*! @} */
+
+/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ENABLESET_ENA_MASK            (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLESET_ENA_SHIFT           (0U)
+/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
+ *    number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENA(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ENABLESET */
+#define DMA_COMMON_ENABLESET_COUNT               (1U)
+
+/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ENABLECLR_CLR_MASK            (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLECLR_CLR_SHIFT           (0U)
+/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
+ *    the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
+ *    are reserved.
+ */
+#define DMA_COMMON_ENABLECLR_CLR(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ENABLECLR */
+#define DMA_COMMON_ENABLECLR_COUNT               (1U)
+
+/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ACTIVE_ACT_MASK               (0xFFFFFFFFU)
+#define DMA_COMMON_ACTIVE_ACT_SHIFT              (0U)
+/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
+ *    number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
+ */
+#define DMA_COMMON_ACTIVE_ACT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ACTIVE */
+#define DMA_COMMON_ACTIVE_COUNT                  (1U)
+
+/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_BUSY_BSY_MASK                 (0xFFFFFFFFU)
+#define DMA_COMMON_BUSY_BSY_SHIFT                (0U)
+/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
+ *    number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
+ */
+#define DMA_COMMON_BUSY_BSY(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_BUSY */
+#define DMA_COMMON_BUSY_COUNT                    (1U)
+
+/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ERRINT_ERR_MASK               (0xFFFFFFFFU)
+#define DMA_COMMON_ERRINT_ERR_SHIFT              (0U)
+/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
+ *    bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
+ *    not active. 1 = error interrupt is active.
+ */
+#define DMA_COMMON_ERRINT_ERR(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ERRINT */
+#define DMA_COMMON_ERRINT_COUNT                  (1U)
+
+/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTENSET_INTEN_MASK           (0xFFFFFFFFU)
+#define DMA_COMMON_INTENSET_INTEN_SHIFT          (0U)
+/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
+ *    number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
+ *    interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTENSET */
+#define DMA_COMMON_INTENSET_COUNT                (1U)
+
+/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTENCLR_CLR_MASK             (0xFFFFFFFFU)
+#define DMA_COMMON_INTENCLR_CLR_SHIFT            (0U)
+/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
+ *    corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
+ *    reserved.
+ */
+#define DMA_COMMON_INTENCLR_CLR(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTENCLR */
+#define DMA_COMMON_INTENCLR_COUNT                (1U)
+
+/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTA_IA_MASK                  (0xFFFFFFFFU)
+#define DMA_COMMON_INTA_IA_SHIFT                 (0U)
+/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
+ *    bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
+ *    interrupt A is not active. 1 = the DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_IA(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTA */
+#define DMA_COMMON_INTA_COUNT                    (1U)
+
+/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTB_IB_MASK                  (0xFFFFFFFFU)
+#define DMA_COMMON_INTB_IB_SHIFT                 (0U)
+/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
+ *    bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
+ *    interrupt B is not active. 1 = the DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_IB(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTB */
+#define DMA_COMMON_INTB_COUNT                    (1U)
+
+/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_SETVALID_SV_MASK              (0xFFFFFFFFU)
+#define DMA_COMMON_SETVALID_SV_SHIFT             (0U)
+/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
+ *    = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
+ *    VALIDPENDING control bit for DMA channel n
+ */
+#define DMA_COMMON_SETVALID_SV(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_SETVALID */
+#define DMA_COMMON_SETVALID_COUNT                (1U)
+
+/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_SETTRIG_TRIG_MASK             (0xFFFFFFFFU)
+#define DMA_COMMON_SETTRIG_TRIG_SHIFT            (0U)
+/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
+ *    of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
+ *    sets the TRIG bit for DMA channel n.
+ */
+#define DMA_COMMON_SETTRIG_TRIG(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_SETTRIG */
+#define DMA_COMMON_SETTRIG_COUNT                 (1U)
+
+/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ABORT_ABORTCTRL_MASK          (0xFFFFFFFFU)
+#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT         (0U)
+/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
+ *    1 = aborts DMA operations on channel n.
+ */
+#define DMA_COMMON_ABORT_ABORTCTRL(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ABORT */
+#define DMA_COMMON_ABORT_COUNT                   (1U)
+
+/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
+/*! @{ */
+#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK         (0x1U)
+#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT        (0U)
+/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
+ *    move, any peripheral DMA request associated with that channel can be disabled to prevent any
+ *    interaction between the peripheral and the DMA controller.
+ *  0b0..Disabled. Peripheral DMA requests are disabled.
+ *  0b1..Enabled. Peripheral DMA requests are enabled.
+ */
+#define DMA_CHANNEL_CFG_PERIPHREQEN(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
+#define DMA_CHANNEL_CFG_HWTRIGEN_MASK            (0x2U)
+#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT           (1U)
+/*! HWTRIGEN - Hardware Triggering Enable for this channel.
+ *  0b0..Disabled. Hardware triggering is not used.
+ *  0b1..Enabled. Use hardware triggering.
+ */
+#define DMA_CHANNEL_CFG_HWTRIGEN(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
+#define DMA_CHANNEL_CFG_TRIGPOL_MASK             (0x10U)
+#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT            (4U)
+/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
+ *  0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
+ *  0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
+ */
+#define DMA_CHANNEL_CFG_TRIGPOL(x)               (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
+#define DMA_CHANNEL_CFG_TRIGTYPE_MASK            (0x20U)
+#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT           (5U)
+/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
+ *  0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
+ *  0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
+ *       0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
+ *       trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
+ *       is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
+ *       current BURSTPOWER length are completed.
+ */
+#define DMA_CHANNEL_CFG_TRIGTYPE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
+#define DMA_CHANNEL_CFG_TRIGBURST_MASK           (0x40U)
+#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT          (6U)
+/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
+ *  0b0..Single transfer. Hardware trigger causes a single transfer.
+ *  0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
+ *       burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a
+ *       hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
+ *       complete.
+ */
+#define DMA_CHANNEL_CFG_TRIGBURST(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
+#define DMA_CHANNEL_CFG_BURSTPOWER_MASK          (0xF00U)
+#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT         (8U)
+/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
+ *    SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
+ *    When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
+ *    transfers are performed for each DMA trigger. This can be used, for example, with peripherals that
+ *    contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:
+ *    Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =
+ *    1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The
+ *    total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
+ *    multiple of the burst size.
+ */
+#define DMA_CHANNEL_CFG_BURSTPOWER(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK        (0x4000U)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT       (14U)
+/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
+ *    'wrapped', meaning that the source address range for each burst will be the same. As an example, this
+ *    could be used to read several sequential registers from a peripheral for each DMA burst,
+ *    reading the same registers again for each burst.
+ *  0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
+ *  0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
+ */
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK        (0x8000U)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT       (15U)
+/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
+ *    'wrapped', meaning that the destination address range for each burst will be the same. As an
+ *    example, this could be used to write several sequential registers to a peripheral for each DMA
+ *    burst, writing the same registers again for each burst.
+ *  0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
+ *  0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
+ */
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_CHPRIORITY_MASK          (0x70000U)
+#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT         (16U)
+/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority
+ *    levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
+ */
+#define DMA_CHANNEL_CFG_CHPRIORITY(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
+/*! @} */
+
+/* The count of DMA_CHANNEL_CFG */
+#define DMA_CHANNEL_CFG_COUNT                    (32U)
+
+/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
+/*! @{ */
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK    (0x1U)
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT   (0U)
+/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the
+ *    corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
+ *  0b0..No effect. No effect on DMA operation.
+ *  0b1..Valid pending.
+ */
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x)      (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
+#define DMA_CHANNEL_CTLSTAT_TRIG_MASK            (0x4U)
+#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT           (2U)
+/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is
+ *    cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
+ *  0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
+ *  0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
+ */
+#define DMA_CHANNEL_CTLSTAT_TRIG(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
+/*! @} */
+
+/* The count of DMA_CHANNEL_CTLSTAT */
+#define DMA_CHANNEL_CTLSTAT_COUNT                (32U)
+
+/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
+/*! @{ */
+#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK        (0x1U)
+#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT       (0U)
+/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor
+ *    is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
+ *  0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
+ *  0b1..Valid. The current channel descriptor is considered valid.
+ */
+#define DMA_CHANNEL_XFERCFG_CFGVALID(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
+#define DMA_CHANNEL_XFERCFG_RELOAD_MASK          (0x2U)
+#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT         (1U)
+/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current
+ *    descriptor is exhausted. Reloading allows ping-pong and linked transfers.
+ *  0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
+ *  0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.
+ */
+#define DMA_CHANNEL_XFERCFG_RELOAD(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK          (0x4U)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT         (2U)
+/*! SWTRIG - Software Trigger.
+ *  0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by
+ *       the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
+ *  0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not
+ *       be used with level triggering when TRIGBURST = 0.
+ */
+#define DMA_CHANNEL_XFERCFG_SWTRIG(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK         (0x8U)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT        (3U)
+/*! CLRTRIG - Clear Trigger.
+ *  0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
+ *  0b1..Cleared. The trigger is cleared when this descriptor is exhausted
+ */
+#define DMA_CHANNEL_XFERCFG_CLRTRIG(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
+#define DMA_CHANNEL_XFERCFG_SETINTA_MASK         (0x10U)
+#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT        (4U)
+/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between
+ *    interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
+ *    convention, interrupt A may be used when only one interrupt flag is needed.
+ *  0b0..No effect.
+ *  0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
+ */
+#define DMA_CHANNEL_XFERCFG_SETINTA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
+#define DMA_CHANNEL_XFERCFG_SETINTB_MASK         (0x20U)
+#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT        (5U)
+/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between
+ *    interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
+ *    convention, interrupt A may be used when only one interrupt flag is needed.
+ *  0b0..No effect.
+ *  0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
+ */
+#define DMA_CHANNEL_XFERCFG_SETINTB(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
+#define DMA_CHANNEL_XFERCFG_WIDTH_MASK           (0x300U)
+#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT          (8U)
+/*! WIDTH - Transfer width used for this DMA channel.
+ *  0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
+ *  0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
+ *  0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
+ *  0b11..Reserved. Reserved setting, do not use.
+ */
+#define DMA_CHANNEL_XFERCFG_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
+#define DMA_CHANNEL_XFERCFG_SRCINC_MASK          (0x3000U)
+#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT         (12U)
+/*! SRCINC - Determines whether the source address is incremented for each DMA transfer.
+ *  0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
+ *  0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is
+ *        the usual case when the source is memory.
+ *  0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
+ *  0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
+ */
+#define DMA_CHANNEL_XFERCFG_SRCINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
+#define DMA_CHANNEL_XFERCFG_DSTINC_MASK          (0xC000U)
+#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT         (14U)
+/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer.
+ *  0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when
+ *        the destination is a peripheral device.
+ *  0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer.
+ *        This is the usual case when the destination is memory.
+ *  0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
+ *  0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
+ */
+#define DMA_CHANNEL_XFERCFG_DSTINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK       (0x3FF0000U)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT      (16U)
+/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes
+ *    transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller
+ *    uses this bit field during transfer to count down. Hence, it cannot be used by software to read
+ *    back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1
+ *    transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of
+ *    1,024 transfers will be performed.
+ */
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
+/*! @} */
+
+/* The count of DMA_CHANNEL_XFERCFG */
+#define DMA_CHANNEL_XFERCFG_COUNT                (32U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA0 base address */
+#define DMA0_BASE                                (0x40082000u)
+/** Peripheral DMA0 base pointer */
+#define DMA0                                     ((DMA_Type *)DMA0_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA0_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_IRQS                                 { DMA0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMIC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
+ * @{
+ */
+
+/** DMIC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x100 */
+    __IO uint32_t OSR;                               /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */
+    __IO uint32_t DIVHFCLK;                          /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */
+    __IO uint32_t PREAC2FSCOEF;                      /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */
+    __IO uint32_t PREAC4FSCOEF;                      /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */
+    __IO uint32_t GAINSHIFT;                         /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */
+         uint8_t RESERVED_0[108];
+    __IO uint32_t FIFO_CTRL;                         /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */
+    __IO uint32_t FIFO_STATUS;                       /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */
+    __IO uint32_t FIFO_DATA;                         /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */
+    __IO uint32_t PHY_CTRL;                          /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */
+    __IO uint32_t DC_CTRL;                           /**< DC Control register 0, array offset: 0x90, array step: 0x100 */
+         uint8_t RESERVED_1[108];
+  } CHANNEL[2];
+       uint8_t RESERVED_0[3328];
+  __IO uint32_t CHANEN;                            /**< Channel Enable register, offset: 0xF00 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t IOCFG;                             /**< I/O Configuration register, offset: 0xF0C */
+  __IO uint32_t USE2FS;                            /**< Use 2FS register, offset: 0xF10 */
+       uint8_t RESERVED_2[108];
+  __IO uint32_t HWVADGAIN;                         /**< HWVAD input gain register, offset: 0xF80 */
+  __IO uint32_t HWVADHPFS;                         /**< HWVAD filter control register, offset: 0xF84 */
+  __IO uint32_t HWVADST10;                         /**< HWVAD control register, offset: 0xF88 */
+  __IO uint32_t HWVADRSTT;                         /**< HWVAD filter reset register, offset: 0xF8C */
+  __IO uint32_t HWVADTHGN;                         /**< HWVAD noise estimator gain register, offset: 0xF90 */
+  __IO uint32_t HWVADTHGS;                         /**< HWVAD signal estimator gain register, offset: 0xF94 */
+  __I  uint32_t HWVADLOWZ;                         /**< HWVAD noise envelope estimator register, offset: 0xF98 */
+       uint8_t RESERVED_3[96];
+  __I  uint32_t ID;                                /**< Module Identification register, offset: 0xFFC */
+} DMIC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMIC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Register_Masks DMIC Register Masks
+ * @{
+ */
+
+/*! @name CHANNEL_OSR - Oversample Rate register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_OSR_OSR_MASK                (0xFFU)
+#define DMIC_CHANNEL_OSR_OSR_SHIFT               (0U)
+/*! OSR - Selects the oversample rate for the related input channel.
+ */
+#define DMIC_CHANNEL_OSR_OSR(x)                  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_OSR */
+#define DMIC_CHANNEL_OSR_COUNT                   (2U)
+
+/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK        (0xFU)
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT       (0U)
+/*! PDMDIV - PDM clock divider value. 0 = divide by 1 1 = divide by 2 2 = divide by 3 3 = divide by
+ *    4 4 = divide by 6 5 = divide by 8 6 = divide by 12 7 = divide by 16 8 = divide by 24 9 =
+ *    divide by 32 10 = divide by 48 11 = divide by 64 12 = divide by 96 13 = divide by 128 others =
+ *    reserved.
+ */
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_DIVHFCLK */
+#define DMIC_CHANNEL_DIVHFCLK_COUNT              (2U)
+
+/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */
+/*! @{ */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK      (0x3U)
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT     (0U)
+/*! COMP - Pre-emphasis filer coefficient for 2 FS mode. 0 = Compensation = 0 1 = Compensation = 16
+ *    2 = Compensation = 15 3 = Compensation = 13
+ */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT          (2U)
+
+/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */
+/*! @{ */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK      (0x3U)
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT     (0U)
+/*! COMP - Pre-emphasis filer coefficient for 4 FS mode. 0 = Compensation = 0 1 = Compensation = 16
+ *    2 = Compensation = 15 3 = Compensation = 13
+ */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT          (2U)
+
+/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */
+/*! @{ */
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK         (0x3FU)
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT        (0U)
+/*! GAIN - Gain control, as a positive or negative (two's complement) number of bits to shift.
+ */
+#define DMIC_CHANNEL_GAINSHIFT_GAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_GAINSHIFT */
+#define DMIC_CHANNEL_GAINSHIFT_COUNT             (2U)
+
+/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK       (0x1U)
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT      (0U)
+/*! ENABLE - FIFO enable.
+ *  0b0..FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being
+ *       streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a
+ *       period when the data was not needed.
+ *  0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK       (0x2U)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT      (1U)
+/*! RESETN - FIFO reset.
+ *  0b0..Reset the FIFO.
+ *  0b1..Normal operation
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK        (0x4U)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT       (2U)
+/*! INTEN - Interrupt enable.
+ *  0b0..FIFO level interrupts are not enabled.
+ *  0b1..FIFO level interrupts are enabled.
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK        (0x8U)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT       (3U)
+/*! DMAEN - DMA enable
+ *  0b0..DMA requests are not enabled.
+ *  0b1..DMA requests based on FIFO level are enabled.
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK      (0x1F0000U)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT     (16U)
+/*! TRIGLVL - FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If
+ *    enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then
+ *    return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 =
+ *    trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has
+ *    received two entries. 15 = trigger when the FIFO has received 16 entries (has become full).
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_FIFO_CTRL */
+#define DMIC_CHANNEL_FIFO_CTRL_COUNT             (2U)
+
+/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK        (0x1U)
+#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT       (0U)
+/*! INT - Interrupt flag. Asserted when FIFO data reaches the level specified in the FIFOCTRL
+ *    register. Writing a one to this bit clears the flag. Remark: note that the bus clock to the DMIC
+ *    subsystem must be running in order for an interrupt to occur.
+ */
+#define DMIC_CHANNEL_FIFO_STATUS_INT(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK    (0x2U)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT   (1U)
+/*! OVERRUN - Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one
+ *    to this bit clears the flag. This flag does not cause an interrupt.
+ */
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x)      (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK   (0x4U)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT  (2U)
+/*! UNDERRUN - Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag.
+ */
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x)     (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_FIFO_STATUS */
+#define DMIC_CHANNEL_FIFO_STATUS_COUNT           (2U)
+
+/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK         (0xFFFFFFU)
+#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT        (0U)
+/*! DATA - Data from the top of the input filter FIFO.
+ */
+#define DMIC_CHANNEL_FIFO_DATA_DATA(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_FIFO_DATA */
+#define DMIC_CHANNEL_FIFO_DATA_COUNT             (2U)
+
+/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK      (0x1U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT     (0U)
+/*! PHY_FALL - Capture PDM_DATA
+ *  0b0..Capture PDM_DATA on the rising edge of PDM_CLK.
+ *  0b1..Capture PDM_DATA on the falling edge of PDM_CLK.
+ */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK      (0x2U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT     (1U)
+/*! PHY_HALF - Half rate sampling
+ *  0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
+ *  0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.
+ */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_PHY_CTRL */
+#define DMIC_CHANNEL_PHY_CTRL_COUNT              (2U)
+
+/*! @name CHANNEL_DC_CTRL - DC Control register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK         (0x3U)
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT        (0U)
+/*! DCPOLE - DC block filter
+ *  0b00..Flat response, no filter.
+ *  0b01..155 Hz.
+ *  0b10..78 Hz.
+ *  0b11..39 Hz
+ */
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK         (0xF0U)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT        (4U)
+/*! DCGAIN - Fine gain adjustment in the form of a number of bits to downshift.
+ */
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
+/*! SATURATEAT16BIT - Selects 16-bit saturation.
+ *  0b0..Results roll over if out range and do not saturate.
+ *  0b1..If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
+ */
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x)  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_DC_CTRL */
+#define DMIC_CHANNEL_DC_CTRL_COUNT               (2U)
+
+/*! @name CHANEN - Channel Enable register */
+/*! @{ */
+#define DMIC_CHANEN_EN_CH0_MASK                  (0x1U)
+#define DMIC_CHANEN_EN_CH0_SHIFT                 (0U)
+/*! EN_CH0 - Enable channel 0. When 1, PDM channel 0 is enabled.
+ */
+#define DMIC_CHANEN_EN_CH0(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
+#define DMIC_CHANEN_EN_CH1_MASK                  (0x2U)
+#define DMIC_CHANEN_EN_CH1_SHIFT                 (1U)
+/*! EN_CH1 - Enable channel 1. When 1, PDM channel 1 is enabled.
+ */
+#define DMIC_CHANEN_EN_CH1(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
+/*! @} */
+
+/*! @name IOCFG - I/O Configuration register */
+/*! @{ */
+#define DMIC_IOCFG_CLK_BYPASS0_MASK              (0x1U)
+#define DMIC_IOCFG_CLK_BYPASS0_SHIFT             (0U)
+/*! CLK_BYPASS0 - Bypass CLK0. When 1, PDM_DATA1 becomes the clock for PDM channel 0. This provides
+ *    for the possibility of an external codec taking over the PDM bus.
+ */
+#define DMIC_IOCFG_CLK_BYPASS0(x)                (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)
+#define DMIC_IOCFG_CLK_BYPASS1_MASK              (0x2U)
+#define DMIC_IOCFG_CLK_BYPASS1_SHIFT             (1U)
+/*! CLK_BYPASS1 - Bypass CLK1. When 1, PDM_DATA1 becomes the clock for PDM channel 1. This provides
+ *    for the possibility of an external codec taking over the PDM bus.
+ */
+#define DMIC_IOCFG_CLK_BYPASS1(x)                (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)
+#define DMIC_IOCFG_STEREO_DATA0_MASK             (0x4U)
+#define DMIC_IOCFG_STEREO_DATA0_SHIFT            (2U)
+/*! STEREO_DATA0 - Stereo PDM select. When 1, PDM_DATA0 is routed to both PDM channels in a
+ *    configuration that supports a single stereo digital microphone.
+ */
+#define DMIC_IOCFG_STEREO_DATA0(x)               (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)
+/*! @} */
+
+/*! @name USE2FS - Use 2FS register */
+/*! @{ */
+#define DMIC_USE2FS_USE2FS_MASK                  (0x1U)
+#define DMIC_USE2FS_USE2FS_SHIFT                 (0U)
+/*! USE2FS - Use 2FS register
+ *  0b0..Use 1FS output for PCM data.
+ *  0b1..Use 2FS output for PCM data.
+ */
+#define DMIC_USE2FS_USE2FS(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
+/*! @} */
+
+/*! @name HWVADGAIN - HWVAD input gain register */
+/*! @{ */
+#define DMIC_HWVADGAIN_INPUTGAIN_MASK            (0xFU)
+#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT           (0U)
+/*! INPUTGAIN - Shift value for input bits 0x00 -10 bits 0x01 -8 bits 0x02 -6 bits 0x03 -4 bits 0x04
+ *    -2 bits 0x05 0 bits (default) 0x06 +2 bits 0x07 +4 bits 0x08 +6 bits 0x09 +8 bits 0x0A +10
+ *    bits 0x0B +12 bits 0x0C +14 bits 0x0D to 0x0F Reserved.
+ */
+#define DMIC_HWVADGAIN_INPUTGAIN(x)              (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
+/*! @} */
+
+/*! @name HWVADHPFS - HWVAD filter control register */
+/*! @{ */
+#define DMIC_HWVADHPFS_HPFS_MASK                 (0x3U)
+#define DMIC_HWVADHPFS_HPFS_SHIFT                (0U)
+/*! HPFS - High pass filter
+ *  0b00..First filter by-pass.
+ *  0b01..High pass filter with -3dB cut-off at 1750Hz.
+ *  0b10..High pass filter with -3dB cut-off at 215Hz.
+ *  0b11..Reserved.
+ */
+#define DMIC_HWVADHPFS_HPFS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
+/*! @} */
+
+/*! @name HWVADST10 - HWVAD control register */
+/*! @{ */
+#define DMIC_HWVADST10_ST10_MASK                 (0x1U)
+#define DMIC_HWVADST10_ST10_SHIFT                (0U)
+/*! ST10 - Stage 0
+ *  0b0..Normal operation, waiting for HWVAD trigger event (stage 0).
+ *  0b1..Reset internal interrupt flag by writing a '1' pulse.
+ */
+#define DMIC_HWVADST10_ST10(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
+/*! @} */
+
+/*! @name HWVADRSTT - HWVAD filter reset register */
+/*! @{ */
+#define DMIC_HWVADRSTT_RSTT_MASK                 (0x1U)
+#define DMIC_HWVADRSTT_RSTT_SHIFT                (0U)
+/*! RSTT - Writing a 1 resets all filter values
+ */
+#define DMIC_HWVADRSTT_RSTT(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)
+/*! @} */
+
+/*! @name HWVADTHGN - HWVAD noise estimator gain register */
+/*! @{ */
+#define DMIC_HWVADTHGN_THGN_MASK                 (0xFU)
+#define DMIC_HWVADTHGN_THGN_SHIFT                (0U)
+/*! THGN - Gain value for the noise estimator. Values 0 to 14. 0 corresponds to a gain of 1.
+ */
+#define DMIC_HWVADTHGN_THGN(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
+/*! @} */
+
+/*! @name HWVADTHGS - HWVAD signal estimator gain register */
+/*! @{ */
+#define DMIC_HWVADTHGS_THGS_MASK                 (0xFU)
+#define DMIC_HWVADTHGS_THGS_SHIFT                (0U)
+/*! THGS - Gain value for the signal estimator. Values 0 to 14. 0 corresponds to a gain of 1.
+ */
+#define DMIC_HWVADTHGS_THGS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
+/*! @} */
+
+/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */
+/*! @{ */
+#define DMIC_HWVADLOWZ_LOWZ_MASK                 (0xFFFFU)
+#define DMIC_HWVADLOWZ_LOWZ_SHIFT                (0U)
+/*! LOWZ - Noise envelope estimator value.
+ */
+#define DMIC_HWVADLOWZ_LOWZ(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
+/*! @} */
+
+/*! @name ID - Module Identification register */
+/*! @{ */
+#define DMIC_ID_ID_MASK                          (0xFFFFFFFFU)
+#define DMIC_ID_ID_SHIFT                         (0U)
+/*! ID - Indicates module ID and the number of channels in this DMIC interface.
+ */
+#define DMIC_ID_ID(x)                            (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group DMIC_Register_Masks */
+
+
+/* DMIC - Peripheral instance base addresses */
+/** Peripheral DMIC0 base address */
+#define DMIC0_BASE                               (0x40090000u)
+/** Peripheral DMIC0 base pointer */
+#define DMIC0                                    ((DMIC_Type *)DMIC0_BASE)
+/** Array initializer of DMIC peripheral base addresses */
+#define DMIC_BASE_ADDRS                          { DMIC0_BASE }
+/** Array initializer of DMIC peripheral base pointers */
+#define DMIC_BASE_PTRS                           { DMIC0 }
+/** Interrupt vectors for the DMIC peripheral type */
+#define DMIC_IRQS                                { DMIC0_IRQn }
+#define DMIC_HWVAD_IRQS                          { HWVAD0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMIC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer
+ * @{
+ */
+
+/** EMC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Controls operation of the memory controller, offset: 0x0 */
+  __I  uint32_t STATUS;                            /**< Provides EMC status information, offset: 0x4 */
+  __IO uint32_t CONFIG;                            /**< Configures operation of the memory controller, offset: 0x8 */
+       uint8_t RESERVED_0[20];
+  __IO uint32_t DYNAMICCONTROL;                    /**< Controls dynamic memory operation, offset: 0x20 */
+  __IO uint32_t DYNAMICREFRESH;                    /**< Configures dynamic memory refresh, offset: 0x24 */
+  __IO uint32_t DYNAMICREADCONFIG;                 /**< Configures dynamic memory read strategy, offset: 0x28 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t DYNAMICRP;                         /**< Precharge command period, offset: 0x30 */
+  __IO uint32_t DYNAMICRAS;                        /**< Active to precharge command period, offset: 0x34 */
+  __IO uint32_t DYNAMICSREX;                       /**< Self-refresh exit time, offset: 0x38 */
+  __IO uint32_t DYNAMICAPR;                        /**< Last-data-out to active command time, offset: 0x3C */
+  __IO uint32_t DYNAMICDAL;                        /**< Data-in to active command time, offset: 0x40 */
+  __IO uint32_t DYNAMICWR;                         /**< Write recovery time, offset: 0x44 */
+  __IO uint32_t DYNAMICRC;                         /**< Selects the active to active command period, offset: 0x48 */
+  __IO uint32_t DYNAMICRFC;                        /**< Selects the auto-refresh period, offset: 0x4C */
+  __IO uint32_t DYNAMICXSR;                        /**< Time for exit self-refresh to active command, offset: 0x50 */
+  __IO uint32_t DYNAMICRRD;                        /**< Latency for active bank A to active bank B, offset: 0x54 */
+  __IO uint32_t DYNAMICMRD;                        /**< Time for load mode register to active command, offset: 0x58 */
+       uint8_t RESERVED_2[36];
+  __IO uint32_t STATICEXTENDEDWAIT;                /**< Time for long static memory read and write transfers, offset: 0x80 */
+       uint8_t RESERVED_3[124];
+  struct {                                         /* offset: 0x100, array step: 0x20 */
+    __IO uint32_t DYNAMICCONFIG;                     /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */
+    __IO uint32_t DYNAMICRASCAS;                     /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */
+         uint8_t RESERVED_0[24];
+  } DYNAMIC[4];
+       uint8_t RESERVED_4[128];
+  struct {                                         /* offset: 0x200, array step: 0x20 */
+    __IO uint32_t STATICCONFIG;                      /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */
+    __IO uint32_t STATICWAITWEN;                     /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */
+    __IO uint32_t STATICWAITOEN;                     /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */
+    __IO uint32_t STATICWAITRD;                      /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */
+    __IO uint32_t STATICWAITPAGE;                    /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */
+    __IO uint32_t STATICWAITWR;                      /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */
+    __IO uint32_t STATICWAITTURN;                    /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */
+         uint8_t RESERVED_0[4];
+  } STATIC[4];
+} EMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMC_Register_Masks EMC Register Masks
+ * @{
+ */
+
+/*! @name CONTROL - Controls operation of the memory controller */
+/*! @{ */
+#define EMC_CONTROL_E_MASK                       (0x1U)
+#define EMC_CONTROL_E_SHIFT                      (0U)
+/*! E - EMC Enable.
+ */
+#define EMC_CONTROL_E(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK)
+#define EMC_CONTROL_M_MASK                       (0x2U)
+#define EMC_CONTROL_M_SHIFT                      (1U)
+/*! M - Address mirror.
+ */
+#define EMC_CONTROL_M(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK)
+#define EMC_CONTROL_L_MASK                       (0x4U)
+#define EMC_CONTROL_L_SHIFT                      (2U)
+/*! L - Low-power mode.
+ */
+#define EMC_CONTROL_L(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK)
+/*! @} */
+
+/*! @name STATUS - Provides EMC status information */
+/*! @{ */
+#define EMC_STATUS_B_MASK                        (0x1U)
+#define EMC_STATUS_B_SHIFT                       (0U)
+/*! B - Busy.
+ */
+#define EMC_STATUS_B(x)                          (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK)
+#define EMC_STATUS_S_MASK                        (0x2U)
+#define EMC_STATUS_S_SHIFT                       (1U)
+/*! S - Write buffer status.
+ */
+#define EMC_STATUS_S(x)                          (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK)
+#define EMC_STATUS_SA_MASK                       (0x4U)
+#define EMC_STATUS_SA_SHIFT                      (2U)
+/*! SA - Self-refresh acknowledge.
+ */
+#define EMC_STATUS_SA(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK)
+/*! @} */
+
+/*! @name CONFIG - Configures operation of the memory controller */
+/*! @{ */
+#define EMC_CONFIG_EM_MASK                       (0x1U)
+#define EMC_CONFIG_EM_SHIFT                      (0U)
+/*! EM - Endian mode.
+ */
+#define EMC_CONFIG_EM(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK)
+#define EMC_CONFIG_CLKR_MASK                     (0x100U)
+#define EMC_CONFIG_CLKR_SHIFT                    (8U)
+/*! CLKR - This bit must contain 0 for proper operation of the EMC.
+ */
+#define EMC_CONFIG_CLKR(x)                       (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK)
+/*! @} */
+
+/*! @name DYNAMICCONTROL - Controls dynamic memory operation */
+/*! @{ */
+#define EMC_DYNAMICCONTROL_CE_MASK               (0x1U)
+#define EMC_DYNAMICCONTROL_CE_SHIFT              (0U)
+/*! CE - Dynamic memory clock enable.
+ */
+#define EMC_DYNAMICCONTROL_CE(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK)
+#define EMC_DYNAMICCONTROL_CS_MASK               (0x2U)
+#define EMC_DYNAMICCONTROL_CS_SHIFT              (1U)
+/*! CS - Dynamic memory clock control.
+ */
+#define EMC_DYNAMICCONTROL_CS(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK)
+#define EMC_DYNAMICCONTROL_SR_MASK               (0x4U)
+#define EMC_DYNAMICCONTROL_SR_SHIFT              (2U)
+/*! SR - Self-refresh request, EMCSREFREQ.
+ */
+#define EMC_DYNAMICCONTROL_SR(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK)
+#define EMC_DYNAMICCONTROL_MMC_MASK              (0x20U)
+#define EMC_DYNAMICCONTROL_MMC_SHIFT             (5U)
+/*! MMC - Memory clock control.
+ */
+#define EMC_DYNAMICCONTROL_MMC(x)                (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK)
+#define EMC_DYNAMICCONTROL_I_MASK                (0x180U)
+#define EMC_DYNAMICCONTROL_I_SHIFT               (7U)
+/*! I - SDRAM initialization.
+ */
+#define EMC_DYNAMICCONTROL_I(x)                  (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK)
+/*! @} */
+
+/*! @name DYNAMICREFRESH - Configures dynamic memory refresh */
+/*! @{ */
+#define EMC_DYNAMICREFRESH_REFRESH_MASK          (0x7FFU)
+#define EMC_DYNAMICREFRESH_REFRESH_SHIFT         (0U)
+/*! REFRESH - Refresh timer.
+ */
+#define EMC_DYNAMICREFRESH_REFRESH(x)            (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK)
+/*! @} */
+
+/*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */
+/*! @{ */
+#define EMC_DYNAMICREADCONFIG_RD_MASK            (0x3U)
+#define EMC_DYNAMICREADCONFIG_RD_SHIFT           (0U)
+/*! RD - Read data strategy.
+ */
+#define EMC_DYNAMICREADCONFIG_RD(x)              (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK)
+/*! @} */
+
+/*! @name DYNAMICRP - Precharge command period */
+/*! @{ */
+#define EMC_DYNAMICRP_TRP_MASK                   (0xFU)
+#define EMC_DYNAMICRP_TRP_SHIFT                  (0U)
+/*! TRP - Precharge command period.
+ */
+#define EMC_DYNAMICRP_TRP(x)                     (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK)
+/*! @} */
+
+/*! @name DYNAMICRAS - Active to precharge command period */
+/*! @{ */
+#define EMC_DYNAMICRAS_TRAS_MASK                 (0xFU)
+#define EMC_DYNAMICRAS_TRAS_SHIFT                (0U)
+/*! TRAS - Active to precharge command period.
+ */
+#define EMC_DYNAMICRAS_TRAS(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK)
+/*! @} */
+
+/*! @name DYNAMICSREX - Self-refresh exit time */
+/*! @{ */
+#define EMC_DYNAMICSREX_TSREX_MASK               (0xFU)
+#define EMC_DYNAMICSREX_TSREX_SHIFT              (0U)
+/*! TSREX - Self-refresh exit time.
+ */
+#define EMC_DYNAMICSREX_TSREX(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK)
+/*! @} */
+
+/*! @name DYNAMICAPR - Last-data-out to active command time */
+/*! @{ */
+#define EMC_DYNAMICAPR_TAPR_MASK                 (0xFU)
+#define EMC_DYNAMICAPR_TAPR_SHIFT                (0U)
+/*! TAPR - Last-data-out to active command time.
+ */
+#define EMC_DYNAMICAPR_TAPR(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK)
+/*! @} */
+
+/*! @name DYNAMICDAL - Data-in to active command time */
+/*! @{ */
+#define EMC_DYNAMICDAL_TDAL_MASK                 (0xFU)
+#define EMC_DYNAMICDAL_TDAL_SHIFT                (0U)
+/*! TDAL - Data-in to active command.
+ */
+#define EMC_DYNAMICDAL_TDAL(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK)
+/*! @} */
+
+/*! @name DYNAMICWR - Write recovery time */
+/*! @{ */
+#define EMC_DYNAMICWR_TWR_MASK                   (0xFU)
+#define EMC_DYNAMICWR_TWR_SHIFT                  (0U)
+/*! TWR - Write recovery time.
+ */
+#define EMC_DYNAMICWR_TWR(x)                     (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK)
+/*! @} */
+
+/*! @name DYNAMICRC - Selects the active to active command period */
+/*! @{ */
+#define EMC_DYNAMICRC_TRC_MASK                   (0x1FU)
+#define EMC_DYNAMICRC_TRC_SHIFT                  (0U)
+/*! TRC - Active to active command period.
+ */
+#define EMC_DYNAMICRC_TRC(x)                     (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK)
+/*! @} */
+
+/*! @name DYNAMICRFC - Selects the auto-refresh period */
+/*! @{ */
+#define EMC_DYNAMICRFC_TRFC_MASK                 (0x1FU)
+#define EMC_DYNAMICRFC_TRFC_SHIFT                (0U)
+/*! TRFC - Auto-refresh period and auto-refresh to active command period.
+ */
+#define EMC_DYNAMICRFC_TRFC(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK)
+/*! @} */
+
+/*! @name DYNAMICXSR - Time for exit self-refresh to active command */
+/*! @{ */
+#define EMC_DYNAMICXSR_TXSR_MASK                 (0x1FU)
+#define EMC_DYNAMICXSR_TXSR_SHIFT                (0U)
+/*! TXSR - Exit self-refresh to active command time.
+ */
+#define EMC_DYNAMICXSR_TXSR(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK)
+/*! @} */
+
+/*! @name DYNAMICRRD - Latency for active bank A to active bank B */
+/*! @{ */
+#define EMC_DYNAMICRRD_TRRD_MASK                 (0xFU)
+#define EMC_DYNAMICRRD_TRRD_SHIFT                (0U)
+/*! TRRD - Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles.
+ */
+#define EMC_DYNAMICRRD_TRRD(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK)
+/*! @} */
+
+/*! @name DYNAMICMRD - Time for load mode register to active command */
+/*! @{ */
+#define EMC_DYNAMICMRD_TMRD_MASK                 (0xFU)
+#define EMC_DYNAMICMRD_TMRD_SHIFT                (0U)
+/*! TMRD - Load mode register to active command time.
+ */
+#define EMC_DYNAMICMRD_TMRD(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK)
+/*! @} */
+
+/*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */
+/*! @{ */
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU)
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U)
+/*! EXTENDEDWAIT - Extended wait time out.
+ */
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x)   (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK)
+/*! @} */
+
+/*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */
+/*! @{ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK        (0x18U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT       (3U)
+/*! MD - Memory device.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD(x)          (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK       (0x1F80U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT      (7U)
+/*! AM0 - See Table 933.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK       (0x4000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT      (14U)
+/*! AM1 - See Table 933.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK         (0x80000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT        (19U)
+/*! B - Buffer enable.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_B(x)           (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK         (0x100000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT        (20U)
+/*! P - Write protect.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_P(x)           (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK)
+/*! @} */
+
+/* The count of EMC_DYNAMIC_DYNAMICCONFIG */
+#define EMC_DYNAMIC_DYNAMICCONFIG_COUNT          (4U)
+
+/*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */
+/*! @{ */
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK       (0x3U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT      (0U)
+/*! RAS - RAS latency (active to read/write delay).
+ */
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK)
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK       (0x300U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT      (8U)
+/*! CAS - CAS latency.
+ */
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK)
+/*! @} */
+
+/* The count of EMC_DYNAMIC_DYNAMICRASCAS */
+#define EMC_DYNAMIC_DYNAMICRASCAS_COUNT          (4U)
+
+/*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */
+/*! @{ */
+#define EMC_STATIC_STATICCONFIG_MW_MASK          (0x3U)
+#define EMC_STATIC_STATICCONFIG_MW_SHIFT         (0U)
+/*! MW - Memory width.
+ */
+#define EMC_STATIC_STATICCONFIG_MW(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK)
+#define EMC_STATIC_STATICCONFIG_PM_MASK          (0x8U)
+#define EMC_STATIC_STATICCONFIG_PM_SHIFT         (3U)
+/*! PM - Page mode.
+ */
+#define EMC_STATIC_STATICCONFIG_PM(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK)
+#define EMC_STATIC_STATICCONFIG_PC_MASK          (0x40U)
+#define EMC_STATIC_STATICCONFIG_PC_SHIFT         (6U)
+/*! PC - Chip select polarity.
+ */
+#define EMC_STATIC_STATICCONFIG_PC(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK)
+#define EMC_STATIC_STATICCONFIG_PB_MASK          (0x80U)
+#define EMC_STATIC_STATICCONFIG_PB_SHIFT         (7U)
+/*! PB - Byte lane state.
+ */
+#define EMC_STATIC_STATICCONFIG_PB(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK)
+#define EMC_STATIC_STATICCONFIG_EW_MASK          (0x100U)
+#define EMC_STATIC_STATICCONFIG_EW_SHIFT         (8U)
+/*! EW - Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write
+ *    transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.
+ */
+#define EMC_STATIC_STATICCONFIG_EW(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK)
+#define EMC_STATIC_STATICCONFIG_B_MASK           (0x80000U)
+#define EMC_STATIC_STATICCONFIG_B_SHIFT          (19U)
+/*! B - Buffer enable [2].
+ */
+#define EMC_STATIC_STATICCONFIG_B(x)             (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK)
+#define EMC_STATIC_STATICCONFIG_P_MASK           (0x100000U)
+#define EMC_STATIC_STATICCONFIG_P_SHIFT          (20U)
+/*! P - Write protect.
+ */
+#define EMC_STATIC_STATICCONFIG_P(x)             (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICCONFIG */
+#define EMC_STATIC_STATICCONFIG_COUNT            (4U)
+
+/*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */
+/*! @{ */
+#define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK    (0xFU)
+#define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT   (0U)
+/*! WAITWEN - Wait write enable.
+ */
+#define EMC_STATIC_STATICWAITWEN_WAITWEN(x)      (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITWEN */
+#define EMC_STATIC_STATICWAITWEN_COUNT           (4U)
+
+/*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */
+/*! @{ */
+#define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK    (0xFU)
+#define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT   (0U)
+/*! WAITOEN - Wait output enable.
+ */
+#define EMC_STATIC_STATICWAITOEN_WAITOEN(x)      (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITOEN */
+#define EMC_STATIC_STATICWAITOEN_COUNT           (4U)
+
+/*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */
+/*! @{ */
+#define EMC_STATIC_STATICWAITRD_WAITRD_MASK      (0x1FU)
+#define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT     (0U)
+/*! WAITRD - .
+ */
+#define EMC_STATIC_STATICWAITRD_WAITRD(x)        (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITRD */
+#define EMC_STATIC_STATICWAITRD_COUNT            (4U)
+
+/*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */
+/*! @{ */
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK  (0x1FU)
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U)
+/*! WAITPAGE - Asynchronous page mode read after the first read wait states.
+ */
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x)    (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITPAGE */
+#define EMC_STATIC_STATICWAITPAGE_COUNT          (4U)
+
+/*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */
+/*! @{ */
+#define EMC_STATIC_STATICWAITWR_WAITWR_MASK      (0x1FU)
+#define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT     (0U)
+/*! WAITWR - Write wait states.
+ */
+#define EMC_STATIC_STATICWAITWR_WAITWR(x)        (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITWR */
+#define EMC_STATIC_STATICWAITWR_COUNT            (4U)
+
+/*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */
+/*! @{ */
+#define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK  (0xFU)
+#define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U)
+/*! WAITTURN - Bus turn-around cycles.
+ */
+#define EMC_STATIC_STATICWAITTURN_WAITTURN(x)    (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITTURN */
+#define EMC_STATIC_STATICWAITTURN_COUNT          (4U)
+
+
+/*!
+ * @}
+ */ /* end of group EMC_Register_Masks */
+
+
+/* EMC - Peripheral instance base addresses */
+/** Peripheral EMC base address */
+#define EMC_BASE                                 (0x40081000u)
+/** Peripheral EMC base pointer */
+#define EMC                                      ((EMC_Type *)EMC_BASE)
+/** Array initializer of EMC peripheral base addresses */
+#define EMC_BASE_ADDRS                           { EMC_BASE }
+/** Array initializer of EMC peripheral base pointers */
+#define EMC_BASE_PTRS                            { EMC }
+
+/*!
+ * @}
+ */ /* end of group EMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FLEXCOMM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXCOMM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[4088];
+  __IO uint32_t PSELID;                            /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
+  __I  uint32_t PID;                               /**< Peripheral identification register., offset: 0xFFC */
+} FLEXCOMM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FLEXCOMM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
+ * @{
+ */
+
+/*! @name PSELID - Peripheral Select and Flexcomm ID register. */
+/*! @{ */
+#define FLEXCOMM_PSELID_PERSEL_MASK              (0x7U)
+#define FLEXCOMM_PSELID_PERSEL_SHIFT             (0U)
+/*! PERSEL - Peripheral Select. This field is writable by software.
+ *  0b000..No peripheral selected.
+ *  0b001..USART function selected.
+ *  0b010..SPI function selected.
+ *  0b011..I2C function selected.
+ *  0b100..I2S transmit function selected.
+ *  0b101..I2S receive function selected.
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define FLEXCOMM_PSELID_PERSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
+#define FLEXCOMM_PSELID_LOCK_MASK                (0x8U)
+#define FLEXCOMM_PSELID_LOCK_SHIFT               (3U)
+/*! LOCK - Lock the peripheral select. This field is writable by software.
+ *  0b0..Peripheral select can be changed by software.
+ *  0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset.
+ */
+#define FLEXCOMM_PSELID_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
+#define FLEXCOMM_PSELID_USARTPRESENT_MASK        (0x10U)
+#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT       (4U)
+/*! USARTPRESENT - USART present indicator. This field is Read-only.
+ *  0b0..This Flexcomm does not include the USART function.
+ *  0b1..This Flexcomm includes the USART function.
+ */
+#define FLEXCOMM_PSELID_USARTPRESENT(x)          (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
+#define FLEXCOMM_PSELID_SPIPRESENT_MASK          (0x20U)
+#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT         (5U)
+/*! SPIPRESENT - SPI present indicator. This field is Read-only.
+ *  0b0..This Flexcomm does not include the SPI function.
+ *  0b1..This Flexcomm includes the SPI function.
+ */
+#define FLEXCOMM_PSELID_SPIPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
+#define FLEXCOMM_PSELID_I2CPRESENT_MASK          (0x40U)
+#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT         (6U)
+/*! I2CPRESENT - I2C present indicator. This field is Read-only.
+ *  0b0..This Flexcomm does not include the I2C function.
+ *  0b1..This Flexcomm includes the I2C function.
+ */
+#define FLEXCOMM_PSELID_I2CPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
+#define FLEXCOMM_PSELID_I2SPRESENT_MASK          (0x80U)
+#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT         (7U)
+/*! I2SPRESENT - I 2S present indicator. This field is Read-only.
+ *  0b0..This Flexcomm does not include the I2S function.
+ *  0b1..This Flexcomm includes the I2S function.
+ */
+#define FLEXCOMM_PSELID_I2SPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
+#define FLEXCOMM_PSELID_ID_MASK                  (0xFFFFF000U)
+#define FLEXCOMM_PSELID_ID_SHIFT                 (12U)
+/*! ID - Flexcomm ID.
+ */
+#define FLEXCOMM_PSELID_ID(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
+/*! @} */
+
+/*! @name PID - Peripheral identification register. */
+/*! @{ */
+#define FLEXCOMM_PID_Minor_Rev_MASK              (0xF00U)
+#define FLEXCOMM_PID_Minor_Rev_SHIFT             (8U)
+/*! Minor_Rev - Minor revision of module implementation.
+ */
+#define FLEXCOMM_PID_Minor_Rev(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)
+#define FLEXCOMM_PID_Major_Rev_MASK              (0xF000U)
+#define FLEXCOMM_PID_Major_Rev_SHIFT             (12U)
+/*! Major_Rev - Major revision of module implementation.
+ */
+#define FLEXCOMM_PID_Major_Rev(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)
+#define FLEXCOMM_PID_ID_MASK                     (0xFFFF0000U)
+#define FLEXCOMM_PID_ID_SHIFT                    (16U)
+/*! ID - Module identifier for the selected function.
+ */
+#define FLEXCOMM_PID_ID(x)                       (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FLEXCOMM_Register_Masks */
+
+
+/* FLEXCOMM - Peripheral instance base addresses */
+/** Peripheral FLEXCOMM0 base address */
+#define FLEXCOMM0_BASE                           (0x40086000u)
+/** Peripheral FLEXCOMM0 base pointer */
+#define FLEXCOMM0                                ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
+/** Peripheral FLEXCOMM1 base address */
+#define FLEXCOMM1_BASE                           (0x40087000u)
+/** Peripheral FLEXCOMM1 base pointer */
+#define FLEXCOMM1                                ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
+/** Peripheral FLEXCOMM2 base address */
+#define FLEXCOMM2_BASE                           (0x40088000u)
+/** Peripheral FLEXCOMM2 base pointer */
+#define FLEXCOMM2                                ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
+/** Peripheral FLEXCOMM3 base address */
+#define FLEXCOMM3_BASE                           (0x40089000u)
+/** Peripheral FLEXCOMM3 base pointer */
+#define FLEXCOMM3                                ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
+/** Peripheral FLEXCOMM4 base address */
+#define FLEXCOMM4_BASE                           (0x4008A000u)
+/** Peripheral FLEXCOMM4 base pointer */
+#define FLEXCOMM4                                ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
+/** Peripheral FLEXCOMM5 base address */
+#define FLEXCOMM5_BASE                           (0x40096000u)
+/** Peripheral FLEXCOMM5 base pointer */
+#define FLEXCOMM5                                ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
+/** Peripheral FLEXCOMM6 base address */
+#define FLEXCOMM6_BASE                           (0x40097000u)
+/** Peripheral FLEXCOMM6 base pointer */
+#define FLEXCOMM6                                ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
+/** Peripheral FLEXCOMM7 base address */
+#define FLEXCOMM7_BASE                           (0x40098000u)
+/** Peripheral FLEXCOMM7 base pointer */
+#define FLEXCOMM7                                ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
+/** Peripheral FLEXCOMM8 base address */
+#define FLEXCOMM8_BASE                           (0x40099000u)
+/** Peripheral FLEXCOMM8 base pointer */
+#define FLEXCOMM8                                ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
+/** Peripheral FLEXCOMM9 base address */
+#define FLEXCOMM9_BASE                           (0x4009A000u)
+/** Peripheral FLEXCOMM9 base pointer */
+#define FLEXCOMM9                                ((FLEXCOMM_Type *)FLEXCOMM9_BASE)
+/** Peripheral FLEXCOMM10 base address */
+#define FLEXCOMM10_BASE                          (0x4009F000u)
+/** Peripheral FLEXCOMM10 base pointer */
+#define FLEXCOMM10                               ((FLEXCOMM_Type *)FLEXCOMM10_BASE)
+/** Array initializer of FLEXCOMM peripheral base addresses */
+#define FLEXCOMM_BASE_ADDRS                      { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE, FLEXCOMM10_BASE }
+/** Array initializer of FLEXCOMM peripheral base pointers */
+#define FLEXCOMM_BASE_PTRS                       { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9, FLEXCOMM10 }
+/** Interrupt vectors for the FLEXCOMM peripheral type */
+#define FLEXCOMM_IRQS                            { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn, FLEXCOMM10_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FLEXCOMM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GINT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer
+ * @{
+ */
+
+/** GINT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< GPIO grouped interrupt control register, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  __IO uint32_t PORT_POL[2];                       /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_1[24];
+  __IO uint32_t PORT_ENA[2];                       /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */
+} GINT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GINT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GINT_Register_Masks GINT Register Masks
+ * @{
+ */
+
+/*! @name CTRL - GPIO grouped interrupt control register */
+/*! @{ */
+#define GINT_CTRL_INT_MASK                       (0x1U)
+#define GINT_CTRL_INT_SHIFT                      (0U)
+/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.
+ *  0b0..No request. No interrupt request is pending.
+ *  0b1..Request active. Interrupt request is active.
+ */
+#define GINT_CTRL_INT(x)                         (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)
+#define GINT_CTRL_COMB_MASK                      (0x2U)
+#define GINT_CTRL_COMB_SHIFT                     (1U)
+/*! COMB - Combine enabled inputs for group interrupt
+ *  0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).
+ *  0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).
+ */
+#define GINT_CTRL_COMB(x)                        (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)
+#define GINT_CTRL_TRIG_MASK                      (0x4U)
+#define GINT_CTRL_TRIG_SHIFT                     (2U)
+/*! TRIG - Group interrupt trigger
+ *  0b0..Edge-triggered.
+ *  0b1..Level-triggered.
+ */
+#define GINT_CTRL_TRIG(x)                        (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)
+/*! @} */
+
+/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */
+/*! @{ */
+#define GINT_PORT_POL_POL_MASK                   (0xFFFFFFFFU)
+#define GINT_PORT_POL_POL_SHIFT                  (0U)
+/*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n
+ *    of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to
+ *    the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin
+ *    contributes to the group interrupt.
+ */
+#define GINT_PORT_POL_POL(x)                     (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)
+/*! @} */
+
+/* The count of GINT_PORT_POL */
+#define GINT_PORT_POL_COUNT                      (2U)
+
+/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */
+/*! @{ */
+#define GINT_PORT_ENA_ENA_MASK                   (0xFFFFFFFFU)
+#define GINT_PORT_ENA_ENA_SHIFT                  (0U)
+/*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the
+ *    port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is
+ *    enabled and contributes to the grouped interrupt.
+ */
+#define GINT_PORT_ENA_ENA(x)                     (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)
+/*! @} */
+
+/* The count of GINT_PORT_ENA */
+#define GINT_PORT_ENA_COUNT                      (2U)
+
+
+/*!
+ * @}
+ */ /* end of group GINT_Register_Masks */
+
+
+/* GINT - Peripheral instance base addresses */
+/** Peripheral GINT0 base address */
+#define GINT0_BASE                               (0x40002000u)
+/** Peripheral GINT0 base pointer */
+#define GINT0                                    ((GINT_Type *)GINT0_BASE)
+/** Peripheral GINT1 base address */
+#define GINT1_BASE                               (0x40003000u)
+/** Peripheral GINT1 base pointer */
+#define GINT1                                    ((GINT_Type *)GINT1_BASE)
+/** Array initializer of GINT peripheral base addresses */
+#define GINT_BASE_ADDRS                          { GINT0_BASE, GINT1_BASE }
+/** Array initializer of GINT peripheral base pointers */
+#define GINT_BASE_PTRS                           { GINT0, GINT1 }
+/** Interrupt vectors for the GINT peripheral type */
+#define GINT_IRQS                                { GINT0_IRQn, GINT1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group GINT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t B[6][32];                           /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
+       uint8_t RESERVED_0[3904];
+  __IO uint32_t W[6][32];                          /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
+       uint8_t RESERVED_1[3328];
+  __IO uint32_t DIR[6];                            /**< Direction registers, array offset: 0x2000, array step: 0x4 */
+       uint8_t RESERVED_2[104];
+  __IO uint32_t MASK[6];                           /**< Mask register, array offset: 0x2080, array step: 0x4 */
+       uint8_t RESERVED_3[104];
+  __IO uint32_t PIN[6];                            /**< Port pin register, array offset: 0x2100, array step: 0x4 */
+       uint8_t RESERVED_4[104];
+  __IO uint32_t MPIN[6];                           /**< Masked port register, array offset: 0x2180, array step: 0x4 */
+       uint8_t RESERVED_5[104];
+  __IO uint32_t SET[6];                            /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
+       uint8_t RESERVED_6[104];
+  __O  uint32_t CLR[6];                            /**< Clear port, array offset: 0x2280, array step: 0x4 */
+       uint8_t RESERVED_7[104];
+  __O  uint32_t NOT[6];                            /**< Toggle port, array offset: 0x2300, array step: 0x4 */
+       uint8_t RESERVED_8[104];
+  __O  uint32_t DIRSET[6];                         /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
+       uint8_t RESERVED_9[104];
+  __O  uint32_t DIRCLR[6];                         /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
+       uint8_t RESERVED_10[104];
+  __O  uint32_t DIRNOT[6];                         /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
+/*! @{ */
+#define GPIO_B_PBYTE_MASK                        (0x1U)
+#define GPIO_B_PBYTE_SHIFT                       (0U)
+/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function,
+ *    except that pins configured as analog I/O always read as 0. One register for each port pin.
+ *    Supported pins depends on the specific device and package. Write: loads the pin's output bit.
+ *    One register for each port pin. Supported pins depends on the specific device and package.
+ */
+#define GPIO_B_PBYTE(x)                          (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
+/*! @} */
+
+/* The count of GPIO_B */
+#define GPIO_B_COUNT                             (6U)
+
+/* The count of GPIO_B */
+#define GPIO_B_COUNT2                            (32U)
+
+/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
+/*! @{ */
+#define GPIO_W_PWORD_MASK                        (0xFFFFFFFFU)
+#define GPIO_W_PWORD_SHIFT                       (0U)
+/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is
+ *    HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be
+ *    read. Writing any value other than 0 will set the output bit. One register for each port pin.
+ *    Supported pins depends on the specific device and package.
+ */
+#define GPIO_W_PWORD(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
+/*! @} */
+
+/* The count of GPIO_W */
+#define GPIO_W_COUNT                             (6U)
+
+/* The count of GPIO_W */
+#define GPIO_W_COUNT2                            (32U)
+
+/*! @name DIR - Direction registers */
+/*! @{ */
+#define GPIO_DIR_DIRP_MASK                       (0xFFFFFFFFU)
+#define GPIO_DIR_DIRP_SHIFT                      (0U)
+/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
+ *    pins depends on the specific device and package. 0 = input. 1 = output.
+ */
+#define GPIO_DIR_DIRP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
+/*! @} */
+
+/* The count of GPIO_DIR */
+#define GPIO_DIR_COUNT                           (6U)
+
+/*! @name MASK - Mask register */
+/*! @{ */
+#define GPIO_MASK_MASKP_MASK                     (0xFFFFFFFFU)
+#define GPIO_MASK_MASKP_SHIFT                    (0U)
+/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 =
+ *    PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 =
+ *    Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit
+ *    not affected.
+ */
+#define GPIO_MASK_MASKP(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
+/*! @} */
+
+/* The count of GPIO_MASK */
+#define GPIO_MASK_COUNT                          (6U)
+
+/*! @name PIN - Port pin register */
+/*! @{ */
+#define GPIO_PIN_PORT_MASK                       (0xFFFFFFFFU)
+#define GPIO_PIN_PORT_SHIFT                      (0U)
+/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
+ *    pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit.
+ *    1 = Read: pin is high; write: set output bit.
+ */
+#define GPIO_PIN_PORT(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
+/*! @} */
+
+/* The count of GPIO_PIN */
+#define GPIO_PIN_COUNT                           (6U)
+
+/*! @name MPIN - Masked port register */
+/*! @{ */
+#define GPIO_MPIN_MPORTP_MASK                    (0xFFFFFFFFU)
+#define GPIO_MPIN_MPORTP_SHIFT                   (0U)
+/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
+ *    the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK
+ *    register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1
+ *    = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit
+ *    if the corresponding bit in the MASK register is 0.
+ */
+#define GPIO_MPIN_MPORTP(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
+/*! @} */
+
+/* The count of GPIO_MPIN */
+#define GPIO_MPIN_COUNT                          (6U)
+
+/*! @name SET - Write: Set register for port Read: output bits for port */
+/*! @{ */
+#define GPIO_SET_SETP_MASK                       (0xFFFFFFFFU)
+#define GPIO_SET_SETP_SHIFT                      (0U)
+/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
+ *    the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output
+ *    bit; write: set output bit.
+ */
+#define GPIO_SET_SETP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
+/*! @} */
+
+/* The count of GPIO_SET */
+#define GPIO_SET_COUNT                           (6U)
+
+/*! @name CLR - Clear port */
+/*! @{ */
+#define GPIO_CLR_CLRP_MASK                       (0xFFFFFFFFU)
+#define GPIO_CLR_CLRP_SHIFT                      (0U)
+/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
+ *    specific device and package. 0 = No operation. 1 = Clear output bit.
+ */
+#define GPIO_CLR_CLRP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
+/*! @} */
+
+/* The count of GPIO_CLR */
+#define GPIO_CLR_COUNT                           (6U)
+
+/*! @name NOT - Toggle port */
+/*! @{ */
+#define GPIO_NOT_NOTP_MASK                       (0xFFFFFFFFU)
+#define GPIO_NOT_NOTP_SHIFT                      (0U)
+/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
+ *    specific device and package. 0 = no operation. 1 = Toggle output bit.
+ */
+#define GPIO_NOT_NOTP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
+/*! @} */
+
+/* The count of GPIO_NOT */
+#define GPIO_NOT_COUNT                           (6U)
+
+/*! @name DIRSET - Set pin direction bits for port */
+/*! @{ */
+#define GPIO_DIRSET_DIRSETP_MASK                 (0x1FFFFFFFU)
+#define GPIO_DIRSET_DIRSETP_SHIFT                (0U)
+/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
+ *    the specific device and package. 0 = No operation. 1 = Set direction bit.
+ */
+#define GPIO_DIRSET_DIRSETP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
+/*! @} */
+
+/* The count of GPIO_DIRSET */
+#define GPIO_DIRSET_COUNT                        (6U)
+
+/*! @name DIRCLR - Clear pin direction bits for port */
+/*! @{ */
+#define GPIO_DIRCLR_DIRCLRP_MASK                 (0x1FFFFFFFU)
+#define GPIO_DIRCLR_DIRCLRP_SHIFT                (0U)
+/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
+ *    the specific device and package. 0 = No operation. 1 = Clear direction bit.
+ */
+#define GPIO_DIRCLR_DIRCLRP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
+/*! @} */
+
+/* The count of GPIO_DIRCLR */
+#define GPIO_DIRCLR_COUNT                        (6U)
+
+/*! @name DIRNOT - Toggle pin direction bits for port */
+/*! @{ */
+#define GPIO_DIRNOT_DIRNOTP_MASK                 (0x1FFFFFFFU)
+#define GPIO_DIRNOT_DIRNOTP_SHIFT                (0U)
+/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends
+ *    on the specific device and package. 0 = no operation. 1 = Toggle direction bit.
+ */
+#define GPIO_DIRNOT_DIRNOTP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
+/*! @} */
+
+/* The count of GPIO_DIRNOT */
+#define GPIO_DIRNOT_COUNT                        (6U)
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIO base address */
+#define GPIO_BASE                                (0x4008C000u)
+/** Peripheral GPIO base pointer */
+#define GPIO                                     ((GPIO_Type *)GPIO_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { GPIO_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { GPIO }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[2048];
+  __IO uint32_t CFG;                               /**< Configuration for shared functions., offset: 0x800 */
+  __IO uint32_t STAT;                              /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */
+  __IO uint32_t INTENSET;                          /**< Interrupt Enable Set and read register., offset: 0x808 */
+  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear register., offset: 0x80C */
+  __IO uint32_t TIMEOUT;                           /**< Time-out value register., offset: 0x810 */
+  __IO uint32_t CLKDIV;                            /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t MSTCTL;                            /**< Master control register., offset: 0x820 */
+  __IO uint32_t MSTTIME;                           /**< Master timing configuration., offset: 0x824 */
+  __IO uint32_t MSTDAT;                            /**< Combined Master receiver and transmitter data register., offset: 0x828 */
+       uint8_t RESERVED_2[20];
+  __IO uint32_t SLVCTL;                            /**< Slave control register., offset: 0x840 */
+  __IO uint32_t SLVDAT;                            /**< Combined Slave receiver and transmitter data register., offset: 0x844 */
+  __IO uint32_t SLVADR[4];                         /**< Slave address register., array offset: 0x848, array step: 0x4 */
+  __IO uint32_t SLVQUAL0;                          /**< Slave Qualification for address 0., offset: 0x858 */
+       uint8_t RESERVED_3[36];
+  __I  uint32_t MONRXDAT;                          /**< Monitor receiver data register., offset: 0x880 */
+       uint8_t RESERVED_4[1912];
+  __I  uint32_t ID;                                /**< Peripheral identification register., offset: 0xFFC */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/*! @name CFG - Configuration for shared functions. */
+/*! @{ */
+#define I2C_CFG_MSTEN_MASK                       (0x1U)
+#define I2C_CFG_MSTEN_SHIFT                      (0U)
+/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not
+ *    changed, but the Master function is internally reset.
+ *  0b0..Disabled. The I2C Master function is disabled.
+ *  0b1..Enabled. The I2C Master function is enabled.
+ */
+#define I2C_CFG_MSTEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
+#define I2C_CFG_SLVEN_MASK                       (0x2U)
+#define I2C_CFG_SLVEN_SHIFT                      (1U)
+/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not
+ *    changed, but the Slave function is internally reset.
+ *  0b0..Disabled. The I2C slave function is disabled.
+ *  0b1..Enabled. The I2C slave function is enabled.
+ */
+#define I2C_CFG_SLVEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
+#define I2C_CFG_MONEN_MASK                       (0x4U)
+#define I2C_CFG_MONEN_SHIFT                      (2U)
+/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not
+ *    changed, but the Monitor function is internally reset.
+ *  0b0..Disabled. The I2C Monitor function is disabled.
+ *  0b1..Enabled. The I2C Monitor function is enabled.
+ */
+#define I2C_CFG_MONEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
+#define I2C_CFG_TIMEOUTEN_MASK                   (0x8U)
+#define I2C_CFG_TIMEOUTEN_SHIFT                  (3U)
+/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
+ *  0b0..Disabled. Time-out function is disabled.
+ *  0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause
+ *       interrupts if they are enabled. Typically, only one time-out will be used in a system.
+ */
+#define I2C_CFG_TIMEOUTEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
+#define I2C_CFG_MONCLKSTR_MASK                   (0x10U)
+#define I2C_CFG_MONCLKSTR_SHIFT                  (4U)
+/*! MONCLKSTR - Monitor function Clock Stretching.
+ *  0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able
+ *       to read data provided by the Monitor function before it is overwritten. This mode may be used when
+ *       non-invasive monitoring is critical.
+ *  0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can
+ *       read all incoming data supplied by the Monitor function.
+ */
+#define I2C_CFG_MONCLKSTR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
+#define I2C_CFG_HSCAPABLE_MASK                   (0x20U)
+#define I2C_CFG_HSCAPABLE_SHIFT                  (5U)
+/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive
+ *    and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies
+ *    to all functions: Master, Slave, and Monitor.
+ *  0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the
+ *       extent that the pin electronics support these modes. Any changes that need to be made to the pin controls,
+ *       such as changing the drive strength or filtering, must be made by software via the IOCON register associated
+ *       with each I2C pin,
+ *  0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support
+ *       High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more
+ *       information.
+ */
+#define I2C_CFG_HSCAPABLE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
+/*! @} */
+
+/*! @name STAT - Status register for Master, Slave, and Monitor functions. */
+/*! @{ */
+#define I2C_STAT_MSTPENDING_MASK                 (0x1U)
+#define I2C_STAT_MSTPENDING_SHIFT                (0U)
+/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on
+ *    the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what
+ *    type of software service if any the master expects. This flag will cause an interrupt when set
+ *    if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling
+ *    an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle
+ *    state, and no communication is needed, mask this interrupt.
+ *  0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
+ *  0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the
+ *       idle state, it is waiting to receive or transmit data or the NACK bit.
+ */
+#define I2C_STAT_MSTPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
+#define I2C_STAT_MSTSTATE_MASK                   (0xEU)
+#define I2C_STAT_MSTSTATE_SHIFT                  (1U)
+/*! MSTSTATE - Master State code. The master state code reflects the master state when the
+ *    MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field
+ *    indicates a specific required service for the Master function. All other values are reserved. See
+ *    Table 400 for details of state values and appropriate responses.
+ *  0b000..Idle. The Master function is available to be used for a new transaction.
+ *  0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
+ *  0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
+ *  0b011..NACK Address. Slave NACKed address.
+ *  0b100..NACK Data. Slave NACKed transmitted data.
+ */
+#define I2C_STAT_MSTSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
+#define I2C_STAT_MSTARBLOSS_MASK                 (0x10U)
+#define I2C_STAT_MSTARBLOSS_SHIFT                (4U)
+/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to
+ *    this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
+ *  0b0..No Arbitration Loss has occurred.
+ *  0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master
+ *       function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing,
+ *       or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
+ */
+#define I2C_STAT_MSTARBLOSS(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
+#define I2C_STAT_MSTSTSTPERR_MASK                (0x40U)
+#define I2C_STAT_MSTSTSTPERR_SHIFT               (6U)
+/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to
+ *    this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
+ *  0b0..No Start/Stop Error has occurred.
+ *  0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is
+ *       not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an
+ *       idle state, no action is required. A request for a Start could be made, or software could attempt to insure
+ *       that the bus has not stalled.
+ */
+#define I2C_STAT_MSTSTSTPERR(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
+#define I2C_STAT_SLVPENDING_MASK                 (0x100U)
+#define I2C_STAT_SLVPENDING_SHIFT                (8U)
+/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue
+ *    communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if
+ *    enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the
+ *    SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is
+ *    automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time
+ *    when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section
+ *    25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are
+ *    detected automatically. Due to the requirements of the HS I2C specification, slave addresses must
+ *    also be detected automatically, since the address must be acknowledged before the clock can be
+ *    stretched.
+ *  0b0..In progress. The Slave function does not currently need service.
+ *  0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
+ */
+#define I2C_STAT_SLVPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
+#define I2C_STAT_SLVSTATE_MASK                   (0x600U)
+#define I2C_STAT_SLVSTATE_SHIFT                  (9U)
+/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for
+ *    the Slave function. All other values are reserved. See Table 401 for state values and actions.
+ *    note that the occurrence of some states and how they are handled are affected by DMA mode and
+ *    Automatic Operation modes.
+ *  0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
+ *  0b01..Slave receive. Received data is available (Slave Receiver mode).
+ *  0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode).
+ */
+#define I2C_STAT_SLVSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
+#define I2C_STAT_SLVNOTSTR_MASK                  (0x800U)
+#define I2C_STAT_SLVNOTSTR_SHIFT                 (11U)
+/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock.
+ *    This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave
+ *    operation. This read-only flag reflects the slave function status in real time.
+ *  0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
+ *  0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or
+ *       Power-down mode could be entered at this time.
+ */
+#define I2C_STAT_SLVNOTSTR(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
+#define I2C_STAT_SLVIDX_MASK                     (0x3000U)
+#define I2C_STAT_SLVIDX_SHIFT                    (12U)
+/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been
+ *    selected by receiving an address that matches one of the slave addresses defined by any enabled
+ *    slave address registers, and provides an identification of the address that was matched. It is
+ *    possible that more than one address could be matched, but only one match can be reported here.
+ *  0b00..Address 0. Slave address 0 was matched.
+ *  0b01..Address 1. Slave address 1 was matched.
+ *  0b10..Address 2. Slave address 2 was matched.
+ *  0b11..Address 3. Slave address 3 was matched.
+ */
+#define I2C_STAT_SLVIDX(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
+#define I2C_STAT_SLVSEL_MASK                     (0x4000U)
+#define I2C_STAT_SLVSEL_SHIFT                    (14U)
+/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave
+ *    function to acknowledge the address, or when the address has been automatically acknowledged.
+ *    It is cleared when another address cycle presents an address that does not match an enabled
+ *    address on the Slave function, when slave software decides to NACK a matched address, when
+ *    there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of
+ *    Automatic Operation. SLVSEL is not cleared if software NACKs data.
+ *  0b0..Not selected. The Slave function is not currently selected.
+ *  0b1..Selected. The Slave function is currently selected.
+ */
+#define I2C_STAT_SLVSEL(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
+#define I2C_STAT_SLVDESEL_MASK                   (0x8000U)
+#define I2C_STAT_SLVDESEL_SHIFT                  (15U)
+/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via
+ *    INTENSET. This flag can be cleared by writing a 1 to this bit.
+ *  0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently
+ *       selected. That information can be found in the SLVSEL flag.
+ *  0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag
+ *       changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
+ */
+#define I2C_STAT_SLVDESEL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
+#define I2C_STAT_MONRDY_MASK                     (0x10000U)
+#define I2C_STAT_MONRDY_SHIFT                    (16U)
+/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read.
+ *  0b0..No data. The Monitor function does not currently have data available.
+ *  0b1..Data waiting. The Monitor function has data waiting to be read.
+ */
+#define I2C_STAT_MONRDY(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
+#define I2C_STAT_MONOV_MASK                      (0x20000U)
+#define I2C_STAT_MONOV_SHIFT                     (17U)
+/*! MONOV - Monitor Overflow flag.
+ *  0b0..No overrun. Monitor data has not overrun.
+ *  0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not
+ *       enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
+ */
+#define I2C_STAT_MONOV(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
+#define I2C_STAT_MONACTIVE_MASK                  (0x40000U)
+#define I2C_STAT_MONACTIVE_SHIFT                 (18U)
+/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to
+ *    be active. Active is defined here as when some Master is on the bus: a bus Start has occurred
+ *    more recently than a bus Stop.
+ *  0b0..Inactive. The Monitor function considers the I2C bus to be inactive.
+ *  0b1..Active. The Monitor function considers the I2C bus to be active.
+ */
+#define I2C_STAT_MONACTIVE(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
+#define I2C_STAT_MONIDLE_MASK                    (0x80000U)
+#define I2C_STAT_MONIDLE_SHIFT                   (19U)
+/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change
+ *    from active to inactive. This can be used by software to decide when to process data
+ *    accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the
+ *    INTENSET register. The flag can be cleared by writing a 1 to this bit.
+ *  0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software.
+ *  0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
+ */
+#define I2C_STAT_MONIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
+#define I2C_STAT_EVENTTIMEOUT_MASK               (0x1000000U)
+#define I2C_STAT_EVENTTIMEOUT_SHIFT              (24U)
+/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been
+ *    longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock
+ *    edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus
+ *    is idle.
+ *  0b0..No time-out. I2C bus events have not caused a time-out.
+ *  0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
+ */
+#define I2C_STAT_EVENTTIMEOUT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
+#define I2C_STAT_SCLTIMEOUT_MASK                 (0x2000000U)
+#define I2C_STAT_SCLTIMEOUT_SHIFT                (25U)
+/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the
+ *    time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
+ *  0b0..No time-out. SCL low time has not caused a time-out.
+ *  0b1..Time-out. SCL low time has caused a time-out.
+ */
+#define I2C_STAT_SCLTIMEOUT(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
+/*! @} */
+
+/*! @name INTENSET - Interrupt Enable Set and read register. */
+/*! @{ */
+#define I2C_INTENSET_MSTPENDINGEN_MASK           (0x1U)
+#define I2C_INTENSET_MSTPENDINGEN_SHIFT          (0U)
+/*! MSTPENDINGEN - Master Pending interrupt Enable.
+ *  0b0..Disabled. The MstPending interrupt is disabled.
+ *  0b1..Enabled. The MstPending interrupt is enabled.
+ */
+#define I2C_INTENSET_MSTPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
+#define I2C_INTENSET_MSTARBLOSSEN_MASK           (0x10U)
+#define I2C_INTENSET_MSTARBLOSSEN_SHIFT          (4U)
+/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable.
+ *  0b0..Disabled. The MstArbLoss interrupt is disabled.
+ *  0b1..Enabled. The MstArbLoss interrupt is enabled.
+ */
+#define I2C_INTENSET_MSTARBLOSSEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
+#define I2C_INTENSET_MSTSTSTPERREN_MASK          (0x40U)
+#define I2C_INTENSET_MSTSTSTPERREN_SHIFT         (6U)
+/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable.
+ *  0b0..Disabled. The MstStStpErr interrupt is disabled.
+ *  0b1..Enabled. The MstStStpErr interrupt is enabled.
+ */
+#define I2C_INTENSET_MSTSTSTPERREN(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
+#define I2C_INTENSET_SLVPENDINGEN_MASK           (0x100U)
+#define I2C_INTENSET_SLVPENDINGEN_SHIFT          (8U)
+/*! SLVPENDINGEN - Slave Pending interrupt Enable.
+ *  0b0..Disabled. The SlvPending interrupt is disabled.
+ *  0b1..Enabled. The SlvPending interrupt is enabled.
+ */
+#define I2C_INTENSET_SLVPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
+#define I2C_INTENSET_SLVNOTSTREN_MASK            (0x800U)
+#define I2C_INTENSET_SLVNOTSTREN_SHIFT           (11U)
+/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable.
+ *  0b0..Disabled. The SlvNotStr interrupt is disabled.
+ *  0b1..Enabled. The SlvNotStr interrupt is enabled.
+ */
+#define I2C_INTENSET_SLVNOTSTREN(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
+#define I2C_INTENSET_SLVDESELEN_MASK             (0x8000U)
+#define I2C_INTENSET_SLVDESELEN_SHIFT            (15U)
+/*! SLVDESELEN - Slave Deselect interrupt Enable.
+ *  0b0..Disabled. The SlvDeSel interrupt is disabled.
+ *  0b1..Enabled. The SlvDeSel interrupt is enabled.
+ */
+#define I2C_INTENSET_SLVDESELEN(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
+#define I2C_INTENSET_MONRDYEN_MASK               (0x10000U)
+#define I2C_INTENSET_MONRDYEN_SHIFT              (16U)
+/*! MONRDYEN - Monitor data Ready interrupt Enable.
+ *  0b0..Disabled. The MonRdy interrupt is disabled.
+ *  0b1..Enabled. The MonRdy interrupt is enabled.
+ */
+#define I2C_INTENSET_MONRDYEN(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
+#define I2C_INTENSET_MONOVEN_MASK                (0x20000U)
+#define I2C_INTENSET_MONOVEN_SHIFT               (17U)
+/*! MONOVEN - Monitor Overrun interrupt Enable.
+ *  0b0..Disabled. The MonOv interrupt is disabled.
+ *  0b1..Enabled. The MonOv interrupt is enabled.
+ */
+#define I2C_INTENSET_MONOVEN(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
+#define I2C_INTENSET_MONIDLEEN_MASK              (0x80000U)
+#define I2C_INTENSET_MONIDLEEN_SHIFT             (19U)
+/*! MONIDLEEN - Monitor Idle interrupt Enable.
+ *  0b0..Disabled. The MonIdle interrupt is disabled.
+ *  0b1..Enabled. The MonIdle interrupt is enabled.
+ */
+#define I2C_INTENSET_MONIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
+#define I2C_INTENSET_EVENTTIMEOUTEN_MASK         (0x1000000U)
+#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT        (24U)
+/*! EVENTTIMEOUTEN - Event time-out interrupt Enable.
+ *  0b0..Disabled. The Event time-out interrupt is disabled.
+ *  0b1..Enabled. The Event time-out interrupt is enabled.
+ */
+#define I2C_INTENSET_EVENTTIMEOUTEN(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
+#define I2C_INTENSET_SCLTIMEOUTEN_MASK           (0x2000000U)
+#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT          (25U)
+/*! SCLTIMEOUTEN - SCL time-out interrupt Enable.
+ *  0b0..Disabled. The SCL time-out interrupt is disabled.
+ *  0b1..Enabled. The SCL time-out interrupt is enabled.
+ */
+#define I2C_INTENSET_SCLTIMEOUTEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
+/*! @} */
+
+/*! @name INTENCLR - Interrupt Enable Clear register. */
+/*! @{ */
+#define I2C_INTENCLR_MSTPENDINGCLR_MASK          (0x1U)
+#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT         (0U)
+/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding
+ *    bit in the INTENSET register if implemented.
+ */
+#define I2C_INTENCLR_MSTPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
+#define I2C_INTENCLR_MSTARBLOSSCLR_MASK          (0x10U)
+#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT         (4U)
+/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear.
+ */
+#define I2C_INTENCLR_MSTARBLOSSCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
+#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK         (0x40U)
+#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT        (6U)
+/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear.
+ */
+#define I2C_INTENCLR_MSTSTSTPERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
+#define I2C_INTENCLR_SLVPENDINGCLR_MASK          (0x100U)
+#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT         (8U)
+/*! SLVPENDINGCLR - Slave Pending interrupt clear.
+ */
+#define I2C_INTENCLR_SLVPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
+#define I2C_INTENCLR_SLVNOTSTRCLR_MASK           (0x800U)
+#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT          (11U)
+/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear.
+ */
+#define I2C_INTENCLR_SLVNOTSTRCLR(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
+#define I2C_INTENCLR_SLVDESELCLR_MASK            (0x8000U)
+#define I2C_INTENCLR_SLVDESELCLR_SHIFT           (15U)
+/*! SLVDESELCLR - Slave Deselect interrupt clear.
+ */
+#define I2C_INTENCLR_SLVDESELCLR(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
+#define I2C_INTENCLR_MONRDYCLR_MASK              (0x10000U)
+#define I2C_INTENCLR_MONRDYCLR_SHIFT             (16U)
+/*! MONRDYCLR - Monitor data Ready interrupt clear.
+ */
+#define I2C_INTENCLR_MONRDYCLR(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
+#define I2C_INTENCLR_MONOVCLR_MASK               (0x20000U)
+#define I2C_INTENCLR_MONOVCLR_SHIFT              (17U)
+/*! MONOVCLR - Monitor Overrun interrupt clear.
+ */
+#define I2C_INTENCLR_MONOVCLR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
+#define I2C_INTENCLR_MONIDLECLR_MASK             (0x80000U)
+#define I2C_INTENCLR_MONIDLECLR_SHIFT            (19U)
+/*! MONIDLECLR - Monitor Idle interrupt clear.
+ */
+#define I2C_INTENCLR_MONIDLECLR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK        (0x1000000U)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT       (24U)
+/*! EVENTTIMEOUTCLR - Event time-out interrupt clear.
+ */
+#define I2C_INTENCLR_EVENTTIMEOUTCLR(x)          (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
+#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK          (0x2000000U)
+#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT         (25U)
+/*! SCLTIMEOUTCLR - SCL time-out interrupt clear.
+ */
+#define I2C_INTENCLR_SCLTIMEOUTCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
+/*! @} */
+
+/*! @name TIMEOUT - Time-out value register. */
+/*! @{ */
+#define I2C_TIMEOUT_TOMIN_MASK                   (0xFU)
+#define I2C_TIMEOUT_TOMIN_SHIFT                  (0U)
+/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum
+ *    time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
+ */
+#define I2C_TIMEOUT_TOMIN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
+#define I2C_TIMEOUT_TO_MASK                      (0xFFF0U)
+#define I2C_TIMEOUT_TO_SHIFT                     (4U)
+/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C
+ *    function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation,
+ *    disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A
+ *    time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after
+ *    32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the
+ *    I2C function clock.
+ */
+#define I2C_TIMEOUT_TO(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
+/*! @} */
+
+/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */
+/*! @{ */
+#define I2C_CLKDIV_DIVVAL_MASK                   (0xFFFFU)
+#define I2C_CLKDIV_DIVVAL_SHIFT                  (0U)
+/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that
+ *    need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 =
+ *    FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is
+ *    divided by 65,536 before use.
+ */
+#define I2C_CLKDIV_DIVVAL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
+/*! @{ */
+#define I2C_INTSTAT_MSTPENDING_MASK              (0x1U)
+#define I2C_INTSTAT_MSTPENDING_SHIFT             (0U)
+/*! MSTPENDING - Master Pending.
+ */
+#define I2C_INTSTAT_MSTPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
+#define I2C_INTSTAT_MSTARBLOSS_MASK              (0x10U)
+#define I2C_INTSTAT_MSTARBLOSS_SHIFT             (4U)
+/*! MSTARBLOSS - Master Arbitration Loss flag.
+ */
+#define I2C_INTSTAT_MSTARBLOSS(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
+#define I2C_INTSTAT_MSTSTSTPERR_MASK             (0x40U)
+#define I2C_INTSTAT_MSTSTSTPERR_SHIFT            (6U)
+/*! MSTSTSTPERR - Master Start/Stop Error flag.
+ */
+#define I2C_INTSTAT_MSTSTSTPERR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
+#define I2C_INTSTAT_SLVPENDING_MASK              (0x100U)
+#define I2C_INTSTAT_SLVPENDING_SHIFT             (8U)
+/*! SLVPENDING - Slave Pending.
+ */
+#define I2C_INTSTAT_SLVPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
+#define I2C_INTSTAT_SLVNOTSTR_MASK               (0x800U)
+#define I2C_INTSTAT_SLVNOTSTR_SHIFT              (11U)
+/*! SLVNOTSTR - Slave Not Stretching status.
+ */
+#define I2C_INTSTAT_SLVNOTSTR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
+#define I2C_INTSTAT_SLVDESEL_MASK                (0x8000U)
+#define I2C_INTSTAT_SLVDESEL_SHIFT               (15U)
+/*! SLVDESEL - Slave Deselected flag.
+ */
+#define I2C_INTSTAT_SLVDESEL(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
+#define I2C_INTSTAT_MONRDY_MASK                  (0x10000U)
+#define I2C_INTSTAT_MONRDY_SHIFT                 (16U)
+/*! MONRDY - Monitor Ready.
+ */
+#define I2C_INTSTAT_MONRDY(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
+#define I2C_INTSTAT_MONOV_MASK                   (0x20000U)
+#define I2C_INTSTAT_MONOV_SHIFT                  (17U)
+/*! MONOV - Monitor Overflow flag.
+ */
+#define I2C_INTSTAT_MONOV(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
+#define I2C_INTSTAT_MONIDLE_MASK                 (0x80000U)
+#define I2C_INTSTAT_MONIDLE_SHIFT                (19U)
+/*! MONIDLE - Monitor Idle flag.
+ */
+#define I2C_INTSTAT_MONIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
+#define I2C_INTSTAT_EVENTTIMEOUT_MASK            (0x1000000U)
+#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT           (24U)
+/*! EVENTTIMEOUT - Event time-out Interrupt flag.
+ */
+#define I2C_INTSTAT_EVENTTIMEOUT(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
+#define I2C_INTSTAT_SCLTIMEOUT_MASK              (0x2000000U)
+#define I2C_INTSTAT_SCLTIMEOUT_SHIFT             (25U)
+/*! SCLTIMEOUT - SCL time-out Interrupt flag.
+ */
+#define I2C_INTSTAT_SCLTIMEOUT(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
+/*! @} */
+
+/*! @name MSTCTL - Master control register. */
+/*! @{ */
+#define I2C_MSTCTL_MSTCONTINUE_MASK              (0x1U)
+#define I2C_MSTCTL_MSTCONTINUE_SHIFT             (0U)
+/*! MSTCONTINUE - Master Continue. This bit is write-only.
+ *  0b0..No effect.
+ *  0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing
+ *       transmit data, reading received data, or any other housekeeping related to the next bus operation.
+ */
+#define I2C_MSTCTL_MSTCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
+#define I2C_MSTCTL_MSTSTART_MASK                 (0x2U)
+#define I2C_MSTCTL_MSTSTART_SHIFT                (1U)
+/*! MSTSTART - Master Start control. This bit is write-only.
+ *  0b0..No effect.
+ *  0b1..Start. A Start will be generated on the I2C bus at the next allowed time.
+ */
+#define I2C_MSTCTL_MSTSTART(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
+#define I2C_MSTCTL_MSTSTOP_MASK                  (0x4U)
+#define I2C_MSTCTL_MSTSTOP_SHIFT                 (2U)
+/*! MSTSTOP - Master Stop control. This bit is write-only.
+ *  0b0..No effect.
+ *  0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave
+ *       if the master is receiving data from the slave (Master Receiver mode).
+ */
+#define I2C_MSTCTL_MSTSTOP(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
+#define I2C_MSTCTL_MSTDMA_MASK                   (0x8U)
+#define I2C_MSTCTL_MSTDMA_SHIFT                  (3U)
+/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type
+ *    operations such as Start, address, Stop, and address match must always be done with software,
+ *    typically via an interrupt. Address acknowledgement must also be done by software except when
+ *    the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by
+ *    hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA
+ *    must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is
+ *    read/write.
+ *  0b0..Disable. No DMA requests are generated for master operation.
+ *  0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating
+ *       Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
+ */
+#define I2C_MSTCTL_MSTDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
+/*! @} */
+
+/*! @name MSTTIME - Master timing configuration. */
+/*! @{ */
+#define I2C_MSTTIME_MSTSCLLOW_MASK               (0x7U)
+#define I2C_MSTTIME_MSTSCLLOW_SHIFT              (0U)
+/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this
+ *    master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This
+ *    corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters
+ *    tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.
+ *  0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
+ *  0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
+ *  0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
+ *  0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
+ *  0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
+ *  0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
+ *  0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
+ *  0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
+ */
+#define I2C_MSTTIME_MSTSCLLOW(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
+#define I2C_MSTTIME_MSTSCLHIGH_MASK              (0x70U)
+#define I2C_MSTTIME_MSTSCLHIGH_SHIFT             (4U)
+/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this
+ *    master on SCL. Other masters in a multi-master system could shorten this time. This
+ *    corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters
+ *    tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.
+ *  0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
+ *  0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
+ *  0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
+ *  0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
+ *  0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
+ *  0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
+ *  0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
+ *  0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
+ */
+#define I2C_MSTTIME_MSTSCLHIGH(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
+/*! @} */
+
+/*! @name MSTDAT - Combined Master receiver and transmitter data register. */
+/*! @{ */
+#define I2C_MSTDAT_DATA_MASK                     (0xFFU)
+#define I2C_MSTDAT_DATA_SHIFT                    (0U)
+/*! DATA - Master function data register. Read: read the most recently received data for the Master
+ *    function. Write: transmit data using the Master function.
+ */
+#define I2C_MSTDAT_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
+/*! @} */
+
+/*! @name SLVCTL - Slave control register. */
+/*! @{ */
+#define I2C_SLVCTL_SLVCONTINUE_MASK              (0x1U)
+#define I2C_SLVCTL_SLVCONTINUE_SHIFT             (0U)
+/*! SLVCONTINUE - Slave Continue.
+ *  0b0..No effect.
+ *  0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag
+ *       in the STAT register. This must be done after writing transmit data, reading received data, or any other
+ *       housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE
+ *       should not be set unless SLVPENDING = 1.
+ */
+#define I2C_SLVCTL_SLVCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
+#define I2C_SLVCTL_SLVNACK_MASK                  (0x2U)
+#define I2C_SLVCTL_SLVNACK_SHIFT                 (1U)
+/*! SLVNACK - Slave NACK.
+ *  0b0..No effect.
+ *  0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).
+ */
+#define I2C_SLVCTL_SLVNACK(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
+#define I2C_SLVCTL_SLVDMA_MASK                   (0x8U)
+#define I2C_SLVCTL_SLVDMA_SHIFT                  (3U)
+/*! SLVDMA - Slave DMA enable.
+ *  0b0..Disabled. No DMA requests are issued for Slave mode operation.
+ *  0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception.
+ */
+#define I2C_SLVCTL_SLVDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
+#define I2C_SLVCTL_AUTOACK_MASK                  (0x100U)
+#define I2C_SLVCTL_AUTOACK_SHIFT                 (8U)
+/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches
+ *    SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA
+ *    to allow processing of the data without intervention. If this bit is clear and a header
+ *    matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or
+ *    interrupt.
+ *  0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching
+ *       address is received. If AUTONACK = 1, received addresses are NACKed (ignored).
+ *  0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately,
+ *       allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does
+ *       not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK
+ *       is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated.
+ */
+#define I2C_SLVCTL_AUTOACK(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)
+#define I2C_SLVCTL_AUTOMATCHREAD_MASK            (0x200U)
+#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT           (9U)
+/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write
+ *    request on the next header with an address matching SLVADR0. Since DMA needs to be configured to
+ *    match the transfer direction, the direction needs to be specified. This bit allows a direction to
+ *    be chosen for the next operation.
+ *  0b0..The expected next operation in Automatic Mode is an I2C write.
+ *  0b1..The expected next operation in Automatic Mode is an I2C read.
+ */
+#define I2C_SLVCTL_AUTOMATCHREAD(x)              (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
+/*! @} */
+
+/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */
+/*! @{ */
+#define I2C_SLVDAT_DATA_MASK                     (0xFFU)
+#define I2C_SLVDAT_DATA_SHIFT                    (0U)
+/*! DATA - Slave function data register. Read: read the most recently received data for the Slave
+ *    function. Write: transmit data using the Slave function.
+ */
+#define I2C_SLVDAT_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
+/*! @} */
+
+/*! @name SLVADR - Slave address register. */
+/*! @{ */
+#define I2C_SLVADR_SADISABLE_MASK                (0x1U)
+#define I2C_SLVADR_SADISABLE_SHIFT               (0U)
+/*! SADISABLE - Slave Address n Disable.
+ *  0b0..Enabled. Slave Address n is enabled.
+ *  0b1..Ignored Slave Address n is ignored.
+ */
+#define I2C_SLVADR_SADISABLE(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
+#define I2C_SLVADR_SLVADR_MASK                   (0xFEU)
+#define I2C_SLVADR_SLVADR_SHIFT                  (1U)
+/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled.
+ */
+#define I2C_SLVADR_SLVADR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
+#define I2C_SLVADR_AUTONACK_MASK                 (0x8000U)
+#define I2C_SLVADR_AUTONACK_SHIFT                (15U)
+/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows
+ *    software to ignore I2C traffic while handling previous I2C data or other operations.
+ *  0b0..Normal operation, matching I2C addresses are not ignored.
+ *  0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches
+ *       SLVADRn, and AUTOMATCHREAD matches the direction.
+ */
+#define I2C_SLVADR_AUTONACK(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
+/*! @} */
+
+/* The count of I2C_SLVADR */
+#define I2C_SLVADR_COUNT                         (4U)
+
+/*! @name SLVQUAL0 - Slave Qualification for address 0. */
+/*! @{ */
+#define I2C_SLVQUAL0_QUALMODE0_MASK              (0x1U)
+#define I2C_SLVQUAL0_QUALMODE0_SHIFT             (0U)
+/*! QUALMODE0 - Qualify mode for slave address 0.
+ *  0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
+ *  0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
+ */
+#define I2C_SLVQUAL0_QUALMODE0(x)                (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
+#define I2C_SLVQUAL0_SLVQUAL0_MASK               (0xFEU)
+#define I2C_SLVQUAL0_SLVQUAL0_SHIFT              (1U)
+/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to
+ *    be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is
+ *    set to 1 will cause an automatic match of the corresponding bit of the received address when it
+ *    is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for
+ *    address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0
+ *    (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).
+ */
+#define I2C_SLVQUAL0_SLVQUAL0(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
+/*! @} */
+
+/*! @name MONRXDAT - Monitor receiver data register. */
+/*! @{ */
+#define I2C_MONRXDAT_MONRXDAT_MASK               (0xFFU)
+#define I2C_MONRXDAT_MONRXDAT_SHIFT              (0U)
+/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.
+ */
+#define I2C_MONRXDAT_MONRXDAT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
+#define I2C_MONRXDAT_MONSTART_MASK               (0x100U)
+#define I2C_MONRXDAT_MONSTART_SHIFT              (8U)
+/*! MONSTART - Monitor Received Start.
+ *  0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus.
+ *  0b1..Start detected. The Monitor function has detected a Start event on the I2C bus.
+ */
+#define I2C_MONRXDAT_MONSTART(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
+#define I2C_MONRXDAT_MONRESTART_MASK             (0x200U)
+#define I2C_MONRXDAT_MONRESTART_SHIFT            (9U)
+/*! MONRESTART - Monitor Received Repeated Start.
+ *  0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
+ *  0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
+ */
+#define I2C_MONRXDAT_MONRESTART(x)               (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
+#define I2C_MONRXDAT_MONNACK_MASK                (0x400U)
+#define I2C_MONRXDAT_MONNACK_SHIFT               (10U)
+/*! MONNACK - Monitor Received NACK.
+ *  0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
+ *  0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
+ */
+#define I2C_MONRXDAT_MONNACK(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
+/*! @} */
+
+/*! @name ID - Peripheral identification register. */
+/*! @{ */
+#define I2C_ID_APERTURE_MASK                     (0xFFU)
+#define I2C_ID_APERTURE_SHIFT                    (0U)
+/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
+ */
+#define I2C_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)
+#define I2C_ID_MINOR_REV_MASK                    (0xF00U)
+#define I2C_ID_MINOR_REV_SHIFT                   (8U)
+/*! MINOR_REV - Minor revision of module implementation.
+ */
+#define I2C_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)
+#define I2C_ID_MAJOR_REV_MASK                    (0xF000U)
+#define I2C_ID_MAJOR_REV_SHIFT                   (12U)
+/*! MAJOR_REV - Major revision of module implementation.
+ */
+#define I2C_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)
+#define I2C_ID_ID_MASK                           (0xFFFF0000U)
+#define I2C_ID_ID_SHIFT                          (16U)
+/*! ID - Module identifier for the selected function.
+ */
+#define I2C_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40086000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE                                (0x40087000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1                                     ((I2C_Type *)I2C1_BASE)
+/** Peripheral I2C2 base address */
+#define I2C2_BASE                                (0x40088000u)
+/** Peripheral I2C2 base pointer */
+#define I2C2                                     ((I2C_Type *)I2C2_BASE)
+/** Peripheral I2C3 base address */
+#define I2C3_BASE                                (0x40089000u)
+/** Peripheral I2C3 base pointer */
+#define I2C3                                     ((I2C_Type *)I2C3_BASE)
+/** Peripheral I2C4 base address */
+#define I2C4_BASE                                (0x4008A000u)
+/** Peripheral I2C4 base pointer */
+#define I2C4                                     ((I2C_Type *)I2C4_BASE)
+/** Peripheral I2C5 base address */
+#define I2C5_BASE                                (0x40096000u)
+/** Peripheral I2C5 base pointer */
+#define I2C5                                     ((I2C_Type *)I2C5_BASE)
+/** Peripheral I2C6 base address */
+#define I2C6_BASE                                (0x40097000u)
+/** Peripheral I2C6 base pointer */
+#define I2C6                                     ((I2C_Type *)I2C6_BASE)
+/** Peripheral I2C7 base address */
+#define I2C7_BASE                                (0x40098000u)
+/** Peripheral I2C7 base pointer */
+#define I2C7                                     ((I2C_Type *)I2C7_BASE)
+/** Peripheral I2C8 base address */
+#define I2C8_BASE                                (0x40099000u)
+/** Peripheral I2C8 base pointer */
+#define I2C8                                     ((I2C_Type *)I2C8_BASE)
+/** Peripheral I2C9 base address */
+#define I2C9_BASE                                (0x4009A000u)
+/** Peripheral I2C9 base pointer */
+#define I2C9                                     ((I2C_Type *)I2C9_BASE)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE, I2C9_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[3072];
+  __IO uint32_t CFG1;                              /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */
+  __IO uint32_t CFG2;                              /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */
+  __IO uint32_t STAT;                              /**< Status register for the primary channel pair., offset: 0xC08 */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t DIV;                               /**< Clock divider, used by all channel pairs., offset: 0xC1C */
+  struct {                                         /* offset: 0xC20, array step: 0x20 */
+    __IO uint32_t PCFG1;                             /**< Configuration register 1 for channel pair, array offset: 0xC20, array step: 0x20 */
+    __IO uint32_t PCFG2;                             /**< Configuration register 2 for channel pair, array offset: 0xC24, array step: 0x20 */
+    __IO uint32_t PSTAT;                             /**< Status register for channel pair, array offset: 0xC28, array step: 0x20 */
+         uint8_t RESERVED_0[20];
+  } SECCHANNEL[3];
+       uint8_t RESERVED_2[384];
+  __IO uint32_t FIFOCFG;                           /**< FIFO configuration and enable register., offset: 0xE00 */
+  __IO uint32_t FIFOSTAT;                          /**< FIFO status register., offset: 0xE04 */
+  __IO uint32_t FIFOTRIG;                          /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t FIFOINTENSET;                      /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+  __IO uint32_t FIFOINTENCLR;                      /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+  __I  uint32_t FIFOINTSTAT;                       /**< FIFO interrupt status register., offset: 0xE18 */
+       uint8_t RESERVED_4[4];
+  __O  uint32_t FIFOWR;                            /**< FIFO write data., offset: 0xE20 */
+  __O  uint32_t FIFOWR48H;                         /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */
+       uint8_t RESERVED_5[8];
+  __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */
+  __I  uint32_t FIFORD48H;                         /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */
+       uint8_t RESERVED_6[8];
+  __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+  __I  uint32_t FIFORD48HNOPOP;                    /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */
+       uint8_t RESERVED_7[4020];
+  __I  uint32_t ID;                                /**< I2S Module identification, offset: 0x1DFC */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/*! @name CFG1 - Configuration register 1 for the primary channel pair. */
+/*! @{ */
+#define I2S_CFG1_MAINENABLE_MASK                 (0x1U)
+#define I2S_CFG1_MAINENABLE_SHIFT                (0U)
+/*! MAINENABLE - Main enable for I 2S function in this Flexcomm
+ *  0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags
+ *       are reset. No other channel pairs can be enabled.
+ *  0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits.
+ */
+#define I2S_CFG1_MAINENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)
+#define I2S_CFG1_DATAPAUSE_MASK                  (0x2U)
+#define I2S_CFG1_DATAPAUSE_SHIFT                 (1U)
+/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer
+ *    and the FIFO. This could be done in order to change streams, or while restarting after a data
+ *    underflow or overflow. When paused, FIFO operations can be done without corrupting data that is
+ *    in the process of being sent or received. Once a data pause has been requested, the interface
+ *    may need to complete sending data that was in progress before interrupting the flow of data.
+ *    Software must check that the pause is actually in effect before taking action. This is done by
+ *    monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer
+ *    will resume at the beginning of the next frame.
+ *  0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused.
+ *  0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1.
+ */
+#define I2S_CFG1_DATAPAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)
+#define I2S_CFG1_PAIRCOUNT_MASK                  (0xCU)
+#define I2S_CFG1_PAIRCOUNT_SHIFT                 (2U)
+/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field
+ *    whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this
+ *    Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs
+ *    in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm.
+ *  0b00..1 I2S channel pairs in this flexcomm
+ *  0b01..2 I2S channel pairs in this flexcomm
+ *  0b10..3 I2S channel pairs in this flexcomm
+ *  0b11..4 I2S channel pairs in this flexcomm
+ */
+#define I2S_CFG1_PAIRCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)
+#define I2S_CFG1_MSTSLVCFG_MASK                  (0x30U)
+#define I2S_CFG1_MSTSLVCFG_SHIFT                 (4U)
+/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm.
+ *  0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data.
+ *  0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of
+ *        SCK, when divided from the Flexcomm function clock.
+ *  0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data.
+ *  0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices.
+ */
+#define I2S_CFG1_MSTSLVCFG(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)
+#define I2S_CFG1_MODE_MASK                       (0xC0U)
+#define I2S_CFG1_MODE_SHIFT                      (6U)
+/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all
+ *    supported cases. See Formats and modes for examples.
+ *  0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece
+ *        of left channel data occurring during the first phase, and one pieces of right channel data occurring
+ *        during the second phase. In this mode, the data region begins one clock after the leading WS edge for the
+ *        frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If
+ *        FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right.
+ *  0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0.
+ *  0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame.
+ *  0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame.
+ */
+#define I2S_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)
+#define I2S_CFG1_RIGHTLOW_MASK                   (0x100U)
+#define I2S_CFG1_RIGHTLOW_SHIFT                  (8U)
+/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left
+ *    and right channel data as it is transferred to or from the FIFO. This bit is not used if the
+ *    data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10
+ *    of this register) = 1, the one channel to be used is the nominally the left channel. POSITION
+ *    can still place that data in the frame where right channel data is normally located. if all
+ *    enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed.
+ *  0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO
+ *       bits 31:16 are used for the right channel.
+ *  0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO
+ *       bits 15:0 are used for the right channel.
+ */
+#define I2S_CFG1_RIGHTLOW(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)
+#define I2S_CFG1_LEFTJUST_MASK                   (0x200U)
+#define I2S_CFG1_LEFTJUST_SHIFT                  (9U)
+/*! LEFTJUST - Left Justify data.
+ *  0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting
+ *       from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data
+ *       in the stream on the data bus.
+ *  0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting
+ *       from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would
+ *       correspond to left justified data in the stream on the data bus.
+ */
+#define I2S_CFG1_LEFTJUST(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)
+#define I2S_CFG1_ONECHANNEL_MASK                 (0x400U)
+#define I2S_CFG1_ONECHANNEL_SHIFT                (10U)
+/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit
+ *    applies only to the first I2S channel pair. Other channel pairs may select this mode
+ *    independently in their separate CFG1 registers.
+ *  0b0..I2S data for this channel pair is treated as left and right channels.
+ *  0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this
+ *       pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a
+ *       clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel
+ *       of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side
+ *       (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data
+ *       for the single channel of data is placed at the clock defined by POSITION.
+ */
+#define I2S_CFG1_ONECHANNEL(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
+#define I2S_CFG1_PDMDATA_MASK                    (0x800U)
+#define I2S_CFG1_PDMDATA_SHIFT                   (11U)
+/*! PDMDATA - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be
+ *    set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a
+ *    D-Mic subsystem. For the LPC5411x, this bit applies only to Flexcomm 7.
+ *  0b0..Normal operation, data is transferred to or from the Flexcomm FIFO.
+ *  0b1..The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in
+ *       this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample
+ *       rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun.
+ */
+#define I2S_CFG1_PDMDATA(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK)
+#define I2S_CFG1_SCK_POL_MASK                    (0x1000U)
+#define I2S_CFG1_SCK_POL_SHIFT                   (12U)
+/*! SCK_POL - SCK polarity.
+ *  0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S).
+ *  0b1..Data is launched on SCK rising edges and sampled on SCK falling edges.
+ */
+#define I2S_CFG1_SCK_POL(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)
+#define I2S_CFG1_WS_POL_MASK                     (0x2000U)
+#define I2S_CFG1_WS_POL_SHIFT                    (13U)
+/*! WS_POL - WS polarity.
+ *  0b0..Data frames begin at a falling edge of WS (standard for classic I2S).
+ *  0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S).
+ */
+#define I2S_CFG1_WS_POL(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)
+#define I2S_CFG1_DATALEN_MASK                    (0x1F0000U)
+#define I2S_CFG1_DATALEN_SHIFT                   (16U)
+/*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or
+ *    received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received
+ *    from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the
+ *    I2S: Determines the size of data transfers between the FIFO and the I2S
+ *    serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of
+ *    right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse
+ *    at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to
+ *    0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F =
+ *    data is 32 bits in length
+ */
+#define I2S_CFG1_DATALEN(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)
+/*! @} */
+
+/*! @name CFG2 - Configuration register 2 for the primary channel pair. */
+/*! @{ */
+#define I2S_CFG2_FRAMELEN_MASK                   (0x1FFU)
+#define I2S_CFG2_FRAMELEN_SHIFT                  (0U)
+/*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the
+ *    frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported
+ *    0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is
+ *    512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in
+ *    mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger
+ *    than DATALEN in order for the WS pulse to be generated correctly.
+ */
+#define I2S_CFG2_FRAMELEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)
+#define I2S_CFG2_POSITION_MASK                   (0x1FF0000U)
+#define I2S_CFG2_POSITION_SHIFT                  (16U)
+/*! POSITION - Data Position. Defines the location within the frame of the data for this channel
+ *    pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION
+ *    defines the location of data in both the left phase and right phase, starting one clock after
+ *    the WS edge. In other modes, POSITION defines the location of data within the entire frame.
+ *    ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The
+ *    combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels
+ *    do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit
+ *    position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS
+ *    phase. 0x002 = data begins at bit position 2 within the frame or WS phase.
+ */
+#define I2S_CFG2_POSITION(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)
+/*! @} */
+
+/*! @name STAT - Status register for the primary channel pair. */
+/*! @{ */
+#define I2S_STAT_BUSY_MASK                       (0x1U)
+#define I2S_STAT_BUSY_SHIFT                      (0U)
+/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair.
+ *  0b0..The transmitter/receiver for channel pair is currently idle.
+ *  0b1..The transmitter/receiver for channel pair is currently processing data.
+ */
+#define I2S_STAT_BUSY(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)
+#define I2S_STAT_SLVFRMERR_MASK                  (0x2U)
+#define I2S_STAT_SLVFRMERR_SHIFT                 (1U)
+/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as
+ *    a slave. An error indicates that the incoming WS signal did not transition as expected due to
+ *    a mismatch between FRAMELEN and the actual incoming I2S stream.
+ *  0b0..No error has been recorded.
+ *  0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position.
+ */
+#define I2S_STAT_SLVFRMERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)
+#define I2S_STAT_LR_MASK                         (0x4U)
+#define I2S_STAT_LR_SHIFT                        (2U)
+/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to
+ *    be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data
+ *    being processed for the currently busy channel pair.
+ *  0b0..Left channel.
+ *  0b1..Right channel.
+ */
+#define I2S_STAT_LR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)
+#define I2S_STAT_DATAPAUSED_MASK                 (0x8U)
+#define I2S_STAT_DATAPAUSED_SHIFT                (3U)
+/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels
+ *  0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for
+ *       an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register.
+ *  0b1..A data pause has been requested and is now in force.
+ */
+#define I2S_STAT_DATAPAUSED(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)
+/*! @} */
+
+/*! @name DIV - Clock divider, used by all channel pairs. */
+/*! @{ */
+#define I2S_DIV_DIV_MASK                         (0xFFFU)
+#define I2S_DIV_DIV_SHIFT                        (0U)
+/*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The
+ *    Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2.
+ *    0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is
+ *    divided by 4,096.
+ */
+#define I2S_DIV_DIV(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)
+/*! @} */
+
+/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */
+/*! @{ */
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK     (0x1U)
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT    (0U)
+/*! PAIRENABLE - Enable for this channel pair..
+ */
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK)
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK     (0x400U)
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT    (10U)
+/*! ONECHANNEL - Single channel mode.
+ */
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK)
+/*! @} */
+
+/* The count of I2S_SECCHANNEL_PCFG1 */
+#define I2S_SECCHANNEL_PCFG1_COUNT               (3U)
+
+/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */
+/*! @{ */
+#define I2S_SECCHANNEL_PCFG2_POSITION_MASK       (0x1FF0000U)
+#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT      (16U)
+/*! POSITION - Data Position.
+ */
+#define I2S_SECCHANNEL_PCFG2_POSITION(x)         (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK)
+/*! @} */
+
+/* The count of I2S_SECCHANNEL_PCFG2 */
+#define I2S_SECCHANNEL_PCFG2_COUNT               (3U)
+
+/*! @name SECCHANNEL_PSTAT - Status register for channel pair */
+/*! @{ */
+#define I2S_SECCHANNEL_PSTAT_BUSY_MASK           (0x1U)
+#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT          (0U)
+/*! BUSY - Busy status for this channel pair.
+ */
+#define I2S_SECCHANNEL_PSTAT_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK)
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK      (0x2U)
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT     (1U)
+/*! SLVFRMERR - Save Frame Error flag.
+ */
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x)        (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK)
+#define I2S_SECCHANNEL_PSTAT_LR_MASK             (0x4U)
+#define I2S_SECCHANNEL_PSTAT_LR_SHIFT            (2U)
+/*! LR - Left/Right indication.
+ */
+#define I2S_SECCHANNEL_PSTAT_LR(x)               (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK)
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK     (0x8U)
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT    (3U)
+/*! DATAPAUSED - Data Paused status flag.
+ */
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK)
+/*! @} */
+
+/* The count of I2S_SECCHANNEL_PSTAT */
+#define I2S_SECCHANNEL_PSTAT_COUNT               (3U)
+
+/*! @name FIFOCFG - FIFO configuration and enable register. */
+/*! @{ */
+#define I2S_FIFOCFG_ENABLETX_MASK                (0x1U)
+#define I2S_FIFOCFG_ENABLETX_SHIFT               (0U)
+/*! ENABLETX - Enable the transmit FIFO.
+ *  0b0..The transmit FIFO is not enabled.
+ *  0b1..The transmit FIFO is enabled.
+ */
+#define I2S_FIFOCFG_ENABLETX(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)
+#define I2S_FIFOCFG_ENABLERX_MASK                (0x2U)
+#define I2S_FIFOCFG_ENABLERX_SHIFT               (1U)
+/*! ENABLERX - Enable the receive FIFO.
+ *  0b0..The receive FIFO is not enabled.
+ *  0b1..The receive FIFO is enabled.
+ */
+#define I2S_FIFOCFG_ENABLERX(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)
+#define I2S_FIFOCFG_TXI2SE0_MASK                 (0x4U)
+#define I2S_FIFOCFG_TXI2SE0_SHIFT                (2U)
+/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX
+ *    FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is
+ *    cleared, new data is provided, and the I2S is un-paused.
+ *  0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24
+ *       bits or less, or when MONO = 1 for this channel pair.
+ *  0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred.
+ */
+#define I2S_FIFOCFG_TXI2SE0(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)
+#define I2S_FIFOCFG_PACK48_MASK                  (0x8U)
+#define I2S_FIFOCFG_PACK48_SHIFT                 (3U)
+/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA.
+ *  0b0..48-bit I2S FIFO entries are handled as all 24-bit values.
+ *  0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values.
+ */
+#define I2S_FIFOCFG_PACK48(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
+#define I2S_FIFOCFG_SIZE_MASK                    (0x30U)
+#define I2S_FIFOCFG_SIZE_SHIFT                   (4U)
+/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16
+ *    entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
+ */
+#define I2S_FIFOCFG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)
+#define I2S_FIFOCFG_DMATX_MASK                   (0x1000U)
+#define I2S_FIFOCFG_DMATX_SHIFT                  (12U)
+/*! DMATX - DMA configuration for transmit.
+ *  0b0..DMA is not used for the transmit function.
+ *  0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define I2S_FIFOCFG_DMATX(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)
+#define I2S_FIFOCFG_DMARX_MASK                   (0x2000U)
+#define I2S_FIFOCFG_DMARX_SHIFT                  (13U)
+/*! DMARX - DMA configuration for receive.
+ *  0b0..DMA is not used for the receive function.
+ *  0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define I2S_FIFOCFG_DMARX(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)
+#define I2S_FIFOCFG_WAKETX_MASK                  (0x4000U)
+#define I2S_FIFOCFG_WAKETX_SHIFT                 (14U)
+/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power
+ *    modes (up to power-down, as long as the peripheral function works in that power mode) without
+ *    enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
+ *    CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
+ *    Wake-up control register.
+ *  0b0..Only enabled interrupts will wake up the device form reduced power modes.
+ *  0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
+ *       FIFOTRIG, even when the TXLVL interrupt is not enabled.
+ */
+#define I2S_FIFOCFG_WAKETX(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)
+#define I2S_FIFOCFG_WAKERX_MASK                  (0x8000U)
+#define I2S_FIFOCFG_WAKERX_SHIFT                 (15U)
+/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power
+ *    modes (up to power-down, as long as the peripheral function works in that power mode) without
+ *    enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
+ *    CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
+ *    Wake-up control register.
+ *  0b0..Only enabled interrupts will wake up the device form reduced power modes.
+ *  0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in
+ *       FIFOTRIG, even when the RXLVL interrupt is not enabled.
+ */
+#define I2S_FIFOCFG_WAKERX(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)
+#define I2S_FIFOCFG_EMPTYTX_MASK                 (0x10000U)
+#define I2S_FIFOCFG_EMPTYTX_SHIFT                (16U)
+/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
+ */
+#define I2S_FIFOCFG_EMPTYTX(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)
+#define I2S_FIFOCFG_EMPTYRX_MASK                 (0x20000U)
+#define I2S_FIFOCFG_EMPTYRX_SHIFT                (17U)
+/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
+ */
+#define I2S_FIFOCFG_EMPTYRX(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)
+/*! @} */
+
+/*! @name FIFOSTAT - FIFO status register. */
+/*! @{ */
+#define I2S_FIFOSTAT_TXERR_MASK                  (0x1U)
+#define I2S_FIFOSTAT_TXERR_SHIFT                 (0U)
+/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow
+ *    caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is
+ *    needed. Cleared by writing a 1 to this bit.
+ */
+#define I2S_FIFOSTAT_TXERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)
+#define I2S_FIFOSTAT_RXERR_MASK                  (0x2U)
+#define I2S_FIFOSTAT_RXERR_SHIFT                 (1U)
+/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA
+ *    not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.
+ */
+#define I2S_FIFOSTAT_RXERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)
+#define I2S_FIFOSTAT_PERINT_MASK                 (0x8U)
+#define I2S_FIFOSTAT_PERINT_SHIFT                (3U)
+/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted
+ *    an interrupt. The details can be found by reading the peripheral's STAT register.
+ */
+#define I2S_FIFOSTAT_PERINT(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)
+#define I2S_FIFOSTAT_TXEMPTY_MASK                (0x10U)
+#define I2S_FIFOSTAT_TXEMPTY_SHIFT               (4U)
+/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.
+ */
+#define I2S_FIFOSTAT_TXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)
+#define I2S_FIFOSTAT_TXNOTFULL_MASK              (0x20U)
+#define I2S_FIFOSTAT_TXNOTFULL_SHIFT             (5U)
+/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be
+ *    written. When 0, the transmit FIFO is full and another write would cause it to overflow.
+ */
+#define I2S_FIFOSTAT_TXNOTFULL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)
+#define I2S_FIFOSTAT_RXNOTEMPTY_MASK             (0x40U)
+#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT            (6U)
+/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.
+ */
+#define I2S_FIFOSTAT_RXNOTEMPTY(x)               (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)
+#define I2S_FIFOSTAT_RXFULL_MASK                 (0x80U)
+#define I2S_FIFOSTAT_RXFULL_SHIFT                (7U)
+/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to
+ *    prevent the peripheral from causing an overflow.
+ */
+#define I2S_FIFOSTAT_RXFULL(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)
+#define I2S_FIFOSTAT_TXLVL_MASK                  (0x1F00U)
+#define I2S_FIFOSTAT_TXLVL_SHIFT                 (8U)
+/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY
+ *    and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at
+ *    the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be
+ *    0.
+ */
+#define I2S_FIFOSTAT_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)
+#define I2S_FIFOSTAT_RXLVL_MASK                  (0x1F0000U)
+#define I2S_FIFOSTAT_RXLVL_SHIFT                 (16U)
+/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and
+ *    RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the
+ *    point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be
+ *    1.
+ */
+#define I2S_FIFOSTAT_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
+/*! @{ */
+#define I2S_FIFOTRIG_TXLVLENA_MASK               (0x1U)
+#define I2S_FIFOTRIG_TXLVLENA_SHIFT              (0U)
+/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled
+ *    in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
+ *  0b0..Transmit FIFO level does not generate a FIFO level trigger.
+ *  0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
+ */
+#define I2S_FIFOTRIG_TXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)
+#define I2S_FIFOTRIG_RXLVLENA_MASK               (0x2U)
+#define I2S_FIFOTRIG_RXLVLENA_SHIFT              (1U)
+/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled
+ *    in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.
+ *  0b0..Receive FIFO level does not generate a FIFO level trigger.
+ *  0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
+ */
+#define I2S_FIFOTRIG_RXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)
+#define I2S_FIFOTRIG_TXLVL_MASK                  (0xF00U)
+#define I2S_FIFOTRIG_TXLVL_SHIFT                 (8U)
+/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled
+ *    to do so, the FIFO level can wake up the device just enough to perform DMA, then return to
+ *    the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO
+ *    becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX
+ *    FIFO level decreases to 15 entries (is no longer full).
+ */
+#define I2S_FIFOTRIG_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)
+#define I2S_FIFOTRIG_RXLVL_MASK                  (0xF0000U)
+#define I2S_FIFOTRIG_RXLVL_SHIFT                 (16U)
+/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data
+ *    is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level
+ *    can wake up the device just enough to perform DMA, then return to the reduced power mode. See
+ *    Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no
+ *    longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX
+ *    FIFO has received 16 entries (has become full).
+ */
+#define I2S_FIFOTRIG_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
+/*! @{ */
+#define I2S_FIFOINTENSET_TXERR_MASK              (0x1U)
+#define I2S_FIFOINTENSET_TXERR_SHIFT             (0U)
+/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
+ *  0b0..No interrupt will be generated for a transmit error.
+ *  0b1..An interrupt will be generated when a transmit error occurs.
+ */
+#define I2S_FIFOINTENSET_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)
+#define I2S_FIFOINTENSET_RXERR_MASK              (0x2U)
+#define I2S_FIFOINTENSET_RXERR_SHIFT             (1U)
+/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.
+ *  0b0..No interrupt will be generated for a receive error.
+ *  0b1..An interrupt will be generated when a receive error occurs.
+ */
+#define I2S_FIFOINTENSET_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)
+#define I2S_FIFOINTENSET_TXLVL_MASK              (0x4U)
+#define I2S_FIFOINTENSET_TXLVL_SHIFT             (2U)
+/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level
+ *    specified by the TXLVL field in the FIFOTRIG register.
+ *  0b0..No interrupt will be generated based on the TX FIFO level.
+ *  0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases
+ *       to the level specified by TXLVL in the FIFOTRIG register.
+ */
+#define I2S_FIFOINTENSET_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)
+#define I2S_FIFOINTENSET_RXLVL_MASK              (0x8U)
+#define I2S_FIFOINTENSET_RXLVL_SHIFT             (3U)
+/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level
+ *    specified by the TXLVL field in the FIFOTRIG register.
+ *  0b0..No interrupt will be generated based on the RX FIFO level.
+ *  0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level
+ *       increases to the level specified by RXLVL in the FIFOTRIG register.
+ */
+#define I2S_FIFOINTENSET_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
+/*! @{ */
+#define I2S_FIFOINTENCLR_TXERR_MASK              (0x1U)
+#define I2S_FIFOINTENCLR_TXERR_SHIFT             (0U)
+/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define I2S_FIFOINTENCLR_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)
+#define I2S_FIFOINTENCLR_RXERR_MASK              (0x2U)
+#define I2S_FIFOINTENCLR_RXERR_SHIFT             (1U)
+/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define I2S_FIFOINTENCLR_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)
+#define I2S_FIFOINTENCLR_TXLVL_MASK              (0x4U)
+#define I2S_FIFOINTENCLR_TXLVL_SHIFT             (2U)
+/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define I2S_FIFOINTENCLR_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)
+#define I2S_FIFOINTENCLR_RXLVL_MASK              (0x8U)
+#define I2S_FIFOINTENCLR_RXLVL_SHIFT             (3U)
+/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define I2S_FIFOINTENCLR_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */
+/*! @{ */
+#define I2S_FIFOINTSTAT_TXERR_MASK               (0x1U)
+#define I2S_FIFOINTSTAT_TXERR_SHIFT              (0U)
+/*! TXERR - TX FIFO error.
+ */
+#define I2S_FIFOINTSTAT_TXERR(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)
+#define I2S_FIFOINTSTAT_RXERR_MASK               (0x2U)
+#define I2S_FIFOINTSTAT_RXERR_SHIFT              (1U)
+/*! RXERR - RX FIFO error.
+ */
+#define I2S_FIFOINTSTAT_RXERR(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)
+#define I2S_FIFOINTSTAT_TXLVL_MASK               (0x4U)
+#define I2S_FIFOINTSTAT_TXLVL_SHIFT              (2U)
+/*! TXLVL - Transmit FIFO level interrupt.
+ */
+#define I2S_FIFOINTSTAT_TXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)
+#define I2S_FIFOINTSTAT_RXLVL_MASK               (0x8U)
+#define I2S_FIFOINTSTAT_RXLVL_SHIFT              (3U)
+/*! RXLVL - Receive FIFO level interrupt.
+ */
+#define I2S_FIFOINTSTAT_RXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)
+#define I2S_FIFOINTSTAT_PERINT_MASK              (0x10U)
+#define I2S_FIFOINTSTAT_PERINT_SHIFT             (4U)
+/*! PERINT - Peripheral interrupt.
+ */
+#define I2S_FIFOINTSTAT_PERINT(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)
+/*! @} */
+
+/*! @name FIFOWR - FIFO write data. */
+/*! @{ */
+#define I2S_FIFOWR_TXDATA_MASK                   (0xFFFFFFFFU)
+#define I2S_FIFOWR_TXDATA_SHIFT                  (0U)
+/*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details.
+ */
+#define I2S_FIFOWR_TXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)
+/*! @} */
+
+/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
+/*! @{ */
+#define I2S_FIFOWR48H_TXDATA_MASK                (0xFFFFFFU)
+#define I2S_FIFOWR48H_TXDATA_SHIFT               (0U)
+/*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details.
+ */
+#define I2S_FIFOWR48H_TXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORD - FIFO read data. */
+/*! @{ */
+#define I2S_FIFORD_RXDATA_MASK                   (0xFFFFFFFFU)
+#define I2S_FIFORD_RXDATA_SHIFT                  (0U)
+/*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details.
+ */
+#define I2S_FIFORD_RXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
+/*! @{ */
+#define I2S_FIFORD48H_RXDATA_MASK                (0xFFFFFFU)
+#define I2S_FIFORD48H_RXDATA_SHIFT               (0U)
+/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details.
+ */
+#define I2S_FIFORD48H_RXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
+/*! @{ */
+#define I2S_FIFORDNOPOP_RXDATA_MASK              (0xFFFFFFFFU)
+#define I2S_FIFORDNOPOP_RXDATA_SHIFT             (0U)
+/*! RXDATA - Received data from the FIFO.
+ */
+#define I2S_FIFORDNOPOP_RXDATA(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
+/*! @{ */
+#define I2S_FIFORD48HNOPOP_RXDATA_MASK           (0xFFFFFFU)
+#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT          (0U)
+/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details.
+ */
+#define I2S_FIFORD48HNOPOP_RXDATA(x)             (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)
+/*! @} */
+
+/*! @name ID - I2S Module identification */
+/*! @{ */
+#define I2S_ID_Aperture_MASK                     (0xFFU)
+#define I2S_ID_Aperture_SHIFT                    (0U)
+/*! Aperture - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
+ */
+#define I2S_ID_Aperture(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK)
+#define I2S_ID_Minor_Rev_MASK                    (0xF00U)
+#define I2S_ID_Minor_Rev_SHIFT                   (8U)
+/*! Minor_Rev - Minor revision of module implementation, starting at 0.
+ */
+#define I2S_ID_Minor_Rev(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK)
+#define I2S_ID_Major_Rev_MASK                    (0xF000U)
+#define I2S_ID_Major_Rev_SHIFT                   (12U)
+/*! Major_Rev - Major revision of module implementation, starting at 0.
+ */
+#define I2S_ID_Major_Rev(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK)
+#define I2S_ID_ID_MASK                           (0xFFFF0000U)
+#define I2S_ID_ID_SHIFT                          (16U)
+/*! ID - Unique module identifier for this IP block.
+ */
+#define I2S_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x40097000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+/** Peripheral I2S1 base address */
+#define I2S1_BASE                                (0x40098000u)
+/** Peripheral I2S1 base pointer */
+#define I2S1                                     ((I2S_Type *)I2S1_BASE)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS                           { I2S0_BASE, I2S1_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS                            { I2S0, I2S1 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_IRQS                                 { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- INPUTMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
+ * @{
+ */
+
+/** INPUTMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SCT0_INMUX[7];                     /**< Trigger select register for DMA channel, array offset: 0x0, array step: 0x4 */
+       uint8_t RESERVED_0[164];
+  __IO uint32_t PINTSEL[8];                        /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */
+  __IO uint32_t DMA_ITRIG_INMUX[32];               /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */
+  __IO uint32_t DMA_OTRIG_INMUX[4];                /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t FREQMEAS_REF;                      /**< Selection for frequency measurement reference clock, offset: 0x180 */
+  __IO uint32_t FREQMEAS_TARGET;                   /**< Selection for frequency measurement target clock, offset: 0x184 */
+} INPUTMUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- INPUTMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
+ * @{
+ */
+
+/*! @name SCT0_INMUX - Trigger select register for DMA channel */
+/*! @{ */
+#define INPUTMUX_SCT0_INMUX_INP_N_MASK           (0x1FU)
+#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT          (0U)
+/*! INP_N - Input number to SCT0 inputs 0 to 6..
+ */
+#define INPUTMUX_SCT0_INMUX_INP_N(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_SCT0_INMUX */
+#define INPUTMUX_SCT0_INMUX_COUNT                (7U)
+
+/*! @name PINTSEL - Pin interrupt select register */
+/*! @{ */
+#define INPUTMUX_PINTSEL_INTPIN_MASK             (0xFFU)
+#define INPUTMUX_PINTSEL_INTPIN_SHIFT            (0U)
+/*! INTPIN - Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63).
+ */
+#define INPUTMUX_PINTSEL_INTPIN(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_PINTSEL */
+#define INPUTMUX_PINTSEL_COUNT                   (8U)
+
+/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */
+/*! @{ */
+#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK        (0x1FU)
+#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT       (0U)
+/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 31). 0 = ADC0 Sequence A
+ *    interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 =
+ *    Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match
+ *    0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer
+ *    CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin
+ *    interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2
+ *    19 = DMA output trigger mux 3
+ */
+#define INPUTMUX_DMA_ITRIG_INMUX_INP(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_DMA_ITRIG_INMUX */
+#define INPUTMUX_DMA_ITRIG_INMUX_COUNT           (32U)
+
+/*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */
+/*! @{ */
+#define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK        (0x1FU)
+#define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT       (0U)
+/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 19).
+ */
+#define INPUTMUX_DMA_OTRIG_INMUX_INP(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_DMA_OTRIG_INMUX */
+#define INPUTMUX_DMA_OTRIG_INMUX_COUNT           (4U)
+
+/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */
+/*! @{ */
+#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK         (0x1FU)
+#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT        (0U)
+/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 =
+ *    CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock
+ *    (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4
+ */
+#define INPUTMUX_FREQMEAS_REF_CLKIN(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK)
+/*! @} */
+
+/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */
+/*! @{ */
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK      (0x1FU)
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT     (0U)
+/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 =
+ *    CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock
+ *    (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4
+ */
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group INPUTMUX_Register_Masks */
+
+
+/* INPUTMUX - Peripheral instance base addresses */
+/** Peripheral INPUTMUX base address */
+#define INPUTMUX_BASE                            (0x40005000u)
+/** Peripheral INPUTMUX base pointer */
+#define INPUTMUX                                 ((INPUTMUX_Type *)INPUTMUX_BASE)
+/** Array initializer of INPUTMUX peripheral base addresses */
+#define INPUTMUX_BASE_ADDRS                      { INPUTMUX_BASE }
+/** Array initializer of INPUTMUX peripheral base pointers */
+#define INPUTMUX_BASE_PTRS                       { INPUTMUX }
+
+/*!
+ * @}
+ */ /* end of group INPUTMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- IOCON Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer
+ * @{
+ */
+
+/** IOCON - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PIO[6][32];                        /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31, array offset: 0x0, array step: index*0x80, index2*0x4 */
+} IOCON_Type;
+
+/* ----------------------------------------------------------------------------
+   -- IOCON Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IOCON_Register_Masks IOCON Register Masks
+ * @{
+ */
+
+/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31 */
+/*! @{ */
+#define IOCON_PIO_FUNC_MASK                      (0xFU)
+#define IOCON_PIO_FUNC_SHIFT                     (0U)
+/*! FUNC - Selects pin function.
+ *  0b0000..Alternative connection 0.
+ *  0b0001..Alternative connection 1.
+ *  0b0010..Alternative connection 2.
+ *  0b0011..Alternative connection 3.
+ *  0b0100..Alternative connection 4.
+ *  0b0101..Alternative connection 5.
+ *  0b0110..Alternative connection 6.
+ *  0b0111..Alternative connection 7.
+ *  0b1000..Alternative connection 8.
+ *  0b1001..Alternative connection 9.
+ *  0b1010..Alternative connection 10.
+ */
+#define IOCON_PIO_FUNC(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)
+#define IOCON_PIO_MODE_MASK                      (0x30U)
+#define IOCON_PIO_MODE_SHIFT                     (4U)
+/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control).
+ *  0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled).
+ *  0b01..Pull-down. Pull-down resistor enabled.
+ *  0b10..Pull-up. Pull-up resistor enabled.
+ *  0b11..Repeater. Repeater mode.
+ */
+#define IOCON_PIO_MODE(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
+#define IOCON_PIO_ANAMODE_MASK                   (0x40U)
+#define IOCON_PIO_ANAMODE_SHIFT                  (6U)
+/*! ANAMODE - Enables or disables analog mode.
+ *  0b0..Enable analog Mode.
+ *  0b1..Disable analog Mode.
+ */
+#define IOCON_PIO_ANAMODE(x)                     (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ANAMODE_SHIFT)) & IOCON_PIO_ANAMODE_MASK)
+#define IOCON_PIO_I2CSLEW_MASK                   (0x40U)
+#define IOCON_PIO_I2CSLEW_SHIFT                  (6U)
+/*! I2CSLEW - Controls slew rate of I2C pad.
+ *  0b0..I2C mode.
+ *  0b1..GPIO mode.
+ */
+#define IOCON_PIO_I2CSLEW(x)                     (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK)
+#define IOCON_PIO_INVERT_MASK                    (0x80U)
+#define IOCON_PIO_INVERT_SHIFT                   (7U)
+/*! INVERT - Input polarity.
+ *  0b0..Disabled. Input function is not inverted.
+ *  0b1..Enabled. Input is function inverted.
+ */
+#define IOCON_PIO_INVERT(x)                      (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK)
+#define IOCON_PIO_DIGIMODE_MASK                  (0x100U)
+#define IOCON_PIO_DIGIMODE_SHIFT                 (8U)
+/*! DIGIMODE - Select Analog/Digital mode.
+ *  0b0..Analog mode.
+ *  0b1..Digital mode.
+ */
+#define IOCON_PIO_DIGIMODE(x)                    (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)
+#define IOCON_PIO_FILTEROFF_MASK                 (0x200U)
+#define IOCON_PIO_FILTEROFF_SHIFT                (9U)
+/*! FILTEROFF - Controls input glitch filter.
+ *  0b0..Filter enabled. Noise pulses below approximately 10 ns are filtered out.
+ *  0b1..Filter disabled. No input filtering is done.
+ */
+#define IOCON_PIO_FILTEROFF(x)                   (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)
+#define IOCON_PIO_I2CDRIVE_MASK                  (0x400U)
+#define IOCON_PIO_I2CDRIVE_SHIFT                 (10U)
+/*! I2CDRIVE - Controls the current sink capability of the pin.
+ *  0b0..Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C.
+ *  0b1..High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate
+ *       specific device data sheet for details.
+ */
+#define IOCON_PIO_I2CDRIVE(x)                    (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK)
+#define IOCON_PIO_SLEW_MASK                      (0x400U)
+#define IOCON_PIO_SLEW_SHIFT                     (10U)
+/*! SLEW - Driver slew rate.
+ *  0b0..Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
+ *  0b1..Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
+ */
+#define IOCON_PIO_SLEW(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK)
+#define IOCON_PIO_I2CFILTEROFF_MASK              (0x800U)
+#define IOCON_PIO_I2CFILTEROFF_SHIFT             (11U)
+/*! I2CFILTEROFF - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.
+ *  0b0..Enabled. I2C 50 ns glitch filter enabled.
+ *  0b1..Disabled. I2C 50 ns glitch filter disabled.
+ */
+#define IOCON_PIO_I2CFILTEROFF(x)                (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTEROFF_SHIFT)) & IOCON_PIO_I2CFILTEROFF_MASK)
+#define IOCON_PIO_OD_MASK                        (0x800U)
+#define IOCON_PIO_OD_SHIFT                       (11U)
+/*! OD - Controls open-drain mode.
+ *  0b0..Normal. Normal push-pull output
+ *  0b1..Open-drain. Simulated open-drain output (high drive disabled).
+ */
+#define IOCON_PIO_OD(x)                          (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
+/*! @} */
+
+/* The count of IOCON_PIO */
+#define IOCON_PIO_COUNT                          (6U)
+
+/* The count of IOCON_PIO */
+#define IOCON_PIO_COUNT2                         (32U)
+
+
+/*!
+ * @}
+ */ /* end of group IOCON_Register_Masks */
+
+
+/* IOCON - Peripheral instance base addresses */
+/** Peripheral IOCON base address */
+#define IOCON_BASE                               (0x40001000u)
+/** Peripheral IOCON base pointer */
+#define IOCON                                    ((IOCON_Type *)IOCON_BASE)
+/** Array initializer of IOCON peripheral base addresses */
+#define IOCON_BASE_ADDRS                         { IOCON_BASE }
+/** Array initializer of IOCON peripheral base pointers */
+#define IOCON_BASE_PTRS                          { IOCON }
+
+/*!
+ * @}
+ */ /* end of group IOCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MRT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
+ * @{
+ */
+
+/** MRT - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x10 */
+    __IO uint32_t INTVAL;                            /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */
+    __I  uint32_t TIMER;                             /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */
+    __IO uint32_t CTRL;                              /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */
+    __IO uint32_t STAT;                              /**< MRT Status register., array offset: 0xC, array step: 0x10 */
+  } CHANNEL[4];
+       uint8_t RESERVED_0[176];
+  __IO uint32_t MODCFG;                            /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */
+  __I  uint32_t IDLE_CH;                           /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */
+  __IO uint32_t IRQ_FLAG;                          /**< Global interrupt flag register, offset: 0xF8 */
+} MRT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MRT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MRT_Register_Masks MRT Register Masks
+ * @{
+ */
+
+/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */
+/*! @{ */
+#define MRT_CHANNEL_INTVAL_IVALUE_MASK           (0xFFFFFFU)
+#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT          (0U)
+/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT
+ *    channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to
+ *    this bit field starts the timer immediately. If the timer is running, writing a zero to this
+ *    bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer
+ *    stops at the end of the time interval.
+ */
+#define MRT_CHANNEL_INTVAL_IVALUE(x)             (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
+#define MRT_CHANNEL_INTVAL_LOAD_MASK             (0x80000000U)
+#define MRT_CHANNEL_INTVAL_LOAD_SHIFT            (31U)
+/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register.
+ *    This bit is write-only. Reading this bit always returns 0.
+ *  0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the
+ *       time interval if the repeat mode is selected.
+ *  0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
+ */
+#define MRT_CHANNEL_INTVAL_LOAD(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
+/*! @} */
+
+/* The count of MRT_CHANNEL_INTVAL */
+#define MRT_CHANNEL_INTVAL_COUNT                 (4U)
+
+/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */
+/*! @{ */
+#define MRT_CHANNEL_TIMER_VALUE_MASK             (0xFFFFFFU)
+#define MRT_CHANNEL_TIMER_VALUE_SHIFT            (0U)
+/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn
+ *    register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval
+ *    or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn
+ *    register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields
+ *    returns -1 (0x00FF FFFF).
+ */
+#define MRT_CHANNEL_TIMER_VALUE(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
+/*! @} */
+
+/* The count of MRT_CHANNEL_TIMER */
+#define MRT_CHANNEL_TIMER_COUNT                  (4U)
+
+/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */
+/*! @{ */
+#define MRT_CHANNEL_CTRL_INTEN_MASK              (0x1U)
+#define MRT_CHANNEL_CTRL_INTEN_SHIFT             (0U)
+/*! INTEN - Enable the TIMERn interrupt.
+ *  0b0..Disabled. TIMERn interrupt is disabled.
+ *  0b1..Enabled. TIMERn interrupt is enabled.
+ */
+#define MRT_CHANNEL_CTRL_INTEN(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
+#define MRT_CHANNEL_CTRL_MODE_MASK               (0x6U)
+#define MRT_CHANNEL_CTRL_MODE_SHIFT              (1U)
+/*! MODE - Selects timer mode.
+ *  0b00..Repeat interrupt mode.
+ *  0b01..One-shot interrupt mode.
+ *  0b10..One-shot stall mode.
+ *  0b11..Reserved.
+ */
+#define MRT_CHANNEL_CTRL_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
+/*! @} */
+
+/* The count of MRT_CHANNEL_CTRL */
+#define MRT_CHANNEL_CTRL_COUNT                   (4U)
+
+/*! @name CHANNEL_STAT - MRT Status register. */
+/*! @{ */
+#define MRT_CHANNEL_STAT_INTFLAG_MASK            (0x1U)
+#define MRT_CHANNEL_STAT_INTFLAG_SHIFT           (0U)
+/*! INTFLAG - Monitors the interrupt flag.
+ *  0b0..No pending interrupt. Writing a zero is equivalent to no operation.
+ *  0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If
+ *       the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt
+ *       are raised. Writing a 1 to this bit clears the interrupt request.
+ */
+#define MRT_CHANNEL_STAT_INTFLAG(x)              (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
+#define MRT_CHANNEL_STAT_RUN_MASK                (0x2U)
+#define MRT_CHANNEL_STAT_RUN_SHIFT               (1U)
+/*! RUN - Indicates the state of TIMERn. This bit is read-only.
+ *  0b0..Idle state. TIMERn is stopped.
+ *  0b1..Running. TIMERn is running.
+ */
+#define MRT_CHANNEL_STAT_RUN(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
+#define MRT_CHANNEL_STAT_INUSE_MASK              (0x4U)
+#define MRT_CHANNEL_STAT_INUSE_SHIFT             (2U)
+/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG
+ *    register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating
+ *    modes.
+ *  0b0..This channel is not in use.
+ *  0b1..This channel is in use.
+ */
+#define MRT_CHANNEL_STAT_INUSE(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
+/*! @} */
+
+/* The count of MRT_CHANNEL_STAT */
+#define MRT_CHANNEL_STAT_COUNT                   (4U)
+
+/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */
+/*! @{ */
+#define MRT_MODCFG_NOC_MASK                      (0xFU)
+#define MRT_MODCFG_NOC_SHIFT                     (0U)
+/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.)
+ */
+#define MRT_MODCFG_NOC(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
+#define MRT_MODCFG_NOB_MASK                      (0x1F0U)
+#define MRT_MODCFG_NOB_SHIFT                     (4U)
+/*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.)
+ */
+#define MRT_MODCFG_NOB(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
+#define MRT_MODCFG_MULTITASK_MASK                (0x80000000U)
+#define MRT_MODCFG_MULTITASK_SHIFT               (31U)
+/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register.
+ *  0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset.
+ *  0b1..Multi-task mode.
+ */
+#define MRT_MODCFG_MULTITASK(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
+/*! @} */
+
+/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */
+/*! @{ */
+#define MRT_IDLE_CH_CHAN_MASK                    (0xF0U)
+#define MRT_IDLE_CH_CHAN_SHIFT                   (4U)
+/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is
+ *    positioned such that it can be used as an offset from the MRT base address in order to access
+ *    the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See
+ *    text above for more details.
+ */
+#define MRT_IDLE_CH_CHAN(x)                      (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
+/*! @} */
+
+/*! @name IRQ_FLAG - Global interrupt flag register */
+/*! @{ */
+#define MRT_IRQ_FLAG_GFLAG0_MASK                 (0x1U)
+#define MRT_IRQ_FLAG_GFLAG0_SHIFT                (0U)
+/*! GFLAG0 - Monitors the interrupt flag of TIMER0.
+ *  0b0..No pending interrupt. Writing a zero is equivalent to no operation.
+ *  0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If
+ *       the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global
+ *       interrupt are raised. Writing a 1 to this bit clears the interrupt request.
+ */
+#define MRT_IRQ_FLAG_GFLAG0(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
+#define MRT_IRQ_FLAG_GFLAG1_MASK                 (0x2U)
+#define MRT_IRQ_FLAG_GFLAG1_SHIFT                (1U)
+/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0.
+ */
+#define MRT_IRQ_FLAG_GFLAG1(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
+#define MRT_IRQ_FLAG_GFLAG2_MASK                 (0x4U)
+#define MRT_IRQ_FLAG_GFLAG2_SHIFT                (2U)
+/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0.
+ */
+#define MRT_IRQ_FLAG_GFLAG2(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
+#define MRT_IRQ_FLAG_GFLAG3_MASK                 (0x8U)
+#define MRT_IRQ_FLAG_GFLAG3_SHIFT                (3U)
+/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0.
+ */
+#define MRT_IRQ_FLAG_GFLAG3(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MRT_Register_Masks */
+
+
+/* MRT - Peripheral instance base addresses */
+/** Peripheral MRT0 base address */
+#define MRT0_BASE                                (0x4000D000u)
+/** Peripheral MRT0 base pointer */
+#define MRT0                                     ((MRT_Type *)MRT0_BASE)
+/** Array initializer of MRT peripheral base addresses */
+#define MRT_BASE_ADDRS                           { MRT0_BASE }
+/** Array initializer of MRT peripheral base pointers */
+#define MRT_BASE_PTRS                            { MRT0 }
+/** Interrupt vectors for the MRT peripheral type */
+#define MRT_IRQS                                 { MRT0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group MRT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OTPC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OTPC_Peripheral_Access_Layer OTPC Peripheral Access Layer
+ * @{
+ */
+
+/** OTPC - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[16];
+  __I  uint32_t AESKEY[8];                         /**< Register for reading the AES key., array offset: 0x10, array step: 0x4 */
+  __I  uint32_t ECRP;                              /**< ECRP options., offset: 0x30 */
+       uint8_t RESERVED_1[4];
+  __I  uint32_t USER0;                             /**< User application specific options., offset: 0x38 */
+  __I  uint32_t USER1;                             /**< User application specific options., offset: 0x3C */
+} OTPC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- OTPC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OTPC_Register_Masks OTPC Register Masks
+ * @{
+ */
+
+/*! @name AESKEY - Register for reading the AES key. */
+/*! @{ */
+#define OTPC_AESKEY_KEY_MASK                     (0xFFFFFFFFU)
+#define OTPC_AESKEY_KEY_SHIFT                    (0U)
+/*! KEY - AES key.
+ */
+#define OTPC_AESKEY_KEY(x)                       (((uint32_t)(((uint32_t)(x)) << OTPC_AESKEY_KEY_SHIFT)) & OTPC_AESKEY_KEY_MASK)
+/*! @} */
+
+/* The count of OTPC_AESKEY */
+#define OTPC_AESKEY_COUNT                        (8U)
+
+/*! @name ECRP - ECRP options. */
+/*! @{ */
+#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK    (0x10U)
+#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT   (4U)
+/*! CRP_MASS_ERASE_DISABLE - Disable or enable CRP mass erase.
+ */
+#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE(x)      (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT)) & OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK)
+#define OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK     (0x20U)
+#define OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT    (5U)
+/*! IAP_PROTECTION_ENABLE - This bit controls the ability to enable checking for ECRP in IAP functions.
+ */
+#define OTPC_ECRP_IAP_PROTECTION_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT)) & OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK)
+#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK       (0x40U)
+#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT      (6U)
+/*! CRP_ISP_DISABLE_PIN - This bit controls the ability to enter ISP mode using the ISP pin.
+ */
+#define OTPC_ECRP_CRP_ISP_DISABLE_PIN(x)         (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK)
+#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK       (0x80U)
+#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT      (7U)
+/*! CRP_ISP_DISABLE_IAP - This bit controls the ability to re-invoke ISP using IAP routines.
+ */
+#define OTPC_ECRP_CRP_ISP_DISABLE_IAP(x)         (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK)
+#define OTPC_ECRP_CRP_ALLOW_ZERO_MASK            (0x200U)
+#define OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT           (9U)
+/*! CRP_ALLOW_ZERO - This bit controls how 0 is treated when read as a ECRP value..
+ */
+#define OTPC_ECRP_CRP_ALLOW_ZERO(x)              (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT)) & OTPC_ECRP_CRP_ALLOW_ZERO_MASK)
+#define OTPC_ECRP_JTAG_DISABLE_MASK              (0x80000000U)
+#define OTPC_ECRP_JTAG_DISABLE_SHIFT             (31U)
+/*! JTAG_DISABLE - 0 => Enable SWD/JTAG; 1 => Disable SWD/JTAG..
+ */
+#define OTPC_ECRP_JTAG_DISABLE(x)                (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_JTAG_DISABLE_SHIFT)) & OTPC_ECRP_JTAG_DISABLE_MASK)
+/*! @} */
+
+/*! @name USER0 - User application specific options. */
+/*! @{ */
+#define OTPC_USER0_USER0_MASK                    (0xFFFFFFFFU)
+#define OTPC_USER0_USER0_SHIFT                   (0U)
+/*! USER0 - User application specific option.
+ */
+#define OTPC_USER0_USER0(x)                      (((uint32_t)(((uint32_t)(x)) << OTPC_USER0_USER0_SHIFT)) & OTPC_USER0_USER0_MASK)
+/*! @} */
+
+/*! @name USER1 - User application specific options. */
+/*! @{ */
+#define OTPC_USER1_USER1_MASK                    (0xFFFFFFFFU)
+#define OTPC_USER1_USER1_SHIFT                   (0U)
+/*! USER1 - User application specific option.
+ */
+#define OTPC_USER1_USER1(x)                      (((uint32_t)(((uint32_t)(x)) << OTPC_USER1_USER1_SHIFT)) & OTPC_USER1_USER1_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group OTPC_Register_Masks */
+
+
+/* OTPC - Peripheral instance base addresses */
+/** Peripheral OTPC base address */
+#define OTPC_BASE                                (0x40015000u)
+/** Peripheral OTPC base pointer */
+#define OTPC                                     ((OTPC_Type *)OTPC_BASE)
+/** Array initializer of OTPC peripheral base addresses */
+#define OTPC_BASE_ADDRS                          { OTPC_BASE }
+/** Array initializer of OTPC peripheral base pointers */
+#define OTPC_BASE_PTRS                           { OTPC }
+
+/*!
+ * @}
+ */ /* end of group OTPC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PINT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
+ * @{
+ */
+
+/** PINT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t ISEL;                              /**< Pin Interrupt Mode register, offset: 0x0 */
+  __IO uint32_t IENR;                              /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */
+  __O  uint32_t SIENR;                             /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */
+  __O  uint32_t CIENR;                             /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */
+  __IO uint32_t IENF;                              /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */
+  __O  uint32_t SIENF;                             /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */
+  __O  uint32_t CIENF;                             /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */
+  __IO uint32_t RISE;                              /**< Pin interrupt rising edge register, offset: 0x1C */
+  __IO uint32_t FALL;                              /**< Pin interrupt falling edge register, offset: 0x20 */
+  __IO uint32_t IST;                               /**< Pin interrupt status register, offset: 0x24 */
+  __IO uint32_t PMCTRL;                            /**< Pattern match interrupt control register, offset: 0x28 */
+  __IO uint32_t PMSRC;                             /**< Pattern match interrupt bit-slice source register, offset: 0x2C */
+  __IO uint32_t PMCFG;                             /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */
+} PINT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PINT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PINT_Register_Masks PINT Register Masks
+ * @{
+ */
+
+/*! @name ISEL - Pin Interrupt Mode register */
+/*! @{ */
+#define PINT_ISEL_PMODE_MASK                     (0xFFU)
+#define PINT_ISEL_PMODE_SHIFT                    (0U)
+/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt
+ *    selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive
+ */
+#define PINT_ISEL_PMODE(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
+/*! @} */
+
+/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */
+/*! @{ */
+#define PINT_IENR_ENRL_MASK                      (0xFFU)
+#define PINT_IENR_ENRL_SHIFT                     (0U)
+/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the
+ *    pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable
+ *    rising edge or level interrupt.
+ */
+#define PINT_IENR_ENRL(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
+/*! @} */
+
+/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */
+/*! @{ */
+#define PINT_SIENR_SETENRL_MASK                  (0xFFU)
+#define PINT_SIENR_SETENRL_SHIFT                 (0U)
+/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n
+ *    sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.
+ */
+#define PINT_SIENR_SETENRL(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
+/*! @} */
+
+/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */
+/*! @{ */
+#define PINT_CIENR_CENRL_MASK                    (0xFFU)
+#define PINT_CIENR_CENRL_SHIFT                   (0U)
+/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit
+ *    n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level
+ *    interrupt.
+ */
+#define PINT_CIENR_CENRL(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
+/*! @} */
+
+/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */
+/*! @{ */
+#define PINT_IENF_ENAF_MASK                      (0xFFU)
+#define PINT_IENF_ENAF_SHIFT                     (0U)
+/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt.
+ *    Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt
+ *    or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active
+ *    interrupt level HIGH.
+ */
+#define PINT_IENF_ENAF(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
+/*! @} */
+
+/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */
+/*! @{ */
+#define PINT_SIENF_SETENAF_MASK                  (0xFFU)
+#define PINT_SIENF_SETENAF_SHIFT                 (0U)
+/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n
+ *    sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable
+ *    falling edge interrupt.
+ */
+#define PINT_SIENF_SETENAF(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
+/*! @} */
+
+/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */
+/*! @{ */
+#define PINT_CIENF_CENAF_MASK                    (0xFFU)
+#define PINT_CIENF_CENAF_SHIFT                   (0U)
+/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n
+ *    clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or
+ *    falling edge interrupt disabled.
+ */
+#define PINT_CIENF_CENAF(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
+/*! @} */
+
+/*! @name RISE - Pin interrupt rising edge register */
+/*! @{ */
+#define PINT_RISE_RDET_MASK                      (0xFFU)
+#define PINT_RISE_RDET_SHIFT                     (0U)
+/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read
+ *    0: No rising edge has been detected on this pin since Reset or the last time a one was written
+ *    to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the
+ *    last time a one was written to this bit. Write 1: clear rising edge detection for this pin.
+ */
+#define PINT_RISE_RDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
+/*! @} */
+
+/*! @name FALL - Pin interrupt falling edge register */
+/*! @{ */
+#define PINT_FALL_FDET_MASK                      (0xFFU)
+#define PINT_FALL_FDET_SHIFT                     (0U)
+/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read
+ *    0: No falling edge has been detected on this pin since Reset or the last time a one was
+ *    written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or
+ *    the last time a one was written to this bit. Write 1: clear falling edge detection for this
+ *    pin.
+ */
+#define PINT_FALL_FDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
+/*! @} */
+
+/*! @name IST - Pin interrupt status register */
+/*! @{ */
+#define PINT_IST_PSTAT_MASK                      (0xFFU)
+#define PINT_IST_PSTAT_SHIFT                     (0U)
+/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts
+ *    the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for
+ *    this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this
+ *    interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin.
+ *    Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).
+ */
+#define PINT_IST_PSTAT(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
+/*! @} */
+
+/*! @name PMCTRL - Pattern match interrupt control register */
+/*! @{ */
+#define PINT_PMCTRL_SEL_PMATCH_MASK              (0x1U)
+#define PINT_PMCTRL_SEL_PMATCH_SHIFT             (0U)
+/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.
+ *  0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.
+ *  0b1..Pattern match. Interrupts are driven in response to pattern matches.
+ */
+#define PINT_PMCTRL_SEL_PMATCH(x)                (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
+#define PINT_PMCTRL_ENA_RXEV_MASK                (0x2U)
+#define PINT_PMCTRL_ENA_RXEV_SHIFT               (1U)
+/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.
+ *  0b0..Disabled. RXEV output to the CPU is disabled.
+ *  0b1..Enabled. RXEV output to the CPU is enabled.
+ */
+#define PINT_PMCTRL_ENA_RXEV(x)                  (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
+#define PINT_PMCTRL_PMAT_MASK                    (0xFF000000U)
+#define PINT_PMCTRL_PMAT_SHIFT                   (24U)
+/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field
+ *    indicates that the corresponding product term is matched by the current state of the appropriate
+ *    inputs.
+ */
+#define PINT_PMCTRL_PMAT(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
+/*! @} */
+
+/*! @name PMSRC - Pattern match interrupt bit-slice source register */
+/*! @{ */
+#define PINT_PMSRC_SRC0_MASK                     (0x700U)
+#define PINT_PMSRC_SRC0_SHIFT                    (8U)
+/*! SRC0 - Selects the input source for bit slice 0
+ *  0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.
+ *  0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0.
+ *  0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0.
+ *  0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0.
+ *  0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0.
+ *  0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0.
+ *  0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0.
+ *  0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0.
+ */
+#define PINT_PMSRC_SRC0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
+#define PINT_PMSRC_SRC1_MASK                     (0x3800U)
+#define PINT_PMSRC_SRC1_SHIFT                    (11U)
+/*! SRC1 - Selects the input source for bit slice 1
+ *  0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.
+ *  0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1.
+ *  0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1.
+ *  0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1.
+ *  0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1.
+ *  0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1.
+ *  0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1.
+ *  0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1.
+ */
+#define PINT_PMSRC_SRC1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
+#define PINT_PMSRC_SRC2_MASK                     (0x1C000U)
+#define PINT_PMSRC_SRC2_SHIFT                    (14U)
+/*! SRC2 - Selects the input source for bit slice 2
+ *  0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.
+ *  0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2.
+ *  0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2.
+ *  0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2.
+ *  0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2.
+ *  0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2.
+ *  0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2.
+ *  0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2.
+ */
+#define PINT_PMSRC_SRC2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
+#define PINT_PMSRC_SRC3_MASK                     (0xE0000U)
+#define PINT_PMSRC_SRC3_SHIFT                    (17U)
+/*! SRC3 - Selects the input source for bit slice 3
+ *  0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3.
+ *  0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3.
+ *  0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3.
+ *  0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3.
+ *  0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3.
+ *  0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3.
+ *  0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3.
+ *  0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3.
+ */
+#define PINT_PMSRC_SRC3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
+#define PINT_PMSRC_SRC4_MASK                     (0x700000U)
+#define PINT_PMSRC_SRC4_SHIFT                    (20U)
+/*! SRC4 - Selects the input source for bit slice 4
+ *  0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.
+ *  0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4.
+ *  0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4.
+ *  0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4.
+ *  0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4.
+ *  0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4.
+ *  0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4.
+ *  0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4.
+ */
+#define PINT_PMSRC_SRC4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
+#define PINT_PMSRC_SRC5_MASK                     (0x3800000U)
+#define PINT_PMSRC_SRC5_SHIFT                    (23U)
+/*! SRC5 - Selects the input source for bit slice 5
+ *  0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.
+ *  0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5.
+ *  0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5.
+ *  0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5.
+ *  0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5.
+ *  0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5.
+ *  0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5.
+ *  0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5.
+ */
+#define PINT_PMSRC_SRC5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
+#define PINT_PMSRC_SRC6_MASK                     (0x1C000000U)
+#define PINT_PMSRC_SRC6_SHIFT                    (26U)
+/*! SRC6 - Selects the input source for bit slice 6
+ *  0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.
+ *  0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6.
+ *  0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6.
+ *  0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6.
+ *  0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6.
+ *  0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6.
+ *  0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6.
+ *  0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6.
+ */
+#define PINT_PMSRC_SRC6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
+#define PINT_PMSRC_SRC7_MASK                     (0xE0000000U)
+#define PINT_PMSRC_SRC7_SHIFT                    (29U)
+/*! SRC7 - Selects the input source for bit slice 7
+ *  0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7.
+ *  0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7.
+ *  0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7.
+ *  0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7.
+ *  0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7.
+ *  0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7.
+ *  0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7.
+ *  0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7.
+ */
+#define PINT_PMSRC_SRC7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
+/*! @} */
+
+/*! @name PMCFG - Pattern match interrupt bit slice configuration register */
+/*! @{ */
+#define PINT_PMCFG_PROD_ENDPTS0_MASK             (0x1U)
+#define PINT_PMCFG_PROD_ENDPTS0_SHIFT            (0U)
+/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint.
+ *  0b0..No effect. Slice 0 is not an endpoint.
+ *  0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS0(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
+#define PINT_PMCFG_PROD_ENDPTS1_MASK             (0x2U)
+#define PINT_PMCFG_PROD_ENDPTS1_SHIFT            (1U)
+/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint.
+ *  0b0..No effect. Slice 1 is not an endpoint.
+ *  0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS1(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
+#define PINT_PMCFG_PROD_ENDPTS2_MASK             (0x4U)
+#define PINT_PMCFG_PROD_ENDPTS2_SHIFT            (2U)
+/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint.
+ *  0b0..No effect. Slice 2 is not an endpoint.
+ *  0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS2(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
+#define PINT_PMCFG_PROD_ENDPTS3_MASK             (0x8U)
+#define PINT_PMCFG_PROD_ENDPTS3_SHIFT            (3U)
+/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint.
+ *  0b0..No effect. Slice 3 is not an endpoint.
+ *  0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS3(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
+#define PINT_PMCFG_PROD_ENDPTS4_MASK             (0x10U)
+#define PINT_PMCFG_PROD_ENDPTS4_SHIFT            (4U)
+/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint.
+ *  0b0..No effect. Slice 4 is not an endpoint.
+ *  0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS4(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
+#define PINT_PMCFG_PROD_ENDPTS5_MASK             (0x20U)
+#define PINT_PMCFG_PROD_ENDPTS5_SHIFT            (5U)
+/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint.
+ *  0b0..No effect. Slice 5 is not an endpoint.
+ *  0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS5(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
+#define PINT_PMCFG_PROD_ENDPTS6_MASK             (0x40U)
+#define PINT_PMCFG_PROD_ENDPTS6_SHIFT            (6U)
+/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint.
+ *  0b0..No effect. Slice 6 is not an endpoint.
+ *  0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS6(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
+#define PINT_PMCFG_CFG0_MASK                     (0x700U)
+#define PINT_PMCFG_CFG0_SHIFT                    (8U)
+/*! CFG0 - Specifies the match contribution condition for bit slice 0.
+ *  0b000..Constant HIGH. This bit slice always contributes to a product term match.
+ *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ *         PMSRC registers are written to.
+ *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ *         PMSRC registers are written to.
+ *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ *         has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
+ *         cleared when the PMCFG or the PMSRC registers are written to.
+ *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ *  0b101..Low level. Match occurs when there is a low level on the specified input.
+ *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
+ *         falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
+ *         is cleared after one clock cycle.
+ */
+#define PINT_PMCFG_CFG0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
+#define PINT_PMCFG_CFG1_MASK                     (0x3800U)
+#define PINT_PMCFG_CFG1_SHIFT                    (11U)
+/*! CFG1 - Specifies the match contribution condition for bit slice 1.
+ *  0b000..Constant HIGH. This bit slice always contributes to a product term match.
+ *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ *         PMSRC registers are written to.
+ *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ *         PMSRC registers are written to.
+ *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ *         has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
+ *         cleared when the PMCFG or the PMSRC registers are written to.
+ *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ *  0b101..Low level. Match occurs when there is a low level on the specified input.
+ *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
+ *         falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
+ *         is cleared after one clock cycle.
+ */
+#define PINT_PMCFG_CFG1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
+#define PINT_PMCFG_CFG2_MASK                     (0x1C000U)
+#define PINT_PMCFG_CFG2_SHIFT                    (14U)
+/*! CFG2 - Specifies the match contribution condition for bit slice 2.
+ *  0b000..Constant HIGH. This bit slice always contributes to a product term match.
+ *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ *         PMSRC registers are written to.
+ *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ *         PMSRC registers are written to.
+ *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ *         has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
+ *         cleared when the PMCFG or the PMSRC registers are written to.
+ *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ *  0b101..Low level. Match occurs when there is a low level on the specified input.
+ *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
+ *         falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
+ *         is cleared after one clock cycle.
+ */
+#define PINT_PMCFG_CFG2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
+#define PINT_PMCFG_CFG3_MASK                     (0xE0000U)
+#define PINT_PMCFG_CFG3_SHIFT                    (17U)
+/*! CFG3 - Specifies the match contribution condition for bit slice 3.
+ *  0b000..Constant HIGH. This bit slice always contributes to a product term match.
+ *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ *         PMSRC registers are written to.
+ *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ *         PMSRC registers are written to.
+ *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ *         has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
+ *         cleared when the PMCFG or the PMSRC registers are written to.
+ *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ *  0b101..Low level. Match occurs when there is a low level on the specified input.
+ *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
+ *         falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
+ *         is cleared after one clock cycle.
+ */
+#define PINT_PMCFG_CFG3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
+#define PINT_PMCFG_CFG4_MASK                     (0x700000U)
+#define PINT_PMCFG_CFG4_SHIFT                    (20U)
+/*! CFG4 - Specifies the match contribution condition for bit slice 4.
+ *  0b000..Constant HIGH. This bit slice always contributes to a product term match.
+ *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ *         PMSRC registers are written to.
+ *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ *         PMSRC registers are written to.
+ *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ *         has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
+ *         cleared when the PMCFG or the PMSRC registers are written to.
+ *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ *  0b101..Low level. Match occurs when there is a low level on the specified input.
+ *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
+ *         falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
+ *         is cleared after one clock cycle.
+ */
+#define PINT_PMCFG_CFG4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
+#define PINT_PMCFG_CFG5_MASK                     (0x3800000U)
+#define PINT_PMCFG_CFG5_SHIFT                    (23U)
+/*! CFG5 - Specifies the match contribution condition for bit slice 5.
+ *  0b000..Constant HIGH. This bit slice always contributes to a product term match.
+ *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ *         PMSRC registers are written to.
+ *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ *         PMSRC registers are written to.
+ *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ *         has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
+ *         cleared when the PMCFG or the PMSRC registers are written to.
+ *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ *  0b101..Low level. Match occurs when there is a low level on the specified input.
+ *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
+ *         falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
+ *         is cleared after one clock cycle.
+ */
+#define PINT_PMCFG_CFG5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
+#define PINT_PMCFG_CFG6_MASK                     (0x1C000000U)
+#define PINT_PMCFG_CFG6_SHIFT                    (26U)
+/*! CFG6 - Specifies the match contribution condition for bit slice 6.
+ *  0b000..Constant HIGH. This bit slice always contributes to a product term match.
+ *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ *         PMSRC registers are written to.
+ *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ *         PMSRC registers are written to.
+ *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ *         has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
+ *         cleared when the PMCFG or the PMSRC registers are written to.
+ *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ *  0b101..Low level. Match occurs when there is a low level on the specified input.
+ *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
+ *         falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
+ *         is cleared after one clock cycle.
+ */
+#define PINT_PMCFG_CFG6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
+#define PINT_PMCFG_CFG7_MASK                     (0xE0000000U)
+#define PINT_PMCFG_CFG7_SHIFT                    (29U)
+/*! CFG7 - Specifies the match contribution condition for bit slice 7.
+ *  0b000..Constant HIGH. This bit slice always contributes to a product term match.
+ *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ *         PMSRC registers are written to.
+ *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ *         PMSRC registers are written to.
+ *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ *         has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
+ *         cleared when the PMCFG or the PMSRC registers are written to.
+ *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ *  0b101..Low level. Match occurs when there is a low level on the specified input.
+ *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
+ *         falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
+ *         is cleared after one clock cycle.
+ */
+#define PINT_PMCFG_CFG7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PINT_Register_Masks */
+
+
+/* PINT - Peripheral instance base addresses */
+/** Peripheral PINT base address */
+#define PINT_BASE                                (0x40004000u)
+/** Peripheral PINT base pointer */
+#define PINT                                     ((PINT_Type *)PINT_BASE)
+/** Array initializer of PINT peripheral base addresses */
+#define PINT_BASE_ADDRS                          { PINT_BASE }
+/** Array initializer of PINT peripheral base pointers */
+#define PINT_BASE_PTRS                           { PINT }
+/** Interrupt vectors for the PINT peripheral type */
+#define PINT_IRQS                                { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PINT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RIT_Peripheral_Access_Layer RIT Peripheral Access Layer
+ * @{
+ */
+
+/** RIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t COMPVAL;                           /**< Compare value LSB register, offset: 0x0 */
+  __IO uint32_t MASK;                              /**< Mask LSB register, offset: 0x4 */
+  __IO uint32_t CTRL;                              /**< Control register, offset: 0x8 */
+  __IO uint32_t COUNTER;                           /**< Counter LSB register, offset: 0xC */
+  __IO uint32_t COMPVAL_H;                         /**< Compare value MSB register, offset: 0x10 */
+  __IO uint32_t MASK_H;                            /**< Mask MSB register, offset: 0x14 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t COUNTER_H;                         /**< Counter MSB register, offset: 0x1C */
+} RIT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RIT_Register_Masks RIT Register Masks
+ * @{
+ */
+
+/*! @name COMPVAL - Compare value LSB register */
+/*! @{ */
+#define RIT_COMPVAL_RICOMP_MASK                  (0xFFFFFFFFU)
+#define RIT_COMPVAL_RICOMP_SHIFT                 (0U)
+/*! RICOMP - .
+ */
+#define RIT_COMPVAL_RICOMP(x)                    (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_RICOMP_SHIFT)) & RIT_COMPVAL_RICOMP_MASK)
+/*! @} */
+
+/*! @name MASK - Mask LSB register */
+/*! @{ */
+#define RIT_MASK_RIMASK_MASK                     (0xFFFFFFFFU)
+#define RIT_MASK_RIMASK_SHIFT                    (0U)
+/*! RIMASK - Mask register.
+ */
+#define RIT_MASK_RIMASK(x)                       (((uint32_t)(((uint32_t)(x)) << RIT_MASK_RIMASK_SHIFT)) & RIT_MASK_RIMASK_MASK)
+/*! @} */
+
+/*! @name CTRL - Control register */
+/*! @{ */
+#define RIT_CTRL_RITINT_MASK                     (0x1U)
+#define RIT_CTRL_RITINT_SHIFT                    (0U)
+/*! RITINT - Interrupt flag.
+ */
+#define RIT_CTRL_RITINT(x)                       (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITINT_SHIFT)) & RIT_CTRL_RITINT_MASK)
+#define RIT_CTRL_RITENCLR_MASK                   (0x2U)
+#define RIT_CTRL_RITENCLR_SHIFT                  (1U)
+/*! RITENCLR - Timer enable clear.
+ */
+#define RIT_CTRL_RITENCLR(x)                     (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENCLR_SHIFT)) & RIT_CTRL_RITENCLR_MASK)
+#define RIT_CTRL_RITENBR_MASK                    (0x4U)
+#define RIT_CTRL_RITENBR_SHIFT                   (2U)
+/*! RITENBR - Timer enable for debug.
+ */
+#define RIT_CTRL_RITENBR(x)                      (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENBR_SHIFT)) & RIT_CTRL_RITENBR_MASK)
+#define RIT_CTRL_RITEN_MASK                      (0x8U)
+#define RIT_CTRL_RITEN_SHIFT                     (3U)
+/*! RITEN - Timer enable.
+ */
+#define RIT_CTRL_RITEN(x)                        (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITEN_SHIFT)) & RIT_CTRL_RITEN_MASK)
+/*! @} */
+
+/*! @name COUNTER - Counter LSB register */
+/*! @{ */
+#define RIT_COUNTER_RICOUNTER_MASK               (0xFFFFFFFFU)
+#define RIT_COUNTER_RICOUNTER_SHIFT              (0U)
+/*! RICOUNTER - 32 LSBs of the up counter.
+ */
+#define RIT_COUNTER_RICOUNTER(x)                 (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_RICOUNTER_SHIFT)) & RIT_COUNTER_RICOUNTER_MASK)
+/*! @} */
+
+/*! @name COMPVAL_H - Compare value MSB register */
+/*! @{ */
+#define RIT_COMPVAL_H_RICOMP_MASK                (0xFFFFU)
+#define RIT_COMPVAL_H_RICOMP_SHIFT               (0U)
+/*! RICOMP - Compare value MSB register.
+ */
+#define RIT_COMPVAL_H_RICOMP(x)                  (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_H_RICOMP_SHIFT)) & RIT_COMPVAL_H_RICOMP_MASK)
+/*! @} */
+
+/*! @name MASK_H - Mask MSB register */
+/*! @{ */
+#define RIT_MASK_H_RIMASK_MASK                   (0xFFFFU)
+#define RIT_MASK_H_RIMASK_SHIFT                  (0U)
+/*! RIMASK - Mask register.
+ */
+#define RIT_MASK_H_RIMASK(x)                     (((uint32_t)(((uint32_t)(x)) << RIT_MASK_H_RIMASK_SHIFT)) & RIT_MASK_H_RIMASK_MASK)
+/*! @} */
+
+/*! @name COUNTER_H - Counter MSB register */
+/*! @{ */
+#define RIT_COUNTER_H_RICOUNTER_MASK             (0xFFFFU)
+#define RIT_COUNTER_H_RICOUNTER_SHIFT            (0U)
+/*! RICOUNTER - 16 LSBs of the up counter.
+ */
+#define RIT_COUNTER_H_RICOUNTER(x)               (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_H_RICOUNTER_SHIFT)) & RIT_COUNTER_H_RICOUNTER_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group RIT_Register_Masks */
+
+
+/* RIT - Peripheral instance base addresses */
+/** Peripheral RIT base address */
+#define RIT_BASE                                 (0x4002D000u)
+/** Peripheral RIT base pointer */
+#define RIT                                      ((RIT_Type *)RIT_BASE)
+/** Array initializer of RIT peripheral base addresses */
+#define RIT_BASE_ADDRS                           { RIT_BASE }
+/** Array initializer of RIT peripheral base pointers */
+#define RIT_BASE_PTRS                            { RIT }
+/** Interrupt vectors for the RIT peripheral type */
+#define RIT_IRQS                                 { RIT_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< RTC control register, offset: 0x0 */
+  __IO uint32_t MATCH;                             /**< RTC match register, offset: 0x4 */
+  __IO uint32_t COUNT;                             /**< RTC counter register, offset: 0x8 */
+  __IO uint32_t WAKE;                              /**< High-resolution/wake-up timer control register, offset: 0xC */
+       uint8_t RESERVED_0[48];
+  __IO uint32_t GPREG[8];                          /**< General Purpose register, array offset: 0x40, array step: 0x4 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - RTC control register */
+/*! @{ */
+#define RTC_CTRL_SWRESET_MASK                    (0x1U)
+#define RTC_CTRL_SWRESET_SHIFT                   (0U)
+/*! SWRESET - Software reset control
+ *  0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC.
+ *  0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value
+ *       except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes
+ *       to set any of the other bits within this register. Do not attempt to write to any bits of this register at
+ *       the same time that the reset bit is being cleared.
+ */
+#define RTC_CTRL_SWRESET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)
+#define RTC_CTRL_ALARM1HZ_MASK                   (0x4U)
+#define RTC_CTRL_ALARM1HZ_SHIFT                  (2U)
+/*! ALARM1HZ - RTC 1 Hz timer alarm flag status.
+ *  0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect.
+ *  0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt
+ *       request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit.
+ */
+#define RTC_CTRL_ALARM1HZ(x)                     (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)
+#define RTC_CTRL_WAKE1KHZ_MASK                   (0x8U)
+#define RTC_CTRL_WAKE1KHZ_SHIFT                  (3U)
+/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status.
+ *  0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect.
+ *  0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up
+ *       interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit.
+ */
+#define RTC_CTRL_WAKE1KHZ(x)                     (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)
+#define RTC_CTRL_ALARMDPD_EN_MASK                (0x10U)
+#define RTC_CTRL_ALARMDPD_EN_SHIFT               (4U)
+/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down.
+ *  0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode.
+ *  0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode.
+ */
+#define RTC_CTRL_ALARMDPD_EN(x)                  (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)
+#define RTC_CTRL_WAKEDPD_EN_MASK                 (0x20U)
+#define RTC_CTRL_WAKEDPD_EN_SHIFT                (5U)
+/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down.
+ *  0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.
+ *  0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode.
+ */
+#define RTC_CTRL_WAKEDPD_EN(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)
+#define RTC_CTRL_RTC1KHZ_EN_MASK                 (0x40U)
+#define RTC_CTRL_RTC1KHZ_EN_SHIFT                (6U)
+/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz
+ *    timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0).
+ *  0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.
+ *  0b1..Enable. The 1 kHz RTC timer is enabled.
+ */
+#define RTC_CTRL_RTC1KHZ_EN(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)
+#define RTC_CTRL_RTC_EN_MASK                     (0x80U)
+#define RTC_CTRL_RTC_EN_SHIFT                    (7U)
+/*! RTC_EN - RTC enable.
+ *  0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should
+ *       be 0 when writing to load a value in the RTC counter register.
+ *  0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate
+ *       operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the
+ *       high-resolution, 1 kHz clock, set bit 6 in this register.
+ */
+#define RTC_CTRL_RTC_EN(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)
+#define RTC_CTRL_RTC_OSC_PD_MASK                 (0x100U)
+#define RTC_CTRL_RTC_OSC_PD_SHIFT                (8U)
+/*! RTC_OSC_PD - RTC oscillator power-down control.
+ *  0b0..See RTC_OSC_BYPASS
+ *  0b1..RTC oscillator is powered-down.
+ */
+#define RTC_CTRL_RTC_OSC_PD(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)
+/*! @} */
+
+/*! @name MATCH - RTC match register */
+/*! @{ */
+#define RTC_MATCH_MATVAL_MASK                    (0xFFFFFFFFU)
+#define RTC_MATCH_MATVAL_SHIFT                   (0U)
+/*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the
+ *    alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled.
+ */
+#define RTC_MATCH_MATVAL(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)
+/*! @} */
+
+/*! @name COUNT - RTC counter register */
+/*! @{ */
+#define RTC_COUNT_VAL_MASK                       (0xFFFFFFFFU)
+#define RTC_COUNT_VAL_SHIFT                      (0U)
+/*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial
+ *    value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC
+ *    Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this
+ *    register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after
+ *    the RTC_EN bit is set.
+ */
+#define RTC_COUNT_VAL(x)                         (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)
+/*! @} */
+
+/*! @name WAKE - High-resolution/wake-up timer control register */
+/*! @{ */
+#define RTC_WAKE_VAL_MASK                        (0xFFFFU)
+#define RTC_WAKE_VAL_SHIFT                       (0U)
+/*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads
+ *    a start count value into the wake-up timer and initializes a count-down sequence. Do not write
+ *    to this register while counting is in progress.
+ */
+#define RTC_WAKE_VAL(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)
+/*! @} */
+
+/*! @name GPREG - General Purpose register */
+/*! @{ */
+#define RTC_GPREG_GPDATA_MASK                    (0xFFFFFFFFU)
+#define RTC_GPREG_GPDATA_SHIFT                   (0U)
+/*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied.
+ */
+#define RTC_GPREG_GPDATA(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK)
+/*! @} */
+
+/* The count of RTC_GPREG */
+#define RTC_GPREG_COUNT                          (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4002C000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SCT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
+ * @{
+ */
+
+/** SCT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONFIG;                            /**< SCT configuration register, offset: 0x0 */
+  union {                                          /* offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint16_t CTRLL;                             /**< SCT_CTRLL register, offset: 0x4 */
+      __IO uint16_t CTRLH;                             /**< SCT_CTRLH register, offset: 0x6 */
+    } CTRL_ACCESS16BIT;
+    __IO uint32_t CTRL;                              /**< SCT control register, offset: 0x4 */
+  };
+  union {                                          /* offset: 0x8 */
+    struct {                                         /* offset: 0x8 */
+      __IO uint16_t LIMITL;                            /**< SCT_LIMITL register, offset: 0x8 */
+      __IO uint16_t LIMITH;                            /**< SCT_LIMITH register, offset: 0xA */
+    } LIMIT_ACCESS16BIT;
+    __IO uint32_t LIMIT;                             /**< SCT limit event select register, offset: 0x8 */
+  };
+  union {                                          /* offset: 0xC */
+    struct {                                         /* offset: 0xC */
+      __IO uint16_t HALTL;                             /**< SCT_HALTL register, offset: 0xC */
+      __IO uint16_t HALTH;                             /**< SCT_HALTH register, offset: 0xE */
+    } HALT_ACCESS16BIT;
+    __IO uint32_t HALT;                              /**< SCT halt event select register, offset: 0xC */
+  };
+  union {                                          /* offset: 0x10 */
+    struct {                                         /* offset: 0x10 */
+      __IO uint16_t STOPL;                             /**< SCT_STOPL register, offset: 0x10 */
+      __IO uint16_t STOPH;                             /**< SCT_STOPH register, offset: 0x12 */
+    } STOP_ACCESS16BIT;
+    __IO uint32_t STOP;                              /**< SCT stop event select register, offset: 0x10 */
+  };
+  union {                                          /* offset: 0x14 */
+    struct {                                         /* offset: 0x14 */
+      __IO uint16_t STARTL;                            /**< SCT_STARTL register, offset: 0x14 */
+      __IO uint16_t STARTH;                            /**< SCT_STARTH register, offset: 0x16 */
+    } START_ACCESS16BIT;
+    __IO uint32_t START;                             /**< SCT start event select register, offset: 0x14 */
+  };
+       uint8_t RESERVED_0[40];
+  union {                                          /* offset: 0x40 */
+    struct {                                         /* offset: 0x40 */
+      __IO uint16_t COUNTL;                            /**< SCT_COUNTL register, offset: 0x40 */
+      __IO uint16_t COUNTH;                            /**< SCT_COUNTH register, offset: 0x42 */
+    } COUNT_ACCESS16BIT;
+    __IO uint32_t COUNT;                             /**< SCT counter register, offset: 0x40 */
+  };
+  union {                                          /* offset: 0x44 */
+    struct {                                         /* offset: 0x44 */
+      __IO uint16_t STATEL;                            /**< SCT_STATEL register, offset: 0x44 */
+      __IO uint16_t STATEH;                            /**< SCT_STATEH register, offset: 0x46 */
+    } STATE_ACCESS16BIT;
+    __IO uint32_t STATE;                             /**< SCT state register, offset: 0x44 */
+  };
+  __I  uint32_t INPUT;                             /**< SCT input register, offset: 0x48 */
+  union {                                          /* offset: 0x4C */
+    struct {                                         /* offset: 0x4C */
+      __IO uint16_t REGMODEL;                          /**< SCT_REGMODEL register, offset: 0x4C */
+      __IO uint16_t REGMODEH;                          /**< SCT_REGMODEH register, offset: 0x4E */
+    } REGMODE_ACCESS16BIT;
+    __IO uint32_t REGMODE;                           /**< SCT match/capture mode register, offset: 0x4C */
+  };
+  __IO uint32_t OUTPUT;                            /**< SCT output register, offset: 0x50 */
+  __IO uint32_t OUTPUTDIRCTRL;                     /**< SCT output counter direction control register, offset: 0x54 */
+  __IO uint32_t RES;                               /**< SCT conflict resolution register, offset: 0x58 */
+  __IO uint32_t DMAREQ0;                           /**< SCT DMA request 0 register, offset: 0x5C */
+  __IO uint32_t DMAREQ1;                           /**< SCT DMA request 1 register, offset: 0x60 */
+       uint8_t RESERVED_1[140];
+  __IO uint32_t EVEN;                              /**< SCT event interrupt enable register, offset: 0xF0 */
+  __IO uint32_t EVFLAG;                            /**< SCT event flag register, offset: 0xF4 */
+  __IO uint32_t CONEN;                             /**< SCT conflict interrupt enable register, offset: 0xF8 */
+  __IO uint32_t CONFLAG;                           /**< SCT conflict flag register, offset: 0xFC */
+  union {                                          /* offset: 0x100 */
+    union {                                          /* offset: 0x100, array step: 0x4 */
+      struct {                                         /* offset: 0x100, array step: 0x4 */
+        __IO uint16_t CAPL;                              /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */
+        __IO uint16_t CAPH;                              /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */
+      } CAP_ACCESS16BIT[16];
+      __IO uint32_t CAP[16];                           /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */
+    };
+    union {                                          /* offset: 0x100, array step: 0x4 */
+      struct {                                         /* offset: 0x100, array step: 0x4 */
+        __IO uint16_t MATCHL;                            /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */
+        __IO uint16_t MATCHH;                            /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */
+      } MATCH_ACCESS16BIT[16];
+      __IO uint32_t MATCH[16];                         /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */
+    };
+  };
+       uint8_t RESERVED_2[192];
+  union {                                          /* offset: 0x200 */
+    union {                                          /* offset: 0x200, array step: 0x4 */
+      struct {                                         /* offset: 0x200, array step: 0x4 */
+        __IO uint16_t CAPCTRLL;                          /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */
+        __IO uint16_t CAPCTRLH;                          /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */
+      } CAPCTRL_ACCESS16BIT[16];
+      __IO uint32_t CAPCTRL[16];                       /**< SCT capture control register, array offset: 0x200, array step: 0x4 */
+    };
+    union {                                          /* offset: 0x200, array step: 0x4 */
+      struct {                                         /* offset: 0x200, array step: 0x4 */
+        __IO uint16_t MATCHRELL;                         /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */
+        __IO uint16_t MATCHRELH;                         /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */
+      } MATCHREL_ACCESS16BIT[16];
+      __IO uint32_t MATCHREL[16];                      /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */
+    };
+  };
+       uint8_t RESERVED_3[192];
+  struct {                                         /* offset: 0x300, array step: 0x8 */
+    __IO uint32_t STATE;                             /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */
+    __IO uint32_t CTRL;                              /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */
+  } EV[16];
+       uint8_t RESERVED_4[384];
+  struct {                                         /* offset: 0x500, array step: 0x8 */
+    __IO uint32_t SET;                               /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */
+    __IO uint32_t CLR;                               /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */
+  } OUT[10];
+} SCT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SCT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCT_Register_Masks SCT Register Masks
+ * @{
+ */
+
+/*! @name CONFIG - SCT configuration register */
+/*! @{ */
+#define SCT_CONFIG_UNIFY_MASK                    (0x1U)
+#define SCT_CONFIG_UNIFY_SHIFT                   (0U)
+/*! UNIFY - SCT operation
+ *  0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.
+ *  0b1..The SCT operates as a unified 32-bit counter.
+ */
+#define SCT_CONFIG_UNIFY(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
+#define SCT_CONFIG_CLKMODE_MASK                  (0x6U)
+#define SCT_CONFIG_CLKMODE_SHIFT                 (1U)
+/*! CLKMODE - SCT clock mode
+ *  0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers.
+ *  0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are
+ *        only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The
+ *        minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the
+ *        high-performance, sampled-clock mode.
+ *  0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the
+ *        counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the
+ *        clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.
+ *  0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL
+ *        field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system
+ *        clock. The input clock rate must be at least half the system clock rate and can be the same or faster than
+ *        the system clock.
+ */
+#define SCT_CONFIG_CLKMODE(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
+#define SCT_CONFIG_CKSEL_MASK                    (0x78U)
+#define SCT_CONFIG_CKSEL_SHIFT                   (3U)
+/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent
+ *    on the CLKMODE bit selection in this register.
+ *  0b0000..Rising edges on input 0.
+ *  0b0001..Falling edges on input 0.
+ *  0b0010..Rising edges on input 1.
+ *  0b0011..Falling edges on input 1.
+ *  0b0100..Rising edges on input 2.
+ *  0b0101..Falling edges on input 2.
+ *  0b0110..Rising edges on input 3.
+ *  0b0111..Falling edges on input 3.
+ *  0b1000..Rising edges on input 4.
+ *  0b1001..Falling edges on input 4.
+ *  0b1010..Rising edges on input 5.
+ *  0b1011..Falling edges on input 5.
+ *  0b1100..Rising edges on input 6.
+ *  0b1101..Falling edges on input 6.
+ *  0b1110..Rising edges on input 7.
+ *  0b1111..Falling edges on input 7.
+ */
+#define SCT_CONFIG_CKSEL(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
+#define SCT_CONFIG_NORELOAD_L_MASK               (0x80U)
+#define SCT_CONFIG_NORELOAD_L_SHIFT              (7U)
+/*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their
+ *    respective reload registers. Setting this bit eliminates the need to write to the reload
+ *    registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any
+ *    time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
+ */
+#define SCT_CONFIG_NORELOAD_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK)
+#define SCT_CONFIG_NORELOAD_H_MASK               (0x100U)
+#define SCT_CONFIG_NORELOAD_H_SHIFT              (8U)
+/*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their
+ *    respective reload registers. Setting this bit eliminates the need to write to the reload
+ *    registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at
+ *    any time. This bit is not used when the UNIFY bit is set.
+ */
+#define SCT_CONFIG_NORELOAD_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
+#define SCT_CONFIG_INSYNC_MASK                   (0x1FE00U)
+#define SCT_CONFIG_INSYNC_SHIFT                  (9U)
+/*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all
+ *    other bits are reserved. A 1 in one of these bits subjects the corresponding input to
+ *    synchronization to the SCT clock, before it is used to create an event. If an input is known to
+ *    already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note:
+ *    The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input
+ *    clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation.
+ *    It does not apply to the clock input specified in the CKSEL field.
+ */
+#define SCT_CONFIG_INSYNC(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
+#define SCT_CONFIG_AUTOLIMIT_L_MASK              (0x20000U)
+#define SCT_CONFIG_AUTOLIMIT_L_SHIFT             (17U)
+/*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto
+ *    LIMIT condition without the need to define an associated event. As with any LIMIT event, this
+ *    automatic limit causes the counter to be cleared to zero in unidirectional mode or to change
+ *    the direction of count in bi-directional mode. Software can write to set or clear this bit at
+ *    any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
+ */
+#define SCT_CONFIG_AUTOLIMIT_L(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
+#define SCT_CONFIG_AUTOLIMIT_H_MASK              (0x40000U)
+#define SCT_CONFIG_AUTOLIMIT_H_SHIFT             (18U)
+/*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a
+ *    de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event,
+ *    this automatic limit causes the counter to be cleared to zero in unidirectional mode or to
+ *    change the direction of count in bi-directional mode. Software can write to set or clear this bit
+ *    at any time. This bit is not used when the UNIFY bit is set.
+ */
+#define SCT_CONFIG_AUTOLIMIT_H(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
+/*! @} */
+
+/*! @name CTRLL - SCT_CTRLL register */
+/*! @{ */
+#define SCT_CTRLL_DOWN_L_MASK                    (0x1U)
+#define SCT_CTRLL_DOWN_L_SHIFT                   (0U)
+/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit
+ *    when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit
+ *    when the counter is counting down and a limit condition occurs or when the counter reaches 0.
+ */
+#define SCT_CTRLL_DOWN_L(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK)
+#define SCT_CTRLL_STOP_L_MASK                    (0x2U)
+#define SCT_CTRLL_STOP_L_SHIFT                   (1U)
+/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events
+ *    related to the counter can occur. If a designated start event occurs, this bit is cleared and
+ *    counting resumes.
+ */
+#define SCT_CTRLL_STOP_L(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK)
+#define SCT_CTRLL_HALT_L_MASK                    (0x4U)
+#define SCT_CTRLL_HALT_L_SHIFT                   (2U)
+/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A
+ *    reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to
+ *    remove the halt condition while keeping the SCT in the stop condition (not running) with a
+ *    single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set,
+ *    only software can clear this bit to restore counter operation. This bit is set on reset.
+ */
+#define SCT_CTRLL_HALT_L(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK)
+#define SCT_CTRLL_CLRCTR_L_MASK                  (0x8U)
+#define SCT_CTRLL_CLRCTR_L_SHIFT                 (3U)
+/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
+ */
+#define SCT_CTRLL_CLRCTR_L(x)                    (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK)
+#define SCT_CTRLL_BIDIR_L_MASK                   (0x10U)
+#define SCT_CTRLL_BIDIR_L_SHIFT                  (4U)
+/*! BIDIR_L - L or unified counter direction select
+ *  0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
+ *  0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
+ */
+#define SCT_CTRLL_BIDIR_L(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK)
+#define SCT_CTRLL_PRE_L_MASK                     (0x1FE0U)
+#define SCT_CTRLL_PRE_L_SHIFT                    (5U)
+/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified
+ *    counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1.
+ *    Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
+ */
+#define SCT_CTRLL_PRE_L(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK)
+/*! @} */
+
+/*! @name CTRLH - SCT_CTRLH register */
+/*! @{ */
+#define SCT_CTRLH_DOWN_H_MASK                    (0x1U)
+#define SCT_CTRLH_DOWN_H_SHIFT                   (0U)
+/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the
+ *    counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit
+ *    when the counter is counting down and a limit condition occurs or when the counter reaches 0.
+ */
+#define SCT_CTRLH_DOWN_H(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK)
+#define SCT_CTRLH_STOP_H_MASK                    (0x2U)
+#define SCT_CTRLH_STOP_H_SHIFT                   (1U)
+/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to
+ *    the counter can occur. If such an event matches the mask in the Start register, this bit is
+ *    cleared and counting resumes.
+ */
+#define SCT_CTRLH_STOP_H(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK)
+#define SCT_CTRLH_HALT_H_MASK                    (0x4U)
+#define SCT_CTRLH_HALT_H_SHIFT                   (2U)
+/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets
+ *    this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the
+ *    halt condition while keeping the SCT in the stop condition (not running) with a single write to
+ *    this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit
+ *    can only be cleared by software to restore counter operation. This bit is set on reset.
+ */
+#define SCT_CTRLH_HALT_H(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK)
+#define SCT_CTRLH_CLRCTR_H_MASK                  (0x8U)
+#define SCT_CTRLH_CLRCTR_H_SHIFT                 (3U)
+/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0.
+ */
+#define SCT_CTRLH_CLRCTR_H(x)                    (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK)
+#define SCT_CTRLH_BIDIR_H_MASK                   (0x10U)
+#define SCT_CTRLH_BIDIR_H_SHIFT                  (4U)
+/*! BIDIR_H - Direction select
+ *  0b0..The H counter counts up to its limit condition, then is cleared to zero.
+ *  0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0.
+ */
+#define SCT_CTRLH_BIDIR_H(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK)
+#define SCT_CTRLH_PRE_H_MASK                     (0x1FE0U)
+#define SCT_CTRLH_PRE_H_SHIFT                    (5U)
+/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock.
+ *    The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the
+ *    counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
+ */
+#define SCT_CTRLH_PRE_H(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK)
+/*! @} */
+
+/*! @name CTRL - SCT control register */
+/*! @{ */
+#define SCT_CTRL_DOWN_L_MASK                     (0x1U)
+#define SCT_CTRL_DOWN_L_SHIFT                    (0U)
+/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit
+ *    when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit
+ *    when the counter is counting down and a limit condition occurs or when the counter reaches 0.
+ */
+#define SCT_CTRL_DOWN_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
+#define SCT_CTRL_STOP_L_MASK                     (0x2U)
+#define SCT_CTRL_STOP_L_SHIFT                    (1U)
+/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events
+ *    related to the counter can occur. If a designated start event occurs, this bit is cleared and
+ *    counting resumes.
+ */
+#define SCT_CTRL_STOP_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
+#define SCT_CTRL_HALT_L_MASK                     (0x4U)
+#define SCT_CTRL_HALT_L_SHIFT                    (2U)
+/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A
+ *    reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to
+ *    remove the halt condition while keeping the SCT in the stop condition (not running) with a
+ *    single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set,
+ *    only software can clear this bit to restore counter operation. This bit is set on reset.
+ */
+#define SCT_CTRL_HALT_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
+#define SCT_CTRL_CLRCTR_L_MASK                   (0x8U)
+#define SCT_CTRL_CLRCTR_L_SHIFT                  (3U)
+/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
+ */
+#define SCT_CTRL_CLRCTR_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
+#define SCT_CTRL_BIDIR_L_MASK                    (0x10U)
+#define SCT_CTRL_BIDIR_L_SHIFT                   (4U)
+/*! BIDIR_L - L or unified counter direction select
+ *  0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
+ *  0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
+ */
+#define SCT_CTRL_BIDIR_L(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
+#define SCT_CTRL_PRE_L_MASK                      (0x1FE0U)
+#define SCT_CTRL_PRE_L_SHIFT                     (5U)
+/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified
+ *    counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1.
+ *    Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
+ */
+#define SCT_CTRL_PRE_L(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
+#define SCT_CTRL_DOWN_H_MASK                     (0x10000U)
+#define SCT_CTRL_DOWN_H_SHIFT                    (16U)
+/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the
+ *    counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit
+ *    when the counter is counting down and a limit condition occurs or when the counter reaches 0.
+ */
+#define SCT_CTRL_DOWN_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
+#define SCT_CTRL_STOP_H_MASK                     (0x20000U)
+#define SCT_CTRL_STOP_H_SHIFT                    (17U)
+/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to
+ *    the counter can occur. If such an event matches the mask in the Start register, this bit is
+ *    cleared and counting resumes.
+ */
+#define SCT_CTRL_STOP_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
+#define SCT_CTRL_HALT_H_MASK                     (0x40000U)
+#define SCT_CTRL_HALT_H_SHIFT                    (18U)
+/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets
+ *    this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the
+ *    halt condition while keeping the SCT in the stop condition (not running) with a single write to
+ *    this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit
+ *    can only be cleared by software to restore counter operation. This bit is set on reset.
+ */
+#define SCT_CTRL_HALT_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
+#define SCT_CTRL_CLRCTR_H_MASK                   (0x80000U)
+#define SCT_CTRL_CLRCTR_H_SHIFT                  (19U)
+/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0.
+ */
+#define SCT_CTRL_CLRCTR_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
+#define SCT_CTRL_BIDIR_H_MASK                    (0x100000U)
+#define SCT_CTRL_BIDIR_H_SHIFT                   (20U)
+/*! BIDIR_H - Direction select
+ *  0b0..The H counter counts up to its limit condition, then is cleared to zero.
+ *  0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0.
+ */
+#define SCT_CTRL_BIDIR_H(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
+#define SCT_CTRL_PRE_H_MASK                      (0x1FE00000U)
+#define SCT_CTRL_PRE_H_SHIFT                     (21U)
+/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock.
+ *    The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the
+ *    counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
+ */
+#define SCT_CTRL_PRE_H(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
+/*! @} */
+
+/*! @name LIMITL - SCT_LIMITL register */
+/*! @{ */
+#define SCT_LIMITL_LIMITL_MASK                   (0xFFFFU)
+#define SCT_LIMITL_LIMITL_SHIFT                  (0U)
+#define SCT_LIMITL_LIMITL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK)
+/*! @} */
+
+/*! @name LIMITH - SCT_LIMITH register */
+/*! @{ */
+#define SCT_LIMITH_LIMITH_MASK                   (0xFFFFU)
+#define SCT_LIMITH_LIMITH_SHIFT                  (0U)
+#define SCT_LIMITH_LIMITH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK)
+/*! @} */
+
+/*! @name LIMIT - SCT limit event select register */
+/*! @{ */
+#define SCT_LIMIT_LIMMSK_L_MASK                  (0xFFFFU)
+#define SCT_LIMIT_LIMMSK_L_SHIFT                 (0U)
+/*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter
+ *    (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_LIMIT_LIMMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
+#define SCT_LIMIT_LIMMSK_H_MASK                  (0xFFFF0000U)
+#define SCT_LIMIT_LIMMSK_H_SHIFT                 (16U)
+/*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit
+ *    16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_LIMIT_LIMMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
+/*! @} */
+
+/*! @name HALTL - SCT_HALTL register */
+/*! @{ */
+#define SCT_HALTL_HALTL_MASK                     (0xFFFFU)
+#define SCT_HALTL_HALTL_SHIFT                    (0U)
+#define SCT_HALTL_HALTL(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK)
+/*! @} */
+
+/*! @name HALTH - SCT_HALTH register */
+/*! @{ */
+#define SCT_HALTH_HALTH_MASK                     (0xFFFFU)
+#define SCT_HALTH_HALTH_SHIFT                    (0U)
+#define SCT_HALTH_HALTH(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK)
+/*! @} */
+
+/*! @name HALT - SCT halt event select register */
+/*! @{ */
+#define SCT_HALT_HALTMSK_L_MASK                  (0xFFFFU)
+#define SCT_HALT_HALTMSK_L_SHIFT                 (0U)
+/*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0,
+ *    event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_HALT_HALTMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
+#define SCT_HALT_HALTMSK_H_MASK                  (0xFFFF0000U)
+#define SCT_HALT_HALTMSK_H_SHIFT                 (16U)
+/*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16,
+ *    event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_HALT_HALTMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
+/*! @} */
+
+/*! @name STOPL - SCT_STOPL register */
+/*! @{ */
+#define SCT_STOPL_STOPL_MASK                     (0xFFFFU)
+#define SCT_STOPL_STOPL_SHIFT                    (0U)
+#define SCT_STOPL_STOPL(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK)
+/*! @} */
+
+/*! @name STOPH - SCT_STOPH register */
+/*! @{ */
+#define SCT_STOPH_STOPH_MASK                     (0xFFFFU)
+#define SCT_STOPH_STOPH_SHIFT                    (0U)
+#define SCT_STOPH_STOPH(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK)
+/*! @} */
+
+/*! @name STOP - SCT stop event select register */
+/*! @{ */
+#define SCT_STOP_STOPMSK_L_MASK                  (0xFFFFU)
+#define SCT_STOP_STOPMSK_L_SHIFT                 (0U)
+/*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0,
+ *    event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_STOP_STOPMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
+#define SCT_STOP_STOPMSK_H_MASK                  (0xFFFF0000U)
+#define SCT_STOP_STOPMSK_H_SHIFT                 (16U)
+/*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16,
+ *    event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_STOP_STOPMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
+/*! @} */
+
+/*! @name STARTL - SCT_STARTL register */
+/*! @{ */
+#define SCT_STARTL_STARTL_MASK                   (0xFFFFU)
+#define SCT_STARTL_STARTL_SHIFT                  (0U)
+#define SCT_STARTL_STARTL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK)
+/*! @} */
+
+/*! @name STARTH - SCT_STARTH register */
+/*! @{ */
+#define SCT_STARTH_STARTH_MASK                   (0xFFFFU)
+#define SCT_STARTH_STARTH_SHIFT                  (0U)
+#define SCT_STARTH_STARTH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK)
+/*! @} */
+
+/*! @name START - SCT start event select register */
+/*! @{ */
+#define SCT_START_STARTMSK_L_MASK                (0xFFFFU)
+#define SCT_START_STARTMSK_L_SHIFT               (0U)
+/*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit
+ *    0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_START_STARTMSK_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
+#define SCT_START_STARTMSK_H_MASK                (0xFFFF0000U)
+#define SCT_START_STARTMSK_H_SHIFT               (16U)
+/*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit
+ *    16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_START_STARTMSK_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
+/*! @} */
+
+/*! @name COUNTL - SCT_COUNTL register */
+/*! @{ */
+#define SCT_COUNTL_COUNTL_MASK                   (0xFFFFU)
+#define SCT_COUNTL_COUNTL_SHIFT                  (0U)
+#define SCT_COUNTL_COUNTL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK)
+/*! @} */
+
+/*! @name COUNTH - SCT_COUNTH register */
+/*! @{ */
+#define SCT_COUNTH_COUNTH_MASK                   (0xFFFFU)
+#define SCT_COUNTH_COUNTH_SHIFT                  (0U)
+#define SCT_COUNTH_COUNTH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK)
+/*! @} */
+
+/*! @name COUNT - SCT counter register */
+/*! @{ */
+#define SCT_COUNT_CTR_L_MASK                     (0xFFFFU)
+#define SCT_COUNT_CTR_L_SHIFT                    (0U)
+/*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write
+ *    the lower 16 bits of the 32-bit unified counter.
+ */
+#define SCT_COUNT_CTR_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
+#define SCT_COUNT_CTR_H_MASK                     (0xFFFF0000U)
+#define SCT_COUNT_CTR_H_SHIFT                    (16U)
+/*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write
+ *    the upper 16 bits of the 32-bit unified counter.
+ */
+#define SCT_COUNT_CTR_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
+/*! @} */
+
+/*! @name STATEL - SCT_STATEL register */
+/*! @{ */
+#define SCT_STATEL_STATEL_MASK                   (0xFFFFU)
+#define SCT_STATEL_STATEL_SHIFT                  (0U)
+#define SCT_STATEL_STATEL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK)
+/*! @} */
+
+/*! @name STATEH - SCT_STATEH register */
+/*! @{ */
+#define SCT_STATEH_STATEH_MASK                   (0xFFFFU)
+#define SCT_STATEH_STATEH_SHIFT                  (0U)
+#define SCT_STATEH_STATEH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK)
+/*! @} */
+
+/*! @name STATE - SCT state register */
+/*! @{ */
+#define SCT_STATE_STATE_L_MASK                   (0x1FU)
+#define SCT_STATE_STATE_L_SHIFT                  (0U)
+/*! STATE_L - State variable.
+ */
+#define SCT_STATE_STATE_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
+#define SCT_STATE_STATE_H_MASK                   (0x1F0000U)
+#define SCT_STATE_STATE_H_SHIFT                  (16U)
+/*! STATE_H - State variable.
+ */
+#define SCT_STATE_STATE_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
+/*! @} */
+
+/*! @name INPUT - SCT input register */
+/*! @{ */
+#define SCT_INPUT_AIN0_MASK                      (0x1U)
+#define SCT_INPUT_AIN0_SHIFT                     (0U)
+/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
+#define SCT_INPUT_AIN1_MASK                      (0x2U)
+#define SCT_INPUT_AIN1_SHIFT                     (1U)
+/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
+#define SCT_INPUT_AIN2_MASK                      (0x4U)
+#define SCT_INPUT_AIN2_SHIFT                     (2U)
+/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
+#define SCT_INPUT_AIN3_MASK                      (0x8U)
+#define SCT_INPUT_AIN3_SHIFT                     (3U)
+/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
+#define SCT_INPUT_AIN4_MASK                      (0x10U)
+#define SCT_INPUT_AIN4_SHIFT                     (4U)
+/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)
+#define SCT_INPUT_AIN5_MASK                      (0x20U)
+#define SCT_INPUT_AIN5_SHIFT                     (5U)
+/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)
+#define SCT_INPUT_AIN6_MASK                      (0x40U)
+#define SCT_INPUT_AIN6_SHIFT                     (6U)
+/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)
+#define SCT_INPUT_AIN7_MASK                      (0x80U)
+#define SCT_INPUT_AIN7_SHIFT                     (7U)
+/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)
+#define SCT_INPUT_AIN8_MASK                      (0x100U)
+#define SCT_INPUT_AIN8_SHIFT                     (8U)
+/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)
+#define SCT_INPUT_AIN9_MASK                      (0x200U)
+#define SCT_INPUT_AIN9_SHIFT                     (9U)
+/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)
+#define SCT_INPUT_AIN10_MASK                     (0x400U)
+#define SCT_INPUT_AIN10_SHIFT                    (10U)
+/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)
+#define SCT_INPUT_AIN11_MASK                     (0x800U)
+#define SCT_INPUT_AIN11_SHIFT                    (11U)
+/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)
+#define SCT_INPUT_AIN12_MASK                     (0x1000U)
+#define SCT_INPUT_AIN12_SHIFT                    (12U)
+/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)
+#define SCT_INPUT_AIN13_MASK                     (0x2000U)
+#define SCT_INPUT_AIN13_SHIFT                    (13U)
+/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)
+#define SCT_INPUT_AIN14_MASK                     (0x4000U)
+#define SCT_INPUT_AIN14_SHIFT                    (14U)
+/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)
+#define SCT_INPUT_AIN15_MASK                     (0x8000U)
+#define SCT_INPUT_AIN15_SHIFT                    (15U)
+/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)
+#define SCT_INPUT_SIN0_MASK                      (0x10000U)
+#define SCT_INPUT_SIN0_SHIFT                     (16U)
+/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
+#define SCT_INPUT_SIN1_MASK                      (0x20000U)
+#define SCT_INPUT_SIN1_SHIFT                     (17U)
+/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
+#define SCT_INPUT_SIN2_MASK                      (0x40000U)
+#define SCT_INPUT_SIN2_SHIFT                     (18U)
+/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
+#define SCT_INPUT_SIN3_MASK                      (0x80000U)
+#define SCT_INPUT_SIN3_SHIFT                     (19U)
+/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
+#define SCT_INPUT_SIN4_MASK                      (0x100000U)
+#define SCT_INPUT_SIN4_SHIFT                     (20U)
+/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)
+#define SCT_INPUT_SIN5_MASK                      (0x200000U)
+#define SCT_INPUT_SIN5_SHIFT                     (21U)
+/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)
+#define SCT_INPUT_SIN6_MASK                      (0x400000U)
+#define SCT_INPUT_SIN6_SHIFT                     (22U)
+/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)
+#define SCT_INPUT_SIN7_MASK                      (0x800000U)
+#define SCT_INPUT_SIN7_SHIFT                     (23U)
+/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)
+#define SCT_INPUT_SIN8_MASK                      (0x1000000U)
+#define SCT_INPUT_SIN8_SHIFT                     (24U)
+/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)
+#define SCT_INPUT_SIN9_MASK                      (0x2000000U)
+#define SCT_INPUT_SIN9_SHIFT                     (25U)
+/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)
+#define SCT_INPUT_SIN10_MASK                     (0x4000000U)
+#define SCT_INPUT_SIN10_SHIFT                    (26U)
+/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)
+#define SCT_INPUT_SIN11_MASK                     (0x8000000U)
+#define SCT_INPUT_SIN11_SHIFT                    (27U)
+/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)
+#define SCT_INPUT_SIN12_MASK                     (0x10000000U)
+#define SCT_INPUT_SIN12_SHIFT                    (28U)
+/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)
+#define SCT_INPUT_SIN13_MASK                     (0x20000000U)
+#define SCT_INPUT_SIN13_SHIFT                    (29U)
+/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)
+#define SCT_INPUT_SIN14_MASK                     (0x40000000U)
+#define SCT_INPUT_SIN14_SHIFT                    (30U)
+/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)
+#define SCT_INPUT_SIN15_MASK                     (0x80000000U)
+#define SCT_INPUT_SIN15_SHIFT                    (31U)
+/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
+/*! @} */
+
+/*! @name REGMODEL - SCT_REGMODEL register */
+/*! @{ */
+#define SCT_REGMODEL_REGMODEL_MASK               (0xFFFFU)
+#define SCT_REGMODEL_REGMODEL_SHIFT              (0U)
+#define SCT_REGMODEL_REGMODEL(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK)
+/*! @} */
+
+/*! @name REGMODEH - SCT_REGMODEH register */
+/*! @{ */
+#define SCT_REGMODEH_REGMODEH_MASK               (0xFFFFU)
+#define SCT_REGMODEH_REGMODEH_SHIFT              (0U)
+#define SCT_REGMODEH_REGMODEH(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK)
+/*! @} */
+
+/*! @name REGMODE - SCT match/capture mode register */
+/*! @{ */
+#define SCT_REGMODE_REGMOD_L_MASK                (0xFFFFU)
+#define SCT_REGMODE_REGMOD_L_SHIFT               (0U)
+/*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1,
+ *    etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as
+ *    match register. 1 = register operates as capture register.
+ */
+#define SCT_REGMODE_REGMOD_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
+#define SCT_REGMODE_REGMOD_H_MASK                (0xFFFF0000U)
+#define SCT_REGMODE_REGMOD_H_SHIFT               (16U)
+/*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit
+ *    17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as
+ *    match registers. 1 = register operates as capture registers.
+ */
+#define SCT_REGMODE_REGMOD_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
+/*! @} */
+
+/*! @name OUTPUT - SCT output register */
+/*! @{ */
+#define SCT_OUTPUT_OUT_MASK                      (0xFFFFU)
+#define SCT_OUTPUT_OUT_SHIFT                     (0U)
+/*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the
+ *    corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of
+ *    outputs in this SCT.
+ */
+#define SCT_OUTPUT_OUT(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)
+/*! @} */
+
+/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */
+/*! @{ */
+#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK           (0x3U)
+#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT          (0U)
+/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR0(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK           (0xCU)
+#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT          (2U)
+/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR1(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK           (0x30U)
+#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT          (4U)
+/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR2(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK           (0xC0U)
+#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT          (6U)
+/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR3(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK           (0x300U)
+#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT          (8U)
+/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR4(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK           (0xC00U)
+#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT          (10U)
+/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR5(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK           (0x3000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT          (12U)
+/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR6(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK           (0xC000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT          (14U)
+/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR7(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK           (0x30000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT          (16U)
+/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR8(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK           (0xC0000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT          (18U)
+/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR9(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK          (0x300000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT         (20U)
+/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value.
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR10(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK          (0xC00000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT         (22U)
+/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR11(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK          (0x3000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT         (24U)
+/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR12(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK          (0xC000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT         (26U)
+/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR13(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK          (0x30000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT         (28U)
+/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR14(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK          (0xC0000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT         (30U)
+/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR15(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK)
+/*! @} */
+
+/*! @name RES - SCT conflict resolution register */
+/*! @{ */
+#define SCT_RES_O0RES_MASK                       (0x3U)
+#define SCT_RES_O0RES_SHIFT                      (0U)
+/*! O0RES - Effect of simultaneous set and clear on output 0.
+ *  0b00..No change.
+ *  0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register).
+ *  0b10..Clear output (or set based on the SETCLR0 field).
+ *  0b11..Toggle output.
+ */
+#define SCT_RES_O0RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
+#define SCT_RES_O1RES_MASK                       (0xCU)
+#define SCT_RES_O1RES_SHIFT                      (2U)
+/*! O1RES - Effect of simultaneous set and clear on output 1.
+ *  0b00..No change.
+ *  0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register).
+ *  0b10..Clear output (or set based on the SETCLR1 field).
+ *  0b11..Toggle output.
+ */
+#define SCT_RES_O1RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
+#define SCT_RES_O2RES_MASK                       (0x30U)
+#define SCT_RES_O2RES_SHIFT                      (4U)
+/*! O2RES - Effect of simultaneous set and clear on output 2.
+ *  0b00..No change.
+ *  0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register).
+ *  0b10..Clear output n (or set based on the SETCLR2 field).
+ *  0b11..Toggle output.
+ */
+#define SCT_RES_O2RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
+#define SCT_RES_O3RES_MASK                       (0xC0U)
+#define SCT_RES_O3RES_SHIFT                      (6U)
+/*! O3RES - Effect of simultaneous set and clear on output 3.
+ *  0b00..No change.
+ *  0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register).
+ *  0b10..Clear output (or set based on the SETCLR3 field).
+ *  0b11..Toggle output.
+ */
+#define SCT_RES_O3RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
+#define SCT_RES_O4RES_MASK                       (0x300U)
+#define SCT_RES_O4RES_SHIFT                      (8U)
+/*! O4RES - Effect of simultaneous set and clear on output 4.
+ *  0b00..No change.
+ *  0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register).
+ *  0b10..Clear output (or set based on the SETCLR4 field).
+ *  0b11..Toggle output.
+ */
+#define SCT_RES_O4RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
+#define SCT_RES_O5RES_MASK                       (0xC00U)
+#define SCT_RES_O5RES_SHIFT                      (10U)
+/*! O5RES - Effect of simultaneous set and clear on output 5.
+ *  0b00..No change.
+ *  0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register).
+ *  0b10..Clear output (or set based on the SETCLR5 field).
+ *  0b11..Toggle output.
+ */
+#define SCT_RES_O5RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
+#define SCT_RES_O6RES_MASK                       (0x3000U)
+#define SCT_RES_O6RES_SHIFT                      (12U)
+/*! O6RES - Effect of simultaneous set and clear on output 6.
+ *  0b00..No change.
+ *  0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register).
+ *  0b10..Clear output (or set based on the SETCLR6 field).
+ *  0b11..Toggle output.
+ */
+#define SCT_RES_O6RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)
+#define SCT_RES_O7RES_MASK                       (0xC000U)
+#define SCT_RES_O7RES_SHIFT                      (14U)
+/*! O7RES - Effect of simultaneous set and clear on output 7.
+ *  0b00..No change.
+ *  0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register).
+ *  0b10..Clear output n (or set based on the SETCLR7 field).
+ *  0b11..Toggle output.
+ */
+#define SCT_RES_O7RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)
+#define SCT_RES_O8RES_MASK                       (0x30000U)
+#define SCT_RES_O8RES_SHIFT                      (16U)
+/*! O8RES - Effect of simultaneous set and clear on output 8.
+ *  0b00..No change.
+ *  0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register).
+ *  0b10..Clear output (or set based on the SETCLR8 field).
+ *  0b11..Toggle output.
+ */
+#define SCT_RES_O8RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)
+#define SCT_RES_O9RES_MASK                       (0xC0000U)
+#define SCT_RES_O9RES_SHIFT                      (18U)
+/*! O9RES - Effect of simultaneous set and clear on output 9.
+ *  0b00..No change.
+ *  0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register).
+ *  0b10..Clear output (or set based on the SETCLR9 field).
+ *  0b11..Toggle output.
+ */
+#define SCT_RES_O9RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
+#define SCT_RES_O10RES_MASK                      (0x300000U)
+#define SCT_RES_O10RES_SHIFT                     (20U)
+/*! O10RES - Effect of simultaneous set and clear on output 10.
+ *  0b00..No change.
+ *  0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register).
+ *  0b10..Clear output (or set based on the SETCLR10 field).
+ *  0b11..Toggle output.
+ */
+#define SCT_RES_O10RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK)
+#define SCT_RES_O11RES_MASK                      (0xC00000U)
+#define SCT_RES_O11RES_SHIFT                     (22U)
+/*! O11RES - Effect of simultaneous set and clear on output 11.
+ *  0b00..No change.
+ *  0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register).
+ *  0b10..Clear output (or set based on the SETCLR11 field).
+ *  0b11..Toggle output.
+ */
+#define SCT_RES_O11RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK)
+#define SCT_RES_O12RES_MASK                      (0x3000000U)
+#define SCT_RES_O12RES_SHIFT                     (24U)
+/*! O12RES - Effect of simultaneous set and clear on output 12.
+ *  0b00..No change.
+ *  0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register).
+ *  0b10..Clear output (or set based on the SETCLR12 field).
+ *  0b11..Toggle output.
+ */
+#define SCT_RES_O12RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK)
+#define SCT_RES_O13RES_MASK                      (0xC000000U)
+#define SCT_RES_O13RES_SHIFT                     (26U)
+/*! O13RES - Effect of simultaneous set and clear on output 13.
+ *  0b00..No change.
+ *  0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register).
+ *  0b10..Clear output (or set based on the SETCLR13 field).
+ *  0b11..Toggle output.
+ */
+#define SCT_RES_O13RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK)
+#define SCT_RES_O14RES_MASK                      (0x30000000U)
+#define SCT_RES_O14RES_SHIFT                     (28U)
+/*! O14RES - Effect of simultaneous set and clear on output 14.
+ *  0b00..No change.
+ *  0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register).
+ *  0b10..Clear output (or set based on the SETCLR14 field).
+ *  0b11..Toggle output.
+ */
+#define SCT_RES_O14RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK)
+#define SCT_RES_O15RES_MASK                      (0xC0000000U)
+#define SCT_RES_O15RES_SHIFT                     (30U)
+/*! O15RES - Effect of simultaneous set and clear on output 15.
+ *  0b00..No change.
+ *  0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register).
+ *  0b10..Clear output (or set based on the SETCLR15 field).
+ *  0b11..Toggle output.
+ */
+#define SCT_RES_O15RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK)
+/*! @} */
+
+/*! @name DMAREQ0 - SCT DMA request 0 register */
+/*! @{ */
+#define SCT_DMAREQ0_DEV_0_MASK                   (0xFFFFU)
+#define SCT_DMAREQ0_DEV_0_SHIFT                  (0U)
+/*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1,
+ *    etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_DMAREQ0_DEV_0(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK)
+#define SCT_DMAREQ0_DRL0_MASK                    (0x40000000U)
+#define SCT_DMAREQ0_DRL0_SHIFT                   (30U)
+/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers.
+ */
+#define SCT_DMAREQ0_DRL0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK)
+#define SCT_DMAREQ0_DRQ0_MASK                    (0x80000000U)
+#define SCT_DMAREQ0_DRQ0_SHIFT                   (31U)
+/*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA
+ *    channel is enabled and properly set up, it is unlikely that software will see this flag, it will
+ *    be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA
+ *    setup.
+ */
+#define SCT_DMAREQ0_DRQ0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK)
+/*! @} */
+
+/*! @name DMAREQ1 - SCT DMA request 1 register */
+/*! @{ */
+#define SCT_DMAREQ1_DEV_1_MASK                   (0xFFFFU)
+#define SCT_DMAREQ1_DEV_1_SHIFT                  (0U)
+/*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1,
+ *    etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_DMAREQ1_DEV_1(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK)
+#define SCT_DMAREQ1_DRL1_MASK                    (0x40000000U)
+#define SCT_DMAREQ1_DRL1_SHIFT                   (30U)
+/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
+ */
+#define SCT_DMAREQ1_DRL1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK)
+#define SCT_DMAREQ1_DRQ1_MASK                    (0x80000000U)
+#define SCT_DMAREQ1_DRQ1_SHIFT                   (31U)
+/*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA
+ *    channel is enabled and properly set up, it is unlikely that software will see this flag, it will
+ *    be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA
+ *    setup.
+ */
+#define SCT_DMAREQ1_DRQ1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK)
+/*! @} */
+
+/*! @name EVEN - SCT event interrupt enable register */
+/*! @{ */
+#define SCT_EVEN_IEN_MASK                        (0xFFFFU)
+#define SCT_EVEN_IEN_SHIFT                       (0U)
+/*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are
+ *    both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in
+ *    this SCT.
+ */
+#define SCT_EVEN_IEN(x)                          (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)
+/*! @} */
+
+/*! @name EVFLAG - SCT event flag register */
+/*! @{ */
+#define SCT_EVFLAG_FLAG_MASK                     (0xFFFFU)
+#define SCT_EVFLAG_FLAG_SHIFT                    (0U)
+/*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit
+ *    (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_EVFLAG_FLAG(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)
+/*! @} */
+
+/*! @name CONEN - SCT conflict interrupt enable register */
+/*! @{ */
+#define SCT_CONEN_NCEN_MASK                      (0xFFFFU)
+#define SCT_CONEN_NCEN_SHIFT                     (0U)
+/*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag
+ *    register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of
+ *    outputs in this SCT.
+ */
+#define SCT_CONEN_NCEN(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)
+/*! @} */
+
+/*! @name CONFLAG - SCT conflict flag register */
+/*! @{ */
+#define SCT_CONFLAG_NCFLAG_MASK                  (0xFFFFU)
+#define SCT_CONFLAG_NCFLAG_SHIFT                 (0U)
+/*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was
+ *    last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits =
+ *    number of outputs in this SCT.
+ */
+#define SCT_CONFLAG_NCFLAG(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)
+#define SCT_CONFLAG_BUSERRL_MASK                 (0x40000000U)
+#define SCT_CONFLAG_BUSERRL_SHIFT                (30U)
+/*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE
+ *    L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write
+ *    to certain L and H registers can be half successful and half unsuccessful.
+ */
+#define SCT_CONFLAG_BUSERRL(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
+#define SCT_CONFLAG_BUSERRH_MASK                 (0x80000000U)
+#define SCT_CONFLAG_BUSERRH_SHIFT                (31U)
+/*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or
+ *    the Output register when the H counter was not halted.
+ */
+#define SCT_CONFLAG_BUSERRH(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
+/*! @} */
+
+/*! @name CAPL - SCT_CAPL register */
+/*! @{ */
+#define SCT_CAPL_CAPL_MASK                       (0xFFFFU)
+#define SCT_CAPL_CAPL_SHIFT                      (0U)
+#define SCT_CAPL_CAPL(x)                         (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK)
+/*! @} */
+
+/* The count of SCT_CAPL */
+#define SCT_CAPL_COUNT                           (16U)
+
+/*! @name CAPH - SCT_CAPH register */
+/*! @{ */
+#define SCT_CAPH_CAPH_MASK                       (0xFFFFU)
+#define SCT_CAPH_CAPH_SHIFT                      (0U)
+#define SCT_CAPH_CAPH(x)                         (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK)
+/*! @} */
+
+/* The count of SCT_CAPH */
+#define SCT_CAPH_COUNT                           (16U)
+
+/*! @name CAP - SCT capture register of capture channel */
+/*! @{ */
+#define SCT_CAP_CAPn_L_MASK                      (0xFFFFU)
+#define SCT_CAP_CAPn_L_SHIFT                     (0U)
+/*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured.
+ *    When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last
+ *    captured.
+ */
+#define SCT_CAP_CAPn_L(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK)
+#define SCT_CAP_CAPn_H_MASK                      (0xFFFF0000U)
+#define SCT_CAP_CAPn_H_SHIFT                     (16U)
+/*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured.
+ *    When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last
+ *    captured.
+ */
+#define SCT_CAP_CAPn_H(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK)
+/*! @} */
+
+/* The count of SCT_CAP */
+#define SCT_CAP_COUNT                            (16U)
+
+/*! @name MATCHL - SCT_MATCHL register */
+/*! @{ */
+#define SCT_MATCHL_MATCHL_MASK                   (0xFFFFU)
+#define SCT_MATCHL_MATCHL_SHIFT                  (0U)
+#define SCT_MATCHL_MATCHL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHL */
+#define SCT_MATCHL_COUNT                         (16U)
+
+/*! @name MATCHH - SCT_MATCHH register */
+/*! @{ */
+#define SCT_MATCHH_MATCHH_MASK                   (0xFFFFU)
+#define SCT_MATCHH_MATCHH_SHIFT                  (0U)
+#define SCT_MATCHH_MATCHH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHH */
+#define SCT_MATCHH_COUNT                         (16U)
+
+/*! @name MATCH - SCT match value register of match channels */
+/*! @{ */
+#define SCT_MATCH_MATCHn_L_MASK                  (0xFFFFU)
+#define SCT_MATCH_MATCHn_L_SHIFT                 (0U)
+/*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When
+ *    UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified
+ *    counter.
+ */
+#define SCT_MATCH_MATCHn_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK)
+#define SCT_MATCH_MATCHn_H_MASK                  (0xFFFF0000U)
+#define SCT_MATCH_MATCHn_H_SHIFT                 (16U)
+/*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When
+ *    UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified
+ *    counter.
+ */
+#define SCT_MATCH_MATCHn_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK)
+/*! @} */
+
+/* The count of SCT_MATCH */
+#define SCT_MATCH_COUNT                          (16U)
+
+/*! @name CAPCTRLL - SCT_CAPCTRLL register */
+/*! @{ */
+#define SCT_CAPCTRLL_CAPCTRLL_MASK               (0xFFFFU)
+#define SCT_CAPCTRLL_CAPCTRLL_SHIFT              (0U)
+#define SCT_CAPCTRLL_CAPCTRLL(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK)
+/*! @} */
+
+/* The count of SCT_CAPCTRLL */
+#define SCT_CAPCTRLL_COUNT                       (16U)
+
+/*! @name CAPCTRLH - SCT_CAPCTRLH register */
+/*! @{ */
+#define SCT_CAPCTRLH_CAPCTRLH_MASK               (0xFFFFU)
+#define SCT_CAPCTRLH_CAPCTRLH_SHIFT              (0U)
+#define SCT_CAPCTRLH_CAPCTRLH(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK)
+/*! @} */
+
+/* The count of SCT_CAPCTRLH */
+#define SCT_CAPCTRLH_COUNT                       (16U)
+
+/*! @name CAPCTRL - SCT capture control register */
+/*! @{ */
+#define SCT_CAPCTRL_CAPCONn_L_MASK               (0xFFFFU)
+#define SCT_CAPCTRL_CAPCONn_L_SHIFT              (0U)
+/*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1)
+ *    register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of
+ *    match/captures in this SCT.
+ */
+#define SCT_CAPCTRL_CAPCONn_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK)
+#define SCT_CAPCTRL_CAPCONn_H_MASK               (0xFFFF0000U)
+#define SCT_CAPCTRL_CAPCONn_H_SHIFT              (16U)
+/*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event
+ *    0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
+ */
+#define SCT_CAPCTRL_CAPCONn_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK)
+/*! @} */
+
+/* The count of SCT_CAPCTRL */
+#define SCT_CAPCTRL_COUNT                        (16U)
+
+/*! @name MATCHRELL - SCT_MATCHRELL register */
+/*! @{ */
+#define SCT_MATCHRELL_MATCHRELL_MASK             (0xFFFFU)
+#define SCT_MATCHRELL_MATCHRELL_SHIFT            (0U)
+#define SCT_MATCHRELL_MATCHRELL(x)               (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHRELL */
+#define SCT_MATCHRELL_COUNT                      (16U)
+
+/*! @name MATCHRELH - SCT_MATCHRELH register */
+/*! @{ */
+#define SCT_MATCHRELH_MATCHRELH_MASK             (0xFFFFU)
+#define SCT_MATCHRELH_MATCHRELH_SHIFT            (0U)
+#define SCT_MATCHRELH_MATCHRELH(x)               (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHRELH */
+#define SCT_MATCHRELH_COUNT                      (16U)
+
+/*! @name MATCHREL - SCT match reload value register */
+/*! @{ */
+#define SCT_MATCHREL_RELOADn_L_MASK              (0xFFFFU)
+#define SCT_MATCHREL_RELOADn_L_SHIFT             (0U)
+/*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register.
+ *    When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn
+ *    register.
+ */
+#define SCT_MATCHREL_RELOADn_L(x)                (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK)
+#define SCT_MATCHREL_RELOADn_H_MASK              (0xFFFF0000U)
+#define SCT_MATCHREL_RELOADn_H_SHIFT             (16U)
+/*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When
+ *    UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn
+ *    register.
+ */
+#define SCT_MATCHREL_RELOADn_H(x)                (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHREL */
+#define SCT_MATCHREL_COUNT                       (16U)
+
+/*! @name EV_STATE - SCT event state register 0 */
+/*! @{ */
+#define SCT_EV_STATE_STATEMSKn_MASK              (0xFFFFU)
+#define SCT_EV_STATE_STATEMSKn_SHIFT             (0U)
+/*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT
+ *    bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of
+ *    bits = number of states in this SCT.
+ */
+#define SCT_EV_STATE_STATEMSKn(x)                (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK)
+/*! @} */
+
+/* The count of SCT_EV_STATE */
+#define SCT_EV_STATE_COUNT                       (16U)
+
+/*! @name EV_CTRL - SCT event control register 0 */
+/*! @{ */
+#define SCT_EV_CTRL_MATCHSEL_MASK                (0xFU)
+#define SCT_EV_CTRL_MATCHSEL_SHIFT               (0U)
+/*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur
+ *    only when the counter selected by the HEVENT bit is running.
+ */
+#define SCT_EV_CTRL_MATCHSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK)
+#define SCT_EV_CTRL_HEVENT_MASK                  (0x10U)
+#define SCT_EV_CTRL_HEVENT_SHIFT                 (4U)
+/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1.
+ *  0b0..Selects the L state and the L match register selected by MATCHSEL.
+ *  0b1..Selects the H state and the H match register selected by MATCHSEL.
+ */
+#define SCT_EV_CTRL_HEVENT(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK)
+#define SCT_EV_CTRL_OUTSEL_MASK                  (0x20U)
+#define SCT_EV_CTRL_OUTSEL_SHIFT                 (5U)
+/*! OUTSEL - Input/output select
+ *  0b0..Selects the inputs selected by IOSEL.
+ *  0b1..Selects the outputs selected by IOSEL.
+ */
+#define SCT_EV_CTRL_OUTSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK)
+#define SCT_EV_CTRL_IOSEL_MASK                   (0x3C0U)
+#define SCT_EV_CTRL_IOSEL_SHIFT                  (6U)
+/*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not
+ *    select an input in this register if CKMODE is 1x. In this case the clock input is an implicit
+ *    ingredient of every event.
+ */
+#define SCT_EV_CTRL_IOSEL(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK)
+#define SCT_EV_CTRL_IOCOND_MASK                  (0xC00U)
+#define SCT_EV_CTRL_IOCOND_SHIFT                 (10U)
+/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the
+ *    conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state
+ *    detection, an input must have a minimum pulse width of at least one SCT clock period .
+ *  0b00..LOW
+ *  0b01..Rise
+ *  0b10..Fall
+ *  0b11..HIGH
+ */
+#define SCT_EV_CTRL_IOCOND(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK)
+#define SCT_EV_CTRL_COMBMODE_MASK                (0x3000U)
+#define SCT_EV_CTRL_COMBMODE_SHIFT               (12U)
+/*! COMBMODE - Selects how the specified match and I/O condition are used and combined.
+ *  0b00..OR. The event occurs when either the specified match or I/O condition occurs.
+ *  0b01..MATCH. Uses the specified match only.
+ *  0b10..IO. Uses the specified I/O condition only.
+ *  0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously.
+ */
+#define SCT_EV_CTRL_COMBMODE(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK)
+#define SCT_EV_CTRL_STATELD_MASK                 (0x4000U)
+#define SCT_EV_CTRL_STATELD_SHIFT                (14U)
+/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this
+ *    event is the highest-numbered event occurring for that state.
+ *  0b0..STATEV value is added into STATE (the carry-out is ignored).
+ *  0b1..STATEV value is loaded into STATE.
+ */
+#define SCT_EV_CTRL_STATELD(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK)
+#define SCT_EV_CTRL_STATEV_MASK                  (0xF8000U)
+#define SCT_EV_CTRL_STATEV_SHIFT                 (15U)
+/*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on
+ *    STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and
+ *    STATEV are both zero, there is no change to the STATE value.
+ */
+#define SCT_EV_CTRL_STATEV(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK)
+#define SCT_EV_CTRL_MATCHMEM_MASK                (0x100000U)
+#define SCT_EV_CTRL_MATCHMEM_SHIFT               (20U)
+/*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the
+ *    triggering of this event, then a match is considered to be active whenever the counter value is
+ *    GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR
+ *    EQUAL TO the match value when counting down. If this bit is zero, a match is only be active
+ *    during the cycle when the counter is equal to the match value.
+ */
+#define SCT_EV_CTRL_MATCHMEM(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK)
+#define SCT_EV_CTRL_DIRECTION_MASK               (0x600000U)
+#define SCT_EV_CTRL_DIRECTION_SHIFT              (21U)
+/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters
+ *    are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
+ *  0b00..Direction independent. This event is triggered regardless of the count direction.
+ *  0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1.
+ *  0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1.
+ */
+#define SCT_EV_CTRL_DIRECTION(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK)
+/*! @} */
+
+/* The count of SCT_EV_CTRL */
+#define SCT_EV_CTRL_COUNT                        (16U)
+
+/*! @name OUT_SET - SCT output 0 set register */
+/*! @{ */
+#define SCT_OUT_SET_SET_MASK                     (0xFFFFU)
+#define SCT_OUT_SET_SET_SHIFT                    (0U)
+/*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output
+ *    0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the
+ *    counter is used in bi-directional mode, it is possible to reverse the action specified by the
+ *    output set and clear registers when counting down, See the OUTPUTCTRL register.
+ */
+#define SCT_OUT_SET_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
+/*! @} */
+
+/* The count of SCT_OUT_SET */
+#define SCT_OUT_SET_COUNT                        (10U)
+
+/*! @name OUT_CLR - SCT output 0 clear register */
+/*! @{ */
+#define SCT_OUT_CLR_CLR_MASK                     (0xFFFFU)
+#define SCT_OUT_CLR_CLR_SHIFT                    (0U)
+/*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0
+ *    = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the
+ *    counter is used in bi-directional mode, it is possible to reverse the action specified by the
+ *    output set and clear registers when counting down, See the OUTPUTCTRL register.
+ */
+#define SCT_OUT_CLR_CLR(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
+/*! @} */
+
+/* The count of SCT_OUT_CLR */
+#define SCT_OUT_CLR_COUNT                        (10U)
+
+
+/*!
+ * @}
+ */ /* end of group SCT_Register_Masks */
+
+
+/* SCT - Peripheral instance base addresses */
+/** Peripheral SCT0 base address */
+#define SCT0_BASE                                (0x40085000u)
+/** Peripheral SCT0 base pointer */
+#define SCT0                                     ((SCT_Type *)SCT0_BASE)
+/** Array initializer of SCT peripheral base addresses */
+#define SCT_BASE_ADDRS                           { SCT0_BASE }
+/** Array initializer of SCT peripheral base pointers */
+#define SCT_BASE_PTRS                            { SCT0 }
+/** Interrupt vectors for the SCT peripheral type */
+#define SCT_IRQS                                 { SCT0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SCT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDIF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer
+ * @{
+ */
+
+/** SDIF - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< Control register, offset: 0x0 */
+  __IO uint32_t PWREN;                             /**< Power Enable register, offset: 0x4 */
+  __IO uint32_t CLKDIV;                            /**< Clock Divider register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CLKENA;                            /**< Clock Enable register, offset: 0x10 */
+  __IO uint32_t TMOUT;                             /**< Time-out register, offset: 0x14 */
+  __IO uint32_t CTYPE;                             /**< Card Type register, offset: 0x18 */
+  __IO uint32_t BLKSIZ;                            /**< Block Size register, offset: 0x1C */
+  __IO uint32_t BYTCNT;                            /**< Byte Count register, offset: 0x20 */
+  __IO uint32_t INTMASK;                           /**< Interrupt Mask register, offset: 0x24 */
+  __IO uint32_t CMDARG;                            /**< Command Argument register, offset: 0x28 */
+  __IO uint32_t CMD;                               /**< Command register, offset: 0x2C */
+  __I  uint32_t RESP[4];                           /**< Response register, array offset: 0x30, array step: 0x4 */
+  __I  uint32_t MINTSTS;                           /**< Masked Interrupt Status register, offset: 0x40 */
+  __IO uint32_t RINTSTS;                           /**< Raw Interrupt Status register, offset: 0x44 */
+  __I  uint32_t STATUS;                            /**< Status register, offset: 0x48 */
+  __IO uint32_t FIFOTH;                            /**< FIFO Threshold Watermark register, offset: 0x4C */
+  __I  uint32_t CDETECT;                           /**< Card Detect register, offset: 0x50 */
+  __I  uint32_t WRTPRT;                            /**< Write Protect register, offset: 0x54 */
+       uint8_t RESERVED_1[4];
+  __I  uint32_t TCBCNT;                            /**< Transferred CIU Card Byte Count register, offset: 0x5C */
+  __I  uint32_t TBBCNT;                            /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */
+  __IO uint32_t DEBNCE;                            /**< Debounce Count register, offset: 0x64 */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t RST_N;                             /**< Hardware Reset, offset: 0x78 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t BMOD;                              /**< Bus Mode register, offset: 0x80 */
+  __O  uint32_t PLDMND;                            /**< Poll Demand register, offset: 0x84 */
+  __IO uint32_t DBADDR;                            /**< Descriptor List Base Address register, offset: 0x88 */
+  __IO uint32_t IDSTS;                             /**< Internal DMAC Status register, offset: 0x8C */
+  __IO uint32_t IDINTEN;                           /**< Internal DMAC Interrupt Enable register, offset: 0x90 */
+  __I  uint32_t DSCADDR;                           /**< Current Host Descriptor Address register, offset: 0x94 */
+  __I  uint32_t BUFADDR;                           /**< Current Buffer Descriptor Address register, offset: 0x98 */
+       uint8_t RESERVED_4[100];
+  __IO uint32_t CARDTHRCTL;                        /**< Card Threshold Control, offset: 0x100 */
+  __IO uint32_t BACKENDPWR;                        /**< Power control, offset: 0x104 */
+       uint8_t RESERVED_5[248];
+  __IO uint32_t FIFO[64];                          /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */
+} SDIF_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SDIF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDIF_Register_Masks SDIF Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control register */
+/*! @{ */
+#define SDIF_CTRL_CONTROLLER_RESET_MASK          (0x1U)
+#define SDIF_CTRL_CONTROLLER_RESET_SHIFT         (0U)
+/*! CONTROLLER_RESET - Controller reset.
+ */
+#define SDIF_CTRL_CONTROLLER_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK)
+#define SDIF_CTRL_FIFO_RESET_MASK                (0x2U)
+#define SDIF_CTRL_FIFO_RESET_SHIFT               (1U)
+/*! FIFO_RESET - Fifo reset.
+ */
+#define SDIF_CTRL_FIFO_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK)
+#define SDIF_CTRL_DMA_RESET_MASK                 (0x4U)
+#define SDIF_CTRL_DMA_RESET_SHIFT                (2U)
+/*! DMA_RESET - DMA reset.
+ */
+#define SDIF_CTRL_DMA_RESET(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
+#define SDIF_CTRL_INT_ENABLE_MASK                (0x10U)
+#define SDIF_CTRL_INT_ENABLE_SHIFT               (4U)
+/*! INT_ENABLE - Global interrupt enable/disable bit.
+ */
+#define SDIF_CTRL_INT_ENABLE(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK)
+#define SDIF_CTRL_READ_WAIT_MASK                 (0x40U)
+#define SDIF_CTRL_READ_WAIT_SHIFT                (6U)
+/*! READ_WAIT - Read/wait.
+ */
+#define SDIF_CTRL_READ_WAIT(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK)
+#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK         (0x80U)
+#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT        (7U)
+/*! SEND_IRQ_RESPONSE - Send irq response.
+ */
+#define SDIF_CTRL_SEND_IRQ_RESPONSE(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK)
+#define SDIF_CTRL_ABORT_READ_DATA_MASK           (0x100U)
+#define SDIF_CTRL_ABORT_READ_DATA_SHIFT          (8U)
+/*! ABORT_READ_DATA - Abort read data.
+ */
+#define SDIF_CTRL_ABORT_READ_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK)
+#define SDIF_CTRL_SEND_CCSD_MASK                 (0x200U)
+#define SDIF_CTRL_SEND_CCSD_SHIFT                (9U)
+/*! SEND_CCSD - Send ccsd.
+ */
+#define SDIF_CTRL_SEND_CCSD(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK)
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK       (0x400U)
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT      (10U)
+/*! SEND_AUTO_STOP_CCSD - Send auto stop ccsd.
+ */
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK)
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U)
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U)
+/*! CEATA_DEVICE_INTERRUPT_STATUS - CEATA device interrupt status.
+ */
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK)
+#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK           (0x10000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT          (16U)
+/*! CARD_VOLTAGE_A0 - Controls the state of the SD_VOLT0 pin.
+ */
+#define SDIF_CTRL_CARD_VOLTAGE_A0(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK)
+#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK           (0x20000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT          (17U)
+/*! CARD_VOLTAGE_A1 - Controls the state of the SD_VOLT1 pin.
+ */
+#define SDIF_CTRL_CARD_VOLTAGE_A1(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK)
+#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK           (0x40000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT          (18U)
+/*! CARD_VOLTAGE_A2 - Controls the state of the SD_VOLT2 pin.
+ */
+#define SDIF_CTRL_CARD_VOLTAGE_A2(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK)
+#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK         (0x2000000U)
+#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT        (25U)
+/*! USE_INTERNAL_DMAC - SD/MMC DMA use.
+ */
+#define SDIF_CTRL_USE_INTERNAL_DMAC(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK)
+/*! @} */
+
+/*! @name PWREN - Power Enable register */
+/*! @{ */
+#define SDIF_PWREN_POWER_ENABLE_MASK             (0x1U)
+#define SDIF_PWREN_POWER_ENABLE_SHIFT            (0U)
+/*! POWER_ENABLE - Power on/off switch for card; once power is turned on, software should wait for
+ *    regulator/switch ramp-up time before trying to initialize card.
+ */
+#define SDIF_PWREN_POWER_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE_SHIFT)) & SDIF_PWREN_POWER_ENABLE_MASK)
+/*! @} */
+
+/*! @name CLKDIV - Clock Divider register */
+/*! @{ */
+#define SDIF_CLKDIV_CLK_DIVIDER0_MASK            (0xFFU)
+#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT           (0U)
+/*! CLK_DIVIDER0 - Clock divider-0 value.
+ */
+#define SDIF_CLKDIV_CLK_DIVIDER0(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK)
+/*! @} */
+
+/*! @name CLKENA - Clock Enable register */
+/*! @{ */
+#define SDIF_CLKENA_CCLK_ENABLE_MASK             (0x1U)
+#define SDIF_CLKENA_CCLK_ENABLE_SHIFT            (0U)
+/*! CCLK_ENABLE - Clock-enable control for SD card clock.
+ */
+#define SDIF_CLKENA_CCLK_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK_ENABLE_MASK)
+#define SDIF_CLKENA_CCLK_LOW_POWER_MASK          (0x10000U)
+#define SDIF_CLKENA_CCLK_LOW_POWER_SHIFT         (16U)
+/*! CCLK_LOW_POWER - Low-power control for SD card clock.
+ */
+#define SDIF_CLKENA_CCLK_LOW_POWER(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK_LOW_POWER_MASK)
+/*! @} */
+
+/*! @name TMOUT - Time-out register */
+/*! @{ */
+#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK         (0xFFU)
+#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT        (0U)
+/*! RESPONSE_TIMEOUT - Response time-out value.
+ */
+#define SDIF_TMOUT_RESPONSE_TIMEOUT(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK)
+#define SDIF_TMOUT_DATA_TIMEOUT_MASK             (0xFFFFFF00U)
+#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT            (8U)
+/*! DATA_TIMEOUT - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out.
+ */
+#define SDIF_TMOUT_DATA_TIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK)
+/*! @} */
+
+/*! @name CTYPE - Card Type register */
+/*! @{ */
+#define SDIF_CTYPE_CARD_WIDTH0_MASK              (0x1U)
+#define SDIF_CTYPE_CARD_WIDTH0_SHIFT             (0U)
+/*! CARD_WIDTH0 - Indicates if card is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit
+ *    modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to
+ *    0).
+ */
+#define SDIF_CTYPE_CARD_WIDTH0(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD_WIDTH0_MASK)
+#define SDIF_CTYPE_CARD_WIDTH1_MASK              (0x10000U)
+#define SDIF_CTYPE_CARD_WIDTH1_SHIFT             (16U)
+/*! CARD_WIDTH1 - Indicates if card is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode.
+ */
+#define SDIF_CTYPE_CARD_WIDTH1(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD_WIDTH1_MASK)
+/*! @} */
+
+/*! @name BLKSIZ - Block Size register */
+/*! @{ */
+#define SDIF_BLKSIZ_BLOCK_SIZE_MASK              (0xFFFFU)
+#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT             (0U)
+/*! BLOCK_SIZE - Block size.
+ */
+#define SDIF_BLKSIZ_BLOCK_SIZE(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK)
+/*! @} */
+
+/*! @name BYTCNT - Byte Count register */
+/*! @{ */
+#define SDIF_BYTCNT_BYTE_COUNT_MASK              (0xFFFFFFFFU)
+#define SDIF_BYTCNT_BYTE_COUNT_SHIFT             (0U)
+/*! BYTE_COUNT - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers.
+ */
+#define SDIF_BYTCNT_BYTE_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK)
+/*! @} */
+
+/*! @name INTMASK - Interrupt Mask register */
+/*! @{ */
+#define SDIF_INTMASK_CDET_MASK                   (0x1U)
+#define SDIF_INTMASK_CDET_SHIFT                  (0U)
+/*! CDET - Card detect.
+ */
+#define SDIF_INTMASK_CDET(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK)
+#define SDIF_INTMASK_RE_MASK                     (0x2U)
+#define SDIF_INTMASK_RE_SHIFT                    (1U)
+/*! RE - Response error.
+ */
+#define SDIF_INTMASK_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK)
+#define SDIF_INTMASK_CDONE_MASK                  (0x4U)
+#define SDIF_INTMASK_CDONE_SHIFT                 (2U)
+/*! CDONE - Command done.
+ */
+#define SDIF_INTMASK_CDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK)
+#define SDIF_INTMASK_DTO_MASK                    (0x8U)
+#define SDIF_INTMASK_DTO_SHIFT                   (3U)
+/*! DTO - Data transfer over.
+ */
+#define SDIF_INTMASK_DTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK)
+#define SDIF_INTMASK_TXDR_MASK                   (0x10U)
+#define SDIF_INTMASK_TXDR_SHIFT                  (4U)
+/*! TXDR - Transmit FIFO data request.
+ */
+#define SDIF_INTMASK_TXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK)
+#define SDIF_INTMASK_RXDR_MASK                   (0x20U)
+#define SDIF_INTMASK_RXDR_SHIFT                  (5U)
+/*! RXDR - Receive FIFO data request.
+ */
+#define SDIF_INTMASK_RXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK)
+#define SDIF_INTMASK_RCRC_MASK                   (0x40U)
+#define SDIF_INTMASK_RCRC_SHIFT                  (6U)
+/*! RCRC - Response CRC error.
+ */
+#define SDIF_INTMASK_RCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK)
+#define SDIF_INTMASK_DCRC_MASK                   (0x80U)
+#define SDIF_INTMASK_DCRC_SHIFT                  (7U)
+/*! DCRC - Data CRC error.
+ */
+#define SDIF_INTMASK_DCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK)
+#define SDIF_INTMASK_RTO_MASK                    (0x100U)
+#define SDIF_INTMASK_RTO_SHIFT                   (8U)
+/*! RTO - Response time-out.
+ */
+#define SDIF_INTMASK_RTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK)
+#define SDIF_INTMASK_DRTO_MASK                   (0x200U)
+#define SDIF_INTMASK_DRTO_SHIFT                  (9U)
+/*! DRTO - Data read time-out.
+ */
+#define SDIF_INTMASK_DRTO(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK)
+#define SDIF_INTMASK_HTO_MASK                    (0x400U)
+#define SDIF_INTMASK_HTO_SHIFT                   (10U)
+/*! HTO - Data starvation-by-host time-out (HTO).
+ */
+#define SDIF_INTMASK_HTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK)
+#define SDIF_INTMASK_FRUN_MASK                   (0x800U)
+#define SDIF_INTMASK_FRUN_SHIFT                  (11U)
+/*! FRUN - FIFO underrun/overrun error.
+ */
+#define SDIF_INTMASK_FRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK)
+#define SDIF_INTMASK_HLE_MASK                    (0x1000U)
+#define SDIF_INTMASK_HLE_SHIFT                   (12U)
+/*! HLE - Hardware locked write error.
+ */
+#define SDIF_INTMASK_HLE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK)
+#define SDIF_INTMASK_SBE_MASK                    (0x2000U)
+#define SDIF_INTMASK_SBE_SHIFT                   (13U)
+/*! SBE - Start-bit error.
+ */
+#define SDIF_INTMASK_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK)
+#define SDIF_INTMASK_ACD_MASK                    (0x4000U)
+#define SDIF_INTMASK_ACD_SHIFT                   (14U)
+/*! ACD - Auto command done.
+ */
+#define SDIF_INTMASK_ACD(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK)
+#define SDIF_INTMASK_EBE_MASK                    (0x8000U)
+#define SDIF_INTMASK_EBE_SHIFT                   (15U)
+/*! EBE - End-bit error (read)/Write no CRC.
+ */
+#define SDIF_INTMASK_EBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK)
+#define SDIF_INTMASK_SDIO_INT_MASK_MASK          (0x10000U)
+#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT         (16U)
+/*! SDIO_INT_MASK - Mask SDIO interrupt.
+ */
+#define SDIF_INTMASK_SDIO_INT_MASK(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK)
+/*! @} */
+
+/*! @name CMDARG - Command Argument register */
+/*! @{ */
+#define SDIF_CMDARG_CMD_ARG_MASK                 (0xFFFFFFFFU)
+#define SDIF_CMDARG_CMD_ARG_SHIFT                (0U)
+/*! CMD_ARG - Value indicates command argument to be passed to card.
+ */
+#define SDIF_CMDARG_CMD_ARG(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK)
+/*! @} */
+
+/*! @name CMD - Command register */
+/*! @{ */
+#define SDIF_CMD_CMD_INDEX_MASK                  (0x3FU)
+#define SDIF_CMD_CMD_INDEX_SHIFT                 (0U)
+/*! CMD_INDEX - Command index.
+ */
+#define SDIF_CMD_CMD_INDEX(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK)
+#define SDIF_CMD_RESPONSE_EXPECT_MASK            (0x40U)
+#define SDIF_CMD_RESPONSE_EXPECT_SHIFT           (6U)
+/*! RESPONSE_EXPECT - Response expect.
+ */
+#define SDIF_CMD_RESPONSE_EXPECT(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK)
+#define SDIF_CMD_RESPONSE_LENGTH_MASK            (0x80U)
+#define SDIF_CMD_RESPONSE_LENGTH_SHIFT           (7U)
+/*! RESPONSE_LENGTH - Response length.
+ */
+#define SDIF_CMD_RESPONSE_LENGTH(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK)
+#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK         (0x100U)
+#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT        (8U)
+/*! CHECK_RESPONSE_CRC - Check response CRC.
+ */
+#define SDIF_CMD_CHECK_RESPONSE_CRC(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK)
+#define SDIF_CMD_DATA_EXPECTED_MASK              (0x200U)
+#define SDIF_CMD_DATA_EXPECTED_SHIFT             (9U)
+/*! DATA_EXPECTED - Data expected.
+ */
+#define SDIF_CMD_DATA_EXPECTED(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK)
+#define SDIF_CMD_READ_WRITE_MASK                 (0x400U)
+#define SDIF_CMD_READ_WRITE_SHIFT                (10U)
+/*! READ_WRITE - read/write.
+ */
+#define SDIF_CMD_READ_WRITE(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK)
+#define SDIF_CMD_TRANSFER_MODE_MASK              (0x800U)
+#define SDIF_CMD_TRANSFER_MODE_SHIFT             (11U)
+/*! TRANSFER_MODE - Transfer mode.
+ */
+#define SDIF_CMD_TRANSFER_MODE(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK)
+#define SDIF_CMD_SEND_AUTO_STOP_MASK             (0x1000U)
+#define SDIF_CMD_SEND_AUTO_STOP_SHIFT            (12U)
+/*! SEND_AUTO_STOP - Send auto stop.
+ */
+#define SDIF_CMD_SEND_AUTO_STOP(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK)
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK      (0x2000U)
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT     (13U)
+/*! WAIT_PRVDATA_COMPLETE - Wait prvdata complete.
+ */
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x)        (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK)
+#define SDIF_CMD_STOP_ABORT_CMD_MASK             (0x4000U)
+#define SDIF_CMD_STOP_ABORT_CMD_SHIFT            (14U)
+/*! STOP_ABORT_CMD - Stop abort command.
+ */
+#define SDIF_CMD_STOP_ABORT_CMD(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK)
+#define SDIF_CMD_SEND_INITIALIZATION_MASK        (0x8000U)
+#define SDIF_CMD_SEND_INITIALIZATION_SHIFT       (15U)
+/*! SEND_INITIALIZATION - Send initialization.
+ */
+#define SDIF_CMD_SEND_INITIALIZATION(x)          (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK)
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U)
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U)
+/*! UPDATE_CLOCK_REGISTERS_ONLY - Update clock registers only.
+ */
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x)  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK)
+#define SDIF_CMD_READ_CEATA_DEVICE_MASK          (0x400000U)
+#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT         (22U)
+/*! READ_CEATA_DEVICE - Read ceata device.
+ */
+#define SDIF_CMD_READ_CEATA_DEVICE(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK)
+#define SDIF_CMD_CCS_EXPECTED_MASK               (0x800000U)
+#define SDIF_CMD_CCS_EXPECTED_SHIFT              (23U)
+/*! CCS_EXPECTED - CCS expected.
+ */
+#define SDIF_CMD_CCS_EXPECTED(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK)
+#define SDIF_CMD_ENABLE_BOOT_MASK                (0x1000000U)
+#define SDIF_CMD_ENABLE_BOOT_SHIFT               (24U)
+/*! ENABLE_BOOT - Enable Boot - this bit should be set only for mandatory boot mode.
+ */
+#define SDIF_CMD_ENABLE_BOOT(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK)
+#define SDIF_CMD_EXPECT_BOOT_ACK_MASK            (0x2000000U)
+#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT           (25U)
+/*! EXPECT_BOOT_ACK - Expect Boot Acknowledge.
+ */
+#define SDIF_CMD_EXPECT_BOOT_ACK(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK)
+#define SDIF_CMD_DISABLE_BOOT_MASK               (0x4000000U)
+#define SDIF_CMD_DISABLE_BOOT_SHIFT              (26U)
+/*! DISABLE_BOOT - Disable Boot.
+ */
+#define SDIF_CMD_DISABLE_BOOT(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK)
+#define SDIF_CMD_BOOT_MODE_MASK                  (0x8000000U)
+#define SDIF_CMD_BOOT_MODE_SHIFT                 (27U)
+/*! BOOT_MODE - Boot Mode.
+ */
+#define SDIF_CMD_BOOT_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK)
+#define SDIF_CMD_VOLT_SWITCH_MASK                (0x10000000U)
+#define SDIF_CMD_VOLT_SWITCH_SHIFT               (28U)
+/*! VOLT_SWITCH - Voltage switch bit.
+ */
+#define SDIF_CMD_VOLT_SWITCH(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK)
+#define SDIF_CMD_USE_HOLD_REG_MASK               (0x20000000U)
+#define SDIF_CMD_USE_HOLD_REG_SHIFT              (29U)
+/*! USE_HOLD_REG - Use Hold Register.
+ */
+#define SDIF_CMD_USE_HOLD_REG(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK)
+#define SDIF_CMD_START_CMD_MASK                  (0x80000000U)
+#define SDIF_CMD_START_CMD_SHIFT                 (31U)
+/*! START_CMD - Start command.
+ */
+#define SDIF_CMD_START_CMD(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK)
+/*! @} */
+
+/*! @name RESP - Response register */
+/*! @{ */
+#define SDIF_RESP_RESPONSE_MASK                  (0xFFFFFFFFU)
+#define SDIF_RESP_RESPONSE_SHIFT                 (0U)
+/*! RESPONSE - Bits of response.
+ */
+#define SDIF_RESP_RESPONSE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK)
+/*! @} */
+
+/* The count of SDIF_RESP */
+#define SDIF_RESP_COUNT                          (4U)
+
+/*! @name MINTSTS - Masked Interrupt Status register */
+/*! @{ */
+#define SDIF_MINTSTS_CDET_MASK                   (0x1U)
+#define SDIF_MINTSTS_CDET_SHIFT                  (0U)
+/*! CDET - Card detect.
+ */
+#define SDIF_MINTSTS_CDET(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK)
+#define SDIF_MINTSTS_RE_MASK                     (0x2U)
+#define SDIF_MINTSTS_RE_SHIFT                    (1U)
+/*! RE - Response error.
+ */
+#define SDIF_MINTSTS_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK)
+#define SDIF_MINTSTS_CDONE_MASK                  (0x4U)
+#define SDIF_MINTSTS_CDONE_SHIFT                 (2U)
+/*! CDONE - Command done.
+ */
+#define SDIF_MINTSTS_CDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK)
+#define SDIF_MINTSTS_DTO_MASK                    (0x8U)
+#define SDIF_MINTSTS_DTO_SHIFT                   (3U)
+/*! DTO - Data transfer over.
+ */
+#define SDIF_MINTSTS_DTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK)
+#define SDIF_MINTSTS_TXDR_MASK                   (0x10U)
+#define SDIF_MINTSTS_TXDR_SHIFT                  (4U)
+/*! TXDR - Transmit FIFO data request.
+ */
+#define SDIF_MINTSTS_TXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK)
+#define SDIF_MINTSTS_RXDR_MASK                   (0x20U)
+#define SDIF_MINTSTS_RXDR_SHIFT                  (5U)
+/*! RXDR - Receive FIFO data request.
+ */
+#define SDIF_MINTSTS_RXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK)
+#define SDIF_MINTSTS_RCRC_MASK                   (0x40U)
+#define SDIF_MINTSTS_RCRC_SHIFT                  (6U)
+/*! RCRC - Response CRC error.
+ */
+#define SDIF_MINTSTS_RCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK)
+#define SDIF_MINTSTS_DCRC_MASK                   (0x80U)
+#define SDIF_MINTSTS_DCRC_SHIFT                  (7U)
+/*! DCRC - Data CRC error.
+ */
+#define SDIF_MINTSTS_DCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK)
+#define SDIF_MINTSTS_RTO_MASK                    (0x100U)
+#define SDIF_MINTSTS_RTO_SHIFT                   (8U)
+/*! RTO - Response time-out.
+ */
+#define SDIF_MINTSTS_RTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK)
+#define SDIF_MINTSTS_DRTO_MASK                   (0x200U)
+#define SDIF_MINTSTS_DRTO_SHIFT                  (9U)
+/*! DRTO - Data read time-out.
+ */
+#define SDIF_MINTSTS_DRTO(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK)
+#define SDIF_MINTSTS_HTO_MASK                    (0x400U)
+#define SDIF_MINTSTS_HTO_SHIFT                   (10U)
+/*! HTO - Data starvation-by-host time-out (HTO).
+ */
+#define SDIF_MINTSTS_HTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK)
+#define SDIF_MINTSTS_FRUN_MASK                   (0x800U)
+#define SDIF_MINTSTS_FRUN_SHIFT                  (11U)
+/*! FRUN - FIFO underrun/overrun error.
+ */
+#define SDIF_MINTSTS_FRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK)
+#define SDIF_MINTSTS_HLE_MASK                    (0x1000U)
+#define SDIF_MINTSTS_HLE_SHIFT                   (12U)
+/*! HLE - Hardware locked write error.
+ */
+#define SDIF_MINTSTS_HLE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK)
+#define SDIF_MINTSTS_SBE_MASK                    (0x2000U)
+#define SDIF_MINTSTS_SBE_SHIFT                   (13U)
+/*! SBE - Start-bit error.
+ */
+#define SDIF_MINTSTS_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK)
+#define SDIF_MINTSTS_ACD_MASK                    (0x4000U)
+#define SDIF_MINTSTS_ACD_SHIFT                   (14U)
+/*! ACD - Auto command done.
+ */
+#define SDIF_MINTSTS_ACD(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK)
+#define SDIF_MINTSTS_EBE_MASK                    (0x8000U)
+#define SDIF_MINTSTS_EBE_SHIFT                   (15U)
+/*! EBE - End-bit error (read)/write no CRC.
+ */
+#define SDIF_MINTSTS_EBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK)
+#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK         (0x10000U)
+#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT        (16U)
+/*! SDIO_INTERRUPT - Interrupt from SDIO card.
+ */
+#define SDIF_MINTSTS_SDIO_INTERRUPT(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK)
+/*! @} */
+
+/*! @name RINTSTS - Raw Interrupt Status register */
+/*! @{ */
+#define SDIF_RINTSTS_CDET_MASK                   (0x1U)
+#define SDIF_RINTSTS_CDET_SHIFT                  (0U)
+/*! CDET - Card detect.
+ */
+#define SDIF_RINTSTS_CDET(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK)
+#define SDIF_RINTSTS_RE_MASK                     (0x2U)
+#define SDIF_RINTSTS_RE_SHIFT                    (1U)
+/*! RE - Response error.
+ */
+#define SDIF_RINTSTS_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK)
+#define SDIF_RINTSTS_CDONE_MASK                  (0x4U)
+#define SDIF_RINTSTS_CDONE_SHIFT                 (2U)
+/*! CDONE - Command done.
+ */
+#define SDIF_RINTSTS_CDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK)
+#define SDIF_RINTSTS_DTO_MASK                    (0x8U)
+#define SDIF_RINTSTS_DTO_SHIFT                   (3U)
+/*! DTO - Data transfer over.
+ */
+#define SDIF_RINTSTS_DTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK)
+#define SDIF_RINTSTS_TXDR_MASK                   (0x10U)
+#define SDIF_RINTSTS_TXDR_SHIFT                  (4U)
+/*! TXDR - Transmit FIFO data request.
+ */
+#define SDIF_RINTSTS_TXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK)
+#define SDIF_RINTSTS_RXDR_MASK                   (0x20U)
+#define SDIF_RINTSTS_RXDR_SHIFT                  (5U)
+/*! RXDR - Receive FIFO data request.
+ */
+#define SDIF_RINTSTS_RXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK)
+#define SDIF_RINTSTS_RCRC_MASK                   (0x40U)
+#define SDIF_RINTSTS_RCRC_SHIFT                  (6U)
+/*! RCRC - Response CRC error.
+ */
+#define SDIF_RINTSTS_RCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK)
+#define SDIF_RINTSTS_DCRC_MASK                   (0x80U)
+#define SDIF_RINTSTS_DCRC_SHIFT                  (7U)
+/*! DCRC - Data CRC error.
+ */
+#define SDIF_RINTSTS_DCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK)
+#define SDIF_RINTSTS_RTO_BAR_MASK                (0x100U)
+#define SDIF_RINTSTS_RTO_BAR_SHIFT               (8U)
+/*! RTO_BAR - Response time-out (RTO)/Boot Ack Received (BAR).
+ */
+#define SDIF_RINTSTS_RTO_BAR(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK)
+#define SDIF_RINTSTS_DRTO_BDS_MASK               (0x200U)
+#define SDIF_RINTSTS_DRTO_BDS_SHIFT              (9U)
+/*! DRTO_BDS - Data read time-out (DRTO)/Boot Data Start (BDS).
+ */
+#define SDIF_RINTSTS_DRTO_BDS(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK)
+#define SDIF_RINTSTS_HTO_MASK                    (0x400U)
+#define SDIF_RINTSTS_HTO_SHIFT                   (10U)
+/*! HTO - Data starvation-by-host time-out (HTO).
+ */
+#define SDIF_RINTSTS_HTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK)
+#define SDIF_RINTSTS_FRUN_MASK                   (0x800U)
+#define SDIF_RINTSTS_FRUN_SHIFT                  (11U)
+/*! FRUN - FIFO underrun/overrun error.
+ */
+#define SDIF_RINTSTS_FRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK)
+#define SDIF_RINTSTS_HLE_MASK                    (0x1000U)
+#define SDIF_RINTSTS_HLE_SHIFT                   (12U)
+/*! HLE - Hardware locked write error.
+ */
+#define SDIF_RINTSTS_HLE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK)
+#define SDIF_RINTSTS_SBE_MASK                    (0x2000U)
+#define SDIF_RINTSTS_SBE_SHIFT                   (13U)
+/*! SBE - Start-bit error.
+ */
+#define SDIF_RINTSTS_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK)
+#define SDIF_RINTSTS_ACD_MASK                    (0x4000U)
+#define SDIF_RINTSTS_ACD_SHIFT                   (14U)
+/*! ACD - Auto command done.
+ */
+#define SDIF_RINTSTS_ACD(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK)
+#define SDIF_RINTSTS_EBE_MASK                    (0x8000U)
+#define SDIF_RINTSTS_EBE_SHIFT                   (15U)
+/*! EBE - End-bit error (read)/write no CRC.
+ */
+#define SDIF_RINTSTS_EBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK)
+#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK         (0x10000U)
+#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT        (16U)
+/*! SDIO_INTERRUPT - Interrupt from SDIO card.
+ */
+#define SDIF_RINTSTS_SDIO_INTERRUPT(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK)
+/*! @} */
+
+/*! @name STATUS - Status register */
+/*! @{ */
+#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK       (0x1U)
+#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT      (0U)
+/*! FIFO_RX_WATERMARK - FIFO reached Receive watermark level; not qualified with data transfer.
+ */
+#define SDIF_STATUS_FIFO_RX_WATERMARK(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK)
+#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK       (0x2U)
+#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT      (1U)
+/*! FIFO_TX_WATERMARK - FIFO reached Transmit watermark level; not qualified with data transfer.
+ */
+#define SDIF_STATUS_FIFO_TX_WATERMARK(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK)
+#define SDIF_STATUS_FIFO_EMPTY_MASK              (0x4U)
+#define SDIF_STATUS_FIFO_EMPTY_SHIFT             (2U)
+/*! FIFO_EMPTY - FIFO is empty status.
+ */
+#define SDIF_STATUS_FIFO_EMPTY(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK)
+#define SDIF_STATUS_FIFO_FULL_MASK               (0x8U)
+#define SDIF_STATUS_FIFO_FULL_SHIFT              (3U)
+/*! FIFO_FULL - FIFO is full status.
+ */
+#define SDIF_STATUS_FIFO_FULL(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK)
+#define SDIF_STATUS_CMDFSMSTATES_MASK            (0xF0U)
+#define SDIF_STATUS_CMDFSMSTATES_SHIFT           (4U)
+/*! CMDFSMSTATES - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx
+ *    cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 -
+ *    Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp
+ *    crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The
+ *    command FSM state is represented using 19 bits.
+ */
+#define SDIF_STATUS_CMDFSMSTATES(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK)
+#define SDIF_STATUS_DATA_3_STATUS_MASK           (0x100U)
+#define SDIF_STATUS_DATA_3_STATUS_SHIFT          (8U)
+/*! DATA_3_STATUS - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present.
+ */
+#define SDIF_STATUS_DATA_3_STATUS(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK)
+#define SDIF_STATUS_DATA_BUSY_MASK               (0x200U)
+#define SDIF_STATUS_DATA_BUSY_SHIFT              (9U)
+/*! DATA_BUSY - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy.
+ */
+#define SDIF_STATUS_DATA_BUSY(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK)
+#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK      (0x400U)
+#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT     (10U)
+/*! DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy.
+ */
+#define SDIF_STATUS_DATA_STATE_MC_BUSY(x)        (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK)
+#define SDIF_STATUS_RESPONSE_INDEX_MASK          (0x1F800U)
+#define SDIF_STATUS_RESPONSE_INDEX_SHIFT         (11U)
+/*! RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core.
+ */
+#define SDIF_STATUS_RESPONSE_INDEX(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
+#define SDIF_STATUS_FIFO_COUNT_MASK              (0x3FFE0000U)
+#define SDIF_STATUS_FIFO_COUNT_SHIFT             (17U)
+/*! FIFO_COUNT - FIFO count - Number of filled locations in FIFO.
+ */
+#define SDIF_STATUS_FIFO_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK)
+#define SDIF_STATUS_DMA_ACK_MASK                 (0x40000000U)
+#define SDIF_STATUS_DMA_ACK_SHIFT                (30U)
+/*! DMA_ACK - DMA acknowledge signal state.
+ */
+#define SDIF_STATUS_DMA_ACK(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK)
+#define SDIF_STATUS_DMA_REQ_MASK                 (0x80000000U)
+#define SDIF_STATUS_DMA_REQ_SHIFT                (31U)
+/*! DMA_REQ - DMA request signal state.
+ */
+#define SDIF_STATUS_DMA_REQ(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK)
+/*! @} */
+
+/*! @name FIFOTH - FIFO Threshold Watermark register */
+/*! @{ */
+#define SDIF_FIFOTH_TX_WMARK_MASK                (0xFFFU)
+#define SDIF_FIFOTH_TX_WMARK_SHIFT               (0U)
+/*! TX_WMARK - FIFO threshold watermark level when transmitting data to card.
+ */
+#define SDIF_FIFOTH_TX_WMARK(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK)
+#define SDIF_FIFOTH_RX_WMARK_MASK                (0xFFF0000U)
+#define SDIF_FIFOTH_RX_WMARK_SHIFT               (16U)
+/*! RX_WMARK - FIFO threshold watermark level when receiving data to card.
+ */
+#define SDIF_FIFOTH_RX_WMARK(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK)
+#define SDIF_FIFOTH_DMA_MTS_MASK                 (0x70000000U)
+#define SDIF_FIFOTH_DMA_MTS_SHIFT                (28U)
+/*! DMA_MTS - Burst size of multiple transaction; should be programmed same as DW-DMA controller
+ *    multiple-transaction-size SRC/DEST_MSIZE.
+ */
+#define SDIF_FIFOTH_DMA_MTS(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK)
+/*! @} */
+
+/*! @name CDETECT - Card Detect register */
+/*! @{ */
+#define SDIF_CDETECT_CARD_DETECT_MASK            (0x1U)
+#define SDIF_CDETECT_CARD_DETECT_SHIFT           (0U)
+/*! CARD_DETECT - Card detect.
+ */
+#define SDIF_CDETECT_CARD_DETECT(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD_DETECT_SHIFT)) & SDIF_CDETECT_CARD_DETECT_MASK)
+/*! @} */
+
+/*! @name WRTPRT - Write Protect register */
+/*! @{ */
+#define SDIF_WRTPRT_WRITE_PROTECT_MASK           (0x1U)
+#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT          (0U)
+/*! WRITE_PROTECT - Write protect.
+ */
+#define SDIF_WRTPRT_WRITE_PROTECT(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK)
+/*! @} */
+
+/*! @name TCBCNT - Transferred CIU Card Byte Count register */
+/*! @{ */
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK   (0xFFFFFFFFU)
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT  (0U)
+/*! TRANS_CARD_BYTE_COUNT - Number of bytes transferred by CIU unit to card.
+ */
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK)
+/*! @} */
+
+/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */
+/*! @{ */
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK   (0xFFFFFFFFU)
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT  (0U)
+/*! TRANS_FIFO_BYTE_COUNT - Number of bytes transferred between Host/DMA memory and BIU FIFO.
+ */
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK)
+/*! @} */
+
+/*! @name DEBNCE - Debounce Count register */
+/*! @{ */
+#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK          (0xFFFFFFU)
+#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT         (0U)
+/*! DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms.
+ */
+#define SDIF_DEBNCE_DEBOUNCE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK)
+/*! @} */
+
+/*! @name RST_N - Hardware Reset */
+/*! @{ */
+#define SDIF_RST_N_CARD_RESET_MASK               (0x1U)
+#define SDIF_RST_N_CARD_RESET_SHIFT              (0U)
+/*! CARD_RESET - Hardware reset.
+ */
+#define SDIF_RST_N_CARD_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK)
+/*! @} */
+
+/*! @name BMOD - Bus Mode register */
+/*! @{ */
+#define SDIF_BMOD_SWR_MASK                       (0x1U)
+#define SDIF_BMOD_SWR_SHIFT                      (0U)
+/*! SWR - Software Reset.
+ */
+#define SDIF_BMOD_SWR(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK)
+#define SDIF_BMOD_FB_MASK                        (0x2U)
+#define SDIF_BMOD_FB_SHIFT                       (1U)
+/*! FB - Fixed Burst.
+ */
+#define SDIF_BMOD_FB(x)                          (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK)
+#define SDIF_BMOD_DSL_MASK                       (0x7CU)
+#define SDIF_BMOD_DSL_SHIFT                      (2U)
+/*! DSL - Descriptor Skip Length.
+ */
+#define SDIF_BMOD_DSL(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK)
+#define SDIF_BMOD_DE_MASK                        (0x80U)
+#define SDIF_BMOD_DE_SHIFT                       (7U)
+/*! DE - SD/MMC DMA Enable.
+ */
+#define SDIF_BMOD_DE(x)                          (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK)
+#define SDIF_BMOD_PBL_MASK                       (0x700U)
+#define SDIF_BMOD_PBL_SHIFT                      (8U)
+/*! PBL - Programmable Burst Length.
+ */
+#define SDIF_BMOD_PBL(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK)
+/*! @} */
+
+/*! @name PLDMND - Poll Demand register */
+/*! @{ */
+#define SDIF_PLDMND_PD_MASK                      (0xFFFFFFFFU)
+#define SDIF_PLDMND_PD_SHIFT                     (0U)
+/*! PD - Poll Demand.
+ */
+#define SDIF_PLDMND_PD(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK)
+/*! @} */
+
+/*! @name DBADDR - Descriptor List Base Address register */
+/*! @{ */
+#define SDIF_DBADDR_SDL_MASK                     (0xFFFFFFFFU)
+#define SDIF_DBADDR_SDL_SHIFT                    (0U)
+/*! SDL - Start of Descriptor List.
+ */
+#define SDIF_DBADDR_SDL(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK)
+/*! @} */
+
+/*! @name IDSTS - Internal DMAC Status register */
+/*! @{ */
+#define SDIF_IDSTS_TI_MASK                       (0x1U)
+#define SDIF_IDSTS_TI_SHIFT                      (0U)
+/*! TI - Transmit Interrupt.
+ */
+#define SDIF_IDSTS_TI(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK)
+#define SDIF_IDSTS_RI_MASK                       (0x2U)
+#define SDIF_IDSTS_RI_SHIFT                      (1U)
+/*! RI - Receive Interrupt.
+ */
+#define SDIF_IDSTS_RI(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK)
+#define SDIF_IDSTS_FBE_MASK                      (0x4U)
+#define SDIF_IDSTS_FBE_SHIFT                     (2U)
+/*! FBE - Fatal Bus Error Interrupt.
+ */
+#define SDIF_IDSTS_FBE(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK)
+#define SDIF_IDSTS_DU_MASK                       (0x10U)
+#define SDIF_IDSTS_DU_SHIFT                      (4U)
+/*! DU - Descriptor Unavailable Interrupt.
+ */
+#define SDIF_IDSTS_DU(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK)
+#define SDIF_IDSTS_CES_MASK                      (0x20U)
+#define SDIF_IDSTS_CES_SHIFT                     (5U)
+/*! CES - Card Error Summary.
+ */
+#define SDIF_IDSTS_CES(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK)
+#define SDIF_IDSTS_NIS_MASK                      (0x100U)
+#define SDIF_IDSTS_NIS_SHIFT                     (8U)
+/*! NIS - Normal Interrupt Summary.
+ */
+#define SDIF_IDSTS_NIS(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK)
+#define SDIF_IDSTS_AIS_MASK                      (0x200U)
+#define SDIF_IDSTS_AIS_SHIFT                     (9U)
+/*! AIS - Abnormal Interrupt Summary.
+ */
+#define SDIF_IDSTS_AIS(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK)
+#define SDIF_IDSTS_EB_MASK                       (0x1C00U)
+#define SDIF_IDSTS_EB_SHIFT                      (10U)
+/*! EB - Error Bits.
+ */
+#define SDIF_IDSTS_EB(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK)
+#define SDIF_IDSTS_FSM_MASK                      (0x1E000U)
+#define SDIF_IDSTS_FSM_SHIFT                     (13U)
+/*! FSM - DMAC state machine present state.
+ */
+#define SDIF_IDSTS_FSM(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK)
+/*! @} */
+
+/*! @name IDINTEN - Internal DMAC Interrupt Enable register */
+/*! @{ */
+#define SDIF_IDINTEN_TI_MASK                     (0x1U)
+#define SDIF_IDINTEN_TI_SHIFT                    (0U)
+/*! TI - Transmit Interrupt Enable.
+ */
+#define SDIF_IDINTEN_TI(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK)
+#define SDIF_IDINTEN_RI_MASK                     (0x2U)
+#define SDIF_IDINTEN_RI_SHIFT                    (1U)
+/*! RI - Receive Interrupt Enable.
+ */
+#define SDIF_IDINTEN_RI(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK)
+#define SDIF_IDINTEN_FBE_MASK                    (0x4U)
+#define SDIF_IDINTEN_FBE_SHIFT                   (2U)
+/*! FBE - Fatal Bus Error Enable.
+ */
+#define SDIF_IDINTEN_FBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK)
+#define SDIF_IDINTEN_DU_MASK                     (0x10U)
+#define SDIF_IDINTEN_DU_SHIFT                    (4U)
+/*! DU - Descriptor Unavailable Interrupt.
+ */
+#define SDIF_IDINTEN_DU(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK)
+#define SDIF_IDINTEN_CES_MASK                    (0x20U)
+#define SDIF_IDINTEN_CES_SHIFT                   (5U)
+/*! CES - Card Error summary Interrupt Enable.
+ */
+#define SDIF_IDINTEN_CES(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK)
+#define SDIF_IDINTEN_NIS_MASK                    (0x100U)
+#define SDIF_IDINTEN_NIS_SHIFT                   (8U)
+/*! NIS - Normal Interrupt Summary Enable.
+ */
+#define SDIF_IDINTEN_NIS(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK)
+#define SDIF_IDINTEN_AIS_MASK                    (0x200U)
+#define SDIF_IDINTEN_AIS_SHIFT                   (9U)
+/*! AIS - Abnormal Interrupt Summary Enable.
+ */
+#define SDIF_IDINTEN_AIS(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK)
+/*! @} */
+
+/*! @name DSCADDR - Current Host Descriptor Address register */
+/*! @{ */
+#define SDIF_DSCADDR_HDA_MASK                    (0xFFFFFFFFU)
+#define SDIF_DSCADDR_HDA_SHIFT                   (0U)
+/*! HDA - Host Descriptor Address Pointer.
+ */
+#define SDIF_DSCADDR_HDA(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK)
+/*! @} */
+
+/*! @name BUFADDR - Current Buffer Descriptor Address register */
+/*! @{ */
+#define SDIF_BUFADDR_HBA_MASK                    (0xFFFFFFFFU)
+#define SDIF_BUFADDR_HBA_SHIFT                   (0U)
+/*! HBA - Host Buffer Address Pointer.
+ */
+#define SDIF_BUFADDR_HBA(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK)
+/*! @} */
+
+/*! @name CARDTHRCTL - Card Threshold Control */
+/*! @{ */
+#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK         (0x1U)
+#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT        (0U)
+/*! CARDRDTHREN - Card Read Threshold Enable.
+ */
+#define SDIF_CARDTHRCTL_CARDRDTHREN(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK)
+#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK         (0x2U)
+#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT        (1U)
+/*! BSYCLRINTEN - Busy Clear Interrupt Enable.
+ */
+#define SDIF_CARDTHRCTL_BSYCLRINTEN(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK)
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK       (0xFF0000U)
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT      (16U)
+/*! CARDTHRESHOLD - Card Threshold size.
+ */
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK)
+/*! @} */
+
+/*! @name BACKENDPWR - Power control */
+/*! @{ */
+#define SDIF_BACKENDPWR_BACKENDPWR_MASK          (0x1U)
+#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT         (0U)
+/*! BACKENDPWR - Back-end Power control for card application.
+ */
+#define SDIF_BACKENDPWR_BACKENDPWR(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK)
+/*! @} */
+
+/*! @name FIFO - SDIF FIFO */
+/*! @{ */
+#define SDIF_FIFO_DATA_MASK                      (0xFFFFFFFFU)
+#define SDIF_FIFO_DATA_SHIFT                     (0U)
+/*! DATA - SDIF FIFO.
+ */
+#define SDIF_FIFO_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK)
+/*! @} */
+
+/* The count of SDIF_FIFO */
+#define SDIF_FIFO_COUNT                          (64U)
+
+
+/*!
+ * @}
+ */ /* end of group SDIF_Register_Masks */
+
+
+/* SDIF - Peripheral instance base addresses */
+/** Peripheral SDIF base address */
+#define SDIF_BASE                                (0x4009B000u)
+/** Peripheral SDIF base pointer */
+#define SDIF                                     ((SDIF_Type *)SDIF_BASE)
+/** Array initializer of SDIF peripheral base addresses */
+#define SDIF_BASE_ADDRS                          { SDIF_BASE }
+/** Array initializer of SDIF peripheral base pointers */
+#define SDIF_BASE_PTRS                           { SDIF }
+/** Interrupt vectors for the SDIF peripheral type */
+#define SDIF_IRQS                                { SDIO_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SDIF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SHA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SHA_Peripheral_Access_Layer SHA Peripheral Access Layer
+ * @{
+ */
+
+/** SHA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< Control register, offset: 0x0 */
+  __IO uint32_t STATUS;                            /**< Status register, offset: 0x4 */
+  __IO uint32_t INTENSET;                          /**< Interrupt Enable register, offset: 0x8 */
+  __O  uint32_t INTENCLR;                          /**< Interrupt Clear register, offset: 0xC */
+  __IO uint32_t MEMCTRL;                           /**< Memory Control register, offset: 0x10 */
+  __IO uint32_t MEMADDR;                           /**< Memory Address register, offset: 0x14 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t INDATA;                            /**< Input Data register, offset: 0x20 */
+  __O  uint32_t ALIAS[7];                          /**< Alias register, array offset: 0x24, array step: 0x4 */
+  __I  uint32_t DIGEST[8];                         /**< Digest register, array offset: 0x40, array step: 0x4 */
+} SHA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SHA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SHA_Register_Masks SHA Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control register */
+/*! @{ */
+#define SHA_CTRL_MODE_MASK                       (0x3U)
+#define SHA_CTRL_MODE_SHIFT                      (0U)
+/*! MODE - This field is used to select the operational mode of SHA block.
+ */
+#define SHA_CTRL_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_MODE_SHIFT)) & SHA_CTRL_MODE_MASK)
+#define SHA_CTRL_NEW_MASK                        (0x10U)
+#define SHA_CTRL_NEW_SHIFT                       (4U)
+/*! NEW - When this bit is set, a new hash operation is started.
+ */
+#define SHA_CTRL_NEW(x)                          (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_NEW_SHIFT)) & SHA_CTRL_NEW_MASK)
+#define SHA_CTRL_DMA_MASK                        (0x100U)
+#define SHA_CTRL_DMA_SHIFT                       (8U)
+/*! DMA - When this bit is set, the DMA is used to fill INDATA.
+ */
+#define SHA_CTRL_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_DMA_SHIFT)) & SHA_CTRL_DMA_MASK)
+/*! @} */
+
+/*! @name STATUS - Status register */
+/*! @{ */
+#define SHA_STATUS_WAITING_MASK                  (0x1U)
+#define SHA_STATUS_WAITING_SHIFT                 (0U)
+/*! WAITING - This field indicates if the block is waiting for more data to process.
+ */
+#define SHA_STATUS_WAITING(x)                    (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_WAITING_SHIFT)) & SHA_STATUS_WAITING_MASK)
+#define SHA_STATUS_DIGEST_MASK                   (0x2U)
+#define SHA_STATUS_DIGEST_SHIFT                  (1U)
+/*! DIGEST - This field indicates if a DIGEST is ready and waiting and there is no active next block that has already started.
+ */
+#define SHA_STATUS_DIGEST(x)                     (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_DIGEST_SHIFT)) & SHA_STATUS_DIGEST_MASK)
+#define SHA_STATUS_ERROR_MASK                    (0x4U)
+#define SHA_STATUS_ERROR_SHIFT                   (2U)
+/*! ERROR - This field indicates if an error has occurred.
+ */
+#define SHA_STATUS_ERROR(x)                      (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_ERROR_SHIFT)) & SHA_STATUS_ERROR_MASK)
+/*! @} */
+
+/*! @name INTENSET - Interrupt Enable register */
+/*! @{ */
+#define SHA_INTENSET_WAITING_MASK                (0x1U)
+#define SHA_INTENSET_WAITING_SHIFT               (0U)
+/*! WAITING - This field indicates if interrupt should be enabled when waiting for input data.
+ */
+#define SHA_INTENSET_WAITING(x)                  (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_WAITING_SHIFT)) & SHA_INTENSET_WAITING_MASK)
+#define SHA_INTENSET_DIGEST_MASK                 (0x2U)
+#define SHA_INTENSET_DIGEST_SHIFT                (1U)
+/*! DIGEST - This field indicates if interrupt is generated when Digest is ready (completed a Hash or completed a full sequence).
+ */
+#define SHA_INTENSET_DIGEST(x)                   (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_DIGEST_SHIFT)) & SHA_INTENSET_DIGEST_MASK)
+#define SHA_INTENSET_ERROR_MASK                  (0x4U)
+#define SHA_INTENSET_ERROR_SHIFT                 (2U)
+/*! ERROR - This field indicates if interrupt is generated on an ERROR (as defined in STAT register).
+ */
+#define SHA_INTENSET_ERROR(x)                    (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_ERROR_SHIFT)) & SHA_INTENSET_ERROR_MASK)
+/*! @} */
+
+/*! @name INTENCLR - Interrupt Clear register */
+/*! @{ */
+#define SHA_INTENCLR_WAITING_MASK                (0x1U)
+#define SHA_INTENCLR_WAITING_SHIFT               (0U)
+/*! WAITING - Writing a 1 clears the interrupt enabled by the INTENSET register.
+ */
+#define SHA_INTENCLR_WAITING(x)                  (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_WAITING_SHIFT)) & SHA_INTENCLR_WAITING_MASK)
+#define SHA_INTENCLR_DIGEST_MASK                 (0x2U)
+#define SHA_INTENCLR_DIGEST_SHIFT                (1U)
+/*! DIGEST - Writing a 1 clears the interrupt enabled by the INTENSET register.
+ */
+#define SHA_INTENCLR_DIGEST(x)                   (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_DIGEST_SHIFT)) & SHA_INTENCLR_DIGEST_MASK)
+#define SHA_INTENCLR_ERROR_MASK                  (0x4U)
+#define SHA_INTENCLR_ERROR_SHIFT                 (2U)
+/*! ERROR - Writing a 1 clears the interrupt enabled by the INTENSET register.
+ */
+#define SHA_INTENCLR_ERROR(x)                    (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_ERROR_SHIFT)) & SHA_INTENCLR_ERROR_MASK)
+/*! @} */
+
+/*! @name MEMCTRL - Memory Control register */
+/*! @{ */
+#define SHA_MEMCTRL_MASTER_MASK                  (0x1U)
+#define SHA_MEMCTRL_MASTER_SHIFT                 (0U)
+/*! MASTER - This field is used to enable SHA block as AHB bus master.
+ */
+#define SHA_MEMCTRL_MASTER(x)                    (((uint32_t)(((uint32_t)(x)) << SHA_MEMCTRL_MASTER_SHIFT)) & SHA_MEMCTRL_MASTER_MASK)
+#define SHA_MEMCTRL_COUNT_MASK                   (0x7FF0000U)
+#define SHA_MEMCTRL_COUNT_SHIFT                  (16U)
+/*! COUNT - This field indicates the number of 512-bit blocks to copy starting at MEMADDR.
+ */
+#define SHA_MEMCTRL_COUNT(x)                     (((uint32_t)(((uint32_t)(x)) << SHA_MEMCTRL_COUNT_SHIFT)) & SHA_MEMCTRL_COUNT_MASK)
+/*! @} */
+
+/*! @name MEMADDR - Memory Address register */
+/*! @{ */
+#define SHA_MEMADDR_BASEADDR_MASK                (0xFFFFFFFFU)
+#define SHA_MEMADDR_BASEADDR_SHIFT               (0U)
+/*! BASEADDR - This field indicates the base address in Internal Flash, SRAM0, SRAMX, or SPIFI to start copying from.
+ */
+#define SHA_MEMADDR_BASEADDR(x)                  (((uint32_t)(((uint32_t)(x)) << SHA_MEMADDR_BASEADDR_SHIFT)) & SHA_MEMADDR_BASEADDR_MASK)
+/*! @} */
+
+/*! @name INDATA - Input Data register */
+/*! @{ */
+#define SHA_INDATA_DATA_MASK                     (0xFFFFFFFFU)
+#define SHA_INDATA_DATA_SHIFT                    (0U)
+/*! DATA - In this field the next word is written in little-endian format.
+ */
+#define SHA_INDATA_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << SHA_INDATA_DATA_SHIFT)) & SHA_INDATA_DATA_MASK)
+/*! @} */
+
+/*! @name ALIAS - Alias register */
+/*! @{ */
+#define SHA_ALIAS_DATA_MASK                      (0xFFFFFFFFU)
+#define SHA_ALIAS_DATA_SHIFT                     (0U)
+/*! DATA - In this field the next word is written in little-endian format.
+ */
+#define SHA_ALIAS_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << SHA_ALIAS_DATA_SHIFT)) & SHA_ALIAS_DATA_MASK)
+/*! @} */
+
+/* The count of SHA_ALIAS */
+#define SHA_ALIAS_COUNT                          (7U)
+
+/*! @name DIGEST - Digest register */
+/*! @{ */
+#define SHA_DIGEST_DIGEST_MASK                   (0xFFFFFFFFU)
+#define SHA_DIGEST_DIGEST_SHIFT                  (0U)
+/*! DIGEST - This field contains one word of the Digest.
+ */
+#define SHA_DIGEST_DIGEST(x)                     (((uint32_t)(((uint32_t)(x)) << SHA_DIGEST_DIGEST_SHIFT)) & SHA_DIGEST_DIGEST_MASK)
+/*! @} */
+
+/* The count of SHA_DIGEST */
+#define SHA_DIGEST_COUNT                         (8U)
+
+
+/*!
+ * @}
+ */ /* end of group SHA_Register_Masks */
+
+
+/* SHA - Peripheral instance base addresses */
+/** Peripheral SHA0 base address */
+#define SHA0_BASE                                (0x400A4000u)
+/** Peripheral SHA0 base pointer */
+#define SHA0                                     ((SHA_Type *)SHA0_BASE)
+/** Array initializer of SHA peripheral base addresses */
+#define SHA_BASE_ADDRS                           { SHA0_BASE }
+/** Array initializer of SHA peripheral base pointers */
+#define SHA_BASE_PTRS                            { SHA0 }
+
+/*!
+ * @}
+ */ /* end of group SHA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMARTCARD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMARTCARD_Peripheral_Access_Layer SMARTCARD Peripheral Access Layer
+ * @{
+ */
+
+/** SMARTCARD - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    __IO uint32_t DLL;                               /**< Divisor Latch LSB, offset: 0x0 */
+    __I  uint32_t RBR;                               /**< Receiver Buffer Register, offset: 0x0 */
+    __O  uint32_t THR;                               /**< Transmit Holding Register, offset: 0x0 */
+  };
+  union {                                          /* offset: 0x4 */
+    __IO uint32_t DLM;                               /**< Divisor Latch MSB, offset: 0x4 */
+    __IO uint32_t IER;                               /**< Interrupt Enable Register, offset: 0x4 */
+  };
+  union {                                          /* offset: 0x8 */
+    __O  uint32_t FCR;                               /**< FIFO Control Register, offset: 0x8 */
+    __I  uint32_t IIR;                               /**< Interrupt ID Register, offset: 0x8 */
+  };
+  __IO uint32_t LCR;                               /**< Line Control Register, offset: 0xC */
+       uint8_t RESERVED_0[4];
+  __I  uint32_t LSR;                               /**< Line Status Register, offset: 0x14 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SCR;                               /**< Scratch Pad Register, offset: 0x1C */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t OSR;                               /**< Oversampling register, offset: 0x2C */
+       uint8_t RESERVED_3[24];
+  __IO uint32_t SCICTRL;                           /**< Smart Card Interface control register, offset: 0x48 */
+} SMARTCARD_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SMARTCARD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMARTCARD_Register_Masks SMARTCARD Register Masks
+ * @{
+ */
+
+/*! @name DLL - Divisor Latch LSB */
+/*! @{ */
+#define SMARTCARD_DLL_DLLSB_MASK                 (0xFFU)
+#define SMARTCARD_DLL_DLLSB_SHIFT                (0U)
+/*! DLLSB - The SCIn Divisor Latch LSB Register, along with the SCInDLM register, determines the baud rate of the SCIn.
+ */
+#define SMARTCARD_DLL_DLLSB(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLL_DLLSB_SHIFT)) & SMARTCARD_DLL_DLLSB_MASK)
+/*! @} */
+
+/*! @name RBR - Receiver Buffer Register */
+/*! @{ */
+#define SMARTCARD_RBR_RBR_MASK                   (0xFFU)
+#define SMARTCARD_RBR_RBR_SHIFT                  (0U)
+/*! RBR - The SCIn Receiver Buffer Register contains the oldest received byte in the SCIn Rx FIFO.
+ */
+#define SMARTCARD_RBR_RBR(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_RBR_RBR_SHIFT)) & SMARTCARD_RBR_RBR_MASK)
+/*! @} */
+
+/*! @name THR - Transmit Holding Register */
+/*! @{ */
+#define SMARTCARD_THR_THR_MASK                   (0xFFU)
+#define SMARTCARD_THR_THR_SHIFT                  (0U)
+/*! THR - Writing to the SCIn Transmit Holding Register causes the data to be stored in the SCIn transmit FIFO.
+ */
+#define SMARTCARD_THR_THR(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_THR_THR_SHIFT)) & SMARTCARD_THR_THR_MASK)
+/*! @} */
+
+/*! @name DLM - Divisor Latch MSB */
+/*! @{ */
+#define SMARTCARD_DLM_DLMSB_MASK                 (0xFFU)
+#define SMARTCARD_DLM_DLMSB_SHIFT                (0U)
+/*! DLMSB - The SCIn Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the SCIn.
+ */
+#define SMARTCARD_DLM_DLMSB(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLM_DLMSB_SHIFT)) & SMARTCARD_DLM_DLMSB_MASK)
+/*! @} */
+
+/*! @name IER - Interrupt Enable Register */
+/*! @{ */
+#define SMARTCARD_IER_RBRIE_MASK                 (0x1U)
+#define SMARTCARD_IER_RBRIE_SHIFT                (0U)
+/*! RBRIE - RBR Interrupt Enable.
+ */
+#define SMARTCARD_IER_RBRIE(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RBRIE_SHIFT)) & SMARTCARD_IER_RBRIE_MASK)
+#define SMARTCARD_IER_THREIE_MASK                (0x2U)
+#define SMARTCARD_IER_THREIE_SHIFT               (1U)
+/*! THREIE - THRE Interrupt Enable.
+ */
+#define SMARTCARD_IER_THREIE(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_THREIE_SHIFT)) & SMARTCARD_IER_THREIE_MASK)
+#define SMARTCARD_IER_RXIE_MASK                  (0x4U)
+#define SMARTCARD_IER_RXIE_SHIFT                 (2U)
+/*! RXIE - RX Line Status Interrupt Enable.
+ */
+#define SMARTCARD_IER_RXIE(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RXIE_SHIFT)) & SMARTCARD_IER_RXIE_MASK)
+/*! @} */
+
+/*! @name FCR - FIFO Control Register */
+/*! @{ */
+#define SMARTCARD_FCR_FIFOEN_MASK                (0x1U)
+#define SMARTCARD_FCR_FIFOEN_SHIFT               (0U)
+/*! FIFOEN - FIFO Enable.
+ */
+#define SMARTCARD_FCR_FIFOEN(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_FIFOEN_SHIFT)) & SMARTCARD_FCR_FIFOEN_MASK)
+#define SMARTCARD_FCR_RXFIFORES_MASK             (0x2U)
+#define SMARTCARD_FCR_RXFIFORES_SHIFT            (1U)
+/*! RXFIFORES - RX FIFO Reset.
+ */
+#define SMARTCARD_FCR_RXFIFORES(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXFIFORES_SHIFT)) & SMARTCARD_FCR_RXFIFORES_MASK)
+#define SMARTCARD_FCR_TXFIFORES_MASK             (0x4U)
+#define SMARTCARD_FCR_TXFIFORES_SHIFT            (2U)
+/*! TXFIFORES - TX FIFO Reset.
+ */
+#define SMARTCARD_FCR_TXFIFORES(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_TXFIFORES_SHIFT)) & SMARTCARD_FCR_TXFIFORES_MASK)
+#define SMARTCARD_FCR_DMAMODE_MASK               (0x8U)
+#define SMARTCARD_FCR_DMAMODE_SHIFT              (3U)
+/*! DMAMODE - DMA Mode Select.
+ */
+#define SMARTCARD_FCR_DMAMODE(x)                 (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_DMAMODE_SHIFT)) & SMARTCARD_FCR_DMAMODE_MASK)
+#define SMARTCARD_FCR_RXTRIGLVL_MASK             (0xC0U)
+#define SMARTCARD_FCR_RXTRIGLVL_SHIFT            (6U)
+/*! RXTRIGLVL - RX Trigger Level.
+ */
+#define SMARTCARD_FCR_RXTRIGLVL(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXTRIGLVL_SHIFT)) & SMARTCARD_FCR_RXTRIGLVL_MASK)
+/*! @} */
+
+/*! @name IIR - Interrupt ID Register */
+/*! @{ */
+#define SMARTCARD_IIR_INTSTATUS_MASK             (0x1U)
+#define SMARTCARD_IIR_INTSTATUS_SHIFT            (0U)
+/*! INTSTATUS - Interrupt status.
+ */
+#define SMARTCARD_IIR_INTSTATUS(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTSTATUS_SHIFT)) & SMARTCARD_IIR_INTSTATUS_MASK)
+#define SMARTCARD_IIR_INTID_MASK                 (0xEU)
+#define SMARTCARD_IIR_INTID_SHIFT                (1U)
+/*! INTID - Interrupt identification.
+ */
+#define SMARTCARD_IIR_INTID(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTID_SHIFT)) & SMARTCARD_IIR_INTID_MASK)
+#define SMARTCARD_IIR_FIFOENABLE_MASK            (0xC0U)
+#define SMARTCARD_IIR_FIFOENABLE_SHIFT           (6U)
+/*! FIFOENABLE - Copies of SCInFCR[0].
+ */
+#define SMARTCARD_IIR_FIFOENABLE(x)              (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_FIFOENABLE_SHIFT)) & SMARTCARD_IIR_FIFOENABLE_MASK)
+/*! @} */
+
+/*! @name LCR - Line Control Register */
+/*! @{ */
+#define SMARTCARD_LCR_WLS_MASK                   (0x3U)
+#define SMARTCARD_LCR_WLS_SHIFT                  (0U)
+/*! WLS - Word Length Select.
+ */
+#define SMARTCARD_LCR_WLS(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_WLS_SHIFT)) & SMARTCARD_LCR_WLS_MASK)
+#define SMARTCARD_LCR_SBS_MASK                   (0x4U)
+#define SMARTCARD_LCR_SBS_SHIFT                  (2U)
+/*! SBS - Stop Bit Select.
+ */
+#define SMARTCARD_LCR_SBS(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_SBS_SHIFT)) & SMARTCARD_LCR_SBS_MASK)
+#define SMARTCARD_LCR_PE_MASK                    (0x8U)
+#define SMARTCARD_LCR_PE_SHIFT                   (3U)
+/*! PE - Parity Enable.
+ */
+#define SMARTCARD_LCR_PE(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PE_SHIFT)) & SMARTCARD_LCR_PE_MASK)
+#define SMARTCARD_LCR_PS_MASK                    (0x30U)
+#define SMARTCARD_LCR_PS_SHIFT                   (4U)
+/*! PS - Parity Select.
+ */
+#define SMARTCARD_LCR_PS(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PS_SHIFT)) & SMARTCARD_LCR_PS_MASK)
+#define SMARTCARD_LCR_DLAB_MASK                  (0x80U)
+#define SMARTCARD_LCR_DLAB_SHIFT                 (7U)
+/*! DLAB - Divisor Latch Access Bit.
+ */
+#define SMARTCARD_LCR_DLAB(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_DLAB_SHIFT)) & SMARTCARD_LCR_DLAB_MASK)
+/*! @} */
+
+/*! @name LSR - Line Status Register */
+/*! @{ */
+#define SMARTCARD_LSR_RDR_MASK                   (0x1U)
+#define SMARTCARD_LSR_RDR_SHIFT                  (0U)
+/*! RDR - Receiver Data Ready.
+ */
+#define SMARTCARD_LSR_RDR(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RDR_SHIFT)) & SMARTCARD_LSR_RDR_MASK)
+#define SMARTCARD_LSR_OE_MASK                    (0x2U)
+#define SMARTCARD_LSR_OE_SHIFT                   (1U)
+/*! OE - Overrun Error.
+ */
+#define SMARTCARD_LSR_OE(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_OE_SHIFT)) & SMARTCARD_LSR_OE_MASK)
+#define SMARTCARD_LSR_PE_MASK                    (0x4U)
+#define SMARTCARD_LSR_PE_SHIFT                   (2U)
+/*! PE - Parity Error.
+ */
+#define SMARTCARD_LSR_PE(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_PE_SHIFT)) & SMARTCARD_LSR_PE_MASK)
+#define SMARTCARD_LSR_FE_MASK                    (0x8U)
+#define SMARTCARD_LSR_FE_SHIFT                   (3U)
+/*! FE - Framing Error.
+ */
+#define SMARTCARD_LSR_FE(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_FE_SHIFT)) & SMARTCARD_LSR_FE_MASK)
+#define SMARTCARD_LSR_THRE_MASK                  (0x20U)
+#define SMARTCARD_LSR_THRE_SHIFT                 (5U)
+/*! THRE - Transmitter Holding Register Empty.
+ */
+#define SMARTCARD_LSR_THRE(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_THRE_SHIFT)) & SMARTCARD_LSR_THRE_MASK)
+#define SMARTCARD_LSR_TEMT_MASK                  (0x40U)
+#define SMARTCARD_LSR_TEMT_SHIFT                 (6U)
+/*! TEMT - Transmitter Empty.
+ */
+#define SMARTCARD_LSR_TEMT(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_TEMT_SHIFT)) & SMARTCARD_LSR_TEMT_MASK)
+#define SMARTCARD_LSR_RXFE_MASK                  (0x80U)
+#define SMARTCARD_LSR_RXFE_SHIFT                 (7U)
+/*! RXFE - Error in RX FIFO.
+ */
+#define SMARTCARD_LSR_RXFE(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RXFE_SHIFT)) & SMARTCARD_LSR_RXFE_MASK)
+/*! @} */
+
+/*! @name SCR - Scratch Pad Register */
+/*! @{ */
+#define SMARTCARD_SCR_PAD_MASK                   (0xFFU)
+#define SMARTCARD_SCR_PAD_SHIFT                  (0U)
+/*! PAD - A readable, writable byte.
+ */
+#define SMARTCARD_SCR_PAD(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCR_PAD_SHIFT)) & SMARTCARD_SCR_PAD_MASK)
+/*! @} */
+
+/*! @name OSR - Oversampling register */
+/*! @{ */
+#define SMARTCARD_OSR_OSFRAC_MASK                (0xEU)
+#define SMARTCARD_OSR_OSFRAC_SHIFT               (1U)
+/*! OSFRAC - Fractional part of the oversampling ratio, in units of 1/8th of an input clock period.
+ */
+#define SMARTCARD_OSR_OSFRAC(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSFRAC_SHIFT)) & SMARTCARD_OSR_OSFRAC_MASK)
+#define SMARTCARD_OSR_OSINT_MASK                 (0xF0U)
+#define SMARTCARD_OSR_OSINT_SHIFT                (4U)
+/*! OSINT - Integer part of the oversampling ratio, minus 1.
+ */
+#define SMARTCARD_OSR_OSINT(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSINT_SHIFT)) & SMARTCARD_OSR_OSINT_MASK)
+#define SMARTCARD_OSR_FDINT_MASK                 (0x7F00U)
+#define SMARTCARD_OSR_FDINT_SHIFT                (8U)
+/*! FDINT - These bits act as a more-significant extension of the OSint field, allowing an
+ *    oversampling ratio up to 2048 as required by ISO7816-3.
+ */
+#define SMARTCARD_OSR_FDINT(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_FDINT_SHIFT)) & SMARTCARD_OSR_FDINT_MASK)
+/*! @} */
+
+/*! @name SCICTRL - Smart Card Interface control register */
+/*! @{ */
+#define SMARTCARD_SCICTRL_SCIEN_MASK             (0x1U)
+#define SMARTCARD_SCICTRL_SCIEN_SHIFT            (0U)
+/*! SCIEN - Smart Card Interface Enable.
+ */
+#define SMARTCARD_SCICTRL_SCIEN(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_SCIEN_SHIFT)) & SMARTCARD_SCICTRL_SCIEN_MASK)
+#define SMARTCARD_SCICTRL_NACKDIS_MASK           (0x2U)
+#define SMARTCARD_SCICTRL_NACKDIS_SHIFT          (1U)
+/*! NACKDIS - NACK response disable.
+ */
+#define SMARTCARD_SCICTRL_NACKDIS(x)             (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_NACKDIS_SHIFT)) & SMARTCARD_SCICTRL_NACKDIS_MASK)
+#define SMARTCARD_SCICTRL_PROTSEL_MASK           (0x4U)
+#define SMARTCARD_SCICTRL_PROTSEL_SHIFT          (2U)
+/*! PROTSEL - Protocol selection as defined in the ISO7816-3 standard.
+ */
+#define SMARTCARD_SCICTRL_PROTSEL(x)             (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_PROTSEL_SHIFT)) & SMARTCARD_SCICTRL_PROTSEL_MASK)
+#define SMARTCARD_SCICTRL_TXRETRY_MASK           (0xE0U)
+#define SMARTCARD_SCICTRL_TXRETRY_SHIFT          (5U)
+/*! TXRETRY - Maximum number of retransmissions in case of a negative acknowledge (protocol T=0).
+ */
+#define SMARTCARD_SCICTRL_TXRETRY(x)             (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_TXRETRY_SHIFT)) & SMARTCARD_SCICTRL_TXRETRY_MASK)
+#define SMARTCARD_SCICTRL_GUARDTIME_MASK         (0xFF00U)
+#define SMARTCARD_SCICTRL_GUARDTIME_SHIFT        (8U)
+/*! GUARDTIME - Extra guard time.
+ */
+#define SMARTCARD_SCICTRL_GUARDTIME(x)           (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_GUARDTIME_SHIFT)) & SMARTCARD_SCICTRL_GUARDTIME_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SMARTCARD_Register_Masks */
+
+
+/* SMARTCARD - Peripheral instance base addresses */
+/** Peripheral SMARTCARD0 base address */
+#define SMARTCARD0_BASE                          (0x40036000u)
+/** Peripheral SMARTCARD0 base pointer */
+#define SMARTCARD0                               ((SMARTCARD_Type *)SMARTCARD0_BASE)
+/** Peripheral SMARTCARD1 base address */
+#define SMARTCARD1_BASE                          (0x40037000u)
+/** Peripheral SMARTCARD1 base pointer */
+#define SMARTCARD1                               ((SMARTCARD_Type *)SMARTCARD1_BASE)
+/** Array initializer of SMARTCARD peripheral base addresses */
+#define SMARTCARD_BASE_ADDRS                     { SMARTCARD0_BASE, SMARTCARD1_BASE }
+/** Array initializer of SMARTCARD peripheral base pointers */
+#define SMARTCARD_BASE_PTRS                      { SMARTCARD0, SMARTCARD1 }
+/** Interrupt vectors for the SMARTCARD peripheral type */
+#define SMARTCARD_IRQS                           { SMARTCARD0_IRQn, SMARTCARD1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SMARTCARD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[1024];
+  __IO uint32_t CFG;                               /**< SPI Configuration register, offset: 0x400 */
+  __IO uint32_t DLY;                               /**< SPI Delay register, offset: 0x404 */
+  __IO uint32_t STAT;                              /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */
+  __IO uint32_t INTENSET;                          /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */
+  __O  uint32_t INTENCLR;                          /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t DIV;                               /**< SPI clock Divider, offset: 0x424 */
+  __I  uint32_t INTSTAT;                           /**< SPI Interrupt Status, offset: 0x428 */
+       uint8_t RESERVED_2[2516];
+  __IO uint32_t FIFOCFG;                           /**< FIFO configuration and enable register., offset: 0xE00 */
+  __IO uint32_t FIFOSTAT;                          /**< FIFO status register., offset: 0xE04 */
+  __IO uint32_t FIFOTRIG;                          /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t FIFOINTENSET;                      /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+  __IO uint32_t FIFOINTENCLR;                      /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+  __I  uint32_t FIFOINTSTAT;                       /**< FIFO interrupt status register., offset: 0xE18 */
+       uint8_t RESERVED_4[4];
+  __O  uint32_t FIFOWR;                            /**< FIFO write data., offset: 0xE20 */
+       uint8_t RESERVED_5[12];
+  __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */
+       uint8_t RESERVED_6[12];
+  __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+       uint8_t RESERVED_7[440];
+  __I  uint32_t ID;                                /**< Peripheral identification register., offset: 0xFFC */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/*! @name CFG - SPI Configuration register */
+/*! @{ */
+#define SPI_CFG_ENABLE_MASK                      (0x1U)
+#define SPI_CFG_ENABLE_SHIFT                     (0U)
+/*! ENABLE - SPI enable.
+ *  0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset.
+ *  0b1..Enabled. The SPI is enabled for operation.
+ */
+#define SPI_CFG_ENABLE(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
+#define SPI_CFG_MASTER_MASK                      (0x4U)
+#define SPI_CFG_MASTER_SHIFT                     (2U)
+/*! MASTER - Master mode select.
+ *  0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
+ *  0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
+ */
+#define SPI_CFG_MASTER(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
+#define SPI_CFG_LSBF_MASK                        (0x8U)
+#define SPI_CFG_LSBF_SHIFT                       (3U)
+/*! LSBF - LSB First mode enable.
+ *  0b0..Standard. Data is transmitted and received in standard MSB first order.
+ *  0b1..Reverse. Data is transmitted and received in reverse order (LSB first).
+ */
+#define SPI_CFG_LSBF(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
+#define SPI_CFG_CPHA_MASK                        (0x10U)
+#define SPI_CFG_CPHA_SHIFT                       (4U)
+/*! CPHA - Clock Phase select.
+ *  0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock
+ *       changes away from the rest state). Data is changed on the following edge.
+ *  0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock
+ *       changes away from the rest state). Data is captured on the following edge.
+ */
+#define SPI_CFG_CPHA(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
+#define SPI_CFG_CPOL_MASK                        (0x20U)
+#define SPI_CFG_CPOL_SHIFT                       (5U)
+/*! CPOL - Clock Polarity select.
+ *  0b0..Low. The rest state of the clock (between transfers) is low.
+ *  0b1..High. The rest state of the clock (between transfers) is high.
+ */
+#define SPI_CFG_CPOL(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
+#define SPI_CFG_LOOP_MASK                        (0x80U)
+#define SPI_CFG_LOOP_SHIFT                       (7U)
+/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit
+ *    and receive data connected together to allow simple software testing.
+ *  0b0..Disabled.
+ *  0b1..Enabled.
+ */
+#define SPI_CFG_LOOP(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
+#define SPI_CFG_SPOL0_MASK                       (0x100U)
+#define SPI_CFG_SPOL0_SHIFT                      (8U)
+/*! SPOL0 - SSEL0 Polarity select.
+ *  0b0..Low. The SSEL0 pin is active low.
+ *  0b1..High. The SSEL0 pin is active high.
+ */
+#define SPI_CFG_SPOL0(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
+#define SPI_CFG_SPOL1_MASK                       (0x200U)
+#define SPI_CFG_SPOL1_SHIFT                      (9U)
+/*! SPOL1 - SSEL1 Polarity select.
+ *  0b0..Low. The SSEL1 pin is active low.
+ *  0b1..High. The SSEL1 pin is active high.
+ */
+#define SPI_CFG_SPOL1(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
+#define SPI_CFG_SPOL2_MASK                       (0x400U)
+#define SPI_CFG_SPOL2_SHIFT                      (10U)
+/*! SPOL2 - SSEL2 Polarity select.
+ *  0b0..Low. The SSEL2 pin is active low.
+ *  0b1..High. The SSEL2 pin is active high.
+ */
+#define SPI_CFG_SPOL2(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
+#define SPI_CFG_SPOL3_MASK                       (0x800U)
+#define SPI_CFG_SPOL3_SHIFT                      (11U)
+/*! SPOL3 - SSEL3 Polarity select.
+ *  0b0..Low. The SSEL3 pin is active low.
+ *  0b1..High. The SSEL3 pin is active high.
+ */
+#define SPI_CFG_SPOL3(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
+/*! @} */
+
+/*! @name DLY - SPI Delay register */
+/*! @{ */
+#define SPI_DLY_PRE_DELAY_MASK                   (0xFU)
+#define SPI_DLY_PRE_DELAY_SHIFT                  (0U)
+/*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data
+ *    transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This
+ *    is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI
+ *    clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are
+ *    inserted.
+ */
+#define SPI_DLY_PRE_DELAY(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
+#define SPI_DLY_POST_DELAY_MASK                  (0xF0U)
+#define SPI_DLY_POST_DELAY_SHIFT                 (4U)
+/*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL
+ *    deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock
+ *    times are inserted. 0xF = 15 SPI clock times are inserted.
+ */
+#define SPI_DLY_POST_DELAY(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
+#define SPI_DLY_FRAME_DELAY_MASK                 (0xF00U)
+#define SPI_DLY_FRAME_DELAY_SHIFT                (8U)
+/*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current
+ *    frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1
+ *    = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock
+ *    times are inserted.
+ */
+#define SPI_DLY_FRAME_DELAY(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
+#define SPI_DLY_TRANSFER_DELAY_MASK              (0xF000U)
+#define SPI_DLY_TRANSFER_DELAY_SHIFT             (12U)
+/*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between
+ *    transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1
+ *    = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that
+ *    SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16
+ *    SPI clock times.
+ */
+#define SPI_DLY_TRANSFER_DELAY(x)                (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
+/*! @} */
+
+/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */
+/*! @{ */
+#define SPI_STAT_SSA_MASK                        (0x10U)
+#define SPI_STAT_SSA_SHIFT                       (4U)
+/*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from
+ *    deasserted to asserted, in both master and slave modes. This allows determining when the SPI
+ *    transmit/receive functions become busy, and allows waking up the device from reduced power modes when a
+ *    slave mode access begins. This flag is cleared by software.
+ */
+#define SPI_STAT_SSA(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
+#define SPI_STAT_SSD_MASK                        (0x20U)
+#define SPI_STAT_SSD_SHIFT                       (5U)
+/*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to
+ *    deasserted, in both master and slave modes. This allows determining when the SPI
+ *    transmit/receive functions become idle. This flag is cleared by software.
+ */
+#define SPI_STAT_SSD(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
+#define SPI_STAT_STALLED_MASK                    (0x40U)
+#define SPI_STAT_STALLED_SHIFT                   (6U)
+/*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition.
+ */
+#define SPI_STAT_STALLED(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
+#define SPI_STAT_ENDTRANSFER_MASK                (0x80U)
+#define SPI_STAT_ENDTRANSFER_SHIFT               (7U)
+/*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current
+ *    transfer when the transmitter finishes any activity already in progress, as if the EOT flag
+ *    had been set prior to the last transmission. This capability is included to support cases where
+ *    it is not known when transmit data is written that it will be the end of a transfer. The bit
+ *    is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end
+ *    of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
+ */
+#define SPI_STAT_ENDTRANSFER(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
+#define SPI_STAT_MSTIDLE_MASK                    (0x100U)
+#define SPI_STAT_MSTIDLE_SHIFT                   (8U)
+/*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle.
+ *    This means that the transmit holding register is empty and the transmitter is not in the
+ *    process of sending data.
+ */
+#define SPI_STAT_MSTIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
+/*! @} */
+
+/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
+/*! @{ */
+#define SPI_INTENSET_SSAEN_MASK                  (0x10U)
+#define SPI_INTENSET_SSAEN_SHIFT                 (4U)
+/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted.
+ *  0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
+ *  0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
+ */
+#define SPI_INTENSET_SSAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
+#define SPI_INTENSET_SSDEN_MASK                  (0x20U)
+#define SPI_INTENSET_SSDEN_SHIFT                 (5U)
+/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted.
+ *  0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
+ *  0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
+ */
+#define SPI_INTENSET_SSDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
+#define SPI_INTENSET_MSTIDLEEN_MASK              (0x100U)
+#define SPI_INTENSET_MSTIDLEEN_SHIFT             (8U)
+/*! MSTIDLEEN - Master idle interrupt enable.
+ *  0b0..No interrupt will be generated when the SPI master function is idle.
+ *  0b1..An interrupt will be generated when the SPI master function is fully idle.
+ */
+#define SPI_INTENSET_MSTIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
+/*! @} */
+
+/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */
+/*! @{ */
+#define SPI_INTENCLR_SSAEN_MASK                  (0x10U)
+#define SPI_INTENCLR_SSAEN_SHIFT                 (4U)
+/*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define SPI_INTENCLR_SSAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
+#define SPI_INTENCLR_SSDEN_MASK                  (0x20U)
+#define SPI_INTENCLR_SSDEN_SHIFT                 (5U)
+/*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define SPI_INTENCLR_SSDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
+#define SPI_INTENCLR_MSTIDLE_MASK                (0x100U)
+#define SPI_INTENCLR_MSTIDLE_SHIFT               (8U)
+/*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define SPI_INTENCLR_MSTIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
+/*! @} */
+
+/*! @name DIV - SPI clock Divider */
+/*! @{ */
+#define SPI_DIV_DIVVAL_MASK                      (0xFFFFU)
+#define SPI_DIV_DIVVAL_SHIFT                     (0U)
+/*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the
+ *    SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1,
+ *    the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results
+ *    in FCLK/65536.
+ */
+#define SPI_DIV_DIVVAL(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
+/*! @} */
+
+/*! @name INTSTAT - SPI Interrupt Status */
+/*! @{ */
+#define SPI_INTSTAT_SSA_MASK                     (0x10U)
+#define SPI_INTSTAT_SSA_SHIFT                    (4U)
+/*! SSA - Slave Select Assert.
+ */
+#define SPI_INTSTAT_SSA(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
+#define SPI_INTSTAT_SSD_MASK                     (0x20U)
+#define SPI_INTSTAT_SSD_SHIFT                    (5U)
+/*! SSD - Slave Select Deassert.
+ */
+#define SPI_INTSTAT_SSD(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
+#define SPI_INTSTAT_MSTIDLE_MASK                 (0x100U)
+#define SPI_INTSTAT_MSTIDLE_SHIFT                (8U)
+/*! MSTIDLE - Master Idle status flag.
+ */
+#define SPI_INTSTAT_MSTIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
+/*! @} */
+
+/*! @name FIFOCFG - FIFO configuration and enable register. */
+/*! @{ */
+#define SPI_FIFOCFG_ENABLETX_MASK                (0x1U)
+#define SPI_FIFOCFG_ENABLETX_SHIFT               (0U)
+/*! ENABLETX - Enable the transmit FIFO.
+ *  0b0..The transmit FIFO is not enabled.
+ *  0b1..The transmit FIFO is enabled.
+ */
+#define SPI_FIFOCFG_ENABLETX(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
+#define SPI_FIFOCFG_ENABLERX_MASK                (0x2U)
+#define SPI_FIFOCFG_ENABLERX_SHIFT               (1U)
+/*! ENABLERX - Enable the receive FIFO.
+ *  0b0..The receive FIFO is not enabled.
+ *  0b1..The receive FIFO is enabled.
+ */
+#define SPI_FIFOCFG_ENABLERX(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)
+#define SPI_FIFOCFG_SIZE_MASK                    (0x30U)
+#define SPI_FIFOCFG_SIZE_SHIFT                   (4U)
+/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16
+ *    entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
+ */
+#define SPI_FIFOCFG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)
+#define SPI_FIFOCFG_DMATX_MASK                   (0x1000U)
+#define SPI_FIFOCFG_DMATX_SHIFT                  (12U)
+/*! DMATX - DMA configuration for transmit.
+ *  0b0..DMA is not used for the transmit function.
+ *  0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define SPI_FIFOCFG_DMATX(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)
+#define SPI_FIFOCFG_DMARX_MASK                   (0x2000U)
+#define SPI_FIFOCFG_DMARX_SHIFT                  (13U)
+/*! DMARX - DMA configuration for receive.
+ *  0b0..DMA is not used for the receive function.
+ *  0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define SPI_FIFOCFG_DMARX(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
+#define SPI_FIFOCFG_WAKETX_MASK                  (0x4000U)
+#define SPI_FIFOCFG_WAKETX_SHIFT                 (14U)
+/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power
+ *    modes (up to power-down, as long as the peripheral function works in that power mode) without
+ *    enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
+ *    CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
+ *    Wake-up control register.
+ *  0b0..Only enabled interrupts will wake up the device form reduced power modes.
+ *  0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
+ *       FIFOTRIG, even when the TXLVL interrupt is not enabled.
+ */
+#define SPI_FIFOCFG_WAKETX(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)
+#define SPI_FIFOCFG_WAKERX_MASK                  (0x8000U)
+#define SPI_FIFOCFG_WAKERX_SHIFT                 (15U)
+/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power
+ *    modes (up to power-down, as long as the peripheral function works in that power mode) without
+ *    enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
+ *    CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
+ *    Wake-up control register.
+ *  0b0..Only enabled interrupts will wake up the device form reduced power modes.
+ *  0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in
+ *       FIFOTRIG, even when the RXLVL interrupt is not enabled.
+ */
+#define SPI_FIFOCFG_WAKERX(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)
+#define SPI_FIFOCFG_EMPTYTX_MASK                 (0x10000U)
+#define SPI_FIFOCFG_EMPTYTX_SHIFT                (16U)
+/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
+ */
+#define SPI_FIFOCFG_EMPTYTX(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)
+#define SPI_FIFOCFG_EMPTYRX_MASK                 (0x20000U)
+#define SPI_FIFOCFG_EMPTYRX_SHIFT                (17U)
+/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
+ */
+#define SPI_FIFOCFG_EMPTYRX(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)
+/*! @} */
+
+/*! @name FIFOSTAT - FIFO status register. */
+/*! @{ */
+#define SPI_FIFOSTAT_TXERR_MASK                  (0x1U)
+#define SPI_FIFOSTAT_TXERR_SHIFT                 (0U)
+/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow
+ *    caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is
+ *    needed. Cleared by writing a 1 to this bit.
+ */
+#define SPI_FIFOSTAT_TXERR(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)
+#define SPI_FIFOSTAT_RXERR_MASK                  (0x2U)
+#define SPI_FIFOSTAT_RXERR_SHIFT                 (1U)
+/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA
+ *    not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.
+ */
+#define SPI_FIFOSTAT_RXERR(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)
+#define SPI_FIFOSTAT_PERINT_MASK                 (0x8U)
+#define SPI_FIFOSTAT_PERINT_SHIFT                (3U)
+/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted
+ *    an interrupt. The details can be found by reading the peripheral's STAT register.
+ */
+#define SPI_FIFOSTAT_PERINT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)
+#define SPI_FIFOSTAT_TXEMPTY_MASK                (0x10U)
+#define SPI_FIFOSTAT_TXEMPTY_SHIFT               (4U)
+/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.
+ */
+#define SPI_FIFOSTAT_TXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)
+#define SPI_FIFOSTAT_TXNOTFULL_MASK              (0x20U)
+#define SPI_FIFOSTAT_TXNOTFULL_SHIFT             (5U)
+/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be
+ *    written. When 0, the transmit FIFO is full and another write would cause it to overflow.
+ */
+#define SPI_FIFOSTAT_TXNOTFULL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)
+#define SPI_FIFOSTAT_RXNOTEMPTY_MASK             (0x40U)
+#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT            (6U)
+/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.
+ */
+#define SPI_FIFOSTAT_RXNOTEMPTY(x)               (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
+#define SPI_FIFOSTAT_RXFULL_MASK                 (0x80U)
+#define SPI_FIFOSTAT_RXFULL_SHIFT                (7U)
+/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to
+ *    prevent the peripheral from causing an overflow.
+ */
+#define SPI_FIFOSTAT_RXFULL(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)
+#define SPI_FIFOSTAT_TXLVL_MASK                  (0x1F00U)
+#define SPI_FIFOSTAT_TXLVL_SHIFT                 (8U)
+/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY
+ *    and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at
+ *    the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be
+ *    0.
+ */
+#define SPI_FIFOSTAT_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)
+#define SPI_FIFOSTAT_RXLVL_MASK                  (0x1F0000U)
+#define SPI_FIFOSTAT_RXLVL_SHIFT                 (16U)
+/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and
+ *    RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the
+ *    point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be
+ *    1.
+ */
+#define SPI_FIFOSTAT_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
+/*! @{ */
+#define SPI_FIFOTRIG_TXLVLENA_MASK               (0x1U)
+#define SPI_FIFOTRIG_TXLVLENA_SHIFT              (0U)
+/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled
+ *    in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
+ *  0b0..Transmit FIFO level does not generate a FIFO level trigger.
+ *  0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
+ */
+#define SPI_FIFOTRIG_TXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)
+#define SPI_FIFOTRIG_RXLVLENA_MASK               (0x2U)
+#define SPI_FIFOTRIG_RXLVLENA_SHIFT              (1U)
+/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled
+ *    in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.
+ *  0b0..Receive FIFO level does not generate a FIFO level trigger.
+ *  0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
+ */
+#define SPI_FIFOTRIG_RXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)
+#define SPI_FIFOTRIG_TXLVL_MASK                  (0xF00U)
+#define SPI_FIFOTRIG_TXLVL_SHIFT                 (8U)
+/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled
+ *    to do so, the FIFO level can wake up the device just enough to perform DMA, then return to
+ *    the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO
+ *    becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX
+ *    FIFO level decreases to 15 entries (is no longer full).
+ */
+#define SPI_FIFOTRIG_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)
+#define SPI_FIFOTRIG_RXLVL_MASK                  (0xF0000U)
+#define SPI_FIFOTRIG_RXLVL_SHIFT                 (16U)
+/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data
+ *    is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level
+ *    can wake up the device just enough to perform DMA, then return to the reduced power mode. See
+ *    Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no
+ *    longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX
+ *    FIFO has received 16 entries (has become full).
+ */
+#define SPI_FIFOTRIG_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
+/*! @{ */
+#define SPI_FIFOINTENSET_TXERR_MASK              (0x1U)
+#define SPI_FIFOINTENSET_TXERR_SHIFT             (0U)
+/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
+ *  0b0..No interrupt will be generated for a transmit error.
+ *  0b1..An interrupt will be generated when a transmit error occurs.
+ */
+#define SPI_FIFOINTENSET_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)
+#define SPI_FIFOINTENSET_RXERR_MASK              (0x2U)
+#define SPI_FIFOINTENSET_RXERR_SHIFT             (1U)
+/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.
+ *  0b0..No interrupt will be generated for a receive error.
+ *  0b1..An interrupt will be generated when a receive error occurs.
+ */
+#define SPI_FIFOINTENSET_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)
+#define SPI_FIFOINTENSET_TXLVL_MASK              (0x4U)
+#define SPI_FIFOINTENSET_TXLVL_SHIFT             (2U)
+/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level
+ *    specified by the TXLVL field in the FIFOTRIG register.
+ *  0b0..No interrupt will be generated based on the TX FIFO level.
+ *  0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases
+ *       to the level specified by TXLVL in the FIFOTRIG register.
+ */
+#define SPI_FIFOINTENSET_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)
+#define SPI_FIFOINTENSET_RXLVL_MASK              (0x8U)
+#define SPI_FIFOINTENSET_RXLVL_SHIFT             (3U)
+/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level
+ *    specified by the TXLVL field in the FIFOTRIG register.
+ *  0b0..No interrupt will be generated based on the RX FIFO level.
+ *  0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level
+ *       increases to the level specified by RXLVL in the FIFOTRIG register.
+ */
+#define SPI_FIFOINTENSET_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
+/*! @{ */
+#define SPI_FIFOINTENCLR_TXERR_MASK              (0x1U)
+#define SPI_FIFOINTENCLR_TXERR_SHIFT             (0U)
+/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define SPI_FIFOINTENCLR_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)
+#define SPI_FIFOINTENCLR_RXERR_MASK              (0x2U)
+#define SPI_FIFOINTENCLR_RXERR_SHIFT             (1U)
+/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define SPI_FIFOINTENCLR_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)
+#define SPI_FIFOINTENCLR_TXLVL_MASK              (0x4U)
+#define SPI_FIFOINTENCLR_TXLVL_SHIFT             (2U)
+/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define SPI_FIFOINTENCLR_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)
+#define SPI_FIFOINTENCLR_RXLVL_MASK              (0x8U)
+#define SPI_FIFOINTENCLR_RXLVL_SHIFT             (3U)
+/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define SPI_FIFOINTENCLR_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */
+/*! @{ */
+#define SPI_FIFOINTSTAT_TXERR_MASK               (0x1U)
+#define SPI_FIFOINTSTAT_TXERR_SHIFT              (0U)
+/*! TXERR - TX FIFO error.
+ */
+#define SPI_FIFOINTSTAT_TXERR(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)
+#define SPI_FIFOINTSTAT_RXERR_MASK               (0x2U)
+#define SPI_FIFOINTSTAT_RXERR_SHIFT              (1U)
+/*! RXERR - RX FIFO error.
+ */
+#define SPI_FIFOINTSTAT_RXERR(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)
+#define SPI_FIFOINTSTAT_TXLVL_MASK               (0x4U)
+#define SPI_FIFOINTSTAT_TXLVL_SHIFT              (2U)
+/*! TXLVL - Transmit FIFO level interrupt.
+ */
+#define SPI_FIFOINTSTAT_TXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)
+#define SPI_FIFOINTSTAT_RXLVL_MASK               (0x8U)
+#define SPI_FIFOINTSTAT_RXLVL_SHIFT              (3U)
+/*! RXLVL - Receive FIFO level interrupt.
+ */
+#define SPI_FIFOINTSTAT_RXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)
+#define SPI_FIFOINTSTAT_PERINT_MASK              (0x10U)
+#define SPI_FIFOINTSTAT_PERINT_SHIFT             (4U)
+/*! PERINT - Peripheral interrupt.
+ */
+#define SPI_FIFOINTSTAT_PERINT(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)
+/*! @} */
+
+/*! @name FIFOWR - FIFO write data. */
+/*! @{ */
+#define SPI_FIFOWR_TXDATA_MASK                   (0xFFFFU)
+#define SPI_FIFOWR_TXDATA_SHIFT                  (0U)
+/*! TXDATA - Transmit data to the FIFO.
+ */
+#define SPI_FIFOWR_TXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)
+#define SPI_FIFOWR_TXSSEL0_N_MASK                (0x10000U)
+#define SPI_FIFOWR_TXSSEL0_N_SHIFT               (16U)
+/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default.
+ *  0b0..SSEL0 asserted.
+ *  0b1..SSEL0 not asserted.
+ */
+#define SPI_FIFOWR_TXSSEL0_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)
+#define SPI_FIFOWR_TXSSEL1_N_MASK                (0x20000U)
+#define SPI_FIFOWR_TXSSEL1_N_SHIFT               (17U)
+/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default.
+ *  0b0..SSEL1 asserted.
+ *  0b1..SSEL1 not asserted.
+ */
+#define SPI_FIFOWR_TXSSEL1_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)
+#define SPI_FIFOWR_TXSSEL2_N_MASK                (0x40000U)
+#define SPI_FIFOWR_TXSSEL2_N_SHIFT               (18U)
+/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default.
+ *  0b0..SSEL2 asserted.
+ *  0b1..SSEL2 not asserted.
+ */
+#define SPI_FIFOWR_TXSSEL2_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
+#define SPI_FIFOWR_TXSSEL3_N_MASK                (0x80000U)
+#define SPI_FIFOWR_TXSSEL3_N_SHIFT               (19U)
+/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default.
+ *  0b0..SSEL3 asserted.
+ *  0b1..SSEL3 not asserted.
+ */
+#define SPI_FIFOWR_TXSSEL3_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
+#define SPI_FIFOWR_EOT_MASK                      (0x100000U)
+#define SPI_FIFOWR_EOT_SHIFT                     (20U)
+/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain
+ *    so far at least the time specified by the Transfer_delay value in the DLY register.
+ *  0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
+ *  0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
+ */
+#define SPI_FIFOWR_EOT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)
+#define SPI_FIFOWR_EOF_MASK                      (0x200000U)
+#define SPI_FIFOWR_EOF_SHIFT                     (21U)
+/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value
+ *    in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay
+ *    value = 0. This control can be used as part of the support for frame lengths greater than 16
+ *    bits.
+ *  0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame.
+ *  0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be
+ *       inserted before subsequent data is transmitted.
+ */
+#define SPI_FIFOWR_EOF(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)
+#define SPI_FIFOWR_RXIGNORE_MASK                 (0x400000U)
+#define SPI_FIFOWR_RXIGNORE_SHIFT                (22U)
+/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to
+ *    read unneeded data from the receiver. Setting this bit simplifies the transmit process and can
+ *    be used with the DMA.
+ *  0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit
+ *       will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data
+ *       is not read before new data is received.
+ *  0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received
+ *       data. No receiver flags are generated.
+ */
+#define SPI_FIFOWR_RXIGNORE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)
+#define SPI_FIFOWR_LEN_MASK                      (0xF000000U)
+#define SPI_FIFOWR_LEN_SHIFT                     (24U)
+/*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths
+ *    greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved.
+ *    0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data
+ *    transfer is 16 bits in length.
+ */
+#define SPI_FIFOWR_LEN(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)
+/*! @} */
+
+/*! @name FIFORD - FIFO read data. */
+/*! @{ */
+#define SPI_FIFORD_RXDATA_MASK                   (0xFFFFU)
+#define SPI_FIFORD_RXDATA_SHIFT                  (0U)
+/*! RXDATA - Received data from the FIFO.
+ */
+#define SPI_FIFORD_RXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)
+#define SPI_FIFORD_RXSSEL0_N_MASK                (0x10000U)
+#define SPI_FIFORD_RXSSEL0_N_SHIFT               (16U)
+/*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved
+ *    along with received data. The value will reflect the SSEL0 pin for both master and slave
+ *    operation. A zero indicates that a slave select is active. The actual polarity of each slave select
+ *    pin is configured by the related SPOL bit in CFG.
+ */
+#define SPI_FIFORD_RXSSEL0_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)
+#define SPI_FIFORD_RXSSEL1_N_MASK                (0x20000U)
+#define SPI_FIFORD_RXSSEL1_N_SHIFT               (17U)
+/*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved
+ *    along with received data. The value will reflect the SSEL1 pin for both master and slave
+ *    operation. A zero indicates that a slave select is active. The actual polarity of each slave select
+ *    pin is configured by the related SPOL bit in CFG.
+ */
+#define SPI_FIFORD_RXSSEL1_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)
+#define SPI_FIFORD_RXSSEL2_N_MASK                (0x40000U)
+#define SPI_FIFORD_RXSSEL2_N_SHIFT               (18U)
+/*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved
+ *    along with received data. The value will reflect the SSEL2 pin for both master and slave
+ *    operation. A zero indicates that a slave select is active. The actual polarity of each slave select
+ *    pin is configured by the related SPOL bit in CFG.
+ */
+#define SPI_FIFORD_RXSSEL2_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
+#define SPI_FIFORD_RXSSEL3_N_MASK                (0x80000U)
+#define SPI_FIFORD_RXSSEL3_N_SHIFT               (19U)
+/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved
+ *    along with received data. The value will reflect the SSEL3 pin for both master and slave
+ *    operation. A zero indicates that a slave select is active. The actual polarity of each slave select
+ *    pin is configured by the related SPOL bit in CFG.
+ */
+#define SPI_FIFORD_RXSSEL3_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
+#define SPI_FIFORD_SOT_MASK                      (0x100000U)
+#define SPI_FIFORD_SOT_SHIFT                     (20U)
+/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went
+ *    from deasserted to asserted (i.e., any previous transfer has ended). This information can be
+ *    used to identify the first piece of data in cases where the transfer length is greater than 16
+ *    bits.
+ */
+#define SPI_FIFORD_SOT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)
+/*! @} */
+
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
+/*! @{ */
+#define SPI_FIFORDNOPOP_RXDATA_MASK              (0xFFFFU)
+#define SPI_FIFORDNOPOP_RXDATA_SHIFT             (0U)
+/*! RXDATA - Received data from the FIFO.
+ */
+#define SPI_FIFORDNOPOP_RXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK           (0x10000U)
+#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT          (16U)
+/*! RXSSEL0_N - Slave Select for receive.
+ */
+#define SPI_FIFORDNOPOP_RXSSEL0_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK           (0x20000U)
+#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT          (17U)
+/*! RXSSEL1_N - Slave Select for receive.
+ */
+#define SPI_FIFORDNOPOP_RXSSEL1_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK           (0x40000U)
+#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT          (18U)
+/*! RXSSEL2_N - Slave Select for receive.
+ */
+#define SPI_FIFORDNOPOP_RXSSEL2_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK           (0x80000U)
+#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT          (19U)
+/*! RXSSEL3_N - Slave Select for receive.
+ */
+#define SPI_FIFORDNOPOP_RXSSEL3_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
+#define SPI_FIFORDNOPOP_SOT_MASK                 (0x100000U)
+#define SPI_FIFORDNOPOP_SOT_SHIFT                (20U)
+/*! SOT - Start of transfer flag.
+ */
+#define SPI_FIFORDNOPOP_SOT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)
+/*! @} */
+
+/*! @name ID - Peripheral identification register. */
+/*! @{ */
+#define SPI_ID_APERTURE_MASK                     (0xFFU)
+#define SPI_ID_APERTURE_SHIFT                    (0U)
+/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
+ */
+#define SPI_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)
+#define SPI_ID_MINOR_REV_MASK                    (0xF00U)
+#define SPI_ID_MINOR_REV_SHIFT                   (8U)
+/*! MINOR_REV - Minor revision of module implementation.
+ */
+#define SPI_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)
+#define SPI_ID_MAJOR_REV_MASK                    (0xF000U)
+#define SPI_ID_MAJOR_REV_SHIFT                   (12U)
+/*! MAJOR_REV - Major revision of module implementation.
+ */
+#define SPI_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)
+#define SPI_ID_ID_MASK                           (0xFFFF0000U)
+#define SPI_ID_ID_SHIFT                          (16U)
+/*! ID - Module identifier for the selected function.
+ */
+#define SPI_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x40086000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x40087000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+/** Peripheral SPI2 base address */
+#define SPI2_BASE                                (0x40088000u)
+/** Peripheral SPI2 base pointer */
+#define SPI2                                     ((SPI_Type *)SPI2_BASE)
+/** Peripheral SPI3 base address */
+#define SPI3_BASE                                (0x40089000u)
+/** Peripheral SPI3 base pointer */
+#define SPI3                                     ((SPI_Type *)SPI3_BASE)
+/** Peripheral SPI4 base address */
+#define SPI4_BASE                                (0x4008A000u)
+/** Peripheral SPI4 base pointer */
+#define SPI4                                     ((SPI_Type *)SPI4_BASE)
+/** Peripheral SPI5 base address */
+#define SPI5_BASE                                (0x40096000u)
+/** Peripheral SPI5 base pointer */
+#define SPI5                                     ((SPI_Type *)SPI5_BASE)
+/** Peripheral SPI6 base address */
+#define SPI6_BASE                                (0x40097000u)
+/** Peripheral SPI6 base pointer */
+#define SPI6                                     ((SPI_Type *)SPI6_BASE)
+/** Peripheral SPI7 base address */
+#define SPI7_BASE                                (0x40098000u)
+/** Peripheral SPI7 base pointer */
+#define SPI7                                     ((SPI_Type *)SPI7_BASE)
+/** Peripheral SPI8 base address */
+#define SPI8_BASE                                (0x40099000u)
+/** Peripheral SPI8 base pointer */
+#define SPI8                                     ((SPI_Type *)SPI8_BASE)
+/** Peripheral SPI9 base address */
+#define SPI9_BASE                                (0x4009A000u)
+/** Peripheral SPI9 base pointer */
+#define SPI9                                     ((SPI_Type *)SPI9_BASE)
+/** Peripheral SPI10 base address */
+#define SPI10_BASE                               (0x4009F000u)
+/** Peripheral SPI10 base pointer */
+#define SPI10                                    ((SPI_Type *)SPI10_BASE)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE, SPI9_BASE, SPI10_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8, SPI9, SPI10 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn, FLEXCOMM10_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPIFI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer
+ * @{
+ */
+
+/** SPIFI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< SPIFI control register, offset: 0x0 */
+  __IO uint32_t CMD;                               /**< SPIFI command register, offset: 0x4 */
+  __IO uint32_t ADDR;                              /**< SPIFI address register, offset: 0x8 */
+  __IO uint32_t IDATA;                             /**< SPIFI intermediate data register, offset: 0xC */
+  __IO uint32_t CLIMIT;                            /**< SPIFI limit register, offset: 0x10 */
+  __IO uint32_t DATA;                              /**< SPIFI data register, offset: 0x14 */
+  __IO uint32_t MCMD;                              /**< SPIFI memory command register, offset: 0x18 */
+  __IO uint32_t STAT;                              /**< SPIFI status register, offset: 0x1C */
+} SPIFI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPIFI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPIFI_Register_Masks SPIFI Register Masks
+ * @{
+ */
+
+/*! @name CTRL - SPIFI control register */
+/*! @{ */
+#define SPIFI_CTRL_TIMEOUT_MASK                  (0xFFFFU)
+#define SPIFI_CTRL_TIMEOUT_SHIFT                 (0U)
+/*! TIMEOUT - This field contains the number of serial clock periods without the processor reading
+ *    data in memory mode, which will cause the SPIFI hardware to terminate the command by driving
+ *    the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory
+ *    to enter a lower-power state.) If the processor reads data from the flash region after a
+ *    time-out, the command in the Memory Command Register is issued again.
+ */
+#define SPIFI_CTRL_TIMEOUT(x)                    (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK)
+#define SPIFI_CTRL_CSHIGH_MASK                   (0xF0000U)
+#define SPIFI_CTRL_CSHIGH_SHIFT                  (16U)
+/*! CSHIGH - This field controls the minimum CS high time, expressed as a number of serial clock periods minus one.
+ */
+#define SPIFI_CTRL_CSHIGH(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK)
+#define SPIFI_CTRL_D_PRFTCH_DIS_MASK             (0x200000U)
+#define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT            (21U)
+/*! D_PRFTCH_DIS - This bit allows conditioning of memory mode prefetches based on the AHB HPROT
+ *    (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt
+ *    a speculative prefetch when it encounters data accesses.
+ */
+#define SPIFI_CTRL_D_PRFTCH_DIS(x)               (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK)
+#define SPIFI_CTRL_INTEN_MASK                    (0x400000U)
+#define SPIFI_CTRL_INTEN_SHIFT                   (22U)
+/*! INTEN - If this bit is 1 when a command ends, the SPIFI will assert its interrupt request
+ *    output. See INTRQ in the status register for further details.
+ */
+#define SPIFI_CTRL_INTEN(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK)
+#define SPIFI_CTRL_MODE3_MASK                    (0x800000U)
+#define SPIFI_CTRL_MODE3_SHIFT                   (23U)
+/*! MODE3 - SPI Mode 3 select.
+ *  0b0..SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is
+ *       captured, and keeps it low while CS is HIGH.
+ *  0b1..SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is
+ *       HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but
+ *       some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be
+ *       1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the
+ *       frame.
+ */
+#define SPIFI_CTRL_MODE3(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK)
+#define SPIFI_CTRL_PRFTCH_DIS_MASK               (0x8000000U)
+#define SPIFI_CTRL_PRFTCH_DIS_SHIFT              (27U)
+/*! PRFTCH_DIS - Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines.
+ *  0b0..Enable. Cache prefetching enabled.
+ *  0b1..Disable. Disables prefetching of cache lines.
+ */
+#define SPIFI_CTRL_PRFTCH_DIS(x)                 (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK)
+#define SPIFI_CTRL_DUAL_MASK                     (0x10000000U)
+#define SPIFI_CTRL_DUAL_SHIFT                    (28U)
+/*! DUAL - Select dual protocol.
+ *  0b0..Quad protocol. This protocol uses IO3:0.
+ *  0b1..Dual protocol. This protocol uses IO1:0.
+ */
+#define SPIFI_CTRL_DUAL(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK)
+#define SPIFI_CTRL_RFCLK_MASK                    (0x20000000U)
+#define SPIFI_CTRL_RFCLK_SHIFT                   (29U)
+/*! RFCLK - Select active clock edge for input data.
+ *  0b0..Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation.
+ *  0b1..Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time
+ *       in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in
+ *       this case there is no final falling edge on SCK on which to sample the last data bit of the frame.
+ */
+#define SPIFI_CTRL_RFCLK(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK)
+#define SPIFI_CTRL_FBCLK_MASK                    (0x40000000U)
+#define SPIFI_CTRL_FBCLK_SHIFT                   (30U)
+/*! FBCLK - Feedback clock select.
+ *  0b0..Internal clock. The SPIFI samples read data using an internal clock.
+ *  0b1..Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more
+ *       time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no
+ *       final falling edge on SCK on which to sample the last data bit of the frame.
+ */
+#define SPIFI_CTRL_FBCLK(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK)
+#define SPIFI_CTRL_DMAEN_MASK                    (0x80000000U)
+#define SPIFI_CTRL_DMAEN_SHIFT                   (31U)
+/*! DMAEN - A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a
+ *    DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA
+ *    channel is used for memory-to-memory transfers from the SPIFI memory area. DMAEN should only be used
+ *    in Command mode.
+ */
+#define SPIFI_CTRL_DMAEN(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK)
+/*! @} */
+
+/*! @name CMD - SPIFI command register */
+/*! @{ */
+#define SPIFI_CMD_DATALEN_MASK                   (0x3FFFU)
+#define SPIFI_CMD_DATALEN_SHIFT                  (0U)
+/*! DATALEN - Except when the POLL bit in this register is 1, this field controls how many data
+ *    bytes are in the command. 0 indicates that the command does not contain a data field.
+ */
+#define SPIFI_CMD_DATALEN(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK)
+#define SPIFI_CMD_POLL_MASK                      (0x4000U)
+#define SPIFI_CMD_POLL_SHIFT                     (14U)
+/*! POLL - This bit should be written as 1 only with an opcode that a) contains an input data field,
+ *    and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status
+ *    command). When this bit is 1, the SPIFI hardware continues to read bytes until the test
+ *    specified by the DATALEN field is met. The hardware tests the bit in each status byte selected by
+ *    DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds,
+ *    the SPIFI captures the byte that meets this test so that it can be read from the Data
+ *    Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to
+ *    inform software when this occurs
+ */
+#define SPIFI_CMD_POLL(x)                        (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK)
+#define SPIFI_CMD_DOUT_MASK                      (0x8000U)
+#define SPIFI_CMD_DOUT_SHIFT                     (15U)
+/*! DOUT - If the DATALEN field is not zero, this bit controls the direction of the data:
+ *  0b0..Input from serial flash.
+ *  0b1..Output to serial flash.
+ */
+#define SPIFI_CMD_DOUT(x)                        (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK)
+#define SPIFI_CMD_INTLEN_MASK                    (0x70000U)
+#define SPIFI_CMD_INTLEN_SHIFT                   (16U)
+/*! INTLEN - This field controls how many intermediate bytes precede the data. (Each such byte may
+ *    require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or
+ *    4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control
+ *    information, dummy and delay bytes. See the description of the Intermediate Data register for
+ *    the contents of such bytes.
+ */
+#define SPIFI_CMD_INTLEN(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK)
+#define SPIFI_CMD_FIELDFORM_MASK                 (0x180000U)
+#define SPIFI_CMD_FIELDFORM_SHIFT                (19U)
+/*! FIELDFORM - This field controls how the fields of the command are sent.
+ *  0b00..All serial. All fields of the command are serial.
+ *  0b01..Quad/dual data. Data field is quad/dual, other fields are serial.
+ *  0b10..Serial opcode. Opcode field is serial. Other fields are quad/dual.
+ *  0b11..All quad/dual. All fields of the command are in quad/dual format.
+ */
+#define SPIFI_CMD_FIELDFORM(x)                   (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK)
+#define SPIFI_CMD_FRAMEFORM_MASK                 (0xE00000U)
+#define SPIFI_CMD_FRAMEFORM_SHIFT                (21U)
+/*! FRAMEFORM - This field controls the opcode and address fields.
+ *  0b000..Reserved.
+ *  0b001..Opcode. Opcode only, no address.
+ *  0b010..Opcode one byte. Opcode, least significant byte of address.
+ *  0b011..Opcode two bytes. Opcode, two least significant bytes of address.
+ *  0b100..Opcode three bytes. Opcode, three least significant bytes of address.
+ *  0b101..Opcode four bytes. Opcode, 4 bytes of address.
+ *  0b110..No opcode three bytes. No opcode, 3 least significant bytes of address.
+ *  0b111..No opcode four bytes. No opcode, 4 bytes of address.
+ */
+#define SPIFI_CMD_FRAMEFORM(x)                   (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK)
+#define SPIFI_CMD_OPCODE_MASK                    (0xFF000000U)
+#define SPIFI_CMD_OPCODE_SHIFT                   (24U)
+/*! OPCODE - The opcode of the command (not used for some FRAMEFORM values).
+ */
+#define SPIFI_CMD_OPCODE(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK)
+/*! @} */
+
+/*! @name ADDR - SPIFI address register */
+/*! @{ */
+#define SPIFI_ADDR_ADDRESS_MASK                  (0xFFFFFFFFU)
+#define SPIFI_ADDR_ADDRESS_SHIFT                 (0U)
+/*! ADDRESS - Address.
+ */
+#define SPIFI_ADDR_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IDATA - SPIFI intermediate data register */
+/*! @{ */
+#define SPIFI_IDATA_IDATA_MASK                   (0xFFFFFFFFU)
+#define SPIFI_IDATA_IDATA_SHIFT                  (0U)
+/*! IDATA - Value of intermediate bytes.
+ */
+#define SPIFI_IDATA_IDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK)
+/*! @} */
+
+/*! @name CLIMIT - SPIFI limit register */
+/*! @{ */
+#define SPIFI_CLIMIT_CLIMIT_MASK                 (0xFFFFFFFFU)
+#define SPIFI_CLIMIT_CLIMIT_SHIFT                (0U)
+/*! CLIMIT - Zero-based upper limit of cacheable memory
+ */
+#define SPIFI_CLIMIT_CLIMIT(x)                   (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK)
+/*! @} */
+
+/*! @name DATA - SPIFI data register */
+/*! @{ */
+#define SPIFI_DATA_DATA_MASK                     (0xFFFFFFFFU)
+#define SPIFI_DATA_DATA_SHIFT                    (0U)
+/*! DATA - Input or output data
+ */
+#define SPIFI_DATA_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK)
+/*! @} */
+
+/*! @name MCMD - SPIFI memory command register */
+/*! @{ */
+#define SPIFI_MCMD_POLL_MASK                     (0x4000U)
+#define SPIFI_MCMD_POLL_SHIFT                    (14U)
+/*! POLL - This bit should be written as 0.
+ */
+#define SPIFI_MCMD_POLL(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK)
+#define SPIFI_MCMD_DOUT_MASK                     (0x8000U)
+#define SPIFI_MCMD_DOUT_SHIFT                    (15U)
+/*! DOUT - This bit should be written as 0.
+ */
+#define SPIFI_MCMD_DOUT(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK)
+#define SPIFI_MCMD_INTLEN_MASK                   (0x70000U)
+#define SPIFI_MCMD_INTLEN_SHIFT                  (16U)
+/*! INTLEN - This field controls how many intermediate bytes precede the data. (Each such byte may
+ *    require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or
+ *    4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control
+ *    information, dummy and delay bytes. See the description of the Intermediate Data register for
+ *    the contents of such bytes.
+ */
+#define SPIFI_MCMD_INTLEN(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK)
+#define SPIFI_MCMD_FIELDFORM_MASK                (0x180000U)
+#define SPIFI_MCMD_FIELDFORM_SHIFT               (19U)
+/*! FIELDFORM - This field controls how the fields of the command are sent.
+ *  0b00..All serial. All fields of the command are serial.
+ *  0b01..Quad/dual data. Data field is quad/dual, other fields are serial.
+ *  0b10..Serial opcode. Opcode field is serial. Other fields are quad/dual.
+ *  0b11..All quad/dual. All fields of the command are in quad/dual format.
+ */
+#define SPIFI_MCMD_FIELDFORM(x)                  (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK)
+#define SPIFI_MCMD_FRAMEFORM_MASK                (0xE00000U)
+#define SPIFI_MCMD_FRAMEFORM_SHIFT               (21U)
+/*! FRAMEFORM - This field controls the opcode and address fields.
+ *  0b000..Reserved.
+ *  0b001..Opcode. Opcode only, no address.
+ *  0b010..Opcode one byte. Opcode, least-significant byte of address.
+ *  0b011..Opcode two bytes. Opcode, 2 least-significant bytes of address.
+ *  0b100..Opcode three bytes. Opcode, 3 least-significant bytes of address.
+ *  0b101..Opcode four bytes. Opcode, 4 bytes of address.
+ *  0b110..No opcode three bytes. No opcode, 3 least-significant bytes of address.
+ *  0b111..No opcode, 4 bytes of address.
+ */
+#define SPIFI_MCMD_FRAMEFORM(x)                  (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK)
+#define SPIFI_MCMD_OPCODE_MASK                   (0xFF000000U)
+#define SPIFI_MCMD_OPCODE_SHIFT                  (24U)
+/*! OPCODE - The opcode of the command (not used for some FRAMEFORM values).
+ */
+#define SPIFI_MCMD_OPCODE(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK)
+/*! @} */
+
+/*! @name STAT - SPIFI status register */
+/*! @{ */
+#define SPIFI_STAT_MCINIT_MASK                   (0x1U)
+#define SPIFI_STAT_MCINIT_SHIFT                  (0U)
+/*! MCINIT - This bit is set when software successfully writes the Memory Command register, and is
+ *    cleared by Reset or by writing a 1 to the RESET bit in this register.
+ */
+#define SPIFI_STAT_MCINIT(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK)
+#define SPIFI_STAT_CMD_MASK                      (0x2U)
+#define SPIFI_STAT_CMD_SHIFT                     (1U)
+/*! CMD - This bit is 1 when the Command register is written. It is cleared by a hardware reset, a
+ *    write to the RESET bit in this register, or the deassertion of CS which indicates that the
+ *    command has completed communication with the SPI Flash.
+ */
+#define SPIFI_STAT_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK)
+#define SPIFI_STAT_RESET_MASK                    (0x10U)
+#define SPIFI_STAT_RESET_SHIFT                   (4U)
+/*! RESET - Write a 1 to this bit to abort a current command or memory mode. This bit is cleared
+ *    when the hardware is ready for a new command to be written to the Command register.
+ */
+#define SPIFI_STAT_RESET(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK)
+#define SPIFI_STAT_INTRQ_MASK                    (0x20U)
+#define SPIFI_STAT_INTRQ_SHIFT                   (5U)
+/*! INTRQ - This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This
+ *    bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS.
+ */
+#define SPIFI_STAT_INTRQ(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SPIFI_Register_Masks */
+
+
+/* SPIFI - Peripheral instance base addresses */
+/** Peripheral SPIFI0 base address */
+#define SPIFI0_BASE                              (0x40080000u)
+/** Peripheral SPIFI0 base pointer */
+#define SPIFI0                                   ((SPIFI_Type *)SPIFI0_BASE)
+/** Array initializer of SPIFI peripheral base addresses */
+#define SPIFI_BASE_ADDRS                         { SPIFI0_BASE }
+/** Array initializer of SPIFI peripheral base pointers */
+#define SPIFI_BASE_PTRS                          { SPIFI0 }
+/** Interrupt vectors for the SPIFI peripheral type */
+#define SPIFI_IRQS                               { SPIFI0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPIFI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SYSCON Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
+ * @{
+ */
+
+/** SYSCON - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[16];
+  __IO uint32_t AHBMATPRIO;                        /**< AHB multilayer matrix priority control, offset: 0x10 */
+       uint8_t RESERVED_1[44];
+  __IO uint32_t SYSTCKCAL;                         /**< System tick counter calibration, offset: 0x40 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t NMISRC;                            /**< NMI Source Select, offset: 0x48 */
+  __IO uint32_t ASYNCAPBCTRL;                      /**< Asynchronous APB Control, offset: 0x4C */
+       uint8_t RESERVED_3[112];
+  __I  uint32_t PIOPORCAP[2];                      /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_4[8];
+  __I  uint32_t PIORESCAP[2];                      /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */
+       uint8_t RESERVED_5[40];
+  __IO uint32_t PRESETCTRL[3];                     /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */
+       uint8_t RESERVED_6[20];
+  __O  uint32_t PRESETCTRLSET[3];                  /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */
+       uint8_t RESERVED_7[20];
+  __O  uint32_t PRESETCTRLCLR[3];                  /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */
+       uint8_t RESERVED_8[164];
+  __IO uint32_t SYSRSTSTAT;                        /**< System reset status register, offset: 0x1F0 */
+       uint8_t RESERVED_9[12];
+  __IO uint32_t AHBCLKCTRL[3];                     /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_10[20];
+  __O  uint32_t AHBCLKCTRLSET[3];                  /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */
+       uint8_t RESERVED_11[20];
+  __O  uint32_t AHBCLKCTRLCLR[3];                  /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */
+       uint8_t RESERVED_12[48];
+  __IO uint32_t STICKCLKSEL;                       /**< Systick timer clock source selection, offset: 0x27C */
+  __IO uint32_t MAINCLKSELA;                       /**< Main clock source select A, offset: 0x280 */
+  __IO uint32_t MAINCLKSELB;                       /**< Main clock source select B, offset: 0x284 */
+  __IO uint32_t CLKOUTSELA;                        /**< CLKOUT clock source select A, offset: 0x288 */
+       uint8_t RESERVED_13[4];
+  __IO uint32_t SYSPLLCLKSEL;                      /**< PLL clock source select, offset: 0x290 */
+       uint8_t RESERVED_14[4];
+  __IO uint32_t AUDPLLCLKSEL;                      /**< Audio PLL clock source select, offset: 0x298 */
+       uint8_t RESERVED_15[4];
+  __IO uint32_t SPIFICLKSEL;                       /**< SPIFI clock source select, offset: 0x2A0 */
+  __IO uint32_t ADCCLKSEL;                         /**< ADC clock source select, offset: 0x2A4 */
+  __IO uint32_t USB0CLKSEL;                        /**< USB0 clock source select, offset: 0x2A8 */
+  __IO uint32_t USB1CLKSEL;                        /**< USB1 clock source select, offset: 0x2AC */
+  __IO uint32_t FCLKSEL[10];                       /**< Flexcomm clock source select, array offset: 0x2B0, array step: 0x4 */
+  __IO uint32_t FCLKSEL10;                         /**< Flexcomm 10 clock source select, offset: 0x2D8 */
+       uint8_t RESERVED_16[4];
+  __IO uint32_t MCLKCLKSEL;                        /**< MCLK clock source select, offset: 0x2E0 */
+       uint8_t RESERVED_17[4];
+  __IO uint32_t FRGCLKSEL;                         /**< Fractional Rate Generator clock source select, offset: 0x2E8 */
+  __IO uint32_t DMICCLKSEL;                        /**< Digital microphone (DMIC) subsystem clock select, offset: 0x2EC */
+  __IO uint32_t SCTCLKSEL;                         /**< SCTimer/PWM clock source select, offset: 0x2F0 */
+  __IO uint32_t LCDCLKSEL;                         /**< LCD clock source select, offset: 0x2F4 */
+  __IO uint32_t SDIOCLKSEL;                        /**< SDIO clock source select, offset: 0x2F8 */
+       uint8_t RESERVED_18[4];
+  __IO uint32_t SYSTICKCLKDIV;                     /**< SYSTICK clock divider, offset: 0x300 */
+  __IO uint32_t ARMTRACECLKDIV;                    /**< ARM Trace clock divider, offset: 0x304 */
+  __IO uint32_t CAN0CLKDIV;                        /**< MCAN0 clock divider, offset: 0x308 */
+  __IO uint32_t CAN1CLKDIV;                        /**< MCAN1 clock divider, offset: 0x30C */
+  __IO uint32_t SC0CLKDIV;                         /**< Smartcard0 clock divider, offset: 0x310 */
+  __IO uint32_t SC1CLKDIV;                         /**< Smartcard1 clock divider, offset: 0x314 */
+       uint8_t RESERVED_19[104];
+  __IO uint32_t AHBCLKDIV;                         /**< AHB clock divider, offset: 0x380 */
+  __IO uint32_t CLKOUTDIV;                         /**< CLKOUT clock divider, offset: 0x384 */
+  __IO uint32_t FROHFDIV;                          /**< FROHF clock divider, offset: 0x388 */
+       uint8_t RESERVED_20[4];
+  __IO uint32_t SPIFICLKDIV;                       /**< SPIFI clock divider, offset: 0x390 */
+  __IO uint32_t ADCCLKDIV;                         /**< ADC clock divider, offset: 0x394 */
+  __IO uint32_t USB0CLKDIV;                        /**< USB0 clock divider, offset: 0x398 */
+  __IO uint32_t USB1CLKDIV;                        /**< USB1 clock divider, offset: 0x39C */
+  __IO uint32_t FRGCTRL;                           /**< Fractional rate divider, offset: 0x3A0 */
+       uint8_t RESERVED_21[4];
+  __IO uint32_t DMICCLKDIV;                        /**< DMIC clock divider, offset: 0x3A8 */
+  __IO uint32_t MCLKDIV;                           /**< I2S MCLK clock divider, offset: 0x3AC */
+  __IO uint32_t LCDCLKDIV;                         /**< LCD clock divider, offset: 0x3B0 */
+  __IO uint32_t SCTCLKDIV;                         /**< SCT/PWM clock divider, offset: 0x3B4 */
+  __IO uint32_t EMCCLKDIV;                         /**< EMC clock divider, offset: 0x3B8 */
+  __IO uint32_t SDIOCLKDIV;                        /**< SDIO clock divider, offset: 0x3BC */
+       uint8_t RESERVED_22[76];
+  __IO uint32_t USB0CLKCTRL;                       /**< USB0 clock control, offset: 0x40C */
+  __IO uint32_t USB0CLKSTAT;                       /**< USB0 clock status, offset: 0x410 */
+       uint8_t RESERVED_23[4];
+  __IO uint32_t FREQMECTRL;                        /**< Frequency measure register, offset: 0x418 */
+       uint8_t RESERVED_24[4];
+  __IO uint32_t MCLKIO;                            /**< MCLK input/output control, offset: 0x420 */
+  __IO uint32_t USB1CLKCTRL;                       /**< USB1 clock control, offset: 0x424 */
+  __IO uint32_t USB1CLKSTAT;                       /**< USB1 clock status, offset: 0x428 */
+       uint8_t RESERVED_25[24];
+  __IO uint32_t EMCSYSCTRL;                        /**< EMC system control, offset: 0x444 */
+  __IO uint32_t EMCDYCTRL;                         /**< EMC clock delay control, offset: 0x448 */
+  __IO uint32_t EMCCAL;                            /**< EMC delay chain calibration control, offset: 0x44C */
+  __IO uint32_t ETHPHYSEL;                         /**< Ethernet PHY Selection, offset: 0x450 */
+  __IO uint32_t ETHSBDCTRL;                        /**< Ethernet SBD flow control, offset: 0x454 */
+       uint8_t RESERVED_26[8];
+  __IO uint32_t SDIOCLKCTRL;                       /**< SDIO CCLKIN phase and delay control, offset: 0x460 */
+       uint8_t RESERVED_27[12];
+  __IO uint32_t KEYMUXSEL;                         /**< AES key source selection, offset: 0x470 */
+       uint8_t RESERVED_28[140];
+  __IO uint32_t FROCTRL;                           /**< FRO oscillator control, offset: 0x500 */
+  __IO uint32_t SYSOSCCTRL;                        /**< System oscillator control, offset: 0x504 */
+  __IO uint32_t WDTOSCCTRL;                        /**< Watchdog oscillator control, offset: 0x508 */
+  __IO uint32_t RTCOSCCTRL;                        /**< RTC oscillator 32 kHz output control, offset: 0x50C */
+       uint8_t RESERVED_29[12];
+  __IO uint32_t USBPLLCTRL;                        /**< USB PLL control, offset: 0x51C */
+  __IO uint32_t USBPLLSTAT;                        /**< USB PLL status, offset: 0x520 */
+       uint8_t RESERVED_30[92];
+  __IO uint32_t SYSPLLCTRL;                        /**< System PLL control, offset: 0x580 */
+  __IO uint32_t SYSPLLSTAT;                        /**< PLL status, offset: 0x584 */
+  __IO uint32_t SYSPLLNDEC;                        /**< PLL N divider, offset: 0x588 */
+  __IO uint32_t SYSPLLPDEC;                        /**< PLL P divider, offset: 0x58C */
+  __IO uint32_t SYSPLLMDEC;                        /**< System PLL M divider, offset: 0x590 */
+       uint8_t RESERVED_31[12];
+  __IO uint32_t AUDPLLCTRL;                        /**< Audio PLL control, offset: 0x5A0 */
+  __IO uint32_t AUDPLLSTAT;                        /**< Audio PLL status, offset: 0x5A4 */
+  __IO uint32_t AUDPLLNDEC;                        /**< Audio PLL N divider, offset: 0x5A8 */
+  __IO uint32_t AUDPLLPDEC;                        /**< Audio PLL P divider, offset: 0x5AC */
+  __IO uint32_t AUDPLLMDEC;                        /**< Audio PLL M divider, offset: 0x5B0 */
+  __IO uint32_t AUDPLLFRAC;                        /**< Audio PLL fractional divider control, offset: 0x5B4 */
+       uint8_t RESERVED_32[72];
+  __IO uint32_t PDSLEEPCFG[2];                     /**< Sleep configuration register, array offset: 0x600, array step: 0x4 */
+       uint8_t RESERVED_33[8];
+  __IO uint32_t PDRUNCFG[2];                       /**< Power configuration register, array offset: 0x610, array step: 0x4 */
+       uint8_t RESERVED_34[8];
+  __IO uint32_t PDRUNCFGSET[2];                    /**< Power configuration set register, array offset: 0x620, array step: 0x4 */
+       uint8_t RESERVED_35[8];
+  __IO uint32_t PDRUNCFGCLR[2];                    /**< Power configuration clear register, array offset: 0x630, array step: 0x4 */
+       uint8_t RESERVED_36[72];
+  __IO uint32_t STARTER[2];                        /**< Start logic 0 wake-up enable register, array offset: 0x680, array step: 0x4 */
+       uint8_t RESERVED_37[24];
+  __O  uint32_t STARTERSET[2];                     /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */
+       uint8_t RESERVED_38[24];
+  __O  uint32_t STARTERCLR[2];                     /**< Clear bits in STARTER0, array offset: 0x6C0, array step: 0x4 */
+       uint8_t RESERVED_39[184];
+  __IO uint32_t HWWAKE;                            /**< Configures special cases of hardware wake-up, offset: 0x780 */
+       uint8_t RESERVED_40[1664];
+  __IO uint32_t AUTOCGOR;                          /**< Auto Clock-Gate Override Register, offset: 0xE04 */
+       uint8_t RESERVED_41[492];
+  __I  uint32_t JTAGIDCODE;                        /**< JTAG ID code register, offset: 0xFF4 */
+  __I  uint32_t DEVICE_ID0;                        /**< Part ID register, offset: 0xFF8 */
+  __I  uint32_t DEVICE_ID1;                        /**< Boot ROM and die revision register, offset: 0xFFC */
+       uint8_t RESERVED_42[127044];
+  __IO uint32_t BODCTRL;                           /**< Brown-Out Detect control, offset: 0x20044 */
+} SYSCON_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SYSCON Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCON_Register_Masks SYSCON Register Masks
+ * @{
+ */
+
+/*! @name AHBMATPRIO - AHB multilayer matrix priority control */
+/*! @{ */
+#define SYSCON_AHBMATPRIO_PRI_ICODE_MASK         (0x3U)
+#define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT        (0U)
+/*! PRI_ICODE - I-Code bus priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_ICODE(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK)
+#define SYSCON_AHBMATPRIO_PRI_DCODE_MASK         (0xCU)
+#define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT        (2U)
+/*! PRI_DCODE - D-Code bus priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_DCODE(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK)
+#define SYSCON_AHBMATPRIO_PRI_SYS_MASK           (0x30U)
+#define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT          (4U)
+/*! PRI_SYS - System bus priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_SYS(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK)
+#define SYSCON_AHBMATPRIO_PRI_DMA_MASK           (0xC0U)
+#define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT          (6U)
+/*! PRI_DMA - DMA controller priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_DMA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK)
+#define SYSCON_AHBMATPRIO_PRI_ETH_MASK           (0x300U)
+#define SYSCON_AHBMATPRIO_PRI_ETH_SHIFT          (8U)
+/*! PRI_ETH - Ethernet DMA priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_ETH(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ETH_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ETH_MASK)
+#define SYSCON_AHBMATPRIO_PRI_LCD_MASK           (0xC00U)
+#define SYSCON_AHBMATPRIO_PRI_LCD_SHIFT          (10U)
+/*! PRI_LCD - LCD DMA priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_LCD(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_LCD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_LCD_MASK)
+#define SYSCON_AHBMATPRIO_PRI_USB0_MASK          (0x3000U)
+#define SYSCON_AHBMATPRIO_PRI_USB0_SHIFT         (12U)
+/*! PRI_USB0 - USB0 DMA priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_USB0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB0_MASK)
+#define SYSCON_AHBMATPRIO_PRI_USB1_MASK          (0xC000U)
+#define SYSCON_AHBMATPRIO_PRI_USB1_SHIFT         (14U)
+/*! PRI_USB1 - USB1 DMA priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_USB1(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB1_MASK)
+#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK          (0x30000U)
+#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT         (16U)
+/*! PRI_SDIO - SDIO priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_SDIO(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK)
+#define SYSCON_AHBMATPRIO_PRI_MCAN1_MASK         (0xC0000U)
+#define SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT        (18U)
+/*! PRI_MCAN1 - MCAN1 priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_MCAN1(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN1_MASK)
+#define SYSCON_AHBMATPRIO_PRI_MCAN2_MASK         (0x300000U)
+#define SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT        (20U)
+/*! PRI_MCAN2 - MCAN2 priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_MCAN2(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN2_MASK)
+/*! @} */
+
+/*! @name SYSTCKCAL - System tick counter calibration */
+/*! @{ */
+#define SYSCON_SYSTCKCAL_CAL_MASK                (0xFFFFFFU)
+#define SYSCON_SYSTCKCAL_CAL_SHIFT               (0U)
+/*! CAL - System tick timer calibration value.
+ */
+#define SYSCON_SYSTCKCAL_CAL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK)
+#define SYSCON_SYSTCKCAL_SKEW_MASK               (0x1000000U)
+#define SYSCON_SYSTCKCAL_SKEW_SHIFT              (24U)
+/*! SKEW - Initial value for the Systick timer.
+ */
+#define SYSCON_SYSTCKCAL_SKEW(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK)
+#define SYSCON_SYSTCKCAL_NOREF_MASK              (0x2000000U)
+#define SYSCON_SYSTCKCAL_NOREF_SHIFT             (25U)
+/*! NOREF - Initial value for the Systick timer.
+ */
+#define SYSCON_SYSTCKCAL_NOREF(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK)
+/*! @} */
+
+/*! @name NMISRC - NMI Source Select */
+/*! @{ */
+#define SYSCON_NMISRC_IRQM4_MASK                 (0x3FU)
+#define SYSCON_NMISRC_IRQM4_SHIFT                (0U)
+/*! IRQM4 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4, if enabled by NMIENM4.
+ */
+#define SYSCON_NMISRC_IRQM4(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK)
+#define SYSCON_NMISRC_NMIENM4_MASK               (0x80000000U)
+#define SYSCON_NMISRC_NMIENM4_SHIFT              (31U)
+/*! NMIENM4 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4.
+ */
+#define SYSCON_NMISRC_NMIENM4(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCTRL - Asynchronous APB Control */
+/*! @{ */
+#define SYSCON_ASYNCAPBCTRL_ENABLE_MASK          (0x1U)
+#define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT         (0U)
+/*! ENABLE - Enables the asynchronous APB bridge and subsystem.
+ *  0b0..Disabled. Asynchronous APB bridge is disabled.
+ *  0b1..Enabled. Asynchronous APB bridge is enabled.
+ */
+#define SYSCON_ASYNCAPBCTRL_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK)
+/*! @} */
+
+/*! @name PIOPORCAP - POR captured value of port n */
+/*! @{ */
+#define SYSCON_PIOPORCAP_PIOPORCAP_MASK          (0xFFFFFFFFU)
+#define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT         (0U)
+/*! PIOPORCAP - State of PIOn_31 through PIOn_0 at power-on reset
+ */
+#define SYSCON_PIOPORCAP_PIOPORCAP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK)
+/*! @} */
+
+/* The count of SYSCON_PIOPORCAP */
+#define SYSCON_PIOPORCAP_COUNT                   (2U)
+
+/*! @name PIORESCAP - Reset captured value of port n */
+/*! @{ */
+#define SYSCON_PIORESCAP_PIORESCAP_MASK          (0xFFFFFFFFU)
+#define SYSCON_PIORESCAP_PIORESCAP_SHIFT         (0U)
+/*! PIORESCAP - State of PIOn_31 through PIOn_0 for resets other than POR.
+ */
+#define SYSCON_PIORESCAP_PIORESCAP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK)
+/*! @} */
+
+/* The count of SYSCON_PIORESCAP */
+#define SYSCON_PIORESCAP_COUNT                   (2U)
+
+/*! @name PRESETCTRL - Peripheral reset control n */
+/*! @{ */
+#define SYSCON_PRESETCTRL_MRT_RST_MASK           (0x1U)
+#define SYSCON_PRESETCTRL_MRT_RST_SHIFT          (0U)
+/*! MRT_RST - Multi-rate timer (MRT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_MRT_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT_RST_MASK)
+#define SYSCON_PRESETCTRL_LCD_RST_MASK           (0x4U)
+#define SYSCON_PRESETCTRL_LCD_RST_SHIFT          (2U)
+/*! LCD_RST - LCD reset control.
+ */
+#define SYSCON_PRESETCTRL_LCD_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_LCD_RST_SHIFT)) & SYSCON_PRESETCTRL_LCD_RST_MASK)
+#define SYSCON_PRESETCTRL_SCT0_RST_MASK          (0x4U)
+#define SYSCON_PRESETCTRL_SCT0_RST_SHIFT         (2U)
+/*! SCT0_RST - State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_SCT0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK)
+#define SYSCON_PRESETCTRL_SDIO_RST_MASK          (0x8U)
+#define SYSCON_PRESETCTRL_SDIO_RST_SHIFT         (3U)
+/*! SDIO_RST - SDIO reset control.
+ */
+#define SYSCON_PRESETCTRL_SDIO_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL_SDIO_RST_MASK)
+#define SYSCON_PRESETCTRL_USB1H_RST_MASK         (0x10U)
+#define SYSCON_PRESETCTRL_USB1H_RST_SHIFT        (4U)
+/*! USB1H_RST - USB1 Host reset control.
+ */
+#define SYSCON_PRESETCTRL_USB1H_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1H_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1H_RST_MASK)
+#define SYSCON_PRESETCTRL_USB1D_RST_MASK         (0x20U)
+#define SYSCON_PRESETCTRL_USB1D_RST_SHIFT        (5U)
+/*! USB1D_RST - USB1 Device reset control.
+ */
+#define SYSCON_PRESETCTRL_USB1D_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1D_RST_MASK)
+#define SYSCON_PRESETCTRL_USB1RAM_RST_MASK       (0x40U)
+#define SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT      (6U)
+/*! USB1RAM_RST - USB1 RAM reset control.
+ */
+#define SYSCON_PRESETCTRL_USB1RAM_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1RAM_RST_MASK)
+#define SYSCON_PRESETCTRL_EMC_RESET_MASK         (0x80U)
+#define SYSCON_PRESETCTRL_EMC_RESET_SHIFT        (7U)
+/*! EMC_RESET - EMC reset control.
+ */
+#define SYSCON_PRESETCTRL_EMC_RESET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EMC_RESET_SHIFT)) & SYSCON_PRESETCTRL_EMC_RESET_MASK)
+#define SYSCON_PRESETCTRL_MCAN0_RST_MASK         (0x80U)
+#define SYSCON_PRESETCTRL_MCAN0_RST_SHIFT        (7U)
+/*! MCAN0_RST - 0 = Clear reset to this function.
+ */
+#define SYSCON_PRESETCTRL_MCAN0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN0_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN0_RST_MASK)
+#define SYSCON_PRESETCTRL_ETH_RST_MASK           (0x100U)
+#define SYSCON_PRESETCTRL_ETH_RST_SHIFT          (8U)
+/*! ETH_RST - Ethernet reset control.
+ */
+#define SYSCON_PRESETCTRL_ETH_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ETH_RST_SHIFT)) & SYSCON_PRESETCTRL_ETH_RST_MASK)
+#define SYSCON_PRESETCTRL_MCAN1_RST_MASK         (0x100U)
+#define SYSCON_PRESETCTRL_MCAN1_RST_SHIFT        (8U)
+/*! MCAN1_RST - 0 = Clear reset to this function.
+ */
+#define SYSCON_PRESETCTRL_MCAN1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN1_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN1_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO4_RST_MASK         (0x200U)
+#define SYSCON_PRESETCTRL_GPIO4_RST_SHIFT        (9U)
+/*! GPIO4_RST - GPIO4 reset control.
+ */
+#define SYSCON_PRESETCTRL_GPIO4_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO4_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO5_RST_MASK         (0x400U)
+#define SYSCON_PRESETCTRL_GPIO5_RST_SHIFT        (10U)
+/*! GPIO5_RST - GPIO5 reset control.
+ */
+#define SYSCON_PRESETCTRL_GPIO5_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO5_RST_MASK)
+#define SYSCON_PRESETCTRL_SPIFI_RST_MASK         (0x400U)
+#define SYSCON_PRESETCTRL_SPIFI_RST_SHIFT        (10U)
+/*! SPIFI_RST - SPIFI reset control.
+ */
+#define SYSCON_PRESETCTRL_SPIFI_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SPIFI_RST_SHIFT)) & SYSCON_PRESETCTRL_SPIFI_RST_MASK)
+#define SYSCON_PRESETCTRL_UTICK_RST_MASK         (0x400U)
+#define SYSCON_PRESETCTRL_UTICK_RST_SHIFT        (10U)
+/*! UTICK_RST - Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_UTICK_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK_RST_MASK)
+#define SYSCON_PRESETCTRL_FC0_RST_MASK           (0x800U)
+#define SYSCON_PRESETCTRL_FC0_RST_SHIFT          (11U)
+/*! FC0_RST - Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_FC0_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK)
+#define SYSCON_PRESETCTRL_MUX_RST_MASK           (0x800U)
+#define SYSCON_PRESETCTRL_MUX_RST_SHIFT          (11U)
+/*! MUX_RST - Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_MUX_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK)
+#define SYSCON_PRESETCTRL_FC1_RST_MASK           (0x1000U)
+#define SYSCON_PRESETCTRL_FC1_RST_SHIFT          (12U)
+/*! FC1_RST - Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_FC1_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK)
+#define SYSCON_PRESETCTRL_OTP_RST_MASK           (0x1000U)
+#define SYSCON_PRESETCTRL_OTP_RST_SHIFT          (12U)
+/*! OTP_RST - OTP reset control.
+ */
+#define SYSCON_PRESETCTRL_OTP_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL_OTP_RST_MASK)
+#define SYSCON_PRESETCTRL_FC2_RST_MASK           (0x2000U)
+#define SYSCON_PRESETCTRL_FC2_RST_SHIFT          (13U)
+/*! FC2_RST - Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_FC2_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK)
+#define SYSCON_PRESETCTRL_IOCON_RST_MASK         (0x2000U)
+#define SYSCON_PRESETCTRL_IOCON_RST_SHIFT        (13U)
+/*! IOCON_RST - IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_IOCON_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK)
+#define SYSCON_PRESETCTRL_RNG_RST_MASK           (0x2000U)
+#define SYSCON_PRESETCTRL_RNG_RST_SHIFT          (13U)
+/*! RNG_RST - RNG reset control.
+ */
+#define SYSCON_PRESETCTRL_RNG_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL_RNG_RST_MASK)
+#define SYSCON_PRESETCTRL_FC3_RST_MASK           (0x4000U)
+#define SYSCON_PRESETCTRL_FC3_RST_SHIFT          (14U)
+/*! FC3_RST - Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_FC3_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK)
+#define SYSCON_PRESETCTRL_FC8_RST_MASK           (0x4000U)
+#define SYSCON_PRESETCTRL_FC8_RST_SHIFT          (14U)
+/*! FC8_RST - Flexcomm 8 reset control.
+ */
+#define SYSCON_PRESETCTRL_FC8_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC8_RST_SHIFT)) & SYSCON_PRESETCTRL_FC8_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO0_RST_MASK         (0x4000U)
+#define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT        (14U)
+/*! GPIO0_RST - GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_GPIO0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK)
+#define SYSCON_PRESETCTRL_FC4_RST_MASK           (0x8000U)
+#define SYSCON_PRESETCTRL_FC4_RST_SHIFT          (15U)
+/*! FC4_RST - Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_FC4_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK)
+#define SYSCON_PRESETCTRL_FC9_RST_MASK           (0x8000U)
+#define SYSCON_PRESETCTRL_FC9_RST_SHIFT          (15U)
+/*! FC9_RST - Flexcomm 9 reset control.
+ */
+#define SYSCON_PRESETCTRL_FC9_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC9_RST_SHIFT)) & SYSCON_PRESETCTRL_FC9_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO1_RST_MASK         (0x8000U)
+#define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT        (15U)
+/*! GPIO1_RST - GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_GPIO1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK)
+#define SYSCON_PRESETCTRL_FC5_RST_MASK           (0x10000U)
+#define SYSCON_PRESETCTRL_FC5_RST_SHIFT          (16U)
+/*! FC5_RST - Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_FC5_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO2_RST_MASK         (0x10000U)
+#define SYSCON_PRESETCTRL_GPIO2_RST_SHIFT        (16U)
+/*! GPIO2_RST - GPIO2 reset control.
+ */
+#define SYSCON_PRESETCTRL_GPIO2_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO2_RST_MASK)
+#define SYSCON_PRESETCTRL_USB0HMR_RST_MASK       (0x10000U)
+#define SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT      (16U)
+/*! USB0HMR_RST - USB0 HOST master reset control.
+ */
+#define SYSCON_PRESETCTRL_USB0HMR_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HMR_RST_MASK)
+#define SYSCON_PRESETCTRL_FC6_RST_MASK           (0x20000U)
+#define SYSCON_PRESETCTRL_FC6_RST_SHIFT          (17U)
+/*! FC6_RST - Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_FC6_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO3_RST_MASK         (0x20000U)
+#define SYSCON_PRESETCTRL_GPIO3_RST_SHIFT        (17U)
+/*! GPIO3_RST - GPIO3 reset control.
+ */
+#define SYSCON_PRESETCTRL_GPIO3_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO3_RST_MASK)
+#define SYSCON_PRESETCTRL_USB0HSL_RST_MASK       (0x20000U)
+#define SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT      (17U)
+/*! USB0HSL_RST - USB0 HOST slave reset control.
+ */
+#define SYSCON_PRESETCTRL_USB0HSL_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HSL_RST_MASK)
+#define SYSCON_PRESETCTRL_FC7_RST_MASK           (0x40000U)
+#define SYSCON_PRESETCTRL_FC7_RST_SHIFT          (18U)
+/*! FC7_RST - Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_FC7_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK)
+#define SYSCON_PRESETCTRL_PINT_RST_MASK          (0x40000U)
+#define SYSCON_PRESETCTRL_PINT_RST_SHIFT         (18U)
+/*! PINT_RST - Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_PINT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK)
+#define SYSCON_PRESETCTRL_SHA_RST_MASK           (0x40000U)
+#define SYSCON_PRESETCTRL_SHA_RST_SHIFT          (18U)
+/*! SHA_RST - SHA reset control.
+ */
+#define SYSCON_PRESETCTRL_SHA_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SHA_RST_SHIFT)) & SYSCON_PRESETCTRL_SHA_RST_MASK)
+#define SYSCON_PRESETCTRL_DMIC_RST_MASK          (0x80000U)
+#define SYSCON_PRESETCTRL_DMIC_RST_SHIFT         (19U)
+/*! DMIC_RST - Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_DMIC_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC_RST_MASK)
+#define SYSCON_PRESETCTRL_GINT_RST_MASK          (0x80000U)
+#define SYSCON_PRESETCTRL_GINT_RST_SHIFT         (19U)
+/*! GINT_RST - Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_GINT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK)
+#define SYSCON_PRESETCTRL_SC0_RST_MASK           (0x80000U)
+#define SYSCON_PRESETCTRL_SC0_RST_SHIFT          (19U)
+/*! SC0_RST - Smart card 0 reset control.
+ */
+#define SYSCON_PRESETCTRL_SC0_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC0_RST_SHIFT)) & SYSCON_PRESETCTRL_SC0_RST_MASK)
+#define SYSCON_PRESETCTRL_DMA_RST_MASK           (0x100000U)
+#define SYSCON_PRESETCTRL_DMA_RST_SHIFT          (20U)
+/*! DMA_RST - DMA reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_DMA_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA_RST_MASK)
+#define SYSCON_PRESETCTRL_SC1_RST_MASK           (0x100000U)
+#define SYSCON_PRESETCTRL_SC1_RST_SHIFT          (20U)
+/*! SC1_RST - Smart card 1 reset control.
+ */
+#define SYSCON_PRESETCTRL_SC1_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC1_RST_SHIFT)) & SYSCON_PRESETCTRL_SC1_RST_MASK)
+#define SYSCON_PRESETCTRL_CRC_RST_MASK           (0x200000U)
+#define SYSCON_PRESETCTRL_CRC_RST_SHIFT          (21U)
+/*! CRC_RST - CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_CRC_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK)
+#define SYSCON_PRESETCTRL_FC10_RST_MASK          (0x200000U)
+#define SYSCON_PRESETCTRL_FC10_RST_SHIFT         (21U)
+/*! FC10_RST - Flexcomm 10 reset control.
+ */
+#define SYSCON_PRESETCTRL_FC10_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC10_RST_SHIFT)) & SYSCON_PRESETCTRL_FC10_RST_MASK)
+#define SYSCON_PRESETCTRL_CTIMER2_RST_MASK       (0x400000U)
+#define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT      (22U)
+/*! CTIMER2_RST - CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function
+ */
+#define SYSCON_PRESETCTRL_CTIMER2_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK)
+#define SYSCON_PRESETCTRL_WWDT_RST_MASK          (0x400000U)
+#define SYSCON_PRESETCTRL_WWDT_RST_SHIFT         (22U)
+/*! WWDT_RST - Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_WWDT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK)
+#define SYSCON_PRESETCTRL_USB0D_RST_MASK         (0x2000000U)
+#define SYSCON_PRESETCTRL_USB0D_RST_SHIFT        (25U)
+/*! USB0D_RST - USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_USB0D_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0D_RST_MASK)
+#define SYSCON_PRESETCTRL_CTIMER0_RST_MASK       (0x4000000U)
+#define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT      (26U)
+/*! CTIMER0_RST - CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_CTIMER0_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK)
+#define SYSCON_PRESETCTRL_ADC0_RST_MASK          (0x8000000U)
+#define SYSCON_PRESETCTRL_ADC0_RST_SHIFT         (27U)
+/*! ADC0_RST - ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_ADC0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK)
+#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK       (0x8000000U)
+#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT      (27U)
+/*! CTIMER1_RST - CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_CTIMER1_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK)
+/*! @} */
+
+/* The count of SYSCON_PRESETCTRL */
+#define SYSCON_PRESETCTRL_COUNT                  (3U)
+
+/*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */
+/*! @{ */
+#define SYSCON_PRESETCTRLSET_RST_SET_MASK        (0xFFFFFFFFU)
+#define SYSCON_PRESETCTRLSET_RST_SET_SHIFT       (0U)
+/*! RST_SET - Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn
+ *    register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn
+ *    are reserved and only zeroes should be written to them.
+ */
+#define SYSCON_PRESETCTRLSET_RST_SET(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK)
+/*! @} */
+
+/* The count of SYSCON_PRESETCTRLSET */
+#define SYSCON_PRESETCTRLSET_COUNT               (3U)
+
+/*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */
+/*! @{ */
+#define SYSCON_PRESETCTRLCLR_RST_CLR_MASK        (0xFFFFFFFFU)
+#define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT       (0U)
+/*! RST_CLR - Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn
+ *    register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn
+ *    are reserved and only zeroes should be written to them.
+ */
+#define SYSCON_PRESETCTRLCLR_RST_CLR(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK)
+/*! @} */
+
+/* The count of SYSCON_PRESETCTRLCLR */
+#define SYSCON_PRESETCTRLCLR_COUNT               (3U)
+
+/*! @name SYSRSTSTAT - System reset status register */
+/*! @{ */
+#define SYSCON_SYSRSTSTAT_POR_MASK               (0x1U)
+#define SYSCON_SYSRSTSTAT_POR_SHIFT              (0U)
+/*! POR - POR reset status
+ *  0b0..No POR detected
+ *  0b1..POR detected. Writing a one clears this reset.
+ */
+#define SYSCON_SYSRSTSTAT_POR(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK)
+#define SYSCON_SYSRSTSTAT_EXTRST_MASK            (0x2U)
+#define SYSCON_SYSRSTSTAT_EXTRST_SHIFT           (1U)
+/*! EXTRST - Status of the external RESET pin. External reset status
+ *  0b0..No reset event detected.
+ *  0b1..Reset detected. Writing a one clears this reset.
+ */
+#define SYSCON_SYSRSTSTAT_EXTRST(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK)
+#define SYSCON_SYSRSTSTAT_WDT_MASK               (0x4U)
+#define SYSCON_SYSRSTSTAT_WDT_SHIFT              (2U)
+/*! WDT - Status of the Watchdog reset
+ *  0b0..No WDT reset detected
+ *  0b1..WDT reset detected. Writing a one clears this reset.
+ */
+#define SYSCON_SYSRSTSTAT_WDT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK)
+#define SYSCON_SYSRSTSTAT_BOD_MASK               (0x8U)
+#define SYSCON_SYSRSTSTAT_BOD_SHIFT              (3U)
+/*! BOD - Status of the Brown-out detect reset
+ *  0b0..No BOD reset detected
+ *  0b1..BOD reset detected. Writing a one clears this reset.
+ */
+#define SYSCON_SYSRSTSTAT_BOD(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK)
+#define SYSCON_SYSRSTSTAT_SYSRST_MASK            (0x10U)
+#define SYSCON_SYSRSTSTAT_SYSRST_SHIFT           (4U)
+/*! SYSRST - Status of the software system reset
+ *  0b0..No System reset detected
+ *  0b1..System reset detected. Writing a one clears this reset.
+ */
+#define SYSCON_SYSRSTSTAT_SYSRST(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK)
+/*! @} */
+
+/*! @name AHBCLKCTRL - AHB Clock control n */
+/*! @{ */
+#define SYSCON_AHBCLKCTRL_MRT_MASK               (0x1U)
+#define SYSCON_AHBCLKCTRL_MRT_SHIFT              (0U)
+/*! MRT - Enables the clock for the Multi-Rate Timer.
+ */
+#define SYSCON_AHBCLKCTRL_MRT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT_SHIFT)) & SYSCON_AHBCLKCTRL_MRT_MASK)
+#define SYSCON_AHBCLKCTRL_RIT_MASK               (0x2U)
+#define SYSCON_AHBCLKCTRL_RIT_SHIFT              (1U)
+/*! RIT - Enables the clock for the Repetitive Interrupt Timer.
+ */
+#define SYSCON_AHBCLKCTRL_RIT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RIT_SHIFT)) & SYSCON_AHBCLKCTRL_RIT_MASK)
+#define SYSCON_AHBCLKCTRL_ROM_MASK               (0x2U)
+#define SYSCON_AHBCLKCTRL_ROM_SHIFT              (1U)
+/*! ROM - Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_ROM(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK)
+#define SYSCON_AHBCLKCTRL_LCD_MASK               (0x4U)
+#define SYSCON_AHBCLKCTRL_LCD_SHIFT              (2U)
+/*! LCD - Enables the clock for the LCD interface.
+ */
+#define SYSCON_AHBCLKCTRL_LCD(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_LCD_SHIFT)) & SYSCON_AHBCLKCTRL_LCD_MASK)
+#define SYSCON_AHBCLKCTRL_SCT0_MASK              (0x4U)
+#define SYSCON_AHBCLKCTRL_SCT0_SHIFT             (2U)
+/*! SCT0 - Enables the clock for SCT0.
+ */
+#define SYSCON_AHBCLKCTRL_SCT0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK)
+#define SYSCON_AHBCLKCTRL_SDIO_MASK              (0x8U)
+#define SYSCON_AHBCLKCTRL_SDIO_SHIFT             (3U)
+/*! SDIO - Enables the clock for the SDIO interface.
+ */
+#define SYSCON_AHBCLKCTRL_SDIO(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL_SDIO_MASK)
+#define SYSCON_AHBCLKCTRL_SRAM1_MASK             (0x8U)
+#define SYSCON_AHBCLKCTRL_SRAM1_SHIFT            (3U)
+/*! SRAM1 - Enables the clock for SRAM1. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_SRAM1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK)
+#define SYSCON_AHBCLKCTRL_SRAM2_MASK             (0x10U)
+#define SYSCON_AHBCLKCTRL_SRAM2_SHIFT            (4U)
+/*! SRAM2 - Enables the clock for SRAM2. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_SRAM2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK)
+#define SYSCON_AHBCLKCTRL_USB1H_MASK             (0x10U)
+#define SYSCON_AHBCLKCTRL_USB1H_SHIFT            (4U)
+/*! USB1H - Enables the clock for the USB1 host interface.
+ */
+#define SYSCON_AHBCLKCTRL_USB1H(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1H_SHIFT)) & SYSCON_AHBCLKCTRL_USB1H_MASK)
+#define SYSCON_AHBCLKCTRL_SRAM3_MASK             (0x20U)
+#define SYSCON_AHBCLKCTRL_SRAM3_SHIFT            (5U)
+/*! SRAM3 - Enables the clock for SRAM3.
+ */
+#define SYSCON_AHBCLKCTRL_SRAM3(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM3_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM3_MASK)
+#define SYSCON_AHBCLKCTRL_USB1D_MASK             (0x20U)
+#define SYSCON_AHBCLKCTRL_USB1D_SHIFT            (5U)
+/*! USB1D - Enables the clock for the USB1 device interface.
+ */
+#define SYSCON_AHBCLKCTRL_USB1D(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1D_SHIFT)) & SYSCON_AHBCLKCTRL_USB1D_MASK)
+#define SYSCON_AHBCLKCTRL_USB1RAM_MASK           (0x40U)
+#define SYSCON_AHBCLKCTRL_USB1RAM_SHIFT          (6U)
+/*! USB1RAM - Enables the clock for the USB1 RAM interface.
+ */
+#define SYSCON_AHBCLKCTRL_USB1RAM(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1RAM_SHIFT)) & SYSCON_AHBCLKCTRL_USB1RAM_MASK)
+#define SYSCON_AHBCLKCTRL_EMC_MASK               (0x80U)
+#define SYSCON_AHBCLKCTRL_EMC_SHIFT              (7U)
+/*! EMC - Enables the clock for the EMC interface.
+ */
+#define SYSCON_AHBCLKCTRL_EMC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EMC_SHIFT)) & SYSCON_AHBCLKCTRL_EMC_MASK)
+#define SYSCON_AHBCLKCTRL_MCAN0_MASK             (0x80U)
+#define SYSCON_AHBCLKCTRL_MCAN0_SHIFT            (7U)
+/*! MCAN0 - Enables the clock for MCAN0.
+ */
+#define SYSCON_AHBCLKCTRL_MCAN0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN0_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN0_MASK)
+#define SYSCON_AHBCLKCTRL_ETH_MASK               (0x100U)
+#define SYSCON_AHBCLKCTRL_ETH_SHIFT              (8U)
+/*! ETH - Enables the clock for the ethernet interface.
+ */
+#define SYSCON_AHBCLKCTRL_ETH(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ETH_SHIFT)) & SYSCON_AHBCLKCTRL_ETH_MASK)
+#define SYSCON_AHBCLKCTRL_MCAN1_MASK             (0x100U)
+#define SYSCON_AHBCLKCTRL_MCAN1_SHIFT            (8U)
+/*! MCAN1 - Enables the clock for MCAN1.
+ */
+#define SYSCON_AHBCLKCTRL_MCAN1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN1_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN1_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO4_MASK             (0x200U)
+#define SYSCON_AHBCLKCTRL_GPIO4_SHIFT            (9U)
+/*! GPIO4 - Enables the clock for the GPIO4 interface.
+ */
+#define SYSCON_AHBCLKCTRL_GPIO4(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO4_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO5_MASK             (0x400U)
+#define SYSCON_AHBCLKCTRL_GPIO5_SHIFT            (10U)
+/*! GPIO5 - Enables the clock for the GPIO5 interface.
+ */
+#define SYSCON_AHBCLKCTRL_GPIO5(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO5_MASK)
+#define SYSCON_AHBCLKCTRL_SPIFI_MASK             (0x400U)
+#define SYSCON_AHBCLKCTRL_SPIFI_SHIFT            (10U)
+/*! SPIFI - Enables the clock for the SPIFI. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_SPIFI(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SPIFI_SHIFT)) & SYSCON_AHBCLKCTRL_SPIFI_MASK)
+#define SYSCON_AHBCLKCTRL_UTICK_MASK             (0x400U)
+#define SYSCON_AHBCLKCTRL_UTICK_SHIFT            (10U)
+/*! UTICK - Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_UTICK(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK         (0x800U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT        (11U)
+/*! FLEXCOMM0 - Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK)
+#define SYSCON_AHBCLKCTRL_INPUTMUX_MASK          (0x800U)
+#define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT         (11U)
+/*! INPUTMUX - Enables the clock for the input muxes. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_INPUTMUX(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK         (0x1000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT        (12U)
+/*! FLEXCOMM1 - Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK)
+#define SYSCON_AHBCLKCTRL_OTP_MASK               (0x1000U)
+#define SYSCON_AHBCLKCTRL_OTP_SHIFT              (12U)
+/*! OTP - Enables the clock for the OTP interface.
+ */
+#define SYSCON_AHBCLKCTRL_OTP(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_OTP_SHIFT)) & SYSCON_AHBCLKCTRL_OTP_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK         (0x2000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT        (13U)
+/*! FLEXCOMM2 - Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK)
+#define SYSCON_AHBCLKCTRL_IOCON_MASK             (0x2000U)
+#define SYSCON_AHBCLKCTRL_IOCON_SHIFT            (13U)
+/*! IOCON - Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_IOCON(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK)
+#define SYSCON_AHBCLKCTRL_RNG_MASK               (0x2000U)
+#define SYSCON_AHBCLKCTRL_RNG_SHIFT              (13U)
+/*! RNG - Enables the clock for the RNG interface.
+ */
+#define SYSCON_AHBCLKCTRL_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RNG_SHIFT)) & SYSCON_AHBCLKCTRL_RNG_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK         (0x4000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT        (14U)
+/*! FLEXCOMM3 - Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK         (0x4000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT        (14U)
+/*! FLEXCOMM8 - Enables the clock for the Flexcomm8 interface.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM8(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO0_MASK             (0x4000U)
+#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT            (14U)
+/*! GPIO0 - Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_GPIO0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK         (0x8000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT        (15U)
+/*! FLEXCOMM4 - Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK         (0x8000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT        (15U)
+/*! FLEXCOMM9 - Enables the clock for the Flexcomm9 interface.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM9(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO1_MASK             (0x8000U)
+#define SYSCON_AHBCLKCTRL_GPIO1_SHIFT            (15U)
+/*! GPIO1 - Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_GPIO1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK         (0x10000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT        (16U)
+/*! FLEXCOMM5 - Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO2_MASK             (0x10000U)
+#define SYSCON_AHBCLKCTRL_GPIO2_SHIFT            (16U)
+/*! GPIO2 - Enables the clock for the GPIO2 port registers.
+ */
+#define SYSCON_AHBCLKCTRL_GPIO2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO2_MASK)
+#define SYSCON_AHBCLKCTRL_USB0HMR_MASK           (0x10000U)
+#define SYSCON_AHBCLKCTRL_USB0HMR_SHIFT          (16U)
+/*! USB0HMR - Enables the clock for the USB host master interface.
+ */
+#define SYSCON_AHBCLKCTRL_USB0HMR(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HMR_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HMR_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK         (0x20000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT        (17U)
+/*! FLEXCOMM6 - Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO3_MASK             (0x20000U)
+#define SYSCON_AHBCLKCTRL_GPIO3_SHIFT            (17U)
+/*! GPIO3 - Enables the clock for the GPIO3 port registers.
+ */
+#define SYSCON_AHBCLKCTRL_GPIO3(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO3_MASK)
+#define SYSCON_AHBCLKCTRL_USB0HSL_MASK           (0x20000U)
+#define SYSCON_AHBCLKCTRL_USB0HSL_SHIFT          (17U)
+/*! USB0HSL - Enables the clock for the USB host slave interface.
+ */
+#define SYSCON_AHBCLKCTRL_USB0HSL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HSL_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HSL_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK         (0x40000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT        (18U)
+/*! FLEXCOMM7 - Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK)
+#define SYSCON_AHBCLKCTRL_PINT_MASK              (0x40000U)
+#define SYSCON_AHBCLKCTRL_PINT_SHIFT             (18U)
+/*! PINT - Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_PINT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK)
+#define SYSCON_AHBCLKCTRL_SHA_MASK               (0x40000U)
+#define SYSCON_AHBCLKCTRL_SHA_SHIFT              (18U)
+/*! SHA - Enables the clock for the SHA interface.
+ */
+#define SYSCON_AHBCLKCTRL_SHA(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SHA_SHIFT)) & SYSCON_AHBCLKCTRL_SHA_MASK)
+#define SYSCON_AHBCLKCTRL_DMIC_MASK              (0x80000U)
+#define SYSCON_AHBCLKCTRL_DMIC_SHIFT             (19U)
+/*! DMIC - Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_DMIC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC_MASK)
+#define SYSCON_AHBCLKCTRL_GINT_MASK              (0x80000U)
+#define SYSCON_AHBCLKCTRL_GINT_SHIFT             (19U)
+/*! GINT - Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_GINT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK)
+#define SYSCON_AHBCLKCTRL_SC0_MASK               (0x80000U)
+#define SYSCON_AHBCLKCTRL_SC0_SHIFT              (19U)
+/*! SC0 - Enables the clock for the Smart card0 interface.
+ */
+#define SYSCON_AHBCLKCTRL_SC0(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC0_SHIFT)) & SYSCON_AHBCLKCTRL_SC0_MASK)
+#define SYSCON_AHBCLKCTRL_DMA_MASK               (0x100000U)
+#define SYSCON_AHBCLKCTRL_DMA_SHIFT              (20U)
+/*! DMA - Enables the clock for the DMA controller. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_DMA(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA_SHIFT)) & SYSCON_AHBCLKCTRL_DMA_MASK)
+#define SYSCON_AHBCLKCTRL_SC1_MASK               (0x100000U)
+#define SYSCON_AHBCLKCTRL_SC1_SHIFT              (20U)
+/*! SC1 - Enables the clock for the Smart card1 interface.
+ */
+#define SYSCON_AHBCLKCTRL_SC1(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC1_SHIFT)) & SYSCON_AHBCLKCTRL_SC1_MASK)
+#define SYSCON_AHBCLKCTRL_CRC_MASK               (0x200000U)
+#define SYSCON_AHBCLKCTRL_CRC_SHIFT              (21U)
+/*! CRC - Enables the clock for the CRC engine. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_CRC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM10_MASK        (0x200000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM10_SHIFT       (21U)
+/*! FLEXCOMM10 - Enables the clock for the Flexcomm10 interface.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM10(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM10_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM10_MASK)
+#define SYSCON_AHBCLKCTRL_CTIMER2_MASK           (0x400000U)
+#define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT          (22U)
+/*! CTIMER2 - Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_CTIMER2(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK)
+#define SYSCON_AHBCLKCTRL_WWDT_MASK              (0x400000U)
+#define SYSCON_AHBCLKCTRL_WWDT_SHIFT             (22U)
+/*! WWDT - Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_WWDT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK)
+#define SYSCON_AHBCLKCTRL_RTC_MASK               (0x800000U)
+#define SYSCON_AHBCLKCTRL_RTC_SHIFT              (23U)
+/*! RTC - Enables the bus clock for the RTC. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_RTC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK)
+#define SYSCON_AHBCLKCTRL_USB0D_MASK             (0x2000000U)
+#define SYSCON_AHBCLKCTRL_USB0D_SHIFT            (25U)
+/*! USB0D - Enables the clock for the USB0 device interface. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_USB0D(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0D_SHIFT)) & SYSCON_AHBCLKCTRL_USB0D_MASK)
+#define SYSCON_AHBCLKCTRL_CTIMER0_MASK           (0x4000000U)
+#define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT          (26U)
+/*! CTIMER0 - Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_CTIMER0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK)
+#define SYSCON_AHBCLKCTRL_ADC0_MASK              (0x8000000U)
+#define SYSCON_AHBCLKCTRL_ADC0_SHIFT             (27U)
+/*! ADC0 - Enables the clock for the ADC0 register interface.
+ */
+#define SYSCON_AHBCLKCTRL_ADC0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK)
+#define SYSCON_AHBCLKCTRL_CTIMER1_MASK           (0x8000000U)
+#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT          (27U)
+/*! CTIMER1 - Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_CTIMER1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK)
+/*! @} */
+
+/* The count of SYSCON_AHBCLKCTRL */
+#define SYSCON_AHBCLKCTRL_COUNT                  (3U)
+
+/*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */
+/*! @{ */
+#define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK        (0xFFFFFFFFU)
+#define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT       (0U)
+/*! CLK_SET - Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn
+ *    register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn
+ *    are reserved and only zeroes should be written to them.
+ */
+#define SYSCON_AHBCLKCTRLSET_CLK_SET(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK)
+/*! @} */
+
+/* The count of SYSCON_AHBCLKCTRLSET */
+#define SYSCON_AHBCLKCTRLSET_COUNT               (3U)
+
+/*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */
+/*! @{ */
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK        (0xFFFFFFFFU)
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT       (0U)
+/*! CLK_CLR - Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn
+ *    register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn
+ *    are reserved and only zeroes should be written to them.
+ */
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK)
+/*! @} */
+
+/* The count of SYSCON_AHBCLKCTRLCLR */
+#define SYSCON_AHBCLKCTRLCLR_COUNT               (3U)
+
+/*! @name STICKCLKSEL - Systick timer clock source selection */
+/*! @{ */
+#define SYSCON_STICKCLKSEL_SEL_MASK              (0x7U)
+#define SYSCON_STICKCLKSEL_SEL_SHIFT             (0U)
+/*! SEL - Systick timer clock source selection
+ *  0b000..Main clock (main_clk)
+ *  0b001..Watchdog oscillator (wdt_clk)
+ *  0b010..RTC oscillator 32 kHz output (32k_clk)
+ *  0b011..FRO 12 MHz (fro_12m)
+ *  0b100..Reserved setting
+ *  0b101..Reserved setting
+ *  0b110..Reserved setting
+ *  0b111..None, this may be selected to reduce power when no output is needed.
+ */
+#define SYSCON_STICKCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STICKCLKSEL_SEL_SHIFT)) & SYSCON_STICKCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name MAINCLKSELA - Main clock source select A */
+/*! @{ */
+#define SYSCON_MAINCLKSELA_SEL_MASK              (0x3U)
+#define SYSCON_MAINCLKSELA_SEL_SHIFT             (0U)
+/*! SEL - Clock source for main clock source selector A
+ *  0b00..FRO 12 MHz (fro_12m)
+ *  0b01..CLKIN (clk_in)
+ *  0b10..Watchdog oscillator (wdt_clk)
+ *  0b11..FRO 96 or 48 MHz (fro_hf)
+ */
+#define SYSCON_MAINCLKSELA_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK)
+/*! @} */
+
+/*! @name MAINCLKSELB - Main clock source select B */
+/*! @{ */
+#define SYSCON_MAINCLKSELB_SEL_MASK              (0x3U)
+#define SYSCON_MAINCLKSELB_SEL_SHIFT             (0U)
+/*! SEL - Clock source for main clock source selector B. Selects the clock source for the main clock.
+ *  0b00..MAINCLKSELA. Use the clock source selected in MAINCLKSELA register.
+ *  0b01..Reserved setting
+ *  0b10..System PLL output (pll_clk)
+ *  0b11..RTC oscillator 32 kHz output (32k_clk)
+ */
+#define SYSCON_MAINCLKSELB_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK)
+/*! @} */
+
+/*! @name CLKOUTSELA - CLKOUT clock source select A */
+/*! @{ */
+#define SYSCON_CLKOUTSELA_SEL_MASK               (0x7U)
+#define SYSCON_CLKOUTSELA_SEL_SHIFT              (0U)
+/*! SEL - CLKOUT clock source selection
+ *  0b000..Main clock (main_clk)
+ *  0b001..CLKIN (clk_in)
+ *  0b010..Watchdog oscillator (wdt_clk)
+ *  0b011..FRO 96 or 48 MHz (fro_hf)
+ *  0b100..PLL output (pll_clk)
+ *  0b101..USB PLL clock (usb_pll_clk)
+ *  0b110..Audio PLL clock (audio_pll_clk)
+ *  0b111..RTC oscillator 32 kHz output (32k_clk)
+ */
+#define SYSCON_CLKOUTSELA_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK)
+/*! @} */
+
+/*! @name SYSPLLCLKSEL - PLL clock source select */
+/*! @{ */
+#define SYSCON_SYSPLLCLKSEL_SEL_MASK             (0x7U)
+#define SYSCON_SYSPLLCLKSEL_SEL_SHIFT            (0U)
+/*! SEL - System PLL clock source selection.
+ *  0b000..FRO 12 MHz (fro_12m)
+ *  0b001..CLKIN (clk_in)
+ *  0b011..RTC oscillator 32 kHz output (32k_clk)
+ *  0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_SYSPLLCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name AUDPLLCLKSEL - Audio PLL clock source select */
+/*! @{ */
+#define SYSCON_AUDPLLCLKSEL_SEL_MASK             (0x7U)
+#define SYSCON_AUDPLLCLKSEL_SEL_SHIFT            (0U)
+/*! SEL - Audio PLL clock source selection.
+ *  0b000..FRO 12 MHz (fro_12m)
+ *  0b001..CLKIN (clk_in)
+ *  0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_AUDPLLCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCLKSEL_SEL_SHIFT)) & SYSCON_AUDPLLCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SPIFICLKSEL - SPIFI clock source select */
+/*! @{ */
+#define SYSCON_SPIFICLKSEL_SEL_MASK              (0x7U)
+#define SYSCON_SPIFICLKSEL_SEL_SHIFT             (0U)
+/*! SEL - System PLL clock source selection
+ *  0b000..Main clock (main_clk)
+ *  0b001..System PLL output (pll_clk)
+ *  0b010..USB PLL clock (usb_pll_clk)
+ *  0b011..FRO 96 or 48 MHz (fro_hf)
+ *  0b100..Audio PLL clock (audio_pll_clk)
+ *  0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_SPIFICLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name ADCCLKSEL - ADC clock source select */
+/*! @{ */
+#define SYSCON_ADCCLKSEL_SEL_MASK                (0x7U)
+#define SYSCON_ADCCLKSEL_SEL_SHIFT               (0U)
+/*! SEL - ADC clock source selection
+ *  0b000..FRO 96 or 48 MHz (fro_hf)
+ *  0b001..System PLL output (pll_clk)
+ *  0b010..USB PLL clock (usb_pll_clk)
+ *  0b011..Audio PLL clock (audio_pll_clk)
+ *  0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_ADCCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name USB0CLKSEL - USB0 clock source select */
+/*! @{ */
+#define SYSCON_USB0CLKSEL_SEL_MASK               (0x7U)
+#define SYSCON_USB0CLKSEL_SEL_SHIFT              (0U)
+/*! SEL - USB0 device clock source selection.
+ *  0b000..FRO 96 or 48 MHz (fro_hf)
+ *  0b001..System PLL output (pll_clk)
+ *  0b010..USB PLL clock (usb_pll_clk)
+ *  0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_USB0CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name USB1CLKSEL - USB1 clock source select */
+/*! @{ */
+#define SYSCON_USB1CLKSEL_SEL_MASK               (0x7U)
+#define SYSCON_USB1CLKSEL_SEL_SHIFT              (0U)
+/*! SEL - USB1 PHY clock source selection.
+ *  0b000..Main clock (main_clk)
+ *  0b001..System PLL output (pll_clk)
+ *  0b010..USB PLL clock (usb_pll_clk)
+ *  0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_USB1CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name FCLKSEL - Flexcomm clock source select */
+/*! @{ */
+#define SYSCON_FCLKSEL_SEL_MASK                  (0x7U)
+#define SYSCON_FCLKSEL_SEL_SHIFT                 (0U)
+/*! SEL - Flexcomm clock source selection. One per Flexcomm.
+ *  0b000..FRO 12 MHz (fro_12m)
+ *  0b001..FRO HF DIV (fro_hf_div)
+ *  0b010..Audio PLL clock (audio_pll_clk)
+ *  0b011..MCLK pin input, when selected in IOCON (mclk_in)
+ *  0b100..FRG clock, the output of the fractional rate generator (frg_clk)
+ *  0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_FCLKSEL_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_FCLKSEL_SEL_SHIFT)) & SYSCON_FCLKSEL_SEL_MASK)
+/*! @} */
+
+/* The count of SYSCON_FCLKSEL */
+#define SYSCON_FCLKSEL_COUNT                     (10U)
+
+/*! @name FCLKSEL10 - Flexcomm 10 clock source select */
+/*! @{ */
+#define SYSCON_FCLKSEL10_SEL_MASK                (0x7U)
+#define SYSCON_FCLKSEL10_SEL_SHIFT               (0U)
+/*! SEL - Flexcomm clock source selection. One per Flexcomm.
+ *  0b000..Main clock (main_clk)
+ *  0b001..System PLL output (pll_clk)
+ *  0b010..USB PLL clock (usb_pll_clk)
+ *  0b011..FRO 96 or 48 MHz (fro_hf)
+ *  0b100..Audio PLL clock (audio_pll_clk)
+ *  0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_FCLKSEL10_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FCLKSEL10_SEL_SHIFT)) & SYSCON_FCLKSEL10_SEL_MASK)
+/*! @} */
+
+/*! @name MCLKCLKSEL - MCLK clock source select */
+/*! @{ */
+#define SYSCON_MCLKCLKSEL_SEL_MASK               (0x7U)
+#define SYSCON_MCLKCLKSEL_SEL_SHIFT              (0U)
+/*! SEL - MCLK source select. This may be used by Flexcomms that support I2S, and/or by the digital microphone subsystem.
+ *  0b000..FRO HF DIV (fro_hf_div)
+ *  0b001..Audio PLL clock (audio_pll_clk)
+ *  0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_MCLKCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name FRGCLKSEL - Fractional Rate Generator clock source select */
+/*! @{ */
+#define SYSCON_FRGCLKSEL_SEL_MASK                (0x7U)
+#define SYSCON_FRGCLKSEL_SEL_SHIFT               (0U)
+/*! SEL - Fractional Rate Generator clock source select.
+ *  0b000..Main clock (main_clk)
+ *  0b001..System PLL output (pll_clk)
+ *  0b010..FRO 12 MHz (fro_12m)
+ *  0b011..FRO 96 or 48 MHz (fro_hf)
+ *  0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_FRGCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name DMICCLKSEL - Digital microphone (DMIC) subsystem clock select */
+/*! @{ */
+#define SYSCON_DMICCLKSEL_SEL_MASK               (0x7U)
+#define SYSCON_DMICCLKSEL_SEL_SHIFT              (0U)
+/*! SEL - DMIC (audio subsystem) clock source select.
+ *  0b000..FRO 12 MHz (fro_12m)
+ *  0b001..FRO HF DIV (fro_hf_div)
+ *  0b010..Audio PLL clock (audio_pll_clk)
+ *  0b011..MCLK pin input, when selected in IOCON (mclk_in)
+ *  0b100..Main clock (main_clk)
+ *  0b101..Watchdog oscillator (wdt_clk)
+ *  0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_DMICCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SCTCLKSEL - SCTimer/PWM clock source select */
+/*! @{ */
+#define SYSCON_SCTCLKSEL_SEL_MASK                (0x7U)
+#define SYSCON_SCTCLKSEL_SEL_SHIFT               (0U)
+/*! SEL - SCT clock source select.
+ *  0b000..Main clock (main_clk)
+ *  0b001..System PLL output (pll_clk)
+ *  0b010..FRO 96 or 48 MHz (fro_hf)
+ *  0b011..Audio PLL clock (audio_pll_clk)
+ *  0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_SCTCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name LCDCLKSEL - LCD clock source select */
+/*! @{ */
+#define SYSCON_LCDCLKSEL_SEL_MASK                (0x3U)
+#define SYSCON_LCDCLKSEL_SEL_SHIFT               (0U)
+/*! SEL - LCD clock source select.
+ *  0b00..Main clock (main_clk)
+ *  0b01..LCDCLKIN (LCDCLK_EXT)
+ *  0b10..FRO 96 or 48 MHz (fro_hf)
+ *  0b11..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_LCDCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKSEL_SEL_SHIFT)) & SYSCON_LCDCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SDIOCLKSEL - SDIO clock source select */
+/*! @{ */
+#define SYSCON_SDIOCLKSEL_SEL_MASK               (0x7U)
+#define SYSCON_SDIOCLKSEL_SEL_SHIFT              (0U)
+/*! SEL - SDIO clock source select.
+ *  0b000..Main clock (main_clk)
+ *  0b001..System PLL output (pll_clk)
+ *  0b010..USB PLL clock (usb_pll_clk)
+ *  0b011..FRO 96 or 48 MHz (fro_hf)
+ *  0b100..Audio PLL clock (audio_pll_clk)
+ *  0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_SDIOCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SYSTICKCLKDIV - SYSTICK clock divider */
+/*! @{ */
+#define SYSCON_SYSTICKCLKDIV_DIV_MASK            (0xFFU)
+#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT           (0U)
+/*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
+ */
+#define SYSCON_SYSTICKCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK)
+#define SYSCON_SYSTICKCLKDIV_RESET_MASK          (0x20000000U)
+#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT         (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count.
+ */
+#define SYSCON_SYSTICKCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK)
+#define SYSCON_SYSTICKCLKDIV_HALT_MASK           (0x40000000U)
+#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT          (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_SYSTICKCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK)
+#define SYSCON_SYSTICKCLKDIV_REQFLAG_MASK        (0x80000000U)
+#define SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT       (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_SYSTICKCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name ARMTRACECLKDIV - ARM Trace clock divider */
+/*! @{ */
+#define SYSCON_ARMTRACECLKDIV_DIV_MASK           (0xFFU)
+#define SYSCON_ARMTRACECLKDIV_DIV_SHIFT          (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_ARMTRACECLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_DIV_SHIFT)) & SYSCON_ARMTRACECLKDIV_DIV_MASK)
+#define SYSCON_ARMTRACECLKDIV_RESET_MASK         (0x20000000U)
+#define SYSCON_ARMTRACECLKDIV_RESET_SHIFT        (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_ARMTRACECLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_RESET_SHIFT)) & SYSCON_ARMTRACECLKDIV_RESET_MASK)
+#define SYSCON_ARMTRACECLKDIV_HALT_MASK          (0x40000000U)
+#define SYSCON_ARMTRACECLKDIV_HALT_SHIFT         (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_ARMTRACECLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_HALT_SHIFT)) & SYSCON_ARMTRACECLKDIV_HALT_MASK)
+#define SYSCON_ARMTRACECLKDIV_REQFLAG_MASK       (0x80000000U)
+#define SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT      (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_ARMTRACECLKDIV_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_ARMTRACECLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name CAN0CLKDIV - MCAN0 clock divider */
+/*! @{ */
+#define SYSCON_CAN0CLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_CAN0CLKDIV_DIV_SHIFT              (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_CAN0CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_DIV_SHIFT)) & SYSCON_CAN0CLKDIV_DIV_MASK)
+#define SYSCON_CAN0CLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_CAN0CLKDIV_RESET_SHIFT            (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_CAN0CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_RESET_SHIFT)) & SYSCON_CAN0CLKDIV_RESET_MASK)
+#define SYSCON_CAN0CLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_CAN0CLKDIV_HALT_SHIFT             (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_CAN0CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_HALT_SHIFT)) & SYSCON_CAN0CLKDIV_HALT_MASK)
+#define SYSCON_CAN0CLKDIV_REQFLAG_MASK           (0x80000000U)
+#define SYSCON_CAN0CLKDIV_REQFLAG_SHIFT          (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_CAN0CLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN0CLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name CAN1CLKDIV - MCAN1 clock divider */
+/*! @{ */
+#define SYSCON_CAN1CLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_CAN1CLKDIV_DIV_SHIFT              (0U)
+/*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
+ */
+#define SYSCON_CAN1CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_DIV_SHIFT)) & SYSCON_CAN1CLKDIV_DIV_MASK)
+#define SYSCON_CAN1CLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_CAN1CLKDIV_RESET_SHIFT            (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count.
+ */
+#define SYSCON_CAN1CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_RESET_SHIFT)) & SYSCON_CAN1CLKDIV_RESET_MASK)
+#define SYSCON_CAN1CLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_CAN1CLKDIV_HALT_SHIFT             (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_CAN1CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_HALT_SHIFT)) & SYSCON_CAN1CLKDIV_HALT_MASK)
+#define SYSCON_CAN1CLKDIV_REQFLAG_MASK           (0x80000000U)
+#define SYSCON_CAN1CLKDIV_REQFLAG_SHIFT          (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_CAN1CLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN1CLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name SC0CLKDIV - Smartcard0 clock divider */
+/*! @{ */
+#define SYSCON_SC0CLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_SC0CLKDIV_DIV_SHIFT               (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_SC0CLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_DIV_SHIFT)) & SYSCON_SC0CLKDIV_DIV_MASK)
+#define SYSCON_SC0CLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_SC0CLKDIV_RESET_SHIFT             (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_SC0CLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_RESET_SHIFT)) & SYSCON_SC0CLKDIV_RESET_MASK)
+#define SYSCON_SC0CLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_SC0CLKDIV_HALT_SHIFT              (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_SC0CLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_HALT_SHIFT)) & SYSCON_SC0CLKDIV_HALT_MASK)
+#define SYSCON_SC0CLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_SC0CLKDIV_REQFLAG_SHIFT           (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_SC0CLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC0CLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name SC1CLKDIV - Smartcard1 clock divider */
+/*! @{ */
+#define SYSCON_SC1CLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_SC1CLKDIV_DIV_SHIFT               (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_SC1CLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_DIV_SHIFT)) & SYSCON_SC1CLKDIV_DIV_MASK)
+#define SYSCON_SC1CLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_SC1CLKDIV_RESET_SHIFT             (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_SC1CLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_RESET_SHIFT)) & SYSCON_SC1CLKDIV_RESET_MASK)
+#define SYSCON_SC1CLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_SC1CLKDIV_HALT_SHIFT              (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_SC1CLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_HALT_SHIFT)) & SYSCON_SC1CLKDIV_HALT_MASK)
+#define SYSCON_SC1CLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_SC1CLKDIV_REQFLAG_SHIFT           (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_SC1CLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC1CLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name AHBCLKDIV - AHB clock divider */
+/*! @{ */
+#define SYSCON_AHBCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_AHBCLKDIV_DIV_SHIFT               (0U)
+/*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
+ */
+#define SYSCON_AHBCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
+#define SYSCON_AHBCLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT           (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_AHBCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name CLKOUTDIV - CLKOUT clock divider */
+/*! @{ */
+#define SYSCON_CLKOUTDIV_DIV_MASK                (0xFFU)
+#define SYSCON_CLKOUTDIV_DIV_SHIFT               (0U)
+/*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
+ */
+#define SYSCON_CLKOUTDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK)
+#define SYSCON_CLKOUTDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_CLKOUTDIV_RESET_SHIFT             (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count.
+ */
+#define SYSCON_CLKOUTDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK)
+#define SYSCON_CLKOUTDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_CLKOUTDIV_HALT_SHIFT              (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ *    without the risk of a glitch at the output.
+ */
+#define SYSCON_CLKOUTDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK)
+#define SYSCON_CLKOUTDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT           (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_CLKOUTDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name FROHFDIV - FROHF clock divider */
+/*! @{ */
+#define SYSCON_FROHFDIV_DIV_MASK                 (0xFFU)
+#define SYSCON_FROHFDIV_DIV_SHIFT                (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_FROHFDIV_DIV(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK)
+#define SYSCON_FROHFDIV_RESET_MASK               (0x20000000U)
+#define SYSCON_FROHFDIV_RESET_SHIFT              (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_FROHFDIV_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK)
+#define SYSCON_FROHFDIV_HALT_MASK                (0x40000000U)
+#define SYSCON_FROHFDIV_HALT_SHIFT               (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_FROHFDIV_HALT(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK)
+#define SYSCON_FROHFDIV_REQFLAG_MASK             (0x80000000U)
+#define SYSCON_FROHFDIV_REQFLAG_SHIFT            (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_FROHFDIV_REQFLAG(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name SPIFICLKDIV - SPIFI clock divider */
+/*! @{ */
+#define SYSCON_SPIFICLKDIV_DIV_MASK              (0xFFU)
+#define SYSCON_SPIFICLKDIV_DIV_SHIFT             (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_SPIFICLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK)
+#define SYSCON_SPIFICLKDIV_RESET_MASK            (0x20000000U)
+#define SYSCON_SPIFICLKDIV_RESET_SHIFT           (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count.
+ */
+#define SYSCON_SPIFICLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK)
+#define SYSCON_SPIFICLKDIV_HALT_MASK             (0x40000000U)
+#define SYSCON_SPIFICLKDIV_HALT_SHIFT            (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ *    without the risk of a glitch at the output.
+ */
+#define SYSCON_SPIFICLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
+#define SYSCON_SPIFICLKDIV_REQFLAG_MASK          (0x80000000U)
+#define SYSCON_SPIFICLKDIV_REQFLAG_SHIFT         (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_SPIFICLKDIV_REQFLAG(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_REQFLAG_SHIFT)) & SYSCON_SPIFICLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name ADCCLKDIV - ADC clock divider */
+/*! @{ */
+#define SYSCON_ADCCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_ADCCLKDIV_DIV_SHIFT               (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_ADCCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK)
+#define SYSCON_ADCCLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_ADCCLKDIV_RESET_SHIFT             (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_ADCCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK)
+#define SYSCON_ADCCLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_ADCCLKDIV_HALT_SHIFT              (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_ADCCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK)
+#define SYSCON_ADCCLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT           (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_ADCCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name USB0CLKDIV - USB0 clock divider */
+/*! @{ */
+#define SYSCON_USB0CLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_USB0CLKDIV_DIV_SHIFT              (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_USB0CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK)
+#define SYSCON_USB0CLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_USB0CLKDIV_RESET_SHIFT            (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_USB0CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK)
+#define SYSCON_USB0CLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_USB0CLKDIV_HALT_SHIFT             (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_USB0CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK)
+#define SYSCON_USB0CLKDIV_REQFLAG_MASK           (0x80000000U)
+#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT          (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_USB0CLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name USB1CLKDIV - USB1 clock divider */
+/*! @{ */
+#define SYSCON_USB1CLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_USB1CLKDIV_DIV_SHIFT              (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_USB1CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_DIV_SHIFT)) & SYSCON_USB1CLKDIV_DIV_MASK)
+#define SYSCON_USB1CLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_USB1CLKDIV_RESET_SHIFT            (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_USB1CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_RESET_SHIFT)) & SYSCON_USB1CLKDIV_RESET_MASK)
+#define SYSCON_USB1CLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_USB1CLKDIV_HALT_SHIFT             (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_USB1CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_HALT_SHIFT)) & SYSCON_USB1CLKDIV_HALT_MASK)
+#define SYSCON_USB1CLKDIV_REQFLAG_MASK           (0x80000000U)
+#define SYSCON_USB1CLKDIV_REQFLAG_SHIFT          (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_USB1CLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB1CLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name FRGCTRL - Fractional rate divider */
+/*! @{ */
+#define SYSCON_FRGCTRL_DIV_MASK                  (0xFFU)
+#define SYSCON_FRGCTRL_DIV_SHIFT                 (0U)
+/*! DIV - Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set
+ *    to 0xFF to use with the fractional baud rate generator.
+ */
+#define SYSCON_FRGCTRL_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK)
+#define SYSCON_FRGCTRL_MULT_MASK                 (0xFF00U)
+#define SYSCON_FRGCTRL_MULT_SHIFT                (8U)
+/*! MULT - Numerator of the fractional divider. MULT is equal to the programmed value.
+ */
+#define SYSCON_FRGCTRL_MULT(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK)
+/*! @} */
+
+/*! @name DMICCLKDIV - DMIC clock divider */
+/*! @{ */
+#define SYSCON_DMICCLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_DMICCLKDIV_DIV_SHIFT              (0U)
+/*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
+ */
+#define SYSCON_DMICCLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK)
+#define SYSCON_DMICCLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_DMICCLKDIV_RESET_SHIFT            (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count.
+ */
+#define SYSCON_DMICCLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK)
+#define SYSCON_DMICCLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_DMICCLKDIV_HALT_SHIFT             (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ *    without the risk of a glitch at the output.
+ */
+#define SYSCON_DMICCLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK)
+#define SYSCON_DMICCLKDIV_REQFLAG_MASK           (0x80000000U)
+#define SYSCON_DMICCLKDIV_REQFLAG_SHIFT          (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_DMICCLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_REQFLAG_SHIFT)) & SYSCON_DMICCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name MCLKDIV - I2S MCLK clock divider */
+/*! @{ */
+#define SYSCON_MCLKDIV_DIV_MASK                  (0xFFU)
+#define SYSCON_MCLKDIV_DIV_SHIFT                 (0U)
+/*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
+ */
+#define SYSCON_MCLKDIV_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK)
+#define SYSCON_MCLKDIV_RESET_MASK                (0x20000000U)
+#define SYSCON_MCLKDIV_RESET_SHIFT               (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_MCLKDIV_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK)
+#define SYSCON_MCLKDIV_HALT_MASK                 (0x40000000U)
+#define SYSCON_MCLKDIV_HALT_SHIFT                (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_MCLKDIV_HALT(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK)
+#define SYSCON_MCLKDIV_REQFLAG_MASK              (0x80000000U)
+#define SYSCON_MCLKDIV_REQFLAG_SHIFT             (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_MCLKDIV_REQFLAG(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name LCDCLKDIV - LCD clock divider */
+/*! @{ */
+#define SYSCON_LCDCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_LCDCLKDIV_DIV_SHIFT               (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_LCDCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_DIV_SHIFT)) & SYSCON_LCDCLKDIV_DIV_MASK)
+#define SYSCON_LCDCLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_LCDCLKDIV_RESET_SHIFT             (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_LCDCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_RESET_SHIFT)) & SYSCON_LCDCLKDIV_RESET_MASK)
+#define SYSCON_LCDCLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_LCDCLKDIV_HALT_SHIFT              (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_LCDCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_HALT_SHIFT)) & SYSCON_LCDCLKDIV_HALT_MASK)
+#define SYSCON_LCDCLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_LCDCLKDIV_REQFLAG_SHIFT           (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_LCDCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_REQFLAG_SHIFT)) & SYSCON_LCDCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name SCTCLKDIV - SCT/PWM clock divider */
+/*! @{ */
+#define SYSCON_SCTCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_SCTCLKDIV_DIV_SHIFT               (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_SCTCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK)
+#define SYSCON_SCTCLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_SCTCLKDIV_RESET_SHIFT             (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_SCTCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK)
+#define SYSCON_SCTCLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_SCTCLKDIV_HALT_SHIFT              (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_SCTCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK)
+#define SYSCON_SCTCLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT           (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_SCTCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name EMCCLKDIV - EMC clock divider */
+/*! @{ */
+#define SYSCON_EMCCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_EMCCLKDIV_DIV_SHIFT               (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_EMCCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_DIV_SHIFT)) & SYSCON_EMCCLKDIV_DIV_MASK)
+#define SYSCON_EMCCLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_EMCCLKDIV_RESET_SHIFT             (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_EMCCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_RESET_SHIFT)) & SYSCON_EMCCLKDIV_RESET_MASK)
+#define SYSCON_EMCCLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_EMCCLKDIV_HALT_SHIFT              (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_EMCCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_HALT_SHIFT)) & SYSCON_EMCCLKDIV_HALT_MASK)
+#define SYSCON_EMCCLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_EMCCLKDIV_REQFLAG_SHIFT           (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_EMCCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_REQFLAG_SHIFT)) & SYSCON_EMCCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name SDIOCLKDIV - SDIO clock divider */
+/*! @{ */
+#define SYSCON_SDIOCLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_SDIOCLKDIV_DIV_SHIFT              (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_SDIOCLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK)
+#define SYSCON_SDIOCLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_SDIOCLKDIV_RESET_SHIFT            (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_SDIOCLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK)
+#define SYSCON_SDIOCLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_SDIOCLKDIV_HALT_SHIFT             (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_SDIOCLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK)
+#define SYSCON_SDIOCLKDIV_REQFLAG_MASK           (0x80000000U)
+#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT          (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_SDIOCLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name USB0CLKCTRL - USB0 clock control */
+/*! @{ */
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK    (0x1U)
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT   (0U)
+/*! AP_FS_DEV_CLK - USB0 Device USB0_NEEDCLK signal control.
+ */
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK   (0x2U)
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT  (1U)
+/*! POL_FS_DEV_CLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt.
+ */
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK   (0x4U)
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT  (2U)
+/*! AP_FS_HOST_CLK - USB0 Host USB0_NEEDCLK signal control.
+ */
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK  (0x8U)
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)
+/*! POL_FS_HOST_CLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt.
+ */
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK       (0x10U)
+#define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT      (4U)
+/*! PU_DISABLE - Internal pull-up disable control.
+ */
+#define SYSCON_USB0CLKCTRL_PU_DISABLE(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK)
+/*! @} */
+
+/*! @name USB0CLKSTAT - USB0 clock status */
+/*! @{ */
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK   (0x1U)
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT  (0U)
+/*! DEV_NEED_CLKST - USB0 Device USB0_NEEDCLK signal status.
+ */
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK)
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK  (0x2U)
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
+/*! HOST_NEED_CLKST - USB0 Host USB0_NEEDCLK signal status.
+ */
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK)
+/*! @} */
+
+/*! @name FREQMECTRL - Frequency measure register */
+/*! @{ */
+#define SYSCON_FREQMECTRL_CAPVAL_MASK            (0x3FFFU)
+#define SYSCON_FREQMECTRL_CAPVAL_SHIFT           (0U)
+/*! CAPVAL - Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only.
+ */
+#define SYSCON_FREQMECTRL_CAPVAL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK)
+#define SYSCON_FREQMECTRL_PROG_MASK              (0x80000000U)
+#define SYSCON_FREQMECTRL_PROG_SHIFT             (31U)
+/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit
+ *    when the measurement cycle has completed and there is valid capture data in the CAPVAL field
+ *    (bits 13:0).
+ */
+#define SYSCON_FREQMECTRL_PROG(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK)
+/*! @} */
+
+/*! @name MCLKIO - MCLK input/output control */
+/*! @{ */
+#define SYSCON_MCLKIO_DIR_MASK                   (0x1U)
+#define SYSCON_MCLKIO_DIR_SHIFT                  (0U)
+/*! DIR - MCLK direction control.
+ */
+#define SYSCON_MCLKIO_DIR(x)                     (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK)
+/*! @} */
+
+/*! @name USB1CLKCTRL - USB1 clock control */
+/*! @{ */
+#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK    (0x1U)
+#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT   (0U)
+/*! AP_FS_DEV_CLK - USB1 Device need_clock signal control.
+ */
+#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK   (0x2U)
+#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT  (1U)
+/*! POL_FS_DEV_CLK - USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt.
+ */
+#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK   (0x4U)
+#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT  (2U)
+/*! AP_FS_HOST_CLK - USB1 Host need_clock signal control.
+ */
+#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK  (0x8U)
+#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)
+/*! POL_FS_HOST_CLK - USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt.
+ */
+#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK  (0x10U)
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U)
+/*! HS_DEV_WAKEUP_N - External user wake-up signal for device mode; asserting this signal (active
+ *    low) will result in exiting the low power mode; input to asynchronous control logic.
+ */
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK)
+/*! @} */
+
+/*! @name USB1CLKSTAT - USB1 clock status */
+/*! @{ */
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK   (0x1U)
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT  (0U)
+/*! DEV_NEED_CLKST - USB1 Device USB1_NEEDCLK signal status.
+ */
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK)
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK  (0x2U)
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
+/*! HOST_NEED_CLKST - USB1 Device host USB1_NEEDCLK signal status.
+ */
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK)
+/*! @} */
+
+/*! @name EMCSYSCTRL - EMC system control */
+/*! @{ */
+#define SYSCON_EMCSYSCTRL_EMCSC_MASK             (0x1U)
+#define SYSCON_EMCSYSCTRL_EMCSC_SHIFT            (0U)
+/*! EMCSC - EMC Shift Control.
+ */
+#define SYSCON_EMCSYSCTRL_EMCSC(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCSC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCSC_MASK)
+#define SYSCON_EMCSYSCTRL_EMCRD_MASK             (0x2U)
+#define SYSCON_EMCSYSCTRL_EMCRD_SHIFT            (1U)
+/*! EMCRD - EMC Reset Disable.
+ */
+#define SYSCON_EMCSYSCTRL_EMCRD(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCRD_SHIFT)) & SYSCON_EMCSYSCTRL_EMCRD_MASK)
+#define SYSCON_EMCSYSCTRL_EMCBC_MASK             (0x4U)
+#define SYSCON_EMCSYSCTRL_EMCBC_SHIFT            (2U)
+/*! EMCBC - External Memory Controller burst control.
+ */
+#define SYSCON_EMCSYSCTRL_EMCBC(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCBC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCBC_MASK)
+#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK     (0x8U)
+#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT    (3U)
+/*! EMCFBCLKINSEL - External Memory Controller clock select.
+ */
+#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT)) & SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK)
+/*! @} */
+
+/*! @name EMCDYCTRL - EMC clock delay control */
+/*! @{ */
+#define SYSCON_EMCDYCTRL_CMD_DELAY_MASK          (0x1FU)
+#define SYSCON_EMCDYCTRL_CMD_DELAY_SHIFT         (0U)
+/*! CMD_DELAY - Programmable delay value for EMC outputs in command delayed mode.
+ */
+#define SYSCON_EMCDYCTRL_CMD_DELAY(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDYCTRL_CMD_DELAY_SHIFT)) & SYSCON_EMCDYCTRL_CMD_DELAY_MASK)
+#define SYSCON_EMCDYCTRL_FBCLK_DELAY_MASK        (0x1F00U)
+#define SYSCON_EMCDYCTRL_FBCLK_DELAY_SHIFT       (8U)
+/*! FBCLK_DELAY - Programmable delay value for the feedback clock that controls input data sampling.
+ */
+#define SYSCON_EMCDYCTRL_FBCLK_DELAY(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDYCTRL_FBCLK_DELAY_SHIFT)) & SYSCON_EMCDYCTRL_FBCLK_DELAY_MASK)
+/*! @} */
+
+/*! @name EMCCAL - EMC delay chain calibration control */
+/*! @{ */
+#define SYSCON_EMCCAL_CALVALUE_MASK              (0xFFU)
+#define SYSCON_EMCCAL_CALVALUE_SHIFT             (0U)
+/*! CALVALUE - Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the FRO 12 MHz.
+ */
+#define SYSCON_EMCCAL_CALVALUE(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCAL_CALVALUE_SHIFT)) & SYSCON_EMCCAL_CALVALUE_MASK)
+#define SYSCON_EMCCAL_START_MASK                 (0x4000U)
+#define SYSCON_EMCCAL_START_SHIFT                (14U)
+/*! START - Start control bit for the EMC calibration counter.
+ */
+#define SYSCON_EMCCAL_START(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCAL_START_SHIFT)) & SYSCON_EMCCAL_START_MASK)
+#define SYSCON_EMCCAL_DONE_MASK                  (0x8000U)
+#define SYSCON_EMCCAL_DONE_SHIFT                 (15U)
+/*! DONE - Measurement completion flag.
+ */
+#define SYSCON_EMCCAL_DONE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCAL_DONE_SHIFT)) & SYSCON_EMCCAL_DONE_MASK)
+/*! @} */
+
+/*! @name ETHPHYSEL - Ethernet PHY Selection */
+/*! @{ */
+#define SYSCON_ETHPHYSEL_PHY_SEL_MASK            (0x4U)
+#define SYSCON_ETHPHYSEL_PHY_SEL_SHIFT           (2U)
+/*! PHY_SEL - PHY interface select.
+ */
+#define SYSCON_ETHPHYSEL_PHY_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHPHYSEL_PHY_SEL_SHIFT)) & SYSCON_ETHPHYSEL_PHY_SEL_MASK)
+/*! @} */
+
+/*! @name ETHSBDCTRL - Ethernet SBD flow control */
+/*! @{ */
+#define SYSCON_ETHSBDCTRL_SBD_CTRL_MASK          (0x3U)
+#define SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT         (0U)
+/*! SBD_CTRL - Sideband Flow Control.
+ */
+#define SYSCON_ETHSBDCTRL_SBD_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT)) & SYSCON_ETHSBDCTRL_SBD_CTRL_MASK)
+/*! @} */
+
+/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */
+/*! @{ */
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK   (0x3U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT  (0U)
+/*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.
+ */
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U)
+/*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
+ */
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK     (0x80U)
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT    (7U)
+/*! PHASE_ACTIVE - sdio_clk by 2, before feeding into ccl_in, cclk_in_sample, and cclk_in_drv.
+ */
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK   (0x1F0000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT  (16U)
+/*! CCLK_DRV_DELAY - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in.
+ */
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U)
+/*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field.
+ */
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U)
+/*! CCLK_SAMPLE_DELAY - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
+ */
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U)
+/*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.
+ */
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK)
+/*! @} */
+
+/*! @name KEYMUXSEL - AES key source selection */
+/*! @{ */
+#define SYSCON_KEYMUXSEL_SEL_MASK                (0x3U)
+#define SYSCON_KEYMUXSEL_SEL_SHIFT               (0U)
+/*! SEL - PHY interface select.
+ */
+#define SYSCON_KEYMUXSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_KEYMUXSEL_SEL_SHIFT)) & SYSCON_KEYMUXSEL_SEL_MASK)
+#define SYSCON_KEYMUXSEL_LOCK_MASK               (0x80U)
+#define SYSCON_KEYMUXSEL_LOCK_SHIFT              (7U)
+/*! LOCK - LOCK stat.
+ */
+#define SYSCON_KEYMUXSEL_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_KEYMUXSEL_LOCK_SHIFT)) & SYSCON_KEYMUXSEL_LOCK_MASK)
+/*! @} */
+
+/*! @name FROCTRL - FRO oscillator control */
+/*! @{ */
+#define SYSCON_FROCTRL_SEL_MASK                  (0x4000U)
+#define SYSCON_FROCTRL_SEL_SHIFT                 (14U)
+/*! SEL - Select the FRO HF output frequency.
+ */
+#define SYSCON_FROCTRL_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK)
+#define SYSCON_FROCTRL_FREQTRIM_MASK             (0xFF0000U)
+#define SYSCON_FROCTRL_FREQTRIM_SHIFT            (16U)
+/*! FREQTRIM - Frequency trim.
+ */
+#define SYSCON_FROCTRL_FREQTRIM(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK)
+#define SYSCON_FROCTRL_USBCLKADJ_MASK            (0x1000000U)
+#define SYSCON_FROCTRL_USBCLKADJ_SHIFT           (24U)
+/*! USBCLKADJ - USB clock adjust mode.
+ */
+#define SYSCON_FROCTRL_USBCLKADJ(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK)
+#define SYSCON_FROCTRL_USBMODCHG_MASK            (0x2000000U)
+#define SYSCON_FROCTRL_USBMODCHG_SHIFT           (25U)
+/*! USBMODCHG - USB Mode value Change flag.
+ */
+#define SYSCON_FROCTRL_USBMODCHG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK)
+#define SYSCON_FROCTRL_HSPDCLK_MASK              (0x40000000U)
+#define SYSCON_FROCTRL_HSPDCLK_SHIFT             (30U)
+/*! HSPDCLK - High speed clock enable.
+ */
+#define SYSCON_FROCTRL_HSPDCLK(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK)
+/*! @} */
+
+/*! @name SYSOSCCTRL - System oscillator control */
+/*! @{ */
+#define SYSCON_SYSOSCCTRL_FREQRANGE_MASK         (0x2U)
+#define SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT        (1U)
+/*! FREQRANGE - Determines frequency range for system oscillator.
+ */
+#define SYSCON_SYSOSCCTRL_FREQRANGE(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT)) & SYSCON_SYSOSCCTRL_FREQRANGE_MASK)
+/*! @} */
+
+/*! @name WDTOSCCTRL - Watchdog oscillator control */
+/*! @{ */
+#define SYSCON_WDTOSCCTRL_DIVSEL_MASK            (0x1FU)
+#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT           (0U)
+/*! DIVSEL - Divider select.
+ */
+#define SYSCON_WDTOSCCTRL_DIVSEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK)
+#define SYSCON_WDTOSCCTRL_FREQSEL_MASK           (0x3E0U)
+#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT          (5U)
+/*! FREQSEL - Frequency select.
+ */
+#define SYSCON_WDTOSCCTRL_FREQSEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK)
+/*! @} */
+
+/*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */
+/*! @{ */
+#define SYSCON_RTCOSCCTRL_EN_MASK                (0x1U)
+#define SYSCON_RTCOSCCTRL_EN_SHIFT               (0U)
+/*! EN - RTC 32 kHz clock enable.
+ */
+#define SYSCON_RTCOSCCTRL_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK)
+/*! @} */
+
+/*! @name USBPLLCTRL - USB PLL control */
+/*! @{ */
+#define SYSCON_USBPLLCTRL_MSEL_MASK              (0xFFU)
+#define SYSCON_USBPLLCTRL_MSEL_SHIFT             (0U)
+/*! MSEL - PLL feedback Divider value.
+ */
+#define SYSCON_USBPLLCTRL_MSEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_MSEL_SHIFT)) & SYSCON_USBPLLCTRL_MSEL_MASK)
+#define SYSCON_USBPLLCTRL_PSEL_MASK              (0x300U)
+#define SYSCON_USBPLLCTRL_PSEL_SHIFT             (8U)
+/*! PSEL - PLL Divider value.
+ */
+#define SYSCON_USBPLLCTRL_PSEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_PSEL_SHIFT)) & SYSCON_USBPLLCTRL_PSEL_MASK)
+#define SYSCON_USBPLLCTRL_NSEL_MASK              (0xC00U)
+#define SYSCON_USBPLLCTRL_NSEL_SHIFT             (10U)
+/*! NSEL - PLL feedback Divider value.
+ */
+#define SYSCON_USBPLLCTRL_NSEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_NSEL_SHIFT)) & SYSCON_USBPLLCTRL_NSEL_MASK)
+#define SYSCON_USBPLLCTRL_DIRECT_MASK            (0x1000U)
+#define SYSCON_USBPLLCTRL_DIRECT_SHIFT           (12U)
+/*! DIRECT - Direct CCO clock output control.
+ *  0b0..CCO Clock signal goes through post divider.
+ *  0b1..CCO Clock signal goes directly to output(s)..
+ */
+#define SYSCON_USBPLLCTRL_DIRECT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_DIRECT_SHIFT)) & SYSCON_USBPLLCTRL_DIRECT_MASK)
+#define SYSCON_USBPLLCTRL_BYPASS_MASK            (0x2000U)
+#define SYSCON_USBPLLCTRL_BYPASS_SHIFT           (13U)
+/*! BYPASS - Input clock bypass control.
+ *  0b0..CCO clock is sent to post dividers..
+ *  0b1..PLL input clock is sent to post dividers..
+ */
+#define SYSCON_USBPLLCTRL_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_BYPASS_SHIFT)) & SYSCON_USBPLLCTRL_BYPASS_MASK)
+#define SYSCON_USBPLLCTRL_FBSEL_MASK             (0x4000U)
+#define SYSCON_USBPLLCTRL_FBSEL_SHIFT            (14U)
+/*! FBSEL - Feedback divider input clock control.
+ */
+#define SYSCON_USBPLLCTRL_FBSEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_FBSEL_SHIFT)) & SYSCON_USBPLLCTRL_FBSEL_MASK)
+/*! @} */
+
+/*! @name USBPLLSTAT - USB PLL status */
+/*! @{ */
+#define SYSCON_USBPLLSTAT_LOCK_MASK              (0x1U)
+#define SYSCON_USBPLLSTAT_LOCK_SHIFT             (0U)
+/*! LOCK - USBPLL lock indicator.
+ */
+#define SYSCON_USBPLLSTAT_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLSTAT_LOCK_SHIFT)) & SYSCON_USBPLLSTAT_LOCK_MASK)
+/*! @} */
+
+/*! @name SYSPLLCTRL - System PLL control */
+/*! @{ */
+#define SYSCON_SYSPLLCTRL_SELR_MASK              (0xFU)
+#define SYSCON_SYSPLLCTRL_SELR_SHIFT             (0U)
+/*! SELR - Bandwidth select R value.
+ */
+#define SYSCON_SYSPLLCTRL_SELR(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK)
+#define SYSCON_SYSPLLCTRL_SELI_MASK              (0x3F0U)
+#define SYSCON_SYSPLLCTRL_SELI_SHIFT             (4U)
+/*! SELI - Bandwidth select I value.
+ */
+#define SYSCON_SYSPLLCTRL_SELI(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK)
+#define SYSCON_SYSPLLCTRL_SELP_MASK              (0x7C00U)
+#define SYSCON_SYSPLLCTRL_SELP_SHIFT             (10U)
+/*! SELP - Bandwidth select P value.
+ */
+#define SYSCON_SYSPLLCTRL_SELP(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK)
+#define SYSCON_SYSPLLCTRL_BYPASS_MASK            (0x8000U)
+#define SYSCON_SYSPLLCTRL_BYPASS_SHIFT           (15U)
+/*! BYPASS - PLL bypass control.
+ *  0b0..Bypass disabled. PLL CCO is sent to the PLL post-dividers.
+ *  0b1..Bypass enabled. PLL input clock is sent directly to the PLL output (default).
+ */
+#define SYSCON_SYSPLLCTRL_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK)
+#define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK          (0x20000U)
+#define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT         (17U)
+/*! UPLIMOFF - Disable upper frequency limiter.
+ */
+#define SYSCON_SYSPLLCTRL_UPLIMOFF(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK)
+#define SYSCON_SYSPLLCTRL_DIRECTI_MASK           (0x80000U)
+#define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT          (19U)
+/*! DIRECTI - PLL0 direct input enable.
+ */
+#define SYSCON_SYSPLLCTRL_DIRECTI(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK)
+#define SYSCON_SYSPLLCTRL_DIRECTO_MASK           (0x100000U)
+#define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT          (20U)
+/*! DIRECTO - PLL0 direct output enable.
+ *  0b0..Disabled. The PLL output divider (P divider) is used to create the PLL output.
+ *  0b1..Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output.
+ */
+#define SYSCON_SYSPLLCTRL_DIRECTO(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK)
+/*! @} */
+
+/*! @name SYSPLLSTAT - PLL status */
+/*! @{ */
+#define SYSCON_SYSPLLSTAT_LOCK_MASK              (0x1U)
+#define SYSCON_SYSPLLSTAT_LOCK_SHIFT             (0U)
+/*! LOCK - PLL lock indicator.
+ */
+#define SYSCON_SYSPLLSTAT_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK)
+/*! @} */
+
+/*! @name SYSPLLNDEC - PLL N divider */
+/*! @{ */
+#define SYSCON_SYSPLLNDEC_NDEC_MASK              (0x3FFU)
+#define SYSCON_SYSPLLNDEC_NDEC_SHIFT             (0U)
+/*! NDEC - Decoded N-divider coefficient value.
+ */
+#define SYSCON_SYSPLLNDEC_NDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK)
+#define SYSCON_SYSPLLNDEC_NREQ_MASK              (0x400U)
+#define SYSCON_SYSPLLNDEC_NREQ_SHIFT             (10U)
+/*! NREQ - NDEC reload request.
+ */
+#define SYSCON_SYSPLLNDEC_NREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK)
+/*! @} */
+
+/*! @name SYSPLLPDEC - PLL P divider */
+/*! @{ */
+#define SYSCON_SYSPLLPDEC_PDEC_MASK              (0x7FU)
+#define SYSCON_SYSPLLPDEC_PDEC_SHIFT             (0U)
+/*! PDEC - Decoded P-divider coefficient value.
+ */
+#define SYSCON_SYSPLLPDEC_PDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK)
+#define SYSCON_SYSPLLPDEC_PREQ_MASK              (0x80U)
+#define SYSCON_SYSPLLPDEC_PREQ_SHIFT             (7U)
+/*! PREQ - .
+ */
+#define SYSCON_SYSPLLPDEC_PREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK)
+/*! @} */
+
+/*! @name SYSPLLMDEC - System PLL M divider */
+/*! @{ */
+#define SYSCON_SYSPLLMDEC_MDEC_MASK              (0x1FFFFU)
+#define SYSCON_SYSPLLMDEC_MDEC_SHIFT             (0U)
+/*! MDEC - Decoded M-divider coefficient value.
+ */
+#define SYSCON_SYSPLLMDEC_MDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MDEC_SHIFT)) & SYSCON_SYSPLLMDEC_MDEC_MASK)
+#define SYSCON_SYSPLLMDEC_MREQ_MASK              (0x20000U)
+#define SYSCON_SYSPLLMDEC_MREQ_SHIFT             (17U)
+/*! MREQ - MDEC reload request.
+ */
+#define SYSCON_SYSPLLMDEC_MREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MREQ_SHIFT)) & SYSCON_SYSPLLMDEC_MREQ_MASK)
+/*! @} */
+
+/*! @name AUDPLLCTRL - Audio PLL control */
+/*! @{ */
+#define SYSCON_AUDPLLCTRL_SELR_MASK              (0xFU)
+#define SYSCON_AUDPLLCTRL_SELR_SHIFT             (0U)
+/*! SELR - Bandwidth select R value.
+ */
+#define SYSCON_AUDPLLCTRL_SELR(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELR_SHIFT)) & SYSCON_AUDPLLCTRL_SELR_MASK)
+#define SYSCON_AUDPLLCTRL_SELI_MASK              (0x3F0U)
+#define SYSCON_AUDPLLCTRL_SELI_SHIFT             (4U)
+/*! SELI - Bandwidth select I value.
+ */
+#define SYSCON_AUDPLLCTRL_SELI(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELI_SHIFT)) & SYSCON_AUDPLLCTRL_SELI_MASK)
+#define SYSCON_AUDPLLCTRL_SELP_MASK              (0x7C00U)
+#define SYSCON_AUDPLLCTRL_SELP_SHIFT             (10U)
+/*! SELP - .
+ */
+#define SYSCON_AUDPLLCTRL_SELP(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELP_SHIFT)) & SYSCON_AUDPLLCTRL_SELP_MASK)
+#define SYSCON_AUDPLLCTRL_BYPASS_MASK            (0x8000U)
+#define SYSCON_AUDPLLCTRL_BYPASS_SHIFT           (15U)
+/*! BYPASS - PLL bypass control.
+ *  0b0..Bypass disabled. PLL CCO is sent to the PLL post-dividers.
+ *  0b1..Bypass enabled. PLL input clock is sent directly to the PLL output (default).
+ */
+#define SYSCON_AUDPLLCTRL_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_BYPASS_SHIFT)) & SYSCON_AUDPLLCTRL_BYPASS_MASK)
+#define SYSCON_AUDPLLCTRL_UPLIMOFF_MASK          (0x20000U)
+#define SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT         (17U)
+/*! UPLIMOFF - Disable upper frequency limiter.
+ */
+#define SYSCON_AUDPLLCTRL_UPLIMOFF(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_AUDPLLCTRL_UPLIMOFF_MASK)
+#define SYSCON_AUDPLLCTRL_DIRECTI_MASK           (0x80000U)
+#define SYSCON_AUDPLLCTRL_DIRECTI_SHIFT          (19U)
+/*! DIRECTI - PLL direct input enable.
+ */
+#define SYSCON_AUDPLLCTRL_DIRECTI(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTI_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTI_MASK)
+#define SYSCON_AUDPLLCTRL_DIRECTO_MASK           (0x100000U)
+#define SYSCON_AUDPLLCTRL_DIRECTO_SHIFT          (20U)
+/*! DIRECTO - PLL direct output enable
+ *  0b0..Disabled. The PLL output divider (P divider) is used to create the PLL output.
+ *  0b1..Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output.
+ */
+#define SYSCON_AUDPLLCTRL_DIRECTO(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTO_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTO_MASK)
+/*! @} */
+
+/*! @name AUDPLLSTAT - Audio PLL status */
+/*! @{ */
+#define SYSCON_AUDPLLSTAT_LOCK_MASK              (0x1U)
+#define SYSCON_AUDPLLSTAT_LOCK_SHIFT             (0U)
+/*! LOCK - PLL lock indicator.
+ */
+#define SYSCON_AUDPLLSTAT_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLSTAT_LOCK_SHIFT)) & SYSCON_AUDPLLSTAT_LOCK_MASK)
+/*! @} */
+
+/*! @name AUDPLLNDEC - Audio PLL N divider */
+/*! @{ */
+#define SYSCON_AUDPLLNDEC_NDEC_MASK              (0x3FFU)
+#define SYSCON_AUDPLLNDEC_NDEC_SHIFT             (0U)
+/*! NDEC - Decoded N-divider coefficient value.
+ */
+#define SYSCON_AUDPLLNDEC_NDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NDEC_SHIFT)) & SYSCON_AUDPLLNDEC_NDEC_MASK)
+#define SYSCON_AUDPLLNDEC_NREQ_MASK              (0x400U)
+#define SYSCON_AUDPLLNDEC_NREQ_SHIFT             (10U)
+/*! NREQ - NDEC reload request.
+ */
+#define SYSCON_AUDPLLNDEC_NREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NREQ_SHIFT)) & SYSCON_AUDPLLNDEC_NREQ_MASK)
+/*! @} */
+
+/*! @name AUDPLLPDEC - Audio PLL P divider */
+/*! @{ */
+#define SYSCON_AUDPLLPDEC_PDEC_MASK              (0x7FU)
+#define SYSCON_AUDPLLPDEC_PDEC_SHIFT             (0U)
+/*! PDEC - Decoded P-divider coefficient value.
+ */
+#define SYSCON_AUDPLLPDEC_PDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PDEC_SHIFT)) & SYSCON_AUDPLLPDEC_PDEC_MASK)
+#define SYSCON_AUDPLLPDEC_PREQ_MASK              (0x80U)
+#define SYSCON_AUDPLLPDEC_PREQ_SHIFT             (7U)
+/*! PREQ - PDEC reload request.
+ */
+#define SYSCON_AUDPLLPDEC_PREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PREQ_SHIFT)) & SYSCON_AUDPLLPDEC_PREQ_MASK)
+/*! @} */
+
+/*! @name AUDPLLMDEC - Audio PLL M divider */
+/*! @{ */
+#define SYSCON_AUDPLLMDEC_MDEC_MASK              (0x1FFFFU)
+#define SYSCON_AUDPLLMDEC_MDEC_SHIFT             (0U)
+/*! MDEC - Decoded M-divider coefficient value.
+ */
+#define SYSCON_AUDPLLMDEC_MDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MDEC_SHIFT)) & SYSCON_AUDPLLMDEC_MDEC_MASK)
+#define SYSCON_AUDPLLMDEC_MREQ_MASK              (0x20000U)
+#define SYSCON_AUDPLLMDEC_MREQ_SHIFT             (17U)
+/*! MREQ - MDEC reload request.
+ */
+#define SYSCON_AUDPLLMDEC_MREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MREQ_SHIFT)) & SYSCON_AUDPLLMDEC_MREQ_MASK)
+/*! @} */
+
+/*! @name AUDPLLFRAC - Audio PLL fractional divider control */
+/*! @{ */
+#define SYSCON_AUDPLLFRAC_CTRL_MASK              (0x3FFFFFU)
+#define SYSCON_AUDPLLFRAC_CTRL_SHIFT             (0U)
+/*! CTRL - PLL fractional divider control word
+ */
+#define SYSCON_AUDPLLFRAC_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_CTRL_SHIFT)) & SYSCON_AUDPLLFRAC_CTRL_MASK)
+#define SYSCON_AUDPLLFRAC_REQ_MASK               (0x400000U)
+#define SYSCON_AUDPLLFRAC_REQ_SHIFT              (22U)
+/*! REQ - Writing 1 to REQ signal loads CTRL value into fractional wrapper modulator.
+ */
+#define SYSCON_AUDPLLFRAC_REQ(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_REQ_SHIFT)) & SYSCON_AUDPLLFRAC_REQ_MASK)
+#define SYSCON_AUDPLLFRAC_SEL_EXT_MASK           (0x800000U)
+#define SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT          (23U)
+/*! SEL_EXT - Select fractional divider.
+ */
+#define SYSCON_AUDPLLFRAC_SEL_EXT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT)) & SYSCON_AUDPLLFRAC_SEL_EXT_MASK)
+/*! @} */
+
+/*! @name PDSLEEPCFG - Sleep configuration register */
+/*! @{ */
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK     (0x1U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT    (0U)
+/*! PDEN_USB1_PHY - USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK     (0x2U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT    (1U)
+/*! PDEN_USB1_PLL - USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK      (0x4U)
+#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT     (2U)
+/*! PDEN_AUD_PLL - Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK       (0x8U)
+#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT      (3U)
+/*! PDEN_SYSOSC - System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_FRO_MASK          (0x10U)
+#define SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT         (4U)
+/*! PDEN_FRO - FRO oscillator.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_FRO(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_FRO_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_TS_MASK           (0x40U)
+#define SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT          (6U)
+/*! PDEN_TS - Temp sensor.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_TS(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_TS_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK      (0x80U)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT     (7U)
+/*! PDEN_BOD_RST - Brown-out Detect reset.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_RNG_MASK          (0x80U)
+#define SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT         (7U)
+/*! PDEN_RNG - Random Number Generator Power.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_RNG(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_RNG_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK     (0x100U)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT    (8U)
+/*! PDEN_BOD_INTR - Brown-out Detect interrupt.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK      (0x200U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT     (9U)
+/*! PDEN_VD2_ANA - Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1
+ *    register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19,
+ *    and 23).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK         (0x400U)
+#define SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT        (10U)
+/*! PDEN_ADC0 - ADC power.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_ADC0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK        (0x2000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT       (13U)
+/*! PDEN_SRAMX - PDEN_SRAMX controls SRAMX (also enable/disable bit 27).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_SRAMX(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK        (0x4000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT       (14U)
+/*! PDEN_SRAM0 - PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK    (0x8000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT   (15U)
+/*! PDEN_SRAM1_2_3 - PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK      (0x10000U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT     (16U)
+/*! PDEN_USB_RAM - PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_ROM_MASK          (0x20000U)
+#define SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT         (17U)
+/*! PDEN_ROM - ROM (also enable/disable bit 27).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_ROM(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ROM_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK         (0x80000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT        (19U)
+/*! PDEN_VDDA - Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_VDDA(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK      (0x100000U)
+#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT     (20U)
+/*! PDEN_WDT_OSC - Watchdog oscillator.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK     (0x200000U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT    (21U)
+/*! PDEN_USB0_PHY - USB0 PHY power (also enable/disable bit 28).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK      (0x400000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT     (22U)
+/*! PDEN_SYS_PLL - System PLL (PLL0) power (also enable/disable bit 26).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK        (0x800000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT       (23U)
+/*! PDEN_VREFP - VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_VREFP(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD3_MASK          (0x4000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT         (26U)
+/*! PDEN_VD3 - Power control for all PLLs.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_VD3(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD3_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD4_MASK          (0x8000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT         (27U)
+/*! PDEN_VD4 - Power control for all SRAMs and ROM.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_VD4(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD4_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD5_MASK          (0x10000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT         (28U)
+/*! PDEN_VD5 - Power control both USB0 PHY and USB1 PHY.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_VD5(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD5_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD6_MASK          (0x20000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT         (29U)
+/*! PDEN_VD6 - Power control for EEPROM.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_VD6(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD6_MASK)
+/*! @} */
+
+/* The count of SYSCON_PDSLEEPCFG */
+#define SYSCON_PDSLEEPCFG_COUNT                  (2U)
+
+/*! @name PDRUNCFG - Power configuration register */
+/*! @{ */
+#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK       (0x1U)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT      (0U)
+/*! PDEN_USB1_PHY - USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFG_PDEN_USB1_PHY(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK       (0x2U)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT      (1U)
+/*! PDEN_USB1_PLL - USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFG_PDEN_USB1_PLL(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK        (0x4U)
+#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT       (2U)
+/*! PDEN_AUD_PLL - Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFG_PDEN_AUD_PLL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK         (0x8U)
+#define SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT        (3U)
+/*! PDEN_SYSOSC - System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFG_PDEN_SYSOSC(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK)
+#define SYSCON_PDRUNCFG_PDEN_FRO_MASK            (0x10U)
+#define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT           (4U)
+/*! PDEN_FRO - FRO oscillator.
+ */
+#define SYSCON_PDRUNCFG_PDEN_FRO(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK)
+#define SYSCON_PDRUNCFG_PDEN_TS_MASK             (0x40U)
+#define SYSCON_PDRUNCFG_PDEN_TS_SHIFT            (6U)
+/*! PDEN_TS - Temp sensor.
+ */
+#define SYSCON_PDRUNCFG_PDEN_TS(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK)
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK        (0x80U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT       (7U)
+/*! PDEN_BOD_RST - Brown-out Detect reset.
+ */
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK)
+#define SYSCON_PDRUNCFG_PDEN_RNG_MASK            (0x80U)
+#define SYSCON_PDRUNCFG_PDEN_RNG_SHIFT           (7U)
+/*! PDEN_RNG - Random Number Generator Power.
+ */
+#define SYSCON_PDRUNCFG_PDEN_RNG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFG_PDEN_RNG_MASK)
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK       (0x100U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT      (8U)
+/*! PDEN_BOD_INTR - Brown-out Detect interrupt.
+ */
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK        (0x200U)
+#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT       (9U)
+/*! PDEN_VD2_ANA - Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1
+ *    register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19,
+ *    and 23).
+ */
+#define SYSCON_PDRUNCFG_PDEN_VD2_ANA(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDRUNCFG_PDEN_ADC0_MASK           (0x400U)
+#define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT          (10U)
+/*! PDEN_ADC0 - ADC power.
+ */
+#define SYSCON_PDRUNCFG_PDEN_ADC0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK          (0x2000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT         (13U)
+/*! PDEN_SRAMX - PPDEN_SRAMX controls only SRAMX address 0x0 to 0x0000FFFF.Bit 29 (PDEN_VD6)
+ *    controls SRAMX address 0x00010000 to 0x0002FFFF..
+ */
+#define SYSCON_PDRUNCFG_PDEN_SRAMX(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK          (0x4000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT         (14U)
+/*! PDEN_SRAM0 - PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFG_PDEN_SRAM0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK      (0x8000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT     (15U)
+/*! PDEN_SRAM1_2_3 - PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK        (0x10000U)
+#define SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT       (16U)
+/*! PDEN_USB_RAM - PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFG_PDEN_USB_RAM(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK)
+#define SYSCON_PDRUNCFG_PDEN_ROM_MASK            (0x20000U)
+#define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT           (17U)
+/*! PDEN_ROM - ROM (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFG_PDEN_ROM(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VDDA_MASK           (0x80000U)
+#define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT          (19U)
+/*! PDEN_VDDA - Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).
+ */
+#define SYSCON_PDRUNCFG_PDEN_VDDA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK)
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK        (0x100000U)
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT       (20U)
+/*! PDEN_WDT_OSC - Watchdog oscillator.
+ */
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK       (0x200000U)
+#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT      (21U)
+/*! PDEN_USB0_PHY - USB0 PHY power (also enable/disable bit 28).
+ */
+#define SYSCON_PDRUNCFG_PDEN_USB0_PHY(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK        (0x400000U)
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT       (22U)
+/*! PDEN_SYS_PLL - System PLL (PLL0) power (also enable/disable bit 26).
+ */
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VREFP_MASK          (0x800000U)
+#define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT         (23U)
+/*! PDEN_VREFP - VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).
+ */
+#define SYSCON_PDRUNCFG_PDEN_VREFP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD3_MASK            (0x4000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD3_SHIFT           (26U)
+/*! PDEN_VD3 - Power control for all PLLs.
+ */
+#define SYSCON_PDRUNCFG_PDEN_VD3(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD3_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD4_MASK            (0x8000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD4_SHIFT           (27U)
+/*! PDEN_VD4 - Power control for all SRAMs and ROM.
+ */
+#define SYSCON_PDRUNCFG_PDEN_VD4(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD4_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD5_MASK            (0x10000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD5_SHIFT           (28U)
+/*! PDEN_VD5 - Power control both USB0 PHY and USB1 PHY.
+ */
+#define SYSCON_PDRUNCFG_PDEN_VD5(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD5_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD6_MASK            (0x20000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD6_SHIFT           (29U)
+/*! PDEN_VD6 - Power control for OTP and SRAMX from address 0x00010000 to 0x0002FFFF.
+ */
+#define SYSCON_PDRUNCFG_PDEN_VD6(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD6_MASK)
+/*! @} */
+
+/* The count of SYSCON_PDRUNCFG */
+#define SYSCON_PDRUNCFG_COUNT                    (2U)
+
+/*! @name PDRUNCFGSET - Power configuration set register */
+/*! @{ */
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK    (0x1U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT   (0U)
+/*! PDEN_USB1_PHY - USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK    (0x2U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT   (1U)
+/*! PDEN_USB1_PLL - USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK     (0x4U)
+#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT    (2U)
+/*! PDEN_AUD_PLL - Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK      (0x8U)
+#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT     (3U)
+/*! PDEN_SYSOSC - System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_FRO_MASK         (0x10U)
+#define SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT        (4U)
+/*! PDEN_FRO - FRO oscillator.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_FRO(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_FRO_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_TS_MASK          (0x40U)
+#define SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT         (6U)
+/*! PDEN_TS - Temp sensor.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_TS(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_TS_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK     (0x80U)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT    (7U)
+/*! PDEN_BOD_RST - Brown-out Detect reset.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_RNG_MASK         (0x80U)
+#define SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT        (7U)
+/*! PDEN_RNG - Random Number Generator Power.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_RNG(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_RNG_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK    (0x100U)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT   (8U)
+/*! PDEN_BOD_INTR - Brown-out Detect interrupt.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK     (0x200U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT    (9U)
+/*! PDEN_VD2_ANA - Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1
+ *    register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19,
+ *    and 23).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK        (0x400U)
+#define SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT       (10U)
+/*! PDEN_ADC0 - ADC power.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_ADC0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK       (0x2000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT      (13U)
+/*! PDEN_SRAMX - PDEN_SRAMX controls SRAMX (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_SRAMX(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK       (0x4000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT      (14U)
+/*! PDEN_SRAM0 - PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM0(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK   (0x8000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT  (15U)
+/*! PDEN_SRAM1_2_3 - PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK     (0x10000U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT    (16U)
+/*! PDEN_USB_RAM - PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_ROM_MASK         (0x20000U)
+#define SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT        (17U)
+/*! PDEN_ROM - ROM (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_ROM(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ROM_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK        (0x80000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT       (19U)
+/*! PDEN_VDDA - Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_VDDA(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK     (0x100000U)
+#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT    (20U)
+/*! PDEN_WDT_OSC - Watchdog oscillator.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK    (0x200000U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT   (21U)
+/*! PDEN_USB0_PHY - USB0 PHY power (also enable/disable bit 28).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK     (0x400000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT    (22U)
+/*! PDEN_SYS_PLL - System PLL (PLL0) power (also enable/disable bit 26).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK       (0x800000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT      (23U)
+/*! PDEN_VREFP - VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_VREFP(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD3_MASK         (0x4000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT        (26U)
+/*! PDEN_VD3 - Power control for all PLLs.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_VD3(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD3_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD4_MASK         (0x8000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT        (27U)
+/*! PDEN_VD4 - Power control for all SRAMs and ROM.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_VD4(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD4_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD5_MASK         (0x10000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT        (28U)
+/*! PDEN_VD5 - Power control both USB0 PHY and USB1 PHY.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_VD5(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD5_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD6_MASK         (0x20000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT        (29U)
+/*! PDEN_VD6 - Power control for EEPROM.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_VD6(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD6_MASK)
+/*! @} */
+
+/* The count of SYSCON_PDRUNCFGSET */
+#define SYSCON_PDRUNCFGSET_COUNT                 (2U)
+
+/*! @name PDRUNCFGCLR - Power configuration clear register */
+/*! @{ */
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK    (0x1U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT   (0U)
+/*! PDEN_USB1_PHY - USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK    (0x2U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT   (1U)
+/*! PDEN_USB1_PLL - USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK     (0x4U)
+#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT    (2U)
+/*! PDEN_AUD_PLL - Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK      (0x8U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT     (3U)
+/*! PDEN_SYSOSC - System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK         (0x10U)
+#define SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT        (4U)
+/*! PDEN_FRO - FRO oscillator.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_FRO(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_TS_MASK          (0x40U)
+#define SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT         (6U)
+/*! PDEN_TS - Temp sensor.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_TS(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_TS_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK     (0x80U)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT    (7U)
+/*! PDEN_BOD_RST - Brown-out Detect reset.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK         (0x80U)
+#define SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT        (7U)
+/*! PDEN_RNG - Random Number Generator Power.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_RNG(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK    (0x100U)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT   (8U)
+/*! PDEN_BOD_INTR - Brown-out Detect interrupt.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK     (0x200U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT    (9U)
+/*! PDEN_VD2_ANA - Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1
+ *    register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19,
+ *    and 23).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK        (0x400U)
+#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT       (10U)
+/*! PDEN_ADC0 - ADC power.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_ADC0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK       (0x2000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT      (13U)
+/*! PDEN_SRAMX - PDEN_SRAMX controls SRAMX (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK       (0x4000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT      (14U)
+/*! PDEN_SRAM0 - PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK   (0x8000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT  (15U)
+/*! PDEN_SRAM1_2_3 - PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK     (0x10000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT    (16U)
+/*! PDEN_USB_RAM - PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK         (0x20000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT        (17U)
+/*! PDEN_ROM - ROM (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_ROM(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK        (0x80000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT       (19U)
+/*! PDEN_VDDA - Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_VDDA(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK     (0x100000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT    (20U)
+/*! PDEN_WDT_OSC - Watchdog oscillator.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK    (0x200000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT   (21U)
+/*! PDEN_USB0_PHY - USB0 PHY power (also enable/disable bit 28).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK     (0x400000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT    (22U)
+/*! PDEN_SYS_PLL - System PLL (PLL0) power (also enable/disable bit 26).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK       (0x800000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT      (23U)
+/*! PDEN_VREFP - VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_VREFP(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK         (0x4000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT        (26U)
+/*! PDEN_VD3 - Power control for all PLLs.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_VD3(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK         (0x8000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT        (27U)
+/*! PDEN_VD4 - Power control for all SRAMs and ROM.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_VD4(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK         (0x10000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT        (28U)
+/*! PDEN_VD5 - Power control both USB0 PHY and USB1 PHY.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_VD5(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK         (0x20000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT        (29U)
+/*! PDEN_VD6 - Power control for EEPROM.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_VD6(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK)
+/*! @} */
+
+/* The count of SYSCON_PDRUNCFGCLR */
+#define SYSCON_PDRUNCFGCLR_COUNT                 (2U)
+
+/*! @name STARTER - Start logic 0 wake-up enable register */
+/*! @{ */
+#define SYSCON_STARTER_PINT4_MASK                (0x1U)
+#define SYSCON_STARTER_PINT4_SHIFT               (0U)
+/*! PINT4 - GPIO pin interrupt 4 wake-up.
+ */
+#define SYSCON_STARTER_PINT4(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT4_SHIFT)) & SYSCON_STARTER_PINT4_MASK)
+#define SYSCON_STARTER_WDT_BOD_MASK              (0x1U)
+#define SYSCON_STARTER_WDT_BOD_SHIFT             (0U)
+/*! WDT_BOD - WWDT and BOD interrupt wake-up.
+ */
+#define SYSCON_STARTER_WDT_BOD(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WDT_BOD_SHIFT)) & SYSCON_STARTER_WDT_BOD_MASK)
+#define SYSCON_STARTER_DMA_MASK                  (0x2U)
+#define SYSCON_STARTER_DMA_SHIFT                 (1U)
+/*! DMA - DMA wake-up.
+ */
+#define SYSCON_STARTER_DMA(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMA_SHIFT)) & SYSCON_STARTER_DMA_MASK)
+#define SYSCON_STARTER_PINT5_MASK                (0x2U)
+#define SYSCON_STARTER_PINT5_SHIFT               (1U)
+/*! PINT5 - GPIO pin interrupt 5 wake-up.
+ */
+#define SYSCON_STARTER_PINT5(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT5_SHIFT)) & SYSCON_STARTER_PINT5_MASK)
+#define SYSCON_STARTER_GINT0_MASK                (0x4U)
+#define SYSCON_STARTER_GINT0_SHIFT               (2U)
+/*! GINT0 - Group interrupt 0 wake-up.
+ */
+#define SYSCON_STARTER_GINT0(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK)
+#define SYSCON_STARTER_PINT6_MASK                (0x4U)
+#define SYSCON_STARTER_PINT6_SHIFT               (2U)
+/*! PINT6 - GPIO pin interrupt 6 wake-up.
+ */
+#define SYSCON_STARTER_PINT6(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT6_SHIFT)) & SYSCON_STARTER_PINT6_MASK)
+#define SYSCON_STARTER_GINT1_MASK                (0x8U)
+#define SYSCON_STARTER_GINT1_SHIFT               (3U)
+/*! GINT1 - Group interrupt 1 wake-up.
+ */
+#define SYSCON_STARTER_GINT1(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK)
+#define SYSCON_STARTER_PINT7_MASK                (0x8U)
+#define SYSCON_STARTER_PINT7_SHIFT               (3U)
+/*! PINT7 - GPIO pin interrupt 7 wake-up.
+ */
+#define SYSCON_STARTER_PINT7(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT7_SHIFT)) & SYSCON_STARTER_PINT7_MASK)
+#define SYSCON_STARTER_PIN_INT0_MASK             (0x10U)
+#define SYSCON_STARTER_PIN_INT0_SHIFT            (4U)
+/*! PIN_INT0 - GPIO pin interrupt 0 wake-up.
+ */
+#define SYSCON_STARTER_PIN_INT0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT0_SHIFT)) & SYSCON_STARTER_PIN_INT0_MASK)
+#define SYSCON_STARTER_PIN_INT1_MASK             (0x20U)
+#define SYSCON_STARTER_PIN_INT1_SHIFT            (5U)
+/*! PIN_INT1 - GPIO pin interrupt 1 wake-up.
+ */
+#define SYSCON_STARTER_PIN_INT1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT1_SHIFT)) & SYSCON_STARTER_PIN_INT1_MASK)
+#define SYSCON_STARTER_PIN_INT2_MASK             (0x40U)
+#define SYSCON_STARTER_PIN_INT2_SHIFT            (6U)
+/*! PIN_INT2 - GPIO pin interrupt 2 wake-up.
+ */
+#define SYSCON_STARTER_PIN_INT2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT2_SHIFT)) & SYSCON_STARTER_PIN_INT2_MASK)
+#define SYSCON_STARTER_PIN_INT3_MASK             (0x80U)
+#define SYSCON_STARTER_PIN_INT3_SHIFT            (7U)
+/*! PIN_INT3 - GPIO pin interrupt 3 wake-up.
+ */
+#define SYSCON_STARTER_PIN_INT3(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT3_SHIFT)) & SYSCON_STARTER_PIN_INT3_MASK)
+#define SYSCON_STARTER_FLEXCOMM8_MASK            (0x100U)
+#define SYSCON_STARTER_FLEXCOMM8_SHIFT           (8U)
+/*! FLEXCOMM8 - Flexcomm Interface 8 wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM8(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM8_SHIFT)) & SYSCON_STARTER_FLEXCOMM8_MASK)
+#define SYSCON_STARTER_UTICK_MASK                (0x100U)
+#define SYSCON_STARTER_UTICK_SHIFT               (8U)
+/*! UTICK - Micro-tick Timer wake-up.
+ */
+#define SYSCON_STARTER_UTICK(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK_SHIFT)) & SYSCON_STARTER_UTICK_MASK)
+#define SYSCON_STARTER_FLEXCOMM9_MASK            (0x200U)
+#define SYSCON_STARTER_FLEXCOMM9_SHIFT           (9U)
+/*! FLEXCOMM9 - Flexcomm Interface 9 wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM9(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM9_SHIFT)) & SYSCON_STARTER_FLEXCOMM9_MASK)
+#define SYSCON_STARTER_FLEXCOMM0_MASK            (0x4000U)
+#define SYSCON_STARTER_FLEXCOMM0_SHIFT           (14U)
+/*! FLEXCOMM0 - Flexcomm0 peripheral interrupt wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM0_SHIFT)) & SYSCON_STARTER_FLEXCOMM0_MASK)
+#define SYSCON_STARTER_FLEXCOMM1_MASK            (0x8000U)
+#define SYSCON_STARTER_FLEXCOMM1_SHIFT           (15U)
+/*! FLEXCOMM1 - Flexcomm1 peripheral interrupt wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM1(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM1_SHIFT)) & SYSCON_STARTER_FLEXCOMM1_MASK)
+#define SYSCON_STARTER_USB1_MASK                 (0x8000U)
+#define SYSCON_STARTER_USB1_SHIFT                (15U)
+/*! USB1 - USB 1 wake-up.
+ */
+#define SYSCON_STARTER_USB1(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK)
+#define SYSCON_STARTER_FLEXCOMM2_MASK            (0x10000U)
+#define SYSCON_STARTER_FLEXCOMM2_SHIFT           (16U)
+/*! FLEXCOMM2 - Flexcomm2 peripheral interrupt wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM2(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM2_SHIFT)) & SYSCON_STARTER_FLEXCOMM2_MASK)
+#define SYSCON_STARTER_USB1_ACT_MASK             (0x10000U)
+#define SYSCON_STARTER_USB1_ACT_SHIFT            (16U)
+/*! USB1_ACT - USB 1 activity wake-up.
+ */
+#define SYSCON_STARTER_USB1_ACT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_ACT_SHIFT)) & SYSCON_STARTER_USB1_ACT_MASK)
+#define SYSCON_STARTER_FLEXCOMM3_MASK            (0x20000U)
+#define SYSCON_STARTER_FLEXCOMM3_SHIFT           (17U)
+/*! FLEXCOMM3 - Flexcomm3 peripheral interrupt wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM3(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM3_SHIFT)) & SYSCON_STARTER_FLEXCOMM3_MASK)
+#define SYSCON_STARTER_FLEXCOMM4_MASK            (0x40000U)
+#define SYSCON_STARTER_FLEXCOMM4_SHIFT           (18U)
+/*! FLEXCOMM4 - Flexcomm4 peripheral interrupt wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM4(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM4_SHIFT)) & SYSCON_STARTER_FLEXCOMM4_MASK)
+#define SYSCON_STARTER_FLEXCOMM5_MASK            (0x80000U)
+#define SYSCON_STARTER_FLEXCOMM5_SHIFT           (19U)
+/*! FLEXCOMM5 - Flexcomm5 peripheral interrupt wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM5(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM5_SHIFT)) & SYSCON_STARTER_FLEXCOMM5_MASK)
+#define SYSCON_STARTER_FLEXCOMM6_MASK            (0x100000U)
+#define SYSCON_STARTER_FLEXCOMM6_SHIFT           (20U)
+/*! FLEXCOMM6 - Flexcomm6 peripheral interrupt wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM6(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM6_SHIFT)) & SYSCON_STARTER_FLEXCOMM6_MASK)
+#define SYSCON_STARTER_FLEXCOMM7_MASK            (0x200000U)
+#define SYSCON_STARTER_FLEXCOMM7_SHIFT           (21U)
+/*! FLEXCOMM7 - Flexcomm7 peripheral interrupt wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM7(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM7_SHIFT)) & SYSCON_STARTER_FLEXCOMM7_MASK)
+#define SYSCON_STARTER_DMIC_MASK                 (0x2000000U)
+#define SYSCON_STARTER_DMIC_SHIFT                (25U)
+/*! DMIC - Digital microphone interrupt wake-up.
+ */
+#define SYSCON_STARTER_DMIC(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMIC_SHIFT)) & SYSCON_STARTER_DMIC_MASK)
+#define SYSCON_STARTER_HWVAD_MASK                (0x4000000U)
+#define SYSCON_STARTER_HWVAD_SHIFT               (26U)
+/*! HWVAD - Hardware voice activity detect interrupt wake-up.
+ */
+#define SYSCON_STARTER_HWVAD(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HWVAD_SHIFT)) & SYSCON_STARTER_HWVAD_MASK)
+#define SYSCON_STARTER_USB0_NEEDCLK_MASK         (0x8000000U)
+#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT        (27U)
+/*! USB0_NEEDCLK - USB activity interrupt wake-up.
+ */
+#define SYSCON_STARTER_USB0_NEEDCLK(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK)
+#define SYSCON_STARTER_USB0_MASK                 (0x10000000U)
+#define SYSCON_STARTER_USB0_SHIFT                (28U)
+/*! USB0 - USB function interrupt wake-up.
+ */
+#define SYSCON_STARTER_USB0(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK)
+#define SYSCON_STARTER_RTC_MASK                  (0x20000000U)
+#define SYSCON_STARTER_RTC_SHIFT                 (29U)
+/*! RTC - RTC interrupt alarm and wake-up timer.
+ */
+#define SYSCON_STARTER_RTC(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_SHIFT)) & SYSCON_STARTER_RTC_MASK)
+#define SYSCON_STARTER_FLEXCOMM10_MASK           (0x40000000U)
+#define SYSCON_STARTER_FLEXCOMM10_SHIFT          (30U)
+/*! FLEXCOMM10 - Flexcomm10 peripheral interrupt wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM10(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM10_SHIFT)) & SYSCON_STARTER_FLEXCOMM10_MASK)
+/*! @} */
+
+/* The count of SYSCON_STARTER */
+#define SYSCON_STARTER_COUNT                     (2U)
+
+/*! @name STARTERSET - Set bits in STARTER */
+/*! @{ */
+#define SYSCON_STARTERSET_START_SET_MASK         (0xFFFFFFFFU)
+#define SYSCON_STARTERSET_START_SET_SHIFT        (0U)
+/*! START_SET - Writing ones to this register sets the corresponding bit or bits in the STARTER0 register, if they are implemented.
+ */
+#define SYSCON_STARTERSET_START_SET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK)
+/*! @} */
+
+/* The count of SYSCON_STARTERSET */
+#define SYSCON_STARTERSET_COUNT                  (2U)
+
+/*! @name STARTERCLR - Clear bits in STARTER0 */
+/*! @{ */
+#define SYSCON_STARTERCLR_START_CLR_MASK         (0xFFFFFFFFU)
+#define SYSCON_STARTERCLR_START_CLR_SHIFT        (0U)
+/*! START_CLR - Writing ones to this register clears the corresponding bit or bits in the STARTER0 register, if they are implemented.
+ */
+#define SYSCON_STARTERCLR_START_CLR(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK)
+/*! @} */
+
+/* The count of SYSCON_STARTERCLR */
+#define SYSCON_STARTERCLR_COUNT                  (2U)
+
+/*! @name HWWAKE - Configures special cases of hardware wake-up */
+/*! @{ */
+#define SYSCON_HWWAKE_FORCEWAKE_MASK             (0x1U)
+#define SYSCON_HWWAKE_FORCEWAKE_SHIFT            (0U)
+/*! FORCEWAKE - Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1,
+ *    clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and
+ *    Power-down modes. This is intended to allow a coprocessor to continue operating while the main
+ *    CPU(s) are shut down.
+ */
+#define SYSCON_HWWAKE_FORCEWAKE(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK)
+#define SYSCON_HWWAKE_FCWAKE_MASK                (0x2U)
+#define SYSCON_HWWAKE_FCWAKE_SHIFT               (1U)
+/*! FCWAKE - Wake for Flexcomms. When 1, any Flexcomm FIFO reaching the level specified by its own
+ *    TXLVL will cause peripheral clocking to wake up temporarily while the related status is
+ *    asserted.
+ */
+#define SYSCON_HWWAKE_FCWAKE(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK)
+#define SYSCON_HWWAKE_WAKEDMIC_MASK              (0x4U)
+#define SYSCON_HWWAKE_WAKEDMIC_SHIFT             (2U)
+/*! WAKEDMIC - Wake for Digital Microphone. When 1, the digital microphone input FIFO reaching the
+ *    level specified by TRIGLVL of either channel will cause peripheral clocking to wake up
+ *    temporarily while the related status is asserted.
+ */
+#define SYSCON_HWWAKE_WAKEDMIC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK)
+#define SYSCON_HWWAKE_WAKEDMA_MASK               (0x8U)
+#define SYSCON_HWWAKE_WAKEDMA_SHIFT              (3U)
+/*! WAKEDMA - Wake for DMA. When 1, DMA being busy will cause peripheral clocking to remain running
+ *    until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to
+ *    prevent peripheral clocking from being shut down as soon as the cause of wake-up is cleared, but
+ *    before DMA has completed its related activity.
+ */
+#define SYSCON_HWWAKE_WAKEDMA(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK)
+/*! @} */
+
+/*! @name AUTOCGOR - Auto Clock-Gate Override Register */
+/*! @{ */
+#define SYSCON_AUTOCGOR_RAM0X_MASK               (0x2U)
+#define SYSCON_AUTOCGOR_RAM0X_SHIFT              (1U)
+/*! RAM0X - When 1, automatic clock gating for RAMX and RAM0 are turned off.
+ */
+#define SYSCON_AUTOCGOR_RAM0X(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK)
+#define SYSCON_AUTOCGOR_RAM1_MASK                (0x4U)
+#define SYSCON_AUTOCGOR_RAM1_SHIFT               (2U)
+/*! RAM1 - When 1, automatic clock gating for RAM1 are turned off.
+ */
+#define SYSCON_AUTOCGOR_RAM1(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK)
+#define SYSCON_AUTOCGOR_RAM2_MASK                (0x8U)
+#define SYSCON_AUTOCGOR_RAM2_SHIFT               (3U)
+/*! RAM2 - When 1, automatic clock gating for RAM1 are turned off.
+ */
+#define SYSCON_AUTOCGOR_RAM2(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK)
+#define SYSCON_AUTOCGOR_RAM3_MASK                (0x10U)
+#define SYSCON_AUTOCGOR_RAM3_SHIFT               (4U)
+/*! RAM3 - When 1, automatic clock gating for RAM1 are turned off.
+ */
+#define SYSCON_AUTOCGOR_RAM3(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM3_SHIFT)) & SYSCON_AUTOCGOR_RAM3_MASK)
+/*! @} */
+
+/*! @name JTAGIDCODE - JTAG ID code register */
+/*! @{ */
+#define SYSCON_JTAGIDCODE_JTAGID_MASK            (0xFFFFFFFFU)
+#define SYSCON_JTAGIDCODE_JTAGID_SHIFT           (0U)
+/*! JTAGID - JTAG ID code.
+ */
+#define SYSCON_JTAGIDCODE_JTAGID(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK)
+/*! @} */
+
+/*! @name DEVICE_ID0 - Part ID register */
+/*! @{ */
+#define SYSCON_DEVICE_ID0_PARTID_MASK            (0xFFFFFFFFU)
+#define SYSCON_DEVICE_ID0_PARTID_SHIFT           (0U)
+/*! PARTID - Part ID
+ */
+#define SYSCON_DEVICE_ID0_PARTID(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK)
+/*! @} */
+
+/*! @name DEVICE_ID1 - Boot ROM and die revision register */
+/*! @{ */
+#define SYSCON_DEVICE_ID1_REVID_MASK             (0xFFFFFFFFU)
+#define SYSCON_DEVICE_ID1_REVID_SHIFT            (0U)
+/*! REVID - Revision.
+ */
+#define SYSCON_DEVICE_ID1_REVID(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK)
+/*! @} */
+
+/*! @name BODCTRL - Brown-Out Detect control */
+/*! @{ */
+#define SYSCON_BODCTRL_BODRSTLEV_MASK            (0x3U)
+#define SYSCON_BODCTRL_BODRSTLEV_SHIFT           (0U)
+/*! BODRSTLEV - BOD reset level
+ *  0b00..Level 0: 1.5 V
+ *  0b01..Level 1: 1.85 V
+ *  0b10..Level 2: 2.0 V
+ *  0b11..Level 3: 2.3 V
+ */
+#define SYSCON_BODCTRL_BODRSTLEV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK)
+#define SYSCON_BODCTRL_BODRSTENA_MASK            (0x4U)
+#define SYSCON_BODCTRL_BODRSTENA_SHIFT           (2U)
+/*! BODRSTENA - BOD reset enable
+ *  0b0..Disable reset function.
+ *  0b1..Enable reset function.
+ */
+#define SYSCON_BODCTRL_BODRSTENA(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK)
+#define SYSCON_BODCTRL_BODINTLEV_MASK            (0x18U)
+#define SYSCON_BODCTRL_BODINTLEV_SHIFT           (3U)
+/*! BODINTLEV - BOD interrupt level
+ *  0b00..Level 0: 2.05 V
+ *  0b01..Level 1: 2.45 V
+ *  0b10..Level 2: 2.75 V
+ *  0b11..Level 3: 3.05 V
+ */
+#define SYSCON_BODCTRL_BODINTLEV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK)
+#define SYSCON_BODCTRL_BODINTENA_MASK            (0x20U)
+#define SYSCON_BODCTRL_BODINTENA_SHIFT           (5U)
+/*! BODINTENA - BOD interrupt enable
+ *  0b0..Disable interrupt function.
+ *  0b1..Enable interrupt function.
+ */
+#define SYSCON_BODCTRL_BODINTENA(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK)
+#define SYSCON_BODCTRL_BODRSTSTAT_MASK           (0x40U)
+#define SYSCON_BODCTRL_BODRSTSTAT_SHIFT          (6U)
+/*! BODRSTSTAT - BOD reset status. When 1, a BOD reset has occurred. Cleared by writing 1 to this bit.
+ */
+#define SYSCON_BODCTRL_BODRSTSTAT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK)
+#define SYSCON_BODCTRL_BODINTSTAT_MASK           (0x80U)
+#define SYSCON_BODCTRL_BODINTSTAT_SHIFT          (7U)
+/*! BODINTSTAT - BOD interrupt status. When 1, a BOD interrupt has occurred. Cleared by writing 1 to this bit.
+ */
+#define SYSCON_BODCTRL_BODINTSTAT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SYSCON_Register_Masks */
+
+
+/* SYSCON - Peripheral instance base addresses */
+/** Peripheral SYSCON base address */
+#define SYSCON_BASE                              (0x40000000u)
+/** Peripheral SYSCON base pointer */
+#define SYSCON                                   ((SYSCON_Type *)SYSCON_BASE)
+/** Array initializer of SYSCON peripheral base addresses */
+#define SYSCON_BASE_ADDRS                        { SYSCON_BASE }
+/** Array initializer of SYSCON peripheral base pointers */
+#define SYSCON_BASE_PTRS                         { SYSCON }
+
+/*!
+ * @}
+ */ /* end of group SYSCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer
+ * @{
+ */
+
+/** USART - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CFG;                               /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */
+  __IO uint32_t CTL;                               /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */
+  __IO uint32_t STAT;                              /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */
+  __IO uint32_t INTENSET;                          /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */
+  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t BRG;                               /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */
+  __IO uint32_t OSR;                               /**< Oversample selection register for asynchronous communication., offset: 0x28 */
+  __IO uint32_t ADDR;                              /**< Address register for automatic address matching., offset: 0x2C */
+       uint8_t RESERVED_1[3536];
+  __IO uint32_t FIFOCFG;                           /**< FIFO configuration and enable register., offset: 0xE00 */
+  __IO uint32_t FIFOSTAT;                          /**< FIFO status register., offset: 0xE04 */
+  __IO uint32_t FIFOTRIG;                          /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t FIFOINTENSET;                      /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+  __IO uint32_t FIFOINTENCLR;                      /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+  __I  uint32_t FIFOINTSTAT;                       /**< FIFO interrupt status register., offset: 0xE18 */
+       uint8_t RESERVED_3[4];
+  __O  uint32_t FIFOWR;                            /**< FIFO write data., offset: 0xE20 */
+       uint8_t RESERVED_4[12];
+  __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */
+       uint8_t RESERVED_5[12];
+  __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+       uint8_t RESERVED_6[440];
+  __I  uint32_t ID;                                /**< Peripheral identification register., offset: 0xFFC */
+} USART_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USART_Register_Masks USART Register Masks
+ * @{
+ */
+
+/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */
+/*! @{ */
+#define USART_CFG_ENABLE_MASK                    (0x1U)
+#define USART_CFG_ENABLE_SHIFT                   (0U)
+/*! ENABLE - USART Enable.
+ *  0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0,
+ *       all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control
+ *       bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the
+ *       transmitter has been reset and is therefore available.
+ *  0b1..Enabled. The USART is enabled for operation.
+ */
+#define USART_CFG_ENABLE(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)
+#define USART_CFG_DATALEN_MASK                   (0xCU)
+#define USART_CFG_DATALEN_SHIFT                  (2U)
+/*! DATALEN - Selects the data size for the USART.
+ *  0b00..7 bit Data length.
+ *  0b01..8 bit Data length.
+ *  0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.
+ *  0b11..Reserved.
+ */
+#define USART_CFG_DATALEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)
+#define USART_CFG_PARITYSEL_MASK                 (0x30U)
+#define USART_CFG_PARITYSEL_SHIFT                (4U)
+/*! PARITYSEL - Selects what type of parity is used by the USART.
+ *  0b00..No parity.
+ *  0b01..Reserved.
+ *  0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even,
+ *        and the number of 1s in a received character is expected to be even.
+ *  0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd,
+ *        and the number of 1s in a received character is expected to be odd.
+ */
+#define USART_CFG_PARITYSEL(x)                   (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)
+#define USART_CFG_STOPLEN_MASK                   (0x40U)
+#define USART_CFG_STOPLEN_SHIFT                  (6U)
+/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
+ *  0b0..1 stop bit.
+ *  0b1..2 stop bits. This setting should only be used for asynchronous communication.
+ */
+#define USART_CFG_STOPLEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)
+#define USART_CFG_MODE32K_MASK                   (0x80U)
+#define USART_CFG_MODE32K_SHIFT                  (7U)
+/*! MODE32K - Selects standard or 32 kHz clocking mode.
+ *  0b0..Disabled. USART uses standard clocking.
+ *  0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme.
+ */
+#define USART_CFG_MODE32K(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)
+#define USART_CFG_LINMODE_MASK                   (0x100U)
+#define USART_CFG_LINMODE_SHIFT                  (8U)
+/*! LINMODE - LIN break mode enable.
+ *  0b0..Disabled. Break detect and generate is configured for normal operation.
+ *  0b1..Enabled. Break detect and generate is configured for LIN bus operation.
+ */
+#define USART_CFG_LINMODE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)
+#define USART_CFG_CTSEN_MASK                     (0x200U)
+#define USART_CFG_CTSEN_SHIFT                    (9U)
+/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input
+ *    pin, or from the USART's own RTS if loopback mode is enabled.
+ *  0b0..No flow control. The transmitter does not receive any automatic flow control signal.
+ *  0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
+ */
+#define USART_CFG_CTSEN(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)
+#define USART_CFG_SYNCEN_MASK                    (0x800U)
+#define USART_CFG_SYNCEN_SHIFT                   (11U)
+/*! SYNCEN - Selects synchronous or asynchronous operation.
+ *  0b0..Asynchronous mode.
+ *  0b1..Synchronous mode.
+ */
+#define USART_CFG_SYNCEN(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)
+#define USART_CFG_CLKPOL_MASK                    (0x1000U)
+#define USART_CFG_CLKPOL_SHIFT                   (12U)
+/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode.
+ *  0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK.
+ *  0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK.
+ */
+#define USART_CFG_CLKPOL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)
+#define USART_CFG_SYNCMST_MASK                   (0x4000U)
+#define USART_CFG_SYNCMST_SHIFT                  (14U)
+/*! SYNCMST - Synchronous mode Master select.
+ *  0b0..Slave. When synchronous mode is enabled, the USART is a slave.
+ *  0b1..Master. When synchronous mode is enabled, the USART is a master.
+ */
+#define USART_CFG_SYNCMST(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)
+#define USART_CFG_LOOP_MASK                      (0x8000U)
+#define USART_CFG_LOOP_SHIFT                     (15U)
+/*! LOOP - Selects data loopback mode.
+ *  0b0..Normal operation.
+ *  0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial
+ *       data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD
+ *       and Un_RTS activity will also appear on external pins if these functions are configured to appear on device
+ *       pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
+ */
+#define USART_CFG_LOOP(x)                        (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)
+#define USART_CFG_OETA_MASK                      (0x40000U)
+#define USART_CFG_OETA_SHIFT                     (18U)
+/*! OETA - Output Enable Turnaround time enable for RS-485 operation.
+ *  0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
+ *  0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the
+ *       end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins
+ *       before it is deasserted.
+ */
+#define USART_CFG_OETA(x)                        (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)
+#define USART_CFG_AUTOADDR_MASK                  (0x80000U)
+#define USART_CFG_AUTOADDR_SHIFT                 (19U)
+/*! AUTOADDR - Automatic Address matching enable.
+ *  0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the
+ *       possibility of versatile addressing (e.g. respond to more than one address).
+ *  0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in
+ *       the ADDR register as the address to match.
+ */
+#define USART_CFG_AUTOADDR(x)                    (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)
+#define USART_CFG_OESEL_MASK                     (0x100000U)
+#define USART_CFG_OESEL_SHIFT                    (20U)
+/*! OESEL - Output Enable Select.
+ *  0b0..Standard. The RTS signal is used as the standard flow control function.
+ *  0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver.
+ */
+#define USART_CFG_OESEL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)
+#define USART_CFG_OEPOL_MASK                     (0x200000U)
+#define USART_CFG_OEPOL_SHIFT                    (21U)
+/*! OEPOL - Output Enable Polarity.
+ *  0b0..Low. If selected by OESEL, the output enable is active low.
+ *  0b1..High. If selected by OESEL, the output enable is active high.
+ */
+#define USART_CFG_OEPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)
+#define USART_CFG_RXPOL_MASK                     (0x400000U)
+#define USART_CFG_RXPOL_SHIFT                    (22U)
+/*! RXPOL - Receive data polarity.
+ *  0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start
+ *       bit is 0, data is not inverted, and the stop bit is 1.
+ *  0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is
+ *       0, start bit is 1, data is inverted, and the stop bit is 0.
+ */
+#define USART_CFG_RXPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)
+#define USART_CFG_TXPOL_MASK                     (0x800000U)
+#define USART_CFG_TXPOL_SHIFT                    (23U)
+/*! TXPOL - Transmit data polarity.
+ *  0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is
+ *       0, data is not inverted, and the stop bit is 1.
+ *  0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value
+ *       is 0, start bit is 1, data is inverted, and the stop bit is 0.
+ */
+#define USART_CFG_TXPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)
+/*! @} */
+
+/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */
+/*! @{ */
+#define USART_CTL_TXBRKEN_MASK                   (0x2U)
+#define USART_CTL_TXBRKEN_SHIFT                  (1U)
+/*! TXBRKEN - Break Enable.
+ *  0b0..Normal operation.
+ *  0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit
+ *       is cleared. A break may be sent without danger of corrupting any currently transmitting character if the
+ *       transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled
+ *       (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
+ */
+#define USART_CTL_TXBRKEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)
+#define USART_CTL_ADDRDET_MASK                   (0x4U)
+#define USART_CTL_ADDRDET_SHIFT                  (2U)
+/*! ADDRDET - Enable address detect mode.
+ *  0b0..Disabled. The USART presents all incoming data.
+ *  0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data
+ *       (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally,
+ *       generating a received data interrupt. Software can then check the data to see if this is an address that
+ *       should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled
+ *       normally.
+ */
+#define USART_CTL_ADDRDET(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)
+#define USART_CTL_TXDIS_MASK                     (0x40U)
+#define USART_CTL_TXDIS_SHIFT                    (6U)
+/*! TXDIS - Transmit Disable.
+ *  0b0..Not disabled. USART transmitter is not disabled.
+ *  0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This
+ *       feature can be used to facilitate software flow control.
+ */
+#define USART_CTL_TXDIS(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)
+#define USART_CTL_CC_MASK                        (0x100U)
+#define USART_CTL_CC_SHIFT                       (8U)
+/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
+ *  0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to
+ *       complete a character that is being received.
+ *  0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on
+ *       Un_RxD independently from transmission on Un_TXD).
+ */
+#define USART_CTL_CC(x)                          (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)
+#define USART_CTL_CLRCCONRX_MASK                 (0x200U)
+#define USART_CTL_CLRCCONRX_SHIFT                (9U)
+/*! CLRCCONRX - Clear Continuous Clock.
+ *  0b0..No effect. No effect on the CC bit.
+ *  0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.
+ */
+#define USART_CTL_CLRCCONRX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)
+#define USART_CTL_AUTOBAUD_MASK                  (0x10000U)
+#define USART_CTL_AUTOBAUD_SHIFT                 (16U)
+/*! AUTOBAUD - Autobaud enable.
+ *  0b0..Disabled. USART is in normal operating mode.
+ *  0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The
+ *       first start bit of RX is measured and used the update the BRG register to match the received data rate.
+ *       AUTOBAUD is cleared once this process is complete, or if there is an AERR.
+ */
+#define USART_CTL_AUTOBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)
+/*! @} */
+
+/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */
+/*! @{ */
+#define USART_STAT_RXIDLE_MASK                   (0x2U)
+#define USART_STAT_RXIDLE_SHIFT                  (1U)
+/*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of
+ *    receiving data. When 1, indicates that the receiver is not currently in the process of receiving
+ *    data.
+ */
+#define USART_STAT_RXIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)
+#define USART_STAT_TXIDLE_MASK                   (0x8U)
+#define USART_STAT_TXIDLE_SHIFT                  (3U)
+/*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of
+ *    sending data.When 1, indicate that the transmitter is not currently in the process of sending
+ *    data.
+ */
+#define USART_STAT_TXIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)
+#define USART_STAT_CTS_MASK                      (0x10U)
+#define USART_STAT_CTS_SHIFT                     (4U)
+/*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the
+ *    CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode
+ *    is enabled.
+ */
+#define USART_STAT_CTS(x)                        (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)
+#define USART_STAT_DELTACTS_MASK                 (0x20U)
+#define USART_STAT_DELTACTS_SHIFT                (5U)
+/*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
+ */
+#define USART_STAT_DELTACTS(x)                   (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)
+#define USART_STAT_TXDISSTAT_MASK                (0x40U)
+#define USART_STAT_TXDISSTAT_SHIFT               (6U)
+/*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART
+ *    transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1).
+ */
+#define USART_STAT_TXDISSTAT(x)                  (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)
+#define USART_STAT_RXBRK_MASK                    (0x400U)
+#define USART_STAT_RXBRK_SHIFT                   (10U)
+/*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection
+ *    logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also
+ *    be set when this condition occurs because the stop bit(s) for the character would be missing.
+ *    RXBRK is cleared when the Un_RXD pin goes high.
+ */
+#define USART_STAT_RXBRK(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)
+#define USART_STAT_DELTARXBRK_MASK               (0x800U)
+#define USART_STAT_DELTARXBRK_SHIFT              (11U)
+/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software.
+ */
+#define USART_STAT_DELTARXBRK(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)
+#define USART_STAT_START_MASK                    (0x1000U)
+#define USART_STAT_START_SHIFT                   (12U)
+/*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily
+ *    to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected.
+ *    Cleared by software.
+ */
+#define USART_STAT_START(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)
+#define USART_STAT_FRAMERRINT_MASK               (0x2000U)
+#define USART_STAT_FRAMERRINT_SHIFT              (13U)
+/*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a
+ *    missing stop bit at the expected location. This could be an indication of a baud rate or
+ *    configuration mismatch with the transmitting source.
+ */
+#define USART_STAT_FRAMERRINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)
+#define USART_STAT_PARITYERRINT_MASK             (0x4000U)
+#define USART_STAT_PARITYERRINT_SHIFT            (14U)
+/*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.
+ */
+#define USART_STAT_PARITYERRINT(x)               (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)
+#define USART_STAT_RXNOISEINT_MASK               (0x8000U)
+#define USART_STAT_RXNOISEINT_SHIFT              (15U)
+/*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to
+ *    determine the value of each received data bit, except in synchronous mode. This acts as a
+ *    noise filter if one sample disagrees. This flag is set when a received data bit contains one
+ *    disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or
+ *    loss of synchronization during data reception.
+ */
+#define USART_STAT_RXNOISEINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)
+#define USART_STAT_ABERR_MASK                    (0x10000U)
+#define USART_STAT_ABERR_SHIFT                   (16U)
+/*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the
+ *    end of the start bit that is being measured, essentially an auto baud time-out.
+ */
+#define USART_STAT_ABERR(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)
+/*! @} */
+
+/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
+/*! @{ */
+#define USART_INTENSET_TXIDLEEN_MASK             (0x8U)
+#define USART_INTENSET_TXIDLEEN_SHIFT            (3U)
+/*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).
+ */
+#define USART_INTENSET_TXIDLEEN(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)
+#define USART_INTENSET_DELTACTSEN_MASK           (0x20U)
+#define USART_INTENSET_DELTACTSEN_SHIFT          (5U)
+/*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input.
+ */
+#define USART_INTENSET_DELTACTSEN(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)
+#define USART_INTENSET_TXDISEN_MASK              (0x40U)
+#define USART_INTENSET_TXDISEN_SHIFT             (6U)
+/*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by
+ *    the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
+ */
+#define USART_INTENSET_TXDISEN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)
+#define USART_INTENSET_DELTARXBRKEN_MASK         (0x800U)
+#define USART_INTENSET_DELTARXBRKEN_SHIFT        (11U)
+/*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection
+ *    of a received break condition (break condition asserted or deasserted).
+ */
+#define USART_INTENSET_DELTARXBRKEN(x)           (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)
+#define USART_INTENSET_STARTEN_MASK              (0x1000U)
+#define USART_INTENSET_STARTEN_SHIFT             (12U)
+/*! STARTEN - When 1, enables an interrupt when a received start bit has been detected.
+ */
+#define USART_INTENSET_STARTEN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)
+#define USART_INTENSET_FRAMERREN_MASK            (0x2000U)
+#define USART_INTENSET_FRAMERREN_SHIFT           (13U)
+/*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected.
+ */
+#define USART_INTENSET_FRAMERREN(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)
+#define USART_INTENSET_PARITYERREN_MASK          (0x4000U)
+#define USART_INTENSET_PARITYERREN_SHIFT         (14U)
+/*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected.
+ */
+#define USART_INTENSET_PARITYERREN(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)
+#define USART_INTENSET_RXNOISEEN_MASK            (0x8000U)
+#define USART_INTENSET_RXNOISEEN_SHIFT           (15U)
+/*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354.
+ */
+#define USART_INTENSET_RXNOISEEN(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)
+#define USART_INTENSET_ABERREN_MASK              (0x10000U)
+#define USART_INTENSET_ABERREN_SHIFT             (16U)
+/*! ABERREN - When 1, enables an interrupt when an auto baud error occurs.
+ */
+#define USART_INTENSET_ABERREN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)
+/*! @} */
+
+/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */
+/*! @{ */
+#define USART_INTENCLR_TXIDLECLR_MASK            (0x8U)
+#define USART_INTENCLR_TXIDLECLR_SHIFT           (3U)
+/*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define USART_INTENCLR_TXIDLECLR(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)
+#define USART_INTENCLR_DELTACTSCLR_MASK          (0x20U)
+#define USART_INTENCLR_DELTACTSCLR_SHIFT         (5U)
+/*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define USART_INTENCLR_DELTACTSCLR(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)
+#define USART_INTENCLR_TXDISCLR_MASK             (0x40U)
+#define USART_INTENCLR_TXDISCLR_SHIFT            (6U)
+/*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define USART_INTENCLR_TXDISCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)
+#define USART_INTENCLR_DELTARXBRKCLR_MASK        (0x800U)
+#define USART_INTENCLR_DELTARXBRKCLR_SHIFT       (11U)
+/*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define USART_INTENCLR_DELTARXBRKCLR(x)          (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)
+#define USART_INTENCLR_STARTCLR_MASK             (0x1000U)
+#define USART_INTENCLR_STARTCLR_SHIFT            (12U)
+/*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define USART_INTENCLR_STARTCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)
+#define USART_INTENCLR_FRAMERRCLR_MASK           (0x2000U)
+#define USART_INTENCLR_FRAMERRCLR_SHIFT          (13U)
+/*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define USART_INTENCLR_FRAMERRCLR(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)
+#define USART_INTENCLR_PARITYERRCLR_MASK         (0x4000U)
+#define USART_INTENCLR_PARITYERRCLR_SHIFT        (14U)
+/*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define USART_INTENCLR_PARITYERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)
+#define USART_INTENCLR_RXNOISECLR_MASK           (0x8000U)
+#define USART_INTENCLR_RXNOISECLR_SHIFT          (15U)
+/*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define USART_INTENCLR_RXNOISECLR(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)
+#define USART_INTENCLR_ABERRCLR_MASK             (0x10000U)
+#define USART_INTENCLR_ABERRCLR_SHIFT            (16U)
+/*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define USART_INTENCLR_ABERRCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)
+/*! @} */
+
+/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */
+/*! @{ */
+#define USART_BRG_BRGVAL_MASK                    (0xFFFFU)
+#define USART_BRG_BRGVAL_SHIFT                   (0U)
+/*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on
+ *    the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is
+ *    divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART
+ *    function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function.
+ */
+#define USART_BRG_BRGVAL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */
+/*! @{ */
+#define USART_INTSTAT_TXIDLE_MASK                (0x8U)
+#define USART_INTSTAT_TXIDLE_SHIFT               (3U)
+/*! TXIDLE - Transmitter Idle status.
+ */
+#define USART_INTSTAT_TXIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)
+#define USART_INTSTAT_DELTACTS_MASK              (0x20U)
+#define USART_INTSTAT_DELTACTS_SHIFT             (5U)
+/*! DELTACTS - This bit is set when a change in the state of the CTS input is detected.
+ */
+#define USART_INTSTAT_DELTACTS(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)
+#define USART_INTSTAT_TXDISINT_MASK              (0x40U)
+#define USART_INTSTAT_TXDISINT_SHIFT             (6U)
+/*! TXDISINT - Transmitter Disabled Interrupt flag.
+ */
+#define USART_INTSTAT_TXDISINT(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)
+#define USART_INTSTAT_DELTARXBRK_MASK            (0x800U)
+#define USART_INTSTAT_DELTARXBRK_SHIFT           (11U)
+/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs.
+ */
+#define USART_INTSTAT_DELTARXBRK(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)
+#define USART_INTSTAT_START_MASK                 (0x1000U)
+#define USART_INTSTAT_START_SHIFT                (12U)
+/*! START - This bit is set when a start is detected on the receiver input.
+ */
+#define USART_INTSTAT_START(x)                   (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)
+#define USART_INTSTAT_FRAMERRINT_MASK            (0x2000U)
+#define USART_INTSTAT_FRAMERRINT_SHIFT           (13U)
+/*! FRAMERRINT - Framing Error interrupt flag.
+ */
+#define USART_INTSTAT_FRAMERRINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)
+#define USART_INTSTAT_PARITYERRINT_MASK          (0x4000U)
+#define USART_INTSTAT_PARITYERRINT_SHIFT         (14U)
+/*! PARITYERRINT - Parity Error interrupt flag.
+ */
+#define USART_INTSTAT_PARITYERRINT(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)
+#define USART_INTSTAT_RXNOISEINT_MASK            (0x8000U)
+#define USART_INTSTAT_RXNOISEINT_SHIFT           (15U)
+/*! RXNOISEINT - Received Noise interrupt flag.
+ */
+#define USART_INTSTAT_RXNOISEINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)
+#define USART_INTSTAT_ABERRINT_MASK              (0x10000U)
+#define USART_INTSTAT_ABERRINT_SHIFT             (16U)
+/*! ABERRINT - Auto baud Error Interrupt flag.
+ */
+#define USART_INTSTAT_ABERRINT(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)
+/*! @} */
+
+/*! @name OSR - Oversample selection register for asynchronous communication. */
+/*! @{ */
+#define USART_OSR_OSRVAL_MASK                    (0xFU)
+#define USART_OSR_OSRVAL_SHIFT                   (0U)
+/*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to
+ *    transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive
+ *    each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit.
+ */
+#define USART_OSR_OSRVAL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)
+/*! @} */
+
+/*! @name ADDR - Address register for automatic address matching. */
+/*! @{ */
+#define USART_ADDR_ADDRESS_MASK                  (0xFFU)
+#define USART_ADDR_ADDRESS_SHIFT                 (0U)
+/*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is
+ *    enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).
+ */
+#define USART_ADDR_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)
+/*! @} */
+
+/*! @name FIFOCFG - FIFO configuration and enable register. */
+/*! @{ */
+#define USART_FIFOCFG_ENABLETX_MASK              (0x1U)
+#define USART_FIFOCFG_ENABLETX_SHIFT             (0U)
+/*! ENABLETX - Enable the transmit FIFO.
+ *  0b0..The transmit FIFO is not enabled.
+ *  0b1..The transmit FIFO is enabled.
+ */
+#define USART_FIFOCFG_ENABLETX(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)
+#define USART_FIFOCFG_ENABLERX_MASK              (0x2U)
+#define USART_FIFOCFG_ENABLERX_SHIFT             (1U)
+/*! ENABLERX - Enable the receive FIFO.
+ *  0b0..The receive FIFO is not enabled.
+ *  0b1..The receive FIFO is enabled.
+ */
+#define USART_FIFOCFG_ENABLERX(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)
+#define USART_FIFOCFG_SIZE_MASK                  (0x30U)
+#define USART_FIFOCFG_SIZE_SHIFT                 (4U)
+/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16
+ *    entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
+ */
+#define USART_FIFOCFG_SIZE(x)                    (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)
+#define USART_FIFOCFG_DMATX_MASK                 (0x1000U)
+#define USART_FIFOCFG_DMATX_SHIFT                (12U)
+/*! DMATX - DMA configuration for transmit.
+ *  0b0..DMA is not used for the transmit function.
+ *  0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define USART_FIFOCFG_DMATX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)
+#define USART_FIFOCFG_DMARX_MASK                 (0x2000U)
+#define USART_FIFOCFG_DMARX_SHIFT                (13U)
+/*! DMARX - DMA configuration for receive.
+ *  0b0..DMA is not used for the receive function.
+ *  0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define USART_FIFOCFG_DMARX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)
+#define USART_FIFOCFG_WAKETX_MASK                (0x4000U)
+#define USART_FIFOCFG_WAKETX_SHIFT               (14U)
+/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power
+ *    modes (up to power-down, as long as the peripheral function works in that power mode) without
+ *    enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
+ *    CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
+ *    Wake-up control register.
+ *  0b0..Only enabled interrupts will wake up the device form reduced power modes.
+ *  0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
+ *       FIFOTRIG, even when the TXLVL interrupt is not enabled.
+ */
+#define USART_FIFOCFG_WAKETX(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)
+#define USART_FIFOCFG_WAKERX_MASK                (0x8000U)
+#define USART_FIFOCFG_WAKERX_SHIFT               (15U)
+/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power
+ *    modes (up to power-down, as long as the peripheral function works in that power mode) without
+ *    enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
+ *    CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
+ *    Wake-up control register.
+ *  0b0..Only enabled interrupts will wake up the device form reduced power modes.
+ *  0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in
+ *       FIFOTRIG, even when the RXLVL interrupt is not enabled.
+ */
+#define USART_FIFOCFG_WAKERX(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)
+#define USART_FIFOCFG_EMPTYTX_MASK               (0x10000U)
+#define USART_FIFOCFG_EMPTYTX_SHIFT              (16U)
+/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
+ */
+#define USART_FIFOCFG_EMPTYTX(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)
+#define USART_FIFOCFG_EMPTYRX_MASK               (0x20000U)
+#define USART_FIFOCFG_EMPTYRX_SHIFT              (17U)
+/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
+ */
+#define USART_FIFOCFG_EMPTYRX(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)
+/*! @} */
+
+/*! @name FIFOSTAT - FIFO status register. */
+/*! @{ */
+#define USART_FIFOSTAT_TXERR_MASK                (0x1U)
+#define USART_FIFOSTAT_TXERR_SHIFT               (0U)
+/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow
+ *    caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is
+ *    needed. Cleared by writing a 1 to this bit.
+ */
+#define USART_FIFOSTAT_TXERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)
+#define USART_FIFOSTAT_RXERR_MASK                (0x2U)
+#define USART_FIFOSTAT_RXERR_SHIFT               (1U)
+/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA
+ *    not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.
+ */
+#define USART_FIFOSTAT_RXERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)
+#define USART_FIFOSTAT_PERINT_MASK               (0x8U)
+#define USART_FIFOSTAT_PERINT_SHIFT              (3U)
+/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted
+ *    an interrupt. The details can be found by reading the peripheral's STAT register.
+ */
+#define USART_FIFOSTAT_PERINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)
+#define USART_FIFOSTAT_TXEMPTY_MASK              (0x10U)
+#define USART_FIFOSTAT_TXEMPTY_SHIFT             (4U)
+/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.
+ */
+#define USART_FIFOSTAT_TXEMPTY(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)
+#define USART_FIFOSTAT_TXNOTFULL_MASK            (0x20U)
+#define USART_FIFOSTAT_TXNOTFULL_SHIFT           (5U)
+/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be
+ *    written. When 0, the transmit FIFO is full and another write would cause it to overflow.
+ */
+#define USART_FIFOSTAT_TXNOTFULL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)
+#define USART_FIFOSTAT_RXNOTEMPTY_MASK           (0x40U)
+#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT          (6U)
+/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.
+ */
+#define USART_FIFOSTAT_RXNOTEMPTY(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)
+#define USART_FIFOSTAT_RXFULL_MASK               (0x80U)
+#define USART_FIFOSTAT_RXFULL_SHIFT              (7U)
+/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to
+ *    prevent the peripheral from causing an overflow.
+ */
+#define USART_FIFOSTAT_RXFULL(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)
+#define USART_FIFOSTAT_TXLVL_MASK                (0x1F00U)
+#define USART_FIFOSTAT_TXLVL_SHIFT               (8U)
+/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY
+ *    and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at
+ *    the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be
+ *    0.
+ */
+#define USART_FIFOSTAT_TXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)
+#define USART_FIFOSTAT_RXLVL_MASK                (0x1F0000U)
+#define USART_FIFOSTAT_RXLVL_SHIFT               (16U)
+/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and
+ *    RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the
+ *    point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be
+ *    1.
+ */
+#define USART_FIFOSTAT_RXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
+/*! @{ */
+#define USART_FIFOTRIG_TXLVLENA_MASK             (0x1U)
+#define USART_FIFOTRIG_TXLVLENA_SHIFT            (0U)
+/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled
+ *    in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
+ *  0b0..Transmit FIFO level does not generate a FIFO level trigger.
+ *  0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
+ */
+#define USART_FIFOTRIG_TXLVLENA(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)
+#define USART_FIFOTRIG_RXLVLENA_MASK             (0x2U)
+#define USART_FIFOTRIG_RXLVLENA_SHIFT            (1U)
+/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled
+ *    in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.
+ *  0b0..Receive FIFO level does not generate a FIFO level trigger.
+ *  0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
+ */
+#define USART_FIFOTRIG_RXLVLENA(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)
+#define USART_FIFOTRIG_TXLVL_MASK                (0xF00U)
+#define USART_FIFOTRIG_TXLVL_SHIFT               (8U)
+/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled
+ *    to do so, the FIFO level can wake up the device just enough to perform DMA, then return to
+ *    the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO
+ *    becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX
+ *    FIFO level decreases to 15 entries (is no longer full).
+ */
+#define USART_FIFOTRIG_TXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)
+#define USART_FIFOTRIG_RXLVL_MASK                (0xF0000U)
+#define USART_FIFOTRIG_RXLVL_SHIFT               (16U)
+/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data
+ *    is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level
+ *    can wake up the device just enough to perform DMA, then return to the reduced power mode. See
+ *    Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no
+ *    longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX
+ *    FIFO has received 16 entries (has become full).
+ */
+#define USART_FIFOTRIG_RXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
+/*! @{ */
+#define USART_FIFOINTENSET_TXERR_MASK            (0x1U)
+#define USART_FIFOINTENSET_TXERR_SHIFT           (0U)
+/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
+ *  0b0..No interrupt will be generated for a transmit error.
+ *  0b1..An interrupt will be generated when a transmit error occurs.
+ */
+#define USART_FIFOINTENSET_TXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)
+#define USART_FIFOINTENSET_RXERR_MASK            (0x2U)
+#define USART_FIFOINTENSET_RXERR_SHIFT           (1U)
+/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.
+ *  0b0..No interrupt will be generated for a receive error.
+ *  0b1..An interrupt will be generated when a receive error occurs.
+ */
+#define USART_FIFOINTENSET_RXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)
+#define USART_FIFOINTENSET_TXLVL_MASK            (0x4U)
+#define USART_FIFOINTENSET_TXLVL_SHIFT           (2U)
+/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level
+ *    specified by the TXLVL field in the FIFOTRIG register.
+ *  0b0..No interrupt will be generated based on the TX FIFO level.
+ *  0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases
+ *       to the level specified by TXLVL in the FIFOTRIG register.
+ */
+#define USART_FIFOINTENSET_TXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)
+#define USART_FIFOINTENSET_RXLVL_MASK            (0x8U)
+#define USART_FIFOINTENSET_RXLVL_SHIFT           (3U)
+/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level
+ *    specified by the TXLVL field in the FIFOTRIG register.
+ *  0b0..No interrupt will be generated based on the RX FIFO level.
+ *  0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level
+ *       increases to the level specified by RXLVL in the FIFOTRIG register.
+ */
+#define USART_FIFOINTENSET_RXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
+/*! @{ */
+#define USART_FIFOINTENCLR_TXERR_MASK            (0x1U)
+#define USART_FIFOINTENCLR_TXERR_SHIFT           (0U)
+/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define USART_FIFOINTENCLR_TXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)
+#define USART_FIFOINTENCLR_RXERR_MASK            (0x2U)
+#define USART_FIFOINTENCLR_RXERR_SHIFT           (1U)
+/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define USART_FIFOINTENCLR_RXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)
+#define USART_FIFOINTENCLR_TXLVL_MASK            (0x4U)
+#define USART_FIFOINTENCLR_TXLVL_SHIFT           (2U)
+/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define USART_FIFOINTENCLR_TXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)
+#define USART_FIFOINTENCLR_RXLVL_MASK            (0x8U)
+#define USART_FIFOINTENCLR_RXLVL_SHIFT           (3U)
+/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define USART_FIFOINTENCLR_RXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */
+/*! @{ */
+#define USART_FIFOINTSTAT_TXERR_MASK             (0x1U)
+#define USART_FIFOINTSTAT_TXERR_SHIFT            (0U)
+/*! TXERR - TX FIFO error.
+ */
+#define USART_FIFOINTSTAT_TXERR(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)
+#define USART_FIFOINTSTAT_RXERR_MASK             (0x2U)
+#define USART_FIFOINTSTAT_RXERR_SHIFT            (1U)
+/*! RXERR - RX FIFO error.
+ */
+#define USART_FIFOINTSTAT_RXERR(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)
+#define USART_FIFOINTSTAT_TXLVL_MASK             (0x4U)
+#define USART_FIFOINTSTAT_TXLVL_SHIFT            (2U)
+/*! TXLVL - Transmit FIFO level interrupt.
+ */
+#define USART_FIFOINTSTAT_TXLVL(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)
+#define USART_FIFOINTSTAT_RXLVL_MASK             (0x8U)
+#define USART_FIFOINTSTAT_RXLVL_SHIFT            (3U)
+/*! RXLVL - Receive FIFO level interrupt.
+ */
+#define USART_FIFOINTSTAT_RXLVL(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)
+#define USART_FIFOINTSTAT_PERINT_MASK            (0x10U)
+#define USART_FIFOINTSTAT_PERINT_SHIFT           (4U)
+/*! PERINT - Peripheral interrupt.
+ */
+#define USART_FIFOINTSTAT_PERINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)
+/*! @} */
+
+/*! @name FIFOWR - FIFO write data. */
+/*! @{ */
+#define USART_FIFOWR_TXDATA_MASK                 (0x1FFU)
+#define USART_FIFOWR_TXDATA_SHIFT                (0U)
+/*! TXDATA - Transmit data to the FIFO.
+ */
+#define USART_FIFOWR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORD - FIFO read data. */
+/*! @{ */
+#define USART_FIFORD_RXDATA_MASK                 (0x1FFU)
+#define USART_FIFORD_RXDATA_SHIFT                (0U)
+/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings.
+ */
+#define USART_FIFORD_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)
+#define USART_FIFORD_FRAMERR_MASK                (0x2000U)
+#define USART_FIFORD_FRAMERR_SHIFT               (13U)
+/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along
+ *    with from the FIFO, and indicates that the character was received with a missing stop bit at
+ *    the expected location. This could be an indication of a baud rate or configuration mismatch
+ *    with the transmitting source.
+ */
+#define USART_FIFORD_FRAMERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)
+#define USART_FIFORD_PARITYERR_MASK              (0x4000U)
+#define USART_FIFORD_PARITYERR_SHIFT             (14U)
+/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along
+ *    with from the FIFO. This bit will be set when a parity error is detected in a received
+ *    character.
+ */
+#define USART_FIFORD_PARITYERR(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)
+#define USART_FIFORD_RXNOISE_MASK                (0x8000U)
+#define USART_FIFORD_RXNOISE_SHIFT               (15U)
+/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354.
+ */
+#define USART_FIFORD_RXNOISE(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)
+/*! @} */
+
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
+/*! @{ */
+#define USART_FIFORDNOPOP_RXDATA_MASK            (0x1FFU)
+#define USART_FIFORDNOPOP_RXDATA_SHIFT           (0U)
+/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings.
+ */
+#define USART_FIFORDNOPOP_RXDATA(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)
+#define USART_FIFORDNOPOP_FRAMERR_MASK           (0x2000U)
+#define USART_FIFORDNOPOP_FRAMERR_SHIFT          (13U)
+/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along
+ *    with from the FIFO, and indicates that the character was received with a missing stop bit at
+ *    the expected location. This could be an indication of a baud rate or configuration mismatch
+ *    with the transmitting source.
+ */
+#define USART_FIFORDNOPOP_FRAMERR(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)
+#define USART_FIFORDNOPOP_PARITYERR_MASK         (0x4000U)
+#define USART_FIFORDNOPOP_PARITYERR_SHIFT        (14U)
+/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along
+ *    with from the FIFO. This bit will be set when a parity error is detected in a received
+ *    character.
+ */
+#define USART_FIFORDNOPOP_PARITYERR(x)           (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)
+#define USART_FIFORDNOPOP_RXNOISE_MASK           (0x8000U)
+#define USART_FIFORDNOPOP_RXNOISE_SHIFT          (15U)
+/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354.
+ */
+#define USART_FIFORDNOPOP_RXNOISE(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)
+/*! @} */
+
+/*! @name ID - Peripheral identification register. */
+/*! @{ */
+#define USART_ID_APERTURE_MASK                   (0xFFU)
+#define USART_ID_APERTURE_SHIFT                  (0U)
+/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
+ */
+#define USART_ID_APERTURE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)
+#define USART_ID_MINOR_REV_MASK                  (0xF00U)
+#define USART_ID_MINOR_REV_SHIFT                 (8U)
+/*! MINOR_REV - Minor revision of module implementation.
+ */
+#define USART_ID_MINOR_REV(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)
+#define USART_ID_MAJOR_REV_MASK                  (0xF000U)
+#define USART_ID_MAJOR_REV_SHIFT                 (12U)
+/*! MAJOR_REV - Major revision of module implementation.
+ */
+#define USART_ID_MAJOR_REV(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)
+#define USART_ID_ID_MASK                         (0xFFFF0000U)
+#define USART_ID_ID_SHIFT                        (16U)
+/*! ID - Module identifier for the selected function.
+ */
+#define USART_ID_ID(x)                           (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USART_Register_Masks */
+
+
+/* USART - Peripheral instance base addresses */
+/** Peripheral USART0 base address */
+#define USART0_BASE                              (0x40086000u)
+/** Peripheral USART0 base pointer */
+#define USART0                                   ((USART_Type *)USART0_BASE)
+/** Peripheral USART1 base address */
+#define USART1_BASE                              (0x40087000u)
+/** Peripheral USART1 base pointer */
+#define USART1                                   ((USART_Type *)USART1_BASE)
+/** Peripheral USART2 base address */
+#define USART2_BASE                              (0x40088000u)
+/** Peripheral USART2 base pointer */
+#define USART2                                   ((USART_Type *)USART2_BASE)
+/** Peripheral USART3 base address */
+#define USART3_BASE                              (0x40089000u)
+/** Peripheral USART3 base pointer */
+#define USART3                                   ((USART_Type *)USART3_BASE)
+/** Peripheral USART4 base address */
+#define USART4_BASE                              (0x4008A000u)
+/** Peripheral USART4 base pointer */
+#define USART4                                   ((USART_Type *)USART4_BASE)
+/** Peripheral USART5 base address */
+#define USART5_BASE                              (0x40096000u)
+/** Peripheral USART5 base pointer */
+#define USART5                                   ((USART_Type *)USART5_BASE)
+/** Peripheral USART6 base address */
+#define USART6_BASE                              (0x40097000u)
+/** Peripheral USART6 base pointer */
+#define USART6                                   ((USART_Type *)USART6_BASE)
+/** Peripheral USART7 base address */
+#define USART7_BASE                              (0x40098000u)
+/** Peripheral USART7 base pointer */
+#define USART7                                   ((USART_Type *)USART7_BASE)
+/** Peripheral USART8 base address */
+#define USART8_BASE                              (0x40099000u)
+/** Peripheral USART8 base pointer */
+#define USART8                                   ((USART_Type *)USART8_BASE)
+/** Peripheral USART9 base address */
+#define USART9_BASE                              (0x4009A000u)
+/** Peripheral USART9 base pointer */
+#define USART9                                   ((USART_Type *)USART9_BASE)
+/** Array initializer of USART peripheral base addresses */
+#define USART_BASE_ADDRS                         { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE, USART8_BASE, USART9_BASE }
+/** Array initializer of USART peripheral base pointers */
+#define USART_BASE_PTRS                          { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7, USART8, USART9 }
+/** Interrupt vectors for the USART peripheral type */
+#define USART_IRQS                               { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DEVCMDSTAT;                        /**< USB Device Command/Status register, offset: 0x0 */
+  __IO uint32_t INFO;                              /**< USB Info register, offset: 0x4 */
+  __IO uint32_t EPLISTSTART;                       /**< USB EP Command/Status List start address, offset: 0x8 */
+  __IO uint32_t DATABUFSTART;                      /**< USB Data buffer start address, offset: 0xC */
+  __IO uint32_t LPM;                               /**< USB Link Power Management register, offset: 0x10 */
+  __IO uint32_t EPSKIP;                            /**< USB Endpoint skip, offset: 0x14 */
+  __IO uint32_t EPINUSE;                           /**< USB Endpoint Buffer in use, offset: 0x18 */
+  __IO uint32_t EPBUFCFG;                          /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
+  __IO uint32_t INTSTAT;                           /**< USB interrupt status register, offset: 0x20 */
+  __IO uint32_t INTEN;                             /**< USB interrupt enable register, offset: 0x24 */
+  __IO uint32_t INTSETSTAT;                        /**< USB set interrupt status register, offset: 0x28 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t EPTOGGLE;                          /**< USB Endpoint toggle register, offset: 0x34 */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/*! @name DEVCMDSTAT - USB Device Command/Status register */
+/*! @{ */
+#define USB_DEVCMDSTAT_DEV_ADDR_MASK             (0x7FU)
+#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT            (0U)
+/*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit
+ *    is set, the device will respond on packets for function address DEV_ADDR. When receiving a
+ *    SetAddress Control Request from the USB host, software must program the new address before
+ *    completing the status phase of the SetAddress Control Request.
+ */
+#define USB_DEVCMDSTAT_DEV_ADDR(x)               (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK)
+#define USB_DEVCMDSTAT_DEV_EN_MASK               (0x80U)
+#define USB_DEVCMDSTAT_DEV_EN_SHIFT              (7U)
+/*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR.
+ */
+#define USB_DEVCMDSTAT_DEV_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK)
+#define USB_DEVCMDSTAT_SETUP_MASK                (0x100U)
+#define USB_DEVCMDSTAT_SETUP_SHIFT               (8U)
+/*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this
+ *    bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW
+ *    must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the
+ *    CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW.
+ */
+#define USB_DEVCMDSTAT_SETUP(x)                  (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK)
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK        (0x200U)
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT       (9U)
+/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:
+ *  0b0..USB_NEEDCLK has normal function.
+ *  0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend.
+ */
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x)          (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
+#define USB_DEVCMDSTAT_LPM_SUP_MASK              (0x800U)
+#define USB_DEVCMDSTAT_LPM_SUP_SHIFT             (11U)
+/*! LPM_SUP - LPM Supported:
+ *  0b0..LPM not supported.
+ *  0b1..LPM supported.
+ */
+#define USB_DEVCMDSTAT_LPM_SUP(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_AO_MASK          (0x1000U)
+#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT         (12U)
+/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP
+ *  0b0..Only acknowledged packets generate an interrupt
+ *  0b1..Both acknowledged and NAKed packets generate interrupts.
+ */
+#define USB_DEVCMDSTAT_INTONNAK_AO(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_AI_MASK          (0x2000U)
+#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT         (13U)
+/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP
+ *  0b0..Only acknowledged packets generate an interrupt
+ *  0b1..Both acknowledged and NAKed packets generate interrupts.
+ */
+#define USB_DEVCMDSTAT_INTONNAK_AI(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_CO_MASK          (0x4000U)
+#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT         (14U)
+/*! INTONNAK_CO - Interrupt on NAK for control OUT EP
+ *  0b0..Only acknowledged packets generate an interrupt
+ *  0b1..Both acknowledged and NAKed packets generate interrupts.
+ */
+#define USB_DEVCMDSTAT_INTONNAK_CO(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_CI_MASK          (0x8000U)
+#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT         (15U)
+/*! INTONNAK_CI - Interrupt on NAK for control IN EP
+ *  0b0..Only acknowledged packets generate an interrupt
+ *  0b1..Both acknowledged and NAKed packets generate interrupts.
+ */
+#define USB_DEVCMDSTAT_INTONNAK_CI(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK)
+#define USB_DEVCMDSTAT_DCON_MASK                 (0x10000U)
+#define USB_DEVCMDSTAT_DCON_SHIFT                (16U)
+/*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device
+ *    must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and
+ *    the VBUSDEBOUNCED bit is one.
+ */
+#define USB_DEVCMDSTAT_DCON(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK)
+#define USB_DEVCMDSTAT_DSUS_MASK                 (0x20000U)
+#define USB_DEVCMDSTAT_DSUS_SHIFT                (17U)
+/*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set
+ *    to 1 when the device hasn't seen any activity on its upstream port for more than 3
+ *    milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and
+ *    the software writes a 0 to it, the device will generate a remote wake-up. This will only happen
+ *    when the device is connected (Connect bit = 1). When the device is not connected or not
+ *    suspended, a writing a 0 has no effect. Writing a 1 never has an effect.
+ */
+#define USB_DEVCMDSTAT_DSUS(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK)
+#define USB_DEVCMDSTAT_LPM_SUS_MASK              (0x80000U)
+#define USB_DEVCMDSTAT_LPM_SUS_SHIFT             (19U)
+/*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is
+ *    set to 1 by HW when the device has acknowledged the LPM request from the USB host and the
+ *    Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend
+ *    bit = 1) and the software writes a zero to this bit, the device will generate a remote
+ *    walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this
+ *    bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the
+ *    LPM_SUPP bit is equal to one.
+ */
+#define USB_DEVCMDSTAT_LPM_SUS(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK)
+#define USB_DEVCMDSTAT_LPM_REWP_MASK             (0x100000U)
+#define USB_DEVCMDSTAT_LPM_REWP_SHIFT            (20U)
+/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake
+ *    bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the
+ *    host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset
+ *    is received. Software can use this bit to check if the remote wake-up feature is enabled by the
+ *    host for the LPM transaction.
+ */
+#define USB_DEVCMDSTAT_LPM_REWP(x)               (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK)
+#define USB_DEVCMDSTAT_DCON_C_MASK               (0x1000000U)
+#define USB_DEVCMDSTAT_DCON_C_SHIFT              (24U)
+/*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up
+ *    resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it.
+ */
+#define USB_DEVCMDSTAT_DCON_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK)
+#define USB_DEVCMDSTAT_DSUS_C_MASK               (0x2000000U)
+#define USB_DEVCMDSTAT_DSUS_C_SHIFT              (25U)
+/*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit
+ *    toggles. The suspend bit can toggle because: - The device goes in the suspended state - The
+ *    device is disconnected - The device receives resume signaling on its upstream port. The bit is
+ *    reset by writing a one to it.
+ */
+#define USB_DEVCMDSTAT_DSUS_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK)
+#define USB_DEVCMDSTAT_DRES_C_MASK               (0x4000000U)
+#define USB_DEVCMDSTAT_DRES_C_SHIFT              (26U)
+/*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On
+ *    a bus reset the device will automatically go to the default state (unconfigured and responding
+ *    to address 0). The bit is reset by writing a one to it.
+ */
+#define USB_DEVCMDSTAT_DRES_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK)
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK        (0x10000000U)
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT       (28U)
+/*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when
+ *    Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and
+ *    the DCon bit is set, the HW will enable the pull-up resistor to signal a connect.
+ */
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x)          (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK)
+/*! @} */
+
+/*! @name INFO - USB Info register */
+/*! @{ */
+#define USB_INFO_FRAME_NR_MASK                   (0x7FFU)
+#define USB_INFO_FRAME_NR_SHIFT                  (0U)
+/*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF.
+ *    In case no SOF was received by the device at the beginning of a frame, the frame number
+ *    returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC
+ *    error, the frame number returned will be the corrupted frame number as received by the device.
+ */
+#define USB_INFO_FRAME_NR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK)
+#define USB_INFO_ERR_CODE_MASK                   (0x7800U)
+#define USB_INFO_ERR_CODE_SHIFT                  (11U)
+/*! ERR_CODE - The error code which last occurred:
+ *  0b0000..No error
+ *  0b0001..PID encoding error
+ *  0b0010..PID unknown
+ *  0b0011..Packet unexpected
+ *  0b0100..Token CRC error
+ *  0b0101..Data CRC error
+ *  0b0110..Time out
+ *  0b0111..Babble
+ *  0b1000..Truncated EOP
+ *  0b1001..Sent/Received NAK
+ *  0b1010..Sent Stall
+ *  0b1011..Overrun
+ *  0b1100..Sent empty packet
+ *  0b1101..Bitstuff error
+ *  0b1110..Sync error
+ *  0b1111..Wrong data toggle
+ */
+#define USB_INFO_ERR_CODE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK)
+#define USB_INFO_MINREV_MASK                     (0xFF0000U)
+#define USB_INFO_MINREV_SHIFT                    (16U)
+/*! MINREV - Minor Revision.
+ */
+#define USB_INFO_MINREV(x)                       (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK)
+#define USB_INFO_MAJREV_MASK                     (0xFF000000U)
+#define USB_INFO_MAJREV_SHIFT                    (24U)
+/*! MAJREV - Major Revision.
+ */
+#define USB_INFO_MAJREV(x)                       (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK)
+/*! @} */
+
+/*! @name EPLISTSTART - USB EP Command/Status List start address */
+/*! @{ */
+#define USB_EPLISTSTART_EP_LIST_MASK             (0xFFFFFF00U)
+#define USB_EPLISTSTART_EP_LIST_SHIFT            (8U)
+/*! EP_LIST - Start address of the USB EP Command/Status List.
+ */
+#define USB_EPLISTSTART_EP_LIST(x)               (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK)
+/*! @} */
+
+/*! @name DATABUFSTART - USB Data buffer start address */
+/*! @{ */
+#define USB_DATABUFSTART_DA_BUF_MASK             (0xFFC00000U)
+#define USB_DATABUFSTART_DA_BUF_SHIFT            (22U)
+/*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located.
+ */
+#define USB_DATABUFSTART_DA_BUF(x)               (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK)
+/*! @} */
+
+/*! @name LPM - USB Link Power Management register */
+/*! @{ */
+#define USB_LPM_HIRD_HW_MASK                     (0xFU)
+#define USB_LPM_HIRD_HW_SHIFT                    (0U)
+/*! HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token
+ */
+#define USB_LPM_HIRD_HW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK)
+#define USB_LPM_HIRD_SW_MASK                     (0xF0U)
+#define USB_LPM_HIRD_SW_SHIFT                    (4U)
+/*! HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB
+ *    device system to come out of LPM initiated suspend after receiving the host initiated LPM resume.
+ */
+#define USB_LPM_HIRD_SW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK)
+#define USB_LPM_DATA_PENDING_MASK                (0x100U)
+#define USB_LPM_DATA_PENDING_SHIFT               (8U)
+/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will
+ *    return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and
+ *    this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has
+ *    still data pending and LPM is supported, it must set this bit to 1.
+ */
+#define USB_LPM_DATA_PENDING(x)                  (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK)
+/*! @} */
+
+/*! @name EPSKIP - USB Endpoint skip */
+/*! @{ */
+#define USB_EPSKIP_SKIP_MASK                     (0x3FFU)
+#define USB_EPSKIP_SKIP_SHIFT                    (0U)
+/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must
+ *    deactivate the buffer assigned to this endpoint and return control back to software. When HW has
+ *    deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An
+ *    interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering,
+ *    HW will only clear the Active bit of the buffer indicated by the EPINUSE bit.
+ */
+#define USB_EPSKIP_SKIP(x)                       (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK)
+/*! @} */
+
+/*! @name EPINUSE - USB Endpoint Buffer in use */
+/*! @{ */
+#define USB_EPINUSE_BUF_MASK                     (0x3FCU)
+#define USB_EPINUSE_BUF_SHIFT                    (2U)
+/*! BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer
+ *    0. 1: HW is accessing buffer 1.
+ */
+#define USB_EPINUSE_BUF(x)                       (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK)
+/*! @} */
+
+/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
+/*! @{ */
+#define USB_EPBUFCFG_BUF_SB_MASK                 (0x3FCU)
+#define USB_EPBUFCFG_BUF_SB_SHIFT                (2U)
+/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1:
+ *    Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding
+ *    EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle
+ *    the EPINUSE bit when it clears the Active bit for the buffer.
+ */
+#define USB_EPBUFCFG_BUF_SB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK)
+/*! @} */
+
+/*! @name INTSTAT - USB interrupt status register */
+/*! @{ */
+#define USB_INTSTAT_EP0OUT_MASK                  (0x1U)
+#define USB_INTSTAT_EP0OUT_SHIFT                 (0U)
+/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set
+ *    if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is
+ *    successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a
+ *    NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a
+ *    one to it.
+ */
+#define USB_INTSTAT_EP0OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK)
+#define USB_INTSTAT_EP0IN_MASK                   (0x2U)
+#define USB_INTSTAT_EP0IN_SHIFT                  (1U)
+/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if
+ *    NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this
+ *    bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can
+ *    clear this bit by writing a one to it.
+ */
+#define USB_INTSTAT_EP0IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK)
+#define USB_INTSTAT_EP1OUT_MASK                  (0x4U)
+#define USB_INTSTAT_EP1OUT_SHIFT                 (2U)
+/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the
+ *    corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
+ *    transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
+ *    set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by
+ *    writing a one to it.
+ */
+#define USB_INTSTAT_EP1OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK)
+#define USB_INTSTAT_EP1IN_MASK                   (0x8U)
+#define USB_INTSTAT_EP1IN_SHIFT                  (3U)
+/*! EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the
+ *    corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
+ *    to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
+ *    set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing
+ *    a one to it.
+ */
+#define USB_INTSTAT_EP1IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK)
+#define USB_INTSTAT_EP2OUT_MASK                  (0x10U)
+#define USB_INTSTAT_EP2OUT_SHIFT                 (4U)
+/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the
+ *    corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
+ *    transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
+ *    set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by
+ *    writing a one to it.
+ */
+#define USB_INTSTAT_EP2OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK)
+#define USB_INTSTAT_EP2IN_MASK                   (0x20U)
+#define USB_INTSTAT_EP2IN_SHIFT                  (5U)
+/*! EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the
+ *    corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
+ *    to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
+ *    set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing
+ *    a one to it.
+ */
+#define USB_INTSTAT_EP2IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK)
+#define USB_INTSTAT_EP3OUT_MASK                  (0x40U)
+#define USB_INTSTAT_EP3OUT_SHIFT                 (6U)
+/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the
+ *    corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
+ *    transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
+ *    set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by
+ *    writing a one to it.
+ */
+#define USB_INTSTAT_EP3OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK)
+#define USB_INTSTAT_EP3IN_MASK                   (0x80U)
+#define USB_INTSTAT_EP3IN_SHIFT                  (7U)
+/*! EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the
+ *    corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
+ *    to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
+ *    set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing
+ *    a one to it.
+ */
+#define USB_INTSTAT_EP3IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK)
+#define USB_INTSTAT_EP4OUT_MASK                  (0x100U)
+#define USB_INTSTAT_EP4OUT_SHIFT                 (8U)
+/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the
+ *    corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
+ *    transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
+ *    set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by
+ *    writing a one to it.
+ */
+#define USB_INTSTAT_EP4OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK)
+#define USB_INTSTAT_EP4IN_MASK                   (0x200U)
+#define USB_INTSTAT_EP4IN_SHIFT                  (9U)
+/*! EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the
+ *    corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
+ *    to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
+ *    set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing
+ *    a one to it.
+ */
+#define USB_INTSTAT_EP4IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK)
+#define USB_INTSTAT_FRAME_INT_MASK               (0x40000000U)
+#define USB_INTSTAT_FRAME_INT_SHIFT              (30U)
+/*! FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit
+ *    and the DCON bit are set. This bit can be used by software when handling isochronous
+ *    endpoints. Software can clear this bit by writing a one to it.
+ */
+#define USB_INTSTAT_FRAME_INT(x)                 (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK)
+#define USB_INTSTAT_DEV_INT_MASK                 (0x80000000U)
+#define USB_INTSTAT_DEV_INT_SHIFT                (31U)
+/*! DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device
+ *    Status Change register are set. Software can clear this bit by writing a one to it.
+ */
+#define USB_INTSTAT_DEV_INT(x)                   (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK)
+/*! @} */
+
+/*! @name INTEN - USB interrupt enable register */
+/*! @{ */
+#define USB_INTEN_EP_INT_EN_MASK                 (0x3FFU)
+#define USB_INTEN_EP_INT_EN_SHIFT                (0U)
+/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
+ *    interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing
+ *    bit.
+ */
+#define USB_INTEN_EP_INT_EN(x)                   (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK)
+#define USB_INTEN_FRAME_INT_EN_MASK              (0x40000000U)
+#define USB_INTEN_FRAME_INT_EN_SHIFT             (30U)
+/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
+ *    interrupt is generated on the interrupt line indicated by the corresponding USB interrupt
+ *    routing bit.
+ */
+#define USB_INTEN_FRAME_INT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK)
+#define USB_INTEN_DEV_INT_EN_MASK                (0x80000000U)
+#define USB_INTEN_DEV_INT_EN_SHIFT               (31U)
+/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
+ *    interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing
+ *    bit.
+ */
+#define USB_INTEN_DEV_INT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK)
+/*! @} */
+
+/*! @name INTSETSTAT - USB set interrupt status register */
+/*! @{ */
+#define USB_INTSETSTAT_EP_SET_INT_MASK           (0x3FFU)
+#define USB_INTSETSTAT_EP_SET_INT_SHIFT          (0U)
+/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt
+ *    status bit is set. When this register is read, the same value as the USB interrupt status register
+ *    is returned.
+ */
+#define USB_INTSETSTAT_EP_SET_INT(x)             (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK)
+#define USB_INTSETSTAT_FRAME_SET_INT_MASK        (0x40000000U)
+#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT       (30U)
+/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt
+ *    status bit is set. When this register is read, the same value as the USB interrupt status
+ *    register is returned.
+ */
+#define USB_INTSETSTAT_FRAME_SET_INT(x)          (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK)
+#define USB_INTSETSTAT_DEV_SET_INT_MASK          (0x80000000U)
+#define USB_INTSETSTAT_DEV_SET_INT_SHIFT         (31U)
+/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt
+ *    status bit is set. When this register is read, the same value as the USB interrupt status
+ *    register is returned.
+ */
+#define USB_INTSETSTAT_DEV_SET_INT(x)            (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK)
+/*! @} */
+
+/*! @name EPTOGGLE - USB Endpoint toggle register */
+/*! @{ */
+#define USB_EPTOGGLE_TOGGLE_MASK                 (0x3FFU)
+#define USB_EPTOGGLE_TOGGLE_SHIFT                (0U)
+/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint.
+ */
+#define USB_EPTOGGLE_TOGGLE(x)                   (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40084000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS                           { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS                            { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS                                 { USB0_IRQn }
+#define USB_NEEDCLK_IRQS                         { USB0_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBFSH Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer
+ * @{
+ */
+
+/** USBFSH - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t HCREVISION;                        /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */
+  __IO uint32_t HCCONTROL;                         /**< Defines the operating modes of the HC, offset: 0x4 */
+  __IO uint32_t HCCOMMANDSTATUS;                   /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */
+  __IO uint32_t HCINTERRUPTSTATUS;                 /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */
+  __IO uint32_t HCINTERRUPTENABLE;                 /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */
+  __IO uint32_t HCINTERRUPTDISABLE;                /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */
+  __IO uint32_t HCHCCA;                            /**< Contains the physical address of the host controller communication area, offset: 0x18 */
+  __I  uint32_t HCPERIODCURRENTED;                 /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */
+  __IO uint32_t HCCONTROLHEADED;                   /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */
+  __IO uint32_t HCCONTROLCURRENTED;                /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */
+  __IO uint32_t HCBULKHEADED;                      /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */
+  __IO uint32_t HCBULKCURRENTED;                   /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */
+  __I  uint32_t HCDONEHEAD;                        /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */
+  __IO uint32_t HCFMINTERVAL;                      /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */
+  __I  uint32_t HCFMREMAINING;                     /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */
+  __I  uint32_t HCFMNUMBER;                        /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */
+  __IO uint32_t HCPERIODICSTART;                   /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */
+  __IO uint32_t HCLSTHRESHOLD;                     /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */
+  __IO uint32_t HCRHDESCRIPTORA;                   /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */
+  __IO uint32_t HCRHDESCRIPTORB;                   /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */
+  __IO uint32_t HCRHSTATUS;                        /**< This register is divided into two parts, offset: 0x50 */
+  __IO uint32_t HCRHPORTSTATUS;                    /**< Controls and reports the port events on a per-port basis, offset: 0x54 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t PORTMODE;                          /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */
+} USBFSH_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USBFSH Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBFSH_Register_Masks USBFSH Register Masks
+ * @{
+ */
+
+/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */
+/*! @{ */
+#define USBFSH_HCREVISION_REV_MASK               (0xFFU)
+#define USBFSH_HCREVISION_REV_SHIFT              (0U)
+/*! REV - Revision.
+ */
+#define USBFSH_HCREVISION_REV(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK)
+/*! @} */
+
+/*! @name HCCONTROL - Defines the operating modes of the HC */
+/*! @{ */
+#define USBFSH_HCCONTROL_CBSR_MASK               (0x3U)
+#define USBFSH_HCCONTROL_CBSR_SHIFT              (0U)
+/*! CBSR - ControlBulkServiceRatio.
+ */
+#define USBFSH_HCCONTROL_CBSR(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK)
+#define USBFSH_HCCONTROL_PLE_MASK                (0x4U)
+#define USBFSH_HCCONTROL_PLE_SHIFT               (2U)
+/*! PLE - PeriodicListEnable.
+ */
+#define USBFSH_HCCONTROL_PLE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK)
+#define USBFSH_HCCONTROL_IE_MASK                 (0x8U)
+#define USBFSH_HCCONTROL_IE_SHIFT                (3U)
+/*! IE - IsochronousEnable.
+ */
+#define USBFSH_HCCONTROL_IE(x)                   (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK)
+#define USBFSH_HCCONTROL_CLE_MASK                (0x10U)
+#define USBFSH_HCCONTROL_CLE_SHIFT               (4U)
+/*! CLE - ControlListEnable.
+ */
+#define USBFSH_HCCONTROL_CLE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK)
+#define USBFSH_HCCONTROL_BLE_MASK                (0x20U)
+#define USBFSH_HCCONTROL_BLE_SHIFT               (5U)
+/*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame.
+ */
+#define USBFSH_HCCONTROL_BLE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK)
+#define USBFSH_HCCONTROL_HCFS_MASK               (0xC0U)
+#define USBFSH_HCCONTROL_HCFS_SHIFT              (6U)
+/*! HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL
+ *    11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin
+ *    1 ms later.
+ */
+#define USBFSH_HCCONTROL_HCFS(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK)
+#define USBFSH_HCCONTROL_IR_MASK                 (0x100U)
+#define USBFSH_HCCONTROL_IR_SHIFT                (8U)
+/*! IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus.
+ */
+#define USBFSH_HCCONTROL_IR(x)                   (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK)
+#define USBFSH_HCCONTROL_RWC_MASK                (0x200U)
+#define USBFSH_HCCONTROL_RWC_SHIFT               (9U)
+/*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling.
+ */
+#define USBFSH_HCCONTROL_RWC(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK)
+#define USBFSH_HCCONTROL_RWE_MASK                (0x400U)
+#define USBFSH_HCCONTROL_RWE_SHIFT               (10U)
+/*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature
+ *    upon the detection of upstream resume signaling.
+ */
+#define USBFSH_HCCONTROL_RWE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK)
+/*! @} */
+
+/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */
+/*! @{ */
+#define USBFSH_HCCOMMANDSTATUS_HCR_MASK          (0x1U)
+#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT         (0U)
+/*! HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC.
+ */
+#define USBFSH_HCCOMMANDSTATUS_HCR(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK)
+#define USBFSH_HCCOMMANDSTATUS_CLF_MASK          (0x2U)
+#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT         (1U)
+/*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list.
+ */
+#define USBFSH_HCCOMMANDSTATUS_CLF(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK)
+#define USBFSH_HCCOMMANDSTATUS_BLF_MASK          (0x4U)
+#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT         (2U)
+/*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list.
+ */
+#define USBFSH_HCCOMMANDSTATUS_BLF(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK)
+#define USBFSH_HCCOMMANDSTATUS_OCR_MASK          (0x8U)
+#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT         (3U)
+/*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC.
+ */
+#define USBFSH_HCCOMMANDSTATUS_OCR(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK)
+#define USBFSH_HCCOMMANDSTATUS_SOC_MASK          (0xC0U)
+#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT         (6U)
+/*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error.
+ */
+#define USBFSH_HCCOMMANDSTATUS_SOC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK)
+/*! @} */
+
+/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */
+/*! @{ */
+#define USBFSH_HCINTERRUPTSTATUS_SO_MASK         (0x1U)
+#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT        (0U)
+/*! SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and
+ *    after the update of HccaFrameNumber.
+ */
+#define USBFSH_HCINTERRUPTSTATUS_SO(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK        (0x2U)
+#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT       (1U)
+/*! WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead.
+ */
+#define USBFSH_HCINTERRUPTSTATUS_WDH(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_SF_MASK         (0x4U)
+#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT        (2U)
+/*! SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber.
+ */
+#define USBFSH_HCINTERRUPTSTATUS_SF(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_RD_MASK         (0x8U)
+#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT        (3U)
+/*! RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling.
+ */
+#define USBFSH_HCINTERRUPTSTATUS_RD(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_UE_MASK         (0x10U)
+#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT        (4U)
+/*! UE - UnrecoverableError This bit is set when HC detects a system error not related to USB.
+ */
+#define USBFSH_HCINTERRUPTSTATUS_UE(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK        (0x20U)
+#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT       (5U)
+/*! FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value,
+ *    from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated.
+ */
+#define USBFSH_HCINTERRUPTSTATUS_FNO(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK       (0x40U)
+#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT      (6U)
+/*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any
+ *    of HcRhPortStatus[NumberofDownstreamPort] has changed.
+ */
+#define USBFSH_HCINTERRUPTSTATUS_RHSC(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_OC_MASK         (0xFFFFFC00U)
+#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT        (10U)
+/*! OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus.
+ */
+#define USBFSH_HCINTERRUPTSTATUS_OC(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK)
+/*! @} */
+
+/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */
+/*! @{ */
+#define USBFSH_HCINTERRUPTENABLE_SO_MASK         (0x1U)
+#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT        (0U)
+/*! SO - Scheduling Overrun interrupt.
+ */
+#define USBFSH_HCINTERRUPTENABLE_SO(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK)
+#define USBFSH_HCINTERRUPTENABLE_WDH_MASK        (0x2U)
+#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT       (1U)
+/*! WDH - HcDoneHead Writeback interrupt.
+ */
+#define USBFSH_HCINTERRUPTENABLE_WDH(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK)
+#define USBFSH_HCINTERRUPTENABLE_SF_MASK         (0x4U)
+#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT        (2U)
+/*! SF - Start of Frame interrupt.
+ */
+#define USBFSH_HCINTERRUPTENABLE_SF(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK)
+#define USBFSH_HCINTERRUPTENABLE_RD_MASK         (0x8U)
+#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT        (3U)
+/*! RD - Resume Detect interrupt.
+ */
+#define USBFSH_HCINTERRUPTENABLE_RD(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK)
+#define USBFSH_HCINTERRUPTENABLE_UE_MASK         (0x10U)
+#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT        (4U)
+/*! UE - Unrecoverable Error interrupt.
+ */
+#define USBFSH_HCINTERRUPTENABLE_UE(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK)
+#define USBFSH_HCINTERRUPTENABLE_FNO_MASK        (0x20U)
+#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT       (5U)
+/*! FNO - Frame Number Overflow interrupt.
+ */
+#define USBFSH_HCINTERRUPTENABLE_FNO(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK)
+#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK       (0x40U)
+#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT      (6U)
+/*! RHSC - Root Hub Status Change interrupt.
+ */
+#define USBFSH_HCINTERRUPTENABLE_RHSC(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK)
+#define USBFSH_HCINTERRUPTENABLE_OC_MASK         (0x40000000U)
+#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT        (30U)
+/*! OC - Ownership Change interrupt.
+ */
+#define USBFSH_HCINTERRUPTENABLE_OC(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK)
+#define USBFSH_HCINTERRUPTENABLE_MIE_MASK        (0x80000000U)
+#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT       (31U)
+/*! MIE - Master Interrupt Enable.
+ */
+#define USBFSH_HCINTERRUPTENABLE_MIE(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK)
+/*! @} */
+
+/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */
+/*! @{ */
+#define USBFSH_HCINTERRUPTDISABLE_SO_MASK        (0x1U)
+#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT       (0U)
+/*! SO - Scheduling Overrun interrupt.
+ */
+#define USBFSH_HCINTERRUPTDISABLE_SO(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK       (0x2U)
+#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT      (1U)
+/*! WDH - HcDoneHead Writeback interrupt.
+ */
+#define USBFSH_HCINTERRUPTDISABLE_WDH(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_SF_MASK        (0x4U)
+#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT       (2U)
+/*! SF - Start of Frame interrupt.
+ */
+#define USBFSH_HCINTERRUPTDISABLE_SF(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_RD_MASK        (0x8U)
+#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT       (3U)
+/*! RD - Resume Detect interrupt.
+ */
+#define USBFSH_HCINTERRUPTDISABLE_RD(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_UE_MASK        (0x10U)
+#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT       (4U)
+/*! UE - Unrecoverable Error interrupt.
+ */
+#define USBFSH_HCINTERRUPTDISABLE_UE(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK       (0x20U)
+#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT      (5U)
+/*! FNO - Frame Number Overflow interrupt.
+ */
+#define USBFSH_HCINTERRUPTDISABLE_FNO(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK      (0x40U)
+#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT     (6U)
+/*! RHSC - Root Hub Status Change interrupt.
+ */
+#define USBFSH_HCINTERRUPTDISABLE_RHSC(x)        (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_OC_MASK        (0x40000000U)
+#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT       (30U)
+/*! OC - Ownership Change interrupt.
+ */
+#define USBFSH_HCINTERRUPTDISABLE_OC(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK       (0x80000000U)
+#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT      (31U)
+/*! MIE - A 0 written to this field is ignored by HC.
+ */
+#define USBFSH_HCINTERRUPTDISABLE_MIE(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK)
+/*! @} */
+
+/*! @name HCHCCA - Contains the physical address of the host controller communication area */
+/*! @{ */
+#define USBFSH_HCHCCA_HCCA_MASK                  (0xFFFFFF00U)
+#define USBFSH_HCHCCA_HCCA_SHIFT                 (8U)
+/*! HCCA - Base address of the Host Controller Communication Area.
+ */
+#define USBFSH_HCHCCA_HCCA(x)                    (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK)
+/*! @} */
+
+/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */
+/*! @{ */
+#define USBFSH_HCPERIODCURRENTED_PCED_MASK       (0xFFFFFFF0U)
+#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT      (4U)
+/*! PCED - The content of this register is updated by HC after a periodic ED is processed.
+ */
+#define USBFSH_HCPERIODCURRENTED_PCED(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK)
+/*! @} */
+
+/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */
+/*! @{ */
+#define USBFSH_HCCONTROLHEADED_CHED_MASK         (0xFFFFFFF0U)
+#define USBFSH_HCCONTROLHEADED_CHED_SHIFT        (4U)
+/*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer.
+ */
+#define USBFSH_HCCONTROLHEADED_CHED(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK)
+/*! @} */
+
+/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */
+/*! @{ */
+#define USBFSH_HCCONTROLCURRENTED_CCED_MASK      (0xFFFFFFF0U)
+#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT     (4U)
+/*! CCED - ControlCurrentED.
+ */
+#define USBFSH_HCCONTROLCURRENTED_CCED(x)        (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK)
+/*! @} */
+
+/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */
+/*! @{ */
+#define USBFSH_HCBULKHEADED_BHED_MASK            (0xFFFFFFF0U)
+#define USBFSH_HCBULKHEADED_BHED_SHIFT           (4U)
+/*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer.
+ */
+#define USBFSH_HCBULKHEADED_BHED(x)              (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK)
+/*! @} */
+
+/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */
+/*! @{ */
+#define USBFSH_HCBULKCURRENTED_BCED_MASK         (0xFFFFFFF0U)
+#define USBFSH_HCBULKCURRENTED_BCED_SHIFT        (4U)
+/*! BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one.
+ */
+#define USBFSH_HCBULKCURRENTED_BCED(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK)
+/*! @} */
+
+/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */
+/*! @{ */
+#define USBFSH_HCDONEHEAD_DH_MASK                (0xFFFFFFF0U)
+#define USBFSH_HCDONEHEAD_DH_SHIFT               (4U)
+/*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD.
+ */
+#define USBFSH_HCDONEHEAD_DH(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK)
+/*! @} */
+
+/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */
+/*! @{ */
+#define USBFSH_HCFMINTERVAL_FI_MASK              (0x3FFFU)
+#define USBFSH_HCFMINTERVAL_FI_SHIFT             (0U)
+/*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times.
+ */
+#define USBFSH_HCFMINTERVAL_FI(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK)
+#define USBFSH_HCFMINTERVAL_FSMPS_MASK           (0x7FFF0000U)
+#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT          (16U)
+/*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data
+ *    Packet Counter at the beginning of each frame.
+ */
+#define USBFSH_HCFMINTERVAL_FSMPS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK)
+#define USBFSH_HCFMINTERVAL_FIT_MASK             (0x80000000U)
+#define USBFSH_HCFMINTERVAL_FIT_SHIFT            (31U)
+/*! FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval.
+ */
+#define USBFSH_HCFMINTERVAL_FIT(x)               (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK)
+/*! @} */
+
+/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */
+/*! @{ */
+#define USBFSH_HCFMREMAINING_FR_MASK             (0x3FFFU)
+#define USBFSH_HCFMREMAINING_FR_SHIFT            (0U)
+/*! FR - FrameRemaining This counter is decremented at each bit time.
+ */
+#define USBFSH_HCFMREMAINING_FR(x)               (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK)
+#define USBFSH_HCFMREMAINING_FRT_MASK            (0x80000000U)
+#define USBFSH_HCFMREMAINING_FRT_SHIFT           (31U)
+/*! FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval
+ *    whenever FrameRemaining reaches 0.
+ */
+#define USBFSH_HCFMREMAINING_FRT(x)              (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK)
+/*! @} */
+
+/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */
+/*! @{ */
+#define USBFSH_HCFMNUMBER_FN_MASK                (0xFFFFU)
+#define USBFSH_HCFMNUMBER_FN_SHIFT               (0U)
+/*! FN - FrameNumber This is incremented when HcFmRemaining is re-loaded.
+ */
+#define USBFSH_HCFMNUMBER_FN(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK)
+/*! @} */
+
+/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */
+/*! @{ */
+#define USBFSH_HCPERIODICSTART_PS_MASK           (0x3FFFU)
+#define USBFSH_HCPERIODICSTART_PS_SHIFT          (0U)
+/*! PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization.
+ */
+#define USBFSH_HCPERIODICSTART_PS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK)
+/*! @} */
+
+/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */
+/*! @{ */
+#define USBFSH_HCLSTHRESHOLD_LST_MASK            (0xFFFU)
+#define USBFSH_HCLSTHRESHOLD_LST_SHIFT           (0U)
+/*! LST - LSThreshold This field contains a value which is compared to the FrameRemaining field
+ *    prior to initiating a Low Speed transaction.
+ */
+#define USBFSH_HCLSTHRESHOLD_LST(x)              (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK)
+/*! @} */
+
+/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */
+/*! @{ */
+#define USBFSH_HCRHDESCRIPTORA_NDP_MASK          (0xFFU)
+#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT         (0U)
+/*! NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub.
+ */
+#define USBFSH_HCRHDESCRIPTORA_NDP(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK)
+#define USBFSH_HCRHDESCRIPTORA_PSM_MASK          (0x100U)
+#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT         (8U)
+/*! PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled.
+ */
+#define USBFSH_HCRHDESCRIPTORA_PSM(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK)
+#define USBFSH_HCRHDESCRIPTORA_NPS_MASK          (0x200U)
+#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT         (9U)
+/*! NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered.
+ */
+#define USBFSH_HCRHDESCRIPTORA_NPS(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK)
+#define USBFSH_HCRHDESCRIPTORA_DT_MASK           (0x400U)
+#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT          (10U)
+/*! DT - DeviceType This bit specifies that the root hub is not a compound device.
+ */
+#define USBFSH_HCRHDESCRIPTORA_DT(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK)
+#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK         (0x800U)
+#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT        (11U)
+/*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported.
+ */
+#define USBFSH_HCRHDESCRIPTORA_OCPM(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK)
+#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK         (0x1000U)
+#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT        (12U)
+/*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported.
+ */
+#define USBFSH_HCRHDESCRIPTORA_NOCP(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK)
+#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK       (0xFF000000U)
+#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT      (24U)
+/*! POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before
+ *    accessing a powered-on port of the root hub.
+ */
+#define USBFSH_HCRHDESCRIPTORA_POTPGT(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK)
+/*! @} */
+
+/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */
+/*! @{ */
+#define USBFSH_HCRHDESCRIPTORB_DR_MASK           (0xFFFFU)
+#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT          (0U)
+/*! DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub.
+ */
+#define USBFSH_HCRHDESCRIPTORB_DR(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK)
+#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK         (0xFFFF0000U)
+#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT        (16U)
+/*! PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control
+ *    command when PowerSwitchingMode is set.
+ */
+#define USBFSH_HCRHDESCRIPTORB_PPCM(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK)
+/*! @} */
+
+/*! @name HCRHSTATUS - This register is divided into two parts */
+/*! @{ */
+#define USBFSH_HCRHSTATUS_LPS_MASK               (0x1U)
+#define USBFSH_HCRHSTATUS_LPS_SHIFT              (0U)
+/*! LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature;
+ *    thus, this bit is always read as 0.
+ */
+#define USBFSH_HCRHSTATUS_LPS(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK)
+#define USBFSH_HCRHSTATUS_OCI_MASK               (0x2U)
+#define USBFSH_HCRHSTATUS_OCI_SHIFT              (1U)
+/*! OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented.
+ */
+#define USBFSH_HCRHSTATUS_OCI(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK)
+#define USBFSH_HCRHSTATUS_DRWE_MASK              (0x8000U)
+#define USBFSH_HCRHSTATUS_DRWE_SHIFT             (15U)
+/*! DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume
+ *    event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected
+ *    interrupt.
+ */
+#define USBFSH_HCRHSTATUS_DRWE(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK)
+#define USBFSH_HCRHSTATUS_LPSC_MASK              (0x10000U)
+#define USBFSH_HCRHSTATUS_LPSC_SHIFT             (16U)
+/*! LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature.
+ */
+#define USBFSH_HCRHSTATUS_LPSC(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK)
+#define USBFSH_HCRHSTATUS_OCIC_MASK              (0x20000U)
+#define USBFSH_HCRHSTATUS_OCIC_SHIFT             (17U)
+/*! OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register.
+ */
+#define USBFSH_HCRHSTATUS_OCIC(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK)
+#define USBFSH_HCRHSTATUS_CRWE_MASK              (0x80000000U)
+#define USBFSH_HCRHSTATUS_CRWE_SHIFT             (31U)
+/*! CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable.
+ */
+#define USBFSH_HCRHSTATUS_CRWE(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK)
+/*! @} */
+
+/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */
+/*! @{ */
+#define USBFSH_HCRHPORTSTATUS_CCS_MASK           (0x1U)
+#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT          (0U)
+/*! CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port.
+ */
+#define USBFSH_HCRHPORTSTATUS_CCS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK)
+#define USBFSH_HCRHPORTSTATUS_PES_MASK           (0x2U)
+#define USBFSH_HCRHPORTSTATUS_PES_SHIFT          (1U)
+/*! PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled.
+ */
+#define USBFSH_HCRHPORTSTATUS_PES(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK)
+#define USBFSH_HCRHPORTSTATUS_PSS_MASK           (0x4U)
+#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT          (2U)
+/*! PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence.
+ */
+#define USBFSH_HCRHPORTSTATUS_PSS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK)
+#define USBFSH_HCRHPORTSTATUS_POCI_MASK          (0x8U)
+#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT         (3U)
+/*! POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in
+ *    such a way that overcurrent conditions are reported on a per-port basis.
+ */
+#define USBFSH_HCRHPORTSTATUS_POCI(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK)
+#define USBFSH_HCRHPORTSTATUS_PRS_MASK           (0x10U)
+#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT          (4U)
+/*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted.
+ */
+#define USBFSH_HCRHPORTSTATUS_PRS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK)
+#define USBFSH_HCRHPORTSTATUS_PPS_MASK           (0x100U)
+#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT          (8U)
+/*! PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type
+ *    of power switching implemented.
+ */
+#define USBFSH_HCRHPORTSTATUS_PPS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK)
+#define USBFSH_HCRHPORTSTATUS_LSDA_MASK          (0x200U)
+#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT         (9U)
+/*! LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port.
+ */
+#define USBFSH_HCRHPORTSTATUS_LSDA(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK)
+#define USBFSH_HCRHPORTSTATUS_CSC_MASK           (0x10000U)
+#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT          (16U)
+/*! CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs.
+ */
+#define USBFSH_HCRHPORTSTATUS_CSC(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK)
+#define USBFSH_HCRHPORTSTATUS_PESC_MASK          (0x20000U)
+#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT         (17U)
+/*! PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared.
+ */
+#define USBFSH_HCRHPORTSTATUS_PESC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK)
+#define USBFSH_HCRHPORTSTATUS_PSSC_MASK          (0x40000U)
+#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT         (18U)
+/*! PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed.
+ */
+#define USBFSH_HCRHPORTSTATUS_PSSC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK)
+#define USBFSH_HCRHPORTSTATUS_OCIC_MASK          (0x80000U)
+#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT         (19U)
+/*! OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis.
+ */
+#define USBFSH_HCRHPORTSTATUS_OCIC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK)
+#define USBFSH_HCRHPORTSTATUS_PRSC_MASK          (0x100000U)
+#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT         (20U)
+/*! PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal.
+ */
+#define USBFSH_HCRHPORTSTATUS_PRSC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK)
+/*! @} */
+
+/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
+/*! @{ */
+#define USBFSH_PORTMODE_ID_MASK                  (0x1U)
+#define USBFSH_PORTMODE_ID_SHIFT                 (0U)
+/*! ID - Port ID pin value.
+ */
+#define USBFSH_PORTMODE_ID(x)                    (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK)
+#define USBFSH_PORTMODE_ID_EN_MASK               (0x100U)
+#define USBFSH_PORTMODE_ID_EN_SHIFT              (8U)
+/*! ID_EN - Port ID pin pull-up enable.
+ */
+#define USBFSH_PORTMODE_ID_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK)
+#define USBFSH_PORTMODE_DEV_ENABLE_MASK          (0x10000U)
+#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT         (16U)
+/*! DEV_ENABLE - 1: device 0: host.
+ */
+#define USBFSH_PORTMODE_DEV_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USBFSH_Register_Masks */
+
+
+/* USBFSH - Peripheral instance base addresses */
+/** Peripheral USBFSH base address */
+#define USBFSH_BASE                              (0x400A2000u)
+/** Peripheral USBFSH base pointer */
+#define USBFSH                                   ((USBFSH_Type *)USBFSH_BASE)
+/** Array initializer of USBFSH peripheral base addresses */
+#define USBFSH_BASE_ADDRS                        { USBFSH_BASE }
+/** Array initializer of USBFSH peripheral base pointers */
+#define USBFSH_BASE_PTRS                         { USBFSH }
+/** Interrupt vectors for the USBFSH peripheral type */
+#define USBFSH_IRQS                              { USB0_IRQn }
+#define USBFSH_NEEDCLK_IRQS                      { USB0_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBFSH_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBHSD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer
+ * @{
+ */
+
+/** USBHSD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DEVCMDSTAT;                        /**< USB Device Command/Status register, offset: 0x0 */
+  __I  uint32_t INFO;                              /**< USB Info register, offset: 0x4 */
+  __IO uint32_t EPLISTSTART;                       /**< USB EP Command/Status List start address, offset: 0x8 */
+  __IO uint32_t DATABUFSTART;                      /**< USB Data buffer start address, offset: 0xC */
+  __IO uint32_t LPM;                               /**< USB Link Power Management register, offset: 0x10 */
+  __IO uint32_t EPSKIP;                            /**< USB Endpoint skip, offset: 0x14 */
+  __IO uint32_t EPINUSE;                           /**< USB Endpoint Buffer in use, offset: 0x18 */
+  __IO uint32_t EPBUFCFG;                          /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
+  __IO uint32_t INTSTAT;                           /**< USB interrupt status register, offset: 0x20 */
+  __IO uint32_t INTEN;                             /**< USB interrupt enable register, offset: 0x24 */
+  __IO uint32_t INTSETSTAT;                        /**< USB set interrupt status register, offset: 0x28 */
+       uint8_t RESERVED_0[8];
+  __I  uint32_t EPTOGGLE;                          /**< USB Endpoint toggle register, offset: 0x34 */
+} USBHSD_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USBHSD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSD_Register_Masks USBHSD Register Masks
+ * @{
+ */
+
+/*! @name DEVCMDSTAT - USB Device Command/Status register */
+/*! @{ */
+#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK          (0x7FU)
+#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT         (0U)
+/*! DEV_ADDR - USB device address.
+ */
+#define USBHSD_DEVCMDSTAT_DEV_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK)
+#define USBHSD_DEVCMDSTAT_DEV_EN_MASK            (0x80U)
+#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT           (7U)
+/*! DEV_EN - USB device enable.
+ */
+#define USBHSD_DEVCMDSTAT_DEV_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK)
+#define USBHSD_DEVCMDSTAT_SETUP_MASK             (0x100U)
+#define USBHSD_DEVCMDSTAT_SETUP_SHIFT            (8U)
+/*! SETUP - SETUP token received.
+ */
+#define USBHSD_DEVCMDSTAT_SETUP(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK)
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK     (0x200U)
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT    (9U)
+/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:.
+ */
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x)       (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK        (0x400U)
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT       (10U)
+/*! FORCE_VBUS - If this bit is set to 1, the VBUS voltage indicators from the PHY are overruled.
+ */
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS(x)          (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK)
+#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK           (0x800U)
+#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT          (11U)
+/*! LPM_SUP - LPM Supported:.
+ */
+#define USBHSD_DEVCMDSTAT_LPM_SUP(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK       (0x1000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT      (12U)
+/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:.
+ */
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK       (0x2000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT      (13U)
+/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:.
+ */
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK       (0x4000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT      (14U)
+/*! INTONNAK_CO - Interrupt on NAK for control OUT EP:.
+ */
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK       (0x8000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT      (15U)
+/*! INTONNAK_CI - Interrupt on NAK for control IN EP:.
+ */
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK)
+#define USBHSD_DEVCMDSTAT_DCON_MASK              (0x10000U)
+#define USBHSD_DEVCMDSTAT_DCON_SHIFT             (16U)
+/*! DCON - Device status - connect.
+ */
+#define USBHSD_DEVCMDSTAT_DCON(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK)
+#define USBHSD_DEVCMDSTAT_DSUS_MASK              (0x20000U)
+#define USBHSD_DEVCMDSTAT_DSUS_SHIFT             (17U)
+/*! DSUS - Device status - suspend.
+ */
+#define USBHSD_DEVCMDSTAT_DSUS(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK)
+#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK           (0x80000U)
+#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT          (19U)
+/*! LPM_SUS - Device status - LPM Suspend.
+ */
+#define USBHSD_DEVCMDSTAT_LPM_SUS(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK)
+#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK          (0x100000U)
+#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT         (20U)
+/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host.
+ */
+#define USBHSD_DEVCMDSTAT_LPM_REWP(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK)
+#define USBHSD_DEVCMDSTAT_Speed_MASK             (0xC00000U)
+#define USBHSD_DEVCMDSTAT_Speed_SHIFT            (22U)
+/*! Speed - This field indicates the speed at which the device operates: 00b: reserved 01b:
+ *    full-speed 10b: high-speed 11b: super-speed (reserved for future use).
+ */
+#define USBHSD_DEVCMDSTAT_Speed(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK)
+#define USBHSD_DEVCMDSTAT_DCON_C_MASK            (0x1000000U)
+#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT           (24U)
+/*! DCON_C - Device status - connect change.
+ */
+#define USBHSD_DEVCMDSTAT_DCON_C(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK)
+#define USBHSD_DEVCMDSTAT_DSUS_C_MASK            (0x2000000U)
+#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT           (25U)
+/*! DSUS_C - Device status - suspend change.
+ */
+#define USBHSD_DEVCMDSTAT_DSUS_C(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK)
+#define USBHSD_DEVCMDSTAT_DRES_C_MASK            (0x4000000U)
+#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT           (26U)
+/*! DRES_C - Device status - reset change.
+ */
+#define USBHSD_DEVCMDSTAT_DRES_C(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK)
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK    (0x10000000U)
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT   (28U)
+/*! VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not.
+ */
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x)      (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK     (0xE0000000U)
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT    (29U)
+/*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.
+ */
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x)       (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK)
+/*! @} */
+
+/*! @name INFO - USB Info register */
+/*! @{ */
+#define USBHSD_INFO_FRAME_NR_MASK                (0x7FFU)
+#define USBHSD_INFO_FRAME_NR_SHIFT               (0U)
+/*! FRAME_NR - Frame number.
+ */
+#define USBHSD_INFO_FRAME_NR(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK)
+#define USBHSD_INFO_ERR_CODE_MASK                (0x7800U)
+#define USBHSD_INFO_ERR_CODE_SHIFT               (11U)
+/*! ERR_CODE - The error code which last occurred:.
+ */
+#define USBHSD_INFO_ERR_CODE(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK)
+#define USBHSD_INFO_Minrev_MASK                  (0xFF0000U)
+#define USBHSD_INFO_Minrev_SHIFT                 (16U)
+/*! Minrev - Minor revision.
+ */
+#define USBHSD_INFO_Minrev(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK)
+#define USBHSD_INFO_Majrev_MASK                  (0xFF000000U)
+#define USBHSD_INFO_Majrev_SHIFT                 (24U)
+/*! Majrev - Major revision.
+ */
+#define USBHSD_INFO_Majrev(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK)
+/*! @} */
+
+/*! @name EPLISTSTART - USB EP Command/Status List start address */
+/*! @{ */
+#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK      (0xFFF00U)
+#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT     (8U)
+/*! EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address.
+ */
+#define USBHSD_EPLISTSTART_EP_LIST_PRG(x)        (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK)
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK    (0xFFF00000U)
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT   (20U)
+/*! EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address.
+ */
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x)      (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK)
+/*! @} */
+
+/*! @name DATABUFSTART - USB Data buffer start address */
+/*! @{ */
+#define USBHSD_DATABUFSTART_DA_BUF_MASK          (0xFFFC0000U)
+#define USBHSD_DATABUFSTART_DA_BUF_SHIFT         (18U)
+/*! DA_BUF - Start address of the memory page where all endpoint data buffers are located.
+ */
+#define USBHSD_DATABUFSTART_DA_BUF(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK)
+/*! @} */
+
+/*! @name LPM - USB Link Power Management register */
+/*! @{ */
+#define USBHSD_LPM_HIRD_HW_MASK                  (0xFU)
+#define USBHSD_LPM_HIRD_HW_SHIFT                 (0U)
+/*! HIRD_HW - Host Initiated Resume Duration - HW.
+ */
+#define USBHSD_LPM_HIRD_HW(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK)
+#define USBHSD_LPM_HIRD_SW_MASK                  (0xF0U)
+#define USBHSD_LPM_HIRD_SW_SHIFT                 (4U)
+/*! HIRD_SW - Host Initiated Resume Duration - SW.
+ */
+#define USBHSD_LPM_HIRD_SW(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK)
+#define USBHSD_LPM_DATA_PENDING_MASK             (0x100U)
+#define USBHSD_LPM_DATA_PENDING_SHIFT            (8U)
+/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will
+ *    return a NYET handshake on every LPM token it receives.
+ */
+#define USBHSD_LPM_DATA_PENDING(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK)
+/*! @} */
+
+/*! @name EPSKIP - USB Endpoint skip */
+/*! @{ */
+#define USBHSD_EPSKIP_SKIP_MASK                  (0xFFFU)
+#define USBHSD_EPSKIP_SKIP_SHIFT                 (0U)
+/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must
+ *    deactivate the buffer assigned to this endpoint and return control back to software.
+ */
+#define USBHSD_EPSKIP_SKIP(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK)
+/*! @} */
+
+/*! @name EPINUSE - USB Endpoint Buffer in use */
+/*! @{ */
+#define USBHSD_EPINUSE_BUF_MASK                  (0xFFCU)
+#define USBHSD_EPINUSE_BUF_SHIFT                 (2U)
+/*! BUF - Buffer in use: This register has one bit per physical endpoint.
+ */
+#define USBHSD_EPINUSE_BUF(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK)
+/*! @} */
+
+/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
+/*! @{ */
+#define USBHSD_EPBUFCFG_BUF_SB_MASK              (0xFFCU)
+#define USBHSD_EPBUFCFG_BUF_SB_SHIFT             (2U)
+/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint.
+ */
+#define USBHSD_EPBUFCFG_BUF_SB(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK)
+/*! @} */
+
+/*! @name INTSTAT - USB interrupt status register */
+/*! @{ */
+#define USBHSD_INTSTAT_EP0OUT_MASK               (0x1U)
+#define USBHSD_INTSTAT_EP0OUT_SHIFT              (0U)
+/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction.
+ */
+#define USBHSD_INTSTAT_EP0OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK)
+#define USBHSD_INTSTAT_EP0IN_MASK                (0x2U)
+#define USBHSD_INTSTAT_EP0IN_SHIFT               (1U)
+/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction.
+ */
+#define USBHSD_INTSTAT_EP0IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK)
+#define USBHSD_INTSTAT_EP1OUT_MASK               (0x4U)
+#define USBHSD_INTSTAT_EP1OUT_SHIFT              (2U)
+/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction.
+ */
+#define USBHSD_INTSTAT_EP1OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK)
+#define USBHSD_INTSTAT_EP1IN_MASK                (0x8U)
+#define USBHSD_INTSTAT_EP1IN_SHIFT               (3U)
+/*! EP1IN - Interrupt status register bit for the EP1 IN direction.
+ */
+#define USBHSD_INTSTAT_EP1IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK)
+#define USBHSD_INTSTAT_EP2OUT_MASK               (0x10U)
+#define USBHSD_INTSTAT_EP2OUT_SHIFT              (4U)
+/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction.
+ */
+#define USBHSD_INTSTAT_EP2OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK)
+#define USBHSD_INTSTAT_EP2IN_MASK                (0x20U)
+#define USBHSD_INTSTAT_EP2IN_SHIFT               (5U)
+/*! EP2IN - Interrupt status register bit for the EP2 IN direction.
+ */
+#define USBHSD_INTSTAT_EP2IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK)
+#define USBHSD_INTSTAT_EP3OUT_MASK               (0x40U)
+#define USBHSD_INTSTAT_EP3OUT_SHIFT              (6U)
+/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction.
+ */
+#define USBHSD_INTSTAT_EP3OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK)
+#define USBHSD_INTSTAT_EP3IN_MASK                (0x80U)
+#define USBHSD_INTSTAT_EP3IN_SHIFT               (7U)
+/*! EP3IN - Interrupt status register bit for the EP3 IN direction.
+ */
+#define USBHSD_INTSTAT_EP3IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK)
+#define USBHSD_INTSTAT_EP4OUT_MASK               (0x100U)
+#define USBHSD_INTSTAT_EP4OUT_SHIFT              (8U)
+/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction.
+ */
+#define USBHSD_INTSTAT_EP4OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK)
+#define USBHSD_INTSTAT_EP4IN_MASK                (0x200U)
+#define USBHSD_INTSTAT_EP4IN_SHIFT               (9U)
+/*! EP4IN - Interrupt status register bit for the EP4 IN direction.
+ */
+#define USBHSD_INTSTAT_EP4IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK)
+#define USBHSD_INTSTAT_EP5OUT_MASK               (0x400U)
+#define USBHSD_INTSTAT_EP5OUT_SHIFT              (10U)
+/*! EP5OUT - Interrupt status register bit for the EP5 OUT direction.
+ */
+#define USBHSD_INTSTAT_EP5OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK)
+#define USBHSD_INTSTAT_EP5IN_MASK                (0x800U)
+#define USBHSD_INTSTAT_EP5IN_SHIFT               (11U)
+/*! EP5IN - Interrupt status register bit for the EP5 IN direction.
+ */
+#define USBHSD_INTSTAT_EP5IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK)
+#define USBHSD_INTSTAT_FRAME_INT_MASK            (0x40000000U)
+#define USBHSD_INTSTAT_FRAME_INT_SHIFT           (30U)
+/*! FRAME_INT - Frame interrupt.
+ */
+#define USBHSD_INTSTAT_FRAME_INT(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK)
+#define USBHSD_INTSTAT_DEV_INT_MASK              (0x80000000U)
+#define USBHSD_INTSTAT_DEV_INT_SHIFT             (31U)
+/*! DEV_INT - Device status interrupt.
+ */
+#define USBHSD_INTSTAT_DEV_INT(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK)
+/*! @} */
+
+/*! @name INTEN - USB interrupt enable register */
+/*! @{ */
+#define USBHSD_INTEN_EP_INT_EN_MASK              (0xFFFU)
+#define USBHSD_INTEN_EP_INT_EN_SHIFT             (0U)
+/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
+ *    interrupt is generated on the interrupt line.
+ */
+#define USBHSD_INTEN_EP_INT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK)
+#define USBHSD_INTEN_FRAME_INT_EN_MASK           (0x40000000U)
+#define USBHSD_INTEN_FRAME_INT_EN_SHIFT          (30U)
+/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
+ *    interrupt is generated on the interrupt line.
+ */
+#define USBHSD_INTEN_FRAME_INT_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK)
+#define USBHSD_INTEN_DEV_INT_EN_MASK             (0x80000000U)
+#define USBHSD_INTEN_DEV_INT_EN_SHIFT            (31U)
+/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
+ *    interrupt is generated on the interrupt line.
+ */
+#define USBHSD_INTEN_DEV_INT_EN(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK)
+/*! @} */
+
+/*! @name INTSETSTAT - USB set interrupt status register */
+/*! @{ */
+#define USBHSD_INTSETSTAT_EP_SET_INT_MASK        (0xFFFU)
+#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT       (0U)
+/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.
+ */
+#define USBHSD_INTSETSTAT_EP_SET_INT(x)          (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK)
+#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK     (0x40000000U)
+#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT    (30U)
+/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.
+ */
+#define USBHSD_INTSETSTAT_FRAME_SET_INT(x)       (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK)
+#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK       (0x80000000U)
+#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT      (31U)
+/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.
+ */
+#define USBHSD_INTSETSTAT_DEV_SET_INT(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK)
+/*! @} */
+
+/*! @name EPTOGGLE - USB Endpoint toggle register */
+/*! @{ */
+#define USBHSD_EPTOGGLE_TOGGLE_MASK              (0x3FFFFFFFU)
+#define USBHSD_EPTOGGLE_TOGGLE_SHIFT             (0U)
+/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint.
+ */
+#define USBHSD_EPTOGGLE_TOGGLE(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USBHSD_Register_Masks */
+
+
+/* USBHSD - Peripheral instance base addresses */
+/** Peripheral USBHSD base address */
+#define USBHSD_BASE                              (0x40094000u)
+/** Peripheral USBHSD base pointer */
+#define USBHSD                                   ((USBHSD_Type *)USBHSD_BASE)
+/** Array initializer of USBHSD peripheral base addresses */
+#define USBHSD_BASE_ADDRS                        { USBHSD_BASE }
+/** Array initializer of USBHSD peripheral base pointers */
+#define USBHSD_BASE_PTRS                         { USBHSD }
+/** Interrupt vectors for the USBHSD peripheral type */
+#define USBHSD_IRQS                              { USB1_IRQn }
+#define USBHSD_NEEDCLK_IRQS                      { USB1_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBHSD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBHSH Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer
+ * @{
+ */
+
+/** USBHSH - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t CAPLENGTH_CHIPID;                  /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */
+  __I  uint32_t HCSPARAMS;                         /**< Host Controller Structural Parameters, offset: 0x4 */
+  __I  uint32_t HCCPARAMS;                         /**< Host Controller Capability Parameters, offset: 0x8 */
+  __IO uint32_t FLADJ_FRINDEX;                     /**< Frame Length Adjustment, offset: 0xC */
+  __IO uint32_t ATL_PTD_BASE_ADDR;                 /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */
+  __IO uint32_t ISO_PTD_BASE_ADDR;                 /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */
+  __IO uint32_t INT_PTD_BASE_ADDR;                 /**< Memory base address where INT PTD0 is stored, offset: 0x18 */
+  __IO uint32_t DATA_PAYLOAD_BASE_ADDR;            /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */
+  __IO uint32_t USBCMD;                            /**< USB Command register, offset: 0x20 */
+  __IO uint32_t USBSTS;                            /**< USB Interrupt Status register, offset: 0x24 */
+  __IO uint32_t USBINTR;                           /**< USB Interrupt Enable register, offset: 0x28 */
+  __IO uint32_t PORTSC1;                           /**< Port Status and Control register, offset: 0x2C */
+  __IO uint32_t ATL_PTD_DONE_MAP;                  /**< Done map for each ATL PTD, offset: 0x30 */
+  __IO uint32_t ATL_PTD_SKIP_MAP;                  /**< Skip map for each ATL PTD, offset: 0x34 */
+  __IO uint32_t ISO_PTD_DONE_MAP;                  /**< Done map for each ISO PTD, offset: 0x38 */
+  __IO uint32_t ISO_PTD_SKIP_MAP;                  /**< Skip map for each ISO PTD, offset: 0x3C */
+  __IO uint32_t INT_PTD_DONE_MAP;                  /**< Done map for each INT PTD, offset: 0x40 */
+  __IO uint32_t INT_PTD_SKIP_MAP;                  /**< Skip map for each INT PTD, offset: 0x44 */
+  __IO uint32_t LASTPTD;                           /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t PORTMODE;                          /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */
+} USBHSH_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USBHSH Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSH_Register_Masks USBHSH Register Masks
+ * @{
+ */
+
+/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */
+/*! @{ */
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK   (0xFFU)
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT  (0U)
+/*! CAPLENGTH - Capability Length: This is used as an offset.
+ */
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK)
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK      (0xFFFF0000U)
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT     (16U)
+/*! CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major
+ *    revision [23:16] = Minor revision Major revisions used: 0x01: USB2.
+ */
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x)        (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK)
+/*! @} */
+
+/*! @name HCSPARAMS - Host Controller Structural Parameters */
+/*! @{ */
+#define USBHSH_HCSPARAMS_N_PORTS_MASK            (0xFU)
+#define USBHSH_HCSPARAMS_N_PORTS_SHIFT           (0U)
+/*! N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller.
+ */
+#define USBHSH_HCSPARAMS_N_PORTS(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK)
+#define USBHSH_HCSPARAMS_PPC_MASK                (0x10U)
+#define USBHSH_HCSPARAMS_PPC_SHIFT               (4U)
+/*! PPC - This field indicates whether the host controller implementation includes port power control.
+ */
+#define USBHSH_HCSPARAMS_PPC(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK)
+#define USBHSH_HCSPARAMS_P_INDICATOR_MASK        (0x10000U)
+#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT       (16U)
+/*! P_INDICATOR - This bit indicates whether the ports support port indicator control.
+ */
+#define USBHSH_HCSPARAMS_P_INDICATOR(x)          (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK)
+/*! @} */
+
+/*! @name HCCPARAMS - Host Controller Capability Parameters */
+/*! @{ */
+#define USBHSH_HCCPARAMS_LPMC_MASK               (0x20000U)
+#define USBHSH_HCCPARAMS_LPMC_SHIFT              (17U)
+/*! LPMC - Link Power Management Capability.
+ */
+#define USBHSH_HCCPARAMS_LPMC(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK)
+/*! @} */
+
+/*! @name FLADJ_FRINDEX - Frame Length Adjustment */
+/*! @{ */
+#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK          (0x3FU)
+#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT         (0U)
+/*! FLADJ - Frame Length Timing Value.
+ */
+#define USBHSH_FLADJ_FRINDEX_FLADJ(x)            (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK)
+#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK        (0x3FFF0000U)
+#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT       (16U)
+/*! FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet.
+ */
+#define USBHSH_FLADJ_FRINDEX_FRINDEX(x)          (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK)
+/*! @} */
+
+/*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */
+/*! @{ */
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK    (0x1F0U)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT   (4U)
+/*! ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list.
+ */
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK   (0xFFFFFE00U)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT  (9U)
+/*! ATL_BASE - Base address to be used by the hardware to find the start of the ATL list.
+ */
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK)
+/*! @} */
+
+/*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */
+/*! @{ */
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK  (0x3E0U)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U)
+/*! ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list.
+ */
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x)    (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK   (0xFFFFFC00U)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT  (10U)
+/*! ISO_BASE - Base address to be used by the hardware to find the start of the ISO list.
+ */
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK)
+/*! @} */
+
+/*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */
+/*! @{ */
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK  (0x3E0U)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U)
+/*! INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list.
+ */
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x)    (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK   (0xFFFFFC00U)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT  (10U)
+/*! INT_BASE - Base address to be used by the hardware to find the start of the INT list.
+ */
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK)
+/*! @} */
+
+/*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */
+/*! @{ */
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U)
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U)
+/*! DAT_BASE - Base address to be used by the hardware to find the start of the data payload section.
+ */
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK)
+/*! @} */
+
+/*! @name USBCMD - USB Command register */
+/*! @{ */
+#define USBHSH_USBCMD_RS_MASK                    (0x1U)
+#define USBHSH_USBCMD_RS_SHIFT                   (0U)
+/*! RS - Run/Stop: 1b = Run.
+ */
+#define USBHSH_USBCMD_RS(x)                      (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK)
+#define USBHSH_USBCMD_HCRESET_MASK               (0x2U)
+#define USBHSH_USBCMD_HCRESET_SHIFT              (1U)
+/*! HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller.
+ */
+#define USBHSH_USBCMD_HCRESET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK)
+#define USBHSH_USBCMD_FLS_MASK                   (0xCU)
+#define USBHSH_USBCMD_FLS_SHIFT                  (2U)
+/*! FLS - Frame List Size: This field specifies the size of the frame list.
+ */
+#define USBHSH_USBCMD_FLS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK)
+#define USBHSH_USBCMD_LHCR_MASK                  (0x80U)
+#define USBHSH_USBCMD_LHCR_SHIFT                 (7U)
+/*! LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host
+ *    controller without affecting the state of the ports.
+ */
+#define USBHSH_USBCMD_LHCR(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK)
+#define USBHSH_USBCMD_ATL_EN_MASK                (0x100U)
+#define USBHSH_USBCMD_ATL_EN_SHIFT               (8U)
+/*! ATL_EN - ATL List enabled.
+ */
+#define USBHSH_USBCMD_ATL_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK)
+#define USBHSH_USBCMD_ISO_EN_MASK                (0x200U)
+#define USBHSH_USBCMD_ISO_EN_SHIFT               (9U)
+/*! ISO_EN - ISO List enabled.
+ */
+#define USBHSH_USBCMD_ISO_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK)
+#define USBHSH_USBCMD_INT_EN_MASK                (0x400U)
+#define USBHSH_USBCMD_INT_EN_SHIFT               (10U)
+/*! INT_EN - INT List enabled.
+ */
+#define USBHSH_USBCMD_INT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK)
+#define USBHSH_USBCMD_HIRD_MASK                  (0xF000000U)
+#define USBHSH_USBCMD_HIRD_SHIFT                 (24U)
+/*! HIRD - Host-Initiated Resume Duration.
+ */
+#define USBHSH_USBCMD_HIRD(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK)
+/*! @} */
+
+/*! @name USBSTS - USB Interrupt Status register */
+/*! @{ */
+#define USBHSH_USBSTS_PCD_MASK                   (0x4U)
+#define USBHSH_USBSTS_PCD_SHIFT                  (2U)
+/*! PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a
+ *    change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a
+ *    result of a J-K transition detected on a suspended port.
+ */
+#define USBHSH_USBSTS_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK)
+#define USBHSH_USBSTS_FLR_MASK                   (0x8U)
+#define USBHSH_USBSTS_FLR_SHIFT                  (3U)
+/*! FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list
+ *    index rolls over its maximum value to 0.
+ */
+#define USBHSH_USBSTS_FLR(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK)
+#define USBHSH_USBSTS_ATL_IRQ_MASK               (0x10000U)
+#define USBHSH_USBSTS_ATL_IRQ_SHIFT              (16U)
+/*! ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed.
+ */
+#define USBHSH_USBSTS_ATL_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK)
+#define USBHSH_USBSTS_ISO_IRQ_MASK               (0x20000U)
+#define USBHSH_USBSTS_ISO_IRQ_SHIFT              (17U)
+/*! ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed.
+ */
+#define USBHSH_USBSTS_ISO_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK)
+#define USBHSH_USBSTS_INT_IRQ_MASK               (0x40000U)
+#define USBHSH_USBSTS_INT_IRQ_SHIFT              (18U)
+/*! INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed.
+ */
+#define USBHSH_USBSTS_INT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK)
+#define USBHSH_USBSTS_SOF_IRQ_MASK               (0x80000U)
+#define USBHSH_USBSTS_SOF_IRQ_SHIFT              (19U)
+/*! SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set.
+ */
+#define USBHSH_USBSTS_SOF_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK)
+/*! @} */
+
+/*! @name USBINTR - USB Interrupt Enable register */
+/*! @{ */
+#define USBHSH_USBINTR_PCDE_MASK                 (0x4U)
+#define USBHSH_USBINTR_PCDE_SHIFT                (2U)
+/*! PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable.
+ */
+#define USBHSH_USBINTR_PCDE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK)
+#define USBHSH_USBINTR_FLRE_MASK                 (0x8U)
+#define USBHSH_USBINTR_FLRE_SHIFT                (3U)
+/*! FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable.
+ */
+#define USBHSH_USBINTR_FLRE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK)
+#define USBHSH_USBINTR_ATL_IRQ_E_MASK            (0x10000U)
+#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT           (16U)
+/*! ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable.
+ */
+#define USBHSH_USBINTR_ATL_IRQ_E(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK)
+#define USBHSH_USBINTR_ISO_IRQ_E_MASK            (0x20000U)
+#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT           (17U)
+/*! ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable.
+ */
+#define USBHSH_USBINTR_ISO_IRQ_E(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK)
+#define USBHSH_USBINTR_INT_IRQ_E_MASK            (0x40000U)
+#define USBHSH_USBINTR_INT_IRQ_E_SHIFT           (18U)
+/*! INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable.
+ */
+#define USBHSH_USBINTR_INT_IRQ_E(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK)
+#define USBHSH_USBINTR_SOF_E_MASK                (0x80000U)
+#define USBHSH_USBINTR_SOF_E_SHIFT               (19U)
+/*! SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable.
+ */
+#define USBHSH_USBINTR_SOF_E(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK)
+/*! @} */
+
+/*! @name PORTSC1 - Port Status and Control register */
+/*! @{ */
+#define USBHSH_PORTSC1_CCS_MASK                  (0x1U)
+#define USBHSH_PORTSC1_CCS_SHIFT                 (0U)
+/*! CCS - Current Connect Status: Logic 1 indicates a device is present on the port.
+ */
+#define USBHSH_PORTSC1_CCS(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK)
+#define USBHSH_PORTSC1_CSC_MASK                  (0x2U)
+#define USBHSH_PORTSC1_CSC_SHIFT                 (1U)
+/*! CSC - Connect Status Change: Logic 1 means that the value of CCS has changed.
+ */
+#define USBHSH_PORTSC1_CSC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK)
+#define USBHSH_PORTSC1_PED_MASK                  (0x4U)
+#define USBHSH_PORTSC1_PED_SHIFT                 (2U)
+/*! PED - Port Enabled/Disabled.
+ */
+#define USBHSH_PORTSC1_PED(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK)
+#define USBHSH_PORTSC1_PEDC_MASK                 (0x8U)
+#define USBHSH_PORTSC1_PEDC_SHIFT                (3U)
+/*! PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed.
+ */
+#define USBHSH_PORTSC1_PEDC(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK)
+#define USBHSH_PORTSC1_OCA_MASK                  (0x10U)
+#define USBHSH_PORTSC1_OCA_SHIFT                 (4U)
+/*! OCA - Over-current active: Logic 1 means that this port has an over-current condition.
+ */
+#define USBHSH_PORTSC1_OCA(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK)
+#define USBHSH_PORTSC1_OCC_MASK                  (0x20U)
+#define USBHSH_PORTSC1_OCC_SHIFT                 (5U)
+/*! OCC - Over-current change: Logic 1 means that the value of OCA has changed.
+ */
+#define USBHSH_PORTSC1_OCC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK)
+#define USBHSH_PORTSC1_FPR_MASK                  (0x40U)
+#define USBHSH_PORTSC1_FPR_SHIFT                 (6U)
+/*! FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port.
+ */
+#define USBHSH_PORTSC1_FPR(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK)
+#define USBHSH_PORTSC1_SUSP_MASK                 (0x80U)
+#define USBHSH_PORTSC1_SUSP_SHIFT                (7U)
+/*! SUSP - Suspend: Logic 1 means port is in the suspend state.
+ */
+#define USBHSH_PORTSC1_SUSP(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK)
+#define USBHSH_PORTSC1_PR_MASK                   (0x100U)
+#define USBHSH_PORTSC1_PR_SHIFT                  (8U)
+/*! PR - Port Reset: Logic 1 means the port is in the reset state.
+ */
+#define USBHSH_PORTSC1_PR(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK)
+#define USBHSH_PORTSC1_SUS_L1_MASK               (0x200U)
+#define USBHSH_PORTSC1_SUS_L1_SHIFT              (9U)
+/*! SUS_L1 - Suspend using L1 0b = Suspend using L2 1b = Suspend using L1 When this bit is set to a
+ *    1 and a non-zero value is specified in the Device Address field, the host controller will
+ *    generate an LPM Token to enter the L1 state whenever software writes a one to the Suspend bit, as
+ *    well as L1 exit timing during any device or host-initiated resume.
+ */
+#define USBHSH_PORTSC1_SUS_L1(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK)
+#define USBHSH_PORTSC1_LS_MASK                   (0xC00U)
+#define USBHSH_PORTSC1_LS_SHIFT                  (10U)
+/*! LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines.
+ */
+#define USBHSH_PORTSC1_LS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK)
+#define USBHSH_PORTSC1_PP_MASK                   (0x1000U)
+#define USBHSH_PORTSC1_PP_SHIFT                  (12U)
+/*! PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register.
+ */
+#define USBHSH_PORTSC1_PP(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK)
+#define USBHSH_PORTSC1_PIC_MASK                  (0xC000U)
+#define USBHSH_PORTSC1_PIC_SHIFT                 (14U)
+/*! PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the
+ *    HCSPARAMS register is logic 0.
+ */
+#define USBHSH_PORTSC1_PIC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK)
+#define USBHSH_PORTSC1_PTC_MASK                  (0xF0000U)
+#define USBHSH_PORTSC1_PTC_SHIFT                 (16U)
+/*! PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value.
+ */
+#define USBHSH_PORTSC1_PTC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK)
+#define USBHSH_PORTSC1_PSPD_MASK                 (0x300000U)
+#define USBHSH_PORTSC1_PSPD_SHIFT                (20U)
+/*! PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved.
+ */
+#define USBHSH_PORTSC1_PSPD(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK)
+#define USBHSH_PORTSC1_WOO_MASK                  (0x400000U)
+#define USBHSH_PORTSC1_WOO_SHIFT                 (22U)
+/*! WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to
+ *    overcurrent conditions as wake-up events.
+ */
+#define USBHSH_PORTSC1_WOO(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK)
+#define USBHSH_PORTSC1_SUS_STAT_MASK             (0x1800000U)
+#define USBHSH_PORTSC1_SUS_STAT_SHIFT            (23U)
+/*! SUS_STAT - These two bits are used by software to determine whether the most recent L1 suspend
+ *    request was successful: 00b: Success-state transition was successful (ACK) 01b: Not Yet -
+ *    Device was unable to enter the L1 state at this time (NYET) 10b: Not supported - Device does not
+ *    support the L1 state (STALL) 11b: Timeout/Error - Device failed to respond or an error occurred.
+ */
+#define USBHSH_PORTSC1_SUS_STAT(x)               (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK)
+#define USBHSH_PORTSC1_DEV_ADD_MASK              (0xFE000000U)
+#define USBHSH_PORTSC1_DEV_ADD_SHIFT             (25U)
+/*! DEV_ADD - Device Address for LPM tokens.
+ */
+#define USBHSH_PORTSC1_DEV_ADD(x)                (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK)
+/*! @} */
+
+/*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */
+/*! @{ */
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK    (0xFFFFFFFFU)
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT   (0U)
+/*! ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
+ */
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK)
+/*! @} */
+
+/*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */
+/*! @{ */
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK    (0xFFFFFFFFU)
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT   (0U)
+/*! ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be
+ *    skipped, independent of the V bit setting.
+ */
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK)
+/*! @} */
+
+/*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */
+/*! @{ */
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK    (0xFFFFFFFFU)
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT   (0U)
+/*! ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
+ */
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK)
+/*! @} */
+
+/*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */
+/*! @{ */
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK    (0xFFFFFFFFU)
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT   (0U)
+/*! ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
+ */
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK)
+/*! @} */
+
+/*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */
+/*! @{ */
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK    (0xFFFFFFFFU)
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT   (0U)
+/*! INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
+ */
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK)
+/*! @} */
+
+/*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */
+/*! @{ */
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK    (0xFFFFFFFFU)
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT   (0U)
+/*! INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be
+ *    skipped, independent of the V bit setting.
+ */
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK)
+/*! @} */
+
+/*! @name LASTPTD - Marks the last PTD in the list for ISO, INT and ATL */
+/*! @{ */
+#define USBHSH_LASTPTD_ATL_LAST_MASK             (0x1FU)
+#define USBHSH_LASTPTD_ATL_LAST_SHIFT            (0U)
+/*! ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed.
+ */
+#define USBHSH_LASTPTD_ATL_LAST(x)               (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ATL_LAST_SHIFT)) & USBHSH_LASTPTD_ATL_LAST_MASK)
+#define USBHSH_LASTPTD_ISO_LAST_MASK             (0x1F00U)
+#define USBHSH_LASTPTD_ISO_LAST_SHIFT            (8U)
+/*! ISO_LAST - This indicates the last PTD in the ISO list.
+ */
+#define USBHSH_LASTPTD_ISO_LAST(x)               (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ISO_LAST_SHIFT)) & USBHSH_LASTPTD_ISO_LAST_MASK)
+#define USBHSH_LASTPTD_INT_LAST_MASK             (0x1F0000U)
+#define USBHSH_LASTPTD_INT_LAST_SHIFT            (16U)
+/*! INT_LAST - This indicates the last PTD in the INT list.
+ */
+#define USBHSH_LASTPTD_INT_LAST(x)               (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_INT_LAST_SHIFT)) & USBHSH_LASTPTD_INT_LAST_MASK)
+/*! @} */
+
+/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
+/*! @{ */
+#define USBHSH_PORTMODE_ID0_MASK                 (0x1U)
+#define USBHSH_PORTMODE_ID0_SHIFT                (0U)
+/*! ID0 - Port 0 ID pin value.
+ */
+#define USBHSH_PORTMODE_ID0(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK)
+#define USBHSH_PORTMODE_ID0_EN_MASK              (0x100U)
+#define USBHSH_PORTMODE_ID0_EN_SHIFT             (8U)
+/*! ID0_EN - Port 0 ID pin pull-up enable.
+ */
+#define USBHSH_PORTMODE_ID0_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK)
+#define USBHSH_PORTMODE_DEV_ENABLE_MASK          (0x10000U)
+#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT         (16U)
+/*! DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device.
+ */
+#define USBHSH_PORTMODE_DEV_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK)
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK       (0x40000U)
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT      (18U)
+/*! SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware.
+ */
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x)         (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK)
+#define USBHSH_PORTMODE_SW_PDCOM_MASK            (0x80000U)
+#define USBHSH_PORTMODE_SW_PDCOM_SHIFT           (19U)
+/*! SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b.
+ */
+#define USBHSH_PORTMODE_SW_PDCOM(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USBHSH_Register_Masks */
+
+
+/* USBHSH - Peripheral instance base addresses */
+/** Peripheral USBHSH base address */
+#define USBHSH_BASE                              (0x400A3000u)
+/** Peripheral USBHSH base pointer */
+#define USBHSH                                   ((USBHSH_Type *)USBHSH_BASE)
+/** Array initializer of USBHSH peripheral base addresses */
+#define USBHSH_BASE_ADDRS                        { USBHSH_BASE }
+/** Array initializer of USBHSH peripheral base pointers */
+#define USBHSH_BASE_PTRS                         { USBHSH }
+/** Interrupt vectors for the USBHSH peripheral type */
+#define USBHSH_IRQS                              { USB1_IRQn }
+#define USBHSH_NEEDCLK_IRQS                      { USB1_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBHSH_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UTICK Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
+ * @{
+ */
+
+/** UTICK - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< Control register., offset: 0x0 */
+  __IO uint32_t STAT;                              /**< Status register., offset: 0x4 */
+  __IO uint32_t CFG;                               /**< Capture configuration register., offset: 0x8 */
+  __O  uint32_t CAPCLR;                            /**< Capture clear register., offset: 0xC */
+  __I  uint32_t CAP[4];                            /**< Capture register ., array offset: 0x10, array step: 0x4 */
+} UTICK_Type;
+
+/* ----------------------------------------------------------------------------
+   -- UTICK Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UTICK_Register_Masks UTICK Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control register. */
+/*! @{ */
+#define UTICK_CTRL_DELAYVAL_MASK                 (0x7FFFFFFFU)
+#define UTICK_CTRL_DELAYVAL_SHIFT                (0U)
+/*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer
+ *    clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer.
+ */
+#define UTICK_CTRL_DELAYVAL(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
+#define UTICK_CTRL_REPEAT_MASK                   (0x80000000U)
+#define UTICK_CTRL_REPEAT_SHIFT                  (31U)
+/*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously.
+ */
+#define UTICK_CTRL_REPEAT(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
+/*! @} */
+
+/*! @name STAT - Status register. */
+/*! @{ */
+#define UTICK_STAT_INTR_MASK                     (0x1U)
+#define UTICK_STAT_INTR_SHIFT                    (0U)
+/*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any
+ *    value to this register clears this flag.
+ */
+#define UTICK_STAT_INTR(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
+#define UTICK_STAT_ACTIVE_MASK                   (0x2U)
+#define UTICK_STAT_ACTIVE_SHIFT                  (1U)
+/*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active.
+ */
+#define UTICK_STAT_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
+/*! @} */
+
+/*! @name CFG - Capture configuration register. */
+/*! @{ */
+#define UTICK_CFG_CAPEN0_MASK                    (0x1U)
+#define UTICK_CFG_CAPEN0_SHIFT                   (0U)
+/*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled.
+ */
+#define UTICK_CFG_CAPEN0(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
+#define UTICK_CFG_CAPEN1_MASK                    (0x2U)
+#define UTICK_CFG_CAPEN1_SHIFT                   (1U)
+/*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled.
+ */
+#define UTICK_CFG_CAPEN1(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
+#define UTICK_CFG_CAPEN2_MASK                    (0x4U)
+#define UTICK_CFG_CAPEN2_SHIFT                   (2U)
+/*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled.
+ */
+#define UTICK_CFG_CAPEN2(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
+#define UTICK_CFG_CAPEN3_MASK                    (0x8U)
+#define UTICK_CFG_CAPEN3_SHIFT                   (3U)
+/*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled.
+ */
+#define UTICK_CFG_CAPEN3(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
+#define UTICK_CFG_CAPPOL0_MASK                   (0x100U)
+#define UTICK_CFG_CAPPOL0_SHIFT                  (8U)
+/*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture.
+ */
+#define UTICK_CFG_CAPPOL0(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
+#define UTICK_CFG_CAPPOL1_MASK                   (0x200U)
+#define UTICK_CFG_CAPPOL1_SHIFT                  (9U)
+/*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture.
+ */
+#define UTICK_CFG_CAPPOL1(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
+#define UTICK_CFG_CAPPOL2_MASK                   (0x400U)
+#define UTICK_CFG_CAPPOL2_SHIFT                  (10U)
+/*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture.
+ */
+#define UTICK_CFG_CAPPOL2(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
+#define UTICK_CFG_CAPPOL3_MASK                   (0x800U)
+#define UTICK_CFG_CAPPOL3_SHIFT                  (11U)
+/*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture.
+ */
+#define UTICK_CFG_CAPPOL3(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
+/*! @} */
+
+/*! @name CAPCLR - Capture clear register. */
+/*! @{ */
+#define UTICK_CAPCLR_CAPCLR0_MASK                (0x1U)
+#define UTICK_CAPCLR_CAPCLR0_SHIFT               (0U)
+/*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value.
+ */
+#define UTICK_CAPCLR_CAPCLR0(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
+#define UTICK_CAPCLR_CAPCLR1_MASK                (0x2U)
+#define UTICK_CAPCLR_CAPCLR1_SHIFT               (1U)
+/*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value.
+ */
+#define UTICK_CAPCLR_CAPCLR1(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
+#define UTICK_CAPCLR_CAPCLR2_MASK                (0x4U)
+#define UTICK_CAPCLR_CAPCLR2_SHIFT               (2U)
+/*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value.
+ */
+#define UTICK_CAPCLR_CAPCLR2(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
+#define UTICK_CAPCLR_CAPCLR3_MASK                (0x8U)
+#define UTICK_CAPCLR_CAPCLR3_SHIFT               (3U)
+/*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value.
+ */
+#define UTICK_CAPCLR_CAPCLR3(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
+/*! @} */
+
+/*! @name CAP - Capture register . */
+/*! @{ */
+#define UTICK_CAP_CAP_VALUE_MASK                 (0x7FFFFFFFU)
+#define UTICK_CAP_CAP_VALUE_SHIFT                (0U)
+/*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower
+ *    than the actual value of the Micro-tick Timer at the moment of the capture event.
+ */
+#define UTICK_CAP_CAP_VALUE(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
+#define UTICK_CAP_VALID_MASK                     (0x80000000U)
+#define UTICK_CAP_VALID_SHIFT                    (31U)
+/*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related
+ *    UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register.
+ */
+#define UTICK_CAP_VALID(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
+/*! @} */
+
+/* The count of UTICK_CAP */
+#define UTICK_CAP_COUNT                          (4U)
+
+
+/*!
+ * @}
+ */ /* end of group UTICK_Register_Masks */
+
+
+/* UTICK - Peripheral instance base addresses */
+/** Peripheral UTICK0 base address */
+#define UTICK0_BASE                              (0x4000E000u)
+/** Peripheral UTICK0 base pointer */
+#define UTICK0                                   ((UTICK_Type *)UTICK0_BASE)
+/** Array initializer of UTICK peripheral base addresses */
+#define UTICK_BASE_ADDRS                         { UTICK0_BASE }
+/** Array initializer of UTICK peripheral base pointers */
+#define UTICK_BASE_PTRS                          { UTICK0 }
+/** Interrupt vectors for the UTICK peripheral type */
+#define UTICK_IRQS                               { UTICK0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group UTICK_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WWDT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
+ * @{
+ */
+
+/** WWDT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MOD;                               /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */
+  __IO uint32_t TC;                                /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */
+  __O  uint32_t FEED;                              /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */
+  __I  uint32_t TV;                                /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t WARNINT;                           /**< Watchdog Warning Interrupt compare value., offset: 0x14 */
+  __IO uint32_t WINDOW;                            /**< Watchdog Window compare value., offset: 0x18 */
+} WWDT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- WWDT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WWDT_Register_Masks WWDT Register Masks
+ * @{
+ */
+
+/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
+/*! @{ */
+#define WWDT_MOD_WDEN_MASK                       (0x1U)
+#define WWDT_MOD_WDEN_SHIFT                      (0U)
+/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the
+ *    watchdog timer will run permanently.
+ *  0b0..Stop. The watchdog timer is stopped.
+ *  0b1..Run. The watchdog timer is running.
+ */
+#define WWDT_MOD_WDEN(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
+#define WWDT_MOD_WDRESET_MASK                    (0x2U)
+#define WWDT_MOD_WDRESET_SHIFT                   (1U)
+/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0.
+ *  0b0..Interrupt. A watchdog time-out will not cause a chip reset.
+ *  0b1..Reset. A watchdog time-out will cause a chip reset.
+ */
+#define WWDT_MOD_WDRESET(x)                      (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
+#define WWDT_MOD_WDTOF_MASK                      (0x4U)
+#define WWDT_MOD_WDTOF_SHIFT                     (2U)
+/*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by
+ *    events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a
+ *    chip reset if WDRESET = 1.
+ */
+#define WWDT_MOD_WDTOF(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
+#define WWDT_MOD_WDINT_MASK                      (0x8U)
+#define WWDT_MOD_WDINT_SHIFT                     (3U)
+/*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT.
+ *    Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the
+ *    WARNINT value is equal to the value of the TV register. This can occur if the value of
+ *    WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0.
+ */
+#define WWDT_MOD_WDINT(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
+#define WWDT_MOD_WDPROTECT_MASK                  (0x10U)
+#define WWDT_MOD_WDPROTECT_SHIFT                 (4U)
+/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset.
+ *  0b0..Flexible. The watchdog time-out value (TC) can be changed at any time.
+ *  0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.
+ */
+#define WWDT_MOD_WDPROTECT(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
+#define WWDT_MOD_LOCK_MASK                       (0x20U)
+#define WWDT_MOD_LOCK_SHIFT                      (5U)
+/*! LOCK - Once this bit is set to one and a watchdog feed is performed, disabling or powering down
+ *    the watchdog oscillator is prevented by hardware. This bit can be set once by software and is
+ *    only cleared by any reset.
+ */
+#define WWDT_MOD_LOCK(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
+/*! @} */
+
+/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */
+/*! @{ */
+#define WWDT_TC_COUNT_MASK                       (0xFFFFFFU)
+#define WWDT_TC_COUNT_SHIFT                      (0U)
+/*! COUNT - Watchdog time-out value.
+ */
+#define WWDT_TC_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
+/*! @} */
+
+/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */
+/*! @{ */
+#define WWDT_FEED_FEED_MASK                      (0xFFU)
+#define WWDT_FEED_FEED_SHIFT                     (0U)
+/*! FEED - Feed value should be 0xAA followed by 0x55.
+ */
+#define WWDT_FEED_FEED(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
+/*! @} */
+
+/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
+/*! @{ */
+#define WWDT_TV_COUNT_MASK                       (0xFFFFFFU)
+#define WWDT_TV_COUNT_SHIFT                      (0U)
+/*! COUNT - Counter timer value.
+ */
+#define WWDT_TV_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
+/*! @} */
+
+/*! @name WARNINT - Watchdog Warning Interrupt compare value. */
+/*! @{ */
+#define WWDT_WARNINT_WARNINT_MASK                (0x3FFU)
+#define WWDT_WARNINT_WARNINT_SHIFT               (0U)
+/*! WARNINT - Watchdog warning interrupt compare value.
+ */
+#define WWDT_WARNINT_WARNINT(x)                  (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
+/*! @} */
+
+/*! @name WINDOW - Watchdog Window compare value. */
+/*! @{ */
+#define WWDT_WINDOW_WINDOW_MASK                  (0xFFFFFFU)
+#define WWDT_WINDOW_WINDOW_SHIFT                 (0U)
+/*! WINDOW - Watchdog window value.
+ */
+#define WWDT_WINDOW_WINDOW(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group WWDT_Register_Masks */
+
+
+/* WWDT - Peripheral instance base addresses */
+/** Peripheral WWDT base address */
+#define WWDT_BASE                                (0x4000C000u)
+/** Peripheral WWDT base pointer */
+#define WWDT                                     ((WWDT_Type *)WWDT_BASE)
+/** Array initializer of WWDT peripheral base addresses */
+#define WWDT_BASE_ADDRS                          { WWDT_BASE }
+/** Array initializer of WWDT peripheral base pointers */
+#define WWDT_BASE_PTRS                           { WWDT }
+/** Interrupt vectors for the WWDT peripheral type */
+#define WWDT_IRQS                                { WDT_BOD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group WWDT_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header
+  #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDK Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+/** EMC CS base address */
+#define EMC_CS0_BASE                                (0x80000000u)
+#define EMC_CS1_BASE                                (0x88000000u)
+#define EMC_CS2_BASE                                (0x90000000u)
+#define EMC_CS3_BASE                                (0x98000000u)
+#define EMC_DYCS0_BASE                              (0xA0000000u)
+#define EMC_DYCS1_BASE                              (0xA8000000u)
+#define EMC_DYCS2_BASE                              (0xB0000000u)
+#define EMC_DYCS3_BASE                              (0xB8000000u)
+#define EMC_CS_ADDRESS                              {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE}
+#define EMC_DYCS_ADDRESS                            {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE}
+
+/** OTP API */
+typedef struct {
+  uint32_t (*otpInit)(void);                                    /** Initializes OTP controller */
+  uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask);        /** Unlock one or more OTP banks for write access */
+  uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask);       /** Lock one or more OTP banks for write access */
+  uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,
+                                          uint32_t lockWrite);  /** Locks or unlocks write access to a register of an OTP bank and the write lock */
+  uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,
+                                         uint32_t lockWrite);   /** Locks or unlocks read access to a register of an OTP bank and the write lock */
+  uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value);  /** Program a single register in an OTP bank */
+  uint32_t RESERVED_0[5];
+  uint32_t (*rngRead)(void);                                    /** Returns 32-bit number from hardware random number generator */
+  uint32_t (*otpGetDriverVersion)(void);                        /** Returns the version of the OTP driver in ROM */
+} OTP_API_Type;
+
+/** SRAMX and SRAM0 base address */
+#define SRAMX_BASE                                (0x00000000u)
+#define SRAMX_SIZE                                (0x00030000u)
+#define SRAM0_BASE                                (0x20000000u)
+#define SRAM0_SIZE                                (0x00010000u)
+
+/** ROM API */
+typedef struct {
+  __I uint32_t usbdApiBase;                      /** USB API Base */
+      uint32_t RESERVED_0[13];
+  __I OTP_API_Type *otpApiBase;                  /** OTP API Base */
+  __I uint32_t aesApiBase;                       /** AES API Base */
+  __I uint32_t secureApiBase;                    /** Secure API Base */
+} ROM_API_Type;
+
+/** ROM API base address */
+#define ROM_API_BASE                             (0x03000200u)
+/** ROM API base pointer */
+#define ROM_API                                  (*(ROM_API_Type**) ROM_API_BASE)
+/** OTP API base pointer */
+#define OTP_API                                  (ROM_API->otpApiBase)
+
+/** Used for selecting the address of FROHF setting API in ROM */
+#define FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION 1U
+#define FSL_ROM_VERSION_0A 0U
+#define FSL_ROM_VERSION_1B 1U
+#define FSL_ROM_VERSION_0A_FRO_SETTING_ADDR 0x03007933U
+#define FSL_ROM_VERSION_1B_FRO_SETTING_ADDR 0x03008D9BU
+
+/*!
+ * @brief Get the chip value.
+ *
+ * @return chip version, 0x0: 0A version chip, 0x1: 1B version chip, 0xFF: invalid version.
+ */
+static inline uint32_t Chip_GetVersion(void)
+{
+    uint8_t romVersion = 0U;
+    uint32_t command[5] = {0U}, result[4] = {0U};
+    uint32_t syscon_iap_entry_location = 0x03000205;
+
+    command[0] = 55U;
+    result[0]  = 0;
+    result[1]  = 0;
+    ((void (*)(uint32_t cmd[5], uint32_t stat[4]))syscon_iap_entry_location)(command, result);
+
+    romVersion = (uint8_t)(result[1]);
+
+    if (0U == result[0])
+    {
+       if (romVersion == FSL_ROM_VERSION_1B)
+       {
+          return FSL_ROM_VERSION_1B;
+       }
+       else if (romVersion == FSL_ROM_VERSION_0A)
+       {
+          return FSL_ROM_VERSION_0A;
+       }
+       else
+       {
+          return 0xFF;
+       }
+    }
+    else
+    {
+       return 0xFF;
+    }
+}
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif  /* _LPC54005_H_ */
+
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/LPC54005_features.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/LPC54005_features.h
new file mode 100644
index 000000000..95a15204b
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/LPC54005_features.h
@@ -0,0 +1,342 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.2, 2017-06-08
+**     Build:               b191206
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2019 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**     - rev. 1.2 (2017-06-08)
+**         Remove RTC_CTRL_RTC_OSC_BYPASS.
+**         SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
+**         Remove RESET and HALT from SYSCON_AHBCLKDIV.
+**
+** ###################################################################
+*/
+
+#ifndef _LPC54005_FEATURES_H_
+#define _LPC54005_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief ADC availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC_COUNT (1)
+/* @brief ASYNC_SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief CTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (1)
+/* @brief DMIC availability on the SoC. */
+#define FSL_FEATURE_SOC_DMIC_COUNT (1)
+/* @brief EMC availability on the SoC. */
+#define FSL_FEATURE_SOC_EMC_COUNT (1)
+/* @brief FLEXCOMM availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (11)
+/* @brief GINT availability on the SoC. */
+#define FSL_FEATURE_SOC_GINT_COUNT (2)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (1)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (10)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (2)
+/* @brief INPUTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief IOCON availability on the SoC. */
+#define FSL_FEATURE_SOC_IOCON_COUNT (1)
+/* @brief MRT availability on the SoC. */
+#define FSL_FEATURE_SOC_MRT_COUNT (1)
+/* @brief PINT availability on the SoC. */
+#define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief RIT availability on the SoC. */
+#define FSL_FEATURE_SOC_RIT_COUNT (1)
+/* @brief LPC_RNG availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_RNG_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCT availability on the SoC. */
+#define FSL_FEATURE_SOC_SCT_COUNT (1)
+/* @brief SDIF availability on the SoC. */
+#define FSL_FEATURE_SOC_SDIF_COUNT (1)
+/* @brief SHA availability on the SoC. */
+#define FSL_FEATURE_SOC_SHA_COUNT (1)
+/* @brief SMARTCARD availability on the SoC. */
+#define FSL_FEATURE_SOC_SMARTCARD_COUNT (2)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (11)
+/* @brief SPIFI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
+/* @brief SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_USART_COUNT (10)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (1)
+/* @brief USBFSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
+/* @brief USBHSD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
+/* @brief USBHSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
+/* @brief UTICK availability on the SoC. */
+#define FSL_FEATURE_SOC_UTICK_COUNT (1)
+/* @brief WWDT availability on the SoC. */
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)
+
+/* ADC module features */
+
+/* @brief Do not has input select (register INSEL). */
+#define FSL_FEATURE_ADC_HAS_NO_INSEL  (0)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0)
+/* @brief Has startup register. */
+#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1)
+/* @brief Has ADTrim register */
+#define FSL_FEATURE_ADC_HAS_TRIM_REG (0)
+/* @brief Has Calibration register. */
+#define FSL_FEATURE_ADC_HAS_CALIB_REG (1)
+
+/* DMA module features */
+
+/* @brief Number of channels */
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
+/* @brief Align size of DMA descriptor */
+#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
+/* @brief DMA head link descriptor table align size */
+#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
+
+/* FLEXCOMM module features */
+
+/* @brief FLEXCOMM0 USART INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_USART_INDEX  (0)
+/* @brief FLEXCOMM0 SPI INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX  (0)
+/* @brief FLEXCOMM0 I2C INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX  (0)
+/* @brief FLEXCOMM1 USART INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_USART_INDEX  (1)
+/* @brief FLEXCOMM1 SPI INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX  (1)
+/* @brief FLEXCOMM1 I2C INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX  (1)
+/* @brief FLEXCOMM2 USART INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_USART_INDEX  (2)
+/* @brief FLEXCOMM2 SPI INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX  (2)
+/* @brief FLEXCOMM2 I2C INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX  (2)
+/* @brief FLEXCOMM3 USART INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_USART_INDEX  (3)
+/* @brief FLEXCOMM3 SPI INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX  (3)
+/* @brief FLEXCOMM3 I2C INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX  (3)
+/* @brief FLEXCOMM4 USART INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_USART_INDEX  (4)
+/* @brief FLEXCOMM4 SPI INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX  (4)
+/* @brief FLEXCOMM4 I2C INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX  (4)
+/* @brief FLEXCOMM5 USART INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_USART_INDEX  (5)
+/* @brief FLEXCOMM5 SPI INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX  (5)
+/* @brief FLEXCOMM5 I2C INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX  (5)
+/* @brief FLEXCOMM6 USART INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_USART_INDEX  (6)
+/* @brief FLEXCOMM6 SPI INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX  (6)
+/* @brief FLEXCOMM6 I2C INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX  (6)
+/* @brief FLEXCOMM7 I2S INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX  (0)
+/* @brief FLEXCOMM7 USART INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_USART_INDEX  (7)
+/* @brief FLEXCOMM7 SPI INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX  (7)
+/* @brief FLEXCOMM7 I2C INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX  (7)
+/* @brief FLEXCOMM7 I2S INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX  (1)
+/* @brief FLEXCOMM4 USART INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_USART_INDEX  (8)
+/* @brief FLEXCOMM4 SPI INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX  (8)
+/* @brief FLEXCOMM4 I2C INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_I2C_INDEX  (8)
+/* @brief FLEXCOMM5 USART INDEX 9 */
+#define FSL_FEATURE_FLEXCOMM9_USART_INDEX  (9)
+/* @brief FLEXCOMM5 SPI INDEX 9 */
+#define FSL_FEATURE_FLEXCOMM9_SPI_INDEX  (9)
+/* @brief FLEXCOMM5 I2C INDEX 9 */
+#define FSL_FEATURE_FLEXCOMM9_I2C_INDEX  (9)
+/* @brief I2S has DMIC interconnection */
+#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \
+    (((x) == FLEXCOMM0) ? (0) : \
+    (((x) == FLEXCOMM1) ? (0) : \
+    (((x) == FLEXCOMM2) ? (0) : \
+    (((x) == FLEXCOMM3) ? (0) : \
+    (((x) == FLEXCOMM4) ? (0) : \
+    (((x) == FLEXCOMM5) ? (0) : \
+    (((x) == FLEXCOMM6) ? (0) : \
+    (((x) == FLEXCOMM7) ? (1) : \
+    (((x) == FLEXCOMM8) ? (0) : \
+    (((x) == FLEXCOMM9) ? (0) : \
+    (((x) == FLEXCOMM10) ? (0) : (-1))))))))))))
+
+/* I2S module features */
+
+/* @brief I2S support dual channel transfer */
+#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
+/* @brief I2S has DMIC interconnection */
+#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION  (1)
+
+/* IOCON module features */
+
+/* @brief Func bit field width */
+#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
+
+/* MRT module features */
+
+/* @brief number of channels. */
+#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS  (4)
+
+/* interrupt module features */
+
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105)
+
+/* PINT module features */
+
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
+
+/* RIT module features */
+
+/* @brief RIT has no reset control */
+#define FSL_FEATURE_RIT_HAS_NO_RESET (1)
+
+/* RTC module features */
+
+/* @brief RTC has no reset control */
+#define FSL_FEATURE_RTC_HAS_NO_RESET (1)
+
+/* SCT module features */
+
+/* @brief Number of events */
+#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)
+/* @brief Number of states */
+#define FSL_FEATURE_SCT_NUMBER_OF_STATES (16)
+/* @brief Number of match capture */
+#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)
+/* @brief Number of outputs */
+#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
+
+/* SDIF module features */
+
+/* @brief FIFO depth, every location is a WORD */
+#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS  (64)
+/* @brief Max DMA buffer size */
+#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE  (4096)
+/* @brief Max source clock in HZ */
+#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK  (52000000)
+
+/* SHA module features */
+
+/* @brief Has dedicated DMA controller. */
+#define FSL_FEATURE_SHA_HAS_MEMADDR_DMA (1)
+
+/* SPIFI module features */
+
+/* @brief SPIFI start address */
+#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000)
+/* @brief SPIFI end address */
+#define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF)
+
+/* SYSCON module features */
+
+/* @brief Pointer to ROM IAP entry functions */
+#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
+
+/* SysTick module features */
+
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
+
+/* USB module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USB version */
+#define FSL_FEATURE_USB_VERSION (200)
+/* @brief Number of the endpoint in USB FS */
+#define FSL_FEATURE_USB_EP_NUM (5)
+
+/* USBFSH module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBFSH_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBFSH version */
+#define FSL_FEATURE_USBFSH_VERSION (200)
+
+/* USBHSD module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBHSD version */
+#define FSL_FEATURE_USBHSD_VERSION (300)
+/* @brief Number of the endpoint in USB HS */
+#define FSL_FEATURE_USBHSD_EP_NUM (6)
+/* @brief Resetting interrupt endpoint resets DATAx sequence to DATA.1 */
+#define FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK (1)
+
+/* USBHSH module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBHSH version */
+#define FSL_FEATURE_USBHSH_VERSION (300)
+
+#endif /* _LPC54005_FEATURES_H_ */
+
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/arm/LPC540xx_MT25QL128.FLM b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/arm/LPC540xx_MT25QL128.FLM
new file mode 100644
index 000000000..491f1a3a6
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/arm/LPC540xx_MT25QL128.FLM
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/arm/LPC540xx_MX25L12835FM2I.FLM b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/arm/LPC540xx_MX25L12835FM2I.FLM
new file mode 100644
index 000000000..a09805964
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/arm/LPC540xx_MX25L12835FM2I.FLM
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/arm/LPC540xx_W25Q128JVFM.FLM b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/arm/LPC540xx_W25Q128JVFM.FLM
new file mode 100644
index 000000000..b11cdfabe
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/arm/LPC540xx_W25Q128JVFM.FLM
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/driver_reset.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/driver_reset.cmake
new file mode 100644
index 000000000..989530f6f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/driver_reset.cmake
@@ -0,0 +1,14 @@
+if(NOT DRIVER_RESET_INCLUDED)
+
+    set(DRIVER_RESET_INCLUDED true CACHE BOOL "driver_reset component is included.")
+
+    target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    )
+
+    target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+        ${CMAKE_CURRENT_LIST_DIR}/.
+    )
+
+
+
+endif()
\ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_clock.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_clock.c
new file mode 100644
index 000000000..1f4d3c062
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_clock.c
@@ -0,0 +1,2817 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 - 2019 , NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_clock.h"
+#include "fsl_power.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.clock"
+#endif
+#define NVALMAX (0x100U)
+#define PVALMAX (0x20U)
+#define MVALMAX (0x8000U)
+
+#define USB_NVALMAX (0x4U)
+#define USB_PVALMAX (0x8U)
+#define USB_MVALMAX (0x100U)
+
+#define PLL_MAX_N_DIV 0x100U
+#define USB_PLL_MAX_N_DIV 0x100U
+
+#define PLL_MDEC_VAL_P (0U)                          /*!<  MDEC is in bits  16 downto 0 */
+#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P) /*!<  NDEC is in bits  9 downto 0 */
+#define PLL_NDEC_VAL_P (0U)                          /*!<  NDEC is in bits  9:0 */
+#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
+#define PLL_PDEC_VAL_P (0U) /*!<  PDEC is in bits 6:0 */
+#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
+
+#define PLL_MIN_CCO_FREQ_MHZ (275000000U)
+#define PLL_MAX_CCO_FREQ_MHZ (550000000U)
+#define PLL_LOWER_IN_LIMIT (4000U) /*!<  Minimum PLL input rate */
+#define PLL_MIN_IN_SSMODE (2000000U)
+#define PLL_MAX_IN_SSMODE (4000000U)
+
+/*!<  Middle of the range values for spread-spectrum */
+#define PLL_SSCG_MF_FREQ_VALUE 4U
+#define PLL_SSCG_MC_COMP_VALUE 2U
+#define PLL_SSCG_MR_DEPTH_VALUE 4U
+#define PLL_SSCG_DITHER_VALUE 0U
+
+/*!<  USB PLL CCO MAX AND MIN FREQ */
+#define USB_PLL_MIN_CCO_FREQ_MHZ (156000000U)
+#define USB_PLL_MAX_CCO_FREQ_MHZ (320000000U)
+#define USB_PLL_LOWER_IN_LIMIT (1000000U) /*!<  Minimum PLL input rate */
+
+#define USB_PLL_MSEL_VAL_P (0U) /*!<  MSEL is in bits  7 downto 0 */
+#define USB_PLL_MSEL_VAL_M (0xFFU)
+#define USB_PLL_PSEL_VAL_P (8U) /*!<  PDEC is in bits 9:8 */
+#define USB_PLL_PSEL_VAL_M (0x3U)
+#define USB_PLL_NSEL_VAL_P (10U) /*!<  NDEC is in bits  11:10 */
+#define USB_PLL_NSEL_VAL_M (0x3U)
+
+/*!<  SWITCH USB POSTDIVIDER FOR REGITSER WRITING */
+#define SWITCH_USB_PSEL(x) \
+    (((x) == 0x0U) ? 0x1U : ((x) == 0x1U) ? 0x02U : ((x) == 0x2U) ? 0x4U : ((x) == 3U) ? 0x8U : 0U)
+
+/*!<  SYS PLL NDEC reg */
+#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M)
+/*!<  SYS PLL PDEC reg */
+#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M)
+/*!<  SYS PLL MDEC reg */
+#define PLL_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_MDEC_VAL_P) & PLL_MDEC_VAL_M)
+
+/*!<  SYS PLL NSEL reg */
+#define USB_PLL_NSEL_VAL_SET(value) (((unsigned long)(value)&USB_PLL_NSEL_VAL_M) << USB_PLL_NSEL_VAL_P)
+/*!<  SYS PLL PSEL reg */
+#define USB_PLL_PSEL_VAL_SET(value) (((unsigned long)(value)&USB_PLL_PSEL_VAL_M) << USB_PLL_PSEL_VAL_P)
+/*!<  SYS PLL MSEL reg */
+#define USB_PLL_MSEL_VAL_SET(value) (((unsigned long)(value)&USB_PLL_MSEL_VAL_M) << USB_PLL_MSEL_VAL_P)
+
+/*!<  FRAC control */
+#define AUDIO_PLL_FRACT_MD_P (0U)
+#define AUDIO_PLL_FRACT_MD_INT_P (15U)
+#define AUDIO_PLL_FRACT_MD_M (0x7FFFUL << AUDIO_PLL_FRACT_MD_P)
+#define AUDIO_PLL_FRACT_MD_INT_M (0x7FUL << AUDIO_PLL_FRACT_MD_INT_P)
+
+#define AUDIO_PLL_MD_FRACT_SET(value) (((unsigned long)(value) << AUDIO_PLL_FRACT_MD_P) & PLL_FRAC_MD_FRACT_M)
+#define AUDIO_PLL_MD_INT_SET(value) (((unsigned long)(value) << AUDIO_PLL_FRACT_MD_INT_P) & AUDIO_PLL_FRACT_MD_INT_M)
+
+/* Saved value of PLL output rate, computed whenever needed to save run-time
+   computation on each call to retrive the PLL rate. */
+static uint32_t s_Pll_Freq;
+static uint32_t s_Usb_Pll_Freq;
+static uint32_t s_Audio_Pll_Freq;
+
+/** External clock rate on the CLKIN pin in Hz. If not used,
+    set this to 0. Otherwise, set it to the exact rate in Hz this pin is
+    being driven at. */
+static const uint32_t g_I2S_Mclk_Freq   = 0U;
+static const uint32_t g_Ext_Clk_Freq    = 12000000U;
+static const uint32_t g_Lcd_Clk_In_Freq = 0U;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/* Find encoded NDEC value for raw N value, max N = NVALMAX */
+static uint32_t pllEncodeN(uint32_t N);
+/* Find decoded N value for raw NDEC value */
+static uint32_t pllDecodeN(uint32_t NDEC);
+/* Find encoded PDEC value for raw P value, max P = PVALMAX */
+static uint32_t pllEncodeP(uint32_t P);
+/* Find decoded P value for raw PDEC value */
+static uint32_t pllDecodeP(uint32_t PDEC);
+/* Find encoded MDEC value for raw M value, max M = MVALMAX */
+static uint32_t pllEncodeM(uint32_t M);
+/* Find decoded M value for raw MDEC value */
+static uint32_t pllDecodeM(uint32_t MDEC);
+/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */
+static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR);
+/* Get predivider (N) from PLL NDEC setting */
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg);
+/* Get postdivider (P) from PLL PDEC setting */
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg);
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg);
+/* Convert the binary to fractional part */
+static double Binary2Fractional(uint32_t binaryPart);
+/* Calculate the powerTimes' power of 2 */
+static uint32_t power2Cal(uint32_t powerTimes);
+/* Get the greatest common divisor */
+static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n);
+/* Set PLL output based on desired output rate */
+static pll_error_t CLOCK_GetPllConfig(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup);
+
+/* Update local PLL rate variable */
+static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup);
+static void CLOCK_GetAudioPLLOutFromSetupUpdate(pll_setup_t *pSetup);
+/*!
+ * @brief Set fro clock frequency.
+ * Due to LPC540xx 0A silicon and LPC540xx 1B silicon have different ROM addresses for set fro
+ * frequency api, so add this api to get rom version.
+ * @param base romVersion pointer to recieve rom version.
+ */
+#if defined(FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION) && \
+    (FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION)
+static uint32_t CLOCK_GetRomVersion(uint8_t *romVersion);
+#endif
+static const uint8_t wdtFreqLookup[32] = {0,  8,  12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41,
+                                          42, 44, 45, 46, 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION) && \
+    (FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION)
+static uint32_t CLOCK_GetRomVersion(uint8_t *romVersion)
+{
+    uint32_t command[5] = {0U}, result[4] = {0U};
+
+    command[0] = 55U;
+    result[0]  = 0;
+    result[1]  = 0;
+    ((void (*)(uint32_t cmd[5], uint32_t stat[4]))FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION)(command, result);
+
+    *romVersion = (uint8_t)(result[1]);
+
+    return result[0];
+}
+#endif
+
+/**
+ * brief
+ *  Initialize the Core clock to given frequency (12, 48 or 96 MHz), this API is implememnt in ROM code.
+ * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed
+ * output is enabled.
+ * Usage: CLOCK_SetupFROClocking(frequency), (frequency must be one of 12, 48 or 96 MHz)
+ *  Note: Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U) before calling this API since this API is
+ * implemented in ROM code and the FROHF TRIM value is stored in OTP
+ *
+ * param froFreq target fro frequency.
+ * return   Nothing
+ */
+
+void CLOCK_SetupFROClocking(uint32_t froFreq)
+{
+    uint32_t froRomAddr = 0U;
+#if defined(FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION) && \
+    (FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION)
+    uint8_t romVersion = 0U;
+
+    if (CLOCK_GetRomVersion(&romVersion) == (uint32_t)kStatus_Success)
+    {
+        if (romVersion == FSL_ROM_VERSION_1B)
+        {
+            froRomAddr = FSL_ROM_VERSION_1B_FRO_SETTING_ADDR;
+        }
+        else
+        {
+            froRomAddr = FSL_ROM_VERSION_0A_FRO_SETTING_ADDR;
+        }
+
+        (*((void (*)(uint32_t funcname))(froRomAddr)))(froFreq);
+    }
+#else
+    froRomAddr = FSL_ROM_VERSION_0A_FRO_SETTING_ADDR;
+
+    (*((void (*)(uint32_t))(froRomAddr)))(froFreq);
+#endif
+}
+
+/* Clock Selection for IP */
+/**
+ * brief        Configure the clock selection muxes.
+ * param        connection      : Clock to be configured.
+ * return       Nothing
+ */
+void CLOCK_AttachClk(clock_attach_id_t connection)
+{
+    uint8_t mux;
+    uint8_t sel;
+    uint16_t item;
+    uint32_t tmp32 = (uint32_t)connection;
+    uint32_t i;
+    volatile uint32_t *pClkSel;
+
+    pClkSel = &(SYSCON->STICKCLKSEL);
+
+    if (kNONE_to_NONE != connection)
+    {
+        for (i = 0U; i < 2U; i++)
+        {
+            if (tmp32 == 0U)
+            {
+                break;
+            }
+            item = (uint16_t)GET_ID_ITEM(tmp32);
+            if (item != 0UL)
+            {
+                mux = GET_ID_ITEM_MUX(item);
+                sel = GET_ID_ITEM_SEL(item);
+                if (mux == CM_ASYNCAPB)
+                {
+                    SYSCON->ASYNCAPBCTRL          = SYSCON_ASYNCAPBCTRL_ENABLE(1);
+                    ASYNC_SYSCON->ASYNCAPBCLKSELA = sel;
+                }
+                else
+                {
+                    ((volatile uint32_t *)pClkSel)[mux] = sel;
+                }
+            }
+            tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */
+        }
+    }
+}
+
+/* Return the actual clock attach id */
+/**
+ * brief   Get the actual clock attach id.
+ * This fuction uses the offset in input attach id, then it reads the actual source value in
+ * the register and combine the offset to obtain an actual attach id.
+ * param   attachId  : Clock attach id to get.
+ * return  Clock source value.
+ */
+clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId)
+{
+    uint8_t mux;
+    uint8_t actualSel;
+    uint32_t tmp32 = (uint32_t)attachId;
+    uint32_t i;
+    uint32_t actualAttachId = 0U;
+    uint32_t selector       = GET_ID_SELECTOR(tmp32);
+    volatile uint32_t *pClkSel;
+
+    pClkSel = &(SYSCON->STICKCLKSEL);
+
+    if (kNONE_to_NONE == attachId)
+    {
+        return kNONE_to_NONE;
+    }
+
+    for (i = 0U; i < 2U; i++)
+    {
+        mux = GET_ID_ITEM_MUX(tmp32);
+        if (tmp32 != 0UL)
+        {
+            if (mux == CM_ASYNCAPB)
+            {
+                actualSel = (uint8_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA);
+            }
+            else
+            {
+                actualSel = (uint8_t)(((volatile uint32_t *)pClkSel)[mux]);
+            }
+
+            /* Consider the combination of two registers */
+            actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i);
+        }
+        tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!<  pick up next descriptor */
+    }
+
+    actualAttachId |= selector;
+
+    return (clock_attach_id_t)actualAttachId;
+}
+
+/* Set IP Clock Divider */
+/**
+ * brief        Setup peripheral clock dividers.
+ * param        div_name        : Clock divider name
+ * param divided_by_value: Value to be divided
+ * param reset :  Whether to reset the divider counter.
+ * return       Nothing
+ */
+void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset)
+{
+    volatile uint32_t *pClkDiv;
+
+    pClkDiv = &(SYSCON->SYSTICKCLKDIV);
+    if (reset)
+    {
+        ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = 1UL << 29U;
+    }
+    if (divided_by_value == 0U) /*!<  halt */
+    {
+        ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = 1UL << 30U;
+    }
+    else
+    {
+        ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = (divided_by_value - 1U);
+    }
+}
+
+/* Get CLOCK OUT Clk */
+/*! brief       Return Frequency of ClockOut
+ *  return      Frequency of ClockOut
+ */
+uint32_t CLOCK_GetClockOutClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch (SYSCON->CLKOUTSELA)
+    {
+        case 0U:
+            freq = CLOCK_GetCoreSysClkFreq();
+            break;
+
+        case 1U:
+            freq = CLOCK_GetExtClkFreq();
+            break;
+
+        case 2U:
+            freq = CLOCK_GetWdtOscFreq();
+            break;
+
+        case 3U:
+            freq = CLOCK_GetFroHfFreq();
+            break;
+
+        case 4U:
+            freq = CLOCK_GetPllOutFreq();
+            break;
+
+        case 5U:
+            freq = CLOCK_GetUsbPllOutFreq();
+            break;
+
+        case 6U:
+            freq = CLOCK_GetAudioPllOutFreq();
+            break;
+
+        case 7U:
+            freq = CLOCK_GetOsc32KFreq();
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U);
+}
+
+/* Get SPIFI Clk */
+/*! brief       Return Frequency of Spifi Clock
+ *  return      Frequency of Spifi.
+ */
+uint32_t CLOCK_GetSpifiClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch (SYSCON->SPIFICLKSEL)
+    {
+        case 0U:
+            freq = CLOCK_GetCoreSysClkFreq();
+            break;
+        case 1U:
+            freq = CLOCK_GetPllOutFreq();
+            break;
+        case 2U:
+            freq = CLOCK_GetUsbPllOutFreq();
+            break;
+        case 3U:
+            freq = CLOCK_GetFroHfFreq();
+            break;
+        case 4U:
+            freq = CLOCK_GetAudioPllOutFreq();
+            break;
+        case 7U:
+            freq = 0U;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((SYSCON->SPIFICLKDIV & 0xffU) + 1U);
+}
+
+/* Get ADC Clk */
+/*! brief       Return Frequency of Adc Clock
+ *  return      Frequency of Adc Clock.
+ */
+uint32_t CLOCK_GetAdcClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch (SYSCON->ADCCLKSEL)
+    {
+        case 0U:
+            freq = CLOCK_GetFroHfFreq();
+            break;
+        case 1U:
+            freq = CLOCK_GetPllOutFreq();
+            break;
+        case 2U:
+            freq = CLOCK_GetUsbPllOutFreq();
+            break;
+        case 3U:
+            freq = CLOCK_GetAudioPllOutFreq();
+            break;
+        case 7U:
+            freq = 0U;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((SYSCON->ADCCLKDIV & 0xffU) + 1U);
+}
+
+/* Get USB0 Clk */
+/*! brief       Return Frequency of Usb0 Clock
+ *  return      Frequency of Usb0 Clock.
+ */
+uint32_t CLOCK_GetUsb0ClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch (SYSCON->USB0CLKSEL)
+    {
+        case 0U:
+            freq = CLOCK_GetFroHfFreq();
+            break;
+        case 1U:
+            freq = CLOCK_GetPllOutFreq();
+            break;
+        case 2U:
+            freq = CLOCK_GetUsbPllOutFreq();
+            break;
+        case 7U:
+            freq = 0U;
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((SYSCON->USB0CLKDIV & 0xffU) + 1U);
+}
+
+/* Get USB1 Clk */
+/*! brief       Return Frequency of Usb1 Clock
+ *  return      Frequency of Usb1 Clock.
+ */
+uint32_t CLOCK_GetUsb1ClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch (SYSCON->USB1CLKSEL)
+    {
+        case 0U:
+            freq = CLOCK_GetCoreSysClkFreq();
+            break;
+        case 1U:
+            freq = CLOCK_GetPllOutFreq();
+            break;
+        case 2U:
+            freq = CLOCK_GetUsbPllOutFreq();
+            break;
+        case 7U:
+            freq = 0U;
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((SYSCON->USB1CLKDIV & 0xffU) + 1U);
+}
+
+/* Get MCLK Clk */
+/*! brief       Return Frequency of MClk Clock
+ *  return      Frequency of MClk Clock.
+ */
+uint32_t CLOCK_GetMclkClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch (SYSCON->MCLKCLKSEL)
+    {
+        case 0U:
+            freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffu) + 1U);
+            break;
+        case 1U:
+            freq = CLOCK_GetAudioPllOutFreq();
+            break;
+        case 7U:
+            freq = 0U;
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U);
+}
+
+/* Get SCTIMER Clk */
+/*! brief       Return Frequency of SCTimer Clock
+ *  return      Frequency of SCTimer Clock.
+ */
+uint32_t CLOCK_GetSctClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch (SYSCON->SCTCLKSEL)
+    {
+        case 0U:
+            freq = CLOCK_GetCoreSysClkFreq();
+            break;
+        case 1U:
+            freq = CLOCK_GetPllOutFreq();
+            break;
+        case 2U:
+            freq = CLOCK_GetFroHfFreq();
+            break;
+        case 3U:
+            freq = CLOCK_GetAudioPllOutFreq();
+            break;
+        case 7U:
+            freq = 0U;
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U);
+}
+
+/* Get SDIO Clk */
+/*! brief       Return Frequency of SDIO Clock
+ *  return      Frequency of SDIO Clock.
+ */
+uint32_t CLOCK_GetSdioClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch (SYSCON->SDIOCLKSEL)
+    {
+        case 0U:
+            freq = CLOCK_GetCoreSysClkFreq();
+            break;
+        case 1U:
+            freq = CLOCK_GetPllOutFreq();
+            break;
+        case 2U:
+            freq = CLOCK_GetUsbPllOutFreq();
+            break;
+        case 3U:
+            freq = CLOCK_GetFroHfFreq();
+            break;
+        case 4U:
+            freq = CLOCK_GetAudioPllOutFreq();
+            break;
+        case 7U:
+            freq = 0U;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U);
+}
+
+/* Get LCD Clk */
+/*! brief       Return Frequency of LCD Clock
+ *  return      Frequency of LCD Clock.
+ */
+uint32_t CLOCK_GetLcdClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch (SYSCON->LCDCLKSEL)
+    {
+        case 0U:
+            freq = CLOCK_GetCoreSysClkFreq();
+            break;
+        case 1U:
+            freq = CLOCK_GetLcdClkIn();
+            break;
+        case 2U:
+            freq = CLOCK_GetFroHfFreq();
+            break;
+        case 3U:
+            freq = 0U;
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((SYSCON->LCDCLKDIV & 0xffU) + 1U);
+}
+
+/* Get LCD CLK IN Clk */
+/*! brief       Return Frequency of LCD CLKIN Clock
+ *  return      Frequency of LCD CLKIN Clock.
+ */
+uint32_t CLOCK_GetLcdClkIn(void)
+{
+    return g_Lcd_Clk_In_Freq;
+}
+
+/* Get FRO 12M Clk */
+/*! brief       Return Frequency of FRO 12MHz
+ *  return      Frequency of FRO 12MHz
+ */
+uint32_t CLOCK_GetFro12MFreq(void)
+{
+    return ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) != 0UL) ? 0U : 12000000U;
+}
+
+/* Get EXT OSC Clk */
+/*! brief       Return Frequency of External Clock
+ *  return      Frequency of External Clock. If no external clock is used returns 0.
+ */
+uint32_t CLOCK_GetExtClkFreq(void)
+{
+    return g_Ext_Clk_Freq;
+}
+
+/* Get WATCH DOG Clk */
+/*! brief       Return Frequency of Watchdog Oscillator
+ *  return      Frequency of Watchdog Oscillator
+ */
+uint32_t CLOCK_GetWdtOscFreq(void)
+{
+    uint8_t freq_sel, div_sel;
+    if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) != 0UL)
+    {
+        return 0U;
+    }
+    else
+    {
+        div_sel = (uint8_t)(((SYSCON->WDTOSCCTRL & 0x1fU) + 1U) << 1U);
+        freq_sel =
+            wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
+        return ((uint32_t)freq_sel * 50000U) / ((uint32_t)div_sel);
+    }
+}
+
+/* Get HF FRO Clk */
+/*! brief       Return Frequency of High-Freq output of FRO
+ *  return      Frequency of High-Freq output of FRO
+ */
+uint32_t CLOCK_GetFroHfFreq(void)
+{
+    if (((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) != 0UL) ||
+        (0UL == (SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK)))
+    {
+        return 0U;
+    }
+
+    if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) != 0UL)
+    {
+        return 96000000U;
+    }
+    else
+    {
+        return 48000000U;
+    }
+}
+
+/* Get SYSTEM PLL Clk */
+/*! brief       Return Frequency of PLL
+ *  return      Frequency of PLL
+ */
+uint32_t CLOCK_GetPllOutFreq(void)
+{
+    return s_Pll_Freq;
+}
+
+/* Get AUDIO PLL Clk */
+/*! brief       Return Frequency of AUDIO PLL
+ *  return      Frequency of PLL
+ */
+uint32_t CLOCK_GetAudioPllOutFreq(void)
+{
+    return s_Audio_Pll_Freq;
+}
+
+/* Get USB PLL Clk */
+/*! brief       Return Frequency of USB PLL
+ *  return      Frequency of PLL
+ */
+uint32_t CLOCK_GetUsbPllOutFreq(void)
+{
+    return s_Usb_Pll_Freq;
+}
+
+/* Get RTC OSC Clk */
+/*! brief       Return Frequency of 32kHz osc
+ *  return      Frequency of 32kHz osc
+ */
+uint32_t CLOCK_GetOsc32KFreq(void)
+{
+    return CLK_RTC_32K_CLK; /* Needs to be corrected to check that RTC Clock is enabled */
+}
+
+/* Get MAIN Clk */
+/*! brief       Return Frequency of Core System
+ *  return      Frequency of Core System
+ */
+uint32_t CLOCK_GetCoreSysClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch (SYSCON->MAINCLKSELB)
+    {
+        case 0U:
+            if (SYSCON->MAINCLKSELA == 0U)
+            {
+                freq = CLOCK_GetFro12MFreq();
+            }
+            else if (SYSCON->MAINCLKSELA == 1U)
+            {
+                freq = CLOCK_GetExtClkFreq();
+            }
+            else if (SYSCON->MAINCLKSELA == 2U)
+            {
+                freq = CLOCK_GetWdtOscFreq();
+            }
+            else if (SYSCON->MAINCLKSELA == 3U)
+            {
+                freq = CLOCK_GetFroHfFreq();
+            }
+            else
+            {
+                /* Add comment to prevent the case of rule 15.7. */
+            }
+            break;
+        case 2U:
+            freq = CLOCK_GetPllOutFreq();
+            break;
+
+        case 3U:
+            freq = CLOCK_GetOsc32KFreq();
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/* Get I2S MCLK Clk */
+/*! brief       Return Frequency of I2S MCLK Clock
+ *  return      Frequency of I2S MCLK Clock
+ */
+uint32_t CLOCK_GetI2SMClkFreq(void)
+{
+    return g_I2S_Mclk_Freq;
+}
+
+/* Get ASYNC APB Clk */
+/*! brief       Return Frequency of Asynchronous APB Clock
+ *  return      Frequency of Asynchronous APB Clock Clock
+ */
+uint32_t CLOCK_GetAsyncApbClkFreq(void)
+{
+    async_clock_src_t clkSrc;
+    uint32_t clkRate;
+
+    clkSrc = CLOCK_GetAsyncApbClkSrc();
+
+    switch (clkSrc)
+    {
+        case kCLOCK_AsyncMainClk:
+            clkRate = CLOCK_GetCoreSysClkFreq();
+            break;
+        case kCLOCK_AsyncFro12Mhz:
+            clkRate = CLK_FRO_12MHZ;
+            break;
+        default:
+            clkRate = 0U;
+            break;
+    }
+
+    return clkRate;
+}
+
+/* Get MCAN Clk */
+/*! brief       Return Frequency of MCAN Clock
+ *  param       MCanSel : 0U: MCAN0; 1U: MCAN1
+ *  return      Frequency of MCAN Clock
+ */
+uint32_t CLOCK_GetMCanClkFreq(uint32_t MCanSel)
+{
+    uint32_t freq = 0U;
+    switch (MCanSel)
+    {
+        case 0U:
+            freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN0CLKDIV & 0xffU) + 1U);
+            break;
+        case 1U:
+            freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN1CLKDIV & 0xffU) + 1U);
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/* Get FLEXCOMM Clk */
+/*! brief       Return Frequency of Flexcomm functional Clock
+ *  return      Frequency of Flexcomm functional Clock
+ */
+uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id)
+{
+    uint32_t freq = 0U;
+
+    if (id != 10U)
+    {
+        switch (SYSCON->FCLKSEL[id])
+        {
+            case 0U:
+                freq = CLOCK_GetFro12MFreq();
+                break;
+            case 1U:
+                freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffu) + 1U);
+                break;
+            case 2U:
+                freq = CLOCK_GetAudioPllOutFreq();
+                break;
+            case 3U:
+                freq = CLOCK_GetI2SMClkFreq();
+                break;
+            case 4U:
+                freq = CLOCK_GetFrgClkFreq();
+                break;
+
+            default:
+                freq = 0U;
+                break;
+        }
+    }
+    else
+    {
+        switch (SYSCON->FCLKSEL10)
+        {
+            case 0U:
+                freq = CLOCK_GetCoreSysClkFreq();
+                break;
+            case 1U:
+                freq = CLOCK_GetPllOutFreq();
+                break;
+            case 2U:
+                freq = CLOCK_GetUsbPllOutFreq();
+                break;
+            case 3U:
+                freq = CLOCK_GetFroHfFreq();
+                break;
+            case 4U:
+                freq = CLOCK_GetAudioPllOutFreq();
+                break;
+            default:
+                freq = 0U;
+                break;
+        }
+    }
+
+    return freq;
+}
+
+/* Get FRG Clk */
+uint32_t CLOCK_GetFRGInputClock(void)
+{
+    uint32_t freq = 0U;
+
+    switch (SYSCON->FRGCLKSEL)
+    {
+        case 0U:
+            freq = CLOCK_GetCoreSysClkFreq();
+            break;
+        case 1U:
+            freq = CLOCK_GetPllOutFreq();
+            break;
+        case 2U:
+            freq = CLOCK_GetFro12MFreq();
+            break;
+        case 3U:
+            freq = CLOCK_GetFroHfFreq();
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/* Get FRG Clk */
+/*! brief  Return Frequency of frg
+ *  return Frequency of FRG
+ */
+uint32_t CLOCK_GetFrgClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    if ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_DIV_MASK) == SYSCON_FRGCTRL_DIV_MASK)
+    {
+        freq = (uint32_t)(((uint64_t)CLOCK_GetFRGInputClock() * (SYSCON_FRGCTRL_DIV_MASK + 1U)) /
+                          ((SYSCON_FRGCTRL_DIV_MASK + 1U) +
+                           ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_MULT_MASK) >> SYSCON_FRGCTRL_MULT_SHIFT)));
+    }
+    else
+    {
+        freq = 0U;
+    }
+
+    return freq;
+}
+
+/* Get FRG Clk */
+/*! brief  Return Frequency of dmic
+ *  return Frequency of DMIC
+ */
+uint32_t CLOCK_GetDmicClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch (SYSCON->DMICCLKSEL)
+    {
+        case 0U:
+            freq = CLOCK_GetFro12MFreq();
+            break;
+        case 1U:
+            freq = CLOCK_GetFroHfFreq();
+            break;
+        case 2U:
+            freq = CLOCK_GetPllOutFreq();
+            break;
+        case 3U:
+            freq = CLOCK_GetI2SMClkFreq();
+            break;
+        case 4U:
+            freq = CLOCK_GetCoreSysClkFreq();
+            break;
+        case 5U:
+            freq = CLOCK_GetWdtOscFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U);
+    ;
+}
+
+/* Set FRG Clk */
+uint32_t CLOCK_SetFRGClock(uint32_t freq)
+{
+    uint32_t input = CLOCK_GetFRGInputClock();
+    uint32_t mul;
+
+    if ((freq > 48000000U) || (freq > input) || (input / freq >= 2U))
+    {
+        /* FRG output frequency should be less than equal to 48MHz */
+        return 0U;
+    }
+    else
+    {
+        mul             = (uint32_t)((((uint64_t)input - freq) * 256U) / ((uint64_t)freq));
+        SYSCON->FRGCTRL = (mul << SYSCON_FRGCTRL_MULT_SHIFT) | SYSCON_FRGCTRL_DIV_MASK;
+        return 1U;
+    }
+}
+
+/* Set IP Clk */
+/*! brief       Return Frequency of selected clock
+ *  return      Frequency of selected clock
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clockName)
+{
+    uint32_t freq;
+    switch (clockName)
+    {
+        case kCLOCK_CoreSysClk:
+            freq = CLOCK_GetCoreSysClkFreq();
+            break;
+        case kCLOCK_BusClk:
+            freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
+            break;
+        case kCLOCK_ClockOut:
+            freq = CLOCK_GetClockOutClkFreq();
+            break;
+        case kCLOCK_Mclk:
+            freq = CLOCK_GetMclkClkFreq();
+            break;
+        case kCLOCK_FroHf:
+            freq = CLOCK_GetFroHfFreq();
+            break;
+        case kCLOCK_Fro12M:
+            freq = CLOCK_GetFro12MFreq();
+            break;
+        case kCLOCK_ExtClk:
+            freq = CLOCK_GetExtClkFreq();
+            break;
+        case kCLOCK_PllOut:
+            freq = CLOCK_GetPllOutFreq();
+            break;
+        case kCLOCK_WdtOsc:
+            freq = CLOCK_GetWdtOscFreq();
+            break;
+        case kCLOCK_Frg:
+            freq = CLOCK_GetFrgClkFreq();
+            break;
+
+        case kCLOCK_AsyncApbClk:
+            freq = CLOCK_GetAsyncApbClkFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/* Find encoded NDEC value for raw N value, max N = NVALMAX */
+static uint32_t pllEncodeN(uint32_t N)
+{
+    uint32_t x, i;
+
+    /* Find NDec */
+    switch (N)
+    {
+        case 0U:
+            x = 0x3FFU;
+            break;
+
+        case 1U:
+            x = 0x302U;
+            break;
+
+        case 2U:
+            x = 0x202U;
+            break;
+
+        default:
+            x = 0x080U;
+            for (i = N; i <= NVALMAX; i++)
+            {
+                x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU);
+            }
+            break;
+    }
+
+    return x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P);
+}
+
+/* Find decoded N value for raw NDEC value */
+static uint32_t pllDecodeN(uint32_t NDEC)
+{
+    uint32_t n, x, i;
+
+    /* Find NDec */
+    switch (NDEC)
+    {
+        case 0x3FFU:
+            n = 0U;
+            break;
+
+        case 0x302U:
+            n = 1U;
+            break;
+
+        case 0x202U:
+            n = 2U;
+            break;
+
+        default:
+            x = 0x080U;
+            n = 0xFFFFFFFFU;
+            for (i = NVALMAX; i >= 3U; i--)
+            {
+                x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU);
+                if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
+                {
+                    /* Decoded value of NDEC */
+                    n = i;
+                    break;
+                }
+            }
+            break;
+    }
+
+    return n;
+}
+
+/* Find encoded PDEC value for raw P value, max P = PVALMAX */
+static uint32_t pllEncodeP(uint32_t P)
+{
+    uint32_t x, i;
+
+    /* Find PDec */
+    switch (P)
+    {
+        case 0U:
+            x = 0x7FU;
+            break;
+
+        case 1U:
+            x = 0x62U;
+            break;
+
+        case 2U:
+            x = 0x42U;
+            break;
+
+        default:
+            x = 0x10U;
+            for (i = P; i <= PVALMAX; i++)
+            {
+                x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU);
+            }
+            break;
+    }
+
+    return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P);
+}
+
+/* Find decoded P value for raw PDEC value */
+static uint32_t pllDecodeP(uint32_t PDEC)
+{
+    uint32_t p, x, i;
+
+    /* Find PDec */
+    switch (PDEC)
+    {
+        case 0x7FU:
+            p = 0U;
+            break;
+
+        case 0x62U:
+            p = 1U;
+            break;
+
+        case 0x42U:
+            p = 2U;
+            break;
+
+        default:
+            x = 0x10U;
+            p = 0xFFFFFFFFU;
+            for (i = PVALMAX; i >= 3U; i--)
+            {
+                x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU);
+                if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
+                {
+                    /* Decoded value of PDEC */
+                    p = i;
+                    break;
+                }
+            }
+            break;
+    }
+
+    return p;
+}
+
+/* Find encoded MDEC value for raw M value, max M = MVALMAX */
+static uint32_t pllEncodeM(uint32_t M)
+{
+    uint32_t i, x;
+
+    /* Find MDec */
+    switch (M)
+    {
+        case 0U:
+            x = 0x1FFFFU;
+            break;
+
+        case 1U:
+            x = 0x18003U;
+            break;
+
+        case 2U:
+            x = 0x10003U;
+            break;
+
+        default:
+            x = 0x04000U;
+            for (i = M; i <= MVALMAX; i++)
+            {
+                x = (((x ^ (x >> 1U)) & 1U) << 14U) | ((x >> 1U) & 0x3FFFU);
+            }
+            break;
+    }
+
+    return x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P);
+}
+
+/* Find decoded M value for raw MDEC value */
+static uint32_t pllDecodeM(uint32_t MDEC)
+{
+    uint32_t m, i, x;
+
+    /* Find MDec */
+    switch (MDEC)
+    {
+        case 0x1FFFFU:
+            m = 0U;
+            break;
+
+        case 0x18003U:
+            m = 1U;
+            break;
+
+        case 0x10003U:
+            m = 2U;
+            break;
+
+        default:
+            x = 0x04000U;
+            m = 0xFFFFFFFFU;
+            for (i = MVALMAX; i >= 3U; i--)
+            {
+                x = (((x ^ (x >> 1U)) & 1U) << 14U) | ((x >> 1U) & 0x3FFFU);
+                if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
+                {
+                    /* Decoded value of MDEC */
+                    m = i;
+                    break;
+                }
+            }
+            break;
+    }
+
+    return m;
+}
+
+/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */
+static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR)
+{
+    /* bandwidth: compute selP from Multiplier */
+    if (M < 60U)
+    {
+        *pSelP = (M >> 1U) + 1U;
+    }
+    else
+    {
+        *pSelP = PVALMAX - 1U;
+    }
+
+    /* bandwidth: compute selI from Multiplier */
+    if (M > 16384U)
+    {
+        *pSelI = 1U;
+    }
+    else if (M > 8192U)
+    {
+        *pSelI = 2U;
+    }
+    else if (M > 2048U)
+    {
+        *pSelI = 4U;
+    }
+    else if (M >= 501U)
+    {
+        *pSelI = 8U;
+    }
+    else if (M >= 60U)
+    {
+        *pSelI = 4U * (1024U / (M + 9U));
+    }
+    else
+    {
+        *pSelI = (M & 0x3CU) + 4U;
+    }
+
+    if (*pSelI > ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT))
+    {
+        *pSelI = ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT);
+    }
+
+    *pSelR = 0U;
+}
+
+/* Get predivider (N) from PLL NDEC setting */
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
+{
+    uint32_t preDiv = 1;
+
+    /* Direct input is not used? */
+    if ((ctrlReg & (1UL << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) == 0U)
+    {
+        /* Decode NDEC value to get (N) pre divider */
+        preDiv = pllDecodeN(nDecReg & 0x3FFU);
+        if (preDiv == 0U)
+        {
+            preDiv = 1U;
+        }
+    }
+
+    /* Adjusted by 1, directi is used to bypass */
+    return preDiv;
+}
+
+/* Get postdivider (P) from PLL PDEC setting */
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
+{
+    uint32_t postDiv = 1U;
+
+    /* Direct input is not used? */
+    if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U)
+    {
+        /* Decode PDEC value to get (P) post divider */
+        postDiv = 2U * pllDecodeP(pDecReg & 0x7FU);
+        if (postDiv == 0U)
+        {
+            postDiv = 2U;
+        }
+    }
+
+    /* Adjusted by 1, directo is used to bypass */
+    return postDiv;
+}
+
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
+{
+    uint32_t mMult = 1U;
+
+    /* Decode MDEC value to get (M) multiplier */
+    mMult = pllDecodeM(mDecReg & 0x1FFFFU);
+
+    if (mMult == 0U)
+    {
+        mMult = 1U;
+    }
+
+    return mMult;
+}
+
+/* Calculate the powerTimes' power of 2 */
+static uint32_t power2Cal(uint32_t powerTimes)
+{
+    uint32_t ret = 1U;
+    uint32_t i;
+    for (i = 0; i < powerTimes; i++)
+    {
+        ret *= 2U;
+    }
+
+    return ret;
+}
+
+/* Convert the binary to fractional part */
+static double Binary2Fractional(uint32_t binaryPart)
+{
+    double fractional = 0.0;
+    for (uint32_t i = 0U; i <= 14U; i++)
+    {
+        fractional += (double)(uint32_t)((binaryPart >> i) & 0x1U) / (double)(uint32_t)power2Cal(15U - i);
+    }
+    return fractional;
+}
+
+/* Find greatest common divisor between m and n */
+static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n)
+{
+    uint32_t tmp;
+
+    while (n != 0U)
+    {
+        tmp = n;
+        n   = m % n;
+        m   = tmp;
+    }
+
+    return m;
+}
+
+/*
+ * Set PLL output based on desired output rate.
+ * In this function, the it calculates the PLL setting for output frequency from input clock
+ * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently.
+ * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function.
+ */
+static pll_error_t CLOCK_GetPllConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup)
+{
+    uint32_t nDivOutHz, fccoHz, multFccoDiv;
+    uint32_t pllPreDivider, pllMultiplier, pllPostDivider;
+    uint32_t pllDirectInput, pllDirectOutput;
+    uint32_t pllSelP, pllSelI, pllSelR, uplimoff;
+
+    /* Baseline parameters (no input or output dividers) */
+    pllPreDivider   = 1U; /* 1 implies pre-divider will be disabled */
+    pllPostDivider  = 0U; /* 0 implies post-divider will be disabled */
+    pllDirectOutput = 1U;
+    multFccoDiv     = 2U;
+
+    /* Verify output rate parameter */
+    if (foutHz > PLL_MAX_CCO_FREQ_MHZ)
+    {
+        /* Maximum PLL output with post divider=1 cannot go above this frequency */
+        return kStatus_PLL_OutputTooHigh;
+    }
+    if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U)))
+    {
+        /* Minmum PLL output with maximum post divider cannot go below this frequency */
+        return kStatus_PLL_OutputTooLow;
+    }
+
+    /* Verify input rate parameter */
+    if (finHz < PLL_LOWER_IN_LIMIT)
+    {
+        /* Input clock into the PLL cannot be lower than this */
+        return kStatus_PLL_InputTooLow;
+    }
+
+    /* Find the optimal CCO frequency for the output and input that
+       will keep it inside the PLL CCO range. This may require
+       tweaking the post-divider for the PLL. */
+    fccoHz = foutHz;
+    while (fccoHz < PLL_MIN_CCO_FREQ_MHZ)
+    {
+        /* CCO output is less than minimum CCO range, so the CCO output
+           needs to be bumped up and the post-divider is used to bring
+           the PLL output back down. */
+        pllPostDivider++;
+        if (pllPostDivider > PVALMAX)
+        {
+            return kStatus_PLL_OutsideIntLimit;
+        }
+
+        /* Target CCO goes up, PLL output goes down */
+        fccoHz          = foutHz * (pllPostDivider * 2U);
+        pllDirectOutput = 0U;
+    }
+
+    /* Determine if a pre-divider is needed to get the best frequency */
+    if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz))
+    {
+        uint32_t a = FindGreatestCommonDivisor(fccoHz, (multFccoDiv * finHz));
+
+        if (a > 20000U)
+        {
+            a = (multFccoDiv * finHz) / a;
+            if ((a != 0U) && (a < PLL_MAX_N_DIV))
+            {
+                pllPreDivider = a;
+            }
+        }
+    }
+
+    /* Bypass pre-divider hardware if pre-divider is 1 */
+    if (pllPreDivider > 1U)
+    {
+        pllDirectInput = 0U;
+    }
+    else
+    {
+        pllDirectInput = 1U;
+    }
+
+    /* Determine PLL multipler */
+    nDivOutHz     = (finHz / pllPreDivider);
+    pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv;
+
+    /* Find optimal values for filter */
+    /* Will bumping up M by 1 get us closer to the desired CCO frequency? */
+    if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2U) + 1U)) < (fccoHz * 2U))
+    {
+        pllMultiplier++;
+    }
+
+    /* Setup filtering */
+    pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR);
+    uplimoff = 0U;
+
+    /* Get encoded value for M (mult) and use manual filter, disable SS mode */
+    pSetup->pllmdec = PLL_MDEC_VAL_SET(pllEncodeM(pllMultiplier));
+
+    /* Get encoded values for N (prediv) and P (postdiv) */
+    pSetup->pllndec = PLL_NDEC_VAL_SET(pllEncodeN(pllPreDivider));
+    pSetup->pllpdec = PLL_PDEC_VAL_SET(pllEncodeP(pllPostDivider));
+
+    /* PLL control */
+    pSetup->pllctrl = (pllSelR << SYSCON_SYSPLLCTRL_SELR_SHIFT) |           /* Filter coefficient */
+                      (pllSelI << SYSCON_SYSPLLCTRL_SELI_SHIFT) |           /* Filter coefficient */
+                      (pllSelP << SYSCON_SYSPLLCTRL_SELP_SHIFT) |           /* Filter coefficient */
+                      (0UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT) |             /* PLL bypass mode disabled */
+                      (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT) |      /* SS/fractional mode disabled */
+                      (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT) | /* Bypass pre-divider? */
+                      (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT); /* Bypass post-divider? */
+
+    return kStatus_PLL_Success;
+}
+
+#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
+/* Alloct the static buffer for cache. */
+static pll_setup_t gPllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT];
+static uint32_t gFinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]  = {0};
+static uint32_t gFoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};
+static uint32_t gPllSetupCacheIdx                                  = 0U;
+#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
+
+/*
+ * Calculate the PLL setting values from input clock freq to output freq.
+ */
+static pll_error_t CLOCK_GetPllConfig(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup)
+{
+    pll_error_t retErr;
+#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
+    uint32_t i;
+
+    for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++)
+    {
+        if ((finHz == gFinHzCache[i]) && (foutHz == gFoutHzCache[i]))
+        {
+            /* Hit the target in cache buffer. */
+            pSetup->pllctrl = gPllSetupCacheStruct[i].pllctrl;
+            pSetup->pllndec = gPllSetupCacheStruct[i].pllndec;
+            pSetup->pllpdec = gPllSetupCacheStruct[i].pllpdec;
+            pSetup->pllmdec = gPllSetupCacheStruct[i].pllmdec;
+            retErr          = kStatus_PLL_Success;
+            break;
+        }
+    }
+
+    if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
+    {
+        return retErr;
+    }
+#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
+
+    /* No cache or did not hit the cache. */
+    retErr = CLOCK_GetPllConfigInternal(finHz, foutHz, pSetup);
+
+#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
+    if (kStatus_PLL_Success == retErr)
+    {
+        /* Cache the most recent calulation result into buffer. */
+        gFinHzCache[gPllSetupCacheIdx]  = finHz;
+        gFoutHzCache[gPllSetupCacheIdx] = foutHz;
+
+        gPllSetupCacheStruct[gPllSetupCacheIdx].pllctrl = pSetup->pllctrl;
+        gPllSetupCacheStruct[gPllSetupCacheIdx].pllndec = pSetup->pllndec;
+        gPllSetupCacheStruct[gPllSetupCacheIdx].pllpdec = pSetup->pllpdec;
+        gPllSetupCacheStruct[gPllSetupCacheIdx].pllmdec = pSetup->pllmdec;
+        /* Update the index for next available buffer. */
+        gPllSetupCacheIdx = (gPllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT;
+    }
+#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
+
+    return retErr;
+}
+
+/* Update SYSTEM PLL rate variable */
+static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup)
+{
+    s_Pll_Freq = CLOCK_GetSystemPLLOutFromSetup(pSetup);
+}
+
+/* Update AUDIO PLL rate variable */
+static void CLOCK_GetAudioPLLOutFromSetupUpdate(pll_setup_t *pSetup)
+{
+    s_Audio_Pll_Freq = CLOCK_GetAudioPLLOutFromSetup(pSetup);
+}
+
+/* Update AUDIO Fractional PLL rate variable */
+static void CLOCK_GetAudioPLLOutFromAudioFracSetupUpdate(pll_setup_t *pSetup)
+{
+    s_Audio_Pll_Freq = CLOCK_GetAudioPLLOutFromFractSetup(pSetup);
+}
+
+/* Update USB PLL rate variable */
+static void CLOCK_GetUsbPLLOutFromSetupUpdate(const usb_pll_setup_t *pSetup)
+{
+    s_Usb_Pll_Freq = CLOCK_GetUsbPLLOutFromSetup(pSetup);
+}
+
+/* Return System PLL input clock rate */
+/*! brief       Return System PLL input clock rate
+ *  return      System PLL input clock rate
+ */
+uint32_t CLOCK_GetSystemPLLInClockRate(void)
+{
+    uint32_t clkRate = 0U;
+
+    switch ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK))
+    {
+        case 0x00U:
+            clkRate = CLK_FRO_12MHZ;
+            break;
+
+        case 0x01U:
+            clkRate = CLOCK_GetExtClkFreq();
+            break;
+
+        case 0x02U:
+            clkRate = CLOCK_GetWdtOscFreq();
+            break;
+
+        case 0x03U:
+            clkRate = CLOCK_GetOsc32KFreq();
+            break;
+
+        default:
+            clkRate = 0U;
+            break;
+    }
+
+    return clkRate;
+}
+
+/* Return Audio PLL input clock rate */
+/*! brief       Return Audio PLL input clock rate
+ *  return      Audio PLL input clock rate
+ */
+uint32_t CLOCK_GetAudioPLLInClockRate(void)
+{
+    uint32_t clkRate = 0U;
+
+    switch ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK))
+    {
+        case 0x00U:
+            clkRate = CLK_FRO_12MHZ;
+            break;
+
+        case 0x01U:
+            clkRate = CLOCK_GetExtClkFreq();
+            break;
+
+        default:
+            clkRate = 0U;
+            break;
+    }
+
+    return clkRate;
+}
+
+/* Return System PLL output clock rate from setup structure */
+/*! brief       Return System PLL output clock rate from setup structure
+ *  param       pSetup  : Pointer to a PLL setup structure
+ *  return      System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup)
+{
+    uint32_t prediv, postdiv, mMult, inPllRate;
+    uint64_t workRate;
+
+    inPllRate = CLOCK_GetSystemPLLInClockRate();
+    /* If the PLL is bypassed, PLL would not be used and the output of PLL module would just be the input clock*/
+    if ((pSetup->pllctrl & (SYSCON_SYSPLLCTRL_BYPASS_MASK)) == 0U)
+    {
+        /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */
+        /*
+         * 1. Pre-divider
+         * Pre-divider is only available when the DIRECTI is disabled.
+         */
+        if (0U == (pSetup->pllctrl & SYSCON_SYSPLLCTRL_DIRECTI_MASK))
+        {
+            prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec);
+        }
+        else
+        {
+            prediv = 1U; /* The pre-divider is bypassed. */
+        }
+        /*
+         * 2. Post-divider
+         * Post-divider is only available when the DIRECTO is disabled.
+         */
+        if (0U == (pSetup->pllctrl & SYSCON_SYSPLLCTRL_DIRECTO_MASK))
+        {
+            postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec);
+        }
+        else
+        {
+            postdiv = 1U; /* The post-divider is bypassed. */
+        }
+        /* Adjust input clock */
+        inPllRate = inPllRate / prediv;
+
+        /* MDEC used for rate */
+        mMult    = findPllMMult(pSetup->pllctrl, pSetup->pllmdec);
+        workRate = (uint64_t)inPllRate * (uint64_t)mMult;
+
+        workRate = workRate / ((uint64_t)postdiv);
+        workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/
+    }
+    else
+    {
+        /* In bypass mode */
+        workRate = (uint64_t)inPllRate;
+    }
+
+    return (uint32_t)workRate;
+}
+
+/* Return Usb PLL output clock rate from setup structure */
+/*! brief       Return System USB PLL output clock rate from setup structure
+ *  param       pSetup  : Pointer to a PLL setup structure
+ *  return      System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup)
+{
+    uint32_t nsel, psel, msel, inPllRate;
+    uint64_t workRate;
+    inPllRate = CLOCK_GetExtClkFreq();
+    msel      = pSetup->msel;
+    psel      = pSetup->psel;
+    nsel      = pSetup->nsel;
+
+    if (pSetup->fbsel)
+    {
+        /*integer_mode: Fout = M*(Fin/N),  Fcco = 2*P*M*(Fin/N) */
+        workRate = ((uint64_t)inPllRate) * ((uint64_t)msel + 1U) / ((uint64_t)nsel + 1U);
+    }
+    else
+    {
+        /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */
+        workRate = ((uint64_t)inPllRate / ((uint64_t)nsel + 1U)) * (msel + 1U) / (2U * SWITCH_USB_PSEL(psel));
+    }
+
+    return (uint32_t)workRate;
+}
+
+/* Return Audio PLL output clock rate from setup structure */
+/*! brief       Return System AUDIO PLL output clock rate from setup structure
+ *  param       pSetup  : Pointer to a PLL setup structure
+ *  return      System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup)
+{
+    uint32_t prediv, postdiv, mMult, inPllRate;
+    uint64_t workRate;
+
+    inPllRate = CLOCK_GetAudioPLLInClockRate();
+    if ((pSetup->pllctrl & (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) == 0U)
+    {
+        /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */
+        /*
+         * 1. Pre-divider
+         * Pre-divider is only available when the DIRECTI is disabled.
+         */
+        if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTI_MASK))
+        {
+            prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec);
+        }
+        else
+        {
+            prediv = 1U; /* The pre-divider is bypassed. */
+        }
+        /*
+         * 2. Post-divider
+         * Post-divider is only available when the DIRECTO is disabled.
+         */
+        if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTO_MASK))
+        {
+            postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec);
+        }
+        else
+        {
+            postdiv = 1U; /* The post-divider is bypassed. */
+        }
+        /* Adjust input clock */
+        inPllRate = inPllRate / prediv;
+
+        /* MDEC used for rate */
+        mMult    = findPllMMult(pSetup->pllctrl, pSetup->pllmdec);
+        workRate = (uint64_t)inPllRate * (uint64_t)mMult;
+
+        workRate = workRate / ((uint64_t)postdiv);
+        workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/
+    }
+    else
+    {
+        /* In bypass mode */
+        workRate = (uint64_t)inPllRate;
+    }
+
+    return (uint32_t)workRate;
+}
+
+/* Return Audio PLL output clock rate from audio fractioanl setup structure */
+/*! brief       Return System AUDIO PLL output clock rate from audio fractioanl setup structure
+ *  param       pSetup  : Pointer to a PLL setup structure
+ *  return      System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup)
+{
+    uint32_t prediv, postdiv, inPllRate;
+    double workRate, mMultFactional;
+
+    inPllRate = CLOCK_GetAudioPLLInClockRate();
+    if ((pSetup->pllctrl & (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) == 0U)
+    {
+        /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */
+        /*
+         * 1. Pre-divider
+         * Pre-divider is only available when the DIRECTI is disabled.
+         */
+        if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTI_MASK))
+        {
+            prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec);
+        }
+        else
+        {
+            prediv = 1U; /* The pre-divider is bypassed. */
+        }
+        /*
+         * 2. Post-divider
+         * Post-divider is only available when the DIRECTO is disabled.
+         */
+        if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTO_MASK))
+        {
+            postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec);
+        }
+        else
+        {
+            postdiv = 1U; /* The post-divider is bypassed. */
+        }
+        /* Adjust input clock */
+        inPllRate = inPllRate / prediv;
+
+        mMultFactional = (double)(uint32_t)(pSetup->audpllfrac >> 15) +
+                         (double)(uint32_t)Binary2Fractional(pSetup->audpllfrac & 0x7FFFU);
+        workRate = (double)inPllRate * (double)mMultFactional;
+
+        workRate = workRate / ((double)postdiv);
+        workRate = workRate * 2.0; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/
+    }
+    else
+    {
+        /* In bypass mode */
+        workRate = (double)(uint64_t)inPllRate;
+    }
+
+    return (uint32_t)workRate;
+}
+
+/* Set the current PLL Rate */
+/*! brief Store the current PLL rate
+ *  param       rate: Current rate of the PLL
+ *  return      Nothing
+ **/
+void CLOCK_SetStoredPLLClockRate(uint32_t rate)
+{
+    s_Pll_Freq = rate;
+}
+
+/* Set the current Audio PLL Rate */
+/*! brief Store the current AUDIO PLL rate
+ *  param       rate: Current rate of the PLL
+ *  return      Nothing
+ **/
+void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate)
+{
+    s_Audio_Pll_Freq = rate;
+}
+
+/* Set the current Usb PLL Rate */
+void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate)
+{
+    s_Usb_Pll_Freq = rate;
+}
+
+/* Return System PLL output clock rate */
+/*! brief       Return System PLL output clock rate
+ *  param       recompute       : Forces a PLL rate recomputation if true
+ *  return      System PLL output clock rate
+ *  note        The PLL rate is cached in the driver in a variable as
+ *  the rate computation function can take some time to perform. It
+ *  is recommended to use 'false' with the 'recompute' parameter.
+ */
+uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute)
+{
+    pll_setup_t Setup;
+    uint32_t rate;
+
+    if ((recompute) || (s_Pll_Freq == 0U))
+    {
+        Setup.pllctrl = SYSCON->SYSPLLCTRL;
+        Setup.pllndec = SYSCON->SYSPLLNDEC;
+        Setup.pllpdec = SYSCON->SYSPLLPDEC;
+        Setup.pllmdec = SYSCON->SYSPLLMDEC;
+
+        CLOCK_GetSystemPLLOutFromSetupUpdate(&Setup);
+    }
+
+    rate = s_Pll_Freq;
+
+    return rate;
+}
+
+/* Return AUDIO PLL output clock rate */
+/*! brief       Return System AUDIO PLL output clock rate
+ *  param       recompute       : Forces a AUDIO PLL rate recomputation if true
+ *  return      System AUDIO PLL output clock rate
+ *  note        The AUDIO PLL rate is cached in the driver in a variable as
+ *  the rate computation function can take some time to perform. It
+ *  is recommended to use 'false' with the 'recompute' parameter.
+ */
+uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute)
+{
+    pll_setup_t Setup;
+    uint32_t rate;
+
+    if ((recompute) || (s_Audio_Pll_Freq == 0U))
+    {
+        Setup.pllctrl = SYSCON->AUDPLLCTRL;
+        Setup.pllndec = SYSCON->AUDPLLNDEC;
+        Setup.pllpdec = SYSCON->AUDPLLPDEC;
+        Setup.pllmdec = SYSCON->AUDPLLMDEC;
+
+        CLOCK_GetAudioPLLOutFromSetupUpdate(&Setup);
+    }
+
+    rate = s_Audio_Pll_Freq;
+    return rate;
+}
+
+/* Return USB PLL output clock rate */
+uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute)
+{
+    usb_pll_setup_t Setup;
+    uint32_t rate;
+
+    if ((recompute) || (s_Usb_Pll_Freq == 0U))
+    {
+        Setup.msel  = (uint8_t)((SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_MSEL_SHIFT) & SYSCON_USBPLLCTRL_MSEL_MASK);
+        Setup.psel  = (uint8_t)((SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_PSEL_SHIFT) & SYSCON_USBPLLCTRL_PSEL_MASK);
+        Setup.nsel  = (uint8_t)((SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_NSEL_SHIFT) & SYSCON_USBPLLCTRL_NSEL_MASK);
+        Setup.fbsel = (((SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_FBSEL_SHIFT) & SYSCON_USBPLLCTRL_FBSEL_MASK) != 0UL);
+        Setup.bypass =
+            (((SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_BYPASS_SHIFT) & SYSCON_USBPLLCTRL_BYPASS_MASK) != 0UL);
+        Setup.direct =
+            (((SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_DIRECT_SHIFT) & SYSCON_USBPLLCTRL_DIRECT_MASK) != 0UL);
+        CLOCK_GetUsbPLLOutFromSetupUpdate(&Setup);
+    }
+
+    rate = s_Usb_Pll_Freq;
+    return rate;
+}
+
+/* Set PLL output based on the passed PLL setup data */
+/*! brief       Set PLL output based on the passed PLL setup data
+ *  param       pControl        : Pointer to populated PLL control structure to generate setup with
+ *  param       pSetup          : Pointer to PLL setup structure to be filled
+ *  return      PLL_ERROR_SUCCESS on success, or PLL setup error code
+ *  note        Actual frequency for setup may vary from the desired frequency based on the
+ *  accuracy of input clocks, rounding, non-fractional PLL mode, etc.
+ */
+pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup)
+{
+    uint32_t inRate;
+    pll_error_t pllError;
+
+    /* Determine input rate for the PLL */
+    if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U)
+    {
+        inRate = pControl->inputRate;
+    }
+    else
+    {
+        inRate = CLOCK_GetSystemPLLInClockRate();
+    }
+
+    /* PLL flag options */
+    pllError        = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup);
+    pSetup->pllRate = pControl->desiredRate;
+    return pllError;
+}
+
+/* Set PLL output from PLL setup structure */
+/*! brief       Set PLL output from PLL setup structure (precise frequency)
+ * param        pSetup  : Pointer to populated PLL setup structure
+ * param flagcfg : Flag configuration for PLL config structure
+ * return       PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * note This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg)
+{
+    if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U)
+    {
+        /* Turn on the ext clock if system pll input select clk_in */
+        CLOCK_Enable_SysOsc(true);
+    }
+    /* Enable power for PLLs */
+    POWER_SetPLL();
+    /* Power off PLL during setup changes */
+    POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0);
+
+    pSetup->flags = flagcfg;
+
+    /* Write PLL setup data */
+    SYSCON->SYSPLLCTRL = pSetup->pllctrl;
+    SYSCON->SYSPLLNDEC = pSetup->pllndec;
+    SYSCON->SYSPLLNDEC = pSetup->pllndec | (1UL << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
+    SYSCON->SYSPLLPDEC = pSetup->pllpdec;
+    SYSCON->SYSPLLPDEC = pSetup->pllpdec | (1UL << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
+    SYSCON->SYSPLLMDEC = pSetup->pllmdec;
+    SYSCON->SYSPLLMDEC = pSetup->pllmdec | (1UL << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */
+
+    /* Flags for lock or power on */
+    if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)
+    {
+        /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
+        uint32_t maxCCO    = (1UL << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
+        uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1UL << 17U);
+
+        /* Initialize  and power up PLL */
+        SYSCON->SYSPLLMDEC = maxCCO;
+        POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
+
+        /* Set mreq to activate */
+        SYSCON->SYSPLLMDEC = maxCCO | (1UL << 17U);
+
+        /* Delay for 72 uSec @ 12Mhz */
+        SDK_DelayAtLeastUs(72U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+
+        /* clear mreq to prepare for restoring mreq */
+        SYSCON->SYSPLLMDEC = curSSCTRL;
+
+        /* set original value back and activate */
+        SYSCON->SYSPLLMDEC = curSSCTRL | (1UL << 17U);
+
+        /* Enable peripheral states by setting low */
+        POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
+    }
+    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+    {
+        while (CLOCK_IsSystemPLLLocked() == false)
+        {
+        }
+    }
+
+    /* Update current programmed PLL rate var */
+    CLOCK_GetSystemPLLOutFromSetupUpdate(pSetup);
+
+    /* System voltage adjustment, occurs prior to setting main system clock */
+    if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U)
+    {
+        POWER_SetVoltageForFreq(s_Pll_Freq);
+    }
+
+    return kStatus_PLL_Success;
+}
+
+/* Set AUDIO PLL output from AUDIO PLL setup structure */
+/*! brief       Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency)
+ * param        pSetup  : Pointer to populated PLL setup structure
+ * param flagcfg : Flag configuration for PLL config structure
+ * return       PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * note This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
+ * and adjust system voltages to the new AUDIOPLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg)
+{
+    if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U)
+    {
+        /* Turn on the ext clock if system pll input select clk_in */
+        CLOCK_Enable_SysOsc(true);
+    }
+    /* Enable power VD3 for PLLs */
+    POWER_SetPLL();
+    /* Power off PLL during setup changes */
+    POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+    pSetup->flags = flagcfg;
+
+    /* Write PLL setup data */
+    SYSCON->AUDPLLCTRL = pSetup->pllctrl;
+    SYSCON->AUDPLLNDEC = pSetup->pllndec;
+    SYSCON->AUDPLLNDEC = pSetup->pllndec | (1UL << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
+    SYSCON->AUDPLLPDEC = pSetup->pllpdec;
+    SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1UL << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
+    SYSCON->AUDPLLMDEC = pSetup->pllmdec;
+    SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1UL << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */
+    SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1);                            /* disable fractional function */
+
+    /* Flags for lock or power on */
+    if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)
+    {
+        /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
+        uint32_t maxCCO    = (1UL << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
+        uint32_t curSSCTRL = SYSCON->AUDPLLMDEC & ~(1UL << 17U);
+
+        /* Initialize  and power up PLL */
+        SYSCON->AUDPLLMDEC = maxCCO;
+        POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+        /* Set mreq to activate */
+        SYSCON->AUDPLLMDEC = maxCCO | (1UL << 17U);
+
+        /* Delay for 72 uSec @ 12Mhz */
+        SDK_DelayAtLeastUs(72U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+
+        /* clear mreq to prepare for restoring mreq */
+        SYSCON->AUDPLLMDEC = curSSCTRL;
+
+        /* set original value back and activate */
+        SYSCON->AUDPLLMDEC = curSSCTRL | (1UL << 17U);
+
+        /* Enable peripheral states by setting low */
+        POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+    }
+    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+    {
+        while (CLOCK_IsAudioPLLLocked() == false)
+        {
+        }
+    }
+
+    /* Update current programmed PLL rate var */
+    CLOCK_GetAudioPLLOutFromSetupUpdate(pSetup);
+
+    return kStatus_PLL_Success;
+}
+
+/* Set AUDIO PLL output from AUDIO PLL fractional setup structure */
+/*! brief       Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise
+ * frequency)
+ * param        pSetup  : Pointer to populated PLL setup structure
+ * param flagcfg : Flag configuration for PLL config structure
+ * return       PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * note This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
+ * and adjust system voltages to the new AUDIOPLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg)
+{
+    if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U)
+    {
+        /* Turn on the ext clock if system pll input select clk_in */
+        CLOCK_Enable_SysOsc(true);
+    }
+    /* Enable power VD3 for PLLs */
+    POWER_SetPLL();
+    /* Power off PLL during setup changes */
+    POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+    pSetup->flags = flagcfg;
+
+    /* Write PLL setup data */
+    SYSCON->AUDPLLCTRL = pSetup->pllctrl;
+    SYSCON->AUDPLLNDEC = pSetup->pllndec;
+    SYSCON->AUDPLLNDEC = pSetup->pllndec | (1UL << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
+    SYSCON->AUDPLLPDEC = pSetup->pllpdec;
+    SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1UL << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
+    SYSCON->AUDPLLMDEC = pSetup->pllmdec;
+    SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(0); /* enable fractional function */
+    SYSCON->AUDPLLFRAC = pSetup->audpllfrac;
+    SYSCON->AUDPLLFRAC = pSetup->audpllfrac | (1UL << SYSCON_AUDPLLFRAC_REQ_SHIFT);
+
+    /* Enable peripheral states by setting low */
+    POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+    {
+        while (CLOCK_IsAudioPLLLocked() == false)
+        {
+        }
+    }
+
+    /* Update current programmed PLL rate var */
+    CLOCK_GetAudioPLLOutFromAudioFracSetupUpdate(pSetup);
+
+    return kStatus_PLL_Success;
+}
+
+/* Set Audio PLL output based on the passed Audio PLL setup data */
+/*! brief       Set AUDIO PLL output based on the passed AUDIO PLL setup data
+ *  param       pControl        : Pointer to populated PLL control structure to generate setup with
+ *  param       pSetup          : Pointer to PLL setup structure to be filled
+ *  return      PLL_ERROR_SUCCESS on success, or PLL setup error code
+ *  note        Actual frequency for setup may vary from the desired frequency based on the
+ *  accuracy of input clocks, rounding, non-fractional PLL mode, etc.
+ */
+pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup)
+{
+    uint32_t inRate;
+    pll_error_t pllError;
+
+    /* Determine input rate for the PLL */
+    if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U)
+    {
+        inRate = pControl->inputRate;
+    }
+    else
+    {
+        inRate = CLOCK_GetAudioPLLInClockRate();
+    }
+
+    /* PLL flag options */
+    pllError        = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup);
+    pSetup->pllRate = pControl->desiredRate;
+    return pllError;
+}
+
+/* Setup PLL Frequency from pre-calculated value */
+/**
+ * brief        Set PLL output from PLL setup structure (precise frequency)
+ * param        pSetup  : Pointer to populated PLL setup structure
+ * return       kStatus_PLL_Success on success, or PLL setup error code
+ * note This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup)
+{
+    if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U)
+    {
+        /* Turn on the ext clock if system pll input select clk_in */
+        CLOCK_Enable_SysOsc(true);
+    }
+    /* Enable power VD3 for PLLs */
+    POWER_SetPLL();
+    /* Power off PLL during setup changes */
+    POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0);
+
+    /* Write PLL setup data */
+    SYSCON->SYSPLLCTRL = pSetup->pllctrl;
+    SYSCON->SYSPLLNDEC = pSetup->pllndec;
+    SYSCON->SYSPLLNDEC = pSetup->pllndec | (1UL << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
+    SYSCON->SYSPLLPDEC = pSetup->pllpdec;
+    SYSCON->SYSPLLPDEC = pSetup->pllpdec | (1UL << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
+    SYSCON->SYSPLLMDEC = pSetup->pllmdec;
+    SYSCON->SYSPLLMDEC = pSetup->pllmdec | (1UL << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */
+
+    /* Flags for lock or power on */
+    if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)
+    {
+        /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
+        uint32_t maxCCO    = (1UL << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
+        uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1UL << 17U);
+
+        /* Initialize  and power up PLL */
+        SYSCON->SYSPLLMDEC = maxCCO;
+        POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
+
+        /* Set mreq to activate */
+        SYSCON->SYSPLLMDEC = maxCCO | (1UL << 17U);
+
+        /* Delay for 72 uSec @ 12Mhz */
+        SDK_DelayAtLeastUs(72U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+
+        /* clear mreq to prepare for restoring mreq */
+        SYSCON->SYSPLLMDEC = curSSCTRL;
+
+        /* set original value back and activate */
+        SYSCON->SYSPLLMDEC = curSSCTRL | (1UL << 17U);
+
+        /* Enable peripheral states by setting low */
+        POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
+    }
+    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+    {
+        while (CLOCK_IsSystemPLLLocked() == false)
+        {
+        }
+    }
+
+    /* Update current programmed PLL rate var */
+    s_Pll_Freq = pSetup->pllRate;
+
+    return kStatus_PLL_Success;
+}
+
+/* Setup Audio PLL Frequency from pre-calculated value */
+/**
+ * brief        Set Audio PLL output from Audio PLL setup structure (precise frequency)
+ * param        pSetup  : Pointer to populated PLL setup structure
+ * return       kStatus_PLL_Success on success, or Audio PLL setup error code
+ * note This function will power off the PLL, setup the Audio PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the Audio PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup)
+{
+    if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U)
+    {
+        /* Turn on the ext clock if system pll input select clk_in */
+        CLOCK_Enable_SysOsc(true);
+    }
+    /* Enable power VD3 for PLLs */
+    POWER_SetPLL();
+    /* Power off Audio PLL during setup changes */
+    POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+    /* Write Audio PLL setup data */
+    SYSCON->AUDPLLCTRL = pSetup->pllctrl;
+    SYSCON->AUDPLLFRAC = pSetup->audpllfrac;
+    SYSCON->AUDPLLFRAC = pSetup->audpllfrac | (1UL << SYSCON_AUDPLLFRAC_REQ_SHIFT); /* latch */
+    SYSCON->AUDPLLNDEC = pSetup->pllndec;
+    SYSCON->AUDPLLNDEC = pSetup->pllndec | (1UL << SYSCON_AUDPLLNDEC_NREQ_SHIFT); /* latch */
+    SYSCON->AUDPLLPDEC = pSetup->pllpdec;
+    SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1UL << SYSCON_AUDPLLPDEC_PREQ_SHIFT); /* latch */
+    SYSCON->AUDPLLMDEC = pSetup->pllmdec;
+    SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1UL << SYSCON_AUDPLLMDEC_MREQ_SHIFT); /* latch */
+    SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1);                            /* disable fractional function */
+
+    /* Flags for lock or power on */
+    if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)
+    {
+        /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
+        uint32_t maxCCO    = (1UL << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
+        uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1UL << 17U);
+
+        /* Initialize  and power up PLL */
+        SYSCON->SYSPLLMDEC = maxCCO;
+        POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+        /* Set mreq to activate */
+        SYSCON->SYSPLLMDEC = maxCCO | (1UL << 17U);
+
+        /* Delay for 72 uSec @ 12Mhz */
+        SDK_DelayAtLeastUs(72U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+
+        /* clear mreq to prepare for restoring mreq */
+        SYSCON->SYSPLLMDEC = curSSCTRL;
+
+        /* set original value back and activate */
+        SYSCON->SYSPLLMDEC = curSSCTRL | (1UL << 17U);
+
+        /* Enable peripheral states by setting low */
+        POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+    }
+    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+    {
+        while (CLOCK_IsAudioPLLLocked() == false)
+        {
+        }
+    }
+
+    /* Update current programmed PLL rate var */
+    s_Audio_Pll_Freq = pSetup->pllRate;
+
+    return kStatus_PLL_Success;
+}
+
+/* Setup USB PLL Frequency from pre-calculated value */
+/**
+ * brief        Set USB PLL output from USB PLL setup structure (precise frequency)
+ * param        pSetup  : Pointer to populated USB PLL setup structure
+ * return       kStatus_PLL_Success on success, or USB PLL setup error code
+ * note This function will power off the USB PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock,
+ * and adjust system voltages to the new USB PLL rate. The function will not
+ * alter any source clocks (ie, usb pll clock) that may use the USB PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup)
+{
+    uint32_t usbpllctrl, fccoHz;
+    uint8_t msel, psel, nsel;
+    bool pllDirectInput, pllDirectOutput, pllfbsel;
+
+    msel            = pSetup->msel;
+    psel            = pSetup->psel;
+    nsel            = pSetup->nsel;
+    pllDirectOutput = pSetup->direct;
+    pllDirectInput  = pSetup->bypass;
+    pllfbsel        = pSetup->fbsel;
+
+    /* Input clock into the PLL cannot be lower than this */
+    if (pSetup->inputRate < USB_PLL_LOWER_IN_LIMIT)
+    {
+        return kStatus_PLL_InputTooLow;
+    }
+
+    if (pllfbsel)
+    {
+        /*integer_mode: Fout = M*(Fin/N),  Fcco = 2*P*M*(Fin/N) */
+        fccoHz = (pSetup->inputRate / ((uint32_t)nsel + 1U)) * 2U * (msel + 1U) * SWITCH_USB_PSEL(psel);
+
+        /* USB PLL CCO out rate cannot be lower than this */
+        if (fccoHz < USB_PLL_MIN_CCO_FREQ_MHZ)
+        {
+            return kStatus_PLL_CCOTooLow;
+        }
+        /* USB PLL CCO out rate cannot be Higher than this */
+        if (fccoHz > USB_PLL_MAX_CCO_FREQ_MHZ)
+        {
+            return kStatus_PLL_CCOTooHigh;
+        }
+    }
+    else
+    {
+        /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */
+        fccoHz = pSetup->inputRate / ((uint32_t)nsel + 1U) * (msel + 1U);
+
+        /* USB PLL CCO out rate cannot be lower than this */
+        if (fccoHz < USB_PLL_MIN_CCO_FREQ_MHZ)
+        {
+            return kStatus_PLL_CCOTooLow;
+        }
+        /* USB PLL CCO out rate cannot be Higher than this */
+        if (fccoHz > USB_PLL_MAX_CCO_FREQ_MHZ)
+        {
+            return kStatus_PLL_CCOTooHigh;
+        }
+    }
+
+    /* If configure the USB HOST clock, VD5 power for USB PHY should be enable
+       before the PLL is working */
+    /* Turn on the ext clock for usb pll input */
+    CLOCK_Enable_SysOsc(true);
+
+    /* Enable power VD3 for PLLs */
+    POWER_SetPLL();
+
+    /* Power on the VD5 for USB PHY */
+    POWER_SetUsbPhy();
+
+    /* Power off USB PLL during setup changes */
+    POWER_EnablePD(kPDRUNCFG_PD_USB_PLL);
+
+    /* Write USB PLL setup data */
+    usbpllctrl = USB_PLL_NSEL_VAL_SET(nsel) |                                  /* NSEL VALUE */
+                 USB_PLL_PSEL_VAL_SET(psel) |                                  /* PSEL VALUE */
+                 USB_PLL_MSEL_VAL_SET(msel) |                                  /* MSEL VALUE */
+                 (uint32_t)pllDirectInput << SYSCON_USBPLLCTRL_BYPASS_SHIFT |  /* BYPASS DISABLE */
+                 (uint32_t)pllDirectOutput << SYSCON_USBPLLCTRL_DIRECT_SHIFT | /* DIRECTO DISABLE */
+                 (uint32_t)pllfbsel << SYSCON_USBPLLCTRL_FBSEL_SHIFT;          /* FBSEL SELECT */
+
+    SYSCON->USBPLLCTRL = usbpllctrl;
+
+    POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);
+
+    /* Delay for 72 uSec @ 12Mhz for the usb pll to lock */
+    SDK_DelayAtLeastUs(72U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+    if (false == pllDirectInput)
+    {
+        while (CLOCK_IsUsbPLLLocked() == false)
+        {
+        }
+    }
+    CLOCK_GetUsbPLLOutFromSetupUpdate(pSetup);
+    return kStatus_PLL_Success;
+}
+
+/* Set System PLL clock based on the input frequency and multiplier */
+/*! brief       Set PLL output based on the multiplier and input frequency
+ * param        multiply_by     : multiplier
+ * param        input_freq      : Clock input frequency of the PLL
+ * return       Nothing
+ * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
+ * function does not disable or enable PLL power, wait for PLL lock,
+ * or adjust system voltages. These must be done in the application.
+ * The function will not alter any source clocks (ie, main systen clock)
+ * that may use the PLL, so these should be setup prior to and after
+ * exiting the function.
+ */
+void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq)
+{
+    uint32_t cco_freq = input_freq * multiply_by;
+    uint32_t pdec     = 1U;
+    uint32_t selr;
+    uint32_t seli;
+    uint32_t selp;
+    uint32_t mdec, ndec;
+
+    uint32_t directo = SYSCON_SYSPLLCTRL_DIRECTO(1);
+
+    while (cco_freq < 275000000U)
+    {
+        multiply_by <<= 1U; /* double value in each iteration */
+        pdec <<= 1U;        /* correspondingly double pdec to cancel effect of double msel */
+        cco_freq = input_freq * multiply_by;
+    }
+    selr = 0U;
+    if (multiply_by < 60U)
+    {
+        seli = (multiply_by & 0x3cU) + 4U;
+        selp = (multiply_by >> 1U) + 1U;
+    }
+    else
+    {
+        selp = 31U;
+        if (multiply_by > 16384U)
+        {
+            seli = 1U;
+        }
+        else if (multiply_by > 8192U)
+        {
+            seli = 2U;
+        }
+        else if (multiply_by > 2048U)
+        {
+            seli = 4U;
+        }
+        else if (multiply_by >= 501U)
+        {
+            seli = 8U;
+        }
+        else
+        {
+            seli = 4U * (1024U / (multiply_by + 9U));
+        }
+    }
+
+    if (pdec > 1U)
+    {
+        directo = 0U;        /* use post divider */
+        pdec    = pdec / 2U; /* Account for minus 1 encoding */
+                             /* Translate P value */
+        switch (pdec)
+        {
+            case 1U:
+                pdec = 0x62U; /* 1  * 2 */
+                break;
+            case 2U:
+                pdec = 0x42U; /* 2  * 2 */
+                break;
+            case 4U:
+                pdec = 0x02U; /* 4  * 2 */
+                break;
+            case 8U:
+                pdec = 0x0bU; /* 8  * 2 */
+                break;
+            case 16U:
+                pdec = 0x11U; /* 16 * 2 */
+                break;
+            case 32U:
+                pdec = 0x08U; /* 32 * 2 */
+                break;
+            default:
+                pdec = 0x08U;
+                break;
+        }
+    }
+
+    mdec = PLL_MDEC_VAL_SET(pllEncodeM(multiply_by));
+    ndec = 0x302U; /* pre divide by 1 (hardcoded) */
+
+    SYSCON->SYSPLLCTRL = directo | (selr << SYSCON_SYSPLLCTRL_SELR_SHIFT) | (seli << SYSCON_SYSPLLCTRL_SELI_SHIFT) |
+                         (selp << SYSCON_SYSPLLCTRL_SELP_SHIFT);
+    SYSCON->SYSPLLPDEC = pdec | (1U << 7U);   /* set Pdec value and assert preq */
+    SYSCON->SYSPLLNDEC = ndec | (1UL << 10U); /* set Pdec value and assert preq */
+    SYSCON->SYSPLLMDEC = (1UL << 17U) | mdec; /* select non sscg MDEC value, assert mreq and select mdec value */
+}
+
+/* Enable USB DEVICE FULL SPEED clock */
+/*! brief Enable USB Device FS clock.
+ * param        src     : clock source
+ * param        freq: clock frequency
+ * Enable USB Device Full Speed clock.
+ */
+bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq)
+{
+    bool ret = true;
+
+    CLOCK_DisableClock(kCLOCK_Usbd0);
+
+    if (kCLOCK_UsbSrcFro == src)
+    {
+        switch (freq)
+        {
+            case 96000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */
+                break;
+
+            case 48000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */
+                break;
+
+            default:
+                ret = false;
+                break;
+        }
+        /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
+        SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01UL << 15U) | (0xFUL << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
+                          SYSCON_FROCTRL_USBCLKADJ_MASK;
+        /* Select FRO 96 or 48 MHz */
+        CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
+    }
+    else
+    {
+        /*Set the USB PLL as the Usb0 CLK*/
+        POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);
+
+        usb_pll_setup_t pll_setup = {0x3FU, 0x01U, 0x03U, false, false, false, 12000000U};
+
+        (void)CLOCK_SetUsbPLLFreq(&pll_setup);
+        CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false);
+        CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK);
+        SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+    }
+    CLOCK_EnableClock(kCLOCK_Usbd0);
+    CLOCK_EnableClock(kCLOCK_UsbRam1);
+
+    return ret;
+}
+
+/* Enable USB HOST FULL SPEED clock */
+/*! brief Enable USB HOST FS clock.
+ * param        src     : clock source
+ * param        freq: clock frequency
+ * Enable USB HOST Full Speed clock.
+ */
+bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq)
+{
+    bool ret = true;
+
+    CLOCK_DisableClock(kCLOCK_Usbhmr0);
+    CLOCK_DisableClock(kCLOCK_Usbhsl0);
+
+    if (kCLOCK_UsbSrcFro == src)
+    {
+        switch (freq)
+        {
+            case 96000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */
+                break;
+
+            case 48000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */
+                break;
+
+            default:
+                ret = false;
+                break;
+        }
+        /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
+        SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01UL << 15U) | (0xFUL << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
+                          SYSCON_FROCTRL_USBCLKADJ_MASK;
+        /* Select FRO 96 or 48 MHz */
+        CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
+    }
+    else
+    {
+        /*Set the USB PLL as the Usb0 CLK*/
+        POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);
+
+        usb_pll_setup_t pll_setup = {0x3FU, 0x01U, 0x03U, false, false, false, 12000000U};
+
+        (void)CLOCK_SetUsbPLLFreq(&pll_setup);
+        CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false);
+        CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK);
+        SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+    }
+    CLOCK_EnableClock(kCLOCK_Usbhmr0);
+    CLOCK_EnableClock(kCLOCK_Usbhsl0);
+    CLOCK_EnableClock(kCLOCK_UsbRam1);
+
+    return ret;
+}
+
+/* Enable USB DEVICE HIGH SPEED clock */
+/*! brief Enable USB Device HS clock.
+ * param        src     : clock source
+ * param        freq: clock frequency
+ * Enable USB Device High Speed clock.
+ */
+bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq)
+{
+    bool ret = true;
+    CLOCK_DisableClock(kCLOCK_Usbd1);
+    /* Power on the VD5 for USB PHY */
+    POWER_SetUsbPhy();
+    if (kCLOCK_UsbSrcFro == src)
+    {
+        switch (freq)
+        {
+            case 96000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */
+                break;
+
+            case 48000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */
+                break;
+
+            default:
+                ret = false;
+                break;
+        }
+        /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
+        SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01UL << 15U) | (0xFUL << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
+                          SYSCON_FROCTRL_USBCLKADJ_MASK;
+        /* Select FRO 96 or 48 MHz */
+        CLOCK_AttachClk(kFRO_HF_to_USB1_CLK);
+    }
+    else
+    {
+        SDK_DelayAtLeastUs(50, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+        usb_pll_setup_t pll_setup = {0x3FU, 0x01U, 0x03U, false, false, false, 12000000U};
+
+        (void)CLOCK_SetUsbPLLFreq(&pll_setup);
+
+        /* Select USB PLL output as USB clock src */
+        CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false);
+        CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK);
+    }
+
+    SDK_DelayAtLeastUs(50, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+    /* Enable USB1D and USB1RAM */
+    CLOCK_EnableClock(kCLOCK_Usbd1);
+    CLOCK_EnableClock(kCLOCK_UsbRam1);
+    POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* Turn on power for USB PHY */
+    return ret;
+}
+
+/* Enable USB HOST HIGH SPEED clock */
+/*! brief Enable USB HOST HS clock.
+ * param        src     : clock source
+ * param        freq: clock frequency
+ * Enable USB HOST High Speed clock.
+ */
+bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq)
+{
+    bool ret = true;
+    CLOCK_DisableClock(kCLOCK_Usbh1);
+    /* Power on the VD5 for USB PHY */
+    POWER_SetUsbPhy();
+    if (kCLOCK_UsbSrcFro == src)
+    {
+        switch (freq)
+        {
+            case 96000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */
+                break;
+
+            case 48000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */
+                break;
+
+            default:
+                ret = false;
+                break;
+        }
+        /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
+        SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01UL << 15U) | (0xFUL << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
+                          SYSCON_FROCTRL_USBCLKADJ_MASK;
+        /* Select FRO 96 or 48 MHz */
+        CLOCK_AttachClk(kFRO_HF_to_USB1_CLK);
+    }
+    else
+    {
+        SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+        usb_pll_setup_t pll_setup = {0x3FU, 0x01U, 0x03U, false, false, false, 12000000U};
+
+        (void)CLOCK_SetUsbPLLFreq(&pll_setup);
+
+        /* Select USB PLL output as USB clock src */
+        CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false);
+        CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK);
+    }
+
+    SDK_DelayAtLeastUs(50, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+    /* Enable USBh1 and USB1RAM */
+    CLOCK_EnableClock(kCLOCK_Usbh1);
+    CLOCK_EnableClock(kCLOCK_UsbRam1);
+    POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* Turn on power for USB PHY */
+    return ret;
+}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_clock.h
new file mode 100644
index 000000000..381562c22
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_clock.h
@@ -0,0 +1,1293 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 - 2019 , NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_CLOCK_H_
+#define _FSL_CLOCK_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup clock */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *****************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief CLOCK driver version 2.3.1. */
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
+/*@}*/
+
+/*! @brief Configure whether driver controls clock
+ *
+ * When set to 0, peripheral drivers will enable clock in initialize function
+ * and disable clock in de-initialize function. When set to 1, peripheral
+ * driver will not control the clock, application could control the clock out of
+ * the driver.
+ *
+ * @note All drivers share this feature switcher. If it is set to 1, application
+ * should handle clock enable and disable for all drivers.
+ */
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
+#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
+#endif
+
+/*!
+ * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
+ *
+ * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
+ * would cache the recent calulation and accelerate the execution to get the
+ * right settings.
+ */
+#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
+#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
+#endif
+
+/* Definition for delay API in clock driver, users can redefine it to the real application. */
+#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
+#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (180000000UL)
+#endif
+
+/*! @brief Clock ip name array for ADC. */
+#define ADC_CLOCKS  \
+    {               \
+        kCLOCK_Adc0 \
+    }
+/*! @brief Clock ip name array for ROM. */
+#define ROM_CLOCKS \
+    {              \
+        kCLOCK_Rom \
+    }
+/*! @brief Clock ip name array for SRAM. */
+#define SRAM_CLOCKS                              \
+    {                                            \
+        kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \
+    }
+/*! @brief Clock ip name array for FLASH. */
+#define FLASH_CLOCKS \
+    {                \
+        kCLOCK_Flash \
+    }
+/*! @brief Clock ip name array for FMC. */
+#define FMC_CLOCKS \
+    {              \
+        kCLOCK_Fmc \
+    }
+/*! @brief Clock ip name array for EEPROM. */
+#define EEPROM_CLOCKS \
+    {                 \
+        kCLOCK_Eeprom \
+    }
+/*! @brief Clock ip name array for SPIFI. */
+#define SPIFI_CLOCKS \
+    {                \
+        kCLOCK_Spifi \
+    }
+/*! @brief Clock ip name array for INPUTMUX. */
+#define INPUTMUX_CLOCKS \
+    {                   \
+        kCLOCK_InputMux \
+    }
+/*! @brief Clock ip name array for IOCON. */
+#define IOCON_CLOCKS \
+    {                \
+        kCLOCK_Iocon \
+    }
+/*! @brief Clock ip name array for GPIO. */
+#define GPIO_CLOCKS                                                                        \
+    {                                                                                      \
+        kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
+    }
+/*! @brief Clock ip name array for PINT. */
+#define PINT_CLOCKS \
+    {               \
+        kCLOCK_Pint \
+    }
+/*! @brief Clock ip name array for GINT. */
+#define GINT_CLOCKS              \
+    {                            \
+        kCLOCK_Gint, kCLOCK_Gint \
+    }
+/*! @brief Clock ip name array for DMA. */
+#define DMA_CLOCKS \
+    {              \
+        kCLOCK_Dma \
+    }
+/*! @brief Clock ip name array for CRC. */
+#define CRC_CLOCKS \
+    {              \
+        kCLOCK_Crc \
+    }
+/*! @brief Clock ip name array for WWDT. */
+#define WWDT_CLOCKS \
+    {               \
+        kCLOCK_Wwdt \
+    }
+/*! @brief Clock ip name array for RTC. */
+#define RTC_CLOCKS \
+    {              \
+        kCLOCK_Rtc \
+    }
+/*! @brief Clock ip name array for ADC0. */
+#define ADC0_CLOCKS \
+    {               \
+        kCLOCK_Adc0 \
+    }
+/*! @brief Clock ip name array for MRT. */
+#define MRT_CLOCKS \
+    {              \
+        kCLOCK_Mrt \
+    }
+/*! @brief Clock ip name array for RIT. */
+#define RIT_CLOCKS \
+    {              \
+        kCLOCK_Rit \
+    }
+/*! @brief Clock ip name array for SCT0. */
+#define SCT_CLOCKS  \
+    {               \
+        kCLOCK_Sct0 \
+    }
+/*! @brief Clock ip name array for MCAN. */
+#define MCAN_CLOCKS                \
+    {                              \
+        kCLOCK_Mcan0, kCLOCK_Mcan1 \
+    }
+/*! @brief Clock ip name array for UTICK. */
+#define UTICK_CLOCKS \
+    {                \
+        kCLOCK_Utick \
+    }
+/*! @brief Clock ip name array for FLEXCOMM. */
+#define FLEXCOMM_CLOCKS                                                                                             \
+    {                                                                                                               \
+        kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
+            kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_FlexComm8, kCLOCK_FlexComm9, kCLOCK_FlexComm10               \
+    }
+/*! @brief Clock ip name array for LPUART. */
+#define LPUART_CLOCKS                                                                                         \
+    {                                                                                                         \
+        kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
+            kCLOCK_MinUart6, kCLOCK_MinUart7, kCLOCK_MinUart8, kCLOCK_MinUart9                                \
+    }
+
+/*! @brief Clock ip name array for BI2C. */
+#define BI2C_CLOCKS                                                                                       \
+    {                                                                                                     \
+        kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, \
+            kCLOCK_BI2c7, kCLOCK_BI2c8, kCLOCK_BI2c9                                                      \
+    }
+/*! @brief Clock ip name array for LSPI. */
+#define LPSI_CLOCKS                                                                                       \
+    {                                                                                                     \
+        kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, \
+            kCLOCK_LSpi7, kCLOCK_LSpi8, kCLOCK_LSpi9                                                      \
+    }
+/*! @brief Clock ip name array for FLEXI2S. */
+#define FLEXI2S_CLOCKS                                                                                        \
+    {                                                                                                         \
+        kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
+            kCLOCK_FlexI2s6, kCLOCK_FlexI2s7, kCLOCK_FlexI2s8, kCLOCK_FlexI2s9                                \
+    }
+/*! @brief Clock ip name array for DMIC. */
+#define DMIC_CLOCKS \
+    {               \
+        kCLOCK_DMic \
+    }
+/*! @brief Clock ip name array for CT32B. */
+#define CTIMER_CLOCKS                                                             \
+    {                                                                             \
+        kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
+    }
+/*! @brief Clock ip name array for LCD. */
+#define LCD_CLOCKS \
+    {              \
+        kCLOCK_Lcd \
+    }
+/*! @brief Clock ip name array for SDIO. */
+#define SDIO_CLOCKS \
+    {               \
+        kCLOCK_Sdio \
+    }
+/*! @brief Clock ip name array for USBRAM. */
+#define USBRAM_CLOCKS  \
+    {                  \
+        kCLOCK_UsbRam1 \
+    }
+/*! @brief Clock ip name array for EMC. */
+#define EMC_CLOCKS \
+    {              \
+        kCLOCK_Emc \
+    }
+/*! @brief Clock ip name array for ETH. */
+#define ETH_CLOCKS \
+    {              \
+        kCLOCK_Eth \
+    }
+/*! @brief Clock ip name array for AES. */
+#define AES_CLOCKS \
+    {              \
+        kCLOCK_Aes \
+    }
+/*! @brief Clock ip name array for OTP. */
+#define OTP_CLOCKS \
+    {              \
+        kCLOCK_Otp \
+    }
+/*! @brief Clock ip name array for RNG. */
+#define RNG_CLOCKS \
+    {              \
+        kCLOCK_Rng \
+    }
+/*! @brief Clock ip name array for USBHMR0. */
+#define USBHMR0_CLOCKS \
+    {                  \
+        kCLOCK_Usbhmr0 \
+    }
+/*! @brief Clock ip name array for USBHSL0. */
+#define USBHSL0_CLOCKS \
+    {                  \
+        kCLOCK_Usbhsl0 \
+    }
+/*! @brief Clock ip name array for SHA0. */
+#define SHA0_CLOCKS \
+    {               \
+        kCLOCK_Sha0 \
+    }
+/*! @brief Clock ip name array for SMARTCARD. */
+#define SMARTCARD_CLOCKS                     \
+    {                                        \
+        kCLOCK_SmartCard0, kCLOCK_SmartCard1 \
+    }
+/*! @brief Clock ip name array for USBD. */
+#define USBD_CLOCKS                              \
+    {                                            \
+        kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
+    }
+/*! @brief Clock ip name array for USBH. */
+#define USBH_CLOCKS  \
+    {                \
+        kCLOCK_Usbh1 \
+    }
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
+/*------------------------------------------------------------------------------
+ clock_ip_name_t definition:
+------------------------------------------------------------------------------*/
+
+#define CLK_GATE_REG_OFFSET_SHIFT 8U
+#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
+#define CLK_GATE_BIT_SHIFT_SHIFT 0U
+#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
+
+#define CLK_GATE_DEFINE(reg_offset, bit_shift)                                  \
+    ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
+     (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
+
+#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
+#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
+
+#define AHB_CLK_CTRL0 0
+#define AHB_CLK_CTRL1 1
+#define AHB_CLK_CTRL2 2
+#define ASYNC_CLK_CTRL0 3
+
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
+typedef enum _clock_ip_name
+{
+    kCLOCK_IpInvalid  = 0U,
+    kCLOCK_Rom        = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
+    kCLOCK_Sram1      = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
+    kCLOCK_Sram2      = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
+    kCLOCK_Sram3      = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),
+    kCLOCK_Spifi      = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10),
+    kCLOCK_InputMux   = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
+    kCLOCK_Iocon      = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
+    kCLOCK_Gpio0      = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
+    kCLOCK_Gpio1      = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
+    kCLOCK_Gpio2      = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),
+    kCLOCK_Gpio3      = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),
+    kCLOCK_Pint       = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
+    kCLOCK_Gint       = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),
+    kCLOCK_Dma        = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
+    kCLOCK_Crc        = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
+    kCLOCK_Wwdt       = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
+    kCLOCK_Rtc        = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
+    kCLOCK_Adc0       = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
+    kCLOCK_Mrt        = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
+    kCLOCK_Rit        = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),
+    kCLOCK_Sct0       = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
+    kCLOCK_Mcan0      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7),
+    kCLOCK_Mcan1      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8),
+    kCLOCK_Utick      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
+    kCLOCK_FlexComm0  = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_FlexComm1  = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_FlexComm2  = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_FlexComm3  = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_FlexComm4  = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_FlexComm5  = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_FlexComm6  = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_FlexComm7  = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_MinUart0   = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_MinUart1   = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_MinUart2   = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_MinUart3   = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_MinUart4   = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_MinUart5   = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_MinUart6   = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_MinUart7   = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_LSpi0      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_LSpi1      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_LSpi2      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_LSpi3      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_LSpi4      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_LSpi5      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_LSpi6      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_LSpi7      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_BI2c0      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_BI2c1      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_BI2c2      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_BI2c3      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_BI2c4      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_BI2c5      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_BI2c6      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_BI2c7      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_FlexI2s0   = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_FlexI2s1   = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_FlexI2s2   = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_FlexI2s3   = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_FlexI2s4   = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_FlexI2s5   = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_FlexI2s6   = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_FlexI2s7   = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_DMic       = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19),
+    kCLOCK_Ct32b2     = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
+    kCLOCK_Usbd0      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
+    kCLOCK_Ct32b0     = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
+    kCLOCK_Ct32b1     = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
+    kCLOCK_BodyBias0  = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29),
+    kCLOCK_EzhArchB0  = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
+    kCLOCK_Lcd        = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),
+    kCLOCK_Sdio       = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3),
+    kCLOCK_Usbh1      = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),
+    kCLOCK_Usbd1      = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),
+    kCLOCK_UsbRam1    = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),
+    kCLOCK_Emc        = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),
+    kCLOCK_Eth        = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8),
+    kCLOCK_Gpio4      = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9),
+    kCLOCK_Gpio5      = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10),
+    kCLOCK_Aes        = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11),
+    kCLOCK_Otp        = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12),
+    kCLOCK_Rng        = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),
+    kCLOCK_FlexComm8  = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+    kCLOCK_FlexComm9  = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+    kCLOCK_MinUart8   = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+    kCLOCK_MinUart9   = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+    kCLOCK_LSpi8      = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+    kCLOCK_LSpi9      = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+    kCLOCK_BI2c8      = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+    kCLOCK_BI2c9      = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+    kCLOCK_FlexI2s8   = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+    kCLOCK_FlexI2s9   = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+    kCLOCK_Usbhmr0    = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),
+    kCLOCK_Usbhsl0    = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),
+    kCLOCK_Sha0       = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),
+    kCLOCK_SmartCard0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19),
+    kCLOCK_SmartCard1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),
+    kCLOCK_FlexComm10 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21),
+
+    kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13),
+    kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14)
+} clock_ip_name_t;
+
+/*! @brief Clock name used to get clock frequency. */
+typedef enum _clock_name
+{
+    kCLOCK_CoreSysClk,  /*!< Core/system clock  (aka MAIN_CLK)                       */
+    kCLOCK_BusClk,      /*!< Bus clock (AHB clock)                                   */
+    kCLOCK_ClockOut,    /*!< CLOCKOUT                                                */
+    kCLOCK_FroHf,       /*!< FRO48/96                                                */
+    kCLOCK_UsbPll,      /*!< USB1 PLL                                                */
+    kCLOCK_Mclk,        /*!< MCLK                                                    */
+    kCLOCK_Fro12M,      /*!< FRO12M                                                  */
+    kCLOCK_ExtClk,      /*!< External Clock                                          */
+    kCLOCK_PllOut,      /*!< PLL Output                                              */
+    kCLOCK_UsbClk,      /*!< USB input                                               */
+    kCLOCK_WdtOsc,      /*!< Watchdog Oscillator                                     */
+    kCLOCK_Frg,         /*!< Frg Clock                                               */
+    kCLOCK_AsyncApbClk, /*!< Async APB clock                                         */
+} clock_name_t;
+
+/**
+ * Clock source selections for the asynchronous APB clock
+ */
+typedef enum _async_clock_src
+{
+    kCLOCK_AsyncMainClk = 0, /*!< Main System clock */
+    kCLOCK_AsyncFro12Mhz,    /*!< 12MHz FRO */
+    kCLOCK_AsyncAudioPllClk,
+    kCLOCK_AsyncI2cClkFc6,
+
+} async_clock_src_t;
+
+/*! @brief Clock Mux Switches
+ *  The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
+ *  starting from LSB upwards
+ *
+ *  [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
+ *
+ */
+
+#define CLK_ATTACH_ID(mux, sel, pos) ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((pos)*12U))
+#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
+#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
+
+#define GET_ID_ITEM(connection) ((connection)&0xFFFU)
+#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
+#define GET_ID_ITEM_MUX(connection) ((uint8_t)((connection)&0xFFU))
+#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((connection)&0xF00U) >> 8U) - 1U))
+#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
+
+#define CM_STICKCLKSEL 0
+#define CM_MAINCLKSELA 1
+#define CM_MAINCLKSELB 2
+#define CM_CLKOUTCLKSELA 3
+#define CM_SYSPLLCLKSEL 5
+#define CM_AUDPLLCLKSEL 7
+#define CM_SPIFICLKSEL 9
+#define CM_ADCASYNCCLKSEL 10
+#define CM_USB0CLKSEL 11
+#define CM_USB1CLKSEL 12
+#define CM_FXCOMCLKSEL0 13
+#define CM_FXCOMCLKSEL1 14
+#define CM_FXCOMCLKSEL2 15
+#define CM_FXCOMCLKSEL3 16
+#define CM_FXCOMCLKSEL4 17
+#define CM_FXCOMCLKSEL5 18
+#define CM_FXCOMCLKSEL6 19
+#define CM_FXCOMCLKSEL7 20
+#define CM_FXCOMCLKSEL8 21
+#define CM_FXCOMCLKSEL9 22
+#define CM_FXCOMCLKSEL10 23
+#define CM_MCLKCLKSEL 25
+#define CM_FRGCLKSEL 27
+#define CM_DMICCLKSEL 28
+#define CM_SCTCLKSEL 29
+#define CM_LCDCLKSEL 30
+#define CM_SDIOCLKSEL 31
+
+#define CM_ASYNCAPB 32U
+
+typedef enum _clock_attach_id
+{
+
+    kSYSTICK_DIV_CLK_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 0),
+    kWDT_OSC_to_SYSTICKCLK         = MUX_A(CM_STICKCLKSEL, 1),
+    kOSC32K_to_SYSTICKCLK          = MUX_A(CM_STICKCLKSEL, 2),
+    kFRO12M_to_SYSTICKCLK          = MUX_A(CM_STICKCLKSEL, 3),
+    kNONE_to_SYSTICKCLK            = MUX_A(CM_STICKCLKSEL, 7),
+
+    kFRO12M_to_MAIN_CLK  = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),
+    kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),
+    kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),
+    kFRO_HF_to_MAIN_CLK  = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),
+    kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),
+    kOSC32K_to_MAIN_CLK  = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),
+
+    kMAIN_CLK_to_CLKOUT   = MUX_A(CM_CLKOUTCLKSELA, 0),
+    kEXT_CLK_to_CLKOUT    = MUX_A(CM_CLKOUTCLKSELA, 1),
+    kWDT_OSC_to_CLKOUT    = MUX_A(CM_CLKOUTCLKSELA, 2),
+    kFRO_HF_to_CLKOUT     = MUX_A(CM_CLKOUTCLKSELA, 3),
+    kSYS_PLL_to_CLKOUT    = MUX_A(CM_CLKOUTCLKSELA, 4),
+    kUSB_PLL_to_CLKOUT    = MUX_A(CM_CLKOUTCLKSELA, 5),
+    kAUDIO_PLL_to_CLKOUT  = MUX_A(CM_CLKOUTCLKSELA, 6),
+    kOSC32K_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7),
+
+    kFRO12M_to_SYS_PLL  = MUX_A(CM_SYSPLLCLKSEL, 0),
+    kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),
+    kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2),
+    kOSC32K_to_SYS_PLL  = MUX_A(CM_SYSPLLCLKSEL, 3),
+    kNONE_to_SYS_PLL    = MUX_A(CM_SYSPLLCLKSEL, 7),
+
+    kFRO12M_to_AUDIO_PLL  = MUX_A(CM_AUDPLLCLKSEL, 0),
+    kEXT_CLK_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 1),
+    kNONE_to_AUDIO_PLL    = MUX_A(CM_AUDPLLCLKSEL, 7),
+
+    kMAIN_CLK_to_SPIFI_CLK  = MUX_A(CM_SPIFICLKSEL, 0),
+    kSYS_PLL_to_SPIFI_CLK   = MUX_A(CM_SPIFICLKSEL, 1),
+    kUSB_PLL_to_SPIFI_CLK   = MUX_A(CM_SPIFICLKSEL, 2),
+    kFRO_HF_to_SPIFI_CLK    = MUX_A(CM_SPIFICLKSEL, 3),
+    kAUDIO_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 4),
+    kNONE_to_SPIFI_CLK      = MUX_A(CM_SPIFICLKSEL, 7),
+
+    kFRO_HF_to_ADC_CLK    = MUX_A(CM_ADCASYNCCLKSEL, 0),
+    kSYS_PLL_to_ADC_CLK   = MUX_A(CM_ADCASYNCCLKSEL, 1),
+    kUSB_PLL_to_ADC_CLK   = MUX_A(CM_ADCASYNCCLKSEL, 2),
+    kAUDIO_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3),
+    kNONE_to_ADC_CLK      = MUX_A(CM_ADCASYNCCLKSEL, 7),
+
+    kFRO_HF_to_USB0_CLK  = MUX_A(CM_USB0CLKSEL, 0),
+    kSYS_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),
+    kUSB_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 2),
+    kNONE_to_USB0_CLK    = MUX_A(CM_USB0CLKSEL, 7),
+
+    kFRO_HF_to_USB1_CLK  = MUX_A(CM_USB1CLKSEL, 0),
+    kSYS_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 1),
+    kUSB_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 2),
+    kNONE_to_USB1_CLK    = MUX_A(CM_USB1CLKSEL, 7),
+
+    kFRO12M_to_FLEXCOMM0    = MUX_A(CM_FXCOMCLKSEL0, 0),
+    kFRO_HF_to_FLEXCOMM0    = MUX_A(CM_FXCOMCLKSEL0, 1),
+    kAUDIO_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
+    kMCLK_to_FLEXCOMM0      = MUX_A(CM_FXCOMCLKSEL0, 3),
+    kFRG_to_FLEXCOMM0       = MUX_A(CM_FXCOMCLKSEL0, 4),
+    kNONE_to_FLEXCOMM0      = MUX_A(CM_FXCOMCLKSEL0, 7),
+
+    kFRO12M_to_FLEXCOMM1    = MUX_A(CM_FXCOMCLKSEL1, 0),
+    kFRO_HF_to_FLEXCOMM1    = MUX_A(CM_FXCOMCLKSEL1, 1),
+    kAUDIO_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
+    kMCLK_to_FLEXCOMM1      = MUX_A(CM_FXCOMCLKSEL1, 3),
+    kFRG_to_FLEXCOMM1       = MUX_A(CM_FXCOMCLKSEL1, 4),
+    kNONE_to_FLEXCOMM1      = MUX_A(CM_FXCOMCLKSEL1, 7),
+
+    kFRO12M_to_FLEXCOMM2    = MUX_A(CM_FXCOMCLKSEL2, 0),
+    kFRO_HF_to_FLEXCOMM2    = MUX_A(CM_FXCOMCLKSEL2, 1),
+    kAUDIO_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
+    kMCLK_to_FLEXCOMM2      = MUX_A(CM_FXCOMCLKSEL2, 3),
+    kFRG_to_FLEXCOMM2       = MUX_A(CM_FXCOMCLKSEL2, 4),
+    kNONE_to_FLEXCOMM2      = MUX_A(CM_FXCOMCLKSEL2, 7),
+
+    kFRO12M_to_FLEXCOMM3    = MUX_A(CM_FXCOMCLKSEL3, 0),
+    kFRO_HF_to_FLEXCOMM3    = MUX_A(CM_FXCOMCLKSEL3, 1),
+    kAUDIO_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
+    kMCLK_to_FLEXCOMM3      = MUX_A(CM_FXCOMCLKSEL3, 3),
+    kFRG_to_FLEXCOMM3       = MUX_A(CM_FXCOMCLKSEL3, 4),
+    kNONE_to_FLEXCOMM3      = MUX_A(CM_FXCOMCLKSEL3, 7),
+
+    kFRO12M_to_FLEXCOMM4    = MUX_A(CM_FXCOMCLKSEL4, 0),
+    kFRO_HF_to_FLEXCOMM4    = MUX_A(CM_FXCOMCLKSEL4, 1),
+    kAUDIO_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
+    kMCLK_to_FLEXCOMM4      = MUX_A(CM_FXCOMCLKSEL4, 3),
+    kFRG_to_FLEXCOMM4       = MUX_A(CM_FXCOMCLKSEL4, 4),
+    kNONE_to_FLEXCOMM4      = MUX_A(CM_FXCOMCLKSEL4, 7),
+
+    kFRO12M_to_FLEXCOMM5    = MUX_A(CM_FXCOMCLKSEL5, 0),
+    kFRO_HF_to_FLEXCOMM5    = MUX_A(CM_FXCOMCLKSEL5, 1),
+    kAUDIO_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
+    kMCLK_to_FLEXCOMM5      = MUX_A(CM_FXCOMCLKSEL5, 3),
+    kFRG_to_FLEXCOMM5       = MUX_A(CM_FXCOMCLKSEL5, 4),
+    kNONE_to_FLEXCOMM5      = MUX_A(CM_FXCOMCLKSEL5, 7),
+
+    kFRO12M_to_FLEXCOMM6    = MUX_A(CM_FXCOMCLKSEL6, 0),
+    kFRO_HF_to_FLEXCOMM6    = MUX_A(CM_FXCOMCLKSEL6, 1),
+    kAUDIO_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
+    kMCLK_to_FLEXCOMM6      = MUX_A(CM_FXCOMCLKSEL6, 3),
+    kFRG_to_FLEXCOMM6       = MUX_A(CM_FXCOMCLKSEL6, 4),
+    kNONE_to_FLEXCOMM6      = MUX_A(CM_FXCOMCLKSEL6, 7),
+
+    kFRO12M_to_FLEXCOMM7    = MUX_A(CM_FXCOMCLKSEL7, 0),
+    kFRO_HF_to_FLEXCOMM7    = MUX_A(CM_FXCOMCLKSEL7, 1),
+    kAUDIO_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
+    kMCLK_to_FLEXCOMM7      = MUX_A(CM_FXCOMCLKSEL7, 3),
+    kFRG_to_FLEXCOMM7       = MUX_A(CM_FXCOMCLKSEL7, 4),
+    kNONE_to_FLEXCOMM7      = MUX_A(CM_FXCOMCLKSEL7, 7),
+
+    kFRO12M_to_FLEXCOMM8    = MUX_A(CM_FXCOMCLKSEL8, 0),
+    kFRO_HF_to_FLEXCOMM8    = MUX_A(CM_FXCOMCLKSEL8, 1),
+    kAUDIO_PLL_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 2),
+    kMCLK_to_FLEXCOMM8      = MUX_A(CM_FXCOMCLKSEL8, 3),
+    kFRG_to_FLEXCOMM8       = MUX_A(CM_FXCOMCLKSEL8, 4),
+    kNONE_to_FLEXCOMM8      = MUX_A(CM_FXCOMCLKSEL8, 7),
+
+    kFRO12M_to_FLEXCOMM9    = MUX_A(CM_FXCOMCLKSEL9, 0),
+    kFRO_HF_to_FLEXCOMM9    = MUX_A(CM_FXCOMCLKSEL9, 1),
+    kAUDIO_PLL_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 2),
+    kMCLK_to_FLEXCOMM9      = MUX_A(CM_FXCOMCLKSEL9, 3),
+    kFRG_to_FLEXCOMM9       = MUX_A(CM_FXCOMCLKSEL9, 4),
+    kNONE_to_FLEXCOMM9      = MUX_A(CM_FXCOMCLKSEL9, 7),
+
+    kMAIN_CLK_to_FLEXCOMM10  = MUX_A(CM_FXCOMCLKSEL10, 0),
+    kSYS_PLL_to_FLEXCOMM10   = MUX_A(CM_FXCOMCLKSEL10, 1),
+    kUSB_PLL_to_FLEXCOMM10   = MUX_A(CM_FXCOMCLKSEL10, 2),
+    kFRO_HF_to_FLEXCOMM10    = MUX_A(CM_FXCOMCLKSEL10, 3),
+    kAUDIO_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 4),
+    kNONE_to_FLEXCOMM10      = MUX_A(CM_FXCOMCLKSEL10, 7),
+
+    kFRO_HF_to_MCLK    = MUX_A(CM_MCLKCLKSEL, 0),
+    kAUDIO_PLL_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),
+    kNONE_to_MCLK      = MUX_A(CM_MCLKCLKSEL, 7),
+
+    kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0),
+    kSYS_PLL_to_FRG  = MUX_A(CM_FRGCLKSEL, 1),
+    kFRO12M_to_FRG   = MUX_A(CM_FRGCLKSEL, 2),
+    kFRO_HF_to_FRG   = MUX_A(CM_FRGCLKSEL, 3),
+    kNONE_to_FRG     = MUX_A(CM_FRGCLKSEL, 7),
+
+    kFRO12M_to_DMIC     = MUX_A(CM_DMICCLKSEL, 0),
+    kFRO_HF_DIV_to_DMIC = MUX_A(CM_DMICCLKSEL, 1),
+    kAUDIO_PLL_to_DMIC  = MUX_A(CM_DMICCLKSEL, 2),
+    kMCLK_to_DMIC       = MUX_A(CM_DMICCLKSEL, 3),
+    kMAIN_CLK_to_DMIC   = MUX_A(CM_DMICCLKSEL, 4),
+    kWDT_OSC_to_DMIC    = MUX_A(CM_DMICCLKSEL, 5),
+    kNONE_to_DMIC       = MUX_A(CM_DMICCLKSEL, 7),
+
+    kMAIN_CLK_to_SCT_CLK  = MUX_A(CM_SCTCLKSEL, 0),
+    kSYS_PLL_to_SCT_CLK   = MUX_A(CM_SCTCLKSEL, 1),
+    kFRO_HF_to_SCT_CLK    = MUX_A(CM_SCTCLKSEL, 2),
+    kAUDIO_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),
+    kNONE_to_SCT_CLK      = MUX_A(CM_SCTCLKSEL, 7),
+
+    kMAIN_CLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0),
+    kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1),
+    kFRO_HF_to_LCD_CLK   = MUX_A(CM_LCDCLKSEL, 2),
+    kNONE_to_LCD_CLK     = MUX_A(CM_LCDCLKSEL, 3),
+
+    kMAIN_CLK_to_SDIO_CLK  = MUX_A(CM_SDIOCLKSEL, 0),
+    kSYS_PLL_to_SDIO_CLK   = MUX_A(CM_SDIOCLKSEL, 1),
+    kUSB_PLL_to_SDIO_CLK   = MUX_A(CM_SDIOCLKSEL, 2),
+    kFRO_HF_to_SDIO_CLK    = MUX_A(CM_SDIOCLKSEL, 3),
+    kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4),
+    kNONE_to_SDIO_CLK      = MUX_A(CM_SDIOCLKSEL, 7),
+
+    kMAIN_CLK_to_ASYNC_APB    = MUX_A(CM_ASYNCAPB, 0),
+    kFRO12M_to_ASYNC_APB      = MUX_A(CM_ASYNCAPB, 1),
+    kAUDIO_PLL_to_ASYNC_APB   = MUX_A(CM_ASYNCAPB, 2),
+    kI2C_CLK_FC6_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 3),
+    kNONE_to_NONE             = (int)0x80000000U,
+} clock_attach_id_t;
+
+/*  Clock dividers */
+typedef enum _clock_div_name
+{
+    kCLOCK_DivSystickClk    = 0,
+    kCLOCK_DivArmTrClkDiv   = 1,
+    kCLOCK_DivCan0Clk       = 2,
+    kCLOCK_DivCan1Clk       = 3,
+    kCLOCK_DivSmartCard0Clk = 4,
+    kCLOCK_DivSmartCard1Clk = 5,
+    kCLOCK_DivAhbClk        = 32,
+    kCLOCK_DivClkOut        = 33,
+    kCLOCK_DivFrohfClk      = 34,
+    kCLOCK_DivSpifiClk      = 36,
+    kCLOCK_DivAdcAsyncClk   = 37,
+    kCLOCK_DivUsb0Clk       = 38,
+    kCLOCK_DivUsb1Clk       = 39,
+    kCLOCK_DivFrg           = 40,
+    kCLOCK_DivDmicClk       = 42,
+    kCLOCK_DivMClk          = 43,
+    kCLOCK_DivLcdClk        = 44,
+    kCLOCK_DivSctClk        = 45,
+    kCLOCK_DivEmcClk        = 46,
+    kCLOCK_DivSdioClk       = 47
+} clock_div_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+static inline void CLOCK_EnableClock(clock_ip_name_t clk)
+{
+    uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
+    if (index < 3UL)
+    {
+        SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+    }
+    else
+    {
+        SYSCON->ASYNCAPBCTRL             = SYSCON_ASYNCAPBCTRL_ENABLE(1);
+        ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+    }
+}
+
+static inline void CLOCK_DisableClock(clock_ip_name_t clk)
+{
+    uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
+    if (index < 3UL)
+    {
+        SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+    }
+    else
+    {
+        ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+        SYSCON->ASYNCAPBCTRL             = SYSCON_ASYNCAPBCTRL_ENABLE(0);
+    }
+}
+
+/**
+ * @brief
+ *  Initialize the Core clock to given frequency (12, 48 or 96 MHz), this API is implememnt in ROM code.
+ * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed
+ * output is enabled.
+ * Usage: CLOCK_SetupFROClocking(frequency), (frequency must be one of 12, 48 or 96 MHz)
+ *  Note: Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U) before calling this API since this API is
+ * implemented in ROM code and the FROHF TRIM value is stored in OTP
+ *
+ * @param froFreq target fro frequency.
+ * @return   Nothing
+ */
+
+void CLOCK_SetupFROClocking(uint32_t froFreq);
+
+/**
+ * @brief       Configure the clock selection muxes.
+ * @param       connection      : Clock to be configured.
+ * @return      Nothing
+ */
+void CLOCK_AttachClk(clock_attach_id_t connection);
+/**
+ * @brief   Get the actual clock attach id.
+ * This fuction uses the offset in input attach id, then it reads the actual source value in
+ * the register and combine the offset to obtain an actual attach id.
+ * @param   attachId  : Clock attach id to get.
+ * @return  Clock source value.
+ */
+clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
+/**
+ * @brief       Setup peripheral clock dividers.
+ * @param       div_name        : Clock divider name
+ * @param divided_by_value: Value to be divided
+ * @param reset :  Whether to reset the divider counter.
+ * @return      Nothing
+ */
+void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
+
+/*! @brief      Return Frequency of selected clock
+ *  @return     Frequency of selected clock
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clockName);
+/*! @brief      Return Frequency of FRO 12MHz
+ *  @return     Frequency of FRO 12MHz
+ */
+uint32_t CLOCK_GetFro12MFreq(void);
+/*! @brief      Return Frequency of ClockOut
+ *  @return     Frequency of ClockOut
+ */
+uint32_t CLOCK_GetClockOutClkFreq(void);
+/*! @brief      Return Frequency of Spifi Clock
+ *  @return     Frequency of Spifi.
+ */
+uint32_t CLOCK_GetSpifiClkFreq(void);
+/*! @brief      Return Frequency of Adc Clock
+ *  @return     Frequency of Adc Clock.
+ */
+uint32_t CLOCK_GetAdcClkFreq(void);
+/*! brief       Return Frequency of MCAN Clock
+ *  param       MCanSel : 0U: MCAN0; 1U: MCAN1
+ *  return      Frequency of MCAN Clock
+ */
+uint32_t CLOCK_GetMCanClkFreq(uint32_t MCanSel);
+/*! @brief      Return Frequency of Usb0 Clock
+ *  @return     Frequency of Usb0 Clock.
+ */
+uint32_t CLOCK_GetUsb0ClkFreq(void);
+/*! @brief      Return Frequency of Usb1 Clock
+ *  @return     Frequency of Usb1 Clock.
+ */
+uint32_t CLOCK_GetUsb1ClkFreq(void);
+/*! @brief      Return Frequency of MClk Clock
+ *  @return     Frequency of MClk Clock.
+ */
+uint32_t CLOCK_GetMclkClkFreq(void);
+/*! @brief      Return Frequency of SCTimer Clock
+ *  @return     Frequency of SCTimer Clock.
+ */
+uint32_t CLOCK_GetSctClkFreq(void);
+/*! @brief      Return Frequency of SDIO Clock
+ *  @return     Frequency of SDIO Clock.
+ */
+uint32_t CLOCK_GetSdioClkFreq(void);
+/*! @brief      Return Frequency of LCD Clock
+ *  @return     Frequency of LCD Clock.
+ */
+uint32_t CLOCK_GetLcdClkFreq(void);
+/*! @brief      Return Frequency of LCD CLKIN Clock
+ *  @return     Frequency of LCD CLKIN Clock.
+ */
+uint32_t CLOCK_GetLcdClkIn(void);
+/*! @brief      Return Frequency of External Clock
+ *  @return     Frequency of External Clock. If no external clock is used returns 0.
+ */
+uint32_t CLOCK_GetExtClkFreq(void);
+/*! @brief      Return Frequency of Watchdog Oscillator
+ *  @return     Frequency of Watchdog Oscillator
+ */
+uint32_t CLOCK_GetWdtOscFreq(void);
+/*! @brief      Return Frequency of High-Freq output of FRO
+ *  @return     Frequency of High-Freq output of FRO
+ */
+uint32_t CLOCK_GetFroHfFreq(void);
+/*! @brief  Return Frequency of frg
+ *  @return Frequency of FRG
+ */
+uint32_t CLOCK_GetFrgClkFreq(void);
+/*! @brief  Return Frequency of dmic
+ *  @return Frequency of DMIC
+ */
+uint32_t CLOCK_GetDmicClkFreq(void);
+
+/*!
+ * @brief Set FRG Clk
+ * @return
+ *        1: if set FRG CLK successfully.
+ *        0: if set FRG CLK fail.
+ */
+uint32_t CLOCK_SetFRGClock(uint32_t freq);
+
+/*! @brief      Return Frequency of PLL
+ *  @return     Frequency of PLL
+ */
+uint32_t CLOCK_GetPllOutFreq(void);
+/*! @brief      Return Frequency of USB PLL
+ *  @return     Frequency of PLL
+ */
+uint32_t CLOCK_GetUsbPllOutFreq(void);
+/*! @brief      Return Frequency of AUDIO PLL
+ *  @return     Frequency of PLL
+ */
+uint32_t CLOCK_GetAudioPllOutFreq(void);
+/*! @brief      Return Frequency of 32kHz osc
+ *  @return     Frequency of 32kHz osc
+ */
+uint32_t CLOCK_GetOsc32KFreq(void);
+/*! @brief      Return Frequency of Core System
+ *  @return     Frequency of Core System
+ */
+uint32_t CLOCK_GetCoreSysClkFreq(void);
+/*! @brief      Return Frequency of I2S MCLK Clock
+ *  @return     Frequency of I2S MCLK Clock
+ */
+uint32_t CLOCK_GetI2SMClkFreq(void);
+/*! @brief      Return Frequency of Flexcomm functional Clock
+ *  @return     Frequency of Flexcomm functional Clock
+ */
+uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
+
+/*! @brief return FRG Clk
+ *  @return Frequency of FRG CLK.
+ */
+uint32_t CLOCK_GetFRGInputClock(void);
+/*! @brief      Return Asynchronous APB Clock source
+ *  @return     Asynchronous APB CLock source
+ */
+__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)
+{
+    return (async_clock_src_t)(uint32_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3U);
+}
+/*! @brief      Return Frequency of Asynchronous APB Clock
+ *  @return     Frequency of Asynchronous APB Clock Clock
+ */
+uint32_t CLOCK_GetAsyncApbClkFreq(void);
+/*! @brief      Return EMC source
+ *  @return     EMC source
+ */
+__STATIC_INLINE uint32_t CLOCK_GetEmcClkFreq(void)
+{
+    uint32_t freqtmp;
+
+    freqtmp = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
+    return freqtmp / ((SYSCON->EMCCLKDIV & 0xffU) + 1U);
+}
+/*! @brief      Return Audio PLL input clock rate
+ *  @return     Audio PLL input clock rate
+ */
+uint32_t CLOCK_GetAudioPLLInClockRate(void);
+/*! @brief      Return System PLL input clock rate
+ *  @return     System PLL input clock rate
+ */
+uint32_t CLOCK_GetSystemPLLInClockRate(void);
+
+/*! @brief      Return System PLL output clock rate
+ *  @param      recompute       : Forces a PLL rate recomputation if true
+ *  @return     System PLL output clock rate
+ *  @note       The PLL rate is cached in the driver in a variable as
+ *  the rate computation function can take some time to perform. It
+ *  is recommended to use 'false' with the 'recompute' parameter.
+ */
+uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);
+
+/*! @brief      Return System AUDIO PLL output clock rate
+ *  @param      recompute       : Forces a AUDIO PLL rate recomputation if true
+ *  @return     System AUDIO PLL output clock rate
+ *  @note       The AUDIO PLL rate is cached in the driver in a variable as
+ *  the rate computation function can take some time to perform. It
+ *  is recommended to use 'false' with the 'recompute' parameter.
+ */
+uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute);
+
+/*! @brief      Return System USB PLL output clock rate
+ *  @param      recompute       : Forces a USB PLL rate recomputation if true
+ *  @return     System USB PLL output clock rate
+ *  @note       The USB PLL rate is cached in the driver in a variable as
+ *  the rate computation function can take some time to perform. It
+ *  is recommended to use 'false' with the 'recompute' parameter.
+ */
+uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute);
+
+/*! @brief      Enables and disables PLL bypass mode
+ *  @brief      bypass  : true to bypass PLL (PLL output = PLL input, false to disable bypass
+ *  @return     System PLL output clock rate
+ */
+__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)
+{
+    if (bypass)
+    {
+        SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
+    }
+    else
+    {
+        SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
+    }
+}
+
+/*! @brief      Check if PLL is locked or not
+ *  @return     true if the PLL is locked, false if not locked
+ */
+__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)
+{
+    return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0U);
+}
+
+/*! @brief      Check if USB PLL is locked or not
+ *  @return     true if the USB PLL is locked, false if not locked
+ */
+__STATIC_INLINE bool CLOCK_IsUsbPLLLocked(void)
+{
+    return (bool)((SYSCON->USBPLLSTAT & SYSCON_USBPLLSTAT_LOCK_MASK) != 0U);
+}
+
+/*! @brief      Check if AUDIO PLL is locked or not
+ *  @return     true if the AUDIO PLL is locked, false if not locked
+ */
+__STATIC_INLINE bool CLOCK_IsAudioPLLLocked(void)
+{
+    return (bool)((SYSCON->AUDPLLSTAT & SYSCON_AUDPLLSTAT_LOCK_MASK) != 0U);
+}
+
+/*! @brief      Enables and disables SYS OSC
+ *  @brief      enable  : true to enable SYS OSC, false to disable SYS OSC
+ */
+__STATIC_INLINE void CLOCK_Enable_SysOsc(bool enable)
+{
+    if (enable)
+    {
+        SYSCON->PDRUNCFGCLR[0] |= SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
+        SYSCON->PDRUNCFGCLR[1] |= SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
+    }
+
+    else
+    {
+        SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
+        SYSCON->PDRUNCFGSET[1] = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
+    }
+}
+
+/*! @brief Store the current PLL rate
+ *  @param      rate: Current rate of the PLL
+ *  @return     Nothing
+ **/
+void CLOCK_SetStoredPLLClockRate(uint32_t rate);
+
+/*! @brief Store the current AUDIO PLL rate
+ *  @param      rate: Current rate of the PLL
+ *  @return     Nothing
+ **/
+void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate);
+
+/*! @brief PLL configuration structure flags for 'flags' field
+ * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
+ *
+ * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
+ * configuration structure must be assigned with the expected PLL frequency. If the
+ * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
+ * function and the driver will determine the PLL rate from the currently selected
+ * PLL source. This flag might be used to configure the PLL input clock more accurately
+ * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
+ *
+ * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
+ * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
+ * are not used.<br>
+ */
+#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
+#define PLL_CONFIGFLAG_FORCENOFRACT                                                                                   \
+    (1U << 2U) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or \
+                  SS hardware */
+
+/*! @brief PLL configuration structure
+ *
+ * This structure can be used to configure the settings for a PLL
+ * setup structure. Fill in the desired configuration for the PLL
+ * and call the PLL setup function to fill in a PLL setup structure.
+ */
+typedef struct _pll_config
+{
+    uint32_t desiredRate; /*!< Desired PLL rate in Hz */
+    uint32_t inputRate;   /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
+    uint32_t flags;       /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
+} pll_config_t;
+
+/*! @brief PLL setup structure flags for 'flags' field
+ * These flags control how the PLL setup function sets up the PLL
+ */
+#define PLL_SETUPFLAG_POWERUP (1U << 0U)  /*!< Setup will power on the PLL after setup */
+#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
+#define PLL_SETUPFLAG_ADGVOLT (1U << 2U)  /*!< Optimize system voltage for the new PLL rate */
+
+/*! @brief PLL setup structure
+ * This structure can be used to pre-build a PLL setup configuration
+ * at run-time and quickly set the PLL to the configuration. It can be
+ * populated with the PLL setup function. If powering up or waiting
+ * for PLL lock, the PLL input clock source should be configured prior
+ * to PLL setup.
+ */
+typedef struct _pll_setup
+{
+    uint32_t pllctrl;    /*!< PLL control register SYSPLLCTRL */
+    uint32_t pllndec;    /*!< PLL NDEC register SYSPLLNDEC */
+    uint32_t pllpdec;    /*!< PLL PDEC register SYSPLLPDEC */
+    uint32_t pllmdec;    /*!< PLL MDEC registers SYSPLLPDEC */
+    uint32_t pllRate;    /*!< Acutal PLL rate */
+    uint32_t audpllfrac; /*!< only aduio PLL has this function*/
+    uint32_t flags;      /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
+} pll_setup_t;
+
+/*! @brief PLL status definitions
+ */
+typedef enum _pll_error
+{
+    kStatus_PLL_Success         = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
+    kStatus_PLL_OutputTooLow    = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
+    kStatus_PLL_OutputTooHigh   = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
+    kStatus_PLL_InputTooLow     = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
+    kStatus_PLL_InputTooHigh    = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
+    kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
+    kStatus_PLL_CCOTooLow       = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */
+    kStatus_PLL_CCOTooHigh      = MAKE_STATUS(kStatusGroup_Generic, 7)  /*!< Requested CCO rate isn't possible */
+} pll_error_t;
+
+/*! @brief USB clock source definition. */
+typedef enum _clock_usb_src
+{
+    kCLOCK_UsbSrcFro       = (uint32_t)kCLOCK_FroHf,      /*!< Use FRO 96 or 48 MHz. */
+    kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut,     /*!< Use System PLL output. */
+    kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock.    */
+    kCLOCK_UsbSrcUsbPll    = (uint32_t)kCLOCK_UsbPll,     /*!< Use USB PLL clock.    */
+
+    kCLOCK_UsbSrcNone = SYSCON_USB0CLKSEL_SEL(
+        7U) /*!< Use None, this may be selected in order to reduce power when no output is needed.. */
+} clock_usb_src_t;
+
+/*! @brief USB PDEL Divider. */
+typedef enum _usb_pll_psel
+{
+    pSel_Divide_1 = 0U,
+    pSel_Divide_2,
+    pSel_Divide_4,
+    pSel_Divide_8
+} usb_pll_psel;
+
+/*! @brief PLL setup structure
+ * This structure can be used to pre-build a USB PLL setup configuration
+ * at run-time and quickly set the usb PLL to the configuration. It can be
+ * populated with the USB PLL setup function. If powering up or waiting
+ * for USB PLL lock, the PLL input clock source should be configured prior
+ * to USB PLL setup.
+ */
+typedef struct _usb_pll_setup
+{
+    uint8_t msel;       /*!< USB PLL control register msel:1U-256U */
+    uint8_t psel;       /*!< USB PLL control register psel:only support inter 1U 2U 4U 8U */
+    uint8_t nsel;       /*!< USB PLL control register nsel:only suppoet inter 1U 2U 3U 4U */
+    bool direct;        /*!< USB PLL CCO output control */
+    bool bypass;        /*!< USB PLL inout clock bypass control  */
+    bool fbsel;         /*!< USB PLL ineter mode and non-integer mode control*/
+    uint32_t inputRate; /*!< USB PLL input rate */
+} usb_pll_setup_t;
+
+/*! @brief      Return System PLL output clock rate from setup structure
+ *  @param      pSetup  : Pointer to a PLL setup structure
+ *  @return     System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);
+
+/*! @brief      Return System AUDIO PLL output clock rate from setup structure
+ *  @param      pSetup  : Pointer to a PLL setup structure
+ *  @return     System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup);
+
+/*! @brief      Return System AUDIO PLL output clock rate from audio fractioanl setup structure
+ *  @param      pSetup  : Pointer to a PLL setup structure
+ *  @return     System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup);
+
+/*! @brief      Return System USB PLL output clock rate from setup structure
+ *  @param      pSetup  : Pointer to a PLL setup structure
+ *  @return     System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup);
+
+/*! @brief      Set PLL output based on the passed PLL setup data
+ *  @param      pControl        : Pointer to populated PLL control structure to generate setup with
+ *  @param      pSetup          : Pointer to PLL setup structure to be filled
+ *  @return     PLL_ERROR_SUCCESS on success, or PLL setup error code
+ *  @note       Actual frequency for setup may vary from the desired frequency based on the
+ *  accuracy of input clocks, rounding, non-fractional PLL mode, etc.
+ */
+pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
+
+/*! @brief      Set AUDIO PLL output based on the passed AUDIO PLL setup data
+ *  @param      pControl        : Pointer to populated PLL control structure to generate setup with
+ *  @param      pSetup          : Pointer to PLL setup structure to be filled
+ *  @return     PLL_ERROR_SUCCESS on success, or PLL setup error code
+ *  @note       Actual frequency for setup may vary from the desired frequency based on the
+ *  accuracy of input clocks, rounding, non-fractional PLL mode, etc.
+ */
+pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
+
+/*! @brief      Set PLL output from PLL setup structure (precise frequency)
+ * @param       pSetup  : Pointer to populated PLL setup structure
+ * @param flagcfg : Flag configuration for PLL config structure
+ * @return      PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * @note        This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
+
+/*! @brief      Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency)
+ * @param       pSetup  : Pointer to populated PLL setup structure
+ * @param flagcfg : Flag configuration for PLL config structure
+ * @return      PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * @note        This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
+ * and adjust system voltages to the new AUDIOPLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
+
+/*! @brief      Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise
+ * frequency)
+ * @param       pSetup  : Pointer to populated PLL setup structure
+ * @param flagcfg : Flag configuration for PLL config structure
+ * @return      PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * @note        This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
+ * and adjust system voltages to the new AUDIOPLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg);
+
+/**
+ * @brief       Set PLL output from PLL setup structure (precise frequency)
+ * @param       pSetup  : Pointer to populated PLL setup structure
+ * @return      kStatus_PLL_Success on success, or PLL setup error code
+ * @note        This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);
+
+/**
+ * @brief       Set Audio PLL output from Audio PLL setup structure (precise frequency)
+ * @param       pSetup  : Pointer to populated PLL setup structure
+ * @return      kStatus_PLL_Success on success, or Audio PLL setup error code
+ * @note        This function will power off the PLL, setup the Audio PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the Audio PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup);
+
+/**
+ * @brief       Set USB PLL output from USB PLL setup structure (precise frequency)
+ * @param       pSetup  : Pointer to populated USB PLL setup structure
+ * @return      kStatus_PLL_Success on success, or USB PLL setup error code
+ * @note        This function will power off the USB PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock,
+ * and adjust system voltages to the new USB PLL rate. The function will not
+ * alter any source clocks (ie, usb pll clock) that may use the USB PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup);
+
+/*! @brief      Set PLL output based on the multiplier and input frequency
+ * @param       multiply_by     : multiplier
+ * @param       input_freq      : Clock input frequency of the PLL
+ * @return      Nothing
+ * @note        Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
+ * function does not disable or enable PLL power, wait for PLL lock,
+ * or adjust system voltages. These must be done in the application.
+ * The function will not alter any source clocks (ie, main systen clock)
+ * that may use the PLL, so these should be setup prior to and after
+ * exiting the function.
+ */
+void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);
+
+/*! @brief Disable USB clock.
+ *
+ * Disable USB clock.
+ */
+static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
+{
+    CLOCK_DisableClock(clk);
+}
+
+/*! @brief Enable USB Device FS clock.
+ * @param       src     : clock source
+ * @param       freq: clock frequency
+ * Enable USB Device Full Speed clock.
+ */
+bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq);
+
+/*! @brief Enable USB HOST FS clock.
+ * @param       src     : clock source
+ * @param       freq: clock frequency
+ * Enable USB HOST Full Speed clock.
+ */
+bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq);
+
+/*! @brief Set the current Usb PLL Rate
+ */
+void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate);
+
+/*! @brief Enable USB Device HS clock.
+ * @param       src     : clock source
+ * @param       freq: clock frequency
+ * Enable USB Device High Speed clock.
+ */
+bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq);
+
+/*! @brief Enable USB HOST HS clock.
+ * @param       src     : clock source
+ * @param       freq: clock frequency
+ * Enable USB HOST High Speed clock.
+ */
+bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_CLOCK_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_inputmux_connections.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_inputmux_connections.h
new file mode 100644
index 000000000..d7c604b15
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_inputmux_connections.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2017, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_INPUTMUX_CONNECTIONS_
+#define _FSL_INPUTMUX_CONNECTIONS_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections"
+#endif
+
+/*!
+ * @addtogroup inputmux_driver
+ * @{
+ */
+
+/*!
+ * @name Input multiplexing connections
+ * @{
+ */
+
+/*! @brief Periphinmux IDs */
+#define SCT0_PMUX_ID 0x00U
+#define PINTSEL_PMUX_ID 0xC0U
+#define DMA_TRIG0_PMUX_ID 0xE0U
+#define DMA_OTRIG_PMUX_ID 0x160U
+#define FREQMEAS_PMUX_ID 0x180U
+#define PMUX_SHIFT 20U
+
+/*! @brief INPUTMUX connections type */
+typedef enum _inputmux_connection_t
+{
+    /*!< SCT INMUX. */
+    kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_T0Out0ToSct0 = 8U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_T1Out0ToSct0 = 9U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_T2Out0ToSct0 = 10U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_T3Out0ToSct0 = 11U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_T4Out0ToSct0 = 12U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_AdcThcmpIrqToSct0 = 13U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioIntBmatchToSct0 = 14U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_ArmTxevToSct0 = 17U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DebugHaltedToSct0 = 18U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SmartCard0TxActivreToSct0 = 19U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SmartCard0RxActivreToSct0 = 20U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SmartCard1TxActivreToSct0 = 21U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SmartCard1RxActivreToSct0 = 22U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_I2s6SclkToSct0 = 23U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_I2sS7clkToSct0 = 24U + (SCT0_PMUX_ID << PMUX_SHIFT),
+
+    /*!< Frequency measure. */
+    kINPUTMUX_MainOscToFreqmeas = 0U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Fro12MhzToFreqmeas = 1U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Fro96MhzToFreqmeas = 2U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_WdtOscToFreqmeas = 3U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_32KhzOscToFreqmeas = 4U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_MainClkToFreqmeas = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_FreqmeGpioClk_a = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_FreqmeGpioClk_b = 7U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+
+    /*!< Pin Interrupt. */
+    kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    /*!< DMA ITRIG. */
+    kINPUTMUX_Adc0SeqaIrqToDma = 0U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Adc0SeqbIrqToDma = 1U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Sct0DmaReq0ToDma = 2U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Sct0DmaReq1ToDma = 3U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_PinInt0ToDma = 4U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_PinInt1ToDma = 5U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_PinInt2ToDma = 6U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_PinInt3ToDma = 7U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToDma = 8U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToDma = 9U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToDma = 10U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToDma = 11U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToDma = 12U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToDma = 13U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M0ToDma = 14U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToDma = 15U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M0ToDma = 16U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToDma = 17U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Otrig0ToDma = 18U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Otrig1ToDma = 19U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Otrig2ToDma = 20U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Otrig3ToDma = 21U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    /*!< DMA OTRIG. */
+    kINPUTMUX_DmaFlexcomm0RxTrigoutToTriginChannels = 0U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm0TxTrigoutToTriginChannels = 1U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm1RxTrigoutToTriginChannels = 2U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm1TxTrigoutToTriginChannels = 3U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm2RxTrigoutToTriginChannels = 4U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm2TxTrigoutToTriginChannels = 5U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm3RxTrigoutToTriginChannels = 6U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm3TxTrigoutToTriginChannels = 7U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm4RxTrigoutToTriginChannels = 8U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm4TxTrigoutToTriginChannels = 9U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm5RxTrigoutToTriginChannels = 10U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm5TxTrigoutToTriginChannels = 11U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm6RxTrigoutToTriginChannels = 12U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm6TxTrigoutToTriginChannels = 13U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm7RxTrigoutToTriginChannels = 14U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm7TxTrigoutToTriginChannels = 15U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaDmic0Ch0TrigoutToTriginChannels = 16U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Dmamic0Ch1TrigoutToTriginChannels = 17U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaSpifi0TrigoutToTriginChannels = 18U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaSha_TrigoutToTriginChannels = 19U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm8RxTrigoutToTriginChannels = 20U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm8TxTrigoutToTriginChannels = 21U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm9RxTrigoutToTriginChannels = 22U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm9TxTrigoutToTriginChannels = 23U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaSmartcard0RxTrigoutToTriginChannels = 24U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaSmartcard0TxTrigoutToTriginChannels = 25U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaSmartcard1RxTrigoutToTriginChannels = 26U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaSmartcard1TxTrigoutToTriginChannels = 27U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm10RxTrigoutToTriginChannels = 28U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm10TxTrigoutToTriginChannels = 29U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+
+} inputmux_connection_t;
+
+/*@}*/
+
+#endif /* _FSL_INPUTMUX_CONNECTIONS_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_power.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_power.c
new file mode 100644
index 000000000..4d350239c
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_power.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_common.h"
+#include "fsl_power.h"
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.power"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Empty file since implementation is in header file and power library */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_power.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_power.h
new file mode 100644
index 000000000..da73ee56b
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_power.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_POWER_H_
+#define _FSL_POWER_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup power */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief power driver version 2.0.0. */
+#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+#define MAKE_PD_BITS(reg, slot) (((reg) << 8) | (slot))
+#define PDRCFG0 0x0U
+#define PDRCFG1 0x1U
+
+typedef enum pd_bits
+{
+    kPDRUNCFG_LP_REG = MAKE_PD_BITS(PDRCFG0, 2U),
+    kPDRUNCFG_PD_FRO_EN = MAKE_PD_BITS(PDRCFG0, 4U),
+    kPDRUNCFG_PD_TS = MAKE_PD_BITS(PDRCFG0, 6U),
+    kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U),
+    kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U),
+    kPDRUNCFG_PD_VD2_ANA = MAKE_PD_BITS(PDRCFG0, 9U),
+    kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U),
+    kPDRUNCFG_PD_RAM0 = MAKE_PD_BITS(PDRCFG0, 13U),
+    kPDRUNCFG_PD_RAM1 = MAKE_PD_BITS(PDRCFG0, 14U),
+    kPDRUNCFG_PD_RAM2 = MAKE_PD_BITS(PDRCFG0, 15U),
+    kPDRUNCFG_PD_RAM3 = MAKE_PD_BITS(PDRCFG0, 16U),
+    kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U),
+    kPDRUNCFG_PD_VDDA = MAKE_PD_BITS(PDRCFG0, 19U),
+    kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U),
+    kPDRUNCFG_PD_USB0_PHY = MAKE_PD_BITS(PDRCFG0, 21U),
+    kPDRUNCFG_PD_SYS_PLL0 = MAKE_PD_BITS(PDRCFG0, 22U),
+    kPDRUNCFG_PD_VREFP = MAKE_PD_BITS(PDRCFG0, 23U),
+    kPDRUNCFG_PD_FLASH_BG = MAKE_PD_BITS(PDRCFG0, 25U),
+    kPDRUNCFG_PD_VD3 = MAKE_PD_BITS(PDRCFG0, 26U),
+    kPDRUNCFG_PD_VD4 = MAKE_PD_BITS(PDRCFG0, 27U),
+    kPDRUNCFG_PD_VD5 = MAKE_PD_BITS(PDRCFG0, 28U),
+    kPDRUNCFG_PD_VD6 = MAKE_PD_BITS(PDRCFG0, 29U),
+    kPDRUNCFG_REQ_DELAY = MAKE_PD_BITS(PDRCFG0, 30U),
+    kPDRUNCFG_FORCE_RBB = MAKE_PD_BITS(PDRCFG0, 31U),
+
+    kPDRUNCFG_PD_USB1_PHY = MAKE_PD_BITS(PDRCFG1, 0U),
+    kPDRUNCFG_PD_USB_PLL = MAKE_PD_BITS(PDRCFG1, 1U),
+    kPDRUNCFG_PD_AUDIO_PLL = MAKE_PD_BITS(PDRCFG1, 2U),
+    kPDRUNCFG_PD_SYS_OSC = MAKE_PD_BITS(PDRCFG1, 3U),
+    kPDRUNCFG_PD_EEPROM = MAKE_PD_BITS(PDRCFG1, 5U),
+    kPDRUNCFG_PD_rng = MAKE_PD_BITS(PDRCFG1, 6U),
+
+    /*
+    This enum member has no practical meaning,it is used to avoid MISRA issue,
+    user should not trying to use it.
+    */
+    kPDRUNCFG_ForceUnsigned = 0x80000000U,
+} pd_bit_t;
+
+/* Power mode configuration API parameter */
+typedef enum _power_mode_config
+{
+    kPmu_Sleep = 0U,
+    kPmu_Deep_Sleep = 1U,
+    kPmu_Deep_PowerDown = 2U,
+} power_mode_cfg_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+* @name Power Configuration
+* @{
+*/
+
+/*!
+ * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
+ *
+ * @param en    peripheral for which to enable the PDRUNCFG bit
+ * @return none
+ */
+static inline void POWER_EnablePD(pd_bit_t en)
+{
+    /* PDRUNCFGSET */
+    SYSCON->PDRUNCFGSET[((uint32_t)en >> 8UL)] = (1UL << ((uint32_t)en & 0xffU));
+}
+
+/*!
+ * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
+ *
+ * @param en    peripheral for which to disable the PDRUNCFG bit
+ * @return none
+ */
+static inline void POWER_DisablePD(pd_bit_t en)
+{
+    /* PDRUNCFGCLR */
+    SYSCON->PDRUNCFGCLR[((uint32_t)en >> 8UL)] = (1UL << ((uint32_t)en & 0xffU));
+}
+
+/*!
+ * @brief API to enable deep sleep bit in the ARM Core.
+ *
+ * @param none
+ * @return none
+ */
+static inline void POWER_EnableDeepSleep(void)
+{
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+}
+
+/*!
+ * @brief API to disable deep sleep bit in the ARM Core.
+ *
+ * @param none
+ * @return none
+ */
+static inline void POWER_DisableDeepSleep(void)
+{
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+}
+
+/*!
+ * @brief Power Library API to reload OTP.
+ *        This API must be called if VD6 is power down
+ *        and power back again since FROHF TRIM value
+ *        is store in OTP. If not, when calling FROHF settng
+ *        API in clock driver then the FROHF clock out put
+ *        will be inaccurate.
+ * @return none
+ */
+void POWER_OtpReload(void);
+
+/*!
+ * @brief Power Library API to power the PLLs.
+ *
+ * @param none
+ * @return none
+ */
+void POWER_SetPLL(void);
+
+/*!
+ * @brief Power Library API to power the USB PHY.
+ *
+ * @param none
+ * @return none
+ */
+void POWER_SetUsbPhy(void);
+
+/*!
+ * @brief Power Library API to enter different power mode.
+ *
+ * @param exclude_from_pd  Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on
+ * during power mode selected.
+ * @return none
+ */
+void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd);
+
+/*!
+ * @brief Power Library API to enter sleep mode.
+ *
+ * @return none
+ */
+void POWER_EnterSleep(void);
+
+/*!
+ * @brief Power Library API to enter deep sleep mode.
+ *
+ * @param exclude_from_pd  Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) bits that needs to be
+ * powered on during deep sleep
+ * @return none
+ */
+void POWER_EnterDeepSleep(uint64_t exclude_from_pd);
+
+/*!
+ * @brief Power Library API to enter deep power down mode.
+ *
+ * @param exclude_from_pd   Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on
+ during deep power
+ *                          down mode, but this is has no effect as the voltages are cut off.
+
+ * @return none
+ */
+void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd);
+
+/*!
+ * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
+ *
+ * @param freq  - The desired frequency at which the part would like to operate,
+ *                note that the voltage and flash wait states should be set before changing frequency
+ * @return none
+ */
+void POWER_SetVoltageForFreq(uint32_t freq);
+
+/*!
+ * @brief Power Library API to return the library version.
+ *
+ * @param none
+ * @return version number of the power library
+ */
+uint32_t POWER_GetLibVersion(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FSL_POWER_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_reset.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_reset.c
new file mode 100644
index 000000000..5f886b293
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_reset.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_reset.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.reset"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+
+/*!
+ * brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
+{
+    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
+    const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
+    const uint32_t bitMask = 1UL << bitPos;
+
+    assert(bitPos < 32UL);
+
+    /* ASYNC_SYSCON registers have offset 1024 */
+    if (regIndex >= SYSCON_PRESETCTRL_COUNT)
+    {
+        /* reset register is in ASYNC_SYSCON */
+
+        /* set bit */
+        ASYNC_SYSCON->ASYNCPRESETCTRLSET = bitMask;
+        /* wait until it reads 0b1 */
+        while (0u == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
+        {
+        }
+    }
+    else
+    {
+        /* reset register is in SYSCON */
+
+        /* set bit */
+        SYSCON->PRESETCTRLSET[regIndex] = bitMask;
+        /* wait until it reads 0b1 */
+        while (0u == (SYSCON->PRESETCTRL[regIndex] & bitMask))
+        {
+        }
+    }
+}
+
+/*!
+ * brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
+{
+    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
+    const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
+    const uint32_t bitMask = 1UL << bitPos;
+
+    assert(bitPos < 32UL);
+
+    /* ASYNC_SYSCON registers have offset 1024 */
+    if (regIndex >= SYSCON_PRESETCTRL_COUNT)
+    {
+        /* reset register is in ASYNC_SYSCON */
+
+        /* clear bit */
+        ASYNC_SYSCON->ASYNCPRESETCTRLCLR = bitMask;
+        /* wait until it reads 0b0 */
+        while (bitMask == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
+        {
+        }
+    }
+    else
+    {
+        /* reset register is in SYSCON */
+
+        /* clear bit */
+        SYSCON->PRESETCTRLCLR[regIndex] = bitMask;
+        /* wait until it reads 0b0 */
+        while (bitMask == (SYSCON->PRESETCTRL[regIndex] & bitMask))
+        {
+        }
+    }
+}
+
+/*!
+ * brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * param peripheral Peripheral to reset. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral)
+{
+    RESET_SetPeripheralReset(peripheral);
+    RESET_ClearPeripheralReset(peripheral);
+}
+
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_reset.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_reset.h
new file mode 100644
index 000000000..9c4a77f85
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/drivers/fsl_reset.h
@@ -0,0 +1,277 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_RESET_H_
+#define _FSL_RESET_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include "fsl_device_registers.h"
+
+/*! @addtogroup reset */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief reset driver version 2.0.1. */
+#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/*!
+ * @brief Enumeration for peripheral reset control bits
+ *
+ * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
+ */
+typedef enum _SYSCON_RSTn
+{
+    kSPIFI_RST_SHIFT_RSTn = 0 | 10U,         /**< SPIFI reset control */
+    kMUX_RST_SHIFT_RSTn = 0 | 11U,           /**< Input mux reset control */
+    kIOCON_RST_SHIFT_RSTn = 0 | 13U,         /**< IOCON reset control */
+    kGPIO0_RST_SHIFT_RSTn = 0 | 14U,         /**< GPIO0 reset control */
+    kGPIO1_RST_SHIFT_RSTn = 0 | 15U,         /**< GPIO1 reset control */
+    kGPIO2_RST_SHIFT_RSTn = 0 | 16U,         /**< GPIO2 reset control */
+    kGPIO3_RST_SHIFT_RSTn = 0 | 17U,         /**< GPIO3 reset control */
+    kPINT_RST_SHIFT_RSTn = 0 | 18U,          /**< Pin interrupt (PINT) reset control */
+    kGINT_RST_SHIFT_RSTn = 0 | 19U,          /**< Grouped interrupt (PINT) reset control. */
+    kDMA_RST_SHIFT_RSTn = 0 | 20U,           /**< DMA reset control */
+    kCRC_RST_SHIFT_RSTn = 0 | 21U,           /**< CRC reset control */
+    kWWDT_RST_SHIFT_RSTn = 0 | 22U,          /**< Watchdog timer reset control */
+    kADC0_RST_SHIFT_RSTn = 0 | 27U,          /**< ADC0 reset control */
+
+    kMRT_RST_SHIFT_RSTn = 65536 | 0U,        /**< Multi-rate timer (MRT) reset control */
+    kSCT0_RST_SHIFT_RSTn = 65536 | 2U,       /**< SCTimer/PWM 0 (SCT0) reset control */
+    kMCAN0_RST_SHIFT_RSTn = 65536 | 7U,      /**< MCAN0 reset control */
+    kMCAN1_RST_SHIFT_RSTn = 65536 | 8U,      /**< MCAN1 reset control */
+    kUTICK_RST_SHIFT_RSTn = 65536 | 10U,     /**< Micro-tick timer reset control */
+    kFC0_RST_SHIFT_RSTn = 65536 | 11U,       /**< Flexcomm Interface 0 reset control */
+    kFC1_RST_SHIFT_RSTn = 65536 | 12U,       /**< Flexcomm Interface 1 reset control */
+    kFC2_RST_SHIFT_RSTn = 65536 | 13U,       /**< Flexcomm Interface 2 reset control */
+    kFC3_RST_SHIFT_RSTn = 65536 | 14U,       /**< Flexcomm Interface 3 reset control */
+    kFC4_RST_SHIFT_RSTn = 65536 | 15U,       /**< Flexcomm Interface 4 reset control */
+    kFC5_RST_SHIFT_RSTn = 65536 | 16U,       /**< Flexcomm Interface 5 reset control */
+    kFC6_RST_SHIFT_RSTn = 65536 | 17U,       /**< Flexcomm Interface 6 reset control */
+    kFC7_RST_SHIFT_RSTn = 65536 | 18U,       /**< Flexcomm Interface 7 reset control */
+    kDMIC_RST_SHIFT_RSTn = 65536 | 19U,      /**< Digital microphone interface reset control */
+    kCT32B2_RST_SHIFT_RSTn = 65536 | 22U,    /**< CT32B2 reset control */
+    kUSB0D_RST_SHIFT_RSTn = 65536 | 25U,     /**< USB0D reset control */
+    kCT32B0_RST_SHIFT_RSTn = 65536 | 26U,    /**< CT32B0 reset control */
+    kCT32B1_RST_SHIFT_RSTn = 65536 | 27U,    /**< CT32B1 reset control */
+
+    kLCD_RST_SHIFT_RSTn = 131072 | 2U,       /**< LCD reset control */
+    kSDIO_RST_SHIFT_RSTn = 131072 | 3U,      /**< SDIO reset control */
+    kUSB1H_RST_SHIFT_RSTn = 131072 | 4U,     /**< USB1H reset control */
+    kUSB1D_RST_SHIFT_RSTn = 131072 | 5U,     /**< USB1D reset control */
+    kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U,   /**< USB1RAM reset control */
+    kEMC_RST_SHIFT_RSTn = 131072 | 7U,       /**< EMC reset control */
+    kETH_RST_SHIFT_RSTn = 131072 | 8U,       /**< ETH reset control */
+    kGPIO4_RST_SHIFT_RSTn = 131072 | 9U,     /**< GPIO4 reset control */
+    kGPIO5_RST_SHIFT_RSTn = 131072 | 10U,    /**< GPIO5 reset control */
+    kAES_RST_SHIFT_RSTn = 131072 | 11U,      /**< AES reset control */
+    kOTP_RST_SHIFT_RSTn = 131072 | 12U,      /**< OTP reset control */
+    kRNG_RST_SHIFT_RSTn = 131072 | 13U,      /**< RNG  reset control */
+    kFC8_RST_SHIFT_RSTn = 131072 | 14U,      /**< Flexcomm Interface 8 reset control */
+    kFC9_RST_SHIFT_RSTn = 131072 | 15U,      /**< Flexcomm Interface 9 reset control */
+    kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U,  /**< USB0HMR reset control */
+    kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U,  /**< USB0HSL reset control */
+    kSHA_RST_SHIFT_RSTn = 131072 | 18U,      /**< SHA reset control */
+    kSC0_RST_SHIFT_RSTn = 131072 | 19U,      /**< SC0 reset control */
+    kSC1_RST_SHIFT_RSTn = 131072 | 20U,      /**< SC1 reset control */
+    kFC10_RST_SHIFT_RSTn = 131072 | 21U,     /**< Flexcomm Interface 10 reset control */
+
+    kCT32B3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CT32B3 reset control */
+    kCT32B4_RST_SHIFT_RSTn = 67108864 | 14U, /**< CT32B4 reset control */
+} SYSCON_RSTn_t;
+
+/** Array initializers with peripheral reset bits **/
+#define ADC_RSTS             \
+    {                        \
+        kADC0_RST_SHIFT_RSTn \
+    } /* Reset bits for ADC peripheral */
+#define AES_RSTS             \
+    {                        \
+        kAES_RST_SHIFT_RSTn  \
+    } /* Reset bits for AES peripheral */
+#define CRC_RSTS            \
+    {                       \
+        kCRC_RST_SHIFT_RSTn \
+    } /* Reset bits for CRC peripheral */
+#define CTIMER_RSTS                                                                                     \
+    {                                                                                                   \
+        kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \
+            kCT32B4_RST_SHIFT_RSTn                                                                      \
+    } /* Reset bits for CTIMER peripheral */
+#define DMA_RSTS_N            \
+    {                       \
+        kDMA_RST_SHIFT_RSTn \
+    } /* Reset bits for DMA peripheral */
+#define DMIC_RSTS            \
+    {                        \
+        kDMIC_RST_SHIFT_RSTn \
+    } /* Reset bits for DMIC peripheral */
+#define EMC_RSTS             \
+    {                        \
+        kEMC_RST_SHIFT_RSTn  \
+    } /* Reset bits for EMC peripheral */
+#define ETH_RST              \
+    {                        \
+        kETH_RST_SHIFT_RSTn  \
+    } /* Reset bits for EMC peripheral */
+#define FLEXCOMM_RSTS                                                                                            \
+    {                                                                                                            \
+        kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
+            kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC8_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn   \
+    } /* Reset bits for FLEXCOMM peripheral */
+#define GINT_RSTS                                  \
+    {                                              \
+        kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \
+    } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
+#define GPIO_RSTS_N                                    \
+    {                                                \
+        kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn,  \
+        kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn                                                 \
+    } /* Reset bits for GPIO peripheral */
+#define INPUTMUX_RSTS       \
+    {                       \
+        kMUX_RST_SHIFT_RSTn \
+    } /* Reset bits for INPUTMUX peripheral */
+#define IOCON_RSTS            \
+    {                         \
+        kIOCON_RST_SHIFT_RSTn \
+    } /* Reset bits for IOCON peripheral */
+#define FLASH_RSTS                                 \
+    {                                              \
+        kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \
+    } /* Reset bits for Flash peripheral */
+#define LCD_RSTS                                 \
+    {                                            \
+        kLCD_RST_SHIFT_RSTn                      \
+    } /* Reset bits for LCD peripheral */
+#define MRT_RSTS            \
+    {                       \
+        kMRT_RST_SHIFT_RSTn \
+    } /* Reset bits for MRT peripheral */
+#define MCAN_RSTS                                   \
+    {                                               \
+        kMCAN0_RST_SHIFT_RSTn,kMCAN1_RST_SHIFT_RSTn \
+    } /* Reset bits for MCAN0&MACN1 peripheral */
+#define OTP_RSTS            \
+    {                       \
+        kOTP_RST_SHIFT_RSTn \
+    } /* Reset bits for OTP peripheral */
+#define PINT_RSTS            \
+    {                        \
+        kPINT_RST_SHIFT_RSTn \
+    } /* Reset bits for PINT peripheral */
+#define RNG_RSTS             \
+    {                        \
+        kRNG_RST_SHIFT_RSTn  \
+    } /* Reset bits for RNG peripheral */
+#define SDIO_RST             \
+    {                        \
+        kSDIO_RST_SHIFT_RSTn \
+    } /* Reset bits for SDIO peripheral */
+#define SCT_RSTS             \
+    {                        \
+        kSCT0_RST_SHIFT_RSTn \
+    } /* Reset bits for SCT peripheral */
+#define SHA_RST              \
+    {                        \
+        kSHA_RST_SHIFT_RSTn  \
+    } /* Reset bits for SHA peripheral */
+#define SPIFI_RSTS            \
+    {                         \
+        kSPIFI_RST_SHIFT_RSTn \
+    } /* Reset bits for SPIFI peripheral */
+#define USB0D_RST             \
+    {                         \
+        kUSB0D_RST_SHIFT_RSTn \
+    } /* Reset bits for USB0D peripheral */
+#define USB0HMR_RST             \
+    {                           \
+        kUSB0HMR_RST_SHIFT_RSTn \
+    } /* Reset bits for USB0HMR peripheral */
+#define USB0HSL_RST             \
+    {                           \
+        kUSB0HSL_RST_SHIFT_RSTn \
+    } /* Reset bits for USB0HSL peripheral */
+#define USB1H_RST             \
+    {                         \
+        kUSB1H_RST_SHIFT_RSTn \
+    } /* Reset bits for USB1H peripheral */
+#define USB1D_RST             \
+    {                         \
+        kUSB1D_RST_SHIFT_RSTn \
+    } /* Reset bits for USB1D peripheral */
+#define USB1RAM_RST             \
+    {                           \
+        kUSB1RAM_RST_SHIFT_RSTn \
+    } /* Reset bits for USB1RAM peripheral */
+#define UTICK_RSTS            \
+    {                         \
+        kUTICK_RST_SHIFT_RSTn \
+    } /* Reset bits for UTICK peripheral */
+#define WWDT_RSTS            \
+    {                        \
+        kWWDT_RST_SHIFT_RSTn \
+    } /* Reset bits for WWDT peripheral */
+
+typedef SYSCON_RSTn_t reset_ip_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_RESET_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/fsl_device_registers.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/fsl_device_registers.h
new file mode 100644
index 000000000..9108255d7
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/fsl_device_registers.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_LPC54005JBD100) || defined(CPU_LPC54005JET100))
+
+#define LPC54005_SERIES
+
+/* CMSIS-style register definitions */
+#include "LPC54005.h"
+/* CPU specific feature definitions */
+#include "LPC54005_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/gcc/LPC54005_ram.ld b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/gcc/LPC54005_ram.ld
new file mode 100644
index 000000000..76c7911f9
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/gcc/LPC54005_ram.ld
@@ -0,0 +1,215 @@
+/*
+** ###################################################################
+**     Processors:          LPC54005JBD100
+**                          LPC54005JET100
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
+**     Version:             rev. 1.2, 2017-06-08
+**     Build:               b190925
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2019 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+** ###################################################################
+*/
+
+
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000200
+  m_text                (RX)  : ORIGIN = 0x00000200, LENGTH = 0x0002FE00
+  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00028000
+  m_usb_sram            (RW)  : ORIGIN = 0x40100000, LENGTH = 0x00002000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into internal flash */
+  .interrupts :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  /* The program code and other data goes into internal flash */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.ramfunc*)             /* for functions in ram */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+  __IMAGE_START = LOADADDR(.interrupts);
+  __IMAGE_END = LOADADDR(.data) + SIZEOF(.data);
+  __IMAGE_SIZE = __IMAGE_END - __IMAGE_START;
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+    __heap_limit = .; /* Add for _sbrk */
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data
+
+  m_usb_bdt (NOLOAD) :
+  {
+    . = ALIGN(512);
+    *(m_usb_bdt)
+  } > m_usb_sram
+
+  m_usb_global (NOLOAD) :
+  {
+    *(m_usb_global)
+  } > m_usb_sram
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/gcc/libpower_hardabi.a b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/gcc/libpower_hardabi.a
new file mode 100644
index 000000000..0e5c92f49
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/gcc/libpower_hardabi.a
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/gcc/libpower_softabi.a b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/gcc/libpower_softabi.a
new file mode 100644
index 000000000..78e7c633e
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/gcc/libpower_softabi.a
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/gcc/startup_LPC54005.S b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/gcc/startup_LPC54005.S
new file mode 100644
index 000000000..66d8d46fc
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/gcc/startup_LPC54005.S
@@ -0,0 +1,908 @@
+/* --------------------------------------------------------------------------*/
+/* @file:    startup_LPC54005.S                                                */
+/* @purpose: CMSIS Cortex-M4 Core Device Startup File                        */
+/*           LPC54005                                                          */
+/* @version: 1.2                                                      */
+/* @date:    2017-6-8                                                         */
+/* --------------------------------------------------------------------------*/
+/*                                                                           */
+/* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
+/* Copyright 2016-2019 NXP                                                   */
+/* All rights reserved.                                                      */
+/*                                                                           */
+/* SPDX-License-Identifier: BSD-3-Clause                                     */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+
+
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __Vectors
+__Vectors:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   MemManage_Handler                               /* MPU Fault Handler*/
+    .long   BusFault_Handler                                /* Bus Fault Handler*/
+    .long   UsageFault_Handler                              /* Usage Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0xEDDC94BD                                      /* Enhanced image marker, set to 0x0 for legacy boot */
+    .long   0x160                                           /* Pointer to enhanced boot block, set to 0x0 for legacy boot */
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+    /* External Interrupts */
+    .long   WDT_BOD_IRQHandler                     /* Windowed watchdog timer, Brownout detect */
+    .long   DMA0_IRQHandler                     /* DMA controller */
+    .long   GINT0_IRQHandler                     /* GPIO group 0 */
+    .long   GINT1_IRQHandler                     /* GPIO group 1 */
+    .long   PIN_INT0_IRQHandler                     /* Pin interrupt 0 or pattern match engine slice 0 */
+    .long   PIN_INT1_IRQHandler                     /* Pin interrupt 1or pattern match engine slice 1 */
+    .long   PIN_INT2_IRQHandler                     /* Pin interrupt 2 or pattern match engine slice 2 */
+    .long   PIN_INT3_IRQHandler                     /* Pin interrupt 3 or pattern match engine slice 3 */
+    .long   UTICK0_IRQHandler                     /* Micro-tick Timer */
+    .long   MRT0_IRQHandler                     /* Multi-rate timer */
+    .long   CTIMER0_IRQHandler                     /* Standard counter/timer CTIMER0 */
+    .long   CTIMER1_IRQHandler                     /* Standard counter/timer CTIMER1 */
+    .long   SCT0_IRQHandler                     /* SCTimer/PWM */
+    .long   CTIMER3_IRQHandler                     /* Standard counter/timer CTIMER3 */
+    .long   FLEXCOMM0_IRQHandler                     /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM1_IRQHandler                     /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM2_IRQHandler                     /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM3_IRQHandler                     /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM4_IRQHandler                     /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM5_IRQHandler                     /* Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
+    .long   FLEXCOMM6_IRQHandler                     /* Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+    .long   FLEXCOMM7_IRQHandler                     /* Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+    .long   ADC0_SEQA_IRQHandler                     /* ADC0 sequence A completion. */
+    .long   ADC0_SEQB_IRQHandler                     /* ADC0 sequence B completion. */
+    .long   ADC0_THCMP_IRQHandler                     /* ADC0 threshold compare and error. */
+    .long   DMIC0_IRQHandler                     /* Digital microphone and DMIC subsystem */
+    .long   HWVAD0_IRQHandler                     /* Hardware Voice Activity Detector */
+    .long   USB0_NEEDCLK_IRQHandler                     /* USB Activity Wake-up Interrupt */
+    .long   USB0_IRQHandler                     /* USB device */
+    .long   RTC_IRQHandler                     /* RTC alarm and wake-up interrupts */
+    .long   FLEXCOMM10_IRQHandler                     /* Flexcomm Interface 10 (SPI, FLEXCOMM) */
+    .long   Reserved47_IRQHandler                     /* Reserved interrupt */
+    .long   PIN_INT4_IRQHandler                     /* Pin interrupt 4 or pattern match engine slice 4 int */
+    .long   PIN_INT5_IRQHandler                     /* Pin interrupt 5 or pattern match engine slice 5 int */
+    .long   PIN_INT6_IRQHandler                     /* Pin interrupt 6 or pattern match engine slice 6 int */
+    .long   PIN_INT7_IRQHandler                     /* Pin interrupt 7 or pattern match engine slice 7 int */
+    .long   CTIMER2_IRQHandler                     /* Standard counter/timer CTIMER2 */
+    .long   CTIMER4_IRQHandler                     /* Standard counter/timer CTIMER4 */
+    .long   RIT_IRQHandler                     /* Repetitive Interrupt Timer */
+    .long   SPIFI0_IRQHandler                     /* SPI flash interface */
+    .long   FLEXCOMM8_IRQHandler                     /* Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM9_IRQHandler                     /* Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
+    .long   SDIO_IRQHandler                     /* SD/MMC  */
+    .long   CAN0_IRQ0_IRQHandler                     /* CAN0 interrupt0 */
+    .long   CAN0_IRQ1_IRQHandler                     /* CAN0 interrupt1 */
+    .long   CAN1_IRQ0_IRQHandler                     /* CAN1 interrupt0 */
+    .long   CAN1_IRQ1_IRQHandler                     /* CAN1 interrupt1 */
+    .long   USB1_IRQHandler                     /* USB1 interrupt */
+    .long   USB1_NEEDCLK_IRQHandler                     /* USB1 activity */
+    .long   ETHERNET_IRQHandler                     /* Ethernet */
+    .long   ETHERNET_PMT_IRQHandler                     /* Ethernet power management interrupt */
+    .long   ETHERNET_MACLP_IRQHandler                     /* Ethernet MAC interrupt */
+    .long   Reserved68_IRQHandler                     /* Reserved interrupt */
+    .long   LCD_IRQHandler                     /* LCD interrupt */
+    .long   SHA_IRQHandler                     /* SHA interrupt */
+    .long   SMARTCARD0_IRQHandler                     /* Smart card 0 interrupt */
+    .long   SMARTCARD1_IRQHandler                     /* Smart card 1 interrupt */
+
+    .size    __Vectors, . - __Vectors
+
+    .long   0                                               /* Reserved */
+    .long   0                                               /* Reserved */
+    .long   0                                               /* Reserved */
+    .long   0                                               /* Reserved */
+    .long   0                                               /* Reserved */
+    .long   0                                               /* Reserved */
+    .long   0                                               /* Reserved */
+    .long   0                                               /* Reserved */
+    .long   0                                               /* Reserved */
+    .long   0                                               /* Reserved */
+    .long   0                                               /* Reserved */
+    .long   0                                               /* Reserved */
+    .long   0                                               /* Reserved */
+    .long   0                                               /* Reserved */
+    .long   0                                               /* Reserved */
+
+#ifndef IMG_BAUDRATE
+#define IMG_BAUDRATE 0
+#endif
+
+__image_header:
+    .long   0xFEEDA5A5                                      /* (0x00, 0x160) Header Marker */
+    #ifdef XIP_IMAGE
+          #ifdef ADD_CRC
+          .long   0x2                                       /* (0x04) Image Type */
+          #else
+          .long   0x3                                       /* (0x04) Image Type */
+          #endif
+    #else
+          #ifdef ADD_CRC
+          .long   0x0                                       /* (0x04) Image Type */
+          #else
+          .long   0x1                                       /* (0x04) Image Type */
+          #endif
+    #endif
+
+    #ifdef XIP_IMAGE
+          .long   0x10000000                                /* (0x08) Load_address */
+    #else
+          .long   0x00000000                                /* (0x08) Load_address */
+    #endif
+    .long   __IMAGE_SIZE - 4                                /* (0x0C) load_length, exclude 4 bytes CRC field */
+    .long   0                                               /* (0x10) CRC value (only applicable to NON Non-secure images) */
+    .long   0                                               /* (0x14) Version (only applicable to DUAL_ENH image type */
+    .long   0                                               /* (0x18) EMC static memory configuration settings, required for EMC boot */
+    .long   IMG_BAUDRATE                                    /* image baudrate */
+    .long   0                                               /* Reserved */
+    .long   0xEDDC94BD                                      /* (0x24) Image_marker */
+    .long   0                                               /* (0x28) SBZ */
+    .long   0                                               /* (0x2C) reserved */
+     #ifdef W25Q128JVFM
+     /* SPI Descriptor - W25Q128JVFM */
+    .long   0x00000000                                      /* 0xFFFFFFFF to default 1-bit SPI mode   ;DevStrAdr */
+    .long   0x001870EF                                      /* mfgId + extCount */
+    .long   0x00000000                                      /* extid 0-3 */
+    .long   0x00000000                                      /* extid 4-7 */
+    .long   0x0001001D                                      /* caps */
+    .long   0x00000100                                      /* Blks + RESV1 */
+    .long   0x00010000                                      /* blkSize */
+    .long   0x00000000                                      /* subBlks + subBlkSize */
+    .long   0x00000100                                      /* pageSize + RESV2 */
+    .long   0x00003F00                                      /* maxReadSize */
+    .long   0x68506850                                      /* maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate */
+    .long   0x04030050                                      /* maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId, */
+    .long   0x14110D09                                      /* setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId */
+    #endif
+
+     #ifdef MXL12835F
+     /* SPI Descriptor - MXL12835F */
+    .long   0x00000000                                      /* 0xFFFFFFFF to default 1-bit SPI mode  ;DevStrAdr */
+    .long   0x001820C2                                      /* mfgId + extCount */
+    .long   0x00000000                                      /* extid 0-3 */
+    .long   0x00000000                                      /* extid 4-7 */
+    .long   0x0001001D                                      /* caps */
+    .long   0x00000100                                      /* Blks + RESV1 */
+    .long   0x00010000                                      /* blkSize */
+    .long   0x00000000                                      /* subBlks + subBlkSize */
+    .long   0x00000100                                      /* pageSize + RESV2 */
+    .long   0x00003F00                                      /* maxReadSize */
+    .long   0x68506850                                      /* maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate */
+    .long   0x06030050                                      /* maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId */
+    .long   0x14110F0B                                      /* setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId */
+    #endif
+    .text
+    .thumb
+
+/* Reset Handler */
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+
+#ifndef __NO_SYSTEM_INIT
+    movs  r0,#56
+    ldr   r1, =0x40000220
+    str   r0, [r1]           /* Enable SRAM clock used by Stack */
+    ldr   r0,=SystemInit
+    blx   r0
+#endif
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+#if 1
+/* Here are two copies of loop implemenations. First one favors code size
+ * and the second one favors performance. Default uses the first one.
+ * Change to "#if 0" to use the second one */
+.LC0:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt    .LC0
+#else
+    subs    r3, r2
+    ble    .LC1
+.LC0:
+    subs    r3, #4
+    ldr    r0, [r1, r3]
+    str    r0, [r2, r3]
+    bgt    .LC0
+.LC1:
+#endif
+
+#ifdef __STARTUP_CLEAR_BSS
+/*     This part of work usually is done in C library startup code. Otherwise,
+ *     define this macro to enable it in this startup.
+ *
+ *     Loop to zero out BSS section, which uses following symbols
+ *     in linker script:
+ *      __bss_start__: start of BSS section. Must align to 4
+ *      __bss_end__: end of BSS section. Must align to 4
+ */
+    ldr r1, =__bss_start__
+    ldr r2, =__bss_end__
+
+    movs    r0, 0
+.LC2:
+    cmp     r1, r2
+    itt    lt
+    strlt   r0, [r1], #4
+    blt    .LC2
+#endif /* __STARTUP_CLEAR_BSS */
+
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    ldr   r0,=__START
+    blx   r0
+#else
+    ldr   r0,=__libc_init_array
+    blx   r0
+    ldr   r0,=main
+    bx    r0
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+    .align 1
+    .thumb_func
+    .weak NMI_Handler
+    .type NMI_Handler, %function
+NMI_Handler:
+    ldr   r0,=NMI_Handler
+    bx    r0
+    .size NMI_Handler, . - NMI_Handler
+
+    .align 1
+    .thumb_func
+    .weak HardFault_Handler
+    .type HardFault_Handler, %function
+HardFault_Handler:
+    ldr   r0,=HardFault_Handler
+    bx    r0
+    .size HardFault_Handler, . - HardFault_Handler
+
+    .align 1
+    .thumb_func
+    .weak SVC_Handler
+    .type SVC_Handler, %function
+SVC_Handler:
+    ldr   r0,=SVC_Handler
+    bx    r0
+    .size SVC_Handler, . - SVC_Handler
+
+    .align 1
+    .thumb_func
+    .weak PendSV_Handler
+    .type PendSV_Handler, %function
+PendSV_Handler:
+    ldr   r0,=PendSV_Handler
+    bx    r0
+    .size PendSV_Handler, . - PendSV_Handler
+
+    .align 1
+    .thumb_func
+    .weak SysTick_Handler
+    .type SysTick_Handler, %function
+SysTick_Handler:
+    ldr   r0,=SysTick_Handler
+    bx    r0
+    .size SysTick_Handler, . - SysTick_Handler
+
+    .align 1
+    .thumb_func
+    .weak WDT_BOD_IRQHandler
+    .type WDT_BOD_IRQHandler, %function
+WDT_BOD_IRQHandler:
+    ldr   r0,=WDT_BOD_DriverIRQHandler
+    bx    r0
+    .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA0_IRQHandler
+    .type DMA0_IRQHandler, %function
+DMA0_IRQHandler:
+    ldr   r0,=DMA0_DriverIRQHandler
+    bx    r0
+    .size DMA0_IRQHandler, . - DMA0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak GINT0_IRQHandler
+    .type GINT0_IRQHandler, %function
+GINT0_IRQHandler:
+    ldr   r0,=GINT0_DriverIRQHandler
+    bx    r0
+    .size GINT0_IRQHandler, . - GINT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak GINT1_IRQHandler
+    .type GINT1_IRQHandler, %function
+GINT1_IRQHandler:
+    ldr   r0,=GINT1_DriverIRQHandler
+    bx    r0
+    .size GINT1_IRQHandler, . - GINT1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT0_IRQHandler
+    .type PIN_INT0_IRQHandler, %function
+PIN_INT0_IRQHandler:
+    ldr   r0,=PIN_INT0_DriverIRQHandler
+    bx    r0
+    .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT1_IRQHandler
+    .type PIN_INT1_IRQHandler, %function
+PIN_INT1_IRQHandler:
+    ldr   r0,=PIN_INT1_DriverIRQHandler
+    bx    r0
+    .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT2_IRQHandler
+    .type PIN_INT2_IRQHandler, %function
+PIN_INT2_IRQHandler:
+    ldr   r0,=PIN_INT2_DriverIRQHandler
+    bx    r0
+    .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT3_IRQHandler
+    .type PIN_INT3_IRQHandler, %function
+PIN_INT3_IRQHandler:
+    ldr   r0,=PIN_INT3_DriverIRQHandler
+    bx    r0
+    .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak UTICK0_IRQHandler
+    .type UTICK0_IRQHandler, %function
+UTICK0_IRQHandler:
+    ldr   r0,=UTICK0_DriverIRQHandler
+    bx    r0
+    .size UTICK0_IRQHandler, . - UTICK0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak MRT0_IRQHandler
+    .type MRT0_IRQHandler, %function
+MRT0_IRQHandler:
+    ldr   r0,=MRT0_DriverIRQHandler
+    bx    r0
+    .size MRT0_IRQHandler, . - MRT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER0_IRQHandler
+    .type CTIMER0_IRQHandler, %function
+CTIMER0_IRQHandler:
+    ldr   r0,=CTIMER0_DriverIRQHandler
+    bx    r0
+    .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER1_IRQHandler
+    .type CTIMER1_IRQHandler, %function
+CTIMER1_IRQHandler:
+    ldr   r0,=CTIMER1_DriverIRQHandler
+    bx    r0
+    .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SCT0_IRQHandler
+    .type SCT0_IRQHandler, %function
+SCT0_IRQHandler:
+    ldr   r0,=SCT0_DriverIRQHandler
+    bx    r0
+    .size SCT0_IRQHandler, . - SCT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER3_IRQHandler
+    .type CTIMER3_IRQHandler, %function
+CTIMER3_IRQHandler:
+    ldr   r0,=CTIMER3_DriverIRQHandler
+    bx    r0
+    .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM0_IRQHandler
+    .type FLEXCOMM0_IRQHandler, %function
+FLEXCOMM0_IRQHandler:
+    ldr   r0,=FLEXCOMM0_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM1_IRQHandler
+    .type FLEXCOMM1_IRQHandler, %function
+FLEXCOMM1_IRQHandler:
+    ldr   r0,=FLEXCOMM1_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM2_IRQHandler
+    .type FLEXCOMM2_IRQHandler, %function
+FLEXCOMM2_IRQHandler:
+    ldr   r0,=FLEXCOMM2_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM3_IRQHandler
+    .type FLEXCOMM3_IRQHandler, %function
+FLEXCOMM3_IRQHandler:
+    ldr   r0,=FLEXCOMM3_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM4_IRQHandler
+    .type FLEXCOMM4_IRQHandler, %function
+FLEXCOMM4_IRQHandler:
+    ldr   r0,=FLEXCOMM4_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM5_IRQHandler
+    .type FLEXCOMM5_IRQHandler, %function
+FLEXCOMM5_IRQHandler:
+    ldr   r0,=FLEXCOMM5_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM6_IRQHandler
+    .type FLEXCOMM6_IRQHandler, %function
+FLEXCOMM6_IRQHandler:
+    ldr   r0,=FLEXCOMM6_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM7_IRQHandler
+    .type FLEXCOMM7_IRQHandler, %function
+FLEXCOMM7_IRQHandler:
+    ldr   r0,=FLEXCOMM7_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ADC0_SEQA_IRQHandler
+    .type ADC0_SEQA_IRQHandler, %function
+ADC0_SEQA_IRQHandler:
+    ldr   r0,=ADC0_SEQA_DriverIRQHandler
+    bx    r0
+    .size ADC0_SEQA_IRQHandler, . - ADC0_SEQA_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ADC0_SEQB_IRQHandler
+    .type ADC0_SEQB_IRQHandler, %function
+ADC0_SEQB_IRQHandler:
+    ldr   r0,=ADC0_SEQB_DriverIRQHandler
+    bx    r0
+    .size ADC0_SEQB_IRQHandler, . - ADC0_SEQB_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ADC0_THCMP_IRQHandler
+    .type ADC0_THCMP_IRQHandler, %function
+ADC0_THCMP_IRQHandler:
+    ldr   r0,=ADC0_THCMP_DriverIRQHandler
+    bx    r0
+    .size ADC0_THCMP_IRQHandler, . - ADC0_THCMP_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMIC0_IRQHandler
+    .type DMIC0_IRQHandler, %function
+DMIC0_IRQHandler:
+    ldr   r0,=DMIC0_DriverIRQHandler
+    bx    r0
+    .size DMIC0_IRQHandler, . - DMIC0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak HWVAD0_IRQHandler
+    .type HWVAD0_IRQHandler, %function
+HWVAD0_IRQHandler:
+    ldr   r0,=HWVAD0_DriverIRQHandler
+    bx    r0
+    .size HWVAD0_IRQHandler, . - HWVAD0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB0_NEEDCLK_IRQHandler
+    .type USB0_NEEDCLK_IRQHandler, %function
+USB0_NEEDCLK_IRQHandler:
+    ldr   r0,=USB0_NEEDCLK_DriverIRQHandler
+    bx    r0
+    .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB0_IRQHandler
+    .type USB0_IRQHandler, %function
+USB0_IRQHandler:
+    ldr   r0,=USB0_DriverIRQHandler
+    bx    r0
+    .size USB0_IRQHandler, . - USB0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak RTC_IRQHandler
+    .type RTC_IRQHandler, %function
+RTC_IRQHandler:
+    ldr   r0,=RTC_DriverIRQHandler
+    bx    r0
+    .size RTC_IRQHandler, . - RTC_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM10_IRQHandler
+    .type FLEXCOMM10_IRQHandler, %function
+FLEXCOMM10_IRQHandler:
+    ldr   r0,=FLEXCOMM10_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM10_IRQHandler, . - FLEXCOMM10_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved47_IRQHandler
+    .type Reserved47_IRQHandler, %function
+Reserved47_IRQHandler:
+    ldr   r0,=Reserved47_DriverIRQHandler
+    bx    r0
+    .size Reserved47_IRQHandler, . - Reserved47_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT4_IRQHandler
+    .type PIN_INT4_IRQHandler, %function
+PIN_INT4_IRQHandler:
+    ldr   r0,=PIN_INT4_DriverIRQHandler
+    bx    r0
+    .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT5_IRQHandler
+    .type PIN_INT5_IRQHandler, %function
+PIN_INT5_IRQHandler:
+    ldr   r0,=PIN_INT5_DriverIRQHandler
+    bx    r0
+    .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT6_IRQHandler
+    .type PIN_INT6_IRQHandler, %function
+PIN_INT6_IRQHandler:
+    ldr   r0,=PIN_INT6_DriverIRQHandler
+    bx    r0
+    .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT7_IRQHandler
+    .type PIN_INT7_IRQHandler, %function
+PIN_INT7_IRQHandler:
+    ldr   r0,=PIN_INT7_DriverIRQHandler
+    bx    r0
+    .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER2_IRQHandler
+    .type CTIMER2_IRQHandler, %function
+CTIMER2_IRQHandler:
+    ldr   r0,=CTIMER2_DriverIRQHandler
+    bx    r0
+    .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER4_IRQHandler
+    .type CTIMER4_IRQHandler, %function
+CTIMER4_IRQHandler:
+    ldr   r0,=CTIMER4_DriverIRQHandler
+    bx    r0
+    .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak RIT_IRQHandler
+    .type RIT_IRQHandler, %function
+RIT_IRQHandler:
+    ldr   r0,=RIT_DriverIRQHandler
+    bx    r0
+    .size RIT_IRQHandler, . - RIT_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SPIFI0_IRQHandler
+    .type SPIFI0_IRQHandler, %function
+SPIFI0_IRQHandler:
+    ldr   r0,=SPIFI0_DriverIRQHandler
+    bx    r0
+    .size SPIFI0_IRQHandler, . - SPIFI0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM8_IRQHandler
+    .type FLEXCOMM8_IRQHandler, %function
+FLEXCOMM8_IRQHandler:
+    ldr   r0,=FLEXCOMM8_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM9_IRQHandler
+    .type FLEXCOMM9_IRQHandler, %function
+FLEXCOMM9_IRQHandler:
+    ldr   r0,=FLEXCOMM9_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM9_IRQHandler, . - FLEXCOMM9_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SDIO_IRQHandler
+    .type SDIO_IRQHandler, %function
+SDIO_IRQHandler:
+    ldr   r0,=SDIO_DriverIRQHandler
+    bx    r0
+    .size SDIO_IRQHandler, . - SDIO_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CAN0_IRQ0_IRQHandler
+    .type CAN0_IRQ0_IRQHandler, %function
+CAN0_IRQ0_IRQHandler:
+    ldr   r0,=CAN0_IRQ0_DriverIRQHandler
+    bx    r0
+    .size CAN0_IRQ0_IRQHandler, . - CAN0_IRQ0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CAN0_IRQ1_IRQHandler
+    .type CAN0_IRQ1_IRQHandler, %function
+CAN0_IRQ1_IRQHandler:
+    ldr   r0,=CAN0_IRQ1_DriverIRQHandler
+    bx    r0
+    .size CAN0_IRQ1_IRQHandler, . - CAN0_IRQ1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CAN1_IRQ0_IRQHandler
+    .type CAN1_IRQ0_IRQHandler, %function
+CAN1_IRQ0_IRQHandler:
+    ldr   r0,=CAN1_IRQ0_DriverIRQHandler
+    bx    r0
+    .size CAN1_IRQ0_IRQHandler, . - CAN1_IRQ0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CAN1_IRQ1_IRQHandler
+    .type CAN1_IRQ1_IRQHandler, %function
+CAN1_IRQ1_IRQHandler:
+    ldr   r0,=CAN1_IRQ1_DriverIRQHandler
+    bx    r0
+    .size CAN1_IRQ1_IRQHandler, . - CAN1_IRQ1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB1_IRQHandler
+    .type USB1_IRQHandler, %function
+USB1_IRQHandler:
+    ldr   r0,=USB1_DriverIRQHandler
+    bx    r0
+    .size USB1_IRQHandler, . - USB1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB1_NEEDCLK_IRQHandler
+    .type USB1_NEEDCLK_IRQHandler, %function
+USB1_NEEDCLK_IRQHandler:
+    ldr   r0,=USB1_NEEDCLK_DriverIRQHandler
+    bx    r0
+    .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ETHERNET_IRQHandler
+    .type ETHERNET_IRQHandler, %function
+ETHERNET_IRQHandler:
+    ldr   r0,=ETHERNET_DriverIRQHandler
+    bx    r0
+    .size ETHERNET_IRQHandler, . - ETHERNET_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ETHERNET_PMT_IRQHandler
+    .type ETHERNET_PMT_IRQHandler, %function
+ETHERNET_PMT_IRQHandler:
+    ldr   r0,=ETHERNET_PMT_DriverIRQHandler
+    bx    r0
+    .size ETHERNET_PMT_IRQHandler, . - ETHERNET_PMT_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ETHERNET_MACLP_IRQHandler
+    .type ETHERNET_MACLP_IRQHandler, %function
+ETHERNET_MACLP_IRQHandler:
+    ldr   r0,=ETHERNET_MACLP_DriverIRQHandler
+    bx    r0
+    .size ETHERNET_MACLP_IRQHandler, . - ETHERNET_MACLP_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved68_IRQHandler
+    .type Reserved68_IRQHandler, %function
+Reserved68_IRQHandler:
+    ldr   r0,=Reserved68_DriverIRQHandler
+    bx    r0
+    .size Reserved68_IRQHandler, . - Reserved68_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LCD_IRQHandler
+    .type LCD_IRQHandler, %function
+LCD_IRQHandler:
+    ldr   r0,=LCD_DriverIRQHandler
+    bx    r0
+    .size LCD_IRQHandler, . - LCD_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SHA_IRQHandler
+    .type SHA_IRQHandler, %function
+SHA_IRQHandler:
+    ldr   r0,=SHA_DriverIRQHandler
+    bx    r0
+    .size SHA_IRQHandler, . - SHA_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SMARTCARD0_IRQHandler
+    .type SMARTCARD0_IRQHandler, %function
+SMARTCARD0_IRQHandler:
+    ldr   r0,=SMARTCARD0_DriverIRQHandler
+    bx    r0
+    .size SMARTCARD0_IRQHandler, . - SMARTCARD0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SMARTCARD1_IRQHandler
+    .type SMARTCARD1_IRQHandler, %function
+SMARTCARD1_IRQHandler:
+    ldr   r0,=SMARTCARD1_DriverIRQHandler
+    bx    r0
+    .size SMARTCARD1_IRQHandler, . - SMARTCARD1_IRQHandler
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler  handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+/* Exception Handlers */
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    WDT_BOD_DriverIRQHandler
+    def_irq_handler    DMA0_DriverIRQHandler
+    def_irq_handler    GINT0_DriverIRQHandler
+    def_irq_handler    GINT1_DriverIRQHandler
+    def_irq_handler    PIN_INT0_DriverIRQHandler
+    def_irq_handler    PIN_INT1_DriverIRQHandler
+    def_irq_handler    PIN_INT2_DriverIRQHandler
+    def_irq_handler    PIN_INT3_DriverIRQHandler
+    def_irq_handler    UTICK0_DriverIRQHandler
+    def_irq_handler    MRT0_DriverIRQHandler
+    def_irq_handler    CTIMER0_DriverIRQHandler
+    def_irq_handler    CTIMER1_DriverIRQHandler
+    def_irq_handler    SCT0_DriverIRQHandler
+    def_irq_handler    CTIMER3_DriverIRQHandler
+    def_irq_handler    FLEXCOMM0_DriverIRQHandler
+    def_irq_handler    FLEXCOMM1_DriverIRQHandler
+    def_irq_handler    FLEXCOMM2_DriverIRQHandler
+    def_irq_handler    FLEXCOMM3_DriverIRQHandler
+    def_irq_handler    FLEXCOMM4_DriverIRQHandler
+    def_irq_handler    FLEXCOMM5_DriverIRQHandler
+    def_irq_handler    FLEXCOMM6_DriverIRQHandler
+    def_irq_handler    FLEXCOMM7_DriverIRQHandler
+    def_irq_handler    ADC0_SEQA_DriverIRQHandler
+    def_irq_handler    ADC0_SEQB_DriverIRQHandler
+    def_irq_handler    ADC0_THCMP_DriverIRQHandler
+    def_irq_handler    DMIC0_DriverIRQHandler
+    def_irq_handler    HWVAD0_DriverIRQHandler
+    def_irq_handler    USB0_NEEDCLK_DriverIRQHandler
+    def_irq_handler    USB0_DriverIRQHandler
+    def_irq_handler    RTC_DriverIRQHandler
+    def_irq_handler    FLEXCOMM10_DriverIRQHandler
+    def_irq_handler    Reserved47_DriverIRQHandler
+    def_irq_handler    PIN_INT4_DriverIRQHandler
+    def_irq_handler    PIN_INT5_DriverIRQHandler
+    def_irq_handler    PIN_INT6_DriverIRQHandler
+    def_irq_handler    PIN_INT7_DriverIRQHandler
+    def_irq_handler    CTIMER2_DriverIRQHandler
+    def_irq_handler    CTIMER4_DriverIRQHandler
+    def_irq_handler    RIT_DriverIRQHandler
+    def_irq_handler    SPIFI0_DriverIRQHandler
+    def_irq_handler    FLEXCOMM8_DriverIRQHandler
+    def_irq_handler    FLEXCOMM9_DriverIRQHandler
+    def_irq_handler    SDIO_DriverIRQHandler
+    def_irq_handler    CAN0_IRQ0_DriverIRQHandler
+    def_irq_handler    CAN0_IRQ1_DriverIRQHandler
+    def_irq_handler    CAN1_IRQ0_DriverIRQHandler
+    def_irq_handler    CAN1_IRQ1_DriverIRQHandler
+    def_irq_handler    USB1_DriverIRQHandler
+    def_irq_handler    USB1_NEEDCLK_DriverIRQHandler
+    def_irq_handler    ETHERNET_DriverIRQHandler
+    def_irq_handler    ETHERNET_PMT_DriverIRQHandler
+    def_irq_handler    ETHERNET_MACLP_DriverIRQHandler
+    def_irq_handler    Reserved68_DriverIRQHandler
+    def_irq_handler    LCD_DriverIRQHandler
+    def_irq_handler    SHA_DriverIRQHandler
+    def_irq_handler    SMARTCARD0_DriverIRQHandler
+    def_irq_handler    SMARTCARD1_DriverIRQHandler
+
+    .end
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/mcuxpresso/libpower_hardabi.a b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/mcuxpresso/libpower_hardabi.a
new file mode 100644
index 000000000..0e5c92f49
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/mcuxpresso/libpower_hardabi.a
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/mcuxpresso/libpower_softabi.a b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/mcuxpresso/libpower_softabi.a
new file mode 100644
index 000000000..78e7c633e
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/mcuxpresso/libpower_softabi.a
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/mcuxpresso/startup_lpc54005.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/mcuxpresso/startup_lpc54005.c
new file mode 100644
index 000000000..39943aa41
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/mcuxpresso/startup_lpc54005.c
@@ -0,0 +1,824 @@
+//*****************************************************************************
+// LPC54005 startup code for use with MCUXpresso IDE
+//
+// Version : 160420
+//*****************************************************************************
+//
+// Copyright 2016-2020 NXP
+// All rights reserved.
+//
+// SPDX-License-Identifier: BSD-3-Clause
+//*****************************************************************************
+
+#if defined (DEBUG)
+#pragma GCC push_options
+#pragma GCC optimize ("Og")
+#endif // (DEBUG)
+
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+    extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define WEAK_AV __attribute__ ((weak, section(".after_vectors")))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+// Variable to store CRP value in. Will be placed automatically
+// by the linker when "Enable Code Read Protect" selected.
+// See crp.h header for more information
+//*****************************************************************************
+#include <NXP/crp.h>
+__CRP const unsigned int CRP_WORD = CRP_NO_CRP ;
+
+//*****************************************************************************
+// Declaration of external SystemInit function
+//*****************************************************************************
+#if defined (__USE_CMSIS)
+extern void SystemInit(void);
+#endif // (__USE_CMSIS)
+
+//*****************************************************************************
+// Forward declaration of the core exception handlers.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions.
+// If your application is a C++ one, then any interrupt handlers defined
+// in C++ files within in your main application will need to have C linkage
+// rather than C++ linkage. To do this, make sure that you are using extern "C"
+// { .... } around the interrupt handler within your main application code.
+//*****************************************************************************
+     void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the application IRQ handlers. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over weak definitions below
+//*****************************************************************************
+WEAK void WDT_BOD_IRQHandler(void);
+WEAK void DMA0_IRQHandler(void);
+WEAK void GINT0_IRQHandler(void);
+WEAK void GINT1_IRQHandler(void);
+WEAK void PIN_INT0_IRQHandler(void);
+WEAK void PIN_INT1_IRQHandler(void);
+WEAK void PIN_INT2_IRQHandler(void);
+WEAK void PIN_INT3_IRQHandler(void);
+WEAK void UTICK0_IRQHandler(void);
+WEAK void MRT0_IRQHandler(void);
+WEAK void CTIMER0_IRQHandler(void);
+WEAK void CTIMER1_IRQHandler(void);
+WEAK void SCT0_IRQHandler(void);
+WEAK void CTIMER3_IRQHandler(void);
+WEAK void FLEXCOMM0_IRQHandler(void);
+WEAK void FLEXCOMM1_IRQHandler(void);
+WEAK void FLEXCOMM2_IRQHandler(void);
+WEAK void FLEXCOMM3_IRQHandler(void);
+WEAK void FLEXCOMM4_IRQHandler(void);
+WEAK void FLEXCOMM5_IRQHandler(void);
+WEAK void FLEXCOMM6_IRQHandler(void);
+WEAK void FLEXCOMM7_IRQHandler(void);
+WEAK void ADC0_SEQA_IRQHandler(void);
+WEAK void ADC0_SEQB_IRQHandler(void);
+WEAK void ADC0_THCMP_IRQHandler(void);
+WEAK void DMIC0_IRQHandler(void);
+WEAK void HWVAD0_IRQHandler(void);
+WEAK void USB0_NEEDCLK_IRQHandler(void);
+WEAK void USB0_IRQHandler(void);
+WEAK void RTC_IRQHandler(void);
+WEAK void FLEXCOMM10_IRQHandler(void);
+WEAK void Reserved47_IRQHandler(void);
+WEAK void PIN_INT4_IRQHandler(void);
+WEAK void PIN_INT5_IRQHandler(void);
+WEAK void PIN_INT6_IRQHandler(void);
+WEAK void PIN_INT7_IRQHandler(void);
+WEAK void CTIMER2_IRQHandler(void);
+WEAK void CTIMER4_IRQHandler(void);
+WEAK void RIT_IRQHandler(void);
+WEAK void SPIFI0_IRQHandler(void);
+WEAK void FLEXCOMM8_IRQHandler(void);
+WEAK void FLEXCOMM9_IRQHandler(void);
+WEAK void SDIO_IRQHandler(void);
+WEAK void CAN0_IRQ0_IRQHandler(void);
+WEAK void CAN0_IRQ1_IRQHandler(void);
+WEAK void CAN1_IRQ0_IRQHandler(void);
+WEAK void CAN1_IRQ1_IRQHandler(void);
+WEAK void USB1_IRQHandler(void);
+WEAK void USB1_NEEDCLK_IRQHandler(void);
+WEAK void ETHERNET_IRQHandler(void);
+WEAK void ETHERNET_PMT_IRQHandler(void);
+WEAK void ETHERNET_MACLP_IRQHandler(void);
+WEAK void Reserved68_IRQHandler(void);
+WEAK void LCD_IRQHandler(void);
+WEAK void SHA_IRQHandler(void);
+WEAK void SMARTCARD0_IRQHandler(void);
+WEAK void SMARTCARD1_IRQHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the driver IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the driver
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//*****************************************************************************
+void WDT_BOD_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_SEQA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_SEQB_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_THCMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DMIC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void HWVAD0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB0_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM10_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved47_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void RIT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SPIFI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM8_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM9_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN0_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN0_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN1_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN1_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB1_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ETHERNET_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ETHERNET_PMT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ETHERNET_MACLP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved68_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void LCD_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SHA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SMARTCARD0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SMARTCARD1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+
+//*****************************************************************************
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+
+//*****************************************************************************
+// External declaration for the pointer to the stack top from the Linker Script
+//*****************************************************************************
+extern void _vStackTop(void);
+extern void _image_size(void);
+//*****************************************************************************
+// External declaration for LPC MCU vector table checksum from  Linker Script
+//*****************************************************************************
+WEAK extern void __valid_user_code_checksum();
+
+//*****************************************************************************
+// External declaration for image type and load address from  Linker Script
+//*****************************************************************************
+WEAK extern void __imghdr_loadaddress();
+WEAK extern void __imghdr_imagetype();
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+#ifndef IMG_BAUDRATE
+#define IMG_BAUDRATE 0
+#endif
+//*****************************************************************************
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//*****************************************************************************
+
+
+
+extern void (* const g_pfnVectors[])(void);
+extern void * __Vectors __attribute__ ((alias ("g_pfnVectors")));
+
+__attribute__ ((used, section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+    // Core Level - CM4
+    &_vStackTop,                       // The initial stack pointer
+    ResetISR,                          // The reset handler
+    NMI_Handler,                       // The NMI handler
+    HardFault_Handler,                 // The hard fault handler
+    MemManage_Handler,                 // The MPU fault handler
+    BusFault_Handler,                  // The bus fault handler
+    UsageFault_Handler,                // The usage fault handler
+    __valid_user_code_checksum,        // LPC MCU checksum
+    0,                                 // ECRP
+    (void (*)(void))0xEDDC94BD,        // Reserved
+    (void (*)(void))0x160,             // Reserved
+    SVC_Handler,                       // SVCall handler
+    DebugMon_Handler,                  // Debug monitor handler
+    0,                                 // Reserved
+    PendSV_Handler,                    // The PendSV handler
+    SysTick_Handler,                   // The SysTick handler
+
+    // Chip Level - LPC54005
+    WDT_BOD_IRQHandler,         // 16: Windowed watchdog timer, Brownout detect
+    DMA0_IRQHandler,            // 17: DMA controller
+    GINT0_IRQHandler,           // 18: GPIO group 0
+    GINT1_IRQHandler,           // 19: GPIO group 1
+    PIN_INT0_IRQHandler,        // 20: Pin interrupt 0 or pattern match engine slice 0
+    PIN_INT1_IRQHandler,        // 21: Pin interrupt 1or pattern match engine slice 1
+    PIN_INT2_IRQHandler,        // 22: Pin interrupt 2 or pattern match engine slice 2
+    PIN_INT3_IRQHandler,        // 23: Pin interrupt 3 or pattern match engine slice 3
+    UTICK0_IRQHandler,          // 24: Micro-tick Timer
+    MRT0_IRQHandler,            // 25: Multi-rate timer
+    CTIMER0_IRQHandler,         // 26: Standard counter/timer CTIMER0
+    CTIMER1_IRQHandler,         // 27: Standard counter/timer CTIMER1
+    SCT0_IRQHandler,            // 28: SCTimer/PWM
+    CTIMER3_IRQHandler,         // 29: Standard counter/timer CTIMER3
+    FLEXCOMM0_IRQHandler,       // 30: Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM)
+    FLEXCOMM1_IRQHandler,       // 31: Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM)
+    FLEXCOMM2_IRQHandler,       // 32: Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM)
+    FLEXCOMM3_IRQHandler,       // 33: Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM)
+    FLEXCOMM4_IRQHandler,       // 34: Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM)
+    FLEXCOMM5_IRQHandler,       // 35: Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM)
+    FLEXCOMM6_IRQHandler,       // 36: Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM)
+    FLEXCOMM7_IRQHandler,       // 37: Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM)
+    ADC0_SEQA_IRQHandler,       // 38: ADC0 sequence A completion.
+    ADC0_SEQB_IRQHandler,       // 39: ADC0 sequence B completion.
+    ADC0_THCMP_IRQHandler,      // 40: ADC0 threshold compare and error.
+    DMIC0_IRQHandler,           // 41: Digital microphone and DMIC subsystem
+    HWVAD0_IRQHandler,          // 42: Hardware Voice Activity Detector
+    USB0_NEEDCLK_IRQHandler,    // 43: USB Activity Wake-up Interrupt
+    USB0_IRQHandler,            // 44: USB device
+    RTC_IRQHandler,             // 45: RTC alarm and wake-up interrupts
+    FLEXCOMM10_IRQHandler,      // 46: Flexcomm Interface 10 (SPI, FLEXCOMM)
+    Reserved47_IRQHandler,      // 47: Reserved interrupt
+    PIN_INT4_IRQHandler,        // 48: Pin interrupt 4 or pattern match engine slice 4 int
+    PIN_INT5_IRQHandler,        // 49: Pin interrupt 5 or pattern match engine slice 5 int
+    PIN_INT6_IRQHandler,        // 50: Pin interrupt 6 or pattern match engine slice 6 int
+    PIN_INT7_IRQHandler,        // 51: Pin interrupt 7 or pattern match engine slice 7 int
+    CTIMER2_IRQHandler,         // 52: Standard counter/timer CTIMER2
+    CTIMER4_IRQHandler,         // 53: Standard counter/timer CTIMER4
+    RIT_IRQHandler,             // 54: Repetitive Interrupt Timer
+    SPIFI0_IRQHandler,          // 55: SPI flash interface
+    FLEXCOMM8_IRQHandler,       // 56: Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM)
+    FLEXCOMM9_IRQHandler,       // 57: Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM)
+    SDIO_IRQHandler,            // 58: SD/MMC
+    CAN0_IRQ0_IRQHandler,       // 59: CAN0 interrupt0
+    CAN0_IRQ1_IRQHandler,       // 60: CAN0 interrupt1
+    CAN1_IRQ0_IRQHandler,       // 61: CAN1 interrupt0
+    CAN1_IRQ1_IRQHandler,       // 62: CAN1 interrupt1
+    USB1_IRQHandler,            // 63: USB1 interrupt
+    USB1_NEEDCLK_IRQHandler,    // 64: USB1 activity
+    ETHERNET_IRQHandler,        // 65: Ethernet
+    ETHERNET_PMT_IRQHandler,    // 66: Ethernet power management interrupt
+    ETHERNET_MACLP_IRQHandler,  // 67: Ethernet MAC interrupt
+    Reserved68_IRQHandler,      // 68: Reserved interrupt
+    LCD_IRQHandler,             // 69: LCD interrupt
+    SHA_IRQHandler,             // 70: SHA interrupt
+    SMARTCARD0_IRQHandler,      // 71: Smart card 0 interrupt
+    SMARTCARD1_IRQHandler,      // 72: Smart card 1 interrupt
+
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    (void (*)(void))0xFEEDA5A5, // Header Marker
+
+#if defined (ADD_CRC)
+    (__imghdr_imagetype - 1),   // (0x04) Image Type
+     __imghdr_loadaddress,      // (0x08) Load_address
+#else
+    __imghdr_imagetype,         // (0x04) Image Type
+    __imghdr_loadaddress,       // (0x08) Load_address
+#endif
+    (void (*)(void))(((unsigned)_image_size) - 4),            // (0x0C) load_length, exclude 4 bytes CRC field.
+    0,                          // (0x10) CRC value (only applicable to NON Non-secure images).
+    0,                          // (0x14) Version (only applicable to DUAL_ENH image type.
+    0,                          // (0x18) EMC static memory configuration settings, required for EMC boot
+    (void (*)(void))IMG_BAUDRATE,       // (0x1C) image baudrate
+    0,                          // (0x20) reserved
+    (void (*)(void))0xEDDC94BD,         // (0x24) Image_marker
+    0,                          // (0x28) SBZ
+    0,                          // (0x2C) reserved
+    #ifdef W25Q128JVFM
+    /* SPIFI Descriptor - W25Q128JVFM */
+    (void (*)(void))0x00000000,         // 0xFFFFFFFF to default 1-bit SPI mode  ；DevStrAdr
+    (void (*)(void))0x001870EF,         // mfgId + extCount
+    (void (*)(void))0x00000000,         // extid 0-3
+    (void (*)(void))0x00000000,         // extid 4-7
+    (void (*)(void))0x0001001D,         // caps
+    (void (*)(void))0x00000100,         // Blks + RESV1
+    (void (*)(void))0x00010000,         // blkSize
+    (void (*)(void))0x00000000,         // subBlks + subBlkSize
+    (void (*)(void))0x00000100,         // pageSize + RESV2
+    (void (*)(void))0x00003F00,         // maxReadSize
+    (void (*)(void))0x68506850,         // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate
+    (void (*)(void))0x04030050,         // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId,
+    (void (*)(void))0x14110D09,         // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId
+    #endif
+
+     #ifdef MXL12835F
+     /* SPI Descriptor - MXL12835F */
+    (void (*)(void))0x00000000,         // 0xFFFFFFFF to default 1-bit SPI mode  ;DevStrAdr
+    (void (*)(void))0x001820C2,         // mfgId + extCount
+    (void (*)(void))0x00000000,         // extid 0-3
+    (void (*)(void))0x00000000,         // extid 4-7
+    (void (*)(void))0x0001001D,         // caps
+    (void (*)(void))0x00000100,         // Blks + RESV1
+    (void (*)(void))0x00010000,         // blkSize
+    (void (*)(void))0x00000000,         // subBlks + subBlkSize
+    (void (*)(void))0x00000100,         // pageSize + RESV2
+    (void (*)(void))0x00003F00,         // maxReadSize
+    (void (*)(void))0x68506850,         // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate
+    (void (*)(void))0x06030050,         // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId
+    (void (*)(void))0x14110F0B,         // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId
+    #endif
+
+
+}; /* End of g_pfnVectors */
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors.init_data")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int *pulSrc = (unsigned int*) romstart;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors.init_bss")))
+void bss_init(unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors.reset")))
+void ResetISR(void) {
+
+    // Disable interrupts
+    __asm volatile ("cpsid i");
+
+
+    // Enable SRAM clock used by Stack
+    __asm volatile ("LDR R0, =0x40000220\n\t"
+                    "MOV R1, #56\n\t"
+                    "STR R1, [R0]");
+
+#if defined (__USE_CMSIS)
+// If __USE_CMSIS defined, then call CMSIS SystemInit code
+    SystemInit();
+
+#endif // (__USE_CMSIS)
+
+    //
+    // Copy the data sections from flash to SRAM.
+    //
+    unsigned int LoadAddr, ExeAddr, SectionLen;
+    unsigned int *SectionTableAddr;
+
+    // Load base address of Global Section Table
+    SectionTableAddr = &__data_section_table;
+
+    // Copy the data sections from flash to SRAM.
+    while (SectionTableAddr < &__data_section_table_end) {
+        LoadAddr = *SectionTableAddr++;
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        data_init(LoadAddr, ExeAddr, SectionLen);
+    }
+
+    // At this point, SectionTableAddr = &__bss_section_table;
+    // Zero fill the bss segment
+    while (SectionTableAddr < &__bss_section_table_end) {
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        bss_init(ExeAddr, SectionLen);
+    }
+
+#if !defined (__USE_CMSIS)
+// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
+// will enable the FPU
+#if defined (__VFP_FP__) && !defined (__SOFTFP__)
+    //
+    // Code to enable the Cortex-M4 FPU only included
+    // if appropriate build options have been selected.
+    // Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
+    //
+    // Read CPACR (located at address 0xE000ED88)
+    // Set bits 20-23 to enable CP10 and CP11 coprocessors
+    // Write back the modified value to the CPACR
+    asm volatile ("LDR.W R0, =0xE000ED88\n\t"
+                  "LDR R1, [R0]\n\t"
+                  "ORR R1, R1, #(0xF << 20)\n\t"
+                  "STR R1, [R0]");
+#endif // (__VFP_FP__) && !(__SOFTFP__)
+#endif // (__USE_CMSIS)
+
+
+#if !defined (__USE_CMSIS)
+// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
+// will setup the VTOR register
+
+    // Check to see if we are running the code from a non-zero
+    // address (eg RAM, external flash), in which case we need
+    // to modify the VTOR register to tell the CPU that the
+    // vector table is located at a non-0x0 address.
+    unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
+    if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
+        *pSCB_VTOR = (unsigned int)g_pfnVectors;
+    }
+#endif // (__USE_CMSIS)
+#if defined (__cplusplus)
+    //
+    // Call C++ library initialisation
+    //
+    __libc_init_array();
+#endif
+
+    // Reenable interrupts
+    __asm volatile ("cpsie i");
+
+#if defined (__REDLIB__)
+    // Call the Redlib library, which in turn calls main()
+    __main();
+#else
+    main();
+#endif
+
+    //
+    // main() shouldn't return, but if it does, we'll just enter an infinite loop
+    //
+    while (1) {
+        ;
+    }
+}
+
+//*****************************************************************************
+// Default core exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+WEAK_AV void NMI_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void HardFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void MemManage_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void BusFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void UsageFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void SVC_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void DebugMon_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void PendSV_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void SysTick_Handler(void)
+{ while(1) {}
+}
+
+//*****************************************************************************
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//*****************************************************************************
+WEAK_AV void IntDefaultHandler(void)
+{ while(1) {}
+}
+
+//*****************************************************************************
+// Default application exception handlers. Override the ones here by defining
+// your own handler routines in your application code. These routines call
+// driver exception handlers or IntDefaultHandler() if no driver exception
+// handler is included.
+//*****************************************************************************
+WEAK void WDT_BOD_IRQHandler(void)
+{   WDT_BOD_DriverIRQHandler();
+}
+
+WEAK void DMA0_IRQHandler(void)
+{   DMA0_DriverIRQHandler();
+}
+
+WEAK void GINT0_IRQHandler(void)
+{   GINT0_DriverIRQHandler();
+}
+
+WEAK void GINT1_IRQHandler(void)
+{   GINT1_DriverIRQHandler();
+}
+
+WEAK void PIN_INT0_IRQHandler(void)
+{   PIN_INT0_DriverIRQHandler();
+}
+
+WEAK void PIN_INT1_IRQHandler(void)
+{   PIN_INT1_DriverIRQHandler();
+}
+
+WEAK void PIN_INT2_IRQHandler(void)
+{   PIN_INT2_DriverIRQHandler();
+}
+
+WEAK void PIN_INT3_IRQHandler(void)
+{   PIN_INT3_DriverIRQHandler();
+}
+
+WEAK void UTICK0_IRQHandler(void)
+{   UTICK0_DriverIRQHandler();
+}
+
+WEAK void MRT0_IRQHandler(void)
+{   MRT0_DriverIRQHandler();
+}
+
+WEAK void CTIMER0_IRQHandler(void)
+{   CTIMER0_DriverIRQHandler();
+}
+
+WEAK void CTIMER1_IRQHandler(void)
+{   CTIMER1_DriverIRQHandler();
+}
+
+WEAK void SCT0_IRQHandler(void)
+{   SCT0_DriverIRQHandler();
+}
+
+WEAK void CTIMER3_IRQHandler(void)
+{   CTIMER3_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM0_IRQHandler(void)
+{   FLEXCOMM0_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM1_IRQHandler(void)
+{   FLEXCOMM1_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM2_IRQHandler(void)
+{   FLEXCOMM2_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM3_IRQHandler(void)
+{   FLEXCOMM3_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM4_IRQHandler(void)
+{   FLEXCOMM4_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM5_IRQHandler(void)
+{   FLEXCOMM5_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM6_IRQHandler(void)
+{   FLEXCOMM6_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM7_IRQHandler(void)
+{   FLEXCOMM7_DriverIRQHandler();
+}
+
+WEAK void ADC0_SEQA_IRQHandler(void)
+{   ADC0_SEQA_DriverIRQHandler();
+}
+
+WEAK void ADC0_SEQB_IRQHandler(void)
+{   ADC0_SEQB_DriverIRQHandler();
+}
+
+WEAK void ADC0_THCMP_IRQHandler(void)
+{   ADC0_THCMP_DriverIRQHandler();
+}
+
+WEAK void DMIC0_IRQHandler(void)
+{   DMIC0_DriverIRQHandler();
+}
+
+WEAK void HWVAD0_IRQHandler(void)
+{   HWVAD0_DriverIRQHandler();
+}
+
+WEAK void USB0_NEEDCLK_IRQHandler(void)
+{   USB0_NEEDCLK_DriverIRQHandler();
+}
+
+WEAK void USB0_IRQHandler(void)
+{   USB0_DriverIRQHandler();
+}
+
+WEAK void RTC_IRQHandler(void)
+{   RTC_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM10_IRQHandler(void)
+{   FLEXCOMM10_DriverIRQHandler();
+}
+
+WEAK void Reserved47_IRQHandler(void)
+{   Reserved47_DriverIRQHandler();
+}
+
+WEAK void PIN_INT4_IRQHandler(void)
+{   PIN_INT4_DriverIRQHandler();
+}
+
+WEAK void PIN_INT5_IRQHandler(void)
+{   PIN_INT5_DriverIRQHandler();
+}
+
+WEAK void PIN_INT6_IRQHandler(void)
+{   PIN_INT6_DriverIRQHandler();
+}
+
+WEAK void PIN_INT7_IRQHandler(void)
+{   PIN_INT7_DriverIRQHandler();
+}
+
+WEAK void CTIMER2_IRQHandler(void)
+{   CTIMER2_DriverIRQHandler();
+}
+
+WEAK void CTIMER4_IRQHandler(void)
+{   CTIMER4_DriverIRQHandler();
+}
+
+WEAK void RIT_IRQHandler(void)
+{   RIT_DriverIRQHandler();
+}
+
+WEAK void SPIFI0_IRQHandler(void)
+{   SPIFI0_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM8_IRQHandler(void)
+{   FLEXCOMM8_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM9_IRQHandler(void)
+{   FLEXCOMM9_DriverIRQHandler();
+}
+
+WEAK void SDIO_IRQHandler(void)
+{   SDIO_DriverIRQHandler();
+}
+
+WEAK void CAN0_IRQ0_IRQHandler(void)
+{   CAN0_IRQ0_DriverIRQHandler();
+}
+
+WEAK void CAN0_IRQ1_IRQHandler(void)
+{   CAN0_IRQ1_DriverIRQHandler();
+}
+
+WEAK void CAN1_IRQ0_IRQHandler(void)
+{   CAN1_IRQ0_DriverIRQHandler();
+}
+
+WEAK void CAN1_IRQ1_IRQHandler(void)
+{   CAN1_IRQ1_DriverIRQHandler();
+}
+
+WEAK void USB1_IRQHandler(void)
+{   USB1_DriverIRQHandler();
+}
+
+WEAK void USB1_NEEDCLK_IRQHandler(void)
+{   USB1_NEEDCLK_DriverIRQHandler();
+}
+
+WEAK void ETHERNET_IRQHandler(void)
+{   ETHERNET_DriverIRQHandler();
+}
+
+WEAK void ETHERNET_PMT_IRQHandler(void)
+{   ETHERNET_PMT_DriverIRQHandler();
+}
+
+WEAK void ETHERNET_MACLP_IRQHandler(void)
+{   ETHERNET_MACLP_DriverIRQHandler();
+}
+
+WEAK void Reserved68_IRQHandler(void)
+{   Reserved68_DriverIRQHandler();
+}
+
+WEAK void LCD_IRQHandler(void)
+{   LCD_DriverIRQHandler();
+}
+
+WEAK void SHA_IRQHandler(void)
+{   SHA_DriverIRQHandler();
+}
+
+WEAK void SMARTCARD0_IRQHandler(void)
+{   SMARTCARD0_DriverIRQHandler();
+}
+
+WEAK void SMARTCARD1_IRQHandler(void)
+{   SMARTCARD1_DriverIRQHandler();
+}
+
+//*****************************************************************************
+
+#if defined (DEBUG)
+#pragma GCC pop_options
+#endif // (DEBUG)
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/mcuxpresso/startup_lpc54005.cpp b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/mcuxpresso/startup_lpc54005.cpp
new file mode 100644
index 000000000..39943aa41
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/mcuxpresso/startup_lpc54005.cpp
@@ -0,0 +1,824 @@
+//*****************************************************************************
+// LPC54005 startup code for use with MCUXpresso IDE
+//
+// Version : 160420
+//*****************************************************************************
+//
+// Copyright 2016-2020 NXP
+// All rights reserved.
+//
+// SPDX-License-Identifier: BSD-3-Clause
+//*****************************************************************************
+
+#if defined (DEBUG)
+#pragma GCC push_options
+#pragma GCC optimize ("Og")
+#endif // (DEBUG)
+
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+    extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define WEAK_AV __attribute__ ((weak, section(".after_vectors")))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+// Variable to store CRP value in. Will be placed automatically
+// by the linker when "Enable Code Read Protect" selected.
+// See crp.h header for more information
+//*****************************************************************************
+#include <NXP/crp.h>
+__CRP const unsigned int CRP_WORD = CRP_NO_CRP ;
+
+//*****************************************************************************
+// Declaration of external SystemInit function
+//*****************************************************************************
+#if defined (__USE_CMSIS)
+extern void SystemInit(void);
+#endif // (__USE_CMSIS)
+
+//*****************************************************************************
+// Forward declaration of the core exception handlers.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions.
+// If your application is a C++ one, then any interrupt handlers defined
+// in C++ files within in your main application will need to have C linkage
+// rather than C++ linkage. To do this, make sure that you are using extern "C"
+// { .... } around the interrupt handler within your main application code.
+//*****************************************************************************
+     void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the application IRQ handlers. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over weak definitions below
+//*****************************************************************************
+WEAK void WDT_BOD_IRQHandler(void);
+WEAK void DMA0_IRQHandler(void);
+WEAK void GINT0_IRQHandler(void);
+WEAK void GINT1_IRQHandler(void);
+WEAK void PIN_INT0_IRQHandler(void);
+WEAK void PIN_INT1_IRQHandler(void);
+WEAK void PIN_INT2_IRQHandler(void);
+WEAK void PIN_INT3_IRQHandler(void);
+WEAK void UTICK0_IRQHandler(void);
+WEAK void MRT0_IRQHandler(void);
+WEAK void CTIMER0_IRQHandler(void);
+WEAK void CTIMER1_IRQHandler(void);
+WEAK void SCT0_IRQHandler(void);
+WEAK void CTIMER3_IRQHandler(void);
+WEAK void FLEXCOMM0_IRQHandler(void);
+WEAK void FLEXCOMM1_IRQHandler(void);
+WEAK void FLEXCOMM2_IRQHandler(void);
+WEAK void FLEXCOMM3_IRQHandler(void);
+WEAK void FLEXCOMM4_IRQHandler(void);
+WEAK void FLEXCOMM5_IRQHandler(void);
+WEAK void FLEXCOMM6_IRQHandler(void);
+WEAK void FLEXCOMM7_IRQHandler(void);
+WEAK void ADC0_SEQA_IRQHandler(void);
+WEAK void ADC0_SEQB_IRQHandler(void);
+WEAK void ADC0_THCMP_IRQHandler(void);
+WEAK void DMIC0_IRQHandler(void);
+WEAK void HWVAD0_IRQHandler(void);
+WEAK void USB0_NEEDCLK_IRQHandler(void);
+WEAK void USB0_IRQHandler(void);
+WEAK void RTC_IRQHandler(void);
+WEAK void FLEXCOMM10_IRQHandler(void);
+WEAK void Reserved47_IRQHandler(void);
+WEAK void PIN_INT4_IRQHandler(void);
+WEAK void PIN_INT5_IRQHandler(void);
+WEAK void PIN_INT6_IRQHandler(void);
+WEAK void PIN_INT7_IRQHandler(void);
+WEAK void CTIMER2_IRQHandler(void);
+WEAK void CTIMER4_IRQHandler(void);
+WEAK void RIT_IRQHandler(void);
+WEAK void SPIFI0_IRQHandler(void);
+WEAK void FLEXCOMM8_IRQHandler(void);
+WEAK void FLEXCOMM9_IRQHandler(void);
+WEAK void SDIO_IRQHandler(void);
+WEAK void CAN0_IRQ0_IRQHandler(void);
+WEAK void CAN0_IRQ1_IRQHandler(void);
+WEAK void CAN1_IRQ0_IRQHandler(void);
+WEAK void CAN1_IRQ1_IRQHandler(void);
+WEAK void USB1_IRQHandler(void);
+WEAK void USB1_NEEDCLK_IRQHandler(void);
+WEAK void ETHERNET_IRQHandler(void);
+WEAK void ETHERNET_PMT_IRQHandler(void);
+WEAK void ETHERNET_MACLP_IRQHandler(void);
+WEAK void Reserved68_IRQHandler(void);
+WEAK void LCD_IRQHandler(void);
+WEAK void SHA_IRQHandler(void);
+WEAK void SMARTCARD0_IRQHandler(void);
+WEAK void SMARTCARD1_IRQHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the driver IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the driver
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//*****************************************************************************
+void WDT_BOD_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_SEQA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_SEQB_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_THCMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DMIC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void HWVAD0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB0_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM10_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved47_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void RIT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SPIFI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM8_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM9_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN0_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN0_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN1_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN1_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB1_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ETHERNET_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ETHERNET_PMT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ETHERNET_MACLP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved68_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void LCD_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SHA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SMARTCARD0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SMARTCARD1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+
+//*****************************************************************************
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+
+//*****************************************************************************
+// External declaration for the pointer to the stack top from the Linker Script
+//*****************************************************************************
+extern void _vStackTop(void);
+extern void _image_size(void);
+//*****************************************************************************
+// External declaration for LPC MCU vector table checksum from  Linker Script
+//*****************************************************************************
+WEAK extern void __valid_user_code_checksum();
+
+//*****************************************************************************
+// External declaration for image type and load address from  Linker Script
+//*****************************************************************************
+WEAK extern void __imghdr_loadaddress();
+WEAK extern void __imghdr_imagetype();
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+#ifndef IMG_BAUDRATE
+#define IMG_BAUDRATE 0
+#endif
+//*****************************************************************************
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//*****************************************************************************
+
+
+
+extern void (* const g_pfnVectors[])(void);
+extern void * __Vectors __attribute__ ((alias ("g_pfnVectors")));
+
+__attribute__ ((used, section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+    // Core Level - CM4
+    &_vStackTop,                       // The initial stack pointer
+    ResetISR,                          // The reset handler
+    NMI_Handler,                       // The NMI handler
+    HardFault_Handler,                 // The hard fault handler
+    MemManage_Handler,                 // The MPU fault handler
+    BusFault_Handler,                  // The bus fault handler
+    UsageFault_Handler,                // The usage fault handler
+    __valid_user_code_checksum,        // LPC MCU checksum
+    0,                                 // ECRP
+    (void (*)(void))0xEDDC94BD,        // Reserved
+    (void (*)(void))0x160,             // Reserved
+    SVC_Handler,                       // SVCall handler
+    DebugMon_Handler,                  // Debug monitor handler
+    0,                                 // Reserved
+    PendSV_Handler,                    // The PendSV handler
+    SysTick_Handler,                   // The SysTick handler
+
+    // Chip Level - LPC54005
+    WDT_BOD_IRQHandler,         // 16: Windowed watchdog timer, Brownout detect
+    DMA0_IRQHandler,            // 17: DMA controller
+    GINT0_IRQHandler,           // 18: GPIO group 0
+    GINT1_IRQHandler,           // 19: GPIO group 1
+    PIN_INT0_IRQHandler,        // 20: Pin interrupt 0 or pattern match engine slice 0
+    PIN_INT1_IRQHandler,        // 21: Pin interrupt 1or pattern match engine slice 1
+    PIN_INT2_IRQHandler,        // 22: Pin interrupt 2 or pattern match engine slice 2
+    PIN_INT3_IRQHandler,        // 23: Pin interrupt 3 or pattern match engine slice 3
+    UTICK0_IRQHandler,          // 24: Micro-tick Timer
+    MRT0_IRQHandler,            // 25: Multi-rate timer
+    CTIMER0_IRQHandler,         // 26: Standard counter/timer CTIMER0
+    CTIMER1_IRQHandler,         // 27: Standard counter/timer CTIMER1
+    SCT0_IRQHandler,            // 28: SCTimer/PWM
+    CTIMER3_IRQHandler,         // 29: Standard counter/timer CTIMER3
+    FLEXCOMM0_IRQHandler,       // 30: Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM)
+    FLEXCOMM1_IRQHandler,       // 31: Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM)
+    FLEXCOMM2_IRQHandler,       // 32: Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM)
+    FLEXCOMM3_IRQHandler,       // 33: Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM)
+    FLEXCOMM4_IRQHandler,       // 34: Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM)
+    FLEXCOMM5_IRQHandler,       // 35: Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM)
+    FLEXCOMM6_IRQHandler,       // 36: Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM)
+    FLEXCOMM7_IRQHandler,       // 37: Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM)
+    ADC0_SEQA_IRQHandler,       // 38: ADC0 sequence A completion.
+    ADC0_SEQB_IRQHandler,       // 39: ADC0 sequence B completion.
+    ADC0_THCMP_IRQHandler,      // 40: ADC0 threshold compare and error.
+    DMIC0_IRQHandler,           // 41: Digital microphone and DMIC subsystem
+    HWVAD0_IRQHandler,          // 42: Hardware Voice Activity Detector
+    USB0_NEEDCLK_IRQHandler,    // 43: USB Activity Wake-up Interrupt
+    USB0_IRQHandler,            // 44: USB device
+    RTC_IRQHandler,             // 45: RTC alarm and wake-up interrupts
+    FLEXCOMM10_IRQHandler,      // 46: Flexcomm Interface 10 (SPI, FLEXCOMM)
+    Reserved47_IRQHandler,      // 47: Reserved interrupt
+    PIN_INT4_IRQHandler,        // 48: Pin interrupt 4 or pattern match engine slice 4 int
+    PIN_INT5_IRQHandler,        // 49: Pin interrupt 5 or pattern match engine slice 5 int
+    PIN_INT6_IRQHandler,        // 50: Pin interrupt 6 or pattern match engine slice 6 int
+    PIN_INT7_IRQHandler,        // 51: Pin interrupt 7 or pattern match engine slice 7 int
+    CTIMER2_IRQHandler,         // 52: Standard counter/timer CTIMER2
+    CTIMER4_IRQHandler,         // 53: Standard counter/timer CTIMER4
+    RIT_IRQHandler,             // 54: Repetitive Interrupt Timer
+    SPIFI0_IRQHandler,          // 55: SPI flash interface
+    FLEXCOMM8_IRQHandler,       // 56: Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM)
+    FLEXCOMM9_IRQHandler,       // 57: Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM)
+    SDIO_IRQHandler,            // 58: SD/MMC
+    CAN0_IRQ0_IRQHandler,       // 59: CAN0 interrupt0
+    CAN0_IRQ1_IRQHandler,       // 60: CAN0 interrupt1
+    CAN1_IRQ0_IRQHandler,       // 61: CAN1 interrupt0
+    CAN1_IRQ1_IRQHandler,       // 62: CAN1 interrupt1
+    USB1_IRQHandler,            // 63: USB1 interrupt
+    USB1_NEEDCLK_IRQHandler,    // 64: USB1 activity
+    ETHERNET_IRQHandler,        // 65: Ethernet
+    ETHERNET_PMT_IRQHandler,    // 66: Ethernet power management interrupt
+    ETHERNET_MACLP_IRQHandler,  // 67: Ethernet MAC interrupt
+    Reserved68_IRQHandler,      // 68: Reserved interrupt
+    LCD_IRQHandler,             // 69: LCD interrupt
+    SHA_IRQHandler,             // 70: SHA interrupt
+    SMARTCARD0_IRQHandler,      // 71: Smart card 0 interrupt
+    SMARTCARD1_IRQHandler,      // 72: Smart card 1 interrupt
+
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    (void (*)(void))0xFEEDA5A5, // Header Marker
+
+#if defined (ADD_CRC)
+    (__imghdr_imagetype - 1),   // (0x04) Image Type
+     __imghdr_loadaddress,      // (0x08) Load_address
+#else
+    __imghdr_imagetype,         // (0x04) Image Type
+    __imghdr_loadaddress,       // (0x08) Load_address
+#endif
+    (void (*)(void))(((unsigned)_image_size) - 4),            // (0x0C) load_length, exclude 4 bytes CRC field.
+    0,                          // (0x10) CRC value (only applicable to NON Non-secure images).
+    0,                          // (0x14) Version (only applicable to DUAL_ENH image type.
+    0,                          // (0x18) EMC static memory configuration settings, required for EMC boot
+    (void (*)(void))IMG_BAUDRATE,       // (0x1C) image baudrate
+    0,                          // (0x20) reserved
+    (void (*)(void))0xEDDC94BD,         // (0x24) Image_marker
+    0,                          // (0x28) SBZ
+    0,                          // (0x2C) reserved
+    #ifdef W25Q128JVFM
+    /* SPIFI Descriptor - W25Q128JVFM */
+    (void (*)(void))0x00000000,         // 0xFFFFFFFF to default 1-bit SPI mode  ；DevStrAdr
+    (void (*)(void))0x001870EF,         // mfgId + extCount
+    (void (*)(void))0x00000000,         // extid 0-3
+    (void (*)(void))0x00000000,         // extid 4-7
+    (void (*)(void))0x0001001D,         // caps
+    (void (*)(void))0x00000100,         // Blks + RESV1
+    (void (*)(void))0x00010000,         // blkSize
+    (void (*)(void))0x00000000,         // subBlks + subBlkSize
+    (void (*)(void))0x00000100,         // pageSize + RESV2
+    (void (*)(void))0x00003F00,         // maxReadSize
+    (void (*)(void))0x68506850,         // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate
+    (void (*)(void))0x04030050,         // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId,
+    (void (*)(void))0x14110D09,         // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId
+    #endif
+
+     #ifdef MXL12835F
+     /* SPI Descriptor - MXL12835F */
+    (void (*)(void))0x00000000,         // 0xFFFFFFFF to default 1-bit SPI mode  ;DevStrAdr
+    (void (*)(void))0x001820C2,         // mfgId + extCount
+    (void (*)(void))0x00000000,         // extid 0-3
+    (void (*)(void))0x00000000,         // extid 4-7
+    (void (*)(void))0x0001001D,         // caps
+    (void (*)(void))0x00000100,         // Blks + RESV1
+    (void (*)(void))0x00010000,         // blkSize
+    (void (*)(void))0x00000000,         // subBlks + subBlkSize
+    (void (*)(void))0x00000100,         // pageSize + RESV2
+    (void (*)(void))0x00003F00,         // maxReadSize
+    (void (*)(void))0x68506850,         // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate
+    (void (*)(void))0x06030050,         // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId
+    (void (*)(void))0x14110F0B,         // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId
+    #endif
+
+
+}; /* End of g_pfnVectors */
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors.init_data")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int *pulSrc = (unsigned int*) romstart;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors.init_bss")))
+void bss_init(unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors.reset")))
+void ResetISR(void) {
+
+    // Disable interrupts
+    __asm volatile ("cpsid i");
+
+
+    // Enable SRAM clock used by Stack
+    __asm volatile ("LDR R0, =0x40000220\n\t"
+                    "MOV R1, #56\n\t"
+                    "STR R1, [R0]");
+
+#if defined (__USE_CMSIS)
+// If __USE_CMSIS defined, then call CMSIS SystemInit code
+    SystemInit();
+
+#endif // (__USE_CMSIS)
+
+    //
+    // Copy the data sections from flash to SRAM.
+    //
+    unsigned int LoadAddr, ExeAddr, SectionLen;
+    unsigned int *SectionTableAddr;
+
+    // Load base address of Global Section Table
+    SectionTableAddr = &__data_section_table;
+
+    // Copy the data sections from flash to SRAM.
+    while (SectionTableAddr < &__data_section_table_end) {
+        LoadAddr = *SectionTableAddr++;
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        data_init(LoadAddr, ExeAddr, SectionLen);
+    }
+
+    // At this point, SectionTableAddr = &__bss_section_table;
+    // Zero fill the bss segment
+    while (SectionTableAddr < &__bss_section_table_end) {
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        bss_init(ExeAddr, SectionLen);
+    }
+
+#if !defined (__USE_CMSIS)
+// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
+// will enable the FPU
+#if defined (__VFP_FP__) && !defined (__SOFTFP__)
+    //
+    // Code to enable the Cortex-M4 FPU only included
+    // if appropriate build options have been selected.
+    // Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
+    //
+    // Read CPACR (located at address 0xE000ED88)
+    // Set bits 20-23 to enable CP10 and CP11 coprocessors
+    // Write back the modified value to the CPACR
+    asm volatile ("LDR.W R0, =0xE000ED88\n\t"
+                  "LDR R1, [R0]\n\t"
+                  "ORR R1, R1, #(0xF << 20)\n\t"
+                  "STR R1, [R0]");
+#endif // (__VFP_FP__) && !(__SOFTFP__)
+#endif // (__USE_CMSIS)
+
+
+#if !defined (__USE_CMSIS)
+// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
+// will setup the VTOR register
+
+    // Check to see if we are running the code from a non-zero
+    // address (eg RAM, external flash), in which case we need
+    // to modify the VTOR register to tell the CPU that the
+    // vector table is located at a non-0x0 address.
+    unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
+    if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
+        *pSCB_VTOR = (unsigned int)g_pfnVectors;
+    }
+#endif // (__USE_CMSIS)
+#if defined (__cplusplus)
+    //
+    // Call C++ library initialisation
+    //
+    __libc_init_array();
+#endif
+
+    // Reenable interrupts
+    __asm volatile ("cpsie i");
+
+#if defined (__REDLIB__)
+    // Call the Redlib library, which in turn calls main()
+    __main();
+#else
+    main();
+#endif
+
+    //
+    // main() shouldn't return, but if it does, we'll just enter an infinite loop
+    //
+    while (1) {
+        ;
+    }
+}
+
+//*****************************************************************************
+// Default core exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+WEAK_AV void NMI_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void HardFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void MemManage_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void BusFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void UsageFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void SVC_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void DebugMon_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void PendSV_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void SysTick_Handler(void)
+{ while(1) {}
+}
+
+//*****************************************************************************
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//*****************************************************************************
+WEAK_AV void IntDefaultHandler(void)
+{ while(1) {}
+}
+
+//*****************************************************************************
+// Default application exception handlers. Override the ones here by defining
+// your own handler routines in your application code. These routines call
+// driver exception handlers or IntDefaultHandler() if no driver exception
+// handler is included.
+//*****************************************************************************
+WEAK void WDT_BOD_IRQHandler(void)
+{   WDT_BOD_DriverIRQHandler();
+}
+
+WEAK void DMA0_IRQHandler(void)
+{   DMA0_DriverIRQHandler();
+}
+
+WEAK void GINT0_IRQHandler(void)
+{   GINT0_DriverIRQHandler();
+}
+
+WEAK void GINT1_IRQHandler(void)
+{   GINT1_DriverIRQHandler();
+}
+
+WEAK void PIN_INT0_IRQHandler(void)
+{   PIN_INT0_DriverIRQHandler();
+}
+
+WEAK void PIN_INT1_IRQHandler(void)
+{   PIN_INT1_DriverIRQHandler();
+}
+
+WEAK void PIN_INT2_IRQHandler(void)
+{   PIN_INT2_DriverIRQHandler();
+}
+
+WEAK void PIN_INT3_IRQHandler(void)
+{   PIN_INT3_DriverIRQHandler();
+}
+
+WEAK void UTICK0_IRQHandler(void)
+{   UTICK0_DriverIRQHandler();
+}
+
+WEAK void MRT0_IRQHandler(void)
+{   MRT0_DriverIRQHandler();
+}
+
+WEAK void CTIMER0_IRQHandler(void)
+{   CTIMER0_DriverIRQHandler();
+}
+
+WEAK void CTIMER1_IRQHandler(void)
+{   CTIMER1_DriverIRQHandler();
+}
+
+WEAK void SCT0_IRQHandler(void)
+{   SCT0_DriverIRQHandler();
+}
+
+WEAK void CTIMER3_IRQHandler(void)
+{   CTIMER3_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM0_IRQHandler(void)
+{   FLEXCOMM0_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM1_IRQHandler(void)
+{   FLEXCOMM1_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM2_IRQHandler(void)
+{   FLEXCOMM2_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM3_IRQHandler(void)
+{   FLEXCOMM3_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM4_IRQHandler(void)
+{   FLEXCOMM4_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM5_IRQHandler(void)
+{   FLEXCOMM5_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM6_IRQHandler(void)
+{   FLEXCOMM6_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM7_IRQHandler(void)
+{   FLEXCOMM7_DriverIRQHandler();
+}
+
+WEAK void ADC0_SEQA_IRQHandler(void)
+{   ADC0_SEQA_DriverIRQHandler();
+}
+
+WEAK void ADC0_SEQB_IRQHandler(void)
+{   ADC0_SEQB_DriverIRQHandler();
+}
+
+WEAK void ADC0_THCMP_IRQHandler(void)
+{   ADC0_THCMP_DriverIRQHandler();
+}
+
+WEAK void DMIC0_IRQHandler(void)
+{   DMIC0_DriverIRQHandler();
+}
+
+WEAK void HWVAD0_IRQHandler(void)
+{   HWVAD0_DriverIRQHandler();
+}
+
+WEAK void USB0_NEEDCLK_IRQHandler(void)
+{   USB0_NEEDCLK_DriverIRQHandler();
+}
+
+WEAK void USB0_IRQHandler(void)
+{   USB0_DriverIRQHandler();
+}
+
+WEAK void RTC_IRQHandler(void)
+{   RTC_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM10_IRQHandler(void)
+{   FLEXCOMM10_DriverIRQHandler();
+}
+
+WEAK void Reserved47_IRQHandler(void)
+{   Reserved47_DriverIRQHandler();
+}
+
+WEAK void PIN_INT4_IRQHandler(void)
+{   PIN_INT4_DriverIRQHandler();
+}
+
+WEAK void PIN_INT5_IRQHandler(void)
+{   PIN_INT5_DriverIRQHandler();
+}
+
+WEAK void PIN_INT6_IRQHandler(void)
+{   PIN_INT6_DriverIRQHandler();
+}
+
+WEAK void PIN_INT7_IRQHandler(void)
+{   PIN_INT7_DriverIRQHandler();
+}
+
+WEAK void CTIMER2_IRQHandler(void)
+{   CTIMER2_DriverIRQHandler();
+}
+
+WEAK void CTIMER4_IRQHandler(void)
+{   CTIMER4_DriverIRQHandler();
+}
+
+WEAK void RIT_IRQHandler(void)
+{   RIT_DriverIRQHandler();
+}
+
+WEAK void SPIFI0_IRQHandler(void)
+{   SPIFI0_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM8_IRQHandler(void)
+{   FLEXCOMM8_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM9_IRQHandler(void)
+{   FLEXCOMM9_DriverIRQHandler();
+}
+
+WEAK void SDIO_IRQHandler(void)
+{   SDIO_DriverIRQHandler();
+}
+
+WEAK void CAN0_IRQ0_IRQHandler(void)
+{   CAN0_IRQ0_DriverIRQHandler();
+}
+
+WEAK void CAN0_IRQ1_IRQHandler(void)
+{   CAN0_IRQ1_DriverIRQHandler();
+}
+
+WEAK void CAN1_IRQ0_IRQHandler(void)
+{   CAN1_IRQ0_DriverIRQHandler();
+}
+
+WEAK void CAN1_IRQ1_IRQHandler(void)
+{   CAN1_IRQ1_DriverIRQHandler();
+}
+
+WEAK void USB1_IRQHandler(void)
+{   USB1_DriverIRQHandler();
+}
+
+WEAK void USB1_NEEDCLK_IRQHandler(void)
+{   USB1_NEEDCLK_DriverIRQHandler();
+}
+
+WEAK void ETHERNET_IRQHandler(void)
+{   ETHERNET_DriverIRQHandler();
+}
+
+WEAK void ETHERNET_PMT_IRQHandler(void)
+{   ETHERNET_PMT_DriverIRQHandler();
+}
+
+WEAK void ETHERNET_MACLP_IRQHandler(void)
+{   ETHERNET_MACLP_DriverIRQHandler();
+}
+
+WEAK void Reserved68_IRQHandler(void)
+{   Reserved68_DriverIRQHandler();
+}
+
+WEAK void LCD_IRQHandler(void)
+{   LCD_DriverIRQHandler();
+}
+
+WEAK void SHA_IRQHandler(void)
+{   SHA_DriverIRQHandler();
+}
+
+WEAK void SMARTCARD0_IRQHandler(void)
+{   SMARTCARD0_DriverIRQHandler();
+}
+
+WEAK void SMARTCARD1_IRQHandler(void)
+{   SMARTCARD1_DriverIRQHandler();
+}
+
+//*****************************************************************************
+
+#if defined (DEBUG)
+#pragma GCC pop_options
+#endif // (DEBUG)
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/board.c
new file mode 100644
index 000000000..64fddff63
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/board.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include "fsl_common.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Clock rate on the CLKIN pin */
+const uint32_t ExtClockIn = BOARD_EXTCLKINRATE;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+status_t BOARD_InitDebugConsole(void)
+{
+#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))
+    status_t result;
+    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+    CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
+    RESET_PeripheralReset(BOARD_DEBUG_UART_RST);
+    result = DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM,
+                             BOARD_DEBUG_UART_CLK_FREQ);
+    assert(kStatus_Success == result);
+    return result;
+#else
+    return kStatus_Success;
+#endif
+}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/board.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/board.h
new file mode 100644
index 000000000..0cd139f97
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/board.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_common.h"
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "LPCXPRESSO54608"
+
+#define BOARD_EXTCLKINRATE (0)
+
+/*! @brief The UART to use for debug messages. */
+/* TODO: rename UART to USART */
+#define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) USART0
+#define BOARD_DEBUG_UART_INSTANCE 0U
+#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetFreq(kCLOCK_Flexcomm0)
+#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0
+#define BOARD_DEBUG_UART_RST kFC0_RST_SHIFT_RSTn
+#define BOARD_DEBUG_UART_CLKSRC kCLOCK_Flexcomm0
+#define BOARD_UART_IRQ_HANDLER FLEXCOMM0_IRQHandler
+#define BOARD_UART_IRQ FLEXCOMM0_IRQn
+/* TODO: obsolete */
+#define BOARD_DEBUG_SPI_CLK_FREQ 12000000
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE 115200
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+#ifndef BOARD_LED_RED_GPIO
+#define BOARD_LED_RED_GPIO GPIO
+#endif
+#define BOARD_LED_RED_GPIO_PORT 3U
+#ifndef BOARD_LED_RED_GPIO_PIN
+#define BOARD_LED_RED_GPIO_PIN 14U
+#endif
+#ifndef BOARD_LED_GREEN_GPIO
+#define BOARD_LED_GREEN_GPIO GPIO
+#endif
+#define BOARD_LED_GREEN_GPIO_PORT 2U
+#ifndef BOARD_LED_GREEN_GPIO_PIN
+#define BOARD_LED_GREEN_GPIO_PIN 2U
+#endif
+#ifndef BOARD_LED_BLUE_GPIO
+#define BOARD_LED_BLUE_GPIO GPIO
+#endif
+#define BOARD_LED_BLUE_GPIO_PORT 3U
+#ifndef BOARD_LED_BLUE_GPIO_PIN
+#define BOARD_LED_BLUE_GPIO_PIN 3U
+#endif
+
+/* Board led color mapping */
+#define LOGIC_LED_ON 0U
+#define LOGIC_LED_OFF 1U
+
+#define LED_RED_INIT(output)                                                          \
+    GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, \
+                 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_RED */
+#define LED_RED_ON()                                                  \
+    GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                         1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED */
+#define LED_RED_OFF()                                               \
+    GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                       1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */
+#define LED_RED_TOGGLE()                                               \
+    GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                          1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */
+
+#define LED_GREEN_INIT(output)                                                              \
+    GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \
+                 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_GREEN */
+#define LED_GREEN_ON()                                                    \
+    GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                         1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */
+#define LED_GREEN_OFF()                                                 \
+    GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                       1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */
+#define LED_GREEN_TOGGLE()                                                 \
+    GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                          1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */
+
+#define LED_BLUE_INIT(output)                                                            \
+    GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \
+                 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_BLUE */
+#define LED_BLUE_ON()                                                   \
+    GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                         1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */
+#define LED_BLUE_OFF()                                                \
+    GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                       1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */
+#define LED_BLUE_TOGGLE()                                                \
+    GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                          1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+status_t BOARD_InitDebugConsole(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/clock_config.c
new file mode 100644
index 000000000..605114391
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/clock_config.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2018 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Setup voltage for the fastest of the clock outputs
+ *
+ * 3. Set up wait states of the flash.
+ *
+ * 4. Set up all dividers.
+ *
+ * 5. Set up all selectors to provide selected clocks.
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v5.0
+processor: LPC54005
+mcu_data: ksdk2_0
+processor_version: 0.0.8
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: FRO12M_clock.outFreq, value: 12 MHz}
+- {id: FROHF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN);                   /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                  /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
+                                                                being below the voltage for current speed */
+    POWER_SetVoltageForFreq(12000000U);             /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);                  /*!< Reset divider counter and set divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                     /*!< Switch MAIN_CLK to FRO12M */
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
+
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/clock_config.h
new file mode 100644
index 000000000..363742ab0
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/clock_config.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2018 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         12000000U  /*!< Board xtal0 frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK   12000000U    /*!< Core clock frequency:12000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/peripherals.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/peripherals.c
new file mode 100644
index 000000000..11ab6863a
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/peripherals.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2019 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Peripherals v6.0
+processor: LPC54005
+mcu_data: ksdk2_0
+processor_version: 0.0.15
+functionalGroups:
+- name: BOARD_InitPeripherals
+  called_from_default_init: true
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'system'
+- type_id: 'system_54b53072540eeeb8f8e9343e71f28176'
+- global_system_definitions: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "peripherals.h"
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+void BOARD_InitPeripherals(void)
+{
+}
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void)
+{
+  BOARD_InitPeripherals();
+}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/peripherals.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/peripherals.h
new file mode 100644
index 000000000..150360637
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/peripherals.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2019 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PERIPHERALS_H_
+#define _PERIPHERALS_H_
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+void BOARD_InitPeripherals(void);
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _PERIPHERALS_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/pin_mux.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/pin_mux.c
new file mode 100644
index 000000000..0dc94c6ee
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/pin_mux.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2019 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v6.0
+processor: LPC54005
+mcu_data: ksdk2_0
+processor_version: 0.0.15
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', enableClock: 'true'}
+- pin_list: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M4F */
+void BOARD_InitPins(void)
+{
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/pin_mux.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/pin_mux.h
new file mode 100644
index 000000000..9b6492aad
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/project_template/pin_mux.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2019 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /* Function assigned for the Cortex-M4F */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/system_LPC54005.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/system_LPC54005.c
new file mode 100644
index 000000000..1ac1431a6
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/system_LPC54005.c
@@ -0,0 +1,371 @@
+/*
+** ###################################################################
+**     Processors:          LPC54005JBD100
+**                          LPC54005JET100
+**
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
+**     Version:             rev. 1.2, 2017-06-08
+**     Build:               b201015
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2020 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**     - rev. 1.2 (2017-06-08)
+**         Remove RTC_CTRL_RTC_OSC_BYPASS.
+**         SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
+**         Remove RESET and HALT from SYSCON_AHBCLKDIV.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54005
+ * @version 1.2
+ * @date 2017-06-08
+ * @brief Device specific configuration file for LPC54005 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+#define NVALMAX        (0x100)
+#define PVALMAX        (0x20)
+#define MVALMAX        (0x8000)
+#define PLL_MDEC_VAL_P (0) /* MDEC is in bits  16:0 */
+#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
+#define PLL_NDEC_VAL_P (0) /* NDEC is in bits  9:0 */
+#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
+#define PLL_PDEC_VAL_P (0) /* PDEC is in bits  6:0 */
+#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
+
+static const uint8_t wdtFreqLookup[32] = {0,  8,  12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41,
+                                          42, 44, 45, 46, 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
+/* Get WATCH DOG Clk */
+static uint32_t getWdtOscFreq(void)
+{
+    uint8_t freq_sel, div_sel;
+    if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) != 0UL)
+    {
+        return 0U;
+    }
+    else
+    {
+        div_sel = (uint8_t)((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1UL) << 1UL;
+        freq_sel =
+            wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
+        return ((uint32_t)freq_sel * 50000U) / ((uint32_t)div_sel);
+    }
+}
+/* Find decoded N value for raw NDEC value */
+static uint32_t pllDecodeN(uint32_t NDEC)
+{
+    uint32_t n, x, i;
+
+    /* Find NDec */
+    switch (NDEC)
+    {
+        case 0x3FF:
+            n = 0UL;
+            break;
+        case 0x302:
+            n = 1UL;
+            break;
+        case 0x202:
+            n = 2UL;
+            break;
+        default:
+            x = 0x080UL;
+            n = 0xFFFFFFFFUL;
+            for (i = NVALMAX; i >= 3UL; i--)
+            {
+                x = (((x ^ (x >> 2UL) ^ (x >> 3UL) ^ (x >> 4UL)) & 1UL) << 7UL) | ((x >> 1UL) & 0x7FUL);
+                if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
+                {
+                    /* Decoded value of NDEC */
+                    n = i;
+                }
+                if (n != 0xFFFFFFFFUL)
+                {
+                    break;
+                }
+            }
+            break;
+    }
+    return n;
+}
+
+/* Find decoded P value for raw PDEC value */
+static uint32_t pllDecodeP(uint32_t PDEC)
+{
+    uint32_t p, x, i;
+    /* Find PDec */
+    switch (PDEC)
+    {
+        case 0x7F:
+            p = 0UL;
+            break;
+        case 0x62:
+            p = 1UL;
+            break;
+        case 0x42:
+            p = 2UL;
+            break;
+        default:
+            x = 0x10UL;
+            p = 0xFFFFFFFFUL;
+            for (i = PVALMAX; i >= 3UL; i--)
+            {
+                x = (((x ^ (x >> 2UL)) & 1UL) << 4UL) | ((x >> 1UL) & 0xFUL);
+                if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
+                {
+                    /* Decoded value of PDEC */
+                    p = i;
+                }
+                if (p != 0xFFFFFFFFUL)
+                {
+                    break;
+                }
+            }
+            break;
+    }
+    return p;
+}
+
+/* Find decoded M value for raw MDEC value */
+static uint32_t pllDecodeM(uint32_t MDEC)
+{
+    uint32_t m, i, x;
+
+    /* Find MDec */
+    switch (MDEC)
+    {
+        case 0x1FFFF:
+            m = 0UL;
+            break;
+        case 0x18003:
+            m = 1UL;
+            break;
+        case 0x10003:
+            m = 2UL;
+            break;
+        default:
+            x = 0x04000UL;
+            m = 0xFFFFFFFFUL;
+            for (i = MVALMAX; i >= 3UL; i--)
+            {
+                x = (((x ^ (x >> 1UL)) & 1UL) << 14UL) | ((x >> 1UL) & 0x3FFFUL);
+                if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
+                {
+                    /* Decoded value of MDEC */
+                    m = i;
+                }
+                if (m != 0xFFFFFFFFUL)
+                {
+                    break;
+                }
+            }
+            break;
+    }
+    return m;
+}
+
+/* Get predivider (N) from PLL NDEC setting */
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
+{
+    uint32_t preDiv = 1;
+
+    /* Direct input is not used? */
+    if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0UL)
+    {
+        /* Decode NDEC value to get (N) pre divider */
+        preDiv = pllDecodeN(nDecReg & 0x3FFUL);
+        if (preDiv == 0UL)
+        {
+            preDiv = 1;
+        }
+    }
+    /* Adjusted by 1, directi is used to bypass */
+    return preDiv;
+}
+
+/* Get postdivider (P) from PLL PDEC setting */
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
+{
+    uint32_t postDiv = 1;
+
+    /* Direct input is not used? */
+    if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0UL)
+    {
+        /* Decode PDEC value to get (P) post divider */
+        postDiv = 2UL * pllDecodeP(pDecReg & 0x7FUL);
+        if (postDiv == 0UL)
+        {
+            postDiv = 2;
+        }
+    }
+    /* Adjusted by 1, directo is used to bypass */
+    return postDiv;
+}
+
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
+{
+    uint32_t mMult = 1;
+
+    /* Decode MDEC value to get (M) multiplier */
+    mMult = pllDecodeM(mDecReg & 0x1FFFFUL);
+    if (mMult == 0UL)
+    {
+        mMult = 1;
+    }
+    return mMult;
+}
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit(void)
+{
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
+#endif                                                 /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+#if defined(__MCUXPRESSO)
+    extern void (*const g_pfnVectors[])(void);
+    SCB->VTOR = (uint32_t)&g_pfnVectors;
+#else
+    extern void *__Vectors;
+    SCB->VTOR = (uint32_t)&__Vectors;
+#endif
+    SYSCON->ARMTRACECLKDIV = 0;
+/* Optionally enable RAM banks that may be off by default at reset */
+#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
+    SYSCON->AHBCLKCTRLSET[0] =
+        SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
+
+#endif
+    SYSCON->MAINCLKSELA = 0U;
+    SYSCON->MAINCLKSELB = 0U;
+    SystemInitHook();
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate(void)
+{
+    uint32_t clkRate = 0;
+    uint32_t prediv, postdiv;
+    uint64_t workRate;
+
+    switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
+    {
+        case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
+            switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
+            {
+                case 0x00: /* FRO 12 MHz (fro_12m) */
+                    clkRate = CLK_FRO_12MHZ;
+                    break;
+                case 0x01: /* CLKIN Source (clk_in) */
+                    clkRate = CLK_CLK_IN;
+                    break;
+                case 0x02: /* Watchdog oscillator (wdt_clk) */
+                    clkRate = getWdtOscFreq();
+                    break;
+                default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
+                    if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) == SYSCON_FROCTRL_SEL_MASK)
+                    {
+                        clkRate = CLK_FRO_96MHZ;
+                    }
+                    else
+                    {
+                        clkRate = CLK_FRO_48MHZ;
+                    }
+                    break;
+            }
+            break;
+        case 0x02: /* System PLL clock (pll_clk)*/
+            switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
+            {
+                case 0x00: /* FRO 12 MHz (fro_12m) */
+                    clkRate = CLK_FRO_12MHZ;
+                    break;
+                case 0x01: /* CLKIN Source (clk_in) */
+                    clkRate = CLK_CLK_IN;
+                    break;
+                case 0x02: /* Watchdog oscillator (wdt_clk) */
+                    clkRate = getWdtOscFreq();
+                    break;
+                case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
+                    clkRate = CLK_RTC_32K_CLK;
+                    break;
+                default:
+                    clkRate = 0UL;
+                    break;
+            }
+            if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0UL)
+            {
+                /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
+                prediv  = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
+                postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
+                /* Adjust input clock */
+                clkRate = clkRate / prediv;
+
+                /* MDEC used for rate */
+                workRate = (uint64_t)(clkRate) * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
+                clkRate  = (uint32_t)(workRate / ((uint64_t)postdiv));
+                clkRate  = clkRate * 2UL; /* PLL CCO output is divided by 2 before to M-Divider */
+            }
+            break;
+        case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
+            clkRate = CLK_RTC_32K_CLK;
+            break;
+        default:
+            clkRate = 0UL;
+            break;
+    }
+    SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL);
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInitHook()
+   ---------------------------------------------------------------------------- */
+
+__attribute__((weak)) void SystemInitHook(void)
+{
+    /* Void implementation of the weak function. */
+}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/system_LPC54005.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/system_LPC54005.h
new file mode 100644
index 000000000..67a840cdb
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/system_LPC54005.h
@@ -0,0 +1,115 @@
+/*
+** ###################################################################
+**     Processors:          LPC54005JBD100
+**                          LPC54005JET100
+**
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
+**     Version:             rev. 1.2, 2017-06-08
+**     Build:               b201015
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2020 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**     - rev. 1.2 (2017-06-08)
+**         Remove RTC_CTRL_RTC_OSC_BYPASS.
+**         SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
+**         Remove RESET and HALT from SYSCON_AHBCLKDIV.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54005
+ * @version 1.2
+ * @date 2017-06-08
+ * @brief Device specific configuration file for LPC54005 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_LPC54005_H_
+#define _SYSTEM_LPC54005_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */
+#define CLK_RTC_32K_CLK      32768u    /* RTC oscillator 32 kHz output (32k_clk */
+#define CLK_FRO_12MHZ        12000000u /* FRO 12 MHz (fro_12m) */
+#define CLK_FRO_48MHZ        48000000u /* FRO 48 MHz (fro_48m) */
+#define CLK_FRO_96MHZ        96000000u /* FRO 96 MHz (fro_96m) */
+#define CLK_CLK_IN           0u        /* Default CLK_IN pin clock */
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate(void);
+
+/**
+ * @brief SystemInit function hook.
+ *
+ * This weak function allows to call specific initialization code during the
+ * SystemInit() execution.This can be used when an application specific code needs
+ * to be called as close to the reset entry as possible (for example the Multicore
+ * Manager MCMGR_EarlyInit() function call).
+ * NOTE: No global r/w variables can be used in this hook function because the
+ * initialization of these variables happens after this function.
+ */
+void SystemInitHook(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_LPC54005_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/template/RTE_Device.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/template/RTE_Device.h
new file mode 100644
index 000000000..acec606cc
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/template/RTE_Device.h
@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _RTE_DEVICE_H
+#define _RTE_DEVICE_H
+
+#include "pin_mux.h"
+
+/* UART Select, UART0-UART9. */
+/* User needs to provide the implementation of USARTX_GetFreq/USARTX_InitPins/USARTX_DeinitPins for the enabled USART
+ * instance. */
+#define RTE_USART0        0
+#define RTE_USART0_DMA_EN 0
+#define RTE_USART1        0
+#define RTE_USART1_DMA_EN 0
+#define RTE_USART2        0
+#define RTE_USART2_DMA_EN 0
+#define RTE_USART3        0
+#define RTE_USART3_DMA_EN 0
+#define RTE_USART4        0
+#define RTE_USART4_DMA_EN 0
+#define RTE_USART5        0
+#define RTE_USART5_DMA_EN 0
+#define RTE_USART6        0
+#define RTE_USART6_DMA_EN 0
+#define RTE_USART7        0
+#define RTE_USART7_DMA_EN 0
+#define RTE_USART8        0
+#define RTE_USART8_DMA_EN 0
+#define RTE_USART9        0
+#define RTE_USART9_DMA_EN 0
+
+/* USART configuration. */
+#define USART_RX_BUFFER_LEN     64
+#define USART0_RX_BUFFER_ENABLE 0
+#define USART1_RX_BUFFER_ENABLE 0
+#define USART2_RX_BUFFER_ENABLE 0
+#define USART3_RX_BUFFER_ENABLE 0
+#define USART4_RX_BUFFER_ENABLE 0
+#define USART5_RX_BUFFER_ENABLE 0
+#define USART6_RX_BUFFER_ENABLE 0
+#define USART7_RX_BUFFER_ENABLE 0
+#define USART8_RX_BUFFER_ENABLE 0
+#define USART9_RX_BUFFER_ENABLE 0
+
+#define RTE_USART0_PIN_INIT        USART0_InitPins
+#define RTE_USART0_PIN_DEINIT      USART0_DeinitPins
+#define RTE_USART0_DMA_TX_CH       1
+#define RTE_USART0_DMA_TX_DMA_BASE DMA0
+#define RTE_USART0_DMA_RX_CH       0
+#define RTE_USART0_DMA_RX_DMA_BASE DMA0
+
+#define RTE_USART1_PIN_INIT        USART1_InitPins
+#define RTE_USART1_PIN_DEINIT      USART1_DeinitPins
+#define RTE_USART1_DMA_TX_CH       3
+#define RTE_USART1_DMA_TX_DMA_BASE DMA0
+#define RTE_USART1_DMA_RX_CH       2
+#define RTE_USART1_DMA_RX_DMA_BASE DMA0
+
+#define RTE_USART2_PIN_INIT        USART2_InitPins
+#define RTE_USART2_PIN_DEINIT      USART2_DeinitPins
+#define RTE_USART2_DMA_TX_CH       5
+#define RTE_USART2_DMA_TX_DMA_BASE DMA0
+#define RTE_USART2_DMA_RX_CH       4
+#define RTE_USART2_DMA_RX_DMA_BASE DMA0
+
+#define RTE_USART3_PIN_INIT        USART3_InitPins
+#define RTE_USART3_PIN_DEINIT      USART3_DeinitPins
+#define RTE_USART3_DMA_TX_CH       7
+#define RTE_USART3_DMA_TX_DMA_BASE DMA0
+#define RTE_USART3_DMA_RX_CH       6
+#define RTE_USART3_DMA_RX_DMA_BASE DMA0
+
+#define RTE_USART4_PIN_INIT        USART4_InitPins
+#define RTE_USART4_PIN_DEINIT      USART4_DeinitPins
+#define RTE_USART4_DMA_TX_CH       9
+#define RTE_USART4_DMA_TX_DMA_BASE DMA0
+#define RTE_USART4_DMA_RX_CH       8
+#define RTE_USART4_DMA_RX_DMA_BASE DMA0
+
+#define RTE_USART5_PIN_INIT        USART5_InitPins
+#define RTE_USART5_PIN_DEINIT      USART5_DeinitPins
+#define RTE_USART5_DMA_TX_CH       11
+#define RTE_USART5_DMA_TX_DMA_BASE DMA0
+#define RTE_USART5_DMA_RX_CH       10
+#define RTE_USART5_DMA_RX_DMA_BASE DMA0
+
+#define RTE_USART6_PIN_INIT        USART6_InitPins
+#define RTE_USART6_PIN_DEINIT      USART6_DeinitPins
+#define RTE_USART6_DMA_TX_CH       13
+#define RTE_USART6_DMA_TX_DMA_BASE DMA0
+#define RTE_USART6_DMA_RX_CH       12
+#define RTE_USART6_DMA_RX_DMA_BASE DMA0
+
+#define RTE_USART7_PIN_INIT        USART7_InitPins
+#define RTE_USART7_PIN_DEINIT      USART7_DeinitPins
+#define RTE_USART7_DMA_TX_CH       15
+#define RTE_USART7_DMA_TX_DMA_BASE DMA0
+#define RTE_USART7_DMA_RX_CH       14
+#define RTE_USART7_DMA_RX_DMA_BASE DMA0
+
+#define RTE_USART8_PIN_INIT        USART8_InitPins
+#define RTE_USART8_PIN_DEINIT      USART8_DeinitPins
+#define RTE_USART8_DMA_TX_CH       17
+#define RTE_USART8_DMA_TX_DMA_BASE DMA0
+#define RTE_USART8_DMA_RX_CH       16
+#define RTE_USART8_DMA_RX_DMA_BASE DMA0
+
+#define RTE_USART9_PIN_INIT        USART9_InitPins
+#define RTE_USART9_PIN_DEINIT      USART9_DeinitPins
+#define RTE_USART9_DMA_TX_CH       19
+#define RTE_USART9_DMA_TX_DMA_BASE DMA0
+#define RTE_USART9_DMA_RX_CH       18
+#define RTE_USART9_DMA_RX_DMA_BASE DMA0
+
+/* I2C Select, I2C0 -I2C9*/
+/* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance.
+ */
+#define RTE_I2C0        0
+#define RTE_I2C0_DMA_EN 0
+#define RTE_I2C1        0
+#define RTE_I2C1_DMA_EN 0
+#define RTE_I2C2        0
+#define RTE_I2C2_DMA_EN 0
+#define RTE_I2C3        0
+#define RTE_I2C3_DMA_EN 0
+#define RTE_I2C4        0
+#define RTE_I2C4_DMA_EN 0
+#define RTE_I2C5        0
+#define RTE_I2C5_DMA_EN 0
+#define RTE_I2C6        0
+#define RTE_I2C6_DMA_EN 0
+#define RTE_I2C7        0
+#define RTE_I2C7_DMA_EN 0
+#define RTE_I2C8        0
+#define RTE_I2C8_DMA_EN 0
+#define RTE_I2C9        0
+#define RTE_I2C9_DMA_EN 0
+
+/*I2C configuration*/
+#define RTE_I2C0_Master_DMA_BASE DMA0
+#define RTE_I2C0_Master_DMA_CH   1
+
+#define RTE_I2C1_Master_DMA_BASE DMA0
+#define RTE_I2C1_Master_DMA_CH   3
+
+#define RTE_I2C2_Master_DMA_BASE DMA0
+#define RTE_I2C2_Master_DMA_CH   5
+
+#define RTE_I2C3_Master_DMA_BASE DMA0
+#define RTE_I2C3_Master_DMA_CH   7
+
+#define RTE_I2C4_Master_DMA_BASE DMA0
+#define RTE_I2C4_Master_DMA_CH   9
+
+#define RTE_I2C5_Master_DMA_BASE DMA0
+#define RTE_I2C5_Master_DMA_CH   11
+
+#define RTE_I2C6_Master_DMA_BASE DMA0
+#define RTE_I2C6_Master_DMA_CH   13
+
+#define RTE_I2C7_Master_DMA_BASE DMA0
+#define RTE_I2C7_Master_DMA_CH   15
+
+#define RTE_I2C8_Master_DMA_BASE DMA0
+#define RTE_I2C8_Master_DMA_CH   17
+
+#define RTE_I2C9_Master_DMA_BASE DMA0
+#define RTE_I2C9_Master_DMA_CH   19
+
+/* SPI select, SPI0 - SPI9.*/
+/* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance.
+ */
+#define RTE_SPI0        0
+#define RTE_SPI0_DMA_EN 0
+#define RTE_SPI1        0
+#define RTE_SPI1_DMA_EN 0
+#define RTE_SPI2        0
+#define RTE_SPI2_DMA_EN 0
+#define RTE_SPI3        0
+#define RTE_SPI3_DMA_EN 0
+#define RTE_SPI4        0
+#define RTE_SPI4_DMA_EN 0
+#define RTE_SPI5        0
+#define RTE_SPI5_DMA_EN 0
+#define RTE_SPI6        0
+#define RTE_SPI6_DMA_EN 0
+#define RTE_SPI7        0
+#define RTE_SPI7_DMA_EN 0
+#define RTE_SPI8        0
+#define RTE_SPI8_DMA_EN 0
+#define RTE_SPI9        0
+#define RTE_SPI9_DMA_EN 0
+
+/* SPI configuration. */
+#define RTE_SPI0_SSEL_NUM        kSPI_Ssel0
+#define RTE_SPI0_PIN_INIT        SPI0_InitPins
+#define RTE_SPI0_PIN_DEINIT      SPI0_DeinitPins
+#define RTE_SPI0_DMA_TX_CH       1
+#define RTE_SPI0_DMA_TX_DMA_BASE DMA0
+#define RTE_SPI0_DMA_RX_CH       0
+#define RTE_SPI0_DMA_RX_DMA_BASE DMA0
+
+#define RTE_SPI1_SSEL_NUM        kSPI_Ssel0
+#define RTE_SPI1_PIN_INIT        SPI1_InitPins
+#define RTE_SPI1_PIN_DEINIT      SPI1_DeinitPins
+#define RTE_SPI1_DMA_TX_CH       3
+#define RTE_SPI1_DMA_TX_DMA_BASE DMA0
+#define RTE_SPI1_DMA_RX_CH       2
+#define RTE_SPI1_DMA_RX_DMA_BASE DMA0
+
+#define RTE_SPI2_SSEL_NUM        kSPI_Ssel0
+#define RTE_SPI2_PIN_INIT        SPI2_InitPins
+#define RTE_SPI2_PIN_DEINIT      SPI2_DeinitPins
+#define RTE_SPI2_DMA_TX_CH       5
+#define RTE_SPI2_DMA_TX_DMA_BASE DMA0
+#define RTE_SPI2_DMA_RX_CH       4
+#define RTE_SPI2_DMA_RX_DMA_BASE DMA0
+
+#define RTE_SPI3_SSEL_NUM        kSPI_Ssel0
+#define RTE_SPI3_PIN_INIT        SPI3_InitPins
+#define RTE_SPI3_PIN_DEINIT      SPI3_DeinitPins
+#define RTE_SPI3_DMA_TX_CH       7
+#define RTE_SPI3_DMA_TX_DMA_BASE DMA0
+#define RTE_SPI3_DMA_RX_CH       6
+#define RTE_SPI3_DMA_RX_DMA_BASE DMA0
+
+#define RTE_SPI4_SSEL_NUM        kSPI_Ssel0
+#define RTE_SPI4_PIN_INIT        SPI4_InitPins
+#define RTE_SPI4_PIN_DEINIT      SPI4_DeinitPins
+#define RTE_SPI4_DMA_TX_CH       9
+#define RTE_SPI4_DMA_TX_DMA_BASE DMA0
+#define RTE_SPI4_DMA_RX_CH       8
+#define RTE_SPI4_DMA_RX_DMA_BASE DMA0
+
+#define RTE_SPI5_SSEL_NUM        kSPI_Ssel0
+#define RTE_SPI5_PIN_INIT        SPI5_InitPins
+#define RTE_SPI5_PIN_DEINIT      SPI5_DeinitPins
+#define RTE_SPI5_DMA_TX_CH       11
+#define RTE_SPI5_DMA_TX_DMA_BASE DMA0
+#define RTE_SPI5_DMA_RX_CH       10
+#define RTE_SPI5_DMA_RX_DMA_BASE DMA0
+
+#define RTE_SPI6_SSEL_NUM        kSPI_Ssel0
+#define RTE_SPI6_PIN_INIT        SPI6_InitPins
+#define RTE_SPI6_PIN_DEINIT      SPI6_DeinitPins
+#define RTE_SPI6_DMA_TX_CH       13
+#define RTE_SPI6_DMA_TX_DMA_BASE DMA0
+#define RTE_SPI6_DMA_RX_CH       12
+#define RTE_SPI6_DMA_RX_DMA_BASE DMA0
+
+#define RTE_SPI7_SSEL_NUM        kSPI_Ssel0
+#define RTE_SPI7_PIN_INIT        SPI7_InitPins
+#define RTE_SPI7_PIN_DEINIT      SPI7_DeinitPins
+#define RTE_SPI7_DMA_TX_CH       15
+#define RTE_SPI7_DMA_TX_DMA_BASE DMA0
+#define RTE_SPI7_DMA_RX_CH       14
+#define RTE_SPI7_DMA_RX_DMA_BASE DMA0
+
+#define RTE_SPI8_SSEL_NUM        kSPI_Ssel0
+#define RTE_SPI8_PIN_INIT        SPI8_InitPins
+#define RTE_SPI8_PIN_DEINIT      SPI8_DeinitPins
+#define RTE_SPI8_DMA_TX_CH       17
+#define RTE_SPI8_DMA_TX_DMA_BASE DMA0
+#define RTE_SPI8_DMA_RX_CH       16
+#define RTE_SPI8_DMA_RX_DMA_BASE DMA0
+
+#define RTE_SPI9_SSEL_NUM        kSPI_Ssel0
+#define RTE_SPI9_PIN_INIT        SPI9_InitPins
+#define RTE_SPI9_PIN_DEINIT      SPI9_DeinitPins
+#define RTE_SPI9_DMA_TX_CH       23
+#define RTE_SPI9_DMA_TX_DMA_BASE DMA0
+#define RTE_SPI9_DMA_RX_CH       22
+#define RTE_SPI9_DMA_RX_DMA_BASE DMA0
+
+#endif /* _RTE_DEVICE_H */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/utilities/fsl_notifier.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/utilities/fsl_notifier.c
new file mode 100644
index 000000000..7b7c02dc3
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/utilities/fsl_notifier.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_notifier.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief Creates a Notifier handle.
+ *
+ * param notifierHandle A pointer to the notifier handle.
+ * param configs A pointer to an array with references to all configurations which is handled by the Notifier.
+ * param configsNumber Number of configurations. Size of the configuration array.
+ * param callbacks A pointer to an array of callback configurations.
+ *  If there are no callbacks to register during Notifier initialization, use NULL value.
+ * param callbacksNumber Number of registered callbacks. Size of the callbacks array.
+ * param userFunction User function.
+ * param userData User data passed to user function.
+ * return An error Code or kStatus_Success.
+ */
+status_t NOTIFIER_CreateHandle(notifier_handle_t *notifierHandle,
+                               notifier_user_config_t **configs,
+                               uint8_t configsNumber,
+                               notifier_callback_config_t *callbacks,
+                               uint8_t callbacksNumber,
+                               notifier_user_function_t userFunction,
+                               void *userData)
+{
+    /* Check input parameter - at least one configuration is required and userFunction must exist */
+    if ((configs == NULL) || (configsNumber == 0U) || (userFunction == NULL))
+    {
+        return kStatus_Fail;
+    }
+    /* Initialize handle structure */
+    (void)memset(notifierHandle, 0, sizeof(notifier_handle_t));
+    /* Store references to user-defined configurations */
+    notifierHandle->configsTable  = configs;
+    notifierHandle->configsNumber = configsNumber;
+    /* Store references to user-defined callback configurations */
+    if (callbacks != NULL)
+    {
+        notifierHandle->callbacksTable  = callbacks;
+        notifierHandle->callbacksNumber = callbacksNumber;
+        /* If all callbacks return success, then the errorCallbackIndex is callbacksNumber */
+        notifierHandle->errorCallbackIndex = callbacksNumber;
+    }
+    notifierHandle->userFunction = userFunction;
+    notifierHandle->userData     = userData;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Switches the configuration according to a pre-defined structure.
+ *
+ * This function sets the system to the target configuration. Before transition,
+ * the Notifier sends notifications to all callbacks registered to the callback table.
+ * Callbacks are invoked in the following order: All registered callbacks are notified
+ * ordered by index in the callbacks array. The same order is used for before and after switch notifications.
+ * The notifications before the configuration switch can be used to obtain confirmation about
+ * the change from registered callbacks. If any registered callback denies the
+ * configuration change, further execution of this function depends on the notifier policy: the
+ * configuration change is either forced (kNOTIFIER_PolicyForcible) or exited (kNOTIFIER_PolicyAgreement).
+ * When configuration change is forced, the result of the before switch notifications are ignored. If an
+ * agreement is required, if any callback returns an error code, further notifications
+ * before switch notifications are cancelled and all already notified callbacks are re-invoked.
+ * The index of the callback which returned error code during pre-switch notifications is stored
+ * (any error codes during callbacks re-invocation are ignored) and NOTIFIER_GetErrorCallback() can be used to get it.
+ * Regardless of the policies, if any callback returns an error code, an error code indicating in which phase
+ * the error occurred is returned when NOTIFIER_SwitchConfig() exits.
+ * param notifierHandle pointer to notifier handle
+ * param configIndex Index of the target configuration.
+ * param policy            Transaction policy, kNOTIFIER_PolicyAgreement or kNOTIFIER_PolicyForcible.
+ *
+ * return An error code or kStatus_Success.
+ *
+ */
+status_t NOTIFIER_SwitchConfig(notifier_handle_t *notifierHandle, uint8_t configIndex, notifier_policy_t policy)
+{
+    uint8_t currentStaticCallback = 0U;              /* Index to array of statically registered call-backs */
+    status_t returnCode           = kStatus_Success; /* Function return */
+
+    notifier_notification_block_t notifyBlock;  /*  Callback notification block */
+    notifier_callback_config_t *callbackConfig; /* Pointer to callback configuration */
+
+    /* Set errorcallbackindex as callbacksNumber, which means no callback error now */
+    notifierHandle->errorCallbackIndex = notifierHandle->callbacksNumber;
+
+    /* Requested configuration availability check */
+    if (configIndex >= notifierHandle->configsNumber)
+    {
+        return kStatus_OutOfRange;
+    }
+
+    /* Initialization of local variables from the Notifier handle structure */
+
+    notifyBlock.policy       = policy;
+    notifyBlock.targetConfig = notifierHandle->configsTable[configIndex];
+    notifyBlock.notifyType   = kNOTIFIER_NotifyBefore;
+
+    /* From all statically registered call-backs... */
+    for (currentStaticCallback = 0U; currentStaticCallback < notifierHandle->callbacksNumber; currentStaticCallback++)
+    {
+        callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]);
+        /* ...notify only those which asked to be called before the configuration switch */
+        if (((uint32_t)callbackConfig->callbackType & (uint32_t)kNOTIFIER_CallbackBefore) != 0U)
+        {
+            /* In case that call-back returned error code mark it, store the call-back handle and eventually cancel
+             * the configuration switch */
+            if (callbackConfig->callback(&notifyBlock, callbackConfig->callbackData) != kStatus_Success)
+            {
+                returnCode                         = (status_t)kStatus_NOTIFIER_ErrorNotificationBefore;
+                notifierHandle->errorCallbackIndex = currentStaticCallback;
+                /* If not forcing configuration switch, call all already notified call-backs to revert their state
+                 * as the switch is canceled */
+                if (policy != kNOTIFIER_PolicyForcible)
+                {
+                    break;
+                }
+            }
+        }
+    }
+
+    /* Set configuration */
+
+    /* In case that any call-back returned error code and  policy doesn't force the configuration set, go to after
+     * switch call-backs */
+    if ((policy == kNOTIFIER_PolicyForcible) || (returnCode == kStatus_Success))
+    {
+        returnCode = notifierHandle->userFunction(notifierHandle->configsTable[configIndex], notifierHandle->userData);
+        if (returnCode != kStatus_Success)
+        {
+            return returnCode;
+        }
+        /* Update current configuration index */
+        notifierHandle->currentConfigIndex = configIndex;
+        notifyBlock.notifyType             = kNOTIFIER_NotifyAfter;
+        /* From all statically registered call-backs... */
+        for (currentStaticCallback = 0U; currentStaticCallback < notifierHandle->callbacksNumber;
+             currentStaticCallback++)
+        {
+            callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]);
+            /* ...notify only those which asked to be called after the configuration switch */
+            if (((uint32_t)callbackConfig->callbackType & (uint32_t)kNOTIFIER_CallbackAfter) != 0U)
+            {
+                /* In case that call-back returned error code mark it and store the call-back handle */
+                if (callbackConfig->callback(&notifyBlock, callbackConfig->callbackData) != kStatus_Success)
+                {
+                    returnCode                         = (status_t)kStatus_NOTIFIER_ErrorNotificationAfter;
+                    notifierHandle->errorCallbackIndex = currentStaticCallback;
+                    if (policy != kNOTIFIER_PolicyForcible)
+                    {
+                        break;
+                    }
+                }
+            }
+        }
+    }
+    else
+    {
+        /* End of unsuccessful switch */
+        notifyBlock.notifyType = kNOTIFIER_NotifyRecover;
+        while (currentStaticCallback-- > 0U)
+        {
+            callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]);
+            if (((uint32_t)callbackConfig->callbackType & (uint32_t)kNOTIFIER_CallbackBefore) != 0U)
+            {
+                (void)callbackConfig->callback(&notifyBlock, callbackConfig->callbackData);
+            }
+        }
+    }
+
+    return returnCode;
+}
+
+/*!
+ * brief This function returns the last failed notification callback.
+ *
+ * This function returns an index of the last callback that failed during the configuration switch while
+ * the last NOTIFIER_SwitchConfig() was called. If the last NOTIFIER_SwitchConfig() call ended successfully
+ * value equal to callbacks number is returned. The returned value represents an index in the array of
+ * static call-backs.
+ *
+ * param notifierHandle Pointer to the notifier handle
+ * return Callback Index of the last failed callback or value equal to callbacks count.
+ */
+uint8_t NOTIFIER_GetErrorCallbackIndex(notifier_handle_t *notifierHandle)
+{
+    return notifierHandle->errorCallbackIndex;
+}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/utilities/fsl_notifier.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/utilities/fsl_notifier.h
new file mode 100644
index 000000000..d93578c13
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/utilities/fsl_notifier.h
@@ -0,0 +1,237 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_NOTIFIER_H_
+#define _FSL_NOTIFIER_H_
+
+#include "fsl_common.h"
+/*!
+ * @addtogroup notifier
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Notifier error codes.
+ *
+ * Used as return value of Notifier functions.
+ */
+enum _notifier_status
+{
+    kStatus_NOTIFIER_ErrorNotificationBefore =
+        MAKE_STATUS(kStatusGroup_NOTIFIER, 0), /*!< An error occurs during send "BEFORE" notification. */
+    kStatus_NOTIFIER_ErrorNotificationAfter =
+        MAKE_STATUS(kStatusGroup_NOTIFIER, 1), /*!< An error occurs during send "AFTER" notification. */
+};
+
+/*!
+ * @brief Notifier policies.
+ *
+ * Defines whether the user function execution is forced or not.
+ * For kNOTIFIER_PolicyForcible, the user function is executed regardless of the callback results,
+ * while kNOTIFIER_PolicyAgreement policy is used to exit NOTIFIER_SwitchConfig()
+ * when any of the callbacks returns error code.
+ * See also NOTIFIER_SwitchConfig() description.
+ */
+typedef enum _notifier_policy
+{
+    kNOTIFIER_PolicyAgreement, /*!< NOTIFIER_SwitchConfig() method is exited when any of the callbacks returns error
+                                      code. */
+    kNOTIFIER_PolicyForcible,  /*!< The user function is executed regardless of the results. */
+} notifier_policy_t;
+
+/*! @brief Notification type. Used to notify registered callbacks */
+typedef enum _notifier_notification_type
+{
+    kNOTIFIER_NotifyRecover = 0x00U, /*!< Notify IP to recover to previous work state. */
+    kNOTIFIER_NotifyBefore  = 0x01U, /*!< Notify IP that configuration setting is going to change. */
+    kNOTIFIER_NotifyAfter   = 0x02U, /*!< Notify IP that configuration setting has been changed. */
+} notifier_notification_type_t;
+
+/*!
+ * @brief The callback type, which indicates kinds of notification the callback handles.
+ *
+ * Used in the callback configuration structure (notifier_callback_config_t)
+ * to specify when the registered callback is called during configuration switch initiated by the
+ * NOTIFIER_SwitchConfig().
+ * Callback can be invoked in following situations.
+ *  - Before the configuration switch (Callback return value can affect NOTIFIER_SwitchConfig()
+ *    execution. See the NOTIFIER_SwitchConfig() and notifier_policy_t documentation).
+ *  - After an unsuccessful attempt to switch configuration
+ *  - After a successful configuration switch
+ */
+typedef enum _notifier_callback_type
+{
+    kNOTIFIER_CallbackBefore      = 0x01U, /*!< Callback handles BEFORE notification. */
+    kNOTIFIER_CallbackAfter       = 0x02U, /*!< Callback handles AFTER notification. */
+    kNOTIFIER_CallbackBeforeAfter = 0x03U, /*!< Callback handles BEFORE and AFTER notification. */
+} notifier_callback_type_t;
+
+/*! @brief Notifier user configuration type.
+ *
+ * Reference of the user defined configuration is stored in an array; the notifier switches between these configurations
+ * based on this array.
+ */
+typedef void notifier_user_config_t;
+
+/*! @brief Notifier user function prototype
+ * Use this function to execute specific operations in configuration switch.
+ * Before and after this function execution, different notification is sent to registered callbacks.
+ * If this function returns any error code, NOTIFIER_SwitchConfig() exits.
+ *
+ * @param targetConfig target Configuration.
+ * @param userData Refers to other specific data passed to user function.
+ * @return An error code or kStatus_Success.
+ */
+typedef status_t (*notifier_user_function_t)(notifier_user_config_t *targetConfig, void *userData);
+
+/*! @brief notification block passed to the registered callback function. */
+typedef struct _notifier_notification_block
+{
+    notifier_user_config_t *targetConfig;    /*!< Pointer to target configuration. */
+    notifier_policy_t policy;                /*!< Configure transition policy. */
+    notifier_notification_type_t notifyType; /*!< Configure notification type. */
+} notifier_notification_block_t;
+
+/*!
+ * @brief Callback prototype.
+ *
+ * Declaration of a callback. It is common for registered callbacks.
+ * Reference to function of this type is part of the notifier_callback_config_t callback configuration structure.
+ * Depending on callback type, function of this prototype is called (see NOTIFIER_SwitchConfig())
+ * before configuration switch, after it or in both use cases to notify about
+ * the switch progress (see notifier_callback_type_t). When called, the type of the notification
+ * is passed as a parameter along with the reference to the target configuration structure (see
+ * notifier_notification_block_t) and any data passed during the callback registration. When notified before the
+ * configuration switch, depending on the configuration switch policy (see notifier_policy_t), the callback may deny the
+ * execution of the user function by returning an error code different than kStatus_Success (see
+ * NOTIFIER_SwitchConfig()).
+ *
+ * @param notify Notification block.
+ * @param data Callback data. Refers to the data passed during callback registration. Intended to
+ *  pass any driver or application data such as internal state information.
+ * @return An error code or kStatus_Success.
+ */
+typedef status_t (*notifier_callback_t)(notifier_notification_block_t *notify, void *data);
+
+/*!
+ * @brief Callback configuration structure.
+ *
+ * This structure holds the configuration of callbacks.
+ * Callbacks of this type are expected to be statically allocated.
+ * This structure contains the following application-defined data.
+ *  callback - pointer to the callback function
+ *  callbackType - specifies when the callback is called
+ *  callbackData - pointer to the data passed to the callback.
+ */
+typedef struct _notifier_callback_config
+{
+    notifier_callback_t callback;          /*!< Pointer to the callback function. */
+    notifier_callback_type_t callbackType; /*!< Callback type. */
+    void *callbackData;                    /*!< Pointer to the data passed to the callback. */
+} notifier_callback_config_t;
+
+/*!
+ * @brief Notifier handle structure.
+ *
+ * Notifier handle structure. Contains data necessary for the Notifier proper function.
+ * Stores references to registered configurations, callbacks, information about their numbers,
+ * user function, user data, and other internal data.
+ * NOTIFIER_CreateHandle() must be called to initialize this handle.
+ */
+typedef struct _notifier_handle
+{
+    notifier_user_config_t **configsTable;      /*!< Pointer to configure table. */
+    uint8_t configsNumber;                      /*!< Number of configurations. */
+    notifier_callback_config_t *callbacksTable; /*!< Pointer to callback table. */
+    uint8_t callbacksNumber;                    /*!< Maximum number of callback configurations. */
+    uint8_t errorCallbackIndex;                 /*!< Index of callback returns error. */
+    uint8_t currentConfigIndex;                 /*!< Index of current configuration.  */
+    notifier_user_function_t userFunction;      /*!< User function. */
+    void *userData;                             /*!< User data passed to user function. */
+} notifier_handle_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Creates a Notifier handle.
+ *
+ * @param notifierHandle A pointer to the notifier handle.
+ * @param configs A pointer to an array with references to all configurations which is handled by the Notifier.
+ * @param configsNumber Number of configurations. Size of the configuration array.
+ * @param callbacks A pointer to an array of callback configurations.
+ *  If there are no callbacks to register during Notifier initialization, use NULL value.
+ * @param callbacksNumber Number of registered callbacks. Size of the callbacks array.
+ * @param userFunction User function.
+ * @param userData User data passed to user function.
+ * @return An error Code or kStatus_Success.
+ */
+status_t NOTIFIER_CreateHandle(notifier_handle_t *notifierHandle,
+                               notifier_user_config_t **configs,
+                               uint8_t configsNumber,
+                               notifier_callback_config_t *callbacks,
+                               uint8_t callbacksNumber,
+                               notifier_user_function_t userFunction,
+                               void *userData);
+
+/*!
+ * @brief Switches the configuration according to a pre-defined structure.
+ *
+ * This function sets the system to the target configuration. Before transition,
+ * the Notifier sends notifications to all callbacks registered to the callback table.
+ * Callbacks are invoked in the following order: All registered callbacks are notified
+ * ordered by index in the callbacks array. The same order is used for before and after switch notifications.
+ * The notifications before the configuration switch can be used to obtain confirmation about
+ * the change from registered callbacks. If any registered callback denies the
+ * configuration change, further execution of this function depends on the notifier policy: the
+ * configuration change is either forced (kNOTIFIER_PolicyForcible) or exited (kNOTIFIER_PolicyAgreement).
+ * When configuration change is forced, the result of the before switch notifications are ignored. If an
+ * agreement is required, if any callback returns an error code, further notifications
+ * before switch notifications are cancelled and all already notified callbacks are re-invoked.
+ * The index of the callback which returned error code during pre-switch notifications is stored
+ * (any error codes during callbacks re-invocation are ignored) and NOTIFIER_GetErrorCallback() can be used to get it.
+ * Regardless of the policies, if any callback returns an error code, an error code indicating in which phase
+ * the error occurred is returned when NOTIFIER_SwitchConfig() exits.
+ * @param notifierHandle pointer to notifier handle
+ * @param configIndex Index of the target configuration.
+ * @param policy            Transaction policy, kNOTIFIER_PolicyAgreement or kNOTIFIER_PolicyForcible.
+ *
+ * @return An error code or kStatus_Success.
+ *
+ */
+status_t NOTIFIER_SwitchConfig(notifier_handle_t *notifierHandle, uint8_t configIndex, notifier_policy_t policy);
+
+/*!
+ * @brief This function returns the last failed notification callback.
+ *
+ * This function returns an index of the last callback that failed during the configuration switch while
+ * the last NOTIFIER_SwitchConfig() was called. If the last NOTIFIER_SwitchConfig() call ended successfully
+ * value equal to callbacks number is returned. The returned value represents an index in the array of
+ * static call-backs.
+ *
+ * @param notifierHandle Pointer to the notifier handle
+ * @return Callback Index of the last failed callback or value equal to callbacks count.
+ */
+uint8_t NOTIFIER_GetErrorCallbackIndex(notifier_handle_t *notifierHandle);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_NOTIFIER_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/utilities/fsl_shell.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/utilities/fsl_shell.c
new file mode 100644
index 000000000..2cc75f02e
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/utilities/fsl_shell.c
@@ -0,0 +1,1085 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * POSIX getopt for Windows
+ * Code given out at the 1985 UNIFORUM conference in Dallas.
+ *
+ * From [email protected] (Moderator, John Quarterman) Sun Nov  3 14:34:15 1985
+ * Relay-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site gatech.CSNET
+ * Posting-Version: version B 2.10.2 9/18/84; site ut-sally.UUCP
+ * Path: gatech!akgua!mhuxv!mhuxt!mhuxr!ulysses!allegra!mit-eddie!genrad!panda!talcott!harvard!seismo!ut-sally!std-unix
+ * From: [email protected] (Moderator, John Quarterman)
+ * Newsgroups: mod.std.unix
+ * Subject: public domain AT&T getopt source
+ * Message-ID: <[email protected]>
+ * Date: 3 Nov 85 19:34:15 GMT
+ * Date-Received: 4 Nov 85 12:25:09 GMT
+ * Organization: IEEE/P1003 Portable Operating System Environment Committee
+ * Lines: 91
+ * Approved: [email protected]
+ * Here's something you've all been waiting for:  the AT&T public domain
+ * source for getopt(3).  It is the code which was given out at the 1985
+ * UNIFORUM conference in Dallas.  I obtained it by electronic mail
+ * directly from AT&T.  The people there assure me that it is indeed
+ * in the public domain
+ * There is no manual page.  That is because the one they gave out at
+ * UNIFORUM was slightly different from the current System V Release 2
+ * manual page.  The difference apparently involved a note about the
+ * famous rules 5 and 6, recommending using white space between an option
+ * and its first argument, and not grouping options that have arguments.
+ * Getopt itself is currently lenient about both of these things White
+ * space is allowed, but not mandatory, and the last option in a group can
+ * have an argument.  That particular version of the man page evidently
+ * has no official existence, and my source at AT&T did not send a copy.
+ * The current SVR2 man page reflects the actual behavor of this getopt.
+ * However, I am not about to post a copy of anything licensed by AT&T.
+ */
+
+#include <assert.h>
+#include <stdarg.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+#include "fsl_common.h"
+#include "fsl_str.h"
+
+#include "fsl_component_generic_list.h"
+#include "fsl_component_serial_manager.h"
+
+#include "fsl_shell.h"
+
+/*
+ * The OSA_USED macro can only be defined when the OSA component is used.
+ * If the source code of the OSA component does not exist, the OSA_USED cannot be defined.
+ * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED
+ * also cannot be defined.
+ * The source code path of the OSA component is <MCUXpresso_SDK>/components/osa.
+ *
+ */
+#if defined(OSA_USED)
+
+#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U))
+#include "fsl_component_common_task.h"
+#else
+#include "fsl_os_abstraction.h"
+#endif
+
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define KEY_ESC (0x1BU)
+#define KET_DEL (0x7FU)
+
+#define SHELL_EVENT_DATA_ARRIVED (1U << 0)
+#define SHELL_EVENT_DATA_SENT    (1U << 1)
+
+#define SHELL_SPRINTF_BUFFER_SIZE (64U)
+
+/*! @brief A type for the handle special key. */
+typedef enum _fun_key_status
+{
+    kSHELL_Normal   = 0U, /*!< Normal key */
+    kSHELL_Special  = 1U, /*!< Special key */
+    kSHELL_Function = 2U, /*!< Function key */
+} fun_key_status_t;
+
+/*! @brief Data structure for Shell environment. */
+typedef struct _shell_context_handle
+{
+    list_label_t commandContextListHead; /*!< Command shellContextHandle list queue head */
+    serial_handle_t serialHandle;        /*!< Serial manager handle */
+    uint8_t
+        serialWriteHandleBuffer[SERIAL_MANAGER_WRITE_HANDLE_SIZE];   /*!< The buffer for serial manager write handle */
+    serial_write_handle_t serialWriteHandle;                         /*!< The serial manager write handle */
+    uint8_t serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE]; /*!< The buffer for serial manager read handle */
+    serial_read_handle_t serialReadHandle;                           /*!< The serial manager read handle */
+    char *prompt;                                                    /*!< Prompt string */
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U))
+    common_task_message_t commontaskMsg; /*!< Message for common task */
+#else
+    uint8_t event[OSA_EVENT_HANDLE_SIZE]; /*!< Event instance */
+    uint8_t taskId[OSA_TASK_HANDLE_SIZE]; /*!< Task handle */
+#endif
+
+#endif
+
+#endif
+    char line[SHELL_BUFFER_SIZE];                          /*!< Consult buffer */
+    char hist_buf[SHELL_HISTORY_COUNT][SHELL_BUFFER_SIZE]; /*!< History buffer*/
+    char printBuffer[SHELL_SPRINTF_BUFFER_SIZE];           /*!< Buffer for print */
+    uint32_t printLength;                                  /*!< All length has been printed */
+    uint16_t hist_current;                                 /*!< Current history command in hist buff*/
+    uint16_t hist_count;                                   /*!< Total history command in hist buff*/
+    enum _fun_key_status stat;                             /*!< Special key status */
+    uint8_t cmd_num;                                       /*!< Number of user commands */
+    uint8_t l_pos;                                         /*!< Total line position */
+    uint8_t c_pos;                                         /*!< Current line position */
+    volatile uint8_t notificationPost;                     /*!< The serial manager notification is post */
+    uint8_t exit;                                          /*!< Exit Flag*/
+    uint8_t printBusy;                                     /*!< Print is busy */
+} shell_context_handle_t;
+
+#if 0
+#define SHELL_STRUCT_OFFSET(type, field) ((size_t) & (((type *)0)->field))
+#define SHEEL_COMMAND_POINTER(node) \
+    ((shell_command_t *)(((uint32_t)(node)) - SHELL_STRUCT_OFFSET(shell_command_t, link)))
+#else
+#define SHEEL_COMMAND_POINTER(node) \
+    ((shell_command_t *)(((uint32_t)(node)) - (sizeof(shell_command_t) - sizeof(list_element_t))))
+#endif
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static shell_status_t SHELL_HelpCommand(shell_handle_t shellHandle, int32_t argc, char **argv); /*!< help command */
+
+static shell_status_t SHELL_ExitCommand(shell_handle_t shellHandle, int32_t argc, char **argv); /*!< exit command */
+
+static int32_t SHELL_ParseLine(const char *cmd, uint32_t len, char *argv[]); /*!< parse line command */
+
+static int32_t SHELL_StringCompare(const char *str1, const char *str2, int32_t count); /*!< compare string command */
+
+static void SHELL_ProcessCommand(shell_context_handle_t *shellContextHandle, const char *cmd); /*!< process a command */
+
+static void SHELL_GetHistoryCommand(shell_context_handle_t *shellContextHandle,
+                                    uint8_t hist_pos); /*!< get commands history */
+
+static void SHELL_AutoComplete(shell_context_handle_t *shellContextHandle); /*!< auto complete command */
+
+static shell_status_t SHELL_GetChar(shell_context_handle_t *shellContextHandle,
+                                    uint8_t *ch); /*!< get a char from communication interface */
+
+static void SHELL_WriteWithCopy(shell_handle_t shellHandle, const char *buffer, uint32_t length);
+
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+static void SHELL_Task(void *param); /*!<  Shell task*/
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+static SHELL_COMMAND_DEFINE(help, "\r\n\"help\": List all the registered commands\r\n", SHELL_HelpCommand, 0);
+static SHELL_COMMAND_DEFINE(exit, "\r\n\"exit\": Exit program\r\n", SHELL_ExitCommand, 0);
+
+static char s_paramBuffer[SHELL_BUFFER_SIZE];
+
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+#if defined(OSA_USED)
+#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U))
+#else
+/*
+ * \brief Defines the serial manager task's stack
+ */
+static OSA_TASK_DEFINE(SHELL_Task, SHELL_TASK_PRIORITY, 1, SHELL_TASK_STACK_SIZE, false);
+#endif
+#endif /* OSA_USED */
+#endif /* SHELL_NON_BLOCKING_MODE */
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+static void SHELL_SerialManagerRxCallback(void *callbackParam,
+                                          serial_manager_callback_message_t *message,
+                                          serial_manager_status_t status)
+{
+    shell_context_handle_t *shellHandle;
+
+    assert(callbackParam);
+    assert(message);
+
+    shellHandle = (shell_context_handle_t *)callbackParam;
+
+    if (0U == shellHandle->notificationPost)
+    {
+        shellHandle->notificationPost = 1U;
+#if defined(OSA_USED)
+
+#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U))
+        shellHandle->commontaskMsg.callback      = SHELL_Task;
+        shellHandle->commontaskMsg.callbackParam = shellHandle;
+        (void)COMMON_TASK_post_message(&shellHandle->commontaskMsg);
+#else
+        (void)OSA_EventSet((osa_event_handle_t)shellHandle->event, SHELL_EVENT_DATA_ARRIVED);
+#endif
+
+#else
+        SHELL_Task(shellHandle);
+#endif
+    }
+}
+#endif
+
+static void SHELL_WriteBuffer(char *buffer, int32_t *indicator, char val, int len)
+{
+    shell_context_handle_t *shellContextHandle;
+    int i              = 0;
+    shellContextHandle = (shell_context_handle_t *)(void *)buffer;
+
+    for (i = 0; i < len; i++)
+    {
+        if ((*indicator + 1) >= (int32_t)SHELL_SPRINTF_BUFFER_SIZE)
+        {
+#if (!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1)))
+            if (NULL == shellContextHandle->serialHandle)
+            {
+                for (uint32_t index = 0; index < ((uint32_t)*indicator); index++)
+                {
+                    (void)putchar(shellContextHandle->printBuffer[index]);
+                }
+            }
+            else
+#endif
+            {
+                (void)SerialManager_WriteBlocking(shellContextHandle->serialWriteHandle,
+                                                  (uint8_t *)shellContextHandle->printBuffer, (uint32_t)*indicator);
+            }
+
+            shellContextHandle->printLength += (uint32_t)*indicator;
+            *indicator = 0;
+        }
+
+        shellContextHandle->printBuffer[*indicator] = val;
+        (*indicator)++;
+    }
+}
+
+static int SHELL_Sprintf(void *buffer, const char *formatString, va_list ap)
+{
+    shell_context_handle_t *shellContextHandle;
+    uint32_t length;
+    shellContextHandle = (shell_context_handle_t *)buffer;
+
+    length = (uint32_t)StrFormatPrintf(formatString, ap, (char *)buffer, SHELL_WriteBuffer);
+    shellContextHandle->printLength += length;
+    return (int32_t)length;
+}
+
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+static void SHELL_Task(void *param)
+#else
+void SHELL_Task(shell_handle_t shellHandle)
+#endif
+{
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+    shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)param;
+#else
+    shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)shellHandle;
+#endif
+    uint8_t ch;
+
+    if (NULL != shellContextHandle)
+    {
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U))
+#else
+        osa_event_flags_t ev = 0;
+
+        do
+        {
+            if (KOSA_StatusSuccess == OSA_EventWait((osa_event_handle_t)shellContextHandle->event, osaEventFlagsAll_c,
+                                                    0U, osaWaitForever_c, &ev))
+            {
+                if (0U != (ev & SHELL_EVENT_DATA_ARRIVED))
+#endif
+
+#endif
+
+#endif
+        {
+            shellContextHandle->notificationPost = 0;
+            do
+            {
+                if ((bool)shellContextHandle->exit)
+                {
+                    if (shellContextHandle->serialReadHandle != NULL)
+                    {
+                        (void)SerialManager_CloseReadHandle(shellContextHandle->serialReadHandle);
+                        shellContextHandle->serialReadHandle = NULL;
+                    }
+                    if (shellContextHandle->serialWriteHandle != NULL)
+                    {
+                        (void)SerialManager_CloseWriteHandle(shellContextHandle->serialWriteHandle);
+                        shellContextHandle->serialWriteHandle = NULL;
+                    }
+                    break;
+                }
+                if (kStatus_SHELL_Success != (shell_status_t)SHELL_GetChar(shellContextHandle, &ch))
+                {
+                    /* If error occurred when getting a char, exit the task and waiting the new data arriving. */
+                    break;
+                }
+
+                /* Special key */
+                if (ch == KEY_ESC)
+                {
+                    shellContextHandle->stat = kSHELL_Special;
+                    continue;
+                }
+                else if (shellContextHandle->stat == kSHELL_Special)
+                {
+                    /* Function key */
+                    if ((char)ch == '[')
+                    {
+                        shellContextHandle->stat = kSHELL_Function;
+                        continue;
+                    }
+                    shellContextHandle->stat = kSHELL_Normal;
+                }
+                else if (shellContextHandle->stat == kSHELL_Function)
+                {
+                    shellContextHandle->stat = kSHELL_Normal;
+
+                    switch ((char)ch)
+                    {
+                        /* History operation here */
+                        case 'A': /* Up key */
+                            SHELL_GetHistoryCommand(shellContextHandle, (uint8_t)shellContextHandle->hist_current);
+                            if (shellContextHandle->hist_current < (shellContextHandle->hist_count - 1U))
+                            {
+                                shellContextHandle->hist_current++;
+                            }
+                            break;
+                        case 'B': /* Down key */
+                            SHELL_GetHistoryCommand(shellContextHandle, (uint8_t)shellContextHandle->hist_current);
+                            if (shellContextHandle->hist_current > 0U)
+                            {
+                                shellContextHandle->hist_current--;
+                            }
+                            break;
+                        case 'D': /* Left key */
+                            if ((bool)shellContextHandle->c_pos)
+                            {
+                                SHELL_WriteWithCopy(shellContextHandle, "\b", 1);
+                                shellContextHandle->c_pos--;
+                            }
+                            break;
+                        case 'C': /* Right key */
+                            if (shellContextHandle->c_pos < shellContextHandle->l_pos)
+                            {
+                                (void)SHELL_Write(shellContextHandle,
+                                                  &shellContextHandle->line[shellContextHandle->c_pos], 1);
+                                shellContextHandle->c_pos++;
+                            }
+                            break;
+                        default:
+                            /* MISRA C-2012 Rule 16.4 */
+                            break;
+                    }
+                    continue;
+                }
+                /* Handle tab key */
+                else if ((char)ch == '\t')
+                {
+#if SHELL_AUTO_COMPLETE
+                    /* Move the cursor to the beginning of line */
+                    uint32_t i;
+                    for (i = 0; i < (uint32_t)shellContextHandle->c_pos; i++)
+                    {
+                        SHELL_WriteWithCopy(shellContextHandle, "\b", 1);
+                    }
+                    /* Do auto complete */
+                    SHELL_AutoComplete(shellContextHandle);
+                    /* Move position to end */
+                    shellContextHandle->l_pos = (uint8_t)strlen(shellContextHandle->line);
+                    shellContextHandle->c_pos = shellContextHandle->l_pos;
+#endif
+                    continue;
+                }
+                /* Handle backspace key */
+                else if ((ch == KET_DEL) || ((char)ch == '\b'))
+                {
+                    /* There must be at last one char */
+                    if (shellContextHandle->c_pos == 0U)
+                    {
+                        continue;
+                    }
+
+                    shellContextHandle->l_pos--;
+                    shellContextHandle->c_pos--;
+
+                    if (shellContextHandle->l_pos > shellContextHandle->c_pos)
+                    {
+                        (void)memmove(&shellContextHandle->line[shellContextHandle->c_pos],
+                                      &shellContextHandle->line[shellContextHandle->c_pos + 1U],
+                                      (uint32_t)shellContextHandle->l_pos - (uint32_t)shellContextHandle->c_pos);
+                        shellContextHandle->line[shellContextHandle->l_pos] = '\0';
+                        SHELL_WriteWithCopy(shellContextHandle, "\b", 1);
+                        (void)SHELL_Write(shellContextHandle, &shellContextHandle->line[shellContextHandle->c_pos],
+                                          strlen(&shellContextHandle->line[shellContextHandle->c_pos]));
+                        SHELL_WriteWithCopy(shellContextHandle, "  \b", 3);
+
+                        /* Reset position */
+                        uint32_t i;
+                        for (i = (uint32_t)shellContextHandle->c_pos; i <= (uint32_t)shellContextHandle->l_pos; i++)
+                        {
+                            SHELL_WriteWithCopy(shellContextHandle, "\b", 1);
+                        }
+                    }
+                    else /* Normal backspace operation */
+                    {
+                        SHELL_WriteWithCopy(shellContextHandle, "\b \b", 3);
+                        shellContextHandle->line[shellContextHandle->l_pos] = '\0';
+                    }
+                    continue;
+                }
+                else
+                {
+                    /* MISRA C-2012 Rule 15.7 */
+                }
+
+                /* Input too long */
+                if (shellContextHandle->l_pos >= (SHELL_BUFFER_SIZE - 1U))
+                {
+                    shellContextHandle->l_pos = 0U;
+                }
+
+                /* Handle end of line, break */
+                if (((char)ch == '\r') || ((char)ch == '\n'))
+                {
+                    static char endoflinechar = '\0';
+
+                    if (((uint8_t)endoflinechar != 0U) && ((uint8_t)endoflinechar != ch))
+                    {
+                        continue;
+                    }
+                    else
+                    {
+                        endoflinechar = (char)ch;
+                        /* Print new line. */
+                        SHELL_WriteWithCopy(shellContextHandle, "\r\n", 2U); /* MISRA C-2012 Rule 7.4 */
+                        /* If command line is not NULL, will start process it. */
+                        if (0U != strlen(shellContextHandle->line))
+                        {
+                            SHELL_ProcessCommand(shellContextHandle, shellContextHandle->line);
+                        }
+                        /* Print prompt. */
+                        (void)SHELL_Write(shellContextHandle, shellContextHandle->prompt,
+                                          strlen(shellContextHandle->prompt));
+                        /* Reset all params */
+                        shellContextHandle->c_pos = shellContextHandle->l_pos = 0;
+                        shellContextHandle->hist_current                      = 0;
+                        (void)memset(shellContextHandle->line, 0, sizeof(shellContextHandle->line));
+                        continue;
+                    }
+                }
+
+                /* Normal character */
+                if (shellContextHandle->c_pos < shellContextHandle->l_pos)
+                {
+                    (void)memmove(&shellContextHandle->line[shellContextHandle->c_pos + 1U],
+                                  &shellContextHandle->line[shellContextHandle->c_pos],
+                                  (uint32_t)shellContextHandle->l_pos - (uint32_t)shellContextHandle->c_pos);
+                    shellContextHandle->line[shellContextHandle->c_pos] = (char)ch;
+                    (void)SHELL_Write(shellContextHandle, &shellContextHandle->line[shellContextHandle->c_pos],
+                                      strlen(&shellContextHandle->line[shellContextHandle->c_pos]));
+                    /* Move the cursor to new position */
+                    uint32_t i;
+                    for (i = (uint32_t)shellContextHandle->c_pos; i < (uint32_t)shellContextHandle->l_pos; i++)
+                    {
+                        SHELL_WriteWithCopy(shellContextHandle, "\b", 1);
+                    }
+                }
+                else
+                {
+                    shellContextHandle->line[shellContextHandle->l_pos] = (char)ch;
+                    (void)SHELL_Write(shellContextHandle, &shellContextHandle->line[shellContextHandle->l_pos], 1);
+                }
+
+                ch = 0;
+                shellContextHandle->l_pos++;
+                shellContextHandle->c_pos++;
+            } while (0U == shellContextHandle->exit);
+        }
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U))
+#else
+            }
+        } while (1U == gUseRtos_c); /* USE_RTOS = 0 for BareMetal and 1 for OS */
+#endif
+
+#endif
+
+#endif
+    }
+}
+
+static shell_status_t SHELL_HelpCommand(shell_handle_t shellHandle, int32_t argc, char **argv)
+{
+    shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)shellHandle;
+    shell_command_t *shellCommandContextHandle;
+    list_element_handle_t p = LIST_GetHead(&shellContextHandle->commandContextListHead);
+
+    while (p != NULL)
+    {
+        shellCommandContextHandle = SHEEL_COMMAND_POINTER(p);
+        if ((shellCommandContextHandle->pcHelpString != NULL) && (bool)strlen(shellCommandContextHandle->pcHelpString))
+        {
+            (void)SHELL_Write(shellContextHandle, shellCommandContextHandle->pcHelpString,
+                              strlen(shellCommandContextHandle->pcHelpString));
+        }
+
+        p = LIST_GetNext(p);
+    }
+    return kStatus_SHELL_Success;
+}
+
+static shell_status_t SHELL_ExitCommand(shell_handle_t shellHandle, int32_t argc, char **argv)
+{
+    shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)shellHandle;
+    /* Skip warning */
+    SHELL_WriteWithCopy(shellContextHandle, "\r\nSHELL exited\r\n", strlen("\r\nSHELL exited\r\n"));
+    shellContextHandle->exit = (uint8_t) true;
+    return kStatus_SHELL_Success;
+}
+
+static void SHELL_ProcessCommand(shell_context_handle_t *shellContextHandle, const char *cmd)
+{
+    shell_command_t *tmpCommand = NULL;
+    const char *tmpCommandString;
+    int32_t argc;
+    char *argv[SHELL_BUFFER_SIZE] = {0};
+    list_element_handle_t p;
+    uint8_t flag = 1;
+    uint8_t tmpCommandLen;
+    uint8_t tmpLen;
+    uint8_t i = 0;
+
+    tmpLen = (uint8_t)strlen(cmd);
+    argc   = SHELL_ParseLine(cmd, tmpLen, argv);
+
+    if ((argc > 0))
+    {
+        p = LIST_GetHead(&shellContextHandle->commandContextListHead);
+        while (p != NULL)
+        {
+            tmpCommand       = SHEEL_COMMAND_POINTER(p);
+            tmpCommandString = tmpCommand->pcCommand;
+            tmpCommandLen    = (uint8_t)strlen(tmpCommandString);
+            /* Compare with space or end of string */
+            if ((cmd[tmpCommandLen] == ' ') || (cmd[tmpCommandLen] == (char)0x00))
+            {
+                if (SHELL_StringCompare(tmpCommandString, argv[0], (int32_t)tmpCommandLen) == 0)
+                {
+                    /* support commands with optional number of parameters */
+                    if (tmpCommand->cExpectedNumberOfParameters == (uint8_t)SHELL_IGNORE_PARAMETER_COUNT)
+                    {
+                        flag = 0;
+                    }
+                    else if ((tmpCommand->cExpectedNumberOfParameters == 0U) && (argc == 1))
+                    {
+                        flag = 0;
+                    }
+                    else if (tmpCommand->cExpectedNumberOfParameters > 0U)
+                    {
+                        if ((argc - 1) == (int32_t)tmpCommand->cExpectedNumberOfParameters)
+                        {
+                            flag = 0;
+                        }
+                    }
+                    else
+                    {
+                        flag = 1;
+                    }
+                    break;
+                }
+            }
+            p = LIST_GetNext(p);
+        }
+        if (NULL == p)
+        {
+            tmpCommand = NULL;
+        }
+    }
+
+    if ((tmpCommand != NULL) && (flag == 1U))
+    {
+        SHELL_WriteWithCopy(
+            shellContextHandle,
+            "\r\nIncorrect command parameter(s).  Enter \"help\" to view a list of available commands.\r\n\r\n",
+            strlen(
+                "\r\nIncorrect command parameter(s).  Enter \"help\" to view a list of available commands.\r\n\r\n"));
+    }
+    else if (tmpCommand != NULL)
+    {
+        tmpLen = (uint8_t)strlen(cmd);
+        /* Compare with last command. Push back to history buffer if different */
+        if (tmpLen != (uint8_t)SHELL_StringCompare(cmd, shellContextHandle->hist_buf[0], (int32_t)strlen(cmd)))
+        {
+            for (i = SHELL_HISTORY_COUNT - 1U; i > 0U; i--)
+            {
+                (void)memset(shellContextHandle->hist_buf[i], (int)'\0', SHELL_BUFFER_SIZE);
+                tmpLen = (uint8_t)strlen(shellContextHandle->hist_buf[i - 1U]);
+                (void)memcpy(shellContextHandle->hist_buf[i], shellContextHandle->hist_buf[i - 1U], tmpLen);
+            }
+            (void)memset(shellContextHandle->hist_buf[0], (int)'\0', SHELL_BUFFER_SIZE);
+            tmpLen = (uint8_t)strlen(cmd);
+            (void)memcpy(shellContextHandle->hist_buf[0], cmd, tmpLen);
+            if (shellContextHandle->hist_count < SHELL_HISTORY_COUNT)
+            {
+                shellContextHandle->hist_count++;
+            }
+        }
+        (void)tmpCommand->pFuncCallBack(shellContextHandle, argc, argv);
+    }
+    else
+    {
+        SHELL_WriteWithCopy(
+            shellContextHandle,
+            "\r\nCommand not recognized.  Enter 'help' to view a list of available commands.\r\n\r\n",
+            strlen("\r\nCommand not recognized.  Enter 'help' to view a list of available commands.\r\n\r\n"));
+    }
+}
+
+static void SHELL_GetHistoryCommand(shell_context_handle_t *shellContextHandle, uint8_t hist_pos)
+{
+    uint32_t i;
+    uint32_t tmp;
+
+    if (shellContextHandle->hist_buf[0][0] == '\0')
+    {
+        shellContextHandle->hist_current = 0;
+        return;
+    }
+
+#if 0 /*hist_pos is passed from hist_current. And hist_current is only changed in case 'A'/'B',as hist_count is 3 \
+         most, it can't be more than 3  */
+    if (hist_pos >= SHELL_HISTORY_COUNT)
+    {
+        hist_pos = SHELL_HISTORY_COUNT - 1U;
+    }
+#endif
+
+    tmp = strlen(shellContextHandle->line);
+    /* Clear current if have */
+    if (tmp > 0U)
+    {
+        (void)memset(shellContextHandle->line, (int)'\0', tmp);
+        for (i = 0U; i < tmp; i++)
+        {
+            SHELL_WriteWithCopy(shellContextHandle, "\b \b", 3);
+        }
+    }
+
+    shellContextHandle->l_pos = (uint8_t)strlen(shellContextHandle->hist_buf[hist_pos]);
+    shellContextHandle->c_pos = shellContextHandle->l_pos;
+    (void)memcpy(shellContextHandle->line, shellContextHandle->hist_buf[hist_pos], shellContextHandle->l_pos);
+    (void)SHELL_Write(shellContextHandle, shellContextHandle->hist_buf[hist_pos],
+                      strlen(shellContextHandle->hist_buf[hist_pos]));
+}
+
+static void SHELL_AutoComplete(shell_context_handle_t *shellContextHandle)
+{
+    int32_t minLen;
+    list_element_handle_t p;
+    shell_command_t *tmpCommand = NULL;
+    const char *namePtr;
+    const char *cmdName;
+
+    minLen  = (int32_t)SHELL_BUFFER_SIZE;
+    namePtr = NULL;
+
+    /* Empty tab, list all commands */
+    if (shellContextHandle->line[0] == '\0')
+    {
+        (void)SHELL_HelpCommand(shellContextHandle, 0, NULL);
+        return;
+    }
+
+    SHELL_WriteWithCopy(shellContextHandle, "\r\n", 2);
+
+    /* Do auto complete */
+    p = LIST_GetHead(&shellContextHandle->commandContextListHead);
+    while (p != NULL)
+    {
+        tmpCommand = SHEEL_COMMAND_POINTER(p);
+        cmdName    = tmpCommand->pcCommand;
+        if (SHELL_StringCompare(shellContextHandle->line, cmdName, (int32_t)strlen(shellContextHandle->line)) == 0)
+        {
+            /* Show possible matches */
+            (void)SHELL_Printf(shellContextHandle, "%s    ", cmdName);
+            if (minLen > ((int32_t)strlen(cmdName)))
+            {
+                namePtr = cmdName;
+                minLen  = (int32_t)strlen(namePtr);
+            }
+        }
+        p = LIST_GetNext(p);
+    }
+    /* Auto complete string */
+    if (namePtr != NULL)
+    {
+        (void)memcpy(shellContextHandle->line, namePtr, (uint32_t)minLen);
+    }
+    SHELL_PrintPrompt(shellContextHandle);
+    (void)SHELL_Write(shellContextHandle, shellContextHandle->line, strlen(shellContextHandle->line));
+    return;
+}
+
+static int32_t SHELL_StringCompare(const char *str1, const char *str2, int32_t count)
+{
+    while ((bool)(count--))
+    {
+        if (*str1++ != *str2++)
+        {
+            return (int32_t)(*(str1 - 1) - *(str2 - 1));
+        }
+    }
+    return 0;
+}
+
+static int32_t SHELL_ParseLine(const char *cmd, uint32_t len, char *argv[])
+{
+    uint32_t argc;
+    char *p;
+    uint32_t position;
+
+    /* Init params */
+    (void)memset(s_paramBuffer, (int)'\0', len + 1U);
+    (void)memcpy(s_paramBuffer, cmd, len);
+
+    p        = s_paramBuffer;
+    position = 0;
+    argc     = 0;
+
+    while (position < len)
+    {
+        /* Skip all blanks */
+        while ((position < len) && ((char)(*p) == ' '))
+        {
+            *p = '\0';
+            p++;
+            position++;
+        }
+
+        if (position >= len)
+        {
+            break;
+        }
+
+        /* Process begin of a string */
+        if (*p == '"')
+        {
+            p++;
+            position++;
+            argv[argc] = p;
+            argc++;
+            /* Skip this string */
+            while ((*p != '"') && (position < len))
+            {
+                p++;
+                position++;
+            }
+            /* Skip '"' */
+            *p = '\0';
+            p++;
+            position++;
+        }
+        else /* Normal char */
+        {
+            argv[argc] = p;
+            argc++;
+            while (((char)*p != ' ') && (position < len))
+            {
+                p++;
+                position++;
+            }
+        }
+    }
+    return (int32_t)argc;
+}
+
+static shell_status_t SHELL_GetChar(shell_context_handle_t *shellContextHandle, uint8_t *ch)
+{
+    shell_status_t status;
+
+#if (!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1)))
+    if (NULL == shellContextHandle->serialHandle)
+    {
+        int ret;
+        ret = getchar();
+        if (ret > 0)
+        {
+            *ch    = (uint8_t)ret;
+            status = kStatus_SHELL_Success;
+        }
+        else
+        {
+            status = kStatus_SHELL_Error;
+        }
+    }
+    else
+#endif
+    {
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+        uint32_t length = 0;
+
+        (void)SerialManager_TryRead(shellContextHandle->serialReadHandle, ch, 1, &length);
+
+        if (length > 0U)
+        {
+            status = kStatus_SHELL_Success;
+        }
+        else
+        {
+            status = kStatus_SHELL_Error;
+        }
+#else
+        status = (shell_status_t)SerialManager_ReadBlocking(shellContextHandle->serialReadHandle, ch, 1);
+#endif
+    }
+
+    return status;
+}
+
+shell_status_t SHELL_Init(shell_handle_t shellHandle, serial_handle_t serialHandle, char *prompt)
+{
+    shell_context_handle_t *shellContextHandle;
+    serial_manager_status_t status = kStatus_SerialManager_Error;
+    (void)status;
+
+    assert(shellHandle);
+#if !(!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1)))
+    assert(serialHandle);
+#endif
+    assert(prompt);
+    assert(SHELL_HANDLE_SIZE >= sizeof(shell_context_handle_t));
+
+    shellContextHandle = (shell_context_handle_t *)shellHandle;
+
+    /* memory set for shellHandle */
+    (void)memset(shellHandle, 0, SHELL_HANDLE_SIZE);
+
+#if (!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1)))
+    if (NULL == serialHandle)
+    {
+    }
+    else
+#endif
+    {
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U))
+        (void)COMMON_TASK_init();
+#else
+        if (KOSA_StatusSuccess != OSA_EventCreate((osa_event_handle_t)shellContextHandle->event, 1U))
+        {
+            return kStatus_SHELL_Error;
+        }
+
+        if (KOSA_StatusSuccess !=
+            OSA_TaskCreate((osa_task_handle_t)shellContextHandle->taskId, OSA_TASK(SHELL_Task), shellContextHandle))
+        {
+            return kStatus_SHELL_Error;
+        }
+#endif
+
+#endif
+
+#endif
+    }
+
+    shellContextHandle->prompt       = prompt;
+    shellContextHandle->serialHandle = serialHandle;
+
+#if (!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1)))
+    if (NULL == serialHandle)
+    {
+    }
+    else
+#endif
+    {
+        shellContextHandle->serialWriteHandle = (serial_write_handle_t)&shellContextHandle->serialWriteHandleBuffer[0];
+        status = SerialManager_OpenWriteHandle(shellContextHandle->serialHandle, shellContextHandle->serialWriteHandle);
+        assert(kStatus_SerialManager_Success == status);
+
+        shellContextHandle->serialReadHandle = (serial_read_handle_t)&shellContextHandle->serialReadHandleBuffer[0];
+        status = SerialManager_OpenReadHandle(shellContextHandle->serialHandle, shellContextHandle->serialReadHandle);
+        assert(kStatus_SerialManager_Success == status);
+
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+        status = SerialManager_InstallRxCallback(shellContextHandle->serialReadHandle, SHELL_SerialManagerRxCallback,
+                                                 shellContextHandle);
+        assert(kStatus_SerialManager_Success == status);
+#endif
+        (void)status;
+    }
+
+    (void)SHELL_RegisterCommand(shellContextHandle, SHELL_COMMAND(help));
+    (void)SHELL_RegisterCommand(shellContextHandle, SHELL_COMMAND(exit));
+
+    SHELL_WriteWithCopy(shellContextHandle, "\r\nSHELL build: ", strlen("\r\nSHELL build: "));
+    SHELL_WriteWithCopy(shellContextHandle, __DATE__, strlen(__DATE__));
+    SHELL_WriteWithCopy(shellContextHandle, "\r\nCopyright  2020  NXP\r\n", strlen("\r\nCopyright  2020  NXP\r\n"));
+    SHELL_PrintPrompt(shellContextHandle);
+
+    return kStatus_SHELL_Success;
+}
+
+shell_status_t SHELL_RegisterCommand(shell_handle_t shellHandle, shell_command_t *shellCommand)
+{
+    shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)shellHandle;
+    assert(shellHandle);
+    assert(shellCommand);
+
+    /* memory set for shellHandle */
+    (void)memset(&shellCommand->link, 0, sizeof(shellCommand->link));
+
+    (void)LIST_AddTail(&shellContextHandle->commandContextListHead, &shellCommand->link);
+
+    return kStatus_SHELL_Success;
+}
+
+shell_status_t SHELL_UnregisterCommand(shell_command_t *shellCommand)
+{
+    assert(shellCommand);
+
+    (void)LIST_RemoveElement(&shellCommand->link);
+
+    /* memory set for shellHandle */
+    (void)memset(&shellCommand->link, 0, sizeof(shellCommand->link));
+
+    return kStatus_SHELL_Success;
+}
+
+shell_status_t SHELL_Write(shell_handle_t shellHandle, char *buffer, uint32_t length)
+{
+    shell_context_handle_t *shellContextHandle;
+    uint32_t primask;
+    shell_status_t status;
+
+    assert(shellHandle);
+    assert(buffer);
+
+    if (!(bool)length)
+    {
+        return kStatus_SHELL_Success;
+    }
+
+    shellContextHandle = (shell_context_handle_t *)shellHandle;
+
+    primask = DisableGlobalIRQ();
+    if ((bool)shellContextHandle->printBusy)
+    {
+        EnableGlobalIRQ(primask);
+        return kStatus_SHELL_Error;
+    }
+    shellContextHandle->printBusy = 1U;
+    EnableGlobalIRQ(primask);
+#if (!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1)))
+    if (NULL == shellContextHandle->serialHandle)
+    {
+        status = kStatus_SHELL_Success;
+        for (uint32_t index = 0; index < length; index++)
+        {
+            (void)putchar(buffer[index]);
+        }
+    }
+    else
+#endif
+    {
+        status = (shell_status_t)SerialManager_WriteBlocking(shellContextHandle->serialWriteHandle, (uint8_t *)buffer,
+                                                             length);
+    }
+
+    shellContextHandle->printBusy = 0U;
+
+    return status;
+}
+
+/* For MISRA to fix const */
+static void SHELL_WriteWithCopy(shell_handle_t shellHandle, const char *buffer, uint32_t length)
+{
+    char s_shellWriteCopyBuffer[128];
+
+    assert(length <= 128UL);
+
+    (void)memcpy(s_shellWriteCopyBuffer, buffer, length);
+    (void)SHELL_Write(shellHandle, s_shellWriteCopyBuffer, length);
+}
+
+int SHELL_Printf(shell_handle_t shellHandle, const char *formatString, ...)
+{
+    shell_context_handle_t *shellContextHandle;
+    uint32_t length;
+    uint32_t primask;
+    va_list ap;
+
+    assert(shellHandle);
+    assert(formatString);
+
+    shellContextHandle = (shell_context_handle_t *)shellHandle;
+
+    primask = DisableGlobalIRQ();
+    if ((bool)shellContextHandle->printBusy)
+    {
+        EnableGlobalIRQ(primask);
+        return -1;
+    }
+    shellContextHandle->printBusy = 1U;
+    EnableGlobalIRQ(primask);
+
+    va_start(ap, formatString);
+
+    shellContextHandle->printLength = 0U;
+    length                          = (uint32_t)SHELL_Sprintf(shellHandle, formatString, ap);
+#if (!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1)))
+    if (NULL == shellContextHandle->serialHandle)
+    {
+        for (uint32_t index = 0; index < length; index++)
+        {
+            (void)putchar(shellContextHandle->printBuffer[index]);
+        }
+    }
+    else
+#endif
+    {
+        (void)SerialManager_WriteBlocking(shellContextHandle->serialWriteHandle,
+                                          (uint8_t *)shellContextHandle->printBuffer, length);
+    }
+    va_end(ap);
+
+    shellContextHandle->printBusy = 0U;
+    return (int32_t)shellContextHandle->printLength;
+}
+
+void SHELL_ChangePrompt(shell_handle_t shellHandle, char *prompt)
+{
+    shell_context_handle_t *shellContextHandle;
+    assert(shellHandle);
+    assert(prompt);
+
+    shellContextHandle = (shell_context_handle_t *)shellHandle;
+
+    shellContextHandle->prompt = prompt;
+    SHELL_PrintPrompt(shellContextHandle);
+}
+
+void SHELL_PrintPrompt(shell_handle_t shellHandle)
+{
+    shell_context_handle_t *shellContextHandle;
+    assert(shellHandle);
+
+    shellContextHandle = (shell_context_handle_t *)shellHandle;
+
+    SHELL_WriteWithCopy(shellContextHandle, "\r\n", 2U); /* MISRA C-2012 Rule 7.4 */
+    (void)SHELL_Write(shellContextHandle, shellContextHandle->prompt, strlen(shellContextHandle->prompt));
+}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/utilities/fsl_shell.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/utilities/fsl_shell.h
new file mode 100644
index 000000000..28eace717
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54005/utilities/fsl_shell.h
@@ -0,0 +1,292 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FSL_SHELL_H__
+#define __FSL_SHELL_H__
+
+/*!
+ * @addtogroup SHELL
+ * @{
+ */
+
+#include "fsl_common.h"
+#include "fsl_component_serial_manager.h"
+#include "fsl_component_generic_list.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Whether use non-blocking mode. */
+#ifndef SHELL_NON_BLOCKING_MODE
+#define SHELL_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE
+#endif
+
+/*! @brief Macro to set on/off auto-complete feature. */
+#define SHELL_AUTO_COMPLETE (1U)
+
+/*! @brief Macro to set console buffer size. */
+#ifndef SHELL_BUFFER_SIZE
+#define SHELL_BUFFER_SIZE (64U)
+#endif
+
+/*! @brief Macro to set maximum arguments in command. */
+#define SHELL_MAX_ARGS (8U)
+
+/*! @brief Macro to set maximum count of history commands. */
+#ifndef SHELL_HISTORY_COUNT
+#define SHELL_HISTORY_COUNT (3U)
+#endif
+
+/*! @brief Macro to bypass arguments check */
+#define SHELL_IGNORE_PARAMETER_COUNT (0xFF)
+
+/*! @brief The handle size of the shell module. It is the sum of the SHELL_HISTORY_COUNT * SHELL_BUFFER_SIZE +
+ * SHELL_BUFFER_SIZE + SERIAL_MANAGER_READ_HANDLE_SIZE + SERIAL_MANAGER_WRITE_HANDLE_SIZE*/
+#define SHELL_HANDLE_SIZE                                                                                   \
+    (160U + SHELL_HISTORY_COUNT * SHELL_BUFFER_SIZE + SHELL_BUFFER_SIZE + SERIAL_MANAGER_READ_HANDLE_SIZE + \
+     SERIAL_MANAGER_WRITE_HANDLE_SIZE)
+
+/*! @brief Macro to determine whether use common task. */
+#ifndef SHELL_USE_COMMON_TASK
+#define SHELL_USE_COMMON_TASK (0U)
+#endif
+
+/*! @brief Macro to set shell task priority. */
+#ifndef SHELL_TASK_PRIORITY
+#define SHELL_TASK_PRIORITY (2U)
+#endif
+
+/*! @brief Macro to set shell task stack size. */
+#ifndef SHELL_TASK_STACK_SIZE
+#define SHELL_TASK_STACK_SIZE (1000U)
+#endif
+
+/*! @brief Shell status */
+typedef enum _shell_status
+{
+    kStatus_SHELL_Success               = kStatus_Success,                    /*!< Success */
+    kStatus_SHELL_Error                 = MAKE_STATUS(kStatusGroup_SHELL, 1), /*!< Failed */
+    kStatus_SHELL_OpenWriteHandleFailed = MAKE_STATUS(kStatusGroup_SHELL, 2), /*!< Open write handle failed */
+    kStatus_SHELL_OpenReadHandleFailed  = MAKE_STATUS(kStatusGroup_SHELL, 3), /*!< Open read handle failed */
+} shell_status_t;
+
+/*! @brief The handle of the shell module */
+typedef void *shell_handle_t;
+
+/*! @brief User command function prototype. */
+typedef shell_status_t (*cmd_function_t)(shell_handle_t shellHandle, int32_t argc, char **argv);
+
+/*! @brief User command data configuration structure. */
+typedef struct _shell_command
+{
+    const char *pcCommand; /*!< The command that is executed.  For example "help".  It must be all lower case. */
+    char *pcHelpString;    /*!< String that describes how to use the command.  It should start with the command itself,
+                                    and end with "\r\n".  For example "help: Returns a list of all the commands\r\n". */
+    const cmd_function_t
+        pFuncCallBack; /*!< A pointer to the callback function that returns the output generated by the command. */
+    uint8_t cExpectedNumberOfParameters; /*!< Commands expect a fixed number of parameters, which may be zero. */
+    list_element_t link;                 /*!< link of the element */
+} shell_command_t;
+
+/*!
+ * @brief Defines the shell handle
+ *
+ * This macro is used to define a 4 byte aligned shell handle.
+ * Then use "(shell_handle_t)name" to get the shell handle.
+ *
+ * The macro should be global and could be optional. You could also define shell handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * SHELL_HANDLE_DEFINE(shellHandle);
+ * @endcode
+ *
+ * @param name The name string of the shell handle.
+ */
+#define SHELL_HANDLE_DEFINE(name) uint32_t name[((SHELL_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+
+#if defined(__ICCARM__)
+/* disable misra 19.13 */
+_Pragma("diag_suppress=Pm120")
+#endif
+/*!
+ * @brief Defines the shell command structure
+ *
+ * This macro is used to define the shell command structure #shell_command_t.
+ * And then uses the macro SHELL_COMMAND to get the command structure pointer.
+ * The macro should not be used in any function.
+ *
+ * This is a example,
+ * @code
+ * SHELL_COMMAND_DEFINE(exit, "\r\n\"exit\": Exit program\r\n", SHELL_ExitCommand, 0);
+ * SHELL_RegisterCommand(s_shellHandle, SHELL_COMMAND(exit));
+ * @endcode
+ *
+ * @param command The command string of the command. The double quotes do not need. Such as exit for "exit",
+ *                help for "Help", read for "read".
+ * @param descriptor The description of the command is used for showing the command usage when "help" is typing.
+ * @param callback The callback of the command is used to handle the command line when the input command is matched.
+ * @param paramCount The max parameter count of the current command.
+ */
+#define SHELL_COMMAND_DEFINE(command, descriptor, callback, paramCount) \
+                                                                        \
+    shell_command_t g_shellCommand##command = {                         \
+        (#command), (descriptor), (callback), (paramCount), {0},        \
+    }
+
+/*!
+ * @brief Gets the shell command pointer
+ *
+ * This macro is used to get the shell command pointer. The macro should not be used before the macro
+ * SHELL_COMMAND_DEFINE is used.
+ *
+ * @param command The command string of the command. The double quotes do not need. Such as exit for "exit",
+ *                help for "Help", read for "read".
+ */
+#define SHELL_COMMAND(command) &g_shellCommand##command
+
+#if defined(__ICCARM__)
+    _Pragma("diag_default=Pm120")
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+        extern "C"
+{
+#endif /* _cplusplus */
+
+    /*!
+     * @name Shell functional operation
+     * @{
+     */
+
+    /*!
+     * @brief Initializes the shell module
+     *
+     * This function must be called before calling all other Shell functions.
+     * Call operation the Shell commands with user-defined settings.
+     * The example below shows how to set up the Shell and
+     * how to call the SHELL_Init function by passing in these parameters.
+     * This is an example.
+     * @code
+     *   static SHELL_HANDLE_DEFINE(s_shellHandle);
+     *   SHELL_Init((shell_handle_t)s_shellHandle, (serial_handle_t)s_serialHandle, "Test@SHELL>");
+     * @endcode
+     * @param shellHandle Pointer to point to a memory space of size #SHELL_HANDLE_SIZE allocated by the caller.
+     * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+     * You can define the handle in the following two ways:
+     * #SHELL_HANDLE_DEFINE(shellHandle);
+     * or
+     * uint32_t shellHandle[((SHELL_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+     * @param serialHandle The serial manager module handle pointer.
+     * @param prompt  The string prompt pointer of Shell. Only the global variable can be passed.
+     * @retval kStatus_SHELL_Success The shell initialization succeed.
+     * @retval kStatus_SHELL_Error An error occurred when the shell is initialized.
+     * @retval kStatus_SHELL_OpenWriteHandleFailed Open the write handle failed.
+     * @retval kStatus_SHELL_OpenReadHandleFailed Open the read handle failed.
+     */
+    shell_status_t SHELL_Init(shell_handle_t shellHandle, serial_handle_t serialHandle, char *prompt);
+
+    /*!
+     * @brief Registers the shell command
+     *
+     * This function is used to register the shell command by using the command configuration shell_command_config_t.
+     * This is a example,
+     * @code
+     * SHELL_COMMAND_DEFINE(exit, "\r\n\"exit\": Exit program\r\n", SHELL_ExitCommand, 0);
+     * SHELL_RegisterCommand(s_shellHandle, SHELL_COMMAND(exit));
+     * @endcode
+     * @param shellHandle The shell module handle pointer.
+     * @param shellCommand  The command element.
+     * @retval kStatus_SHELL_Success Successfully register the command.
+     * @retval kStatus_SHELL_Error An error occurred.
+     */
+    shell_status_t SHELL_RegisterCommand(shell_handle_t shellHandle, shell_command_t * shellCommand);
+
+    /*!
+     * @brief Unregisters the shell command
+     *
+     * This function is used to unregister the shell command.
+     *
+     * @param shellCommand The command element.
+     * @retval kStatus_SHELL_Success Successfully unregister the command.
+     */
+    shell_status_t SHELL_UnregisterCommand(shell_command_t * shellCommand);
+
+    /*!
+     * @brief Sends data to the shell output stream.
+     *
+     * This function is used to send data to the shell output stream.
+     *
+     * @param shellHandle The shell module handle pointer.
+     * @param buffer Start address of the data to write.
+     * @param length Length of the data to write.
+     * @retval kStatus_SHELL_Success Successfully send data.
+     * @retval kStatus_SHELL_Error An error occurred.
+     */
+    shell_status_t SHELL_Write(shell_handle_t shellHandle, char *buffer, uint32_t length);
+
+    /*!
+     * @brief Writes formatted output to the shell output stream.
+     *
+     * Call this function to write a formatted output to the shell output stream.
+     *
+     * @param shellHandle The shell module handle pointer.
+     *
+     * @param   formatString Format string.
+     * @return  Returns the number of characters printed or a negative value if an error occurs.
+     */
+    int SHELL_Printf(shell_handle_t shellHandle, const char *formatString, ...);
+
+    /*!
+     * @brief Change shell prompt.
+     *
+     * Call this function to change shell prompt.
+     *
+     * @param shellHandle The shell module handle pointer.
+     *
+     * @param prompt The string which will be used for command prompt
+     * @return  NULL.
+     */
+    void SHELL_ChangePrompt(shell_handle_t shellHandle, char *prompt);
+
+    /*!
+     * @brief Print shell prompt.
+     *
+     * Call this function to print shell prompt.
+     *
+     * @param shellHandle The shell module handle pointer.
+     *
+     * @return  NULL.
+     */
+    void SHELL_PrintPrompt(shell_handle_t shellHandle);
+
+/*!
+ * @brief The task function for Shell.
+ * The task function for Shell; The function should be polled by upper layer.
+ * This function does not return until Shell command exit was called.
+ *
+ * @param shellHandle The shell module handle pointer.
+ */
+#if !(defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+    void SHELL_Task(shell_handle_t shellHandle);
+#endif
+
+    /* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_SHELL_H__ */