aboutsummaryrefslogtreecommitdiff
path: root/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54016/LPC54016.h
diff options
context:
space:
mode:
Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/LPC54016/LPC54016.h')
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC54016/LPC54016.h20862
1 files changed, 20862 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54016/LPC54016.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54016/LPC54016.h
new file mode 100644
index 000000000..ad435d74e
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54016/LPC54016.h
@@ -0,0 +1,20862 @@
1/*
2** ###################################################################
3** Processors: LPC54016JBD100
4** LPC54016JBD208
5** LPC54016JET180
6**
7** Compilers: GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9** Keil ARM C/C++ Compiler
10** MCUXpresso Compiler
11**
12** Reference manual: LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
13** Version: rev. 1.2, 2017-06-08
14** Build: b200304
15**
16** Abstract:
17** CMSIS Peripheral Access Layer for LPC54016
18**
19** Copyright 1997-2016 Freescale Semiconductor, Inc.
20** Copyright 2016-2020 NXP
21** All rights reserved.
22**
23** SPDX-License-Identifier: BSD-3-Clause
24**
25** http: www.nxp.com
26** mail: [email protected]
27**
28** Revisions:
29** - rev. 1.0 (2016-08-12)
30** Initial version.
31** - rev. 1.1 (2016-11-25)
32** Update CANFD and Classic CAN register.
33** Add MAC TIMERSTAMP registers.
34** - rev. 1.2 (2017-06-08)
35** Remove RTC_CTRL_RTC_OSC_BYPASS.
36** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
37** Remove RESET and HALT from SYSCON_AHBCLKDIV.
38**
39** ###################################################################
40*/
41
42/*!
43 * @file LPC54016.h
44 * @version 1.2
45 * @date 2017-06-08
46 * @brief CMSIS Peripheral Access Layer for LPC54016
47 *
48 * CMSIS Peripheral Access Layer for LPC54016
49 */
50
51#ifndef _LPC54016_H_
52#define _LPC54016_H_ /**< Symbol preventing repeated inclusion */
53
54/** Memory map major version (memory maps with equal major version number are
55 * compatible) */
56#define MCU_MEM_MAP_VERSION 0x0100U
57/** Memory map minor version */
58#define MCU_MEM_MAP_VERSION_MINOR 0x0002U
59
60
61/* ----------------------------------------------------------------------------
62 -- Interrupt vector numbers
63 ---------------------------------------------------------------------------- */
64
65/*!
66 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
67 * @{
68 */
69
70/** Interrupt Number Definitions */
71#define NUMBER_OF_INT_VECTORS 73 /**< Number of interrupts in the Vector table */
72
73typedef enum IRQn {
74 /* Auxiliary constants */
75 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
76
77 /* Core interrupts */
78 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
79 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
80 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
81 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
82 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
83 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
84 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
85 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
86 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
87
88 /* Device specific interrupts */
89 WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */
90 DMA0_IRQn = 1, /**< DMA controller */
91 GINT0_IRQn = 2, /**< GPIO group 0 */
92 GINT1_IRQn = 3, /**< GPIO group 1 */
93 PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */
94 PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */
95 PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */
96 PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */
97 UTICK0_IRQn = 8, /**< Micro-tick Timer */
98 MRT0_IRQn = 9, /**< Multi-rate timer */
99 CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
100 CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
101 SCT0_IRQn = 12, /**< SCTimer/PWM */
102 CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
103 FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
104 FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
105 FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
106 FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
107 FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
108 FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
109 FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
110 FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
111 ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */
112 ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */
113 ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */
114 DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */
115 HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */
116 USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */
117 USB0_IRQn = 28, /**< USB device */
118 RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */
119 FLEXCOMM10_IRQn = 30, /**< Flexcomm Interface 10 (SPI, FLEXCOMM) */
120 Reserved47_IRQn = 31, /**< Reserved interrupt */
121 PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */
122 PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */
123 PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */
124 PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */
125 CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */
126 CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */
127 RIT_IRQn = 38, /**< Repetitive Interrupt Timer */
128 SPIFI0_IRQn = 39, /**< SPI flash interface */
129 FLEXCOMM8_IRQn = 40, /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
130 FLEXCOMM9_IRQn = 41, /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
131 SDIO_IRQn = 42, /**< SD/MMC */
132 CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */
133 CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */
134 CAN1_IRQ0_IRQn = 45, /**< CAN1 interrupt0 */
135 CAN1_IRQ1_IRQn = 46, /**< CAN1 interrupt1 */
136 USB1_IRQn = 47, /**< USB1 interrupt */
137 USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */
138 ETHERNET_IRQn = 49, /**< Ethernet */
139 ETHERNET_PMT_IRQn = 50, /**< Ethernet power management interrupt */
140 ETHERNET_MACLP_IRQn = 51, /**< Ethernet MAC interrupt */
141 Reserved68_IRQn = 52, /**< Reserved interrupt */
142 LCD_IRQn = 53, /**< LCD interrupt */
143 SHA_IRQn = 54, /**< SHA interrupt */
144 SMARTCARD0_IRQn = 55, /**< Smart card 0 interrupt */
145 SMARTCARD1_IRQn = 56 /**< Smart card 1 interrupt */
146} IRQn_Type;
147
148/*!
149 * @}
150 */ /* end of group Interrupt_vector_numbers */
151
152
153/* ----------------------------------------------------------------------------
154 -- Cortex M4 Core Configuration
155 ---------------------------------------------------------------------------- */
156
157/*!
158 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
159 * @{
160 */
161
162#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
163#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
164#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
165#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
166
167#include "core_cm4.h" /* Core Peripheral Access Layer */
168#include "system_LPC54016.h" /* Device specific configuration file */
169
170/*!
171 * @}
172 */ /* end of group Cortex_Core_Configuration */
173
174
175/* ----------------------------------------------------------------------------
176 -- Mapping Information
177 ---------------------------------------------------------------------------- */
178
179/*!
180 * @addtogroup Mapping_Information Mapping Information
181 * @{
182 */
183
184/** Mapping Information */
185/*!
186 * @addtogroup dma_request
187 * @{
188 */
189
190/*******************************************************************************
191 * Definitions
192 ******************************************************************************/
193
194/*!
195 * @brief Structure for the DMA hardware request
196 *
197 * Defines the structure for the DMA hardware request collections. The user can configure the
198 * hardware request to trigger the DMA transfer accordingly. The index
199 * of the hardware request varies according to the to SoC.
200 */
201typedef enum _dma_request_source
202{
203 kDmaRequestFlexcomm0Rx = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */
204 kDmaRequestFlexcomm0Tx = 1U, /**< Flexcomm Interface 0 TX/I2C Master */
205 kDmaRequestFlexcomm1Rx = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */
206 kDmaRequestFlexcomm1Tx = 3U, /**< Flexcomm Interface 1 TX/I2C Master */
207 kDmaRequestFlexcomm2Rx = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */
208 kDmaRequestFlexcomm2Tx = 5U, /**< Flexcomm Interface 2 TX/I2C Master */
209 kDmaRequestFlexcomm3Rx = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */
210 kDmaRequestFlexcomm3Tx = 7U, /**< Flexcomm Interface 3 TX/I2C Master */
211 kDmaRequestFlexcomm4Rx = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */
212 kDmaRequestFlexcomm4Tx = 9U, /**< Flexcomm Interface 4 TX/I2C Master */
213 kDmaRequestFlexcomm5Rx = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */
214 kDmaRequestFlexcomm5Tx = 11U, /**< Flexcomm Interface 5 TX/I2C Master */
215 kDmaRequestFlexcomm6Rx = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */
216 kDmaRequestFlexcomm6Tx = 13U, /**< Flexcomm Interface 6 TX/I2C Master */
217 kDmaRequestFlexcomm7Rx = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */
218 kDmaRequestFlexcomm7Tx = 15U, /**< Flexcomm Interface 7 TX/I2C Master */
219 kDmaRequestDMIC0 = 16U, /**< Digital microphone interface 0 channel 0 */
220 kDmaRequestDMIC1 = 17U, /**< Digital microphone interface 0 channel 1 */
221 kDmaRequestSPIFI = 18U, /**< SPI Flash Interface */
222 kDmaRequestSHA = 19U, /**< Secure Hash Algorithm */
223 kDmaRequestFlexcomm8Rx = 20U, /**< Flexcomm Interface 8 RX/I2C Slave */
224 kDmaRequestFlexcomm8Tx = 21U, /**< Flexcomm Interface 8 TX/I2C Slave */
225 kDmaRequestFlexcomm9Rx = 22U, /**< Flexcomm Interface 9 RX/I2C Slave */
226 kDmaRequestFlexcomm9Tx = 23U, /**< Flexcomm Interface 9 TX/I2C Slave */
227 kDmaRequestSMARTCARD0_RX = 24U, /**< SMARTCARD0 RX */
228 kDmaRequestSMARTCARD0_TX = 25U, /**< SMARTCARD0 TX */
229 kDmaRequestSMARTCARD1_RX = 26U, /**< SMARTCARD1 RX */
230 kDmaRequestSMARTCARD1_TX = 27U, /**< SMARTCARD1 TX */
231 kDmaRequestFlexcomm10Rx = 28U, /**< Flexcomm Interface 10 RX */
232 kDmaRequestFlexcomm10Tx = 29U, /**< Flexcomm Interface 10 TX */
233} dma_request_source_t;
234
235/* @} */
236
237
238/*!
239 * @}
240 */ /* end of group Mapping_Information */
241
242
243/* ----------------------------------------------------------------------------
244 -- Device Peripheral Access Layer
245 ---------------------------------------------------------------------------- */
246
247/*!
248 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
249 * @{
250 */
251
252
253/*
254** Start of section using anonymous unions
255*/
256
257#if defined(__ARMCC_VERSION)
258 #if (__ARMCC_VERSION >= 6010050)
259 #pragma clang diagnostic push
260 #else
261 #pragma push
262 #pragma anon_unions
263 #endif
264#elif defined(__GNUC__)
265 /* anonymous unions are enabled by default */
266#elif defined(__IAR_SYSTEMS_ICC__)
267 #pragma language=extended
268#else
269 #error Not supported compiler type
270#endif
271
272/* ----------------------------------------------------------------------------
273 -- ADC Peripheral Access Layer
274 ---------------------------------------------------------------------------- */
275
276/*!
277 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
278 * @{
279 */
280
281/** ADC - Register Layout Typedef */
282typedef struct {
283 __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
284 __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
285 __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
286 __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
287 uint8_t RESERVED_0[8];
288 __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
289 __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
290 __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
291 __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
292 __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
293 __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
294 __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
295 __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
296 __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */
297 __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */
298} ADC_Type;
299
300/* ----------------------------------------------------------------------------
301 -- ADC Register Masks
302 ---------------------------------------------------------------------------- */
303
304/*!
305 * @addtogroup ADC_Register_Masks ADC Register Masks
306 * @{
307 */
308
309/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
310/*! @{ */
311#define ADC_CTRL_CLKDIV_MASK (0xFFU)
312#define ADC_CTRL_CLKDIV_SHIFT (0U)
313/*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce
314 * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically,
315 * software should program the smallest value in this field that yields this maximum clock rate or
316 * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may
317 * be desirable. This field is ignored in the asynchronous operating mode.
318 */
319#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
320#define ADC_CTRL_ASYNMODE_MASK (0x100U)
321#define ADC_CTRL_ASYNMODE_SHIFT (8U)
322/*! ASYNMODE - Select clock mode.
323 * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in
324 * the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to
325 * eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger.
326 * In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC
327 * input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger
328 * pulse.
329 * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
330 */
331#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
332#define ADC_CTRL_RESOL_MASK (0x600U)
333#define ADC_CTRL_RESOL_SHIFT (9U)
334/*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher
335 * conversion rates. A single conversion (including one conversion in a burst or sequence) requires the
336 * selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when
337 * the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable
338 * results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate
339 * for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system
340 * clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution
341 * 0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field.
342 * 0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field.
343 * 0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field.
344 * 0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field.
345 */
346#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
347#define ADC_CTRL_BYPASSCAL_MASK (0x800U)
348#define ADC_CTRL_BYPASSCAL_SHIFT (11U)
349/*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset
350 * error is not a concern in the application.
351 * 0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for
352 * offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may
353 * be warranted periodically - especially if operating conditions have changed.
354 * 0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC -
355 * particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set.
356 */
357#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
358#define ADC_CTRL_TSAMP_MASK (0x7000U)
359#define ADC_CTRL_TSAMP_SHIFT (12U)
360/*! TSAMP - Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion
361 * is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions
362 * and the output impedance of the analog source, longer sampling times may be required. See
363 * Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to
364 * seven, by which the sample period will be extended. The total conversion time will increase by
365 * the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A
366 * complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will
367 * be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will
368 * require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock
369 * cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be
370 * extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require
371 * 22 ADC clocks.
372 */
373#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
374/*! @} */
375
376/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
377/*! @{ */
378#define ADC_INSEL_SEL_MASK (0x3U)
379#define ADC_INSEL_SEL_SHIFT (0U)
380/*! SEL - Selects the input source for channel 0. All other values are reserved.
381 * 0b00..ADC0_IN0 function.
382 * 0b11..Internal temperature sensor.
383 */
384#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
385/*! @} */
386
387/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
388/*! @{ */
389#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU)
390#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U)
391/*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this
392 * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be
393 * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1
394 * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via
395 * software command, ADC conversions will be performed on each enabled channel, in sequence,
396 * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31)
397 * is LOW. It is allowed to change this field and set bit 31 in the same write.
398 */
399#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
400#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U)
401#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U)
402/*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion
403 * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order
404 * to avoid generating a spurious trigger, it is recommended writing to this field only when
405 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
406 */
407#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
408#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U)
409#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U)
410/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In
411 * order to avoid generating a spurious trigger, it is recommended writing to this field only when
412 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
413 * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
414 * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
415 */
416#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
417#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U)
418#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U)
419/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization
420 * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a
421 * conversion. There are slightly different criteria for whether or not this bit can be set
422 * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0):
423 * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already
424 * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer).
425 * Whether this bit is set or not, a trigger pulse must be maintained for at least one system
426 * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be
427 * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse
428 * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and
429 * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be
430 * maintained for one system clock period.
431 * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled.
432 * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled.
433 */
434#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
435#define ADC_SEQ_CTRL_START_MASK (0x4000000U)
436#define ADC_SEQ_CTRL_START_SHIFT (26U)
437/*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The
438 * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this
439 * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a
440 * conversion sequence. It will consequently always read back as a zero.
441 */
442#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
443#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U)
444#define ADC_SEQ_CTRL_BURST_SHIFT (27U)
445/*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled
446 * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions
447 * can be halted by clearing this bit. The sequence currently in progress will be completed before
448 * conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
449 */
450#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
451#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U)
452#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U)
453/*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a
454 * single conversion on the next channel in the sequence instead of the default response of
455 * launching an entire sequence of conversions. Once all of the channels comprising a sequence have
456 * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled
457 * channel. Interrupt generation will still occur either after each individual conversion or at
458 * the end of the entire sequence, depending on the state of the MODE bit.
459 */
460#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
461#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U)
462#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U)
463/*! LOWPRIO - Set priority for sequence A.
464 * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
465 * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence
466 * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion
467 * currently in progress will be terminated. The A sequence that was interrupted will automatically resume
468 * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the
469 * conversion sequence will resume from that point.
470 */
471#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
472#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U)
473#define ADC_SEQ_CTRL_MODE_SHIFT (30U)
474/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence
475 * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each
476 * conversion, or the individual channel result registers at the end of the entire sequence. Impacts
477 * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which
478 * overrun conditions contribute to an overrun interrupt as described below.
479 * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC
480 * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The
481 * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger
482 * if enabled.
483 * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A
484 * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in
485 * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun
486 * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
487 */
488#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
489#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U)
490#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U)
491/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be
492 * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state
493 * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered
494 * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care
495 * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE
496 * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be
497 * triggered immediately upon being enabled.
498 * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence
499 * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is
500 * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
501 * 0b1..Enabled. Sequence n is enabled.
502 */
503#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
504/*! @} */
505
506/* The count of ADC_SEQ_CTRL */
507#define ADC_SEQ_CTRL_COUNT (2U)
508
509/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
510/*! @{ */
511#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U)
512#define ADC_SEQ_GDAT_RESULT_SHIFT (4U)
513/*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion
514 * performed under conversion sequence associated with this register. The result is a binary
515 * fraction representing the voltage on the currently-selected input channel as it falls within the
516 * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less
517 * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input
518 * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this
519 * result has not yet been read.
520 */
521#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
522#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U)
523#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U)
524/*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or
525 * within the range established by the designated threshold comparison registers (THRn_LOW and
526 * THRn_HIGH).
527 */
528#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
529#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U)
530#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U)
531/*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a
532 * crossing of the threshold level established by the designated LOW threshold comparison register
533 * (THRn_LOW) and, if so, in what direction the crossing occurred.
534 */
535#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
536#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U)
537#define ADC_SEQ_GDAT_CHN_SHIFT (26U)
538/*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000
539 * identifies channel 0, 0001 channel 1, etc.).
540 */
541#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
542#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U)
543#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U)
544/*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a
545 * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along
546 * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun
547 * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set
548 * to '0' (and if the overrun interrupt is enabled).
549 */
550#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
551#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U)
552#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U)
553/*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded
554 * into the RESULT field. It is cleared whenever this register is read. This bit will cause a
555 * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that
556 * sequence is set to 0 (and if the interrupt is enabled).
557 */
558#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
559/*! @} */
560
561/* The count of ADC_SEQ_GDAT */
562#define ADC_SEQ_GDAT_COUNT (2U)
563
564/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
565/*! @{ */
566#define ADC_DAT_RESULT_MASK (0xFFF0U)
567#define ADC_DAT_RESULT_SHIFT (4U)
568/*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed
569 * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin,
570 * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on
571 * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that
572 * the voltage on the input was close to, equal to, or greater than that on VREFP.
573 */
574#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
575#define ADC_DAT_THCMPRANGE_MASK (0x30000U)
576#define ADC_DAT_THCMPRANGE_SHIFT (16U)
577/*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion
578 * was greater than or equal to the value programmed into the designated LOW threshold register
579 * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold
580 * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value
581 * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last
582 * completed conversion was greater than the value programmed into the designated HIGH threshold
583 * register (THRn_HIGH). 0x3 = Reserved.
584 */
585#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
586#define ADC_DAT_THCMPCROSS_MASK (0xC0000U)
587#define ADC_DAT_THCMPCROSS_SHIFT (18U)
588/*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The
589 * most recent completed conversion on this channel had the same relationship (above or below) to
590 * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the
591 * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing
592 * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the
593 * previous sample on this channel was above the threshold value established by the designated LOW
594 * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward
595 * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred
596 * - i.e. the previous sample on this channel was below the threshold value established by the
597 * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
598 */
599#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
600#define ADC_DAT_CHANNEL_MASK (0x3C000000U)
601#define ADC_DAT_CHANNEL_SHIFT (26U)
602/*! CHANNEL - This field is hard-coded to contain the channel number that this particular register
603 * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1
604 * register, etc)
605 */
606#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
607#define ADC_DAT_OVERRUN_MASK (0x40000000U)
608#define ADC_DAT_OVERRUN_SHIFT (30U)
609/*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and
610 * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit
611 * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when
612 * the data related to this channel is read from either of the global SEQn_GDAT registers. This
613 * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if
614 * the overrun interrupt is enabled. While it is allowed to include the same channels in both
615 * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the
616 * data registers associated with any of the channels that are shared between the two sequences. Any
617 * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
618 */
619#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
620#define ADC_DAT_DATAVALID_MASK (0x80000000U)
621#define ADC_DAT_DATAVALID_SHIFT (31U)
622/*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is
623 * cleared whenever this register is read or when the data related to this channel is read from
624 * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in
625 * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in
626 * the data registers associated with any of the channels that are shared between the two
627 * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
628 */
629#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
630/*! @} */
631
632/* The count of ADC_DAT */
633#define ADC_DAT_COUNT (12U)
634
635/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
636/*! @{ */
637#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U)
638#define ADC_THR0_LOW_THRLOW_SHIFT (4U)
639/*! THRLOW - Low threshold value against which ADC results will be compared
640 */
641#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
642/*! @} */
643
644/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
645/*! @{ */
646#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U)
647#define ADC_THR1_LOW_THRLOW_SHIFT (4U)
648/*! THRLOW - Low threshold value against which ADC results will be compared
649 */
650#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
651/*! @} */
652
653/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
654/*! @{ */
655#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U)
656#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U)
657/*! THRHIGH - High threshold value against which ADC results will be compared
658 */
659#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
660/*! @} */
661
662/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
663/*! @{ */
664#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U)
665#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U)
666/*! THRHIGH - High threshold value against which ADC results will be compared
667 */
668#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
669/*! @} */
670
671/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
672/*! @{ */
673#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U)
674#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U)
675/*! CH0_THRSEL - Threshold select for channel 0.
676 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
677 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
678 */
679#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
680#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U)
681#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U)
682/*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0.
683 */
684#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
685#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U)
686#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U)
687/*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0.
688 */
689#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
690#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U)
691#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U)
692/*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0.
693 */
694#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
695#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U)
696#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U)
697/*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0.
698 */
699#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
700#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U)
701#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U)
702/*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0.
703 */
704#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
705#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U)
706#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U)
707/*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0.
708 */
709#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
710#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U)
711#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U)
712/*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0.
713 */
714#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
715#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U)
716#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U)
717/*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0.
718 */
719#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
720#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U)
721#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U)
722/*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0.
723 */
724#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
725#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U)
726#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U)
727/*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0.
728 */
729#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
730#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U)
731#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U)
732/*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0.
733 */
734#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
735/*! @} */
736
737/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
738/*! @{ */
739#define ADC_INTEN_SEQA_INTEN_MASK (0x1U)
740#define ADC_INTEN_SEQA_INTEN_SHIFT (0U)
741/*! SEQA_INTEN - Sequence A interrupt enable.
742 * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled.
743 * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of
744 * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of
745 * conversions, depending on the MODE bit in the SEQA_CTRL register.
746 */
747#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
748#define ADC_INTEN_SEQB_INTEN_MASK (0x2U)
749#define ADC_INTEN_SEQB_INTEN_SHIFT (1U)
750/*! SEQB_INTEN - Sequence B interrupt enable.
751 * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled.
752 * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of
753 * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of
754 * conversions, depending on the MODE bit in the SEQB_CTRL register.
755 */
756#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
757#define ADC_INTEN_OVR_INTEN_MASK (0x4U)
758#define ADC_INTEN_OVR_INTEN_SHIFT (2U)
759/*! OVR_INTEN - Overrun interrupt enable.
760 * 0b0..Disabled. The overrun interrupt is disabled.
761 * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel
762 * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular
763 * sequence is 0, then an overrun in the global data register for that sequence will also cause this
764 * interrupt/DMA trigger to be asserted.
765 */
766#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
767#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U)
768#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U)
769/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0.
770 * 0b00..Disabled.
771 * 0b01..Outside threshold.
772 * 0b10..Crossing threshold.
773 * 0b11..Reserved
774 */
775#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
776#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U)
777#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U)
778/*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0.
779 */
780#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
781#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U)
782#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U)
783/*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0.
784 */
785#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
786#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U)
787#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U)
788/*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0.
789 */
790#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
791#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U)
792#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U)
793/*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0.
794 */
795#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
796#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U)
797#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U)
798/*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0.
799 */
800#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
801#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U)
802#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U)
803/*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0.
804 */
805#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
806#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U)
807#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U)
808/*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0.
809 */
810#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
811#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U)
812#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U)
813/*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0.
814 */
815#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
816#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U)
817#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U)
818/*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0.
819 */
820#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
821#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U)
822#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U)
823/*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0.
824 */
825#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
826#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U)
827#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U)
828/*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0.
829 */
830#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
831/*! @} */
832
833/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
834/*! @{ */
835#define ADC_FLAGS_THCMP0_MASK (0x1U)
836#define ADC_FLAGS_THCMP0_SHIFT (0U)
837/*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or
838 * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by
839 * writing a 1.
840 */
841#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
842#define ADC_FLAGS_THCMP1_MASK (0x2U)
843#define ADC_FLAGS_THCMP1_SHIFT (1U)
844/*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0.
845 */
846#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
847#define ADC_FLAGS_THCMP2_MASK (0x4U)
848#define ADC_FLAGS_THCMP2_SHIFT (2U)
849/*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0.
850 */
851#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
852#define ADC_FLAGS_THCMP3_MASK (0x8U)
853#define ADC_FLAGS_THCMP3_SHIFT (3U)
854/*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0.
855 */
856#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
857#define ADC_FLAGS_THCMP4_MASK (0x10U)
858#define ADC_FLAGS_THCMP4_SHIFT (4U)
859/*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0.
860 */
861#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
862#define ADC_FLAGS_THCMP5_MASK (0x20U)
863#define ADC_FLAGS_THCMP5_SHIFT (5U)
864/*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0.
865 */
866#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
867#define ADC_FLAGS_THCMP6_MASK (0x40U)
868#define ADC_FLAGS_THCMP6_SHIFT (6U)
869/*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0.
870 */
871#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
872#define ADC_FLAGS_THCMP7_MASK (0x80U)
873#define ADC_FLAGS_THCMP7_SHIFT (7U)
874/*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0.
875 */
876#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
877#define ADC_FLAGS_THCMP8_MASK (0x100U)
878#define ADC_FLAGS_THCMP8_SHIFT (8U)
879/*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0.
880 */
881#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
882#define ADC_FLAGS_THCMP9_MASK (0x200U)
883#define ADC_FLAGS_THCMP9_SHIFT (9U)
884/*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0.
885 */
886#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
887#define ADC_FLAGS_THCMP10_MASK (0x400U)
888#define ADC_FLAGS_THCMP10_SHIFT (10U)
889/*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0.
890 */
891#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
892#define ADC_FLAGS_THCMP11_MASK (0x800U)
893#define ADC_FLAGS_THCMP11_SHIFT (11U)
894/*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0.
895 */
896#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
897#define ADC_FLAGS_OVERRUN0_MASK (0x1000U)
898#define ADC_FLAGS_OVERRUN0_SHIFT (12U)
899/*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0
900 */
901#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
902#define ADC_FLAGS_OVERRUN1_MASK (0x2000U)
903#define ADC_FLAGS_OVERRUN1_SHIFT (13U)
904/*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1
905 */
906#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
907#define ADC_FLAGS_OVERRUN2_MASK (0x4000U)
908#define ADC_FLAGS_OVERRUN2_SHIFT (14U)
909/*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2
910 */
911#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
912#define ADC_FLAGS_OVERRUN3_MASK (0x8000U)
913#define ADC_FLAGS_OVERRUN3_SHIFT (15U)
914/*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3
915 */
916#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
917#define ADC_FLAGS_OVERRUN4_MASK (0x10000U)
918#define ADC_FLAGS_OVERRUN4_SHIFT (16U)
919/*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4
920 */
921#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
922#define ADC_FLAGS_OVERRUN5_MASK (0x20000U)
923#define ADC_FLAGS_OVERRUN5_SHIFT (17U)
924/*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5
925 */
926#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
927#define ADC_FLAGS_OVERRUN6_MASK (0x40000U)
928#define ADC_FLAGS_OVERRUN6_SHIFT (18U)
929/*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6
930 */
931#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
932#define ADC_FLAGS_OVERRUN7_MASK (0x80000U)
933#define ADC_FLAGS_OVERRUN7_SHIFT (19U)
934/*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7
935 */
936#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
937#define ADC_FLAGS_OVERRUN8_MASK (0x100000U)
938#define ADC_FLAGS_OVERRUN8_SHIFT (20U)
939/*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8
940 */
941#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
942#define ADC_FLAGS_OVERRUN9_MASK (0x200000U)
943#define ADC_FLAGS_OVERRUN9_SHIFT (21U)
944/*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9
945 */
946#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
947#define ADC_FLAGS_OVERRUN10_MASK (0x400000U)
948#define ADC_FLAGS_OVERRUN10_SHIFT (22U)
949/*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10
950 */
951#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
952#define ADC_FLAGS_OVERRUN11_MASK (0x800000U)
953#define ADC_FLAGS_OVERRUN11_SHIFT (23U)
954/*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11
955 */
956#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
957#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U)
958#define ADC_FLAGS_SEQA_OVR_SHIFT (24U)
959/*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register
960 */
961#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
962#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U)
963#define ADC_FLAGS_SEQB_OVR_SHIFT (25U)
964/*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register
965 */
966#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
967#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U)
968#define ADC_FLAGS_SEQA_INT_SHIFT (28U)
969/*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0,
970 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which
971 * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared
972 * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register
973 * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be
974 * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN
975 * register.
976 */
977#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
978#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U)
979#define ADC_FLAGS_SEQB_INT_SHIFT (29U)
980/*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0,
981 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which
982 * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared
983 * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register
984 * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be
985 * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN
986 * register.
987 */
988#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
989#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U)
990#define ADC_FLAGS_THCMP_INT_SHIFT (30U)
991/*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in
992 * the lower bits of this register are set to 1 (due to an enabled out-of-range or
993 * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be
994 * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared
995 * when all of the individual threshold flags are cleared via writing 1s to those bits.
996 */
997#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
998#define ADC_FLAGS_OVR_INT_MASK (0x80000000U)
999#define ADC_FLAGS_OVR_INT_SHIFT (31U)
1000/*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data
1001 * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers
1002 * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this
1003 * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all
1004 * of the individual overrun bits have been cleared via reading the corresponding data registers.
1005 */
1006#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
1007/*! @} */
1008
1009/*! @name STARTUP - ADC Startup register. */
1010/*! @{ */
1011#define ADC_STARTUP_ADC_ENA_MASK (0x1U)
1012#define ADC_STARTUP_ADC_ENA_SHIFT (0U)
1013/*! ADC_ENA - ADC Enable bit. This bit can only be set to a 1 by software. It is cleared
1014 * automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds
1015 * after the ADC is powered up (typically by altering a system-level ADC power control bit).
1016 */
1017#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
1018#define ADC_STARTUP_ADC_INIT_MASK (0x2U)
1019#define ADC_STARTUP_ADC_INIT_SHIFT (1U)
1020/*! ADC_INIT - ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine
1021 * will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not
1022 * calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is
1023 * required if a calibration is not performed. It will also reload the stored calibration value from
1024 * a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the
1025 * ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or
1026 * an ADC dummy conversion cycle is required. It should not be set during the same write that
1027 * sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically
1028 * when the 'dummy' conversion cycle completes.
1029 */
1030#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
1031/*! @} */
1032
1033/*! @name CALIB - ADC Calibration register. */
1034/*! @{ */
1035#define ADC_CALIB_CALIB_MASK (0x1U)
1036#define ADC_CALIB_CALIB_SHIFT (0U)
1037/*! CALIB - Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can
1038 * only be set to a '1' by software. It is cleared automatically when the calibration cycle
1039 * completes.
1040 */
1041#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
1042#define ADC_CALIB_CALREQD_MASK (0x2U)
1043#define ADC_CALIB_CALREQD_SHIFT (1U)
1044/*! CALREQD - Calibration required. This read-only bit indicates if calibration is required when
1045 * enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was
1046 * powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to
1047 * determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP
1048 * register) to launch the ADC initialization process which includes a 'dummy' conversion cycle.
1049 * Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks
1050 * required for calibration.
1051 */
1052#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
1053#define ADC_CALIB_CALVALUE_MASK (0x1FCU)
1054#define ADC_CALIB_CALVALUE_SHIFT (2U)
1055/*! CALVALUE - Calibration Value. This read-only field displays the calibration value established
1056 * during last calibration cycle. This value is not typically of any use to the user.
1057 */
1058#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
1059/*! @} */
1060
1061
1062/*!
1063 * @}
1064 */ /* end of group ADC_Register_Masks */
1065
1066
1067/* ADC - Peripheral instance base addresses */
1068/** Peripheral ADC0 base address */
1069#define ADC0_BASE (0x400A0000u)
1070/** Peripheral ADC0 base pointer */
1071#define ADC0 ((ADC_Type *)ADC0_BASE)
1072/** Array initializer of ADC peripheral base addresses */
1073#define ADC_BASE_ADDRS { ADC0_BASE }
1074/** Array initializer of ADC peripheral base pointers */
1075#define ADC_BASE_PTRS { ADC0 }
1076/** Interrupt vectors for the ADC peripheral type */
1077#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
1078#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn }
1079
1080/*!
1081 * @}
1082 */ /* end of group ADC_Peripheral_Access_Layer */
1083
1084
1085/* ----------------------------------------------------------------------------
1086 -- ASYNC_SYSCON Peripheral Access Layer
1087 ---------------------------------------------------------------------------- */
1088
1089/*!
1090 * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
1091 * @{
1092 */
1093
1094/** ASYNC_SYSCON - Register Layout Typedef */
1095typedef struct {
1096 __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */
1097 __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
1098 __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
1099 uint8_t RESERVED_0[4];
1100 __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */
1101 __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
1102 __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
1103 uint8_t RESERVED_1[4];
1104 __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */
1105} ASYNC_SYSCON_Type;
1106
1107/* ----------------------------------------------------------------------------
1108 -- ASYNC_SYSCON Register Masks
1109 ---------------------------------------------------------------------------- */
1110
1111/*!
1112 * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
1113 * @{
1114 */
1115
1116/*! @name ASYNCPRESETCTRL - Async peripheral reset control */
1117/*! @{ */
1118#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
1119#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
1120/*! CTIMER3 - Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
1121 */
1122#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
1123#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
1124#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
1125/*! CTIMER4 - Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
1126 */
1127#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
1128/*! @} */
1129
1130/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
1131/*! @{ */
1132#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
1133#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
1134/*! ARST_SET - Writing ones to this register sets the corresponding bit or bits in the
1135 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1136 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1137 */
1138#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
1139/*! @} */
1140
1141/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
1142/*! @{ */
1143#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
1144#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
1145/*! ARST_CLR - Writing ones to this register clears the corresponding bit or bits in the
1146 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1147 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1148 */
1149#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
1150/*! @} */
1151
1152/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
1153/*! @{ */
1154#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
1155#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
1156/*! CTIMER3 - Controls the clock for CTIMER3. 0 = Disable; 1 = Enable.
1157 */
1158#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
1159#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
1160#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
1161/*! CTIMER4 - Controls the clock for CTIMER4. 0 = Disable; 1 = Enable.
1162 */
1163#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
1164/*! @} */
1165
1166/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
1167/*! @{ */
1168#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
1169#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
1170/*! ACLK_SET - Writing ones to this register sets the corresponding bit or bits in the
1171 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1172 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1173 */
1174#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
1175/*! @} */
1176
1177/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
1178/*! @{ */
1179#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
1180#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
1181/*! ACLK_CLR - Writing ones to this register clears the corresponding bit or bits in the
1182 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1183 * ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them.
1184 */
1185#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
1186/*! @} */
1187
1188/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
1189/*! @{ */
1190#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U)
1191#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U)
1192/*! SEL - Clock source for asynchronous clock source selector A
1193 * 0b00..Main clock (main_clk)
1194 * 0b01..FRO 12 MHz (fro_12m)
1195 * 0b10..Audio PLL clock.(AUDPLL_BYPASS)
1196 * 0b11..fc6 fclk (fc6_fclk)
1197 */
1198#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
1199/*! @} */
1200
1201
1202/*!
1203 * @}
1204 */ /* end of group ASYNC_SYSCON_Register_Masks */
1205
1206
1207/* ASYNC_SYSCON - Peripheral instance base addresses */
1208/** Peripheral ASYNC_SYSCON base address */
1209#define ASYNC_SYSCON_BASE (0x40040000u)
1210/** Peripheral ASYNC_SYSCON base pointer */
1211#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
1212/** Array initializer of ASYNC_SYSCON peripheral base addresses */
1213#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE }
1214/** Array initializer of ASYNC_SYSCON peripheral base pointers */
1215#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON }
1216
1217/*!
1218 * @}
1219 */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
1220
1221
1222/* ----------------------------------------------------------------------------
1223 -- CAN Peripheral Access Layer
1224 ---------------------------------------------------------------------------- */
1225
1226/*!
1227 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
1228 * @{
1229 */
1230
1231/** CAN - Register Layout Typedef */
1232typedef struct {
1233 uint8_t RESERVED_0[12];
1234 __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */
1235 __IO uint32_t TEST; /**< Test Register, offset: 0x10 */
1236 uint8_t RESERVED_1[4];
1237 __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */
1238 __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */
1239 __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */
1240 __I uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */
1241 __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */
1242 __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */
1243 uint8_t RESERVED_2[16];
1244 __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */
1245 __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */
1246 __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */
1247 uint8_t RESERVED_3[4];
1248 __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */
1249 __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */
1250 __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */
1251 __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */
1252 uint8_t RESERVED_4[32];
1253 __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */
1254 __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */
1255 __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */
1256 uint8_t RESERVED_5[4];
1257 __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */
1258 __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */
1259 __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */
1260 __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */
1261 __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */
1262 __I uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */
1263 __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */
1264 __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */
1265 __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */
1266 __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */
1267 __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */
1268 __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */
1269 __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */
1270 __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */
1271 __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */
1272 __I uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */
1273 __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */
1274 __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */
1275 __I uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */
1276 __I uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */
1277 __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */
1278 __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */
1279 uint8_t RESERVED_6[8];
1280 __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */
1281 __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */
1282 __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */
1283 uint8_t RESERVED_7[260];
1284 __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */
1285 uint8_t RESERVED_8[508];
1286 __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */
1287 uint8_t RESERVED_9[508];
1288 __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */
1289} CAN_Type;
1290
1291/* ----------------------------------------------------------------------------
1292 -- CAN Register Masks
1293 ---------------------------------------------------------------------------- */
1294
1295/*!
1296 * @addtogroup CAN_Register_Masks CAN Register Masks
1297 * @{
1298 */
1299
1300/*! @name DBTP - Data Bit Timing Prescaler Register */
1301/*! @{ */
1302#define CAN_DBTP_DSJW_MASK (0xFU)
1303#define CAN_DBTP_DSJW_SHIFT (0U)
1304/*! DSJW - Data (re)synchronization jump width.
1305 */
1306#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK)
1307#define CAN_DBTP_DTSEG2_MASK (0xF0U)
1308#define CAN_DBTP_DTSEG2_SHIFT (4U)
1309/*! DTSEG2 - Data time segment after sample point.
1310 */
1311#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK)
1312#define CAN_DBTP_DTSEG1_MASK (0x1F00U)
1313#define CAN_DBTP_DTSEG1_SHIFT (8U)
1314/*! DTSEG1 - Data time segment before sample point.
1315 */
1316#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK)
1317#define CAN_DBTP_DBRP_MASK (0x1F0000U)
1318#define CAN_DBTP_DBRP_SHIFT (16U)
1319/*! DBRP - Data bit rate prescaler.
1320 */
1321#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK)
1322#define CAN_DBTP_TDC_MASK (0x800000U)
1323#define CAN_DBTP_TDC_SHIFT (23U)
1324/*! TDC - Transmitter delay compensation.
1325 */
1326#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK)
1327/*! @} */
1328
1329/*! @name TEST - Test Register */
1330/*! @{ */
1331#define CAN_TEST_LBCK_MASK (0x10U)
1332#define CAN_TEST_LBCK_SHIFT (4U)
1333/*! LBCK - Loop back mode.
1334 */
1335#define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)
1336#define CAN_TEST_TX_MASK (0x60U)
1337#define CAN_TEST_TX_SHIFT (5U)
1338/*! TX - Control of transmit pin.
1339 */
1340#define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)
1341#define CAN_TEST_RX_MASK (0x80U)
1342#define CAN_TEST_RX_SHIFT (7U)
1343/*! RX - Monitors the actual value of the CAN_RXD.
1344 */
1345#define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)
1346/*! @} */
1347
1348/*! @name CCCR - CC Control Register */
1349/*! @{ */
1350#define CAN_CCCR_INIT_MASK (0x1U)
1351#define CAN_CCCR_INIT_SHIFT (0U)
1352/*! INIT - Initialization.
1353 */
1354#define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)
1355#define CAN_CCCR_CCE_MASK (0x2U)
1356#define CAN_CCCR_CCE_SHIFT (1U)
1357/*! CCE - Configuration change enable.
1358 */
1359#define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)
1360#define CAN_CCCR_ASM_MASK (0x4U)
1361#define CAN_CCCR_ASM_SHIFT (2U)
1362/*! ASM - Restricted operational mode.
1363 */
1364#define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)
1365#define CAN_CCCR_CSA_MASK (0x8U)
1366#define CAN_CCCR_CSA_SHIFT (3U)
1367/*! CSA - Clock Stop Acknowledge.
1368 */
1369#define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)
1370#define CAN_CCCR_CSR_MASK (0x10U)
1371#define CAN_CCCR_CSR_SHIFT (4U)
1372/*! CSR - Clock Stop Request.
1373 */
1374#define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)
1375#define CAN_CCCR_MON_MASK (0x20U)
1376#define CAN_CCCR_MON_SHIFT (5U)
1377/*! MON - Bus monitoring mode.
1378 */
1379#define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)
1380#define CAN_CCCR_DAR_MASK (0x40U)
1381#define CAN_CCCR_DAR_SHIFT (6U)
1382/*! DAR - Disable automatic retransmission.
1383 */
1384#define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)
1385#define CAN_CCCR_TEST_MASK (0x80U)
1386#define CAN_CCCR_TEST_SHIFT (7U)
1387/*! TEST - Test mode enable.
1388 */
1389#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
1390#define CAN_CCCR_FDOE_MASK (0x100U)
1391#define CAN_CCCR_FDOE_SHIFT (8U)
1392/*! FDOE - CAN FD operation enable.
1393 */
1394#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK)
1395#define CAN_CCCR_BRSE_MASK (0x200U)
1396#define CAN_CCCR_BRSE_SHIFT (9U)
1397/*! BRSE - When CAN FD operation is disabled, this bit is not evaluated.
1398 */
1399#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK)
1400#define CAN_CCCR_PXHD_MASK (0x1000U)
1401#define CAN_CCCR_PXHD_SHIFT (12U)
1402/*! PXHD - Protocol exception handling disable.
1403 */
1404#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
1405#define CAN_CCCR_EFBI_MASK (0x2000U)
1406#define CAN_CCCR_EFBI_SHIFT (13U)
1407/*! EFBI - Edge filtering during bus integration.
1408 */
1409#define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)
1410#define CAN_CCCR_TXP_MASK (0x4000U)
1411#define CAN_CCCR_TXP_SHIFT (14U)
1412/*! TXP - Transmit pause.
1413 */
1414#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
1415#define CAN_CCCR_NISO_MASK (0x8000U)
1416#define CAN_CCCR_NISO_SHIFT (15U)
1417/*! NISO - Non ISO operation.
1418 */
1419#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK)
1420/*! @} */
1421
1422/*! @name NBTP - Nominal Bit Timing and Prescaler Register */
1423/*! @{ */
1424#define CAN_NBTP_NTSEG2_MASK (0x7FU)
1425#define CAN_NBTP_NTSEG2_SHIFT (0U)
1426/*! NTSEG2 - Nominal time segment after sample point.
1427 */
1428#define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)
1429#define CAN_NBTP_NTSEG1_MASK (0xFF00U)
1430#define CAN_NBTP_NTSEG1_SHIFT (8U)
1431/*! NTSEG1 - Nominal time segment before sample point.
1432 */
1433#define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)
1434#define CAN_NBTP_NBRP_MASK (0x1FF0000U)
1435#define CAN_NBTP_NBRP_SHIFT (16U)
1436/*! NBRP - Nominal bit rate prescaler.
1437 */
1438#define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)
1439#define CAN_NBTP_NSJW_MASK (0xFE000000U)
1440#define CAN_NBTP_NSJW_SHIFT (25U)
1441/*! NSJW - Nominal (re)synchronization jump width.
1442 */
1443#define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)
1444/*! @} */
1445
1446/*! @name TSCC - Timestamp Counter Configuration */
1447/*! @{ */
1448#define CAN_TSCC_TSS_MASK (0x3U)
1449#define CAN_TSCC_TSS_SHIFT (0U)
1450/*! TSS - Timestamp select.
1451 */
1452#define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)
1453#define CAN_TSCC_TCP_MASK (0xF0000U)
1454#define CAN_TSCC_TCP_SHIFT (16U)
1455/*! TCP - Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times.
1456 */
1457#define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)
1458/*! @} */
1459
1460/*! @name TSCV - Timestamp Counter Value */
1461/*! @{ */
1462#define CAN_TSCV_TSC_MASK (0xFFFFU)
1463#define CAN_TSCV_TSC_SHIFT (0U)
1464/*! TSC - Timestamp counter.
1465 */
1466#define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)
1467/*! @} */
1468
1469/*! @name TOCC - Timeout Counter Configuration */
1470/*! @{ */
1471#define CAN_TOCC_ETOC_MASK (0x1U)
1472#define CAN_TOCC_ETOC_SHIFT (0U)
1473/*! ETOC - Enable timeout counter.
1474 */
1475#define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)
1476#define CAN_TOCC_TOS_MASK (0x6U)
1477#define CAN_TOCC_TOS_SHIFT (1U)
1478/*! TOS - Timeout select.
1479 */
1480#define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)
1481#define CAN_TOCC_TOP_MASK (0xFFFF0000U)
1482#define CAN_TOCC_TOP_SHIFT (16U)
1483/*! TOP - Timeout period.
1484 */
1485#define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)
1486/*! @} */
1487
1488/*! @name TOCV - Timeout Counter Value */
1489/*! @{ */
1490#define CAN_TOCV_TOC_MASK (0xFFFFU)
1491#define CAN_TOCV_TOC_SHIFT (0U)
1492/*! TOC - Timeout counter.
1493 */
1494#define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)
1495/*! @} */
1496
1497/*! @name ECR - Error Counter Register */
1498/*! @{ */
1499#define CAN_ECR_TEC_MASK (0xFFU)
1500#define CAN_ECR_TEC_SHIFT (0U)
1501/*! TEC - Transmit error counter.
1502 */
1503#define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)
1504#define CAN_ECR_REC_MASK (0x7F00U)
1505#define CAN_ECR_REC_SHIFT (8U)
1506/*! REC - Receive error counter.
1507 */
1508#define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)
1509#define CAN_ECR_RP_MASK (0x8000U)
1510#define CAN_ECR_RP_SHIFT (15U)
1511/*! RP - Receive error passive.
1512 */
1513#define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)
1514#define CAN_ECR_CEL_MASK (0xFF0000U)
1515#define CAN_ECR_CEL_SHIFT (16U)
1516/*! CEL - CAN error logging.
1517 */
1518#define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)
1519/*! @} */
1520
1521/*! @name PSR - Protocol Status Register */
1522/*! @{ */
1523#define CAN_PSR_LEC_MASK (0x7U)
1524#define CAN_PSR_LEC_SHIFT (0U)
1525/*! LEC - Last error code.
1526 */
1527#define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)
1528#define CAN_PSR_ACT_MASK (0x18U)
1529#define CAN_PSR_ACT_SHIFT (3U)
1530/*! ACT - Activity.
1531 */
1532#define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)
1533#define CAN_PSR_EP_MASK (0x20U)
1534#define CAN_PSR_EP_SHIFT (5U)
1535/*! EP - Error Passive.
1536 */
1537#define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)
1538#define CAN_PSR_EW_MASK (0x40U)
1539#define CAN_PSR_EW_SHIFT (6U)
1540/*! EW - Warning status.
1541 */
1542#define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)
1543#define CAN_PSR_BO_MASK (0x80U)
1544#define CAN_PSR_BO_SHIFT (7U)
1545/*! BO - Bus Off Status.
1546 */
1547#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
1548#define CAN_PSR_DLEC_MASK (0x700U)
1549#define CAN_PSR_DLEC_SHIFT (8U)
1550/*! DLEC - Data phase last error code.
1551 */
1552#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK)
1553#define CAN_PSR_RESI_MASK (0x800U)
1554#define CAN_PSR_RESI_SHIFT (11U)
1555/*! RESI - ESI flag of the last received CAN FD message.
1556 */
1557#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK)
1558#define CAN_PSR_RBRS_MASK (0x1000U)
1559#define CAN_PSR_RBRS_SHIFT (12U)
1560/*! RBRS - BRS flag of last received CAN FD message.
1561 */
1562#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK)
1563#define CAN_PSR_RFDF_MASK (0x2000U)
1564#define CAN_PSR_RFDF_SHIFT (13U)
1565/*! RFDF - Received a CAN FD message.
1566 */
1567#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK)
1568#define CAN_PSR_PXE_MASK (0x4000U)
1569#define CAN_PSR_PXE_SHIFT (14U)
1570/*! PXE - Protocol exception event.
1571 */
1572#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
1573#define CAN_PSR_TDCV_MASK (0x7F0000U)
1574#define CAN_PSR_TDCV_SHIFT (16U)
1575/*! TDCV - Transmitter delay compensation value.
1576 */
1577#define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)
1578/*! @} */
1579
1580/*! @name TDCR - Transmitter Delay Compensator Register */
1581/*! @{ */
1582#define CAN_TDCR_TDCF_MASK (0x7FU)
1583#define CAN_TDCR_TDCF_SHIFT (0U)
1584/*! TDCF - Transmitter delay compensation filter window length.
1585 */
1586#define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)
1587#define CAN_TDCR_TDCO_MASK (0x7F00U)
1588#define CAN_TDCR_TDCO_SHIFT (8U)
1589/*! TDCO - Transmitter delay compensation offset.
1590 */
1591#define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)
1592/*! @} */
1593
1594/*! @name IR - Interrupt Register */
1595/*! @{ */
1596#define CAN_IR_RF0N_MASK (0x1U)
1597#define CAN_IR_RF0N_SHIFT (0U)
1598/*! RF0N - Rx FIFO 0 new message.
1599 */
1600#define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)
1601#define CAN_IR_RF0W_MASK (0x2U)
1602#define CAN_IR_RF0W_SHIFT (1U)
1603/*! RF0W - Rx FIFO 0 watermark reached.
1604 */
1605#define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)
1606#define CAN_IR_RF0F_MASK (0x4U)
1607#define CAN_IR_RF0F_SHIFT (2U)
1608/*! RF0F - Rx FIFO 0 full.
1609 */
1610#define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)
1611#define CAN_IR_RF0L_MASK (0x8U)
1612#define CAN_IR_RF0L_SHIFT (3U)
1613/*! RF0L - Rx FIFO 0 message lost.
1614 */
1615#define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)
1616#define CAN_IR_RF1N_MASK (0x10U)
1617#define CAN_IR_RF1N_SHIFT (4U)
1618/*! RF1N - Rx FIFO 1 new message.
1619 */
1620#define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)
1621#define CAN_IR_RF1W_MASK (0x20U)
1622#define CAN_IR_RF1W_SHIFT (5U)
1623/*! RF1W - Rx FIFO 1 watermark reached.
1624 */
1625#define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)
1626#define CAN_IR_RF1F_MASK (0x40U)
1627#define CAN_IR_RF1F_SHIFT (6U)
1628/*! RF1F - Rx FIFO 1 full.
1629 */
1630#define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)
1631#define CAN_IR_RF1L_MASK (0x80U)
1632#define CAN_IR_RF1L_SHIFT (7U)
1633/*! RF1L - Rx FIFO 1 message lost.
1634 */
1635#define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)
1636#define CAN_IR_HPM_MASK (0x100U)
1637#define CAN_IR_HPM_SHIFT (8U)
1638/*! HPM - High priority message.
1639 */
1640#define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)
1641#define CAN_IR_TC_MASK (0x200U)
1642#define CAN_IR_TC_SHIFT (9U)
1643/*! TC - Transmission completed.
1644 */
1645#define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)
1646#define CAN_IR_TCF_MASK (0x400U)
1647#define CAN_IR_TCF_SHIFT (10U)
1648/*! TCF - Transmission cancellation finished.
1649 */
1650#define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)
1651#define CAN_IR_TFE_MASK (0x800U)
1652#define CAN_IR_TFE_SHIFT (11U)
1653/*! TFE - Tx FIFO empty.
1654 */
1655#define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)
1656#define CAN_IR_TEFN_MASK (0x1000U)
1657#define CAN_IR_TEFN_SHIFT (12U)
1658/*! TEFN - Tx event FIFO new entry.
1659 */
1660#define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)
1661#define CAN_IR_TEFW_MASK (0x2000U)
1662#define CAN_IR_TEFW_SHIFT (13U)
1663/*! TEFW - Tx event FIFO watermark reached.
1664 */
1665#define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)
1666#define CAN_IR_TEFF_MASK (0x4000U)
1667#define CAN_IR_TEFF_SHIFT (14U)
1668/*! TEFF - Tx event FIFO full.
1669 */
1670#define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)
1671#define CAN_IR_TEFL_MASK (0x8000U)
1672#define CAN_IR_TEFL_SHIFT (15U)
1673/*! TEFL - Tx event FIFO element lost.
1674 */
1675#define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)
1676#define CAN_IR_TSW_MASK (0x10000U)
1677#define CAN_IR_TSW_SHIFT (16U)
1678/*! TSW - Timestamp wraparound.
1679 */
1680#define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)
1681#define CAN_IR_MRAF_MASK (0x20000U)
1682#define CAN_IR_MRAF_SHIFT (17U)
1683/*! MRAF - Message RAM access failure.
1684 */
1685#define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)
1686#define CAN_IR_TOO_MASK (0x40000U)
1687#define CAN_IR_TOO_SHIFT (18U)
1688/*! TOO - Timeout occurred.
1689 */
1690#define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)
1691#define CAN_IR_DRX_MASK (0x80000U)
1692#define CAN_IR_DRX_SHIFT (19U)
1693/*! DRX - Message stored in dedicated Rx buffer.
1694 */
1695#define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)
1696#define CAN_IR_BEC_MASK (0x100000U)
1697#define CAN_IR_BEC_SHIFT (20U)
1698/*! BEC - Bit error corrected.
1699 */
1700#define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)
1701#define CAN_IR_BEU_MASK (0x200000U)
1702#define CAN_IR_BEU_SHIFT (21U)
1703/*! BEU - Bit error uncorrected.
1704 */
1705#define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)
1706#define CAN_IR_ELO_MASK (0x400000U)
1707#define CAN_IR_ELO_SHIFT (22U)
1708/*! ELO - Error logging overflow.
1709 */
1710#define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK)
1711#define CAN_IR_EP_MASK (0x800000U)
1712#define CAN_IR_EP_SHIFT (23U)
1713/*! EP - Error passive.
1714 */
1715#define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK)
1716#define CAN_IR_EW_MASK (0x1000000U)
1717#define CAN_IR_EW_SHIFT (24U)
1718/*! EW - Warning status.
1719 */
1720#define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK)
1721#define CAN_IR_BO_MASK (0x2000000U)
1722#define CAN_IR_BO_SHIFT (25U)
1723/*! BO - Bus_Off Status.
1724 */
1725#define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK)
1726#define CAN_IR_WDI_MASK (0x4000000U)
1727#define CAN_IR_WDI_SHIFT (26U)
1728/*! WDI - Watchdog interrupt.
1729 */
1730#define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK)
1731#define CAN_IR_PEA_MASK (0x8000000U)
1732#define CAN_IR_PEA_SHIFT (27U)
1733/*! PEA - Protocol error in arbitration phase.
1734 */
1735#define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK)
1736#define CAN_IR_PED_MASK (0x10000000U)
1737#define CAN_IR_PED_SHIFT (28U)
1738/*! PED - Protocol error in data phase.
1739 */
1740#define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK)
1741#define CAN_IR_ARA_MASK (0x20000000U)
1742#define CAN_IR_ARA_SHIFT (29U)
1743/*! ARA - Access to reserved address.
1744 */
1745#define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK)
1746/*! @} */
1747
1748/*! @name IE - Interrupt Enable */
1749/*! @{ */
1750#define CAN_IE_RF0NE_MASK (0x1U)
1751#define CAN_IE_RF0NE_SHIFT (0U)
1752/*! RF0NE - Rx FIFO 0 new message interrupt enable.
1753 */
1754#define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK)
1755#define CAN_IE_RF0WE_MASK (0x2U)
1756#define CAN_IE_RF0WE_SHIFT (1U)
1757/*! RF0WE - Rx FIFO 0 watermark reached interrupt enable.
1758 */
1759#define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK)
1760#define CAN_IE_RF0FE_MASK (0x4U)
1761#define CAN_IE_RF0FE_SHIFT (2U)
1762/*! RF0FE - Rx FIFO 0 full interrupt enable.
1763 */
1764#define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK)
1765#define CAN_IE_RF0LE_MASK (0x8U)
1766#define CAN_IE_RF0LE_SHIFT (3U)
1767/*! RF0LE - Rx FIFO 0 message lost interrupt enable.
1768 */
1769#define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK)
1770#define CAN_IE_RF1NE_MASK (0x10U)
1771#define CAN_IE_RF1NE_SHIFT (4U)
1772/*! RF1NE - Rx FIFO 1 new message interrupt enable.
1773 */
1774#define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK)
1775#define CAN_IE_RF1WE_MASK (0x20U)
1776#define CAN_IE_RF1WE_SHIFT (5U)
1777/*! RF1WE - Rx FIFO 1 watermark reached interrupt enable.
1778 */
1779#define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK)
1780#define CAN_IE_RF1FE_MASK (0x40U)
1781#define CAN_IE_RF1FE_SHIFT (6U)
1782/*! RF1FE - Rx FIFO 1 full interrupt enable.
1783 */
1784#define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK)
1785#define CAN_IE_RF1LE_MASK (0x80U)
1786#define CAN_IE_RF1LE_SHIFT (7U)
1787/*! RF1LE - Rx FIFO 1 message lost interrupt enable.
1788 */
1789#define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK)
1790#define CAN_IE_HPME_MASK (0x100U)
1791#define CAN_IE_HPME_SHIFT (8U)
1792/*! HPME - High priority message interrupt enable.
1793 */
1794#define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK)
1795#define CAN_IE_TCE_MASK (0x200U)
1796#define CAN_IE_TCE_SHIFT (9U)
1797/*! TCE - Transmission completed interrupt enable.
1798 */
1799#define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK)
1800#define CAN_IE_TCFE_MASK (0x400U)
1801#define CAN_IE_TCFE_SHIFT (10U)
1802/*! TCFE - Transmission cancellation finished interrupt enable.
1803 */
1804#define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK)
1805#define CAN_IE_TFEE_MASK (0x800U)
1806#define CAN_IE_TFEE_SHIFT (11U)
1807/*! TFEE - Tx FIFO empty interrupt enable.
1808 */
1809#define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK)
1810#define CAN_IE_TEFNE_MASK (0x1000U)
1811#define CAN_IE_TEFNE_SHIFT (12U)
1812/*! TEFNE - Tx event FIFO new entry interrupt enable.
1813 */
1814#define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK)
1815#define CAN_IE_TEFWE_MASK (0x2000U)
1816#define CAN_IE_TEFWE_SHIFT (13U)
1817/*! TEFWE - Tx event FIFO watermark reached interrupt enable.
1818 */
1819#define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK)
1820#define CAN_IE_TEFFE_MASK (0x4000U)
1821#define CAN_IE_TEFFE_SHIFT (14U)
1822/*! TEFFE - Tx event FIFO full interrupt enable.
1823 */
1824#define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK)
1825#define CAN_IE_TEFLE_MASK (0x8000U)
1826#define CAN_IE_TEFLE_SHIFT (15U)
1827/*! TEFLE - Tx event FIFO element lost interrupt enable.
1828 */
1829#define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK)
1830#define CAN_IE_TSWE_MASK (0x10000U)
1831#define CAN_IE_TSWE_SHIFT (16U)
1832/*! TSWE - Timestamp wraparound interrupt enable.
1833 */
1834#define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK)
1835#define CAN_IE_MRAFE_MASK (0x20000U)
1836#define CAN_IE_MRAFE_SHIFT (17U)
1837/*! MRAFE - Message RAM access failure interrupt enable.
1838 */
1839#define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK)
1840#define CAN_IE_TOOE_MASK (0x40000U)
1841#define CAN_IE_TOOE_SHIFT (18U)
1842/*! TOOE - Timeout occurred interrupt enable.
1843 */
1844#define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK)
1845#define CAN_IE_DRXE_MASK (0x80000U)
1846#define CAN_IE_DRXE_SHIFT (19U)
1847/*! DRXE - Message stored in dedicated Rx buffer interrupt enable.
1848 */
1849#define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK)
1850#define CAN_IE_BECE_MASK (0x100000U)
1851#define CAN_IE_BECE_SHIFT (20U)
1852/*! BECE - Bit error corrected interrupt enable.
1853 */
1854#define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK)
1855#define CAN_IE_BEUE_MASK (0x200000U)
1856#define CAN_IE_BEUE_SHIFT (21U)
1857/*! BEUE - Bit error uncorrected interrupt enable.
1858 */
1859#define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK)
1860#define CAN_IE_ELOE_MASK (0x400000U)
1861#define CAN_IE_ELOE_SHIFT (22U)
1862/*! ELOE - Error logging overflow interrupt enable.
1863 */
1864#define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK)
1865#define CAN_IE_EPE_MASK (0x800000U)
1866#define CAN_IE_EPE_SHIFT (23U)
1867/*! EPE - Error passive interrupt enable.
1868 */
1869#define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK)
1870#define CAN_IE_EWE_MASK (0x1000000U)
1871#define CAN_IE_EWE_SHIFT (24U)
1872/*! EWE - Warning status interrupt enable.
1873 */
1874#define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK)
1875#define CAN_IE_BOE_MASK (0x2000000U)
1876#define CAN_IE_BOE_SHIFT (25U)
1877/*! BOE - Bus_Off Status interrupt enable.
1878 */
1879#define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK)
1880#define CAN_IE_WDIE_MASK (0x4000000U)
1881#define CAN_IE_WDIE_SHIFT (26U)
1882/*! WDIE - Watchdog interrupt enable.
1883 */
1884#define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK)
1885#define CAN_IE_PEAE_MASK (0x8000000U)
1886#define CAN_IE_PEAE_SHIFT (27U)
1887/*! PEAE - Protocol error in arbitration phase interrupt enable.
1888 */
1889#define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK)
1890#define CAN_IE_PEDE_MASK (0x10000000U)
1891#define CAN_IE_PEDE_SHIFT (28U)
1892/*! PEDE - Protocol error in data phase interrupt enable.
1893 */
1894#define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK)
1895#define CAN_IE_ARAE_MASK (0x20000000U)
1896#define CAN_IE_ARAE_SHIFT (29U)
1897/*! ARAE - Access to reserved address interrupt enable.
1898 */
1899#define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK)
1900/*! @} */
1901
1902/*! @name ILS - Interrupt Line Select */
1903/*! @{ */
1904#define CAN_ILS_RF0NL_MASK (0x1U)
1905#define CAN_ILS_RF0NL_SHIFT (0U)
1906/*! RF0NL - Rx FIFO 0 new message interrupt line.
1907 */
1908#define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK)
1909#define CAN_ILS_RF0WL_MASK (0x2U)
1910#define CAN_ILS_RF0WL_SHIFT (1U)
1911/*! RF0WL - Rx FIFO 0 watermark reached interrupt line.
1912 */
1913#define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK)
1914#define CAN_ILS_RF0FL_MASK (0x4U)
1915#define CAN_ILS_RF0FL_SHIFT (2U)
1916/*! RF0FL - Rx FIFO 0 full interrupt line.
1917 */
1918#define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK)
1919#define CAN_ILS_RF0LL_MASK (0x8U)
1920#define CAN_ILS_RF0LL_SHIFT (3U)
1921/*! RF0LL - Rx FIFO 0 message lost interrupt line.
1922 */
1923#define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK)
1924#define CAN_ILS_RF1NL_MASK (0x10U)
1925#define CAN_ILS_RF1NL_SHIFT (4U)
1926/*! RF1NL - Rx FIFO 1 new message interrupt line.
1927 */
1928#define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK)
1929#define CAN_ILS_RF1WL_MASK (0x20U)
1930#define CAN_ILS_RF1WL_SHIFT (5U)
1931/*! RF1WL - Rx FIFO 1 watermark reached interrupt line.
1932 */
1933#define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK)
1934#define CAN_ILS_RF1FL_MASK (0x40U)
1935#define CAN_ILS_RF1FL_SHIFT (6U)
1936/*! RF1FL - Rx FIFO 1 full interrupt line.
1937 */
1938#define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK)
1939#define CAN_ILS_RF1LL_MASK (0x80U)
1940#define CAN_ILS_RF1LL_SHIFT (7U)
1941/*! RF1LL - Rx FIFO 1 message lost interrupt line.
1942 */
1943#define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK)
1944#define CAN_ILS_HPML_MASK (0x100U)
1945#define CAN_ILS_HPML_SHIFT (8U)
1946/*! HPML - High priority message interrupt line.
1947 */
1948#define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK)
1949#define CAN_ILS_TCL_MASK (0x200U)
1950#define CAN_ILS_TCL_SHIFT (9U)
1951/*! TCL - Transmission completed interrupt line.
1952 */
1953#define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK)
1954#define CAN_ILS_TCFL_MASK (0x400U)
1955#define CAN_ILS_TCFL_SHIFT (10U)
1956/*! TCFL - Transmission cancellation finished interrupt line.
1957 */
1958#define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK)
1959#define CAN_ILS_TFEL_MASK (0x800U)
1960#define CAN_ILS_TFEL_SHIFT (11U)
1961/*! TFEL - Tx FIFO empty interrupt line.
1962 */
1963#define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK)
1964#define CAN_ILS_TEFNL_MASK (0x1000U)
1965#define CAN_ILS_TEFNL_SHIFT (12U)
1966/*! TEFNL - Tx event FIFO new entry interrupt line.
1967 */
1968#define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK)
1969#define CAN_ILS_TEFWL_MASK (0x2000U)
1970#define CAN_ILS_TEFWL_SHIFT (13U)
1971/*! TEFWL - Tx event FIFO watermark reached interrupt line.
1972 */
1973#define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK)
1974#define CAN_ILS_TEFFL_MASK (0x4000U)
1975#define CAN_ILS_TEFFL_SHIFT (14U)
1976/*! TEFFL - Tx event FIFO full interrupt line.
1977 */
1978#define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK)
1979#define CAN_ILS_TEFLL_MASK (0x8000U)
1980#define CAN_ILS_TEFLL_SHIFT (15U)
1981/*! TEFLL - Tx event FIFO element lost interrupt line.
1982 */
1983#define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK)
1984#define CAN_ILS_TSWL_MASK (0x10000U)
1985#define CAN_ILS_TSWL_SHIFT (16U)
1986/*! TSWL - Timestamp wraparound interrupt line.
1987 */
1988#define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK)
1989#define CAN_ILS_MRAFL_MASK (0x20000U)
1990#define CAN_ILS_MRAFL_SHIFT (17U)
1991/*! MRAFL - Message RAM access failure interrupt line.
1992 */
1993#define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK)
1994#define CAN_ILS_TOOL_MASK (0x40000U)
1995#define CAN_ILS_TOOL_SHIFT (18U)
1996/*! TOOL - Timeout occurred interrupt line.
1997 */
1998#define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK)
1999#define CAN_ILS_DRXL_MASK (0x80000U)
2000#define CAN_ILS_DRXL_SHIFT (19U)
2001/*! DRXL - Message stored in dedicated Rx buffer interrupt line.
2002 */
2003#define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK)
2004#define CAN_ILS_BECL_MASK (0x100000U)
2005#define CAN_ILS_BECL_SHIFT (20U)
2006/*! BECL - Bit error corrected interrupt line.
2007 */
2008#define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK)
2009#define CAN_ILS_BEUL_MASK (0x200000U)
2010#define CAN_ILS_BEUL_SHIFT (21U)
2011/*! BEUL - Bit error uncorrected interrupt line.
2012 */
2013#define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK)
2014#define CAN_ILS_ELOL_MASK (0x400000U)
2015#define CAN_ILS_ELOL_SHIFT (22U)
2016/*! ELOL - Error logging overflow interrupt line.
2017 */
2018#define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK)
2019#define CAN_ILS_EPL_MASK (0x800000U)
2020#define CAN_ILS_EPL_SHIFT (23U)
2021/*! EPL - Error passive interrupt line.
2022 */
2023#define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK)
2024#define CAN_ILS_EWL_MASK (0x1000000U)
2025#define CAN_ILS_EWL_SHIFT (24U)
2026/*! EWL - Warning status interrupt line.
2027 */
2028#define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK)
2029#define CAN_ILS_BOL_MASK (0x2000000U)
2030#define CAN_ILS_BOL_SHIFT (25U)
2031/*! BOL - Bus_Off Status interrupt line.
2032 */
2033#define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK)
2034#define CAN_ILS_WDIL_MASK (0x4000000U)
2035#define CAN_ILS_WDIL_SHIFT (26U)
2036/*! WDIL - Watchdog interrupt line.
2037 */
2038#define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK)
2039#define CAN_ILS_PEAL_MASK (0x8000000U)
2040#define CAN_ILS_PEAL_SHIFT (27U)
2041/*! PEAL - Protocol error in arbitration phase interrupt line.
2042 */
2043#define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK)
2044#define CAN_ILS_PEDL_MASK (0x10000000U)
2045#define CAN_ILS_PEDL_SHIFT (28U)
2046/*! PEDL - Protocol error in data phase interrupt line.
2047 */
2048#define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK)
2049#define CAN_ILS_ARAL_MASK (0x20000000U)
2050#define CAN_ILS_ARAL_SHIFT (29U)
2051/*! ARAL - Access to reserved address interrupt line.
2052 */
2053#define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK)
2054/*! @} */
2055
2056/*! @name ILE - Interrupt Line Enable */
2057/*! @{ */
2058#define CAN_ILE_EINT0_MASK (0x1U)
2059#define CAN_ILE_EINT0_SHIFT (0U)
2060/*! EINT0 - Enable interrupt line 0.
2061 */
2062#define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK)
2063#define CAN_ILE_EINT1_MASK (0x2U)
2064#define CAN_ILE_EINT1_SHIFT (1U)
2065/*! EINT1 - Enable interrupt line 1.
2066 */
2067#define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK)
2068/*! @} */
2069
2070/*! @name GFC - Global Filter Configuration */
2071/*! @{ */
2072#define CAN_GFC_RRFE_MASK (0x1U)
2073#define CAN_GFC_RRFE_SHIFT (0U)
2074/*! RRFE - Reject remote frames extended.
2075 */
2076#define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK)
2077#define CAN_GFC_RRFS_MASK (0x2U)
2078#define CAN_GFC_RRFS_SHIFT (1U)
2079/*! RRFS - Reject remote frames standard.
2080 */
2081#define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK)
2082#define CAN_GFC_ANFE_MASK (0xCU)
2083#define CAN_GFC_ANFE_SHIFT (2U)
2084/*! ANFE - Accept non-matching frames extended.
2085 */
2086#define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK)
2087#define CAN_GFC_ANFS_MASK (0x30U)
2088#define CAN_GFC_ANFS_SHIFT (4U)
2089/*! ANFS - Accept non-matching frames standard.
2090 */
2091#define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK)
2092/*! @} */
2093
2094/*! @name SIDFC - Standard ID Filter Configuration */
2095/*! @{ */
2096#define CAN_SIDFC_FLSSA_MASK (0xFFFCU)
2097#define CAN_SIDFC_FLSSA_SHIFT (2U)
2098/*! FLSSA - Filter list standard start address.
2099 */
2100#define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK)
2101#define CAN_SIDFC_LSS_MASK (0xFF0000U)
2102#define CAN_SIDFC_LSS_SHIFT (16U)
2103/*! LSS - List size standard 0 = No standard message ID filter.
2104 */
2105#define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK)
2106/*! @} */
2107
2108/*! @name XIDFC - Extended ID Filter Configuration */
2109/*! @{ */
2110#define CAN_XIDFC_FLESA_MASK (0xFFFCU)
2111#define CAN_XIDFC_FLESA_SHIFT (2U)
2112/*! FLESA - Filter list extended start address.
2113 */
2114#define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK)
2115#define CAN_XIDFC_LSE_MASK (0xFF0000U)
2116#define CAN_XIDFC_LSE_SHIFT (16U)
2117/*! LSE - List size extended 0 = No extended message ID filter.
2118 */
2119#define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK)
2120/*! @} */
2121
2122/*! @name XIDAM - Extended ID AND Mask */
2123/*! @{ */
2124#define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU)
2125#define CAN_XIDAM_EIDM_SHIFT (0U)
2126/*! EIDM - Extended ID mask.
2127 */
2128#define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK)
2129/*! @} */
2130
2131/*! @name HPMS - High Priority Message Status */
2132/*! @{ */
2133#define CAN_HPMS_BIDX_MASK (0x3FU)
2134#define CAN_HPMS_BIDX_SHIFT (0U)
2135/*! BIDX - Buffer index.
2136 */
2137#define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK)
2138#define CAN_HPMS_MSI_MASK (0xC0U)
2139#define CAN_HPMS_MSI_SHIFT (6U)
2140/*! MSI - Message storage indicator.
2141 */
2142#define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK)
2143#define CAN_HPMS_FIDX_MASK (0x7F00U)
2144#define CAN_HPMS_FIDX_SHIFT (8U)
2145/*! FIDX - Filter index.
2146 */
2147#define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK)
2148#define CAN_HPMS_FLST_MASK (0x8000U)
2149#define CAN_HPMS_FLST_SHIFT (15U)
2150/*! FLST - Filter list.
2151 */
2152#define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK)
2153/*! @} */
2154
2155/*! @name NDAT1 - New Data 1 */
2156/*! @{ */
2157#define CAN_NDAT1_ND_MASK (0xFFFFFFFFU)
2158#define CAN_NDAT1_ND_SHIFT (0U)
2159/*! ND - New Data.
2160 */
2161#define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK)
2162/*! @} */
2163
2164/*! @name NDAT2 - New Data 2 */
2165/*! @{ */
2166#define CAN_NDAT2_ND_MASK (0xFFFFFFFFU)
2167#define CAN_NDAT2_ND_SHIFT (0U)
2168/*! ND - New Data.
2169 */
2170#define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK)
2171/*! @} */
2172
2173/*! @name RXF0C - Rx FIFO 0 Configuration */
2174/*! @{ */
2175#define CAN_RXF0C_F0SA_MASK (0xFFFCU)
2176#define CAN_RXF0C_F0SA_SHIFT (2U)
2177/*! F0SA - Rx FIFO 0 start address.
2178 */
2179#define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK)
2180#define CAN_RXF0C_F0S_MASK (0x7F0000U)
2181#define CAN_RXF0C_F0S_SHIFT (16U)
2182/*! F0S - Rx FIFO 0 size.
2183 */
2184#define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK)
2185#define CAN_RXF0C_F0WM_MASK (0x7F000000U)
2186#define CAN_RXF0C_F0WM_SHIFT (24U)
2187/*! F0WM - Rx FIFO 0 watermark 0 = Watermark interrupt disabled.
2188 */
2189#define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK)
2190#define CAN_RXF0C_F0OM_MASK (0x80000000U)
2191#define CAN_RXF0C_F0OM_SHIFT (31U)
2192/*! F0OM - FIFO 0 operation mode.
2193 */
2194#define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK)
2195/*! @} */
2196
2197/*! @name RXF0S - Rx FIFO 0 Status */
2198/*! @{ */
2199#define CAN_RXF0S_F0FL_MASK (0x7FU)
2200#define CAN_RXF0S_F0FL_SHIFT (0U)
2201/*! F0FL - Rx FIFO 0 fill level.
2202 */
2203#define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK)
2204#define CAN_RXF0S_F0GI_MASK (0x3F00U)
2205#define CAN_RXF0S_F0GI_SHIFT (8U)
2206/*! F0GI - Rx FIFO 0 get index.
2207 */
2208#define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK)
2209#define CAN_RXF0S_F0PI_MASK (0x3F0000U)
2210#define CAN_RXF0S_F0PI_SHIFT (16U)
2211/*! F0PI - Rx FIFO 0 put index.
2212 */
2213#define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK)
2214#define CAN_RXF0S_F0F_MASK (0x1000000U)
2215#define CAN_RXF0S_F0F_SHIFT (24U)
2216/*! F0F - Rx FIFO 0 full.
2217 */
2218#define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK)
2219#define CAN_RXF0S_RF0L_MASK (0x2000000U)
2220#define CAN_RXF0S_RF0L_SHIFT (25U)
2221/*! RF0L - Rx FIFO 0 message lost.
2222 */
2223#define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK)
2224/*! @} */
2225
2226/*! @name RXF0A - Rx FIFO 0 Acknowledge */
2227/*! @{ */
2228#define CAN_RXF0A_F0AI_MASK (0x3FU)
2229#define CAN_RXF0A_F0AI_SHIFT (0U)
2230/*! F0AI - Rx FIFO 0 acknowledge index.
2231 */
2232#define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK)
2233/*! @} */
2234
2235/*! @name RXBC - Rx Buffer Configuration */
2236/*! @{ */
2237#define CAN_RXBC_RBSA_MASK (0xFFFCU)
2238#define CAN_RXBC_RBSA_SHIFT (2U)
2239/*! RBSA - Rx buffer start address.
2240 */
2241#define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK)
2242/*! @} */
2243
2244/*! @name RXF1C - Rx FIFO 1 Configuration */
2245/*! @{ */
2246#define CAN_RXF1C_F1SA_MASK (0xFFFCU)
2247#define CAN_RXF1C_F1SA_SHIFT (2U)
2248/*! F1SA - Rx FIFO 1 start address.
2249 */
2250#define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK)
2251#define CAN_RXF1C_F1S_MASK (0x7F0000U)
2252#define CAN_RXF1C_F1S_SHIFT (16U)
2253/*! F1S - Rx FIFO 1 size 0 = No Rx FIFO 1.
2254 */
2255#define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK)
2256#define CAN_RXF1C_F1WM_MASK (0x7F000000U)
2257#define CAN_RXF1C_F1WM_SHIFT (24U)
2258/*! F1WM - Rx FIFO 1 watermark 0 = Watermark interrupt disabled.
2259 */
2260#define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK)
2261#define CAN_RXF1C_F1OM_MASK (0x80000000U)
2262#define CAN_RXF1C_F1OM_SHIFT (31U)
2263/*! F1OM - FIFO 1 operation mode.
2264 */
2265#define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK)
2266/*! @} */
2267
2268/*! @name RXF1S - Rx FIFO 1 Status */
2269/*! @{ */
2270#define CAN_RXF1S_F1FL_MASK (0x7FU)
2271#define CAN_RXF1S_F1FL_SHIFT (0U)
2272/*! F1FL - Rx FIFO 1 fill level.
2273 */
2274#define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK)
2275#define CAN_RXF1S_F1GI_MASK (0x3F00U)
2276#define CAN_RXF1S_F1GI_SHIFT (8U)
2277/*! F1GI - Rx FIFO 1 get index.
2278 */
2279#define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK)
2280#define CAN_RXF1S_F1PI_MASK (0x3F0000U)
2281#define CAN_RXF1S_F1PI_SHIFT (16U)
2282/*! F1PI - Rx FIFO 1 put index.
2283 */
2284#define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK)
2285#define CAN_RXF1S_F1F_MASK (0x1000000U)
2286#define CAN_RXF1S_F1F_SHIFT (24U)
2287/*! F1F - Rx FIFO 1 full.
2288 */
2289#define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK)
2290#define CAN_RXF1S_RF1L_MASK (0x2000000U)
2291#define CAN_RXF1S_RF1L_SHIFT (25U)
2292/*! RF1L - Rx FIFO 1 message lost.
2293 */
2294#define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK)
2295/*! @} */
2296
2297/*! @name RXF1A - Rx FIFO 1 Acknowledge */
2298/*! @{ */
2299#define CAN_RXF1A_F1AI_MASK (0x3FU)
2300#define CAN_RXF1A_F1AI_SHIFT (0U)
2301/*! F1AI - Rx FIFO 1 acknowledge index.
2302 */
2303#define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK)
2304/*! @} */
2305
2306/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */
2307/*! @{ */
2308#define CAN_RXESC_F0DS_MASK (0x7U)
2309#define CAN_RXESC_F0DS_SHIFT (0U)
2310/*! F0DS - Rx FIFO 0 data field size.
2311 */
2312#define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK)
2313#define CAN_RXESC_F1DS_MASK (0x70U)
2314#define CAN_RXESC_F1DS_SHIFT (4U)
2315/*! F1DS - Rx FIFO 1 data field size.
2316 */
2317#define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK)
2318#define CAN_RXESC_RBDS_MASK (0x700U)
2319#define CAN_RXESC_RBDS_SHIFT (8U)
2320/*! RBDS - .
2321 */
2322#define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK)
2323/*! @} */
2324
2325/*! @name TXBC - Tx Buffer Configuration */
2326/*! @{ */
2327#define CAN_TXBC_TBSA_MASK (0xFFFCU)
2328#define CAN_TXBC_TBSA_SHIFT (2U)
2329/*! TBSA - Tx buffers start address.
2330 */
2331#define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK)
2332#define CAN_TXBC_NDTB_MASK (0x3F0000U)
2333#define CAN_TXBC_NDTB_SHIFT (16U)
2334/*! NDTB - Number of dedicated transmit buffers 0 = No dedicated Tx buffers.
2335 */
2336#define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK)
2337#define CAN_TXBC_TFQS_MASK (0x3F000000U)
2338#define CAN_TXBC_TFQS_SHIFT (24U)
2339/*! TFQS - Transmit FIFO/queue size 0 = No tx FIFO/Queue.
2340 */
2341#define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK)
2342#define CAN_TXBC_TFQM_MASK (0x40000000U)
2343#define CAN_TXBC_TFQM_SHIFT (30U)
2344/*! TFQM - Tx FIFO/queue mode.
2345 */
2346#define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK)
2347/*! @} */
2348
2349/*! @name TXFQS - Tx FIFO/Queue Status */
2350/*! @{ */
2351#define CAN_TXFQS_TFGI_MASK (0x1F00U)
2352#define CAN_TXFQS_TFGI_SHIFT (8U)
2353/*! TFGI - Tx FIFO get index.
2354 */
2355#define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK)
2356#define CAN_TXFQS_TFQPI_MASK (0x1F0000U)
2357#define CAN_TXFQS_TFQPI_SHIFT (16U)
2358/*! TFQPI - Tx FIFO/queue put index.
2359 */
2360#define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK)
2361#define CAN_TXFQS_TFQF_MASK (0x200000U)
2362#define CAN_TXFQS_TFQF_SHIFT (21U)
2363/*! TFQF - Tx FIFO/queue full.
2364 */
2365#define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK)
2366/*! @} */
2367
2368/*! @name TXESC - Tx Buffer Element Size Configuration */
2369/*! @{ */
2370#define CAN_TXESC_TBDS_MASK (0x7U)
2371#define CAN_TXESC_TBDS_SHIFT (0U)
2372/*! TBDS - Tx buffer data field size.
2373 */
2374#define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK)
2375/*! @} */
2376
2377/*! @name TXBRP - Tx Buffer Request Pending */
2378/*! @{ */
2379#define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU)
2380#define CAN_TXBRP_TRP_SHIFT (0U)
2381/*! TRP - Transmission request pending.
2382 */
2383#define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK)
2384/*! @} */
2385
2386/*! @name TXBAR - Tx Buffer Add Request */
2387/*! @{ */
2388#define CAN_TXBAR_AR_MASK (0xFFFFFFFFU)
2389#define CAN_TXBAR_AR_SHIFT (0U)
2390/*! AR - Add request.
2391 */
2392#define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK)
2393/*! @} */
2394
2395/*! @name TXBCR - Tx Buffer Cancellation Request */
2396/*! @{ */
2397#define CAN_TXBCR_CR_MASK (0xFFFFFFFFU)
2398#define CAN_TXBCR_CR_SHIFT (0U)
2399/*! CR - Cancellation request.
2400 */
2401#define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK)
2402/*! @} */
2403
2404/*! @name TXBTO - Tx Buffer Transmission Occurred */
2405/*! @{ */
2406#define CAN_TXBTO_TO_MASK (0xFFFFFFFFU)
2407#define CAN_TXBTO_TO_SHIFT (0U)
2408/*! TO - Transmission occurred.
2409 */
2410#define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK)
2411/*! @} */
2412
2413/*! @name TXBCF - Tx Buffer Cancellation Finished */
2414/*! @{ */
2415#define CAN_TXBCF_TO_MASK (0xFFFFFFFFU)
2416#define CAN_TXBCF_TO_SHIFT (0U)
2417/*! TO - Cancellation finished.
2418 */
2419#define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK)
2420/*! @} */
2421
2422/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */
2423/*! @{ */
2424#define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU)
2425#define CAN_TXBTIE_TIE_SHIFT (0U)
2426/*! TIE - Transmission interrupt enable.
2427 */
2428#define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK)
2429/*! @} */
2430
2431/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */
2432/*! @{ */
2433#define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU)
2434#define CAN_TXBCIE_CFIE_SHIFT (0U)
2435/*! CFIE - Cancellation finished interrupt enable.
2436 */
2437#define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK)
2438/*! @} */
2439
2440/*! @name TXEFC - Tx Event FIFO Configuration */
2441/*! @{ */
2442#define CAN_TXEFC_EFSA_MASK (0xFFFCU)
2443#define CAN_TXEFC_EFSA_SHIFT (2U)
2444/*! EFSA - Event FIFO start address.
2445 */
2446#define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK)
2447#define CAN_TXEFC_EFS_MASK (0x3F0000U)
2448#define CAN_TXEFC_EFS_SHIFT (16U)
2449/*! EFS - Event FIFO size 0 = Tx event FIFO disabled.
2450 */
2451#define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK)
2452#define CAN_TXEFC_EFWM_MASK (0x3F000000U)
2453#define CAN_TXEFC_EFWM_SHIFT (24U)
2454/*! EFWM - Event FIFO watermark 0 = Watermark interrupt disabled.
2455 */
2456#define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK)
2457/*! @} */
2458
2459/*! @name TXEFS - Tx Event FIFO Status */
2460/*! @{ */
2461#define CAN_TXEFS_EFFL_MASK (0x3FU)
2462#define CAN_TXEFS_EFFL_SHIFT (0U)
2463/*! EFFL - Event FIFO fill level.
2464 */
2465#define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK)
2466#define CAN_TXEFS_EFGI_MASK (0x1F00U)
2467#define CAN_TXEFS_EFGI_SHIFT (8U)
2468/*! EFGI - Event FIFO get index.
2469 */
2470#define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK)
2471#define CAN_TXEFS_EFPI_MASK (0x3F0000U)
2472#define CAN_TXEFS_EFPI_SHIFT (16U)
2473/*! EFPI - Event FIFO put index.
2474 */
2475#define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK)
2476#define CAN_TXEFS_EFF_MASK (0x1000000U)
2477#define CAN_TXEFS_EFF_SHIFT (24U)
2478/*! EFF - Event FIFO full.
2479 */
2480#define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK)
2481#define CAN_TXEFS_TEFL_MASK (0x2000000U)
2482#define CAN_TXEFS_TEFL_SHIFT (25U)
2483/*! TEFL - Tx event FIFO element lost.
2484 */
2485#define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK)
2486/*! @} */
2487
2488/*! @name TXEFA - Tx Event FIFO Acknowledge */
2489/*! @{ */
2490#define CAN_TXEFA_EFAI_MASK (0x1FU)
2491#define CAN_TXEFA_EFAI_SHIFT (0U)
2492/*! EFAI - Event FIFO acknowledge index.
2493 */
2494#define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK)
2495/*! @} */
2496
2497/*! @name MRBA - CAN Message RAM Base Address */
2498/*! @{ */
2499#define CAN_MRBA_BA_MASK (0xFFFF0000U)
2500#define CAN_MRBA_BA_SHIFT (16U)
2501/*! BA - Base address for the message RAM in the chip memory map.
2502 */
2503#define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK)
2504/*! @} */
2505
2506/*! @name ETSCC - External Timestamp Counter Configuration */
2507/*! @{ */
2508#define CAN_ETSCC_ETCP_MASK (0x7FFU)
2509#define CAN_ETSCC_ETCP_SHIFT (0U)
2510/*! ETCP - External timestamp prescaler value.
2511 */
2512#define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK)
2513#define CAN_ETSCC_ETCE_MASK (0x80000000U)
2514#define CAN_ETSCC_ETCE_SHIFT (31U)
2515/*! ETCE - External timestamp counter enable.
2516 */
2517#define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK)
2518/*! @} */
2519
2520/*! @name ETSCV - External Timestamp Counter Value */
2521/*! @{ */
2522#define CAN_ETSCV_ETSC_MASK (0xFFFFU)
2523#define CAN_ETSCV_ETSC_SHIFT (0U)
2524/*! ETSC - External timestamp counter.
2525 */
2526#define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK)
2527/*! @} */
2528
2529
2530/*!
2531 * @}
2532 */ /* end of group CAN_Register_Masks */
2533
2534
2535/* CAN - Peripheral instance base addresses */
2536/** Peripheral CAN0 base address */
2537#define CAN0_BASE (0x4009D000u)
2538/** Peripheral CAN0 base pointer */
2539#define CAN0 ((CAN_Type *)CAN0_BASE)
2540/** Peripheral CAN1 base address */
2541#define CAN1_BASE (0x4009E000u)
2542/** Peripheral CAN1 base pointer */
2543#define CAN1 ((CAN_Type *)CAN1_BASE)
2544/** Array initializer of CAN peripheral base addresses */
2545#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
2546/** Array initializer of CAN peripheral base pointers */
2547#define CAN_BASE_PTRS { CAN0, CAN1 }
2548/** Interrupt vectors for the CAN peripheral type */
2549#define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } }
2550
2551/*!
2552 * @}
2553 */ /* end of group CAN_Peripheral_Access_Layer */
2554
2555
2556/* ----------------------------------------------------------------------------
2557 -- CRC Peripheral Access Layer
2558 ---------------------------------------------------------------------------- */
2559
2560/*!
2561 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
2562 * @{
2563 */
2564
2565/** CRC - Register Layout Typedef */
2566typedef struct {
2567 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
2568 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
2569 union { /* offset: 0x8 */
2570 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
2571 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
2572 };
2573} CRC_Type;
2574
2575/* ----------------------------------------------------------------------------
2576 -- CRC Register Masks
2577 ---------------------------------------------------------------------------- */
2578
2579/*!
2580 * @addtogroup CRC_Register_Masks CRC Register Masks
2581 * @{
2582 */
2583
2584/*! @name MODE - CRC mode register */
2585/*! @{ */
2586#define CRC_MODE_CRC_POLY_MASK (0x3U)
2587#define CRC_MODE_CRC_POLY_SHIFT (0U)
2588/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
2589 */
2590#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
2591#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
2592#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
2593/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
2594 */
2595#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
2596#define CRC_MODE_CMPL_WR_MASK (0x8U)
2597#define CRC_MODE_CMPL_WR_SHIFT (3U)
2598/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
2599 */
2600#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
2601#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
2602#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
2603/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
2604 */
2605#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
2606#define CRC_MODE_CMPL_SUM_MASK (0x20U)
2607#define CRC_MODE_CMPL_SUM_SHIFT (5U)
2608/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
2609 */
2610#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
2611/*! @} */
2612
2613/*! @name SEED - CRC seed register */
2614/*! @{ */
2615#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
2616#define CRC_SEED_CRC_SEED_SHIFT (0U)
2617/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
2618 * selected bit order and 1's complement pre-processes. A write access to this register will
2619 * overrule the CRC calculation in progresses.
2620 */
2621#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
2622/*! @} */
2623
2624/*! @name SUM - CRC checksum register */
2625/*! @{ */
2626#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
2627#define CRC_SUM_CRC_SUM_SHIFT (0U)
2628/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
2629 */
2630#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
2631/*! @} */
2632
2633/*! @name WR_DATA - CRC data register */
2634/*! @{ */
2635#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
2636#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
2637/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
2638 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
2639 * accept back-to-back transactions.
2640 */
2641#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
2642/*! @} */
2643
2644
2645/*!
2646 * @}
2647 */ /* end of group CRC_Register_Masks */
2648
2649
2650/* CRC - Peripheral instance base addresses */
2651/** Peripheral CRC_ENGINE base address */
2652#define CRC_ENGINE_BASE (0x40095000u)
2653/** Peripheral CRC_ENGINE base pointer */
2654#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
2655/** Array initializer of CRC peripheral base addresses */
2656#define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
2657/** Array initializer of CRC peripheral base pointers */
2658#define CRC_BASE_PTRS { CRC_ENGINE }
2659
2660/*!
2661 * @}
2662 */ /* end of group CRC_Peripheral_Access_Layer */
2663
2664
2665/* ----------------------------------------------------------------------------
2666 -- CTIMER Peripheral Access Layer
2667 ---------------------------------------------------------------------------- */
2668
2669/*!
2670 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
2671 * @{
2672 */
2673
2674/** CTIMER - Register Layout Typedef */
2675typedef struct {
2676 __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
2677 __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
2678 __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */
2679 __IO uint32_t PR; /**< Prescale Register, offset: 0xC */
2680 __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */
2681 __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */
2682 __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
2683 __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
2684 __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
2685 __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
2686 uint8_t RESERVED_0[48];
2687 __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
2688 __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
2689 __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
2690} CTIMER_Type;
2691
2692/* ----------------------------------------------------------------------------
2693 -- CTIMER Register Masks
2694 ---------------------------------------------------------------------------- */
2695
2696/*!
2697 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
2698 * @{
2699 */
2700
2701/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
2702/*! @{ */
2703#define CTIMER_IR_MR0INT_MASK (0x1U)
2704#define CTIMER_IR_MR0INT_SHIFT (0U)
2705/*! MR0INT - Interrupt flag for match channel 0.
2706 */
2707#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
2708#define CTIMER_IR_MR1INT_MASK (0x2U)
2709#define CTIMER_IR_MR1INT_SHIFT (1U)
2710/*! MR1INT - Interrupt flag for match channel 1.
2711 */
2712#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
2713#define CTIMER_IR_MR2INT_MASK (0x4U)
2714#define CTIMER_IR_MR2INT_SHIFT (2U)
2715/*! MR2INT - Interrupt flag for match channel 2.
2716 */
2717#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
2718#define CTIMER_IR_MR3INT_MASK (0x8U)
2719#define CTIMER_IR_MR3INT_SHIFT (3U)
2720/*! MR3INT - Interrupt flag for match channel 3.
2721 */
2722#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
2723#define CTIMER_IR_CR0INT_MASK (0x10U)
2724#define CTIMER_IR_CR0INT_SHIFT (4U)
2725/*! CR0INT - Interrupt flag for capture channel 0 event.
2726 */
2727#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
2728#define CTIMER_IR_CR1INT_MASK (0x20U)
2729#define CTIMER_IR_CR1INT_SHIFT (5U)
2730/*! CR1INT - Interrupt flag for capture channel 1 event.
2731 */
2732#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
2733#define CTIMER_IR_CR2INT_MASK (0x40U)
2734#define CTIMER_IR_CR2INT_SHIFT (6U)
2735/*! CR2INT - Interrupt flag for capture channel 2 event.
2736 */
2737#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
2738#define CTIMER_IR_CR3INT_MASK (0x80U)
2739#define CTIMER_IR_CR3INT_SHIFT (7U)
2740/*! CR3INT - Interrupt flag for capture channel 3 event.
2741 */
2742#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
2743/*! @} */
2744
2745/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
2746/*! @{ */
2747#define CTIMER_TCR_CEN_MASK (0x1U)
2748#define CTIMER_TCR_CEN_SHIFT (0U)
2749/*! CEN - Counter enable.
2750 * 0b0..Disabled.The counters are disabled.
2751 * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
2752 */
2753#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
2754#define CTIMER_TCR_CRST_MASK (0x2U)
2755#define CTIMER_TCR_CRST_SHIFT (1U)
2756/*! CRST - Counter reset.
2757 * 0b0..Disabled. Do nothing.
2758 * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
2759 * the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
2760 */
2761#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
2762/*! @} */
2763
2764/*! @name TC - Timer Counter */
2765/*! @{ */
2766#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
2767#define CTIMER_TC_TCVAL_SHIFT (0U)
2768/*! TCVAL - Timer counter value.
2769 */
2770#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
2771/*! @} */
2772
2773/*! @name PR - Prescale Register */
2774/*! @{ */
2775#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
2776#define CTIMER_PR_PRVAL_SHIFT (0U)
2777/*! PRVAL - Prescale counter value.
2778 */
2779#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
2780/*! @} */
2781
2782/*! @name PC - Prescale Counter */
2783/*! @{ */
2784#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
2785#define CTIMER_PC_PCVAL_SHIFT (0U)
2786/*! PCVAL - Prescale counter value.
2787 */
2788#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
2789/*! @} */
2790
2791/*! @name MCR - Match Control Register */
2792/*! @{ */
2793#define CTIMER_MCR_MR0I_MASK (0x1U)
2794#define CTIMER_MCR_MR0I_SHIFT (0U)
2795/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
2796 */
2797#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
2798#define CTIMER_MCR_MR0R_MASK (0x2U)
2799#define CTIMER_MCR_MR0R_SHIFT (1U)
2800/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it.
2801 */
2802#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
2803#define CTIMER_MCR_MR0S_MASK (0x4U)
2804#define CTIMER_MCR_MR0S_SHIFT (2U)
2805/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
2806 */
2807#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
2808#define CTIMER_MCR_MR1I_MASK (0x8U)
2809#define CTIMER_MCR_MR1I_SHIFT (3U)
2810/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
2811 */
2812#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
2813#define CTIMER_MCR_MR1R_MASK (0x10U)
2814#define CTIMER_MCR_MR1R_SHIFT (4U)
2815/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it.
2816 */
2817#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
2818#define CTIMER_MCR_MR1S_MASK (0x20U)
2819#define CTIMER_MCR_MR1S_SHIFT (5U)
2820/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
2821 */
2822#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
2823#define CTIMER_MCR_MR2I_MASK (0x40U)
2824#define CTIMER_MCR_MR2I_SHIFT (6U)
2825/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
2826 */
2827#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
2828#define CTIMER_MCR_MR2R_MASK (0x80U)
2829#define CTIMER_MCR_MR2R_SHIFT (7U)
2830/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it.
2831 */
2832#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
2833#define CTIMER_MCR_MR2S_MASK (0x100U)
2834#define CTIMER_MCR_MR2S_SHIFT (8U)
2835/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
2836 */
2837#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
2838#define CTIMER_MCR_MR3I_MASK (0x200U)
2839#define CTIMER_MCR_MR3I_SHIFT (9U)
2840/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
2841 */
2842#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
2843#define CTIMER_MCR_MR3R_MASK (0x400U)
2844#define CTIMER_MCR_MR3R_SHIFT (10U)
2845/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it.
2846 */
2847#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
2848#define CTIMER_MCR_MR3S_MASK (0x800U)
2849#define CTIMER_MCR_MR3S_SHIFT (11U)
2850/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
2851 */
2852#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
2853#define CTIMER_MCR_MR0RL_MASK (0x1000000U)
2854#define CTIMER_MCR_MR0RL_SHIFT (24U)
2855/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
2856 * (either via a match event or a write to bit 1 of the TCR).
2857 */
2858#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
2859#define CTIMER_MCR_MR1RL_MASK (0x2000000U)
2860#define CTIMER_MCR_MR1RL_SHIFT (25U)
2861/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
2862 * (either via a match event or a write to bit 1 of the TCR).
2863 */
2864#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
2865#define CTIMER_MCR_MR2RL_MASK (0x4000000U)
2866#define CTIMER_MCR_MR2RL_SHIFT (26U)
2867/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
2868 * (either via a match event or a write to bit 1 of the TCR).
2869 */
2870#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
2871#define CTIMER_MCR_MR3RL_MASK (0x8000000U)
2872#define CTIMER_MCR_MR3RL_SHIFT (27U)
2873/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
2874 * (either via a match event or a write to bit 1 of the TCR).
2875 */
2876#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
2877/*! @} */
2878
2879/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
2880/*! @{ */
2881#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
2882#define CTIMER_MR_MATCH_SHIFT (0U)
2883/*! MATCH - Timer counter match value.
2884 */
2885#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
2886/*! @} */
2887
2888/* The count of CTIMER_MR */
2889#define CTIMER_MR_COUNT (4U)
2890
2891/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
2892/*! @{ */
2893#define CTIMER_CCR_CAP0RE_MASK (0x1U)
2894#define CTIMER_CCR_CAP0RE_SHIFT (0U)
2895/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
2896 * the contents of TC. 0 = disabled. 1 = enabled.
2897 */
2898#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
2899#define CTIMER_CCR_CAP0FE_MASK (0x2U)
2900#define CTIMER_CCR_CAP0FE_SHIFT (1U)
2901/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
2902 * the contents of TC. 0 = disabled. 1 = enabled.
2903 */
2904#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
2905#define CTIMER_CCR_CAP0I_MASK (0x4U)
2906#define CTIMER_CCR_CAP0I_SHIFT (2U)
2907/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
2908 */
2909#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
2910#define CTIMER_CCR_CAP1RE_MASK (0x8U)
2911#define CTIMER_CCR_CAP1RE_SHIFT (3U)
2912/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
2913 * the contents of TC. 0 = disabled. 1 = enabled.
2914 */
2915#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
2916#define CTIMER_CCR_CAP1FE_MASK (0x10U)
2917#define CTIMER_CCR_CAP1FE_SHIFT (4U)
2918/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
2919 * the contents of TC. 0 = disabled. 1 = enabled.
2920 */
2921#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
2922#define CTIMER_CCR_CAP1I_MASK (0x20U)
2923#define CTIMER_CCR_CAP1I_SHIFT (5U)
2924/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
2925 */
2926#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
2927#define CTIMER_CCR_CAP2RE_MASK (0x40U)
2928#define CTIMER_CCR_CAP2RE_SHIFT (6U)
2929/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
2930 * the contents of TC. 0 = disabled. 1 = enabled.
2931 */
2932#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
2933#define CTIMER_CCR_CAP2FE_MASK (0x80U)
2934#define CTIMER_CCR_CAP2FE_SHIFT (7U)
2935/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
2936 * the contents of TC. 0 = disabled. 1 = enabled.
2937 */
2938#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
2939#define CTIMER_CCR_CAP2I_MASK (0x100U)
2940#define CTIMER_CCR_CAP2I_SHIFT (8U)
2941/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
2942 */
2943#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
2944#define CTIMER_CCR_CAP3RE_MASK (0x200U)
2945#define CTIMER_CCR_CAP3RE_SHIFT (9U)
2946/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with
2947 * the contents of TC. 0 = disabled. 1 = enabled.
2948 */
2949#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
2950#define CTIMER_CCR_CAP3FE_MASK (0x400U)
2951#define CTIMER_CCR_CAP3FE_SHIFT (10U)
2952/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with
2953 * the contents of TC. 0 = disabled. 1 = enabled.
2954 */
2955#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
2956#define CTIMER_CCR_CAP3I_MASK (0x800U)
2957#define CTIMER_CCR_CAP3I_SHIFT (11U)
2958/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
2959 */
2960#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
2961/*! @} */
2962
2963/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
2964/*! @{ */
2965#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
2966#define CTIMER_CR_CAP_SHIFT (0U)
2967/*! CAP - Timer counter capture value.
2968 */
2969#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
2970/*! @} */
2971
2972/* The count of CTIMER_CR */
2973#define CTIMER_CR_COUNT (4U)
2974
2975/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
2976/*! @{ */
2977#define CTIMER_EMR_EM0_MASK (0x1U)
2978#define CTIMER_EMR_EM0_SHIFT (0U)
2979/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
2980 * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
2981 * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
2982 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2983 */
2984#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
2985#define CTIMER_EMR_EM1_MASK (0x2U)
2986#define CTIMER_EMR_EM1_SHIFT (1U)
2987/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
2988 * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
2989 * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
2990 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2991 */
2992#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
2993#define CTIMER_EMR_EM2_MASK (0x4U)
2994#define CTIMER_EMR_EM2_SHIFT (2U)
2995/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
2996 * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
2997 * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
2998 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2999 */
3000#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
3001#define CTIMER_EMR_EM3_MASK (0x8U)
3002#define CTIMER_EMR_EM3_SHIFT (3U)
3003/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
3004 * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
3005 * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
3006 * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
3007 */
3008#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
3009#define CTIMER_EMR_EMC0_MASK (0x30U)
3010#define CTIMER_EMR_EMC0_SHIFT (4U)
3011/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
3012 * 0b00..Do Nothing.
3013 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
3014 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
3015 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3016 */
3017#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
3018#define CTIMER_EMR_EMC1_MASK (0xC0U)
3019#define CTIMER_EMR_EMC1_SHIFT (6U)
3020/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
3021 * 0b00..Do Nothing.
3022 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
3023 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
3024 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3025 */
3026#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
3027#define CTIMER_EMR_EMC2_MASK (0x300U)
3028#define CTIMER_EMR_EMC2_SHIFT (8U)
3029/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
3030 * 0b00..Do Nothing.
3031 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
3032 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
3033 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3034 */
3035#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
3036#define CTIMER_EMR_EMC3_MASK (0xC00U)
3037#define CTIMER_EMR_EMC3_SHIFT (10U)
3038/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
3039 * 0b00..Do Nothing.
3040 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
3041 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
3042 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3043 */
3044#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
3045/*! @} */
3046
3047/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
3048/*! @{ */
3049#define CTIMER_CTCR_CTMODE_MASK (0x3U)
3050#define CTIMER_CTCR_CTMODE_SHIFT (0U)
3051/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
3052 * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
3053 * is incremented when the Prescale Counter matches the Prescale Register.
3054 * 0b00..Timer Mode. Incremented every rising APB bus clock edge.
3055 * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
3056 * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
3057 * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
3058 */
3059#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
3060#define CTIMER_CTCR_CINSEL_MASK (0xCU)
3061#define CTIMER_CTCR_CINSEL_SHIFT (2U)
3062/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
3063 * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
3064 * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
3065 * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
3066 * same timer.
3067 * 0b00..Channel 0. CAPn.0 for CTIMERn
3068 * 0b01..Channel 1. CAPn.1 for CTIMERn
3069 * 0b10..Channel 2. CAPn.2 for CTIMERn
3070 * 0b11..Channel 3. CAPn.3 for CTIMERn
3071 */
3072#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
3073#define CTIMER_CTCR_ENCC_MASK (0x10U)
3074#define CTIMER_CTCR_ENCC_SHIFT (4U)
3075/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
3076 * capture-edge event specified in bits 7:5 occurs.
3077 */
3078#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
3079#define CTIMER_CTCR_SELCC_MASK (0xE0U)
3080#define CTIMER_CTCR_SELCC_SHIFT (5U)
3081/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
3082 * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
3083 * 0x3 and 0x6 to 0x7 are reserved.
3084 * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
3085 * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
3086 * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
3087 * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
3088 * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
3089 * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
3090 */
3091#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
3092/*! @} */
3093
3094/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
3095/*! @{ */
3096#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
3097#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
3098/*! PWMEN0 - PWM mode enable for channel0.
3099 * 0b0..Match. CTIMERn_MAT0 is controlled by EM0.
3100 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
3101 */
3102#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
3103#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
3104#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
3105/*! PWMEN1 - PWM mode enable for channel1.
3106 * 0b0..Match. CTIMERn_MAT01 is controlled by EM1.
3107 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
3108 */
3109#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
3110#define CTIMER_PWMC_PWMEN2_MASK (0x4U)
3111#define CTIMER_PWMC_PWMEN2_SHIFT (2U)
3112/*! PWMEN2 - PWM mode enable for channel2.
3113 * 0b0..Match. CTIMERn_MAT2 is controlled by EM2.
3114 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
3115 */
3116#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
3117#define CTIMER_PWMC_PWMEN3_MASK (0x8U)
3118#define CTIMER_PWMC_PWMEN3_SHIFT (3U)
3119/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
3120 * 0b0..Match. CTIMERn_MAT3 is controlled by EM3.
3121 * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
3122 */
3123#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
3124/*! @} */
3125
3126/*! @name MSR - Match Shadow Register */
3127/*! @{ */
3128#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU)
3129#define CTIMER_MSR_SHADOWW_SHIFT (0U)
3130/*! SHADOWW - Timer counter match shadow value.
3131 */
3132#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)
3133/*! @} */
3134
3135/* The count of CTIMER_MSR */
3136#define CTIMER_MSR_COUNT (4U)
3137
3138
3139/*!
3140 * @}
3141 */ /* end of group CTIMER_Register_Masks */
3142
3143
3144/* CTIMER - Peripheral instance base addresses */
3145/** Peripheral CTIMER0 base address */
3146#define CTIMER0_BASE (0x40008000u)
3147/** Peripheral CTIMER0 base pointer */
3148#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
3149/** Peripheral CTIMER1 base address */
3150#define CTIMER1_BASE (0x40009000u)
3151/** Peripheral CTIMER1 base pointer */
3152#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
3153/** Peripheral CTIMER2 base address */
3154#define CTIMER2_BASE (0x40028000u)
3155/** Peripheral CTIMER2 base pointer */
3156#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
3157/** Peripheral CTIMER3 base address */
3158#define CTIMER3_BASE (0x40048000u)
3159/** Peripheral CTIMER3 base pointer */
3160#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
3161/** Peripheral CTIMER4 base address */
3162#define CTIMER4_BASE (0x40049000u)
3163/** Peripheral CTIMER4 base pointer */
3164#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
3165/** Array initializer of CTIMER peripheral base addresses */
3166#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
3167/** Array initializer of CTIMER peripheral base pointers */
3168#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
3169/** Interrupt vectors for the CTIMER peripheral type */
3170#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
3171
3172/*!
3173 * @}
3174 */ /* end of group CTIMER_Peripheral_Access_Layer */
3175
3176
3177/* ----------------------------------------------------------------------------
3178 -- DMA Peripheral Access Layer
3179 ---------------------------------------------------------------------------- */
3180
3181/*!
3182 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
3183 * @{
3184 */
3185
3186/** DMA - Register Layout Typedef */
3187typedef struct {
3188 __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
3189 __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
3190 __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
3191 uint8_t RESERVED_0[20];
3192 struct { /* offset: 0x20, array step: 0x5C */
3193 __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
3194 uint8_t RESERVED_0[4];
3195 __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
3196 uint8_t RESERVED_1[4];
3197 __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
3198 uint8_t RESERVED_2[4];
3199 __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
3200 uint8_t RESERVED_3[4];
3201 __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
3202 uint8_t RESERVED_4[4];
3203 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
3204 uint8_t RESERVED_5[4];
3205 __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
3206 uint8_t RESERVED_6[4];
3207 __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
3208 uint8_t RESERVED_7[4];
3209 __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
3210 uint8_t RESERVED_8[4];
3211 __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
3212 uint8_t RESERVED_9[4];
3213 __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
3214 uint8_t RESERVED_10[4];
3215 __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
3216 } COMMON[1];
3217 uint8_t RESERVED_1[900];
3218 struct { /* offset: 0x400, array step: 0x10 */
3219 __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
3220 __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
3221 __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
3222 uint8_t RESERVED_0[4];
3223 } CHANNEL[32];
3224} DMA_Type;
3225
3226/* ----------------------------------------------------------------------------
3227 -- DMA Register Masks
3228 ---------------------------------------------------------------------------- */
3229
3230/*!
3231 * @addtogroup DMA_Register_Masks DMA Register Masks
3232 * @{
3233 */
3234
3235/*! @name CTRL - DMA control. */
3236/*! @{ */
3237#define DMA_CTRL_ENABLE_MASK (0x1U)
3238#define DMA_CTRL_ENABLE_SHIFT (0U)
3239/*! ENABLE - DMA controller master enable.
3240 * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
3241 * disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
3242 * 0b1..Enabled. The DMA controller is enabled.
3243 */
3244#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
3245/*! @} */
3246
3247/*! @name INTSTAT - Interrupt status. */
3248/*! @{ */
3249#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
3250#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
3251/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
3252 * 0b0..Not pending. No enabled interrupts are pending.
3253 * 0b1..Pending. At least one enabled interrupt is pending.
3254 */
3255#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
3256#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
3257#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
3258/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
3259 * 0b0..Not pending. No error interrupts are pending.
3260 * 0b1..Pending. At least one error interrupt is pending.
3261 */
3262#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
3263/*! @} */
3264
3265/*! @name SRAMBASE - SRAM address of the channel configuration table. */
3266/*! @{ */
3267#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
3268#define DMA_SRAMBASE_OFFSET_SHIFT (9U)
3269/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
3270 * table must begin on a 512 byte boundary.
3271 */
3272#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
3273/*! @} */
3274
3275/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
3276/*! @{ */
3277#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)
3278#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
3279/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
3280 * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
3281 */
3282#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
3283/*! @} */
3284
3285/* The count of DMA_COMMON_ENABLESET */
3286#define DMA_COMMON_ENABLESET_COUNT (1U)
3287
3288/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
3289/*! @{ */
3290#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)
3291#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
3292/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
3293 * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
3294 * are reserved.
3295 */
3296#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
3297/*! @} */
3298
3299/* The count of DMA_COMMON_ENABLECLR */
3300#define DMA_COMMON_ENABLECLR_COUNT (1U)
3301
3302/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
3303/*! @{ */
3304#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)
3305#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
3306/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
3307 * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
3308 */
3309#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
3310/*! @} */
3311
3312/* The count of DMA_COMMON_ACTIVE */
3313#define DMA_COMMON_ACTIVE_COUNT (1U)
3314
3315/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
3316/*! @{ */
3317#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)
3318#define DMA_COMMON_BUSY_BSY_SHIFT (0U)
3319/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
3320 * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
3321 */
3322#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
3323/*! @} */
3324
3325/* The count of DMA_COMMON_BUSY */
3326#define DMA_COMMON_BUSY_COUNT (1U)
3327
3328/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
3329/*! @{ */
3330#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)
3331#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
3332/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
3333 * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
3334 * not active. 1 = error interrupt is active.
3335 */
3336#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
3337/*! @} */
3338
3339/* The count of DMA_COMMON_ERRINT */
3340#define DMA_COMMON_ERRINT_COUNT (1U)
3341
3342/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
3343/*! @{ */
3344#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)
3345#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
3346/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
3347 * number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
3348 * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
3349 */
3350#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
3351/*! @} */
3352
3353/* The count of DMA_COMMON_INTENSET */
3354#define DMA_COMMON_INTENSET_COUNT (1U)
3355
3356/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
3357/*! @{ */
3358#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)
3359#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
3360/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
3361 * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
3362 * reserved.
3363 */
3364#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
3365/*! @} */
3366
3367/* The count of DMA_COMMON_INTENCLR */
3368#define DMA_COMMON_INTENCLR_COUNT (1U)
3369
3370/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
3371/*! @{ */
3372#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)
3373#define DMA_COMMON_INTA_IA_SHIFT (0U)
3374/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
3375 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
3376 * interrupt A is not active. 1 = the DMA channel interrupt A is active.
3377 */
3378#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
3379/*! @} */
3380
3381/* The count of DMA_COMMON_INTA */
3382#define DMA_COMMON_INTA_COUNT (1U)
3383
3384/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
3385/*! @{ */
3386#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)
3387#define DMA_COMMON_INTB_IB_SHIFT (0U)
3388/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
3389 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
3390 * interrupt B is not active. 1 = the DMA channel interrupt B is active.
3391 */
3392#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
3393/*! @} */
3394
3395/* The count of DMA_COMMON_INTB */
3396#define DMA_COMMON_INTB_COUNT (1U)
3397
3398/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
3399/*! @{ */
3400#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)
3401#define DMA_COMMON_SETVALID_SV_SHIFT (0U)
3402/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
3403 * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
3404 * VALIDPENDING control bit for DMA channel n
3405 */
3406#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
3407/*! @} */
3408
3409/* The count of DMA_COMMON_SETVALID */
3410#define DMA_COMMON_SETVALID_COUNT (1U)
3411
3412/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
3413/*! @{ */
3414#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)
3415#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
3416/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
3417 * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
3418 * sets the TRIG bit for DMA channel n.
3419 */
3420#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
3421/*! @} */
3422
3423/* The count of DMA_COMMON_SETTRIG */
3424#define DMA_COMMON_SETTRIG_COUNT (1U)
3425
3426/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
3427/*! @{ */
3428#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)
3429#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
3430/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
3431 * 1 = aborts DMA operations on channel n.
3432 */
3433#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
3434/*! @} */
3435
3436/* The count of DMA_COMMON_ABORT */
3437#define DMA_COMMON_ABORT_COUNT (1U)
3438
3439/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
3440/*! @{ */
3441#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
3442#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
3443/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
3444 * move, any peripheral DMA request associated with that channel can be disabled to prevent any
3445 * interaction between the peripheral and the DMA controller.
3446 * 0b0..Disabled. Peripheral DMA requests are disabled.
3447 * 0b1..Enabled. Peripheral DMA requests are enabled.
3448 */
3449#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
3450#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
3451#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
3452/*! HWTRIGEN - Hardware Triggering Enable for this channel.
3453 * 0b0..Disabled. Hardware triggering is not used.
3454 * 0b1..Enabled. Use hardware triggering.
3455 */
3456#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
3457#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
3458#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
3459/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
3460 * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
3461 * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
3462 */
3463#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
3464#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
3465#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
3466/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
3467 * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
3468 * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
3469 * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
3470 * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
3471 * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
3472 * current BURSTPOWER length are completed.
3473 */
3474#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
3475#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
3476#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
3477/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
3478 * 0b0..Single transfer. Hardware trigger causes a single transfer.
3479 * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
3480 * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a
3481 * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
3482 * complete.
3483 */
3484#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
3485#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
3486#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
3487/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
3488 * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
3489 * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
3490 * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that
3491 * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:
3492 * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =
3493 * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The
3494 * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
3495 * multiple of the burst size.
3496 */
3497#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
3498#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
3499#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
3500/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
3501 * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this
3502 * could be used to read several sequential registers from a peripheral for each DMA burst,
3503 * reading the same registers again for each burst.
3504 * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
3505 * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
3506 */
3507#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
3508#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
3509#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
3510/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
3511 * 'wrapped', meaning that the destination address range for each burst will be the same. As an
3512 * example, this could be used to write several sequential registers to a peripheral for each DMA
3513 * burst, writing the same registers again for each burst.
3514 * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
3515 * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
3516 */
3517#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
3518#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
3519#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
3520/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority
3521 * levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
3522 */
3523#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
3524/*! @} */
3525
3526/* The count of DMA_CHANNEL_CFG */
3527#define DMA_CHANNEL_CFG_COUNT (32U)
3528
3529/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
3530/*! @{ */
3531#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
3532#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
3533/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the
3534 * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
3535 * 0b0..No effect. No effect on DMA operation.
3536 * 0b1..Valid pending.
3537 */
3538#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
3539#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
3540#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
3541/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is
3542 * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
3543 * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
3544 * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
3545 */
3546#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
3547/*! @} */
3548
3549/* The count of DMA_CHANNEL_CTLSTAT */
3550#define DMA_CHANNEL_CTLSTAT_COUNT (32U)
3551
3552/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
3553/*! @{ */
3554#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
3555#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
3556/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor
3557 * is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
3558 * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
3559 * 0b1..Valid. The current channel descriptor is considered valid.
3560 */
3561#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
3562#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
3563#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
3564/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current
3565 * descriptor is exhausted. Reloading allows ping-pong and linked transfers.
3566 * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
3567 * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.
3568 */
3569#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
3570#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
3571#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
3572/*! SWTRIG - Software Trigger.
3573 * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by
3574 * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
3575 * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not
3576 * be used with level triggering when TRIGBURST = 0.
3577 */
3578#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
3579#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)
3580#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)
3581/*! CLRTRIG - Clear Trigger.
3582 * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
3583 * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted
3584 */
3585#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
3586#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)
3587#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)
3588/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between
3589 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
3590 * convention, interrupt A may be used when only one interrupt flag is needed.
3591 * 0b0..No effect.
3592 * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
3593 */
3594#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
3595#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)
3596#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)
3597/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between
3598 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
3599 * convention, interrupt A may be used when only one interrupt flag is needed.
3600 * 0b0..No effect.
3601 * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
3602 */
3603#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
3604#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)
3605#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)
3606/*! WIDTH - Transfer width used for this DMA channel.
3607 * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
3608 * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
3609 * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
3610 * 0b11..Reserved. Reserved setting, do not use.
3611 */
3612#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
3613#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)
3614#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)
3615/*! SRCINC - Determines whether the source address is incremented for each DMA transfer.
3616 * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
3617 * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is
3618 * the usual case when the source is memory.
3619 * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
3620 * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
3621 */
3622#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
3623#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)
3624#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)
3625/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer.
3626 * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when
3627 * the destination is a peripheral device.
3628 * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer.
3629 * This is the usual case when the destination is memory.
3630 * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
3631 * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
3632 */
3633#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
3634#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)
3635#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)
3636/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes
3637 * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller
3638 * uses this bit field during transfer to count down. Hence, it cannot be used by software to read
3639 * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1
3640 * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of
3641 * 1,024 transfers will be performed.
3642 */
3643#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
3644/*! @} */
3645
3646/* The count of DMA_CHANNEL_XFERCFG */
3647#define DMA_CHANNEL_XFERCFG_COUNT (32U)
3648
3649
3650/*!
3651 * @}
3652 */ /* end of group DMA_Register_Masks */
3653
3654
3655/* DMA - Peripheral instance base addresses */
3656/** Peripheral DMA0 base address */
3657#define DMA0_BASE (0x40082000u)
3658/** Peripheral DMA0 base pointer */
3659#define DMA0 ((DMA_Type *)DMA0_BASE)
3660/** Array initializer of DMA peripheral base addresses */
3661#define DMA_BASE_ADDRS { DMA0_BASE }
3662/** Array initializer of DMA peripheral base pointers */
3663#define DMA_BASE_PTRS { DMA0 }
3664/** Interrupt vectors for the DMA peripheral type */
3665#define DMA_IRQS { DMA0_IRQn }
3666
3667/*!
3668 * @}
3669 */ /* end of group DMA_Peripheral_Access_Layer */
3670
3671
3672/* ----------------------------------------------------------------------------
3673 -- DMIC Peripheral Access Layer
3674 ---------------------------------------------------------------------------- */
3675
3676/*!
3677 * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
3678 * @{
3679 */
3680
3681/** DMIC - Register Layout Typedef */
3682typedef struct {
3683 struct { /* offset: 0x0, array step: 0x100 */
3684 __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */
3685 __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */
3686 __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */
3687 __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */
3688 __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */
3689 uint8_t RESERVED_0[108];
3690 __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */
3691 __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */
3692 __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */
3693 __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */
3694 __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */
3695 uint8_t RESERVED_1[108];
3696 } CHANNEL[2];
3697 uint8_t RESERVED_0[3328];
3698 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */
3699 uint8_t RESERVED_1[8];
3700 __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */
3701 __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */
3702 uint8_t RESERVED_2[108];
3703 __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */
3704 __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */
3705 __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */
3706 __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */
3707 __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */
3708 __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */
3709 __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */
3710 uint8_t RESERVED_3[96];
3711 __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */
3712} DMIC_Type;
3713
3714/* ----------------------------------------------------------------------------
3715 -- DMIC Register Masks
3716 ---------------------------------------------------------------------------- */
3717
3718/*!
3719 * @addtogroup DMIC_Register_Masks DMIC Register Masks
3720 * @{
3721 */
3722
3723/*! @name CHANNEL_OSR - Oversample Rate register 0 */
3724/*! @{ */
3725#define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU)
3726#define DMIC_CHANNEL_OSR_OSR_SHIFT (0U)
3727/*! OSR - Selects the oversample rate for the related input channel.
3728 */
3729#define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
3730/*! @} */
3731
3732/* The count of DMIC_CHANNEL_OSR */
3733#define DMIC_CHANNEL_OSR_COUNT (2U)
3734
3735/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */
3736/*! @{ */
3737#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU)
3738#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U)
3739/*! PDMDIV - PDM clock divider value. 0 = divide by 1 1 = divide by 2 2 = divide by 3 3 = divide by
3740 * 4 4 = divide by 6 5 = divide by 8 6 = divide by 12 7 = divide by 16 8 = divide by 24 9 =
3741 * divide by 32 10 = divide by 48 11 = divide by 64 12 = divide by 96 13 = divide by 128 others =
3742 * reserved.
3743 */
3744#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
3745/*! @} */
3746
3747/* The count of DMIC_CHANNEL_DIVHFCLK */
3748#define DMIC_CHANNEL_DIVHFCLK_COUNT (2U)
3749
3750/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */
3751/*! @{ */
3752#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U)
3753#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U)
3754/*! COMP - Pre-emphasis filer coefficient for 2 FS mode. 0 = Compensation = 0 1 = Compensation = 16
3755 * 2 = Compensation = 15 3 = Compensation = 13
3756 */
3757#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
3758/*! @} */
3759
3760/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
3761#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U)
3762
3763/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */
3764/*! @{ */
3765#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U)
3766#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U)
3767/*! COMP - Pre-emphasis filer coefficient for 4 FS mode. 0 = Compensation = 0 1 = Compensation = 16
3768 * 2 = Compensation = 15 3 = Compensation = 13
3769 */
3770#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
3771/*! @} */
3772
3773/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
3774#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U)
3775
3776/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */
3777/*! @{ */
3778#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU)
3779#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U)
3780/*! GAIN - Gain control, as a positive or negative (two's complement) number of bits to shift.
3781 */
3782#define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
3783/*! @} */
3784
3785/* The count of DMIC_CHANNEL_GAINSHIFT */
3786#define DMIC_CHANNEL_GAINSHIFT_COUNT (2U)
3787
3788/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */
3789/*! @{ */
3790#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U)
3791#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U)
3792/*! ENABLE - FIFO enable.
3793 * 0b0..FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being
3794 * streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a
3795 * period when the data was not needed.
3796 * 0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
3797 */
3798#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
3799#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U)
3800#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U)
3801/*! RESETN - FIFO reset.
3802 * 0b0..Reset the FIFO.
3803 * 0b1..Normal operation
3804 */
3805#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
3806#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U)
3807#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U)
3808/*! INTEN - Interrupt enable.
3809 * 0b0..FIFO level interrupts are not enabled.
3810 * 0b1..FIFO level interrupts are enabled.
3811 */
3812#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
3813#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U)
3814#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U)
3815/*! DMAEN - DMA enable
3816 * 0b0..DMA requests are not enabled.
3817 * 0b1..DMA requests based on FIFO level are enabled.
3818 */
3819#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
3820#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U)
3821#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U)
3822/*! TRIGLVL - FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If
3823 * enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then
3824 * return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 =
3825 * trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has
3826 * received two entries. 15 = trigger when the FIFO has received 16 entries (has become full).
3827 */
3828#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
3829/*! @} */
3830
3831/* The count of DMIC_CHANNEL_FIFO_CTRL */
3832#define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U)
3833
3834/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */
3835/*! @{ */
3836#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U)
3837#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U)
3838/*! INT - Interrupt flag. Asserted when FIFO data reaches the level specified in the FIFOCTRL
3839 * register. Writing a one to this bit clears the flag. Remark: note that the bus clock to the DMIC
3840 * subsystem must be running in order for an interrupt to occur.
3841 */
3842#define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
3843#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U)
3844#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U)
3845/*! OVERRUN - Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one
3846 * to this bit clears the flag. This flag does not cause an interrupt.
3847 */
3848#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
3849#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U)
3850#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U)
3851/*! UNDERRUN - Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag.
3852 */
3853#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
3854/*! @} */
3855
3856/* The count of DMIC_CHANNEL_FIFO_STATUS */
3857#define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U)
3858
3859/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */
3860/*! @{ */
3861#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU)
3862#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U)
3863/*! DATA - Data from the top of the input filter FIFO.
3864 */
3865#define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
3866/*! @} */
3867
3868/* The count of DMIC_CHANNEL_FIFO_DATA */
3869#define DMIC_CHANNEL_FIFO_DATA_COUNT (2U)
3870
3871/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */
3872/*! @{ */
3873#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U)
3874#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U)
3875/*! PHY_FALL - Capture PDM_DATA
3876 * 0b0..Capture PDM_DATA on the rising edge of PDM_CLK.
3877 * 0b1..Capture PDM_DATA on the falling edge of PDM_CLK.
3878 */
3879#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
3880#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U)
3881#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U)
3882/*! PHY_HALF - Half rate sampling
3883 * 0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
3884 * 0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.
3885 */
3886#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
3887/*! @} */
3888
3889/* The count of DMIC_CHANNEL_PHY_CTRL */
3890#define DMIC_CHANNEL_PHY_CTRL_COUNT (2U)
3891
3892/*! @name CHANNEL_DC_CTRL - DC Control register 0 */
3893/*! @{ */
3894#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U)
3895#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U)
3896/*! DCPOLE - DC block filter
3897 * 0b00..Flat response, no filter.
3898 * 0b01..155 Hz.
3899 * 0b10..78 Hz.
3900 * 0b11..39 Hz
3901 */
3902#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
3903#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U)
3904#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U)
3905/*! DCGAIN - Fine gain adjustment in the form of a number of bits to downshift.
3906 */
3907#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
3908#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
3909#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
3910/*! SATURATEAT16BIT - Selects 16-bit saturation.
3911 * 0b0..Results roll over if out range and do not saturate.
3912 * 0b1..If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
3913 */
3914#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
3915/*! @} */
3916
3917/* The count of DMIC_CHANNEL_DC_CTRL */
3918#define DMIC_CHANNEL_DC_CTRL_COUNT (2U)
3919
3920/*! @name CHANEN - Channel Enable register */
3921/*! @{ */
3922#define DMIC_CHANEN_EN_CH0_MASK (0x1U)
3923#define DMIC_CHANEN_EN_CH0_SHIFT (0U)
3924/*! EN_CH0 - Enable channel 0. When 1, PDM channel 0 is enabled.
3925 */
3926#define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
3927#define DMIC_CHANEN_EN_CH1_MASK (0x2U)
3928#define DMIC_CHANEN_EN_CH1_SHIFT (1U)
3929/*! EN_CH1 - Enable channel 1. When 1, PDM channel 1 is enabled.
3930 */
3931#define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
3932/*! @} */
3933
3934/*! @name IOCFG - I/O Configuration register */
3935/*! @{ */
3936#define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U)
3937#define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U)
3938/*! CLK_BYPASS0 - Bypass CLK0. When 1, PDM_DATA1 becomes the clock for PDM channel 0. This provides
3939 * for the possibility of an external codec taking over the PDM bus.
3940 */
3941#define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)
3942#define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U)
3943#define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U)
3944/*! CLK_BYPASS1 - Bypass CLK1. When 1, PDM_DATA1 becomes the clock for PDM channel 1. This provides
3945 * for the possibility of an external codec taking over the PDM bus.
3946 */
3947#define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)
3948#define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U)
3949#define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U)
3950/*! STEREO_DATA0 - Stereo PDM select. When 1, PDM_DATA0 is routed to both PDM channels in a
3951 * configuration that supports a single stereo digital microphone.
3952 */
3953#define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)
3954/*! @} */
3955
3956/*! @name USE2FS - Use 2FS register */
3957/*! @{ */
3958#define DMIC_USE2FS_USE2FS_MASK (0x1U)
3959#define DMIC_USE2FS_USE2FS_SHIFT (0U)
3960/*! USE2FS - Use 2FS register
3961 * 0b0..Use 1FS output for PCM data.
3962 * 0b1..Use 2FS output for PCM data.
3963 */
3964#define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
3965/*! @} */
3966
3967/*! @name HWVADGAIN - HWVAD input gain register */
3968/*! @{ */
3969#define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU)
3970#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U)
3971/*! INPUTGAIN - Shift value for input bits 0x00 -10 bits 0x01 -8 bits 0x02 -6 bits 0x03 -4 bits 0x04
3972 * -2 bits 0x05 0 bits (default) 0x06 +2 bits 0x07 +4 bits 0x08 +6 bits 0x09 +8 bits 0x0A +10
3973 * bits 0x0B +12 bits 0x0C +14 bits 0x0D to 0x0F Reserved.
3974 */
3975#define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
3976/*! @} */
3977
3978/*! @name HWVADHPFS - HWVAD filter control register */
3979/*! @{ */
3980#define DMIC_HWVADHPFS_HPFS_MASK (0x3U)
3981#define DMIC_HWVADHPFS_HPFS_SHIFT (0U)
3982/*! HPFS - High pass filter
3983 * 0b00..First filter by-pass.
3984 * 0b01..High pass filter with -3dB cut-off at 1750Hz.
3985 * 0b10..High pass filter with -3dB cut-off at 215Hz.
3986 * 0b11..Reserved.
3987 */
3988#define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
3989/*! @} */
3990
3991/*! @name HWVADST10 - HWVAD control register */
3992/*! @{ */
3993#define DMIC_HWVADST10_ST10_MASK (0x1U)
3994#define DMIC_HWVADST10_ST10_SHIFT (0U)
3995/*! ST10 - Stage 0
3996 * 0b0..Normal operation, waiting for HWVAD trigger event (stage 0).
3997 * 0b1..Reset internal interrupt flag by writing a '1' pulse.
3998 */
3999#define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
4000/*! @} */
4001
4002/*! @name HWVADRSTT - HWVAD filter reset register */
4003/*! @{ */
4004#define DMIC_HWVADRSTT_RSTT_MASK (0x1U)
4005#define DMIC_HWVADRSTT_RSTT_SHIFT (0U)
4006/*! RSTT - Writing a 1 resets all filter values
4007 */
4008#define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)
4009/*! @} */
4010
4011/*! @name HWVADTHGN - HWVAD noise estimator gain register */
4012/*! @{ */
4013#define DMIC_HWVADTHGN_THGN_MASK (0xFU)
4014#define DMIC_HWVADTHGN_THGN_SHIFT (0U)
4015/*! THGN - Gain value for the noise estimator. Values 0 to 14. 0 corresponds to a gain of 1.
4016 */
4017#define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
4018/*! @} */
4019
4020/*! @name HWVADTHGS - HWVAD signal estimator gain register */
4021/*! @{ */
4022#define DMIC_HWVADTHGS_THGS_MASK (0xFU)
4023#define DMIC_HWVADTHGS_THGS_SHIFT (0U)
4024/*! THGS - Gain value for the signal estimator. Values 0 to 14. 0 corresponds to a gain of 1.
4025 */
4026#define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
4027/*! @} */
4028
4029/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */
4030/*! @{ */
4031#define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU)
4032#define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U)
4033/*! LOWZ - Noise envelope estimator value.
4034 */
4035#define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
4036/*! @} */
4037
4038/*! @name ID - Module Identification register */
4039/*! @{ */
4040#define DMIC_ID_ID_MASK (0xFFFFFFFFU)
4041#define DMIC_ID_ID_SHIFT (0U)
4042/*! ID - Indicates module ID and the number of channels in this DMIC interface.
4043 */
4044#define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)
4045/*! @} */
4046
4047
4048/*!
4049 * @}
4050 */ /* end of group DMIC_Register_Masks */
4051
4052
4053/* DMIC - Peripheral instance base addresses */
4054/** Peripheral DMIC0 base address */
4055#define DMIC0_BASE (0x40090000u)
4056/** Peripheral DMIC0 base pointer */
4057#define DMIC0 ((DMIC_Type *)DMIC0_BASE)
4058/** Array initializer of DMIC peripheral base addresses */
4059#define DMIC_BASE_ADDRS { DMIC0_BASE }
4060/** Array initializer of DMIC peripheral base pointers */
4061#define DMIC_BASE_PTRS { DMIC0 }
4062/** Interrupt vectors for the DMIC peripheral type */
4063#define DMIC_IRQS { DMIC0_IRQn }
4064#define DMIC_HWVAD_IRQS { HWVAD0_IRQn }
4065
4066/*!
4067 * @}
4068 */ /* end of group DMIC_Peripheral_Access_Layer */
4069
4070
4071/* ----------------------------------------------------------------------------
4072 -- EMC Peripheral Access Layer
4073 ---------------------------------------------------------------------------- */
4074
4075/*!
4076 * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer
4077 * @{
4078 */
4079
4080/** EMC - Register Layout Typedef */
4081typedef struct {
4082 __IO uint32_t CONTROL; /**< Controls operation of the memory controller, offset: 0x0 */
4083 __I uint32_t STATUS; /**< Provides EMC status information, offset: 0x4 */
4084 __IO uint32_t CONFIG; /**< Configures operation of the memory controller, offset: 0x8 */
4085 uint8_t RESERVED_0[20];
4086 __IO uint32_t DYNAMICCONTROL; /**< Controls dynamic memory operation, offset: 0x20 */
4087 __IO uint32_t DYNAMICREFRESH; /**< Configures dynamic memory refresh, offset: 0x24 */
4088 __IO uint32_t DYNAMICREADCONFIG; /**< Configures dynamic memory read strategy, offset: 0x28 */
4089 uint8_t RESERVED_1[4];
4090 __IO uint32_t DYNAMICRP; /**< Precharge command period, offset: 0x30 */
4091 __IO uint32_t DYNAMICRAS; /**< Active to precharge command period, offset: 0x34 */
4092 __IO uint32_t DYNAMICSREX; /**< Self-refresh exit time, offset: 0x38 */
4093 __IO uint32_t DYNAMICAPR; /**< Last-data-out to active command time, offset: 0x3C */
4094 __IO uint32_t DYNAMICDAL; /**< Data-in to active command time, offset: 0x40 */
4095 __IO uint32_t DYNAMICWR; /**< Write recovery time, offset: 0x44 */
4096 __IO uint32_t DYNAMICRC; /**< Selects the active to active command period, offset: 0x48 */
4097 __IO uint32_t DYNAMICRFC; /**< Selects the auto-refresh period, offset: 0x4C */
4098 __IO uint32_t DYNAMICXSR; /**< Time for exit self-refresh to active command, offset: 0x50 */
4099 __IO uint32_t DYNAMICRRD; /**< Latency for active bank A to active bank B, offset: 0x54 */
4100 __IO uint32_t DYNAMICMRD; /**< Time for load mode register to active command, offset: 0x58 */
4101 uint8_t RESERVED_2[36];
4102 __IO uint32_t STATICEXTENDEDWAIT; /**< Time for long static memory read and write transfers, offset: 0x80 */
4103 uint8_t RESERVED_3[124];
4104 struct { /* offset: 0x100, array step: 0x20 */
4105 __IO uint32_t DYNAMICCONFIG; /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */
4106 __IO uint32_t DYNAMICRASCAS; /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */
4107 uint8_t RESERVED_0[24];
4108 } DYNAMIC[4];
4109 uint8_t RESERVED_4[128];
4110 struct { /* offset: 0x200, array step: 0x20 */
4111 __IO uint32_t STATICCONFIG; /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */
4112 __IO uint32_t STATICWAITWEN; /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */
4113 __IO uint32_t STATICWAITOEN; /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */
4114 __IO uint32_t STATICWAITRD; /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */
4115 __IO uint32_t STATICWAITPAGE; /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */
4116 __IO uint32_t STATICWAITWR; /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */
4117 __IO uint32_t STATICWAITTURN; /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */
4118 uint8_t RESERVED_0[4];
4119 } STATIC[4];
4120} EMC_Type;
4121
4122/* ----------------------------------------------------------------------------
4123 -- EMC Register Masks
4124 ---------------------------------------------------------------------------- */
4125
4126/*!
4127 * @addtogroup EMC_Register_Masks EMC Register Masks
4128 * @{
4129 */
4130
4131/*! @name CONTROL - Controls operation of the memory controller */
4132/*! @{ */
4133#define EMC_CONTROL_E_MASK (0x1U)
4134#define EMC_CONTROL_E_SHIFT (0U)
4135/*! E - EMC Enable.
4136 */
4137#define EMC_CONTROL_E(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK)
4138#define EMC_CONTROL_M_MASK (0x2U)
4139#define EMC_CONTROL_M_SHIFT (1U)
4140/*! M - Address mirror.
4141 */
4142#define EMC_CONTROL_M(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK)
4143#define EMC_CONTROL_L_MASK (0x4U)
4144#define EMC_CONTROL_L_SHIFT (2U)
4145/*! L - Low-power mode.
4146 */
4147#define EMC_CONTROL_L(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK)
4148/*! @} */
4149
4150/*! @name STATUS - Provides EMC status information */
4151/*! @{ */
4152#define EMC_STATUS_B_MASK (0x1U)
4153#define EMC_STATUS_B_SHIFT (0U)
4154/*! B - Busy.
4155 */
4156#define EMC_STATUS_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK)
4157#define EMC_STATUS_S_MASK (0x2U)
4158#define EMC_STATUS_S_SHIFT (1U)
4159/*! S - Write buffer status.
4160 */
4161#define EMC_STATUS_S(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK)
4162#define EMC_STATUS_SA_MASK (0x4U)
4163#define EMC_STATUS_SA_SHIFT (2U)
4164/*! SA - Self-refresh acknowledge.
4165 */
4166#define EMC_STATUS_SA(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK)
4167/*! @} */
4168
4169/*! @name CONFIG - Configures operation of the memory controller */
4170/*! @{ */
4171#define EMC_CONFIG_EM_MASK (0x1U)
4172#define EMC_CONFIG_EM_SHIFT (0U)
4173/*! EM - Endian mode.
4174 */
4175#define EMC_CONFIG_EM(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK)
4176#define EMC_CONFIG_CLKR_MASK (0x100U)
4177#define EMC_CONFIG_CLKR_SHIFT (8U)
4178/*! CLKR - This bit must contain 0 for proper operation of the EMC.
4179 */
4180#define EMC_CONFIG_CLKR(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK)
4181/*! @} */
4182
4183/*! @name DYNAMICCONTROL - Controls dynamic memory operation */
4184/*! @{ */
4185#define EMC_DYNAMICCONTROL_CE_MASK (0x1U)
4186#define EMC_DYNAMICCONTROL_CE_SHIFT (0U)
4187/*! CE - Dynamic memory clock enable.
4188 */
4189#define EMC_DYNAMICCONTROL_CE(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK)
4190#define EMC_DYNAMICCONTROL_CS_MASK (0x2U)
4191#define EMC_DYNAMICCONTROL_CS_SHIFT (1U)
4192/*! CS - Dynamic memory clock control.
4193 */
4194#define EMC_DYNAMICCONTROL_CS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK)
4195#define EMC_DYNAMICCONTROL_SR_MASK (0x4U)
4196#define EMC_DYNAMICCONTROL_SR_SHIFT (2U)
4197/*! SR - Self-refresh request, EMCSREFREQ.
4198 */
4199#define EMC_DYNAMICCONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK)
4200#define EMC_DYNAMICCONTROL_MMC_MASK (0x20U)
4201#define EMC_DYNAMICCONTROL_MMC_SHIFT (5U)
4202/*! MMC - Memory clock control.
4203 */
4204#define EMC_DYNAMICCONTROL_MMC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK)
4205#define EMC_DYNAMICCONTROL_I_MASK (0x180U)
4206#define EMC_DYNAMICCONTROL_I_SHIFT (7U)
4207/*! I - SDRAM initialization.
4208 */
4209#define EMC_DYNAMICCONTROL_I(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK)
4210/*! @} */
4211
4212/*! @name DYNAMICREFRESH - Configures dynamic memory refresh */
4213/*! @{ */
4214#define EMC_DYNAMICREFRESH_REFRESH_MASK (0x7FFU)
4215#define EMC_DYNAMICREFRESH_REFRESH_SHIFT (0U)
4216/*! REFRESH - Refresh timer.
4217 */
4218#define EMC_DYNAMICREFRESH_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK)
4219/*! @} */
4220
4221/*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */
4222/*! @{ */
4223#define EMC_DYNAMICREADCONFIG_RD_MASK (0x3U)
4224#define EMC_DYNAMICREADCONFIG_RD_SHIFT (0U)
4225/*! RD - Read data strategy.
4226 */
4227#define EMC_DYNAMICREADCONFIG_RD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK)
4228/*! @} */
4229
4230/*! @name DYNAMICRP - Precharge command period */
4231/*! @{ */
4232#define EMC_DYNAMICRP_TRP_MASK (0xFU)
4233#define EMC_DYNAMICRP_TRP_SHIFT (0U)
4234/*! TRP - Precharge command period.
4235 */
4236#define EMC_DYNAMICRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK)
4237/*! @} */
4238
4239/*! @name DYNAMICRAS - Active to precharge command period */
4240/*! @{ */
4241#define EMC_DYNAMICRAS_TRAS_MASK (0xFU)
4242#define EMC_DYNAMICRAS_TRAS_SHIFT (0U)
4243/*! TRAS - Active to precharge command period.
4244 */
4245#define EMC_DYNAMICRAS_TRAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK)
4246/*! @} */
4247
4248/*! @name DYNAMICSREX - Self-refresh exit time */
4249/*! @{ */
4250#define EMC_DYNAMICSREX_TSREX_MASK (0xFU)
4251#define EMC_DYNAMICSREX_TSREX_SHIFT (0U)
4252/*! TSREX - Self-refresh exit time.
4253 */
4254#define EMC_DYNAMICSREX_TSREX(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK)
4255/*! @} */
4256
4257/*! @name DYNAMICAPR - Last-data-out to active command time */
4258/*! @{ */
4259#define EMC_DYNAMICAPR_TAPR_MASK (0xFU)
4260#define EMC_DYNAMICAPR_TAPR_SHIFT (0U)
4261/*! TAPR - Last-data-out to active command time.
4262 */
4263#define EMC_DYNAMICAPR_TAPR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK)
4264/*! @} */
4265
4266/*! @name DYNAMICDAL - Data-in to active command time */
4267/*! @{ */
4268#define EMC_DYNAMICDAL_TDAL_MASK (0xFU)
4269#define EMC_DYNAMICDAL_TDAL_SHIFT (0U)
4270/*! TDAL - Data-in to active command.
4271 */
4272#define EMC_DYNAMICDAL_TDAL(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK)
4273/*! @} */
4274
4275/*! @name DYNAMICWR - Write recovery time */
4276/*! @{ */
4277#define EMC_DYNAMICWR_TWR_MASK (0xFU)
4278#define EMC_DYNAMICWR_TWR_SHIFT (0U)
4279/*! TWR - Write recovery time.
4280 */
4281#define EMC_DYNAMICWR_TWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK)
4282/*! @} */
4283
4284/*! @name DYNAMICRC - Selects the active to active command period */
4285/*! @{ */
4286#define EMC_DYNAMICRC_TRC_MASK (0x1FU)
4287#define EMC_DYNAMICRC_TRC_SHIFT (0U)
4288/*! TRC - Active to active command period.
4289 */
4290#define EMC_DYNAMICRC_TRC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK)
4291/*! @} */
4292
4293/*! @name DYNAMICRFC - Selects the auto-refresh period */
4294/*! @{ */
4295#define EMC_DYNAMICRFC_TRFC_MASK (0x1FU)
4296#define EMC_DYNAMICRFC_TRFC_SHIFT (0U)
4297/*! TRFC - Auto-refresh period and auto-refresh to active command period.
4298 */
4299#define EMC_DYNAMICRFC_TRFC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK)
4300/*! @} */
4301
4302/*! @name DYNAMICXSR - Time for exit self-refresh to active command */
4303/*! @{ */
4304#define EMC_DYNAMICXSR_TXSR_MASK (0x1FU)
4305#define EMC_DYNAMICXSR_TXSR_SHIFT (0U)
4306/*! TXSR - Exit self-refresh to active command time.
4307 */
4308#define EMC_DYNAMICXSR_TXSR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK)
4309/*! @} */
4310
4311/*! @name DYNAMICRRD - Latency for active bank A to active bank B */
4312/*! @{ */
4313#define EMC_DYNAMICRRD_TRRD_MASK (0xFU)
4314#define EMC_DYNAMICRRD_TRRD_SHIFT (0U)
4315/*! TRRD - Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles.
4316 */
4317#define EMC_DYNAMICRRD_TRRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK)
4318/*! @} */
4319
4320/*! @name DYNAMICMRD - Time for load mode register to active command */
4321/*! @{ */
4322#define EMC_DYNAMICMRD_TMRD_MASK (0xFU)
4323#define EMC_DYNAMICMRD_TMRD_SHIFT (0U)
4324/*! TMRD - Load mode register to active command time.
4325 */
4326#define EMC_DYNAMICMRD_TMRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK)
4327/*! @} */
4328
4329/*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */
4330/*! @{ */
4331#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU)
4332#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U)
4333/*! EXTENDEDWAIT - Extended wait time out.
4334 */
4335#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK)
4336/*! @} */
4337
4338/*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */
4339/*! @{ */
4340#define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK (0x18U)
4341#define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT (3U)
4342/*! MD - Memory device.
4343 */
4344#define EMC_DYNAMIC_DYNAMICCONFIG_MD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK)
4345#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK (0x1F80U)
4346#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT (7U)
4347/*! AM0 - See Table 933.
4348 */
4349#define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK)
4350#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK (0x4000U)
4351#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT (14U)
4352/*! AM1 - See Table 933.
4353 */
4354#define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
4355#define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK (0x80000U)
4356#define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT (19U)
4357/*! B - Buffer enable.
4358 */
4359#define EMC_DYNAMIC_DYNAMICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK)
4360#define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK (0x100000U)
4361#define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT (20U)
4362/*! P - Write protect.
4363 */
4364#define EMC_DYNAMIC_DYNAMICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK)
4365/*! @} */
4366
4367/* The count of EMC_DYNAMIC_DYNAMICCONFIG */
4368#define EMC_DYNAMIC_DYNAMICCONFIG_COUNT (4U)
4369
4370/*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */
4371/*! @{ */
4372#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK (0x3U)
4373#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT (0U)
4374/*! RAS - RAS latency (active to read/write delay).
4375 */
4376#define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK)
4377#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK (0x300U)
4378#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT (8U)
4379/*! CAS - CAS latency.
4380 */
4381#define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK)
4382/*! @} */
4383
4384/* The count of EMC_DYNAMIC_DYNAMICRASCAS */
4385#define EMC_DYNAMIC_DYNAMICRASCAS_COUNT (4U)
4386
4387/*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */
4388/*! @{ */
4389#define EMC_STATIC_STATICCONFIG_MW_MASK (0x3U)
4390#define EMC_STATIC_STATICCONFIG_MW_SHIFT (0U)
4391/*! MW - Memory width.
4392 */
4393#define EMC_STATIC_STATICCONFIG_MW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK)
4394#define EMC_STATIC_STATICCONFIG_PM_MASK (0x8U)
4395#define EMC_STATIC_STATICCONFIG_PM_SHIFT (3U)
4396/*! PM - Page mode.
4397 */
4398#define EMC_STATIC_STATICCONFIG_PM(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK)
4399#define EMC_STATIC_STATICCONFIG_PC_MASK (0x40U)
4400#define EMC_STATIC_STATICCONFIG_PC_SHIFT (6U)
4401/*! PC - Chip select polarity.
4402 */
4403#define EMC_STATIC_STATICCONFIG_PC(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK)
4404#define EMC_STATIC_STATICCONFIG_PB_MASK (0x80U)
4405#define EMC_STATIC_STATICCONFIG_PB_SHIFT (7U)
4406/*! PB - Byte lane state.
4407 */
4408#define EMC_STATIC_STATICCONFIG_PB(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK)
4409#define EMC_STATIC_STATICCONFIG_EW_MASK (0x100U)
4410#define EMC_STATIC_STATICCONFIG_EW_SHIFT (8U)
4411/*! EW - Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write
4412 * transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.
4413 */
4414#define EMC_STATIC_STATICCONFIG_EW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK)
4415#define EMC_STATIC_STATICCONFIG_B_MASK (0x80000U)
4416#define EMC_STATIC_STATICCONFIG_B_SHIFT (19U)
4417/*! B - Buffer enable [2].
4418 */
4419#define EMC_STATIC_STATICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK)
4420#define EMC_STATIC_STATICCONFIG_P_MASK (0x100000U)
4421#define EMC_STATIC_STATICCONFIG_P_SHIFT (20U)
4422/*! P - Write protect.
4423 */
4424#define EMC_STATIC_STATICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK)
4425/*! @} */
4426
4427/* The count of EMC_STATIC_STATICCONFIG */
4428#define EMC_STATIC_STATICCONFIG_COUNT (4U)
4429
4430/*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */
4431/*! @{ */
4432#define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK (0xFU)
4433#define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT (0U)
4434/*! WAITWEN - Wait write enable.
4435 */
4436#define EMC_STATIC_STATICWAITWEN_WAITWEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK)
4437/*! @} */
4438
4439/* The count of EMC_STATIC_STATICWAITWEN */
4440#define EMC_STATIC_STATICWAITWEN_COUNT (4U)
4441
4442/*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */
4443/*! @{ */
4444#define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK (0xFU)
4445#define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT (0U)
4446/*! WAITOEN - Wait output enable.
4447 */
4448#define EMC_STATIC_STATICWAITOEN_WAITOEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK)
4449/*! @} */
4450
4451/* The count of EMC_STATIC_STATICWAITOEN */
4452#define EMC_STATIC_STATICWAITOEN_COUNT (4U)
4453
4454/*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */
4455/*! @{ */
4456#define EMC_STATIC_STATICWAITRD_WAITRD_MASK (0x1FU)
4457#define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT (0U)
4458/*! WAITRD - .
4459 */
4460#define EMC_STATIC_STATICWAITRD_WAITRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK)
4461/*! @} */
4462
4463/* The count of EMC_STATIC_STATICWAITRD */
4464#define EMC_STATIC_STATICWAITRD_COUNT (4U)
4465
4466/*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */
4467/*! @{ */
4468#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK (0x1FU)
4469#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U)
4470/*! WAITPAGE - Asynchronous page mode read after the first read wait states.
4471 */
4472#define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK)
4473/*! @} */
4474
4475/* The count of EMC_STATIC_STATICWAITPAGE */
4476#define EMC_STATIC_STATICWAITPAGE_COUNT (4U)
4477
4478/*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */
4479/*! @{ */
4480#define EMC_STATIC_STATICWAITWR_WAITWR_MASK (0x1FU)
4481#define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT (0U)
4482/*! WAITWR - Write wait states.
4483 */
4484#define EMC_STATIC_STATICWAITWR_WAITWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK)
4485/*! @} */
4486
4487/* The count of EMC_STATIC_STATICWAITWR */
4488#define EMC_STATIC_STATICWAITWR_COUNT (4U)
4489
4490/*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */
4491/*! @{ */
4492#define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK (0xFU)
4493#define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U)
4494/*! WAITTURN - Bus turn-around cycles.
4495 */
4496#define EMC_STATIC_STATICWAITTURN_WAITTURN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK)
4497/*! @} */
4498
4499/* The count of EMC_STATIC_STATICWAITTURN */
4500#define EMC_STATIC_STATICWAITTURN_COUNT (4U)
4501
4502
4503/*!
4504 * @}
4505 */ /* end of group EMC_Register_Masks */
4506
4507
4508/* EMC - Peripheral instance base addresses */
4509/** Peripheral EMC base address */
4510#define EMC_BASE (0x40081000u)
4511/** Peripheral EMC base pointer */
4512#define EMC ((EMC_Type *)EMC_BASE)
4513/** Array initializer of EMC peripheral base addresses */
4514#define EMC_BASE_ADDRS { EMC_BASE }
4515/** Array initializer of EMC peripheral base pointers */
4516#define EMC_BASE_PTRS { EMC }
4517
4518/*!
4519 * @}
4520 */ /* end of group EMC_Peripheral_Access_Layer */
4521
4522
4523/* ----------------------------------------------------------------------------
4524 -- ENET Peripheral Access Layer
4525 ---------------------------------------------------------------------------- */
4526
4527/*!
4528 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
4529 * @{
4530 */
4531
4532/** ENET - Register Layout Typedef */
4533typedef struct {
4534 __IO uint32_t MAC_CONFIG; /**< MAC configuration register, offset: 0x0 */
4535 __IO uint32_t MAC_EXT_CONFIG; /**< , offset: 0x4 */
4536 __IO uint32_t MAC_FRAME_FILTER; /**< MAC frame filter register, offset: 0x8 */
4537 __IO uint32_t MAC_WD_TIMEROUT; /**< MAC watchdog Timeout register, offset: 0xC */
4538 uint8_t RESERVED_0[64];
4539 __IO uint32_t MAC_VLAN_TAG; /**< MAC vlan tag register, offset: 0x50 */
4540 uint8_t RESERVED_1[28];
4541 __IO uint32_t MAC_TX_FLOW_CTRL_Q[2]; /**< Transmit flow control register, array offset: 0x70, array step: 0x4 */
4542 uint8_t RESERVED_2[24];
4543 __IO uint32_t MAC_RX_FLOW_CTRL; /**< Receive flow control register, offset: 0x90 */
4544 uint8_t RESERVED_3[4];
4545 __IO uint32_t MAC_TXQ_PRIO_MAP; /**< , offset: 0x98 */
4546 uint8_t RESERVED_4[4];
4547 __IO uint32_t MAC_RXQ_CTRL[3]; /**< Receive Queue Control 0 register 0x0000, array offset: 0xA0, array step: 0x4 */
4548 uint8_t RESERVED_5[4];
4549 __I uint32_t MAC_INTR_STAT; /**< Interrupt status register 0x0000, offset: 0xB0 */
4550 __IO uint32_t MAC_INTR_EN; /**< Interrupt enable register 0x0000, offset: 0xB4 */
4551 __I uint32_t MAC_RXTX_STAT; /**< Receive Transmit Status register, offset: 0xB8 */
4552 uint8_t RESERVED_6[4];
4553 __IO uint32_t MAC_PMT_CRTL_STAT; /**< , offset: 0xC0 */
4554 __IO uint32_t MAC_RWAKE_FRFLT; /**< Remote wake-up frame filter, offset: 0xC4 */
4555 uint8_t RESERVED_7[8];
4556 __IO uint32_t MAC_LPI_CTRL_STAT; /**< LPI Control and Status Register, offset: 0xD0 */
4557 __IO uint32_t MAC_LPI_TIMER_CTRL; /**< LPI Timers Control register, offset: 0xD4 */
4558 __IO uint32_t MAC_LPI_ENTR_TIMR; /**< LPI entry Timer register, offset: 0xD8 */
4559 __IO uint32_t MAC_1US_TIC_COUNTR; /**< , offset: 0xDC */
4560 uint8_t RESERVED_8[48];
4561 __I uint32_t MAC_VERSION; /**< MAC version register, offset: 0x110 */
4562 __I uint32_t MAC_DBG; /**< MAC debug register, offset: 0x114 */
4563 uint8_t RESERVED_9[4];
4564 __I uint32_t MAC_HW_FEAT[3]; /**< MAC hardware feature register 0x0201, array offset: 0x11C, array step: 0x4 */
4565 uint8_t RESERVED_10[216];
4566 __IO uint32_t MAC_MDIO_ADDR; /**< MIDO address Register, offset: 0x200 */
4567 __IO uint32_t MAC_MDIO_DATA; /**< MDIO Data register, offset: 0x204 */
4568 uint8_t RESERVED_11[248];
4569 __IO uint32_t MAC_ADDR_HIGH; /**< MAC address0 high register, offset: 0x300 */
4570 __IO uint32_t MAC_ADDR_LOW; /**< MAC address0 low register, offset: 0x304 */
4571 uint8_t RESERVED_12[2040];
4572 __IO uint32_t MAC_TIMESTAMP_CTRL; /**< Time stamp control register, offset: 0xB00 */
4573 __IO uint32_t MAC_SUB_SCND_INCR; /**< Sub-second increment register, offset: 0xB04 */
4574 __I uint32_t MAC_SYS_TIME_SCND; /**< System time seconds register, offset: 0xB08 */
4575 __I uint32_t MAC_SYS_TIME_NSCND; /**< System time nanoseconds register, offset: 0xB0C */
4576 __IO uint32_t MAC_SYS_TIME_SCND_UPD; /**< , offset: 0xB10 */
4577 __IO uint32_t MAC_SYS_TIME_NSCND_UPD; /**< , offset: 0xB14 */
4578 __IO uint32_t MAC_SYS_TIMESTMP_ADDEND; /**< Time stamp addend register, offset: 0xB18 */
4579 __IO uint32_t MAC_SYS_TIME_HWORD_SCND; /**< , offset: 0xB1C */
4580 __I uint32_t MAC_SYS_TIMESTMP_STAT; /**< Time stamp status register, offset: 0xB20 */
4581 uint8_t RESERVED_13[12];
4582 __I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Tx timestamp status nanoseconds, offset: 0xB30 */
4583 __I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< Tx timestamp status seconds, offset: 0xB34 */
4584 uint8_t RESERVED_14[32];
4585 __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp ingress correction, offset: 0xB58 */
4586 __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp egress correction, offset: 0xB5C */
4587 uint8_t RESERVED_15[160];
4588 __IO uint32_t MTL_OP_MODE; /**< MTL Operation Mode Register, offset: 0xC00 */
4589 uint8_t RESERVED_16[28];
4590 __I uint32_t MTL_INTR_STAT; /**< MTL Interrupt Status register, offset: 0xC20 */
4591 uint8_t RESERVED_17[12];
4592 __IO uint32_t MTL_RXQ_DMA_MAP; /**< MTL Receive Queue and DMA Channel Mapping register, offset: 0xC30 */
4593 uint8_t RESERVED_18[204];
4594 struct { /* offset: 0xD00, array step: 0x40 */
4595 __IO uint32_t MTL_TXQX_OP_MODE; /**< MTL TxQx Operation Mode register, array offset: 0xD00, array step: 0x40 */
4596 __I uint32_t MTL_TXQX_UNDRFLW; /**< MTL TxQx Underflow register, array offset: 0xD04, array step: 0x40 */
4597 __I uint32_t MTL_TXQX_DBG; /**< MTL TxQx Debug register, array offset: 0xD08, array step: 0x40 */
4598 uint8_t RESERVED_0[4];
4599 __IO uint32_t MTL_TXQX_ETS_CTRL; /**< MTL TxQx ETS control register, only TxQ1 support, array offset: 0xD10, array step: 0x40 */
4600 __I uint32_t MTL_TXQX_ETS_STAT; /**< MTL TxQx ETS Status register, array offset: 0xD14, array step: 0x40 */
4601 __IO uint32_t MTL_TXQX_QNTM_WGHT; /**< , array offset: 0xD18, array step: 0x40 */
4602 __IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< MTL TxQx SendSlopCredit register, only TxQ1 support, array offset: 0xD1C, array step: 0x40 */
4603 __IO uint32_t MTL_TXQX_HI_CRDT; /**< MTL TxQx hiCredit register, only TxQ1 support, array offset: 0xD20, array step: 0x40 */
4604 __IO uint32_t MTL_TXQX_LO_CRDT; /**< MTL TxQx loCredit register, only TxQ1 support, array offset: 0xD24, array step: 0x40 */
4605 uint8_t RESERVED_1[4];
4606 __IO uint32_t MTL_TXQX_INTCTRL_STAT; /**< , array offset: 0xD2C, array step: 0x40 */
4607 __IO uint32_t MTL_RXQX_OP_MODE; /**< MTL RxQx Operation Mode register, array offset: 0xD30, array step: 0x40 */
4608 __I uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< MTL RxQx Missed Packet Overflow Counter register, array offset: 0xD34, array step: 0x40 */
4609 __I uint32_t MTL_RXQX_DBG; /**< MTL RxQx Debug register, array offset: 0xD38, array step: 0x40 */
4610 __IO uint32_t MTL_RXQX_CTRL; /**< MTL RxQx Control register, array offset: 0xD3C, array step: 0x40 */
4611 } MTL_QUEUE[2];
4612 uint8_t RESERVED_19[640];
4613 __IO uint32_t DMA_MODE; /**< DMA mode register, offset: 0x1000 */
4614 __IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus mode, offset: 0x1004 */
4615 __IO uint32_t DMA_INTR_STAT; /**< DMA Interrupt status, offset: 0x1008 */
4616 __I uint32_t DMA_DBG_STAT; /**< DMA Debug Status, offset: 0x100C */
4617 uint8_t RESERVED_20[240];
4618 struct { /* offset: 0x1100, array step: 0x80 */
4619 __IO uint32_t DMA_CHX_CTRL; /**< DMA Channelx Control, array offset: 0x1100, array step: 0x80 */
4620 __IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channelx Transmit Control, array offset: 0x1104, array step: 0x80 */
4621 __IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channelx Receive Control, array offset: 0x1108, array step: 0x80 */
4622 uint8_t RESERVED_0[8];
4623 __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< , array offset: 0x1114, array step: 0x80 */
4624 uint8_t RESERVED_1[4];
4625 __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< , array offset: 0x111C, array step: 0x80 */
4626 __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< , array offset: 0x1120, array step: 0x80 */
4627 uint8_t RESERVED_2[4];
4628 __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< , array offset: 0x1128, array step: 0x80 */
4629 __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< , array offset: 0x112C, array step: 0x80 */
4630 __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH; /**< Channelx Rx descriptor Ring Length, array offset: 0x1130, array step: 0x80 */
4631 __IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1134, array step: 0x80 */
4632 __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
4633 __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
4634 uint8_t RESERVED_3[4];
4635 __I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< Channelx Current Host Transmit descriptor, array offset: 0x1144, array step: 0x80 */
4636 uint8_t RESERVED_4[4];
4637 __I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< , array offset: 0x114C, array step: 0x80 */
4638 uint8_t RESERVED_5[4];
4639 __I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< , array offset: 0x1154, array step: 0x80 */
4640 uint8_t RESERVED_6[4];
4641 __I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< Channelx Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
4642 __IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: 0x1160, array step: 0x80 */
4643 uint8_t RESERVED_7[8];
4644 __IO uint32_t DMA_CHX_MISS_FRAME_CNT; /**< Channelx missed frame count., array offset: 0x116C, array step: 0x80 */
4645 uint8_t RESERVED_8[16];
4646 } DMA_CH[2];
4647} ENET_Type;
4648
4649/* ----------------------------------------------------------------------------
4650 -- ENET Register Masks
4651 ---------------------------------------------------------------------------- */
4652
4653/*!
4654 * @addtogroup ENET_Register_Masks ENET Register Masks
4655 * @{
4656 */
4657
4658/*! @name MAC_CONFIG - MAC configuration register */
4659/*! @{ */
4660#define ENET_MAC_CONFIG_RE_MASK (0x1U)
4661#define ENET_MAC_CONFIG_RE_SHIFT (0U)
4662/*! RE - Receiver Enable When this bit is set, the receiver state machine of the MAC is enabled for
4663 * receiving frames from the MII.
4664 */
4665#define ENET_MAC_CONFIG_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_RE_SHIFT)) & ENET_MAC_CONFIG_RE_MASK)
4666#define ENET_MAC_CONFIG_TE_MASK (0x2U)
4667#define ENET_MAC_CONFIG_TE_SHIFT (1U)
4668/*! TE - Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII.
4669 */
4670#define ENET_MAC_CONFIG_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_TE_SHIFT)) & ENET_MAC_CONFIG_TE_MASK)
4671#define ENET_MAC_CONFIG_PRELEN_MASK (0xCU)
4672#define ENET_MAC_CONFIG_PRELEN_SHIFT (2U)
4673/*! PRELEN - Preamble Length for Transmit packets These bits control the number of preamble bytes
4674 * that are added to the beginning of every Tx packet.
4675 */
4676#define ENET_MAC_CONFIG_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PRELEN_SHIFT)) & ENET_MAC_CONFIG_PRELEN_MASK)
4677#define ENET_MAC_CONFIG_DC_MASK (0x10U)
4678#define ENET_MAC_CONFIG_DC_SHIFT (4U)
4679/*! DC - Deferral Check When this bit is set, the deferral check function is enabled in the MAC.
4680 */
4681#define ENET_MAC_CONFIG_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DC_SHIFT)) & ENET_MAC_CONFIG_DC_MASK)
4682#define ENET_MAC_CONFIG_BL_MASK (0x60U)
4683#define ENET_MAC_CONFIG_BL_SHIFT (5U)
4684/*! BL - Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time
4685 * delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before
4686 * rescheduling a transmission attempt during retries after a collision.
4687 */
4688#define ENET_MAC_CONFIG_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BL_SHIFT)) & ENET_MAC_CONFIG_BL_MASK)
4689#define ENET_MAC_CONFIG_DR_MASK (0x100U)
4690#define ENET_MAC_CONFIG_DR_SHIFT (8U)
4691/*! DR - Disable Retry When this bit is set, the MAC will attempt only one transmission.
4692 */
4693#define ENET_MAC_CONFIG_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DR_SHIFT)) & ENET_MAC_CONFIG_DR_MASK)
4694#define ENET_MAC_CONFIG_DCRS_MASK (0x200U)
4695#define ENET_MAC_CONFIG_DCRS_SHIFT (9U)
4696/*! DCRS - Disable Carrier Sense During Transmission When this bit is set, the MAC transmitter
4697 * ignores the MII CRS signal during packet transmission in the half-duplex mode.
4698 */
4699#define ENET_MAC_CONFIG_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DCRS_SHIFT)) & ENET_MAC_CONFIG_DCRS_MASK)
4700#define ENET_MAC_CONFIG_DO_MASK (0x400U)
4701#define ENET_MAC_CONFIG_DO_SHIFT (10U)
4702/*! DO - Disable Receive Own When this bit is set, the MAC disables the reception of frames when the
4703 * gmii_txen_o is asserted in Half-Duplex mode.
4704 */
4705#define ENET_MAC_CONFIG_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DO_SHIFT)) & ENET_MAC_CONFIG_DO_MASK)
4706#define ENET_MAC_CONFIG_ECRSFD_MASK (0x800U)
4707#define ENET_MAC_CONFIG_ECRSFD_SHIFT (11U)
4708/*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set, the
4709 * MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode.
4710 */
4711#define ENET_MAC_CONFIG_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ECRSFD_SHIFT)) & ENET_MAC_CONFIG_ECRSFD_MASK)
4712#define ENET_MAC_CONFIG_LM_MASK (0x1000U)
4713#define ENET_MAC_CONFIG_LM_SHIFT (12U)
4714/*! LM - Loopback Mode When this bit is set, the MAC operates in loopback mode at MII.
4715 */
4716#define ENET_MAC_CONFIG_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_LM_SHIFT)) & ENET_MAC_CONFIG_LM_MASK)
4717#define ENET_MAC_CONFIG_DM_MASK (0x2000U)
4718#define ENET_MAC_CONFIG_DM_SHIFT (13U)
4719/*! DM - Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can
4720 * transmit and receive simultaneously.
4721 */
4722#define ENET_MAC_CONFIG_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DM_SHIFT)) & ENET_MAC_CONFIG_DM_MASK)
4723#define ENET_MAC_CONFIG_FES_MASK (0x4000U)
4724#define ENET_MAC_CONFIG_FES_SHIFT (14U)
4725/*! FES - Speed Indicates the speed in Fast Ethernet (MII) mode: This bit is reserved (RO) by
4726 * default and is enabled only when RMII/SMII is enabled during configuration.
4727 */
4728#define ENET_MAC_CONFIG_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_FES_SHIFT)) & ENET_MAC_CONFIG_FES_MASK)
4729#define ENET_MAC_CONFIG_PS_MASK (0x8000U)
4730#define ENET_MAC_CONFIG_PS_SHIFT (15U)
4731/*! PS - Portselect.
4732 */
4733#define ENET_MAC_CONFIG_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PS_SHIFT)) & ENET_MAC_CONFIG_PS_MASK)
4734#define ENET_MAC_CONFIG_JE_MASK (0x10000U)
4735#define ENET_MAC_CONFIG_JE_SHIFT (16U)
4736/*! JE - Jumbo Frame Enable When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022
4737 * bytes for tagged frames) without reporting a giant frame error in the receive frame status.
4738 */
4739#define ENET_MAC_CONFIG_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JE_SHIFT)) & ENET_MAC_CONFIG_JE_MASK)
4740#define ENET_MAC_CONFIG_JD_MASK (0x20000U)
4741#define ENET_MAC_CONFIG_JD_SHIFT (17U)
4742/*! JD - Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter,
4743 * and can transfer frames of up to 16,384 bytes.
4744 */
4745#define ENET_MAC_CONFIG_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JD_SHIFT)) & ENET_MAC_CONFIG_JD_MASK)
4746#define ENET_MAC_CONFIG_BE_MASK (0x40000U)
4747#define ENET_MAC_CONFIG_BE_SHIFT (18U)
4748/*! BE - Packet Burst Enable When this bit is set, the MAC allows packet bursting during
4749 * transmission in the MII half-duplex mode.
4750 */
4751#define ENET_MAC_CONFIG_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BE_SHIFT)) & ENET_MAC_CONFIG_BE_MASK)
4752#define ENET_MAC_CONFIG_WD_MASK (0x80000U)
4753#define ENET_MAC_CONFIG_WD_SHIFT (19U)
4754/*! WD - Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver,
4755 * and can receive frames of up to 16,384 bytes.
4756 */
4757#define ENET_MAC_CONFIG_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_WD_SHIFT)) & ENET_MAC_CONFIG_WD_MASK)
4758#define ENET_MAC_CONFIG_ACS_MASK (0x100000U)
4759#define ENET_MAC_CONFIG_ACS_SHIFT (20U)
4760/*! ACS - Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field
4761 * on the incoming packets only if the value of the length field is less than 1,536 bytes.
4762 */
4763#define ENET_MAC_CONFIG_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ACS_SHIFT)) & ENET_MAC_CONFIG_ACS_MASK)
4764#define ENET_MAC_CONFIG_CST_MASK (0x200000U)
4765#define ENET_MAC_CONFIG_CST_SHIFT (21U)
4766/*! CST - CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all
4767 * packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding
4768 * the packet to the application.
4769 */
4770#define ENET_MAC_CONFIG_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_CST_SHIFT)) & ENET_MAC_CONFIG_CST_MASK)
4771#define ENET_MAC_CONFIG_S2KP_MASK (0x400000U)
4772#define ENET_MAC_CONFIG_S2KP_SHIFT (22U)
4773/*! S2KP - IEEE 802.
4774 */
4775#define ENET_MAC_CONFIG_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_S2KP_SHIFT)) & ENET_MAC_CONFIG_S2KP_MASK)
4776#define ENET_MAC_CONFIG_GPSLCE_MASK (0x800000U)
4777#define ENET_MAC_CONFIG_GPSLCE_SHIFT (23U)
4778/*! GPSLCE - Giant Packet Size Limit Control Enable When this bit is set, the MAC considers the
4779 * value in GPSL field in MAC Ext Configuration register to declare a received packet as Giant packet.
4780 */
4781#define ENET_MAC_CONFIG_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_GPSLCE_SHIFT)) & ENET_MAC_CONFIG_GPSLCE_MASK)
4782#define ENET_MAC_CONFIG_IPG_MASK (0x7000000U)
4783#define ENET_MAC_CONFIG_IPG_SHIFT (24U)
4784/*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission.
4785 */
4786#define ENET_MAC_CONFIG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPG_SHIFT)) & ENET_MAC_CONFIG_IPG_MASK)
4787#define ENET_MAC_CONFIG_IPC_MASK (0x8000000U)
4788#define ENET_MAC_CONFIG_IPC_SHIFT (27U)
4789/*! IPC - Checksum Offload When set, this bit enables the IPv4 header checksum checking and IPv4 or
4790 * IPv6 TCP, UDP, or ICMP payload checksum checking.
4791 */
4792#define ENET_MAC_CONFIG_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPC_SHIFT)) & ENET_MAC_CONFIG_IPC_MASK)
4793/*! @} */
4794
4795/*! @name MAC_EXT_CONFIG - */
4796/*! @{ */
4797#define ENET_MAC_EXT_CONFIG_GPSL_MASK (0x3FFFU)
4798#define ENET_MAC_EXT_CONFIG_GPSL_SHIFT (0U)
4799/*! GPSL - Giant Packet Size Limit If the received packet size is greater than the value programmed
4800 * in this field in units of bytes, the MAC declares the received packet as Giant packet.
4801 */
4802#define ENET_MAC_EXT_CONFIG_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIG_GPSL_MASK)
4803#define ENET_MAC_EXT_CONFIG_DCRCC_MASK (0x10000U)
4804#define ENET_MAC_EXT_CONFIG_DCRCC_SHIFT (16U)
4805/*! DCRCC - Disable CRC Checking for Received Packets When this bit is set, the MAC receiver does
4806 * not check the CRC field in the received packets.
4807 */
4808#define ENET_MAC_EXT_CONFIG_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIG_DCRCC_MASK)
4809#define ENET_MAC_EXT_CONFIG_SPEN_MASK (0x20000U)
4810#define ENET_MAC_EXT_CONFIG_SPEN_SHIFT (17U)
4811/*! SPEN - Slow Protocol Detection Enable When this bit is set, MAC processes the Slow Protocol
4812 * packets (Ether Type 0x8809) and provides the Rx status.
4813 */
4814#define ENET_MAC_EXT_CONFIG_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIG_SPEN_MASK)
4815#define ENET_MAC_EXT_CONFIG_USP_MASK (0x40000U)
4816#define ENET_MAC_EXT_CONFIG_USP_SHIFT (18U)
4817/*! USP - Unicast Slow Protocol Packet Detect When this bit is set, the MAC detects the Slow
4818 * Protocol packets with unicast address of the station specified in the MAC Address High Table 747 and
4819 * MAC Address Low Table 748 registers.
4820 */
4821#define ENET_MAC_EXT_CONFIG_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_USP_SHIFT)) & ENET_MAC_EXT_CONFIG_USP_MASK)
4822/*! @} */
4823
4824/*! @name MAC_FRAME_FILTER - MAC frame filter register */
4825/*! @{ */
4826#define ENET_MAC_FRAME_FILTER_PR_MASK (0x1U)
4827#define ENET_MAC_FRAME_FILTER_PR_SHIFT (0U)
4828/*! PR - Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frames
4829 * regardless of its destination or source address.
4830 */
4831#define ENET_MAC_FRAME_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PR_SHIFT)) & ENET_MAC_FRAME_FILTER_PR_MASK)
4832#define ENET_MAC_FRAME_FILTER_DAIF_MASK (0x8U)
4833#define ENET_MAC_FRAME_FILTER_DAIF_SHIFT (3U)
4834/*! DAIF - DA Inverse Filtering When this bit is set, the Address Check block operates in inverse
4835 * filtering mode for the DA address comparison for both unicast and multicast frames.
4836 */
4837#define ENET_MAC_FRAME_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_DAIF_MASK)
4838#define ENET_MAC_FRAME_FILTER_PM_MASK (0x10U)
4839#define ENET_MAC_FRAME_FILTER_PM_SHIFT (4U)
4840/*! PM - Pass All Multicast When set, this bit indicates that all received frames with a multicast
4841 * destination address (first bit in the destination address field is '1') are passed.
4842 */
4843#define ENET_MAC_FRAME_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PM_SHIFT)) & ENET_MAC_FRAME_FILTER_PM_MASK)
4844#define ENET_MAC_FRAME_FILTER_DBF_MASK (0x20U)
4845#define ENET_MAC_FRAME_FILTER_DBF_SHIFT (5U)
4846/*! DBF - Disable Broadcast Frames When this bit is set, the AFM module filters all incoming broadcast frames.
4847 */
4848#define ENET_MAC_FRAME_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DBF_SHIFT)) & ENET_MAC_FRAME_FILTER_DBF_MASK)
4849#define ENET_MAC_FRAME_FILTER_PCF_MASK (0xC0U)
4850#define ENET_MAC_FRAME_FILTER_PCF_SHIFT (6U)
4851/*! PCF - Pass Control Frames These bits control the forwarding of all control frames (including
4852 * unicast and multicast PAUSE frames).
4853 */
4854#define ENET_MAC_FRAME_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PCF_SHIFT)) & ENET_MAC_FRAME_FILTER_PCF_MASK)
4855#define ENET_MAC_FRAME_FILTER_SAIF_MASK (0x100U)
4856#define ENET_MAC_FRAME_FILTER_SAIF_SHIFT (8U)
4857/*! SAIF - SA Inverse Filtering When this bit is set, the Address Check block operates in the
4858 * inverse filtering mode for SA address comparison.
4859 */
4860#define ENET_MAC_FRAME_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAIF_MASK)
4861#define ENET_MAC_FRAME_FILTER_SAF_MASK (0x200U)
4862#define ENET_MAC_FRAME_FILTER_SAF_SHIFT (9U)
4863/*! SAF - Source Address Filter Enable When this bit is set, the MAC compares the SA field of the
4864 * received packets with the values programmed in the enabled SA registers.
4865 */
4866#define ENET_MAC_FRAME_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAF_MASK)
4867#define ENET_MAC_FRAME_FILTER_RA_MASK (0x80000000U)
4868#define ENET_MAC_FRAME_FILTER_RA_SHIFT (31U)
4869/*! RA - Receive all When this bit is set, the MAC Receiver module passes to the Application all
4870 * frames received irrespective of whether they pass the address filter.
4871 */
4872#define ENET_MAC_FRAME_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_RA_SHIFT)) & ENET_MAC_FRAME_FILTER_RA_MASK)
4873/*! @} */
4874
4875/*! @name MAC_WD_TIMEROUT - MAC watchdog Timeout register */
4876/*! @{ */
4877#define ENET_MAC_WD_TIMEROUT_WTO_MASK (0xFU)
4878#define ENET_MAC_WD_TIMEROUT_WTO_SHIFT (0U)
4879/*! WTO - Watchdog Timeout When the PWE bit is set and the WD bit of the MAC Configuration register
4880 * Table 722 is reset, this field is used as watchdog timeout for a received packet.
4881 */
4882#define ENET_MAC_WD_TIMEROUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_WTO_SHIFT)) & ENET_MAC_WD_TIMEROUT_WTO_MASK)
4883#define ENET_MAC_WD_TIMEROUT_PWE_MASK (0x100U)
4884#define ENET_MAC_WD_TIMEROUT_PWE_SHIFT (8U)
4885/*! PWE - Programmable Watchdog Enable When this bit is set and the WD bit of the MAC Configuration
4886 * register Table 722 is reset, the WTO field is used as watchdog timeout for a received packet.
4887 */
4888#define ENET_MAC_WD_TIMEROUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_PWE_SHIFT)) & ENET_MAC_WD_TIMEROUT_PWE_MASK)
4889/*! @} */
4890
4891/*! @name MAC_VLAN_TAG - MAC vlan tag register */
4892/*! @{ */
4893#define ENET_MAC_VLAN_TAG_VL_MASK (0xFFFFU)
4894#define ENET_MAC_VLAN_TAG_VL_SHIFT (0U)
4895/*! VL - VLAN Tag Identifier for Receive Packets.
4896 */
4897#define ENET_MAC_VLAN_TAG_VL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VL_SHIFT)) & ENET_MAC_VLAN_TAG_VL_MASK)
4898#define ENET_MAC_VLAN_TAG_ETV_MASK (0x10000U)
4899#define ENET_MAC_VLAN_TAG_ETV_SHIFT (16U)
4900/*! ETV - Enable 12-Bit VLAN Tag Comparison.
4901 */
4902#define ENET_MAC_VLAN_TAG_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_ETV_MASK)
4903#define ENET_MAC_VLAN_TAG_VTIM_MASK (0x20000U)
4904#define ENET_MAC_VLAN_TAG_VTIM_SHIFT (17U)
4905/*! VTIM - VLAN Tag Inverse Match Enable.
4906 */
4907#define ENET_MAC_VLAN_TAG_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_VTIM_MASK)
4908#define ENET_MAC_VLAN_TAG_ESVL_MASK (0x40000U)
4909#define ENET_MAC_VLAN_TAG_ESVL_SHIFT (18U)
4910/*! ESVL - Enable S-VLAN.
4911 */
4912#define ENET_MAC_VLAN_TAG_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_ESVL_MASK)
4913#define ENET_MAC_VLAN_TAG_ERSVLM_MASK (0x80000U)
4914#define ENET_MAC_VLAN_TAG_ERSVLM_SHIFT (19U)
4915/*! ERSVLM - Enable Receive S-VLAN Match.
4916 */
4917#define ENET_MAC_VLAN_TAG_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_ERSVLM_MASK)
4918#define ENET_MAC_VLAN_TAG_DOVLTC_MASK (0x100000U)
4919#define ENET_MAC_VLAN_TAG_DOVLTC_SHIFT (20U)
4920/*! DOVLTC - Disable VLAN Type Check.
4921 */
4922#define ENET_MAC_VLAN_TAG_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_DOVLTC_MASK)
4923#define ENET_MAC_VLAN_TAG_EVLS_MASK (0x600000U)
4924#define ENET_MAC_VLAN_TAG_EVLS_SHIFT (21U)
4925/*! EVLS - Enable VLAN Tag Stripping on Receive.
4926 */
4927#define ENET_MAC_VLAN_TAG_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLS_MASK)
4928#define ENET_MAC_VLAN_TAG_EVLRXS_MASK (0x1000000U)
4929#define ENET_MAC_VLAN_TAG_EVLRXS_SHIFT (24U)
4930/*! EVLRXS - Enable VLAN Tag in Rx status.
4931 */
4932#define ENET_MAC_VLAN_TAG_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLRXS_MASK)
4933#define ENET_MAC_VLAN_TAG_VTHM_MASK (0x2000000U)
4934#define ENET_MAC_VLAN_TAG_VTHM_SHIFT (25U)
4935/*! VTHM - Disable VLAN Type Check.
4936 */
4937#define ENET_MAC_VLAN_TAG_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTHM_SHIFT)) & ENET_MAC_VLAN_TAG_VTHM_MASK)
4938#define ENET_MAC_VLAN_TAG_EDVLP_MASK (0x4000000U)
4939#define ENET_MAC_VLAN_TAG_EDVLP_SHIFT (26U)
4940/*! EDVLP - Enable Double VLAN Processing.
4941 */
4942#define ENET_MAC_VLAN_TAG_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_EDVLP_MASK)
4943#define ENET_MAC_VLAN_TAG_ERIVLT_MASK (0x8000000U)
4944#define ENET_MAC_VLAN_TAG_ERIVLT_SHIFT (27U)
4945/*! ERIVLT - Enable Inner VLAN Tag.
4946 */
4947#define ENET_MAC_VLAN_TAG_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_ERIVLT_MASK)
4948#define ENET_MAC_VLAN_TAG_EIVLS_MASK (0x30000000U)
4949#define ENET_MAC_VLAN_TAG_EIVLS_SHIFT (28U)
4950/*! EIVLS - Enable Inner VLAN Tag Stripping on Receive.
4951 */
4952#define ENET_MAC_VLAN_TAG_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLS_MASK)
4953#define ENET_MAC_VLAN_TAG_EIVLRXS_MASK (0x80000000U)
4954#define ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT (31U)
4955/*! EIVLRXS - Enable Inner VLAN Tag in Rx Status.
4956 */
4957#define ENET_MAC_VLAN_TAG_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLRXS_MASK)
4958/*! @} */
4959
4960/*! @name MAC_TX_FLOW_CTRL_Q - Transmit flow control register */
4961/*! @{ */
4962#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK (0x1U)
4963#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT (0U)
4964/*! FCB - Flow Control Busy/Backpressure Activate This register field can be read by the application
4965 * (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is
4966 * cleared to 0 by the core (Self Clear).
4967 */
4968#define ENET_MAC_TX_FLOW_CTRL_Q_FCB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK)
4969#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U)
4970#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U)
4971/*! TFE - Transmit Flow Control Enable In Full-Duplex mode, when this bit is set, the MAC enables
4972 * the flow control operation to transmit Pause frames.
4973 */
4974#define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
4975#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U)
4976#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U)
4977/*! PLT - Pause Low Threshold This field configures the threshold of the PAUSE timer at which the
4978 * input flow control signal is checked for automatic retransmission of PAUSE Frame.
4979 */
4980#define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
4981#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U)
4982#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U)
4983/*! DZPQ - Disable Zero-Quanta Pause When set, this bit disables the automatic generation of
4984 * Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer.
4985 */
4986#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
4987#define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U)
4988#define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U)
4989/*! PT - Pause time This field holds the value to be used in the Pause Time field in the transmit control frame.
4990 */
4991#define ENET_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK)
4992/*! @} */
4993
4994/* The count of ENET_MAC_TX_FLOW_CTRL_Q */
4995#define ENET_MAC_TX_FLOW_CTRL_Q_COUNT (2U)
4996
4997/*! @name MAC_RX_FLOW_CTRL - Receive flow control register */
4998/*! @{ */
4999#define ENET_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U)
5000#define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U)
5001/*! RFE - Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex
5002 * mode, the MAC decodes the received Pause packet and disables its transmitter for a specified
5003 * (Pause) time.
5004 */
5005#define ENET_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK)
5006#define ENET_MAC_RX_FLOW_CTRL_UP_MASK (0x2U)
5007#define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT (1U)
5008/*! UP - Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast
5009 * address specified in the IEEE 802.
5010 */
5011#define ENET_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK)
5012/*! @} */
5013
5014/*! @name MAC_TXQ_PRIO_MAP - */
5015/*! @{ */
5016#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK (0xFFU)
5017#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT (0U)
5018/*! PSTQ0 - Priorities Selected in Transmit Queue 0 This field holds the priorities assigned to Tx Queue 0 by the software.
5019 */
5020#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK)
5021#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK (0xFF00U)
5022#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT (8U)
5023/*! PSTQ1 - Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit.
5024 */
5025#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK)
5026/*! @} */
5027
5028/*! @name MAC_RXQ_CTRL - Receive Queue Control 0 register 0x0000 */
5029/*! @{ */
5030#define ENET_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U)
5031#define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U)
5032/*! AVCPQ - AV Untagged Control Packets Queue.
5033 */
5034#define ENET_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK)
5035#define ENET_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU)
5036#define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U)
5037/*! PSRQ0 - Priorities Selected in the Receive Queue 0.
5038 */
5039#define ENET_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK)
5040#define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U)
5041#define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U)
5042/*! RXQ0EN - Receive Queue 0 Enable.
5043 */
5044#define ENET_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK)
5045#define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU)
5046#define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U)
5047/*! RXQ1EN - Receive Queue 1 Enable.
5048 */
5049#define ENET_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK)
5050#define ENET_MAC_RXQ_CTRL_AVPTPQ_MASK (0x70U)
5051#define ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT (4U)
5052/*! AVPTPQ - AV PTP Packets Queue.
5053 */
5054#define ENET_MAC_RXQ_CTRL_AVPTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVPTPQ_MASK)
5055#define ENET_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U)
5056#define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U)
5057/*! PSRQ1 - Priorities Selected in the Receive Queue 1.
5058 */
5059#define ENET_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK)
5060#define ENET_MAC_RXQ_CTRL_UPQ_MASK (0x7000U)
5061#define ENET_MAC_RXQ_CTRL_UPQ_SHIFT (12U)
5062/*! UPQ - Untagged Packet Queue.
5063 */
5064#define ENET_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK)
5065#define ENET_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U)
5066#define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U)
5067/*! MCBCQ - Multicast and Broadcast Queue.
5068 */
5069#define ENET_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK)
5070#define ENET_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U)
5071#define ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U)
5072/*! PSRQ2 - Priorities Selected in the Receive Queue 2.
5073 */
5074#define ENET_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ2_MASK)
5075#define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U)
5076#define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U)
5077/*! MCBCQEN - Multicast and Broadcast Queue Enable.
5078 */
5079#define ENET_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK)
5080#define ENET_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U)
5081#define ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U)
5082/*! PSRQ3 - Priorities Selected in the Receive Queue 3.
5083 */
5084#define ENET_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ3_MASK)
5085/*! @} */
5086
5087/* The count of ENET_MAC_RXQ_CTRL */
5088#define ENET_MAC_RXQ_CTRL_COUNT (3U)
5089
5090/*! @name MAC_INTR_STAT - Interrupt status register 0x0000 */
5091/*! @{ */
5092#define ENET_MAC_INTR_STAT_PHYIS_MASK (0x8U)
5093#define ENET_MAC_INTR_STAT_PHYIS_SHIFT (3U)
5094/*! PHYIS - PHY Interrupt.
5095 */
5096#define ENET_MAC_INTR_STAT_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PHYIS_SHIFT)) & ENET_MAC_INTR_STAT_PHYIS_MASK)
5097#define ENET_MAC_INTR_STAT_PMTIS_MASK (0x10U)
5098#define ENET_MAC_INTR_STAT_PMTIS_SHIFT (4U)
5099/*! PMTIS - PMT Interrupt Status.
5100 */
5101#define ENET_MAC_INTR_STAT_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PMTIS_SHIFT)) & ENET_MAC_INTR_STAT_PMTIS_MASK)
5102#define ENET_MAC_INTR_STAT_LPIIS_MASK (0x20U)
5103#define ENET_MAC_INTR_STAT_LPIIS_SHIFT (5U)
5104/*! LPIIS - LPI Interrupt Status.
5105 */
5106#define ENET_MAC_INTR_STAT_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_LPIIS_SHIFT)) & ENET_MAC_INTR_STAT_LPIIS_MASK)
5107#define ENET_MAC_INTR_STAT_TSIS_MASK (0x1000U)
5108#define ENET_MAC_INTR_STAT_TSIS_SHIFT (12U)
5109/*! TSIS - Timestamp interrupt status.
5110 */
5111#define ENET_MAC_INTR_STAT_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TSIS_SHIFT)) & ENET_MAC_INTR_STAT_TSIS_MASK)
5112#define ENET_MAC_INTR_STAT_TXSTSIS_MASK (0x2000U)
5113#define ENET_MAC_INTR_STAT_TXSTSIS_SHIFT (13U)
5114/*! TXSTSIS - Transmit Status Interrupt.
5115 */
5116#define ENET_MAC_INTR_STAT_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_TXSTSIS_MASK)
5117#define ENET_MAC_INTR_STAT_RXSTSIS_MASK (0x4000U)
5118#define ENET_MAC_INTR_STAT_RXSTSIS_SHIFT (14U)
5119/*! RXSTSIS - Receive Status Interrupt.
5120 */
5121#define ENET_MAC_INTR_STAT_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_RXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_RXSTSIS_MASK)
5122/*! @} */
5123
5124/*! @name MAC_INTR_EN - Interrupt enable register 0x0000 */
5125/*! @{ */
5126#define ENET_MAC_INTR_EN_PHYIE_MASK (0x8U)
5127#define ENET_MAC_INTR_EN_PHYIE_SHIFT (3U)
5128/*! PHYIE - PHY Interrupt Enable.
5129 */
5130#define ENET_MAC_INTR_EN_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PHYIE_SHIFT)) & ENET_MAC_INTR_EN_PHYIE_MASK)
5131#define ENET_MAC_INTR_EN_PMTIE_MASK (0x10U)
5132#define ENET_MAC_INTR_EN_PMTIE_SHIFT (4U)
5133/*! PMTIE - PMT Interrupt Enable.
5134 */
5135#define ENET_MAC_INTR_EN_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PMTIE_SHIFT)) & ENET_MAC_INTR_EN_PMTIE_MASK)
5136#define ENET_MAC_INTR_EN_LPIIE_MASK (0x20U)
5137#define ENET_MAC_INTR_EN_LPIIE_SHIFT (5U)
5138/*! LPIIE - LPI Interrupt Enable.
5139 */
5140#define ENET_MAC_INTR_EN_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_LPIIE_SHIFT)) & ENET_MAC_INTR_EN_LPIIE_MASK)
5141#define ENET_MAC_INTR_EN_TSIE_MASK (0x1000U)
5142#define ENET_MAC_INTR_EN_TSIE_SHIFT (12U)
5143/*! TSIE - Timestamp Interrupt Enable.
5144 */
5145#define ENET_MAC_INTR_EN_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TSIE_SHIFT)) & ENET_MAC_INTR_EN_TSIE_MASK)
5146#define ENET_MAC_INTR_EN_TXSTSIE_MASK (0x2000U)
5147#define ENET_MAC_INTR_EN_TXSTSIE_SHIFT (13U)
5148/*! TXSTSIE - Transmit Status Interrupt Enable.
5149 */
5150#define ENET_MAC_INTR_EN_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TXSTSIE_SHIFT)) & ENET_MAC_INTR_EN_TXSTSIE_MASK)
5151#define ENET_MAC_INTR_EN_RXSTSIS_MASK (0x4000U)
5152#define ENET_MAC_INTR_EN_RXSTSIS_SHIFT (14U)
5153/*! RXSTSIS - Receive Status Interrupt Enable.
5154 */
5155#define ENET_MAC_INTR_EN_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_RXSTSIS_SHIFT)) & ENET_MAC_INTR_EN_RXSTSIS_MASK)
5156/*! @} */
5157
5158/*! @name MAC_RXTX_STAT - Receive Transmit Status register */
5159/*! @{ */
5160#define ENET_MAC_RXTX_STAT_TJT_MASK (0x1U)
5161#define ENET_MAC_RXTX_STAT_TJT_SHIFT (0U)
5162/*! TJT - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt
5163 * signal because of the setting of PHYIS bit in MAC Interrupt Status register Table 731.
5164 */
5165#define ENET_MAC_RXTX_STAT_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_TJT_SHIFT)) & ENET_MAC_RXTX_STAT_TJT_MASK)
5166#define ENET_MAC_RXTX_STAT_NCARR_MASK (0x2U)
5167#define ENET_MAC_RXTX_STAT_NCARR_SHIFT (1U)
5168/*! NCARR - No Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758, this
5169 * bit indicates that the carrier signal from the PHY is not present at the end of preamble
5170 * transmission.
5171 */
5172#define ENET_MAC_RXTX_STAT_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_NCARR_SHIFT)) & ENET_MAC_RXTX_STAT_NCARR_MASK)
5173#define ENET_MAC_RXTX_STAT_LCARR_MASK (0x4U)
5174#define ENET_MAC_RXTX_STAT_LCARR_SHIFT (2U)
5175/*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758,
5176 * this bit indicates that the loss of carrier occurred during packet transmission, that is, the
5177 * PHY Carrier signal was inactive for one or more transmission clock periods during packet
5178 * transmission.
5179 */
5180#define ENET_MAC_RXTX_STAT_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCARR_SHIFT)) & ENET_MAC_RXTX_STAT_LCARR_MASK)
5181#define ENET_MAC_RXTX_STAT_EXDEF_MASK (0x8U)
5182#define ENET_MAC_RXTX_STAT_EXDEF_SHIFT (3U)
5183/*! EXDEF - Excessive Deferral When the DTXSTS bit is set in the MTL Operation Mode register Table
5184 * 758 and the DC bit is set in the MAC Configuration register Table 758, this bit indicates that
5185 * the transmission ended because of excessive deferral of over 24,288 bit times (155,680 when
5186 * Jumbo packet is enabled).
5187 */
5188#define ENET_MAC_RXTX_STAT_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXDEF_SHIFT)) & ENET_MAC_RXTX_STAT_EXDEF_MASK)
5189#define ENET_MAC_RXTX_STAT_LCOL_MASK (0x10U)
5190#define ENET_MAC_RXTX_STAT_LCOL_SHIFT (4U)
5191/*! LCOL - Late Collision When the DTXSTS bit is set in the MTL Operation Mode register Table 758,
5192 * this bit indicates that the packet transmission aborted because a collision occurred after the
5193 * collision window (64 bytes including Preamble in MII mode).
5194 */
5195#define ENET_MAC_RXTX_STAT_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCOL_SHIFT)) & ENET_MAC_RXTX_STAT_LCOL_MASK)
5196#define ENET_MAC_RXTX_STAT_EXCOL_MASK (0x20U)
5197#define ENET_MAC_RXTX_STAT_EXCOL_SHIFT (5U)
5198/*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MTL Operation Mode register Table
5199 * 758, this bit indicates that the transmission aborted after 16 successive collisions while
5200 * attempting to transmit the current packet.
5201 */
5202#define ENET_MAC_RXTX_STAT_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXCOL_SHIFT)) & ENET_MAC_RXTX_STAT_EXCOL_MASK)
5203#define ENET_MAC_RXTX_STAT_RWT_MASK (0x100U)
5204#define ENET_MAC_RXTX_STAT_RWT_SHIFT (8U)
5205/*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048
5206 * bytes is received (10,240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the
5207 * MAC Configuration register Table 722.
5208 */
5209#define ENET_MAC_RXTX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_RWT_SHIFT)) & ENET_MAC_RXTX_STAT_RWT_MASK)
5210/*! @} */
5211
5212/*! @name MAC_PMT_CRTL_STAT - */
5213/*! @{ */
5214#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK (0x1U)
5215#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT (0U)
5216/*! PWRDWN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
5217 * entered the LPI state because of the setting of the LPIEN bit.
5218 */
5219#define ENET_MAC_PMT_CRTL_STAT_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK)
5220#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK (0x2U)
5221#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT (1U)
5222/*! MGKPKTEN - Magic Packet Enable.
5223 */
5224#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK)
5225#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK (0x4U)
5226#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT (2U)
5227/*! RWKPKTEN - Remote Wake-Up Packet Enable When this bit is set, a power management event is
5228 * generated when the MAC receives a remote wake-up packet.
5229 */
5230#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK)
5231#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK (0x20U)
5232#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT (5U)
5233/*! MGKPRCVD - Magic Packet Received.
5234 */
5235#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK)
5236#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK (0x40U)
5237#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT (6U)
5238/*! RWKPRCVD - Remote Wake-Up Packet Received.
5239 */
5240#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK)
5241#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK (0x200U)
5242#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT (9U)
5243/*! GLBLUCAST - Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF)
5244 * address recognition is detected as a remote wake-up packet.
5245 */
5246#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK)
5247#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK (0x400U)
5248#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT (10U)
5249/*! RWKPFE - Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the
5250 * MAC receiver drops all received frames until it receives the expected wake-up frame.
5251 */
5252#define ENET_MAC_PMT_CRTL_STAT_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK)
5253#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK (0x1F000000U)
5254#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT (24U)
5255/*! RWKPTR - Remote Wake-up FIFO Pointer This field gives the current value (0 to 7) of the Remote
5256 * Wake-up Packet Filter register pointer.
5257 */
5258#define ENET_MAC_PMT_CRTL_STAT_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK)
5259#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK (0x80000000U)
5260#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT (31U)
5261/*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the
5262 * remote wake-up packet filter register pointer is reset to 3'b000.
5263 */
5264#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK)
5265/*! @} */
5266
5267/*! @name MAC_RWAKE_FRFLT - Remote wake-up frame filter */
5268/*! @{ */
5269#define ENET_MAC_RWAKE_FRFLT_ADDR_MASK (0xFFFFFFFFU)
5270#define ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT (0U)
5271/*! ADDR - WKUPFMFILTER address.
5272 */
5273#define ENET_MAC_RWAKE_FRFLT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT)) & ENET_MAC_RWAKE_FRFLT_ADDR_MASK)
5274/*! @} */
5275
5276/*! @name MAC_LPI_CTRL_STAT - LPI Control and Status Register */
5277/*! @{ */
5278#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK (0x1U)
5279#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT (0U)
5280/*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
5281 * entered the LPI state because of the setting of the LPIEN bit.
5282 */
5283#define ENET_MAC_LPI_CTRL_STAT_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK)
5284#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK (0x2U)
5285#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT (1U)
5286/*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited
5287 * the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired.
5288 */
5289#define ENET_MAC_LPI_CTRL_STAT_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK)
5290#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK (0x4U)
5291#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT (2U)
5292/*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received
5293 * an LPI pattern and entered the LPI state.
5294 */
5295#define ENET_MAC_LPI_CTRL_STAT_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK)
5296#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK (0x8U)
5297#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT (3U)
5298/*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped
5299 * receiving the LPI pattern on the MII interface, exited the LPI state, and resumed the normal
5300 * reception.
5301 */
5302#define ENET_MAC_LPI_CTRL_STAT_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK)
5303#define ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK (0x100U)
5304#define ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT (8U)
5305/*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the LPI pattern on the MII interface.
5306 */
5307#define ENET_MAC_LPI_CTRL_STAT_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK)
5308#define ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK (0x200U)
5309#define ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT (9U)
5310/*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI pattern on the MII interface.
5311 */
5312#define ENET_MAC_LPI_CTRL_STAT_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK)
5313#define ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK (0x10000U)
5314#define ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT (16U)
5315/*! LPIEN - LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state.
5316 */
5317#define ENET_MAC_LPI_CTRL_STAT_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK)
5318#define ENET_MAC_LPI_CTRL_STAT_PLS_MASK (0x20000U)
5319#define ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT (17U)
5320/*! PLS - PHY Link Status This bit indicates the link status of the PHY.
5321 */
5322#define ENET_MAC_LPI_CTRL_STAT_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_PLS_MASK)
5323#define ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK (0x80000U)
5324#define ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT (19U)
5325/*! LPITXA - LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming
5326 * out of the LPI mode on the Transmit side.
5327 */
5328#define ENET_MAC_LPI_CTRL_STAT_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK)
5329#define ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK (0x100000U)
5330#define ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT (20U)
5331/*! LPIATE - LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state.
5332 */
5333#define ENET_MAC_LPI_CTRL_STAT_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK)
5334#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK (0x200000U)
5335#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT (21U)
5336/*! LPITCSE - LPI Tx Clock Stop Enable When this bit is set, the MAC asserts LPI Tx Clock Gating
5337 * Control signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be
5338 * stopped.
5339 */
5340#define ENET_MAC_LPI_CTRL_STAT_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK)
5341/*! @} */
5342
5343/*! @name MAC_LPI_TIMER_CTRL - LPI Timers Control register */
5344/*! @{ */
5345#define ENET_MAC_LPI_TIMER_CTRL_TWT_MASK (0xFFFFU)
5346#define ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT (0U)
5347/*! TWT - LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC
5348 * waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal
5349 * transmission.
5350 */
5351#define ENET_MAC_LPI_TIMER_CTRL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_TWT_MASK)
5352#define ENET_MAC_LPI_TIMER_CTRL_LST_MASK (0x3FF0000U)
5353#define ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT (16U)
5354/*! LST - LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link
5355 * status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY.
5356 */
5357#define ENET_MAC_LPI_TIMER_CTRL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_LST_MASK)
5358/*! @} */
5359
5360/*! @name MAC_LPI_ENTR_TIMR - LPI entry Timer register */
5361/*! @{ */
5362#define ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK (0xFFFF8U)
5363#define ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT (3U)
5364/*! LPIET - LPI Entry Timer This field specifies the time in microseconds the MAC will wait to enter
5365 * LPI mode, after it has transmitted all the frames.
5366 */
5367#define ENET_MAC_LPI_ENTR_TIMR_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT)) & ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK)
5368/*! @} */
5369
5370/*! @name MAC_1US_TIC_COUNTR - */
5371/*! @{ */
5372#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK (0xFFFU)
5373#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT (0U)
5374/*! TIC_1US_CNTR - 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us.
5375 */
5376#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT)) & ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK)
5377/*! @} */
5378
5379/*! @name MAC_VERSION - MAC version register */
5380/*! @{ */
5381#define ENET_MAC_VERSION_SNPVER_MASK (0xFFU)
5382#define ENET_MAC_VERSION_SNPVER_SHIFT (0U)
5383/*! SNPVER - NXP defined version.
5384 */
5385#define ENET_MAC_VERSION_SNPVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPVER_SHIFT)) & ENET_MAC_VERSION_SNPVER_MASK)
5386#define ENET_MAC_VERSION_USERVER_MASK (0xFF00U)
5387#define ENET_MAC_VERSION_USERVER_SHIFT (8U)
5388/*! USERVER - User defined version.
5389 */
5390#define ENET_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK)
5391/*! @} */
5392
5393/*! @name MAC_DBG - MAC debug register */
5394/*! @{ */
5395#define ENET_MAC_DBG_REPESTS_MASK (0x1U)
5396#define ENET_MAC_DBG_REPESTS_SHIFT (0U)
5397/*! REPESTS - MAC MII Receive Protocol Engine Status When this bit is set, it indicates that the MAC
5398 * MII receive protocol engine is actively receiving data, and it is not in the Idle state.
5399 */
5400#define ENET_MAC_DBG_REPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_REPESTS_SHIFT)) & ENET_MAC_DBG_REPESTS_MASK)
5401#define ENET_MAC_DBG_RFCFCSTS_MASK (0x6U)
5402#define ENET_MAC_DBG_RFCFCSTS_SHIFT (1U)
5403/*! RFCFCSTS - MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates
5404 * the active state of the small FIFO Read and Write controllers of the MAC Receive Packet
5405 * Controller module.
5406 */
5407#define ENET_MAC_DBG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_RFCFCSTS_SHIFT)) & ENET_MAC_DBG_RFCFCSTS_MASK)
5408#define ENET_MAC_DBG_TPESTS_MASK (0x10000U)
5409#define ENET_MAC_DBG_TPESTS_SHIFT (16U)
5410/*! TPESTS - MAC MII Transmit Protocol Engine Status When this bit is set, it indicates that the MAC
5411 * or MII transmit protocol engine is actively transmitting data, and it is not in the Idle
5412 * state.
5413 */
5414#define ENET_MAC_DBG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TPESTS_SHIFT)) & ENET_MAC_DBG_TPESTS_MASK)
5415#define ENET_MAC_DBG_TFCSTS_MASK (0x60000U)
5416#define ENET_MAC_DBG_TFCSTS_SHIFT (17U)
5417/*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module.
5418 */
5419#define ENET_MAC_DBG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TFCSTS_SHIFT)) & ENET_MAC_DBG_TFCSTS_MASK)
5420/*! @} */
5421
5422/*! @name MAC_HW_FEAT - MAC hardware feature register 0x0201 */
5423/*! @{ */
5424#define ENET_MAC_HW_FEAT_MIISEL_MASK (0x1U)
5425#define ENET_MAC_HW_FEAT_MIISEL_SHIFT (0U)
5426/*! MIISEL - 10 or 100 Mbps Support.
5427 */
5428#define ENET_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK)
5429#define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU)
5430#define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U)
5431/*! RXFIFOSIZE - MTL Receive FIFO Size.
5432 */
5433#define ENET_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK)
5434#define ENET_MAC_HW_FEAT_RXQCNT_MASK (0xFU)
5435#define ENET_MAC_HW_FEAT_RXQCNT_SHIFT (0U)
5436/*! RXQCNT - Number of MTL Receive Queues.
5437 */
5438#define ENET_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK)
5439#define ENET_MAC_HW_FEAT_HDSEL_MASK (0x4U)
5440#define ENET_MAC_HW_FEAT_HDSEL_SHIFT (2U)
5441/*! HDSEL - Half-duplex Support.
5442 */
5443#define ENET_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK)
5444#define ENET_MAC_HW_FEAT_VLHASH_MASK (0x10U)
5445#define ENET_MAC_HW_FEAT_VLHASH_SHIFT (4U)
5446/*! VLHASH - Hash Table Based Filtering option.
5447 */
5448#define ENET_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK)
5449#define ENET_MAC_HW_FEAT_SMASEL_MASK (0x20U)
5450#define ENET_MAC_HW_FEAT_SMASEL_SHIFT (5U)
5451/*! SMASEL - SMA (MDIO) Interface.
5452 */
5453#define ENET_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK)
5454#define ENET_MAC_HW_FEAT_RWKSEL_MASK (0x40U)
5455#define ENET_MAC_HW_FEAT_RWKSEL_SHIFT (6U)
5456/*! RWKSEL - PMT Remote Wake-up Packet Detection.
5457 */
5458#define ENET_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK)
5459#define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U)
5460#define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U)
5461/*! TXFIFOSIZE - MTL Transmit FIFO Size.
5462 */
5463#define ENET_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK)
5464#define ENET_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U)
5465#define ENET_MAC_HW_FEAT_TXQCNT_SHIFT (6U)
5466/*! TXQCNT - Number of MTL Transmit Queues.
5467 */
5468#define ENET_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK)
5469#define ENET_MAC_HW_FEAT_MGKSEL_MASK (0x80U)
5470#define ENET_MAC_HW_FEAT_MGKSEL_SHIFT (7U)
5471/*! MGKSEL - PMT magic packet detection.
5472 */
5473#define ENET_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK)
5474#define ENET_MAC_HW_FEAT_MMCSEL_MASK (0x100U)
5475#define ENET_MAC_HW_FEAT_MMCSEL_SHIFT (8U)
5476/*! MMCSEL - RMON Module Enable.
5477 */
5478#define ENET_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK)
5479#define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U)
5480#define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U)
5481/*! ARPOFFSEL - ARP Offload Enabled.
5482 */
5483#define ENET_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK)
5484#define ENET_MAC_HW_FEAT_OSTEN_MASK (0x800U)
5485#define ENET_MAC_HW_FEAT_OSTEN_SHIFT (11U)
5486/*! OSTEN - One-Step Timestamping Feature.
5487 */
5488#define ENET_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK)
5489#define ENET_MAC_HW_FEAT_PTOEN_MASK (0x1000U)
5490#define ENET_MAC_HW_FEAT_PTOEN_SHIFT (12U)
5491/*! PTOEN - PTP OffLoad Feature.
5492 */
5493#define ENET_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK)
5494#define ENET_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U)
5495#define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT (12U)
5496/*! RXCHCNT - Number of DMA Receive Channels.
5497 */
5498#define ENET_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK)
5499#define ENET_MAC_HW_FEAT_TSSEL_MASK (0x1000U)
5500#define ENET_MAC_HW_FEAT_TSSEL_SHIFT (12U)
5501/*! TSSEL - IEEE 1588-2008 Timestamp support .
5502 */
5503#define ENET_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK)
5504#define ENET_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U)
5505#define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U)
5506/*! ADVTHWORD - IEEE 1588 High Word Register Feature.
5507 */
5508#define ENET_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK)
5509#define ENET_MAC_HW_FEAT_EEESEL_MASK (0x2000U)
5510#define ENET_MAC_HW_FEAT_EEESEL_SHIFT (13U)
5511/*! EEESEL - Energy Efficient Ethernet Support .
5512 */
5513#define ENET_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK)
5514#define ENET_MAC_HW_FEAT_ADDR64_MASK (0xC000U)
5515#define ENET_MAC_HW_FEAT_ADDR64_SHIFT (14U)
5516/*! ADDR64 - Address width.
5517 */
5518#define ENET_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK)
5519#define ENET_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U)
5520#define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT (14U)
5521/*! TXCOESEL - Transmit Checksum Offload Support.
5522 */
5523#define ENET_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK)
5524#define ENET_MAC_HW_FEAT_DCBEN_MASK (0x10000U)
5525#define ENET_MAC_HW_FEAT_DCBEN_SHIFT (16U)
5526/*! DCBEN - Data Center Bridging feature.
5527 */
5528#define ENET_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK)
5529#define ENET_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U)
5530#define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT (16U)
5531/*! RXCOESEL - Receive Checksum Offload Support.
5532 */
5533#define ENET_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK)
5534#define ENET_MAC_HW_FEAT_SPEN_MASK (0x20000U)
5535#define ENET_MAC_HW_FEAT_SPEN_SHIFT (17U)
5536/*! SPEN - Split Header Structure feature.
5537 */
5538#define ENET_MAC_HW_FEAT_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPEN_SHIFT)) & ENET_MAC_HW_FEAT_SPEN_MASK)
5539#define ENET_MAC_HW_FEAT_TSOEN_MASK (0x40000U)
5540#define ENET_MAC_HW_FEAT_TSOEN_SHIFT (18U)
5541/*! TSOEN - TCP Segment Offload Feature.
5542 */
5543#define ENET_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK)
5544#define ENET_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U)
5545#define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT (18U)
5546/*! TXCHCNT - Number of DMA Transmit Channels.
5547 */
5548#define ENET_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK)
5549#define ENET_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U)
5550#define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT (19U)
5551/*! DBGMEMA - DMA Debug Register Feature.
5552 */
5553#define ENET_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK)
5554#define ENET_MAC_HW_FEAT_AVSEL_MASK (0x100000U)
5555#define ENET_MAC_HW_FEAT_AVSEL_SHIFT (20U)
5556/*! AVSEL - Audio Video Bridging Feature.
5557 */
5558#define ENET_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK)
5559#define ENET_MAC_HW_FEAT_LPMODEEN_MASK (0x800000U)
5560#define ENET_MAC_HW_FEAT_LPMODEEN_SHIFT (23U)
5561/*! LPMODEEN - Low Power Mode Feature Support .
5562 */
5563#define ENET_MAC_HW_FEAT_LPMODEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_LPMODEEN_SHIFT)) & ENET_MAC_HW_FEAT_LPMODEEN_MASK)
5564#define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U)
5565#define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U)
5566/*! HASHTBLSZ - Hash Table Size.
5567 */
5568#define ENET_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK)
5569#define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U)
5570#define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U)
5571/*! PPSOUTNUM - Number of PPS Outputs.
5572 */
5573#define ENET_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK)
5574#define ENET_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U)
5575#define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U)
5576/*! TSSTSSEL - Timestamp System Time Source.
5577 */
5578#define ENET_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK)
5579#define ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK (0x78000000U)
5580#define ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT (27U)
5581/*! L3_L4_FILTER - Total Number of L3 and L4 Filters .
5582 */
5583#define ENET_MAC_HW_FEAT_L3_L4_FILTER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT)) & ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK)
5584#define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U)
5585#define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U)
5586/*! ACTPHYSEL - Active PHY Selected.
5587 */
5588#define ENET_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK)
5589#define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U)
5590#define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U)
5591/*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs.
5592 */
5593#define ENET_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK)
5594/*! @} */
5595
5596/* The count of ENET_MAC_HW_FEAT */
5597#define ENET_MAC_HW_FEAT_COUNT (3U)
5598
5599/*! @name MAC_MDIO_ADDR - MIDO address Register */
5600/*! @{ */
5601#define ENET_MAC_MDIO_ADDR_MB_MASK (0x1U)
5602#define ENET_MAC_MDIO_ADDR_MB_SHIFT (0U)
5603/*! MB - MII busy.
5604 */
5605#define ENET_MAC_MDIO_ADDR_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MB_SHIFT)) & ENET_MAC_MDIO_ADDR_MB_MASK)
5606#define ENET_MAC_MDIO_ADDR_MOC_MASK (0xCU)
5607#define ENET_MAC_MDIO_ADDR_MOC_SHIFT (2U)
5608/*! MOC - MII Operation Command.
5609 */
5610#define ENET_MAC_MDIO_ADDR_MOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MOC_SHIFT)) & ENET_MAC_MDIO_ADDR_MOC_MASK)
5611#define ENET_MAC_MDIO_ADDR_CR_MASK (0xF00U)
5612#define ENET_MAC_MDIO_ADDR_CR_SHIFT (8U)
5613/*! CR - CSR Clock Range.
5614 */
5615#define ENET_MAC_MDIO_ADDR_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_CR_SHIFT)) & ENET_MAC_MDIO_ADDR_CR_MASK)
5616#define ENET_MAC_MDIO_ADDR_NTC_MASK (0x7000U)
5617#define ENET_MAC_MDIO_ADDR_NTC_SHIFT (12U)
5618/*! NTC - Number of Training Clocks This field controls the number of trailing clock cycles
5619 * generated on MDC after the end of transmission of MDIO frame.
5620 */
5621#define ENET_MAC_MDIO_ADDR_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_NTC_SHIFT)) & ENET_MAC_MDIO_ADDR_NTC_MASK)
5622#define ENET_MAC_MDIO_ADDR_RDA_MASK (0x1F0000U)
5623#define ENET_MAC_MDIO_ADDR_RDA_SHIFT (16U)
5624/*! RDA - Register/Device Address These bits select the PHY register in selected PHY device.
5625 */
5626#define ENET_MAC_MDIO_ADDR_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_RDA_SHIFT)) & ENET_MAC_MDIO_ADDR_RDA_MASK)
5627#define ENET_MAC_MDIO_ADDR_PA_MASK (0x3E00000U)
5628#define ENET_MAC_MDIO_ADDR_PA_SHIFT (21U)
5629/*! PA - Physical Layer Address This field indicates which PHY devices (out of 32 devices) the MAC is accessing.
5630 */
5631#define ENET_MAC_MDIO_ADDR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PA_SHIFT)) & ENET_MAC_MDIO_ADDR_PA_MASK)
5632#define ENET_MAC_MDIO_ADDR_BTB_MASK (0x4000000U)
5633#define ENET_MAC_MDIO_ADDR_BTB_SHIFT (26U)
5634/*! BTB - Back to Back transactions When this bit is set and the NTC has value greater than 0, then
5635 * the MAC will inform the completion of a read or write command at the end of frame transfer
5636 * (before the trailing clocks are transmitted).
5637 */
5638#define ENET_MAC_MDIO_ADDR_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_BTB_SHIFT)) & ENET_MAC_MDIO_ADDR_BTB_MASK)
5639#define ENET_MAC_MDIO_ADDR_PSE_MASK (0x8000000U)
5640#define ENET_MAC_MDIO_ADDR_PSE_SHIFT (27U)
5641/*! PSE - Preamble Suppression Enable When this bit is set, the SMA will suppress the 32-bit
5642 * preamble and transmit MDIO frames with only 1 preamble bit.
5643 */
5644#define ENET_MAC_MDIO_ADDR_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PSE_SHIFT)) & ENET_MAC_MDIO_ADDR_PSE_MASK)
5645/*! @} */
5646
5647/*! @name MAC_MDIO_DATA - MDIO Data register */
5648/*! @{ */
5649#define ENET_MAC_MDIO_DATA_MD_MASK (0xFFFFU)
5650#define ENET_MAC_MDIO_DATA_MD_SHIFT (0U)
5651/*! MD - MII Data This field contains the 16-bit data value read from the PHY after a Management
5652 * Read operation or the 16-bit data value to be written to the PHY before a Management Write
5653 * operation.
5654 */
5655#define ENET_MAC_MDIO_DATA_MD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_MD_SHIFT)) & ENET_MAC_MDIO_DATA_MD_MASK)
5656/*! @} */
5657
5658/*! @name MAC_ADDR_HIGH - MAC address0 high register */
5659/*! @{ */
5660#define ENET_MAC_ADDR_HIGH_A47_32_MASK (0xFFFFU)
5661#define ENET_MAC_ADDR_HIGH_A47_32_SHIFT (0U)
5662/*! A47_32 - MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the 6-byte first MAC address.
5663 */
5664#define ENET_MAC_ADDR_HIGH_A47_32(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_A47_32_SHIFT)) & ENET_MAC_ADDR_HIGH_A47_32_MASK)
5665#define ENET_MAC_ADDR_HIGH_DCS_MASK (0x10000U)
5666#define ENET_MAC_ADDR_HIGH_DCS_SHIFT (16U)
5667/*! DCS - DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose
5668 * DA matches the MAC Address content is routed.
5669 */
5670#define ENET_MAC_ADDR_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_DCS_SHIFT)) & ENET_MAC_ADDR_HIGH_DCS_MASK)
5671#define ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000U)
5672#define ENET_MAC_ADDR_HIGH_AE_SHIFT (31U)
5673/*! AE - Address Enable.
5674 */
5675#define ENET_MAC_ADDR_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_AE_SHIFT)) & ENET_MAC_ADDR_HIGH_AE_MASK)
5676/*! @} */
5677
5678/*! @name MAC_ADDR_LOW - MAC address0 low register */
5679/*! @{ */
5680#define ENET_MAC_ADDR_LOW_A31_0_MASK (0xFFFFFFFFU)
5681#define ENET_MAC_ADDR_LOW_A31_0_SHIFT (0U)
5682/*! A31_0 - MAC Address0 [31:0] This field contains the lower 32 bits of the 6-byte first MAC address.
5683 */
5684#define ENET_MAC_ADDR_LOW_A31_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_LOW_A31_0_SHIFT)) & ENET_MAC_ADDR_LOW_A31_0_MASK)
5685/*! @} */
5686
5687/*! @name MAC_TIMESTAMP_CTRL - Time stamp control register */
5688/*! @{ */
5689#define ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK (0x1U)
5690#define ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT (0U)
5691/*! TSENA - Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets.
5692 */
5693#define ENET_MAC_TIMESTAMP_CTRL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK)
5694#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK (0x2U)
5695#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT (1U)
5696/*! TSCFUPDT - Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp.
5697 */
5698#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK)
5699#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK (0x4U)
5700#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT (2U)
5701/*! TSINIT - Initialize Timestamp When this bit is set, the system time is initialized (overwritten)
5702 * with the value specified in the MAC Register 80 (System Time Seconds Update.
5703 */
5704#define ENET_MAC_TIMESTAMP_CTRL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK)
5705#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK (0x8U)
5706#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT (3U)
5707/*! TSUPDT - Update Timestamp When this bit is set, the system time is updated (added or subtracted)
5708 * with the value specified in MAC System Time Seconds Update Table 753 and MAC System Time
5709 * Nanoseconds Update Table 754.
5710 */
5711#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK)
5712#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK (0x10U)
5713#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT (4U)
5714/*! TSTRIG - Enable Timestamp Interrupt Trigger When this bit is set, the timestamp interrupt is
5715 * generated when the System Time becomes greater than the value written in the Target Time register.
5716 */
5717#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK)
5718#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK (0x20U)
5719#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT (5U)
5720/*! TADDREG - Update Addend Register When this bit is set, the content of the Timestamp Addend
5721 * register is updated in the PTP block for fine correction.
5722 */
5723#define ENET_MAC_TIMESTAMP_CTRL_TADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK)
5724#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK (0x100U)
5725#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT (8U)
5726/*! TSENALL - Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is
5727 * enabled for all packets received by the MAC.
5728 */
5729#define ENET_MAC_TIMESTAMP_CTRL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK)
5730#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK (0x200U)
5731#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT (9U)
5732/*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low
5733 * register rolls over after 0x3B9AC9FF value (that is, 1 nanosecond accuracy) and increments
5734 * the timestamp (High) seconds.
5735 */
5736#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)
5737#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK (0x400U)
5738#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT (10U)
5739/*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE
5740 * 1588 version 2 format is used to process the PTP packets.
5741 */
5742#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK)
5743#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK (0x800U)
5744#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT (11U)
5745/*! TSIPENA - Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver
5746 * processes the PTP packets encapsulated directly in the Ethernet packets.
5747 */
5748#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK)
5749#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK (0x1000U)
5750#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT (12U)
5751/*! TSIPV6ENA - Enable Processing of PTP Packets Sent over 1Pv6-UDP When this bit is set, the MAC
5752 * receiver processes the PTP packets encapsulated in IPv6-UDP packets.
5753 */
5754#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK)
5755#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK (0x2000U)
5756#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT (13U)
5757/*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC
5758 * receiver processes the PTP packets encapsulated in IPv4-UDP packets.
5759 */
5760#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK)
5761#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK (0x4000U)
5762#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT (14U)
5763/*! TSEVTENA - Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp
5764 * snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp).
5765 */
5766#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK)
5767#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK (0x8000U)
5768#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT (15U)
5769/*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot
5770 * is taken only for the messages that are relevant to the master node.
5771 */
5772#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK)
5773#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK (0x30000U)
5774#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT (16U)
5775/*! SNAPTYPSEL - Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14,
5776 * decide the set of PTP packet types for which snapshot needs to be taken.
5777 */
5778#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK)
5779#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK (0x40000U)
5780#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT (18U)
5781/*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC
5782 * address (that matches any MAC Address register) is used to filter the PTP packets when PTP is
5783 * directly sent over Ethernet.
5784 */
5785#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK)
5786#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK (0x1000000U)
5787#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT (24U)
5788/*! TXTTSSTSM - Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier
5789 * transmit timestamp status even if it is not read by the software.
5790 */
5791#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK)
5792#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK (0x10000000U)
5793#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT (28U)
5794/*! AV8021ASMEN - AV 802.
5795 */
5796#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK)
5797/*! @} */
5798
5799/*! @name MAC_SUB_SCND_INCR - Sub-second increment register */
5800/*! @{ */
5801#define ENET_MAC_SUB_SCND_INCR_SSINC_MASK (0xFF0000U)
5802#define ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT (16U)
5803/*! SSINC - Sub-second increment value.
5804 */
5805#define ENET_MAC_SUB_SCND_INCR_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT)) & ENET_MAC_SUB_SCND_INCR_SSINC_MASK)
5806/*! @} */
5807
5808/*! @name MAC_SYS_TIME_SCND - System time seconds register */
5809/*! @{ */
5810#define ENET_MAC_SYS_TIME_SCND_TSS_MASK (0xFFFFFFFFU)
5811#define ENET_MAC_SYS_TIME_SCND_TSS_SHIFT (0U)
5812/*! TSS - Time stamp second The value in this field indicates the current value in seconds of the
5813 * System Time maintained by the MAC.
5814 */
5815#define ENET_MAC_SYS_TIME_SCND_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_TSS_MASK)
5816/*! @} */
5817
5818/*! @name MAC_SYS_TIME_NSCND - System time nanoseconds register */
5819/*! @{ */
5820#define ENET_MAC_SYS_TIME_NSCND_TSSS_MASK (0x7FFFFFFFU)
5821#define ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT (0U)
5822/*! TSSS - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.
5823 */
5824#define ENET_MAC_SYS_TIME_NSCND_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK)
5825/*! @} */
5826
5827/*! @name MAC_SYS_TIME_SCND_UPD - */
5828/*! @{ */
5829#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK (0xFFFFFFFFU)
5830#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT (0U)
5831/*! TSS - Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time.
5832 */
5833#define ENET_MAC_SYS_TIME_SCND_UPD_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK)
5834/*! @} */
5835
5836/*! @name MAC_SYS_TIME_NSCND_UPD - */
5837/*! @{ */
5838#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK (0x7FFFFFFFU)
5839#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT (0U)
5840/*! TSSS - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.
5841 */
5842#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK)
5843#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK (0x80000000U)
5844#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT (31U)
5845/*! ADDSUB - Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register.
5846 */
5847#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK)
5848/*! @} */
5849
5850/*! @name MAC_SYS_TIMESTMP_ADDEND - Time stamp addend register */
5851/*! @{ */
5852#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK (0xFFFFFFFFU)
5853#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT (0U)
5854/*! TSAR - Time stamp addend This register indicates the 32-bit time value to be added to the
5855 * Accumulator register to achieve time synchronization.
5856 */
5857#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK)
5858/*! @} */
5859
5860/*! @name MAC_SYS_TIME_HWORD_SCND - */
5861/*! @{ */
5862#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK (0xFFFFU)
5863#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT (0U)
5864/*! TSHWR - Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value.
5865 */
5866#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT)) & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK)
5867/*! @} */
5868
5869/*! @name MAC_SYS_TIMESTMP_STAT - Time stamp status register */
5870/*! @{ */
5871#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK (0x1U)
5872#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT (0U)
5873/*! TSSOVF - Time stamp seconds overflow When set, indicates that the seconds value of the Time
5874 * stamp has overflowed beyond 0xFFFF_FFFF.
5875 */
5876#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT)) & ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK)
5877/*! @} */
5878
5879/*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Tx timestamp status nanoseconds */
5880/*! @{ */
5881#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK (0x7FFFFFFFU)
5882#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT (0U)
5883/*! TXTSSTSLO - Transmit timestamp status low.
5884 */
5885#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK)
5886#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK (0x80000000U)
5887#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT (31U)
5888/*! TXTSSTSMIS - Transmit timestamp status missed.
5889 */
5890#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK)
5891/*! @} */
5892
5893/*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Tx timestamp status seconds */
5894/*! @{ */
5895#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK (0xFFFFFFFFU)
5896#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT (0U)
5897/*! TXTSSTSHI - Transmit timestamp status high.
5898 */
5899#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK)
5900/*! @} */
5901
5902/*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp ingress correction */
5903/*! @{ */
5904#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
5905#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
5906/*! TSIC - Transmit ingress correction.
5907 */
5908#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
5909/*! @} */
5910
5911/*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp egress correction */
5912/*! @{ */
5913#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
5914#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
5915/*! TSEC - Transmit egress correction.
5916 */
5917#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
5918/*! @} */
5919
5920/*! @name MTL_OP_MODE - MTL Operation Mode Register */
5921/*! @{ */
5922#define ENET_MTL_OP_MODE_DTXSTS_MASK (0x2U)
5923#define ENET_MTL_OP_MODE_DTXSTS_SHIFT (1U)
5924/*! DTXSTS - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL.
5925 */
5926#define ENET_MTL_OP_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_DTXSTS_SHIFT)) & ENET_MTL_OP_MODE_DTXSTS_MASK)
5927#define ENET_MTL_OP_MODE_RAA_MASK (0x4U)
5928#define ENET_MTL_OP_MODE_RAA_SHIFT (2U)
5929/*! RAA - Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side.
5930 */
5931#define ENET_MTL_OP_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_RAA_SHIFT)) & ENET_MTL_OP_MODE_RAA_MASK)
5932#define ENET_MTL_OP_MODE_SCHALG_MASK (0x60U)
5933#define ENET_MTL_OP_MODE_SCHALG_SHIFT (5U)
5934/*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: 0x00: WRR
5935 * algorithm 0x1: Reserved 0x2: Reserved 0x3: Strict priority algorithm.
5936 */
5937#define ENET_MTL_OP_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_SCHALG_SHIFT)) & ENET_MTL_OP_MODE_SCHALG_MASK)
5938#define ENET_MTL_OP_MODE_CNTPRST_MASK (0x100U)
5939#define ENET_MTL_OP_MODE_CNTPRST_SHIFT (8U)
5940/*! CNTPRST - Counters Preset When this bit is set, MTL TxQ0 Underflow register (Table 762) and
5941 * MTL_TxQ1_Underflow (Table 762) registers are initialized/preset to 0x7F0.
5942 */
5943#define ENET_MTL_OP_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTPRST_SHIFT)) & ENET_MTL_OP_MODE_CNTPRST_MASK)
5944#define ENET_MTL_OP_MODE_CNTCLR_MASK (0x200U)
5945#define ENET_MTL_OP_MODE_CNTCLR_SHIFT (9U)
5946/*! CNTCLR - Counters Reset When this bit is set, all counters are reset.
5947 */
5948#define ENET_MTL_OP_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTCLR_SHIFT)) & ENET_MTL_OP_MODE_CNTCLR_MASK)
5949/*! @} */
5950
5951/*! @name MTL_INTR_STAT - MTL Interrupt Status register */
5952/*! @{ */
5953#define ENET_MTL_INTR_STAT_Q0IS_MASK (0x1U)
5954#define ENET_MTL_INTR_STAT_Q0IS_SHIFT (0U)
5955/*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0.
5956 */
5957#define ENET_MTL_INTR_STAT_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q0IS_SHIFT)) & ENET_MTL_INTR_STAT_Q0IS_MASK)
5958#define ENET_MTL_INTR_STAT_Q1IS_MASK (0x2U)
5959#define ENET_MTL_INTR_STAT_Q1IS_SHIFT (1U)
5960/*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1.
5961 */
5962#define ENET_MTL_INTR_STAT_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q1IS_SHIFT)) & ENET_MTL_INTR_STAT_Q1IS_MASK)
5963/*! @} */
5964
5965/*! @name MTL_RXQ_DMA_MAP - MTL Receive Queue and DMA Channel Mapping register */
5966/*! @{ */
5967#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK (0x1U)
5968#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT (0U)
5969/*! Q0MDMACH - Queue 0 Mapped to DMA Channel This field controls the routing of the packet received
5970 * in Queue 0 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the
5971 * Q0DDMACH field is reset.
5972 */
5973#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK)
5974#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK (0x10U)
5975#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT (4U)
5976/*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
5977 * the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC
5978 * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
5979 * Ethernet DA address.
5980 */
5981#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK)
5982#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK (0x100U)
5983#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT (8U)
5984/*! Q1MDMACH - Queue 1 Mapped to DMA Channel This field controls the routing of the received packet
5985 * in Queue 1 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the
5986 * Q1DDMACH field is reset.
5987 */
5988#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK)
5989#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK (0x1000U)
5990#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT (12U)
5991/*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
5992 * the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC
5993 * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
5994 * Ethernet DA address.
5995 */
5996#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK)
5997/*! @} */
5998
5999/*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - MTL TxQx Operation Mode register */
6000/*! @{ */
6001#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U)
6002#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U)
6003/*! FTQ - Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values.
6004 */
6005#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK)
6006#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U)
6007#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U)
6008/*! TSF - Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue.
6009 */
6010#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK)
6011#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU)
6012#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U)
6013/*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0.
6014 */
6015#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK)
6016#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U)
6017#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U)
6018/*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue.
6019 */
6020#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK)
6021#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U)
6022#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U)
6023/*! TQS - Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes.
6024 */
6025#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK)
6026/*! @} */
6027
6028/* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */
6029#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT (2U)
6030
6031/*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - MTL TxQx Underflow register */
6032/*! @{ */
6033#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU)
6034#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
6035/*! UFFRMCNT - Underflow Packet Counter This field indicates the number of packets aborted by the
6036 * controller because of Tx Queue Underflow.
6037 */
6038#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
6039#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U)
6040#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
6041/*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue
6042 * Underflow Packet Counter field overflows, that is, it has crossed the maximum count.
6043 */
6044#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
6045/*! @} */
6046
6047/* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */
6048#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT (2U)
6049
6050/*! @name MTL_QUEUE_MTL_TXQX_DBG - MTL TxQx Debug register */
6051/*! @{ */
6052#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U)
6053#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U)
6054/*! TXQPAUSED - Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it
6055 * indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because
6056 * of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue
6057 * when PFC is enabled - Reception of 802.
6058 */
6059#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK)
6060#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK (0x6U)
6061#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U)
6062/*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read
6063 * Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10:
6064 * Waiting for pending Tx Status from the MAC transmitter 11: Flushing the Tx queue because of the
6065 * Packet Abort request from the MAC.
6066 */
6067#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK)
6068#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK (0x8U)
6069#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U)
6070/*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx
6071 * Queue Write Controller is active, and it is transferring the data to the Tx Queue.
6072 */
6073#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK)
6074#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK (0x10U)
6075#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U)
6076/*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue
6077 * is not empty and some data is left for transmission.
6078 */
6079#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK)
6080#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U)
6081#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U)
6082/*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full.
6083 */
6084#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK)
6085#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK (0x70000U)
6086#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT (16U)
6087/*! PTXQ - Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue.
6088 */
6089#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK)
6090#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK (0x700000U)
6091#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT (20U)
6092/*! STSXSTSF - Number of Status Words in Tx Status FIFO of Queue This field indicates the current
6093 * number of status in the Tx Status FIFO of this queue.
6094 */
6095#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK)
6096/*! @} */
6097
6098/* The count of ENET_MTL_QUEUE_MTL_TXQX_DBG */
6099#define ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT (2U)
6100
6101/*! @name MTL_QUEUE_MTL_TXQX_ETS_CTRL - MTL TxQx ETS control register, only TxQ1 support */
6102/*! @{ */
6103#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U)
6104#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U)
6105/*! AVALG - AV Algorithm.
6106 */
6107#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK)
6108#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U)
6109#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U)
6110/*! CC - Credit Control.
6111 */
6112#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK)
6113#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U)
6114#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U)
6115/*! SLC - Credit Control.
6116 */
6117#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK)
6118/*! @} */
6119
6120/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL */
6121#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT (2U)
6122
6123/*! @name MTL_QUEUE_MTL_TXQX_ETS_STAT - MTL TxQx ETS Status register */
6124/*! @{ */
6125#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU)
6126#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U)
6127/*! ABS - Average Bits per Slot.
6128 */
6129#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK)
6130/*! @} */
6131
6132/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT */
6133#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT (2U)
6134
6135/*! @name MTL_QUEUE_MTL_TXQX_QNTM_WGHT - */
6136/*! @{ */
6137#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU)
6138#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U)
6139/*! ISCQW - Average Bits per Slot.
6140 */
6141#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)
6142/*! @} */
6143
6144/* The count of ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT */
6145#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT (2U)
6146
6147/*! @name MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT - MTL TxQx SendSlopCredit register, only TxQ1 support */
6148/*! @{ */
6149#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU)
6150#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U)
6151/*! SSC - sendSlopeCredit.
6152 */
6153#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)
6154/*! @} */
6155
6156/* The count of ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT */
6157#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U)
6158
6159/*! @name MTL_QUEUE_MTL_TXQX_HI_CRDT - MTL TxQx hiCredit register, only TxQ1 support */
6160/*! @{ */
6161#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU)
6162#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U)
6163/*! HC - hiCredit.
6164 */
6165#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK)
6166/*! @} */
6167
6168/* The count of ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT */
6169#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT (2U)
6170
6171/*! @name MTL_QUEUE_MTL_TXQX_LO_CRDT - MTL TxQx loCredit register, only TxQ1 support */
6172/*! @{ */
6173#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU)
6174#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U)
6175/*! LC - loCredit.
6176 */
6177#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK)
6178/*! @} */
6179
6180/* The count of ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT */
6181#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT (2U)
6182
6183/*! @name MTL_QUEUE_MTL_TXQX_INTCTRL_STAT - */
6184/*! @{ */
6185#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)
6186#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)
6187/*! TXUNFIS - Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue
6188 * had an underflow while transmitting the packet.
6189 */
6190#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)
6191#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)
6192#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)
6193/*! ABPSIS - Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value.
6194 */
6195#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)
6196#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)
6197#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)
6198/*! TXUIE - Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled.
6199 */
6200#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)
6201#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)
6202#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)
6203/*! ABPSIE - Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the
6204 * interrupt when the average bits per slot status is updated.
6205 */
6206#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)
6207#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)
6208#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)
6209/*! RXOVFIS - Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had
6210 * an overflow while receiving the packet.
6211 */
6212#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)
6213#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)
6214#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)
6215/*! RXOIE - Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled.
6216 */
6217#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)
6218/*! @} */
6219
6220/* The count of ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT */
6221#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_COUNT (2U)
6222
6223/*! @name MTL_QUEUE_MTL_RXQX_OP_MODE - MTL RxQx Operation Mode register */
6224/*! @{ */
6225#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U)
6226#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U)
6227/*! RTC - Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue
6228 * (in bytes): 00: 64 01: 32 10: 96 11: 128 The packet received is transferred to the
6229 * application or DMA when the packet size within the MTL Rx queue is larger than the threshold.
6230 */
6231#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK)
6232#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U)
6233#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U)
6234/*! FUP - Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized
6235 * good packets (packets with no error and length less than 64 bytes), including pad-bytes and
6236 * CRC.
6237 */
6238#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK)
6239#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U)
6240#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U)
6241/*! FEP - Forward Error Packets When this bit is reset, the Rx queue drops packets with error status
6242 * (CRC error, Mll_ER, watchdog timeout, or overflow).
6243 */
6244#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK)
6245#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U)
6246#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U)
6247/*! RSF - Receive Queue Store and Forward When this bit is set, the ethernet block on this chip
6248 * reads a packet from the Rx queue only after the complete packet has been written to it, ignoring
6249 * the RTC field of this register.
6250 */
6251#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK)
6252#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)
6253#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)
6254/*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC
6255 * does not drop the packets which only have the errors detected by the Receive Checksum Offload
6256 * engine.
6257 */
6258#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)
6259#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U)
6260#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U)
6261/*! RQS - This field indicates the size of the allocated Receive queues in blocks of 256 bytes.
6262 */
6263#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK)
6264/*! @} */
6265
6266/* The count of ENET_MTL_QUEUE_MTL_RXQX_OP_MODE */
6267#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT (2U)
6268
6269/*! @name MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT - MTL RxQx Missed Packet Overflow Counter register */
6270/*! @{ */
6271#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)
6272#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)
6273/*! OVFPKTCNT - Overflow Packet Counter This field indicates the number of packets discarded by the
6274 * Ethernet block because of Receive queue overflow.
6275 */
6276#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)
6277#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)
6278#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)
6279/*! OVFCNTOVF - Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue
6280 * Overflow Packet Counter field crossed the maximum limit.
6281 */
6282#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)
6283/*! @} */
6284
6285/* The count of ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT */
6286#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U)
6287
6288/*! @name MTL_QUEUE_MTL_RXQX_DBG - MTL RxQx Debug register */
6289/*! @{ */
6290#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK (0x1U)
6291#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U)
6292/*! RWCSTS - MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL
6293 * Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue.
6294 */
6295#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK)
6296#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK (0x6U)
6297#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U)
6298/*! RRCSTS - MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read
6299 * controller: 00: Idle state 01: Reading packet data 10: Reading packet status (or timestamp) 11:
6300 * Flushing the packet data and status.
6301 */
6302#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK)
6303#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK (0x30U)
6304#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U)
6305/*! RXQSTS - MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx
6306 * Queue: 0x0: Rx Queue empty 0x1: Rx Queue fill-level below flow-control deactivate threshold
6307 * 0x2: Rx Queue fill-level above flow-control activate threshold 0x3: Rx Queue full.
6308 */
6309#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK)
6310#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U)
6311#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT (16U)
6312/*! PRXQ - Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue.
6313 */
6314#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK)
6315/*! @} */
6316
6317/* The count of ENET_MTL_QUEUE_MTL_RXQX_DBG */
6318#define ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT (2U)
6319
6320/*! @name MTL_QUEUE_MTL_RXQX_CTRL - MTL RxQx Control register */
6321/*! @{ */
6322#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U)
6323#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U)
6324/*! RXQ_WEGT - Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0.
6325 */
6326#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK)
6327#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)
6328#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)
6329/*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration When this bit is set, the The ethernet block
6330 * drives the packet data to the ARI interface such that the entire packet data of
6331 * currently-selected queue is transmitted before switching to other queue.
6332 */
6333#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)
6334/*! @} */
6335
6336/* The count of ENET_MTL_QUEUE_MTL_RXQX_CTRL */
6337#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT (2U)
6338
6339/*! @name DMA_MODE - DMA mode register */
6340/*! @{ */
6341#define ENET_DMA_MODE_SWR_MASK (0x1U)
6342#define ENET_DMA_MODE_SWR_SHIFT (0U)
6343/*! SWR - Software Reset When this bit is set, the MAC and the OMA controller reset the logic and
6344 * all internal registers of the OMA, MTL, and MAC.
6345 */
6346#define ENET_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK)
6347#define ENET_DMA_MODE_DA_MASK (0x2U)
6348#define ENET_DMA_MODE_DA_SHIFT (1U)
6349/*! DA - DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the
6350 * Transmit and Receive paths of all channels: The Tx path has priority over the Rx path when the TXPR
6351 * bit is set.
6352 */
6353#define ENET_DMA_MODE_DA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK)
6354#define ENET_DMA_MODE_TAA_MASK (0x1CU)
6355#define ENET_DMA_MODE_TAA_SHIFT (2U)
6356/*! TAA - Transmit Arbitration Algorithm This field is used to select the arbitration algorithm for
6357 * the Transmit side when multiple Tx DMAs are selected.
6358 */
6359#define ENET_DMA_MODE_TAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK)
6360#define ENET_DMA_MODE_TXPR_MASK (0x800U)
6361#define ENET_DMA_MODE_TXPR_SHIFT (11U)
6362/*! TXPR - Transmit Priority When set, this bit indicates that the Tx DMA has higher priority than
6363 * the Rx DMA during arbitration for the system-side bus.
6364 */
6365#define ENET_DMA_MODE_TXPR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK)
6366#define ENET_DMA_MODE_PR_MASK (0x7000U)
6367#define ENET_DMA_MODE_PR_SHIFT (12U)
6368/*! PR - Priority Ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA.
6369 */
6370#define ENET_DMA_MODE_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK)
6371/*! @} */
6372
6373/*! @name DMA_SYSBUS_MODE - DMA System Bus mode */
6374/*! @{ */
6375#define ENET_DMA_SYSBUS_MODE_FB_MASK (0x1U)
6376#define ENET_DMA_SYSBUS_MODE_FB_SHIFT (0U)
6377/*! FB - Fixed Burst Length When this bit is set to 1, the AHB master will initiate burst transfers
6378 * of specified length (INCRx or SINGLE).
6379 */
6380#define ENET_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK)
6381#define ENET_DMA_SYSBUS_MODE_AAL_MASK (0x1000U)
6382#define ENET_DMA_SYSBUS_MODE_AAL_SHIFT (12U)
6383/*! AAL - Address-Aligned Beats When this bit is set to 1, the AHB master performs address-aligned
6384 * burst transfers on Read and Write channels.
6385 */
6386#define ENET_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK)
6387#define ENET_DMA_SYSBUS_MODE_MB_MASK (0x4000U)
6388#define ENET_DMA_SYSBUS_MODE_MB_SHIFT (14U)
6389/*! MB - Mixed Burst When this bit is set high and the FB bit is low, the AHB master performs
6390 * undefined bursts transfers (INCR) for burst length of 16 or more.
6391 */
6392#define ENET_DMA_SYSBUS_MODE_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK)
6393#define ENET_DMA_SYSBUS_MODE_RB_MASK (0x8000U)
6394#define ENET_DMA_SYSBUS_MODE_RB_SHIFT (15U)
6395/*! RB - Rebuild INCRx Burst When this bit is set high and the AHB master gets SPLIT, RETRY, or
6396 * EarlyBurst Termination (EBT) response, the AHB master interface rebuilds the pending beats of any
6397 * initiated burst transfer with INCRx and SINGLEtransfers.
6398 */
6399#define ENET_DMA_SYSBUS_MODE_RB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK)
6400/*! @} */
6401
6402/*! @name DMA_INTR_STAT - DMA Interrupt status */
6403/*! @{ */
6404#define ENET_DMA_INTR_STAT_DC0IS_MASK (0x1U)
6405#define ENET_DMA_INTR_STAT_DC0IS_SHIFT (0U)
6406/*! DC0IS - DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0.
6407 */
6408#define ENET_DMA_INTR_STAT_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC0IS_SHIFT)) & ENET_DMA_INTR_STAT_DC0IS_MASK)
6409#define ENET_DMA_INTR_STAT_DC1IS_MASK (0x2U)
6410#define ENET_DMA_INTR_STAT_DC1IS_SHIFT (1U)
6411/*! DC1IS - DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1.
6412 */
6413#define ENET_DMA_INTR_STAT_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC1IS_SHIFT)) & ENET_DMA_INTR_STAT_DC1IS_MASK)
6414#define ENET_DMA_INTR_STAT_MTLIS_MASK (0x10000U)
6415#define ENET_DMA_INTR_STAT_MTLIS_SHIFT (16U)
6416/*! MTLIS - MTL Interrupt Status This bit indicates an interrupt event in the MTL.
6417 */
6418#define ENET_DMA_INTR_STAT_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MTLIS_SHIFT)) & ENET_DMA_INTR_STAT_MTLIS_MASK)
6419#define ENET_DMA_INTR_STAT_MACIS_MASK (0x20000U)
6420#define ENET_DMA_INTR_STAT_MACIS_SHIFT (17U)
6421/*! MACIS - MAC Interrupt Status This bit indicates an interrupt event in the MAC.
6422 */
6423#define ENET_DMA_INTR_STAT_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MACIS_SHIFT)) & ENET_DMA_INTR_STAT_MACIS_MASK)
6424/*! @} */
6425
6426/*! @name DMA_DBG_STAT - DMA Debug Status */
6427/*! @{ */
6428#define ENET_DMA_DBG_STAT_AHSTS_MASK (0x1U)
6429#define ENET_DMA_DBG_STAT_AHSTS_SHIFT (0U)
6430/*! AHSTS - AHB Master Status When high, this bit indicates that the AHB master FSMs are in the non-idle state.
6431 */
6432#define ENET_DMA_DBG_STAT_AHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_AHSTS_SHIFT)) & ENET_DMA_DBG_STAT_AHSTS_MASK)
6433#define ENET_DMA_DBG_STAT_RPS0_MASK (0xF00U)
6434#define ENET_DMA_DBG_STAT_RPS0_SHIFT (8U)
6435/*! RPS0 - DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel
6436 * 0: 0x0: Stopped (Reset or Stop Receive Command issued) 0x1: Running (Fetching Rx Transfer )
6437 * 0x2: Reserved 0x3: Running (Waiting for Rx packet) 0x4: Suspended (Rx Unavailable) 0x5: Running
6438 * (Closing the Rx) 0x6: Timestamp write state 0x7: Running (Transferring the received packet
6439 * data from the Rx buffer to the system memory) This field does not generate an interrupt.
6440 */
6441#define ENET_DMA_DBG_STAT_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS0_SHIFT)) & ENET_DMA_DBG_STAT_RPS0_MASK)
6442#define ENET_DMA_DBG_STAT_TPS0_MASK (0xF000U)
6443#define ENET_DMA_DBG_STAT_TPS0_SHIFT (12U)
6444/*! TPS0 - DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for
6445 * Channel 0: 000: Stopped (Reset or Stop Transmit Command issued) 0x1: Running (Fetching Tx Transfer)
6446 * 0x2: Running (Waiting for status) 0x3: Running (Reading Data from system memory buffer and
6447 * queuing it to the Tx buffer (Tx FIFO)) 0x4: Timestamp write state 0x5: Reserved for future use
6448 * 0x6: Suspended (Tx Unavailable or Tx Buffer Underflow) 0x7: Running (Closing Tx ) This field
6449 * does not generate an interrupt.
6450 */
6451#define ENET_DMA_DBG_STAT_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS0_SHIFT)) & ENET_DMA_DBG_STAT_TPS0_MASK)
6452#define ENET_DMA_DBG_STAT_RPS1_MASK (0xF0000U)
6453#define ENET_DMA_DBG_STAT_RPS1_SHIFT (16U)
6454/*! RPS1 - DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1.
6455 */
6456#define ENET_DMA_DBG_STAT_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS1_SHIFT)) & ENET_DMA_DBG_STAT_RPS1_MASK)
6457#define ENET_DMA_DBG_STAT_TPS1_MASK (0xF00000U)
6458#define ENET_DMA_DBG_STAT_TPS1_SHIFT (20U)
6459/*! TPS1 - DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1.
6460 */
6461#define ENET_DMA_DBG_STAT_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS1_SHIFT)) & ENET_DMA_DBG_STAT_TPS1_MASK)
6462/*! @} */
6463
6464/*! @name DMA_CH_DMA_CHX_CTRL - DMA Channelx Control */
6465/*! @{ */
6466#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK (0x10000U)
6467#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT (16U)
6468/*! PBLx8 - 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in DMA Channel
6469 * Transmit Control Table 780 is multiplied eight times.
6470 */
6471#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK)
6472#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK (0x1C0000U)
6473#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT (18U)
6474/*! DSL - Skip Length This bit specifies the Word, Dword, or Lword number (depending on the 32- bit,
6475 * 64-bit, or 128-bit bus) to skip between two unchained s.
6476 */
6477#define ENET_DMA_CH_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK)
6478/*! @} */
6479
6480/* The count of ENET_DMA_CH_DMA_CHX_CTRL */
6481#define ENET_DMA_CH_DMA_CHX_CTRL_COUNT (2U)
6482
6483/*! @name DMA_CH_DMA_CHX_TX_CTRL - DMA Channelx Transmit Control */
6484/*! @{ */
6485#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK (0x1U)
6486#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT (0U)
6487/*! ST - Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state.
6488 */
6489#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK)
6490#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK (0xEU)
6491#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT (1U)
6492/*! TCW - Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel.
6493 */
6494#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK)
6495#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK (0x10U)
6496#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT (4U)
6497/*! OSF - Operate on Second Frame When this bit is set, it instructs the DMA to process the second
6498 * packet of the Transmit data even before the status for the first packet is obtained.
6499 */
6500#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK)
6501#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U)
6502#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U)
6503/*! TxPBL - Transmit Programmable Burst Length These bits indicate the maximum number of beats to be
6504 * transferred in one DMA data transfer.
6505 */
6506#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK)
6507/*! @} */
6508
6509/* The count of ENET_DMA_CH_DMA_CHX_TX_CTRL */
6510#define ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT (2U)
6511
6512/*! @name DMA_CH_DMA_CHX_RX_CTRL - DMA Channelx Receive Control */
6513/*! @{ */
6514#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK (0x1U)
6515#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT (0U)
6516/*! SR - Start or Stop Receive When this bit is set, the DMA tries to acquire the from the receive
6517 * list and processes the incoming packets.
6518 */
6519#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK)
6520#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK (0x7FF8U)
6521#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT (3U)
6522/*! RBSZ - Receive Buffer size This field indicates the size of the Rx buffers specified in bytes.
6523 */
6524#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK)
6525#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U)
6526#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U)
6527/*! RxPBL - Receive Programmable Burst Length These bits indicate the maximum number of beats to be
6528 * transferred in one DMA data transfer.
6529 */
6530#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK)
6531#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U)
6532#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT (31U)
6533/*! RPF - DMA Rx Channel 0 Packet Flush When this bit is set to 1, the DMA will automatically flush
6534 * the packet from the Rx Queues destined to DMA Rx Channel 0 when the DMA Rx Channel 0 is
6535 * stopped after a system bus error has occurred.
6536 */
6537#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK)
6538/*! @} */
6539
6540/* The count of ENET_DMA_CH_DMA_CHX_RX_CTRL */
6541#define ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT (2U)
6542
6543/*! @name DMA_CH_DMA_CHX_TXDESC_LIST_ADDR - */
6544/*! @{ */
6545#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK (0xFFFFFFFCU)
6546#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT (2U)
6547/*! STL - Start of transmit list This field contains the base address of the first in the Transmit list.
6548 */
6549#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK)
6550/*! @} */
6551
6552/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR */
6553#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U)
6554
6555/*! @name DMA_CH_DMA_CHX_RXDESC_LIST_ADDR - */
6556/*! @{ */
6557#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK (0xFFFFFFFCU)
6558#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT (2U)
6559/*! SRL - Start of receive list This field contains the base address of the First in the Receive list.
6560 */
6561#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK)
6562/*! @} */
6563
6564/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR */
6565#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U)
6566
6567/*! @name DMA_CH_DMA_CHX_TXDESC_TAIL_PTR - */
6568/*! @{ */
6569#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU)
6570#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U)
6571/*! TDTP - Transmit Tail Pointer This field contains the tail pointer for the Tx ring.
6572 */
6573#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)
6574/*! @} */
6575
6576/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR */
6577#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U)
6578
6579/*! @name DMA_CH_DMA_CHX_RXDESC_TAIL_PTR - */
6580/*! @{ */
6581#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU)
6582#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U)
6583/*! RDTP - Receive Tail Pointer This field contains the tail pointer for the Rx ring.
6584 */
6585#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)
6586/*! @} */
6587
6588/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR */
6589#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U)
6590
6591/*! @name DMA_CH_DMA_CHX_TXDESC_RING_LENGTH - */
6592/*! @{ */
6593#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)
6594#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
6595/*! TDRL - Transmit Ring Length This field sets the maximum number of Tx descriptors in the circular ring.
6596 */
6597#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)
6598/*! @} */
6599
6600/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH */
6601#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U)
6602
6603/*! @name DMA_CH_DMA_CHX_RXDESC_RING_LENGTH - Channelx Rx descriptor Ring Length */
6604/*! @{ */
6605#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)
6606#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)
6607/*! RDRL - Receive Ring Length This register sets the maximum number of Rx descriptors in the circular ring.
6608 */
6609#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)
6610/*! @} */
6611
6612/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH */
6613#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_COUNT (2U)
6614
6615/*! @name DMA_CH_DMA_CHX_INT_EN - Channelx Interrupt Enable */
6616/*! @{ */
6617#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK (0x1U)
6618#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT (0U)
6619/*! TIE - Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit
6620 * 16 in this register), Transmit Interrupt is enabled.
6621 */
6622#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK)
6623#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK (0x2U)
6624#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT (1U)
6625/*! TSE - Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit
6626 * 15 in this register), Transmission Stopped Interrupt is enabled.
6627 */
6628#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK)
6629#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK (0x4U)
6630#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT (2U)
6631/*! TBUE - Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary
6632 * Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled.
6633 */
6634#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK)
6635#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK (0x40U)
6636#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT (6U)
6637/*! RIE - Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16
6638 * in this register), Receive Interrupt is enabled.
6639 */
6640#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK)
6641#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK (0x80U)
6642#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT (7U)
6643/*! RBUE - Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary
6644 * Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled.
6645 */
6646#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK)
6647#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK (0x100U)
6648#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT (8U)
6649/*! RSE - Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit
6650 * 15 in this register), Receive Stopped Interrupt is enabled.
6651 */
6652#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK)
6653#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK (0x200U)
6654#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT (9U)
6655/*! RWTE - Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary
6656 * Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled.
6657 */
6658#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK)
6659#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK (0x400U)
6660#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT (10U)
6661/*! ETIE - Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary
6662 * Enable (bit 15 in this register), Early Transmit Interrupt is enabled.
6663 */
6664#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK)
6665#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK (0x800U)
6666#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT (11U)
6667/*! ERIE - Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable
6668 * (bit 16 in this register), Early Receive Interrupt is enabled.
6669 */
6670#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK)
6671#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK (0x1000U)
6672#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT (12U)
6673/*! FBEE - Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit
6674 * 15 in this register), the Fatal Bus Error Interrupt is enabled.
6675 */
6676#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK)
6677#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK (0x4000U)
6678#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT (14U)
6679/*! AIE - Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt summary is enabled.
6680 */
6681#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK)
6682#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK (0x8000U)
6683#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT (15U)
6684/*! NIE - Normal interrupt summary enable When this bit is set, a normal interrupt is enabled.
6685 */
6686#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK)
6687/*! @} */
6688
6689/* The count of ENET_DMA_CH_DMA_CHX_INT_EN */
6690#define ENET_DMA_CH_DMA_CHX_INT_EN_COUNT (2U)
6691
6692/*! @name DMA_CH_DMA_CHX_RX_INT_WDTIMER - Receive Interrupt Watchdog Timer */
6693/*! @{ */
6694#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK (0xFFU)
6695#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT (0U)
6696/*! RIWT - Receive Interrupt Watchdog Timer Count Indicates the number of system clock cycles
6697 * multiplied by 256 for which the watchdog timer is set.
6698 */
6699#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK)
6700/*! @} */
6701
6702/* The count of ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER */
6703#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_COUNT (2U)
6704
6705/*! @name DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT - Slot Function Control and Status */
6706/*! @{ */
6707#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)
6708#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)
6709/*! ESC - Enable Slot Comparison When set, this bit enables the checking of the slot numbers
6710 * programmed in the Tx descriptor with the current reference given in the RSN field.
6711 */
6712#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)
6713#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)
6714#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)
6715/*! ASC - Advance Slot Check When set, this bit enables the D MA to fetch the data from the buffer
6716 * when the slot number (SLOTNUM) programmed in the Tx descriptor is equal to the reference slot
6717 * number given in the RSN field or, ahead of the reference slot number by up to two slots This
6718 * bit is applicable only when the ESC bit is set.
6719 */
6720#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)
6721#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)
6722#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)
6723/*! RSN - Reference Slot Number This field gives the current value of the reference slot number in the DMA.
6724 */
6725#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)
6726/*! @} */
6727
6728/* The count of ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT */
6729#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U)
6730
6731/*! @name DMA_CH_DMA_CHX_CUR_HST_TXDESC - Channelx Current Host Transmit descriptor */
6732/*! @{ */
6733#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK (0xFFFFFFFFU)
6734#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT (0U)
6735/*! HTD - Host Transmit descriptor Address Pointer Cleared on Reset.
6736 */
6737#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK)
6738/*! @} */
6739
6740/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC */
6741#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_COUNT (2U)
6742
6743/*! @name DMA_CH_DMA_CHX_CUR_HST_RXDESC - */
6744/*! @{ */
6745#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK (0xFFFFFFFFU)
6746#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT (0U)
6747/*! HRD - Host Receive descriptor Address Pointer Cleared on Reset.
6748 */
6749#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK)
6750/*! @} */
6751
6752/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC */
6753#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_COUNT (2U)
6754
6755/*! @name DMA_CH_DMA_CHX_CUR_HST_TXBUF - */
6756/*! @{ */
6757#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK (0xFFFFFFFFU)
6758#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT (0U)
6759/*! HTB - Host Transmit Buffer Address Pointer Cleared on Reset.
6760 */
6761#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK)
6762/*! @} */
6763
6764/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF */
6765#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_COUNT (2U)
6766
6767/*! @name DMA_CH_DMA_CHX_CUR_HST_RXBUF - Channelx Current Application Receive Buffer Address */
6768/*! @{ */
6769#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK (0xFFFFFFFFU)
6770#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT (0U)
6771/*! HRB - Host Receive Buffer Address Pointer Cleared on Reset.
6772 */
6773#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK)
6774/*! @} */
6775
6776/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF */
6777#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_COUNT (2U)
6778
6779/*! @name DMA_CH_DMA_CHX_STAT - Channelx DMA status register */
6780/*! @{ */
6781#define ENET_DMA_CH_DMA_CHX_STAT_TI_MASK (0x1U)
6782#define ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT (0U)
6783/*! TI - Transmit Interrupt This bit indicates that the packet transmission is complete.
6784 */
6785#define ENET_DMA_CH_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK)
6786#define ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK (0x2U)
6787#define ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT (1U)
6788/*! TPS - Transmit Process Stopped This bit is set when the transmission is stopped.
6789 */
6790#define ENET_DMA_CH_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK)
6791#define ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK (0x4U)
6792#define ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT (2U)
6793/*! TBU - Transmit Buffer Unavailable This bit indicates that the application owns the next
6794 * descriptor in the transmit list, and the DMA cannot acquire it.
6795 */
6796#define ENET_DMA_CH_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK)
6797#define ENET_DMA_CH_DMA_CHX_STAT_RI_MASK (0x40U)
6798#define ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT (6U)
6799/*! RI - Receive Interrupt This bit indicates that the packet reception is complete.
6800 */
6801#define ENET_DMA_CH_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK)
6802#define ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK (0x80U)
6803#define ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT (7U)
6804/*! RBU - Receive Buffer Unavailable This bit indicates that the application owns the next in the
6805 * receive list, and the DMA cannot acquire it.
6806 */
6807#define ENET_DMA_CH_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK)
6808#define ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK (0x100U)
6809#define ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT (8U)
6810/*! RPS - Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state.
6811 */
6812#define ENET_DMA_CH_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK)
6813#define ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK (0x200U)
6814#define ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT (9U)
6815/*! RWT - Receive Watchdog time out This bit is asserted when a packet with length greater than
6816 * 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received.
6817 */
6818#define ENET_DMA_CH_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK)
6819#define ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK (0x400U)
6820#define ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT (10U)
6821/*! ETI - Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO.
6822 */
6823#define ENET_DMA_CH_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK)
6824#define ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK (0x800U)
6825#define ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT (11U)
6826/*! ERI - Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet.
6827 */
6828#define ENET_DMA_CH_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK)
6829#define ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK (0x1000U)
6830#define ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT (12U)
6831/*! FBE - Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field).
6832 */
6833#define ENET_DMA_CH_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK)
6834#define ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK (0x4000U)
6835#define ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT (14U)
6836/*! AIS - Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the
6837 * following when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable
6838 * register Table 778: Bit 1: Transmit Process Stopped Bit 7: Receive Buffer Unavailable Bit 8:
6839 * Receive Process Stopped Bit 10: Ear1y Transmit Interrupt Bit 12: Fatal Bus Error Only unmasked
6840 * bits affect the Abnormal Interrupt Summary bit.
6841 */
6842#define ENET_DMA_CH_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK)
6843#define ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK (0x8000U)
6844#define ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT (15U)
6845/*! NIS - Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the
6846 * following bits when the corresponding interrupt bits are enabled in the DMA Channel Interrupt
6847 * Enable register Table 778: Bit 0: Transmit Interrupt Bit 2: Transmit Buffer Unavailable Bit 6:
6848 * Receive Interrupt Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which
6849 * interrupt enable is set in DMA Channel Interrupt Enable register Table 778) affect the Normal
6850 * Interrupt Summary bit.
6851 */
6852#define ENET_DMA_CH_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK)
6853#define ENET_DMA_CH_DMA_CHX_STAT_EB_MASK (0x70000U)
6854#define ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT (16U)
6855/*! EB - DMA Error Bits This field indicates the type of error that caused a Bus Error.
6856 */
6857#define ENET_DMA_CH_DMA_CHX_STAT_EB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_EB_MASK)
6858/*! @} */
6859
6860/* The count of ENET_DMA_CH_DMA_CHX_STAT */
6861#define ENET_DMA_CH_DMA_CHX_STAT_COUNT (2U)
6862
6863/*! @name DMA_CH_DMA_CHX_MISS_FRAME_CNT - Channelx missed frame count. */
6864/*! @{ */
6865#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_MASK (0x7FFU)
6866#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT (0U)
6867/*! MFC - Dropped packet counters.
6868 */
6869#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT)) & ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_MASK)
6870#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U)
6871#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U)
6872/*! MFCO - Overflow status of the MFC counter.
6873 */
6874#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT)) & ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK)
6875/*! @} */
6876
6877/* The count of ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT */
6878#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_COUNT (2U)
6879
6880
6881/*!
6882 * @}
6883 */ /* end of group ENET_Register_Masks */
6884
6885
6886/* ENET - Peripheral instance base addresses */
6887/** Peripheral ENET base address */
6888#define ENET_BASE (0x40092000u)
6889/** Peripheral ENET base pointer */
6890#define ENET ((ENET_Type *)ENET_BASE)
6891/** Array initializer of ENET peripheral base addresses */
6892#define ENET_BASE_ADDRS { ENET_BASE }
6893/** Array initializer of ENET peripheral base pointers */
6894#define ENET_BASE_PTRS { ENET }
6895/** Interrupt vectors for the ENET peripheral type */
6896#define ENET_IRQS { ETHERNET_IRQn }
6897#define ENET_PMT_IRQS { ETHERNET_PMT_IRQn }
6898#define ENET_MACLP_IRQS { ETHERNET_MACLP_IRQn }
6899
6900/*!
6901 * @}
6902 */ /* end of group ENET_Peripheral_Access_Layer */
6903
6904
6905/* ----------------------------------------------------------------------------
6906 -- FLEXCOMM Peripheral Access Layer
6907 ---------------------------------------------------------------------------- */
6908
6909/*!
6910 * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
6911 * @{
6912 */
6913
6914/** FLEXCOMM - Register Layout Typedef */
6915typedef struct {
6916 uint8_t RESERVED_0[4088];
6917 __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
6918 __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */
6919} FLEXCOMM_Type;
6920
6921/* ----------------------------------------------------------------------------
6922 -- FLEXCOMM Register Masks
6923 ---------------------------------------------------------------------------- */
6924
6925/*!
6926 * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
6927 * @{
6928 */
6929
6930/*! @name PSELID - Peripheral Select and Flexcomm ID register. */
6931/*! @{ */
6932#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U)
6933#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U)
6934/*! PERSEL - Peripheral Select. This field is writable by software.
6935 * 0b000..No peripheral selected.
6936 * 0b001..USART function selected.
6937 * 0b010..SPI function selected.
6938 * 0b011..I2C function selected.
6939 * 0b100..I2S transmit function selected.
6940 * 0b101..I2S receive function selected.
6941 * 0b110..Reserved
6942 * 0b111..Reserved
6943 */
6944#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
6945#define FLEXCOMM_PSELID_LOCK_MASK (0x8U)
6946#define FLEXCOMM_PSELID_LOCK_SHIFT (3U)
6947/*! LOCK - Lock the peripheral select. This field is writable by software.
6948 * 0b0..Peripheral select can be changed by software.
6949 * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset.
6950 */
6951#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
6952#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U)
6953#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U)
6954/*! USARTPRESENT - USART present indicator. This field is Read-only.
6955 * 0b0..This Flexcomm does not include the USART function.
6956 * 0b1..This Flexcomm includes the USART function.
6957 */
6958#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
6959#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U)
6960#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U)
6961/*! SPIPRESENT - SPI present indicator. This field is Read-only.
6962 * 0b0..This Flexcomm does not include the SPI function.
6963 * 0b1..This Flexcomm includes the SPI function.
6964 */
6965#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
6966#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U)
6967#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U)
6968/*! I2CPRESENT - I2C present indicator. This field is Read-only.
6969 * 0b0..This Flexcomm does not include the I2C function.
6970 * 0b1..This Flexcomm includes the I2C function.
6971 */
6972#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
6973#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U)
6974#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U)
6975/*! I2SPRESENT - I 2S present indicator. This field is Read-only.
6976 * 0b0..This Flexcomm does not include the I2S function.
6977 * 0b1..This Flexcomm includes the I2S function.
6978 */
6979#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
6980#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U)
6981#define FLEXCOMM_PSELID_ID_SHIFT (12U)
6982/*! ID - Flexcomm ID.
6983 */
6984#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
6985/*! @} */
6986
6987/*! @name PID - Peripheral identification register. */
6988/*! @{ */
6989#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U)
6990#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U)
6991/*! Minor_Rev - Minor revision of module implementation.
6992 */
6993#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)
6994#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U)
6995#define FLEXCOMM_PID_Major_Rev_SHIFT (12U)
6996/*! Major_Rev - Major revision of module implementation.
6997 */
6998#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)
6999#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U)
7000#define FLEXCOMM_PID_ID_SHIFT (16U)
7001/*! ID - Module identifier for the selected function.
7002 */
7003#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
7004/*! @} */
7005
7006
7007/*!
7008 * @}
7009 */ /* end of group FLEXCOMM_Register_Masks */
7010
7011
7012/* FLEXCOMM - Peripheral instance base addresses */
7013/** Peripheral FLEXCOMM0 base address */
7014#define FLEXCOMM0_BASE (0x40086000u)
7015/** Peripheral FLEXCOMM0 base pointer */
7016#define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
7017/** Peripheral FLEXCOMM1 base address */
7018#define FLEXCOMM1_BASE (0x40087000u)
7019/** Peripheral FLEXCOMM1 base pointer */
7020#define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
7021/** Peripheral FLEXCOMM2 base address */
7022#define FLEXCOMM2_BASE (0x40088000u)
7023/** Peripheral FLEXCOMM2 base pointer */
7024#define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
7025/** Peripheral FLEXCOMM3 base address */
7026#define FLEXCOMM3_BASE (0x40089000u)
7027/** Peripheral FLEXCOMM3 base pointer */
7028#define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
7029/** Peripheral FLEXCOMM4 base address */
7030#define FLEXCOMM4_BASE (0x4008A000u)
7031/** Peripheral FLEXCOMM4 base pointer */
7032#define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
7033/** Peripheral FLEXCOMM5 base address */
7034#define FLEXCOMM5_BASE (0x40096000u)
7035/** Peripheral FLEXCOMM5 base pointer */
7036#define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
7037/** Peripheral FLEXCOMM6 base address */
7038#define FLEXCOMM6_BASE (0x40097000u)
7039/** Peripheral FLEXCOMM6 base pointer */
7040#define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
7041/** Peripheral FLEXCOMM7 base address */
7042#define FLEXCOMM7_BASE (0x40098000u)
7043/** Peripheral FLEXCOMM7 base pointer */
7044#define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
7045/** Peripheral FLEXCOMM8 base address */
7046#define FLEXCOMM8_BASE (0x40099000u)
7047/** Peripheral FLEXCOMM8 base pointer */
7048#define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
7049/** Peripheral FLEXCOMM9 base address */
7050#define FLEXCOMM9_BASE (0x4009A000u)
7051/** Peripheral FLEXCOMM9 base pointer */
7052#define FLEXCOMM9 ((FLEXCOMM_Type *)FLEXCOMM9_BASE)
7053/** Peripheral FLEXCOMM10 base address */
7054#define FLEXCOMM10_BASE (0x4009F000u)
7055/** Peripheral FLEXCOMM10 base pointer */
7056#define FLEXCOMM10 ((FLEXCOMM_Type *)FLEXCOMM10_BASE)
7057/** Array initializer of FLEXCOMM peripheral base addresses */
7058#define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE, FLEXCOMM10_BASE }
7059/** Array initializer of FLEXCOMM peripheral base pointers */
7060#define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9, FLEXCOMM10 }
7061/** Interrupt vectors for the FLEXCOMM peripheral type */
7062#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn, FLEXCOMM10_IRQn }
7063
7064/*!
7065 * @}
7066 */ /* end of group FLEXCOMM_Peripheral_Access_Layer */
7067
7068
7069/* ----------------------------------------------------------------------------
7070 -- GINT Peripheral Access Layer
7071 ---------------------------------------------------------------------------- */
7072
7073/*!
7074 * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer
7075 * @{
7076 */
7077
7078/** GINT - Register Layout Typedef */
7079typedef struct {
7080 __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */
7081 uint8_t RESERVED_0[28];
7082 __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */
7083 uint8_t RESERVED_1[24];
7084 __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */
7085} GINT_Type;
7086
7087/* ----------------------------------------------------------------------------
7088 -- GINT Register Masks
7089 ---------------------------------------------------------------------------- */
7090
7091/*!
7092 * @addtogroup GINT_Register_Masks GINT Register Masks
7093 * @{
7094 */
7095
7096/*! @name CTRL - GPIO grouped interrupt control register */
7097/*! @{ */
7098#define GINT_CTRL_INT_MASK (0x1U)
7099#define GINT_CTRL_INT_SHIFT (0U)
7100/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.
7101 * 0b0..No request. No interrupt request is pending.
7102 * 0b1..Request active. Interrupt request is active.
7103 */
7104#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)
7105#define GINT_CTRL_COMB_MASK (0x2U)
7106#define GINT_CTRL_COMB_SHIFT (1U)
7107/*! COMB - Combine enabled inputs for group interrupt
7108 * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).
7109 * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).
7110 */
7111#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)
7112#define GINT_CTRL_TRIG_MASK (0x4U)
7113#define GINT_CTRL_TRIG_SHIFT (2U)
7114/*! TRIG - Group interrupt trigger
7115 * 0b0..Edge-triggered.
7116 * 0b1..Level-triggered.
7117 */
7118#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)
7119/*! @} */
7120
7121/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */
7122/*! @{ */
7123#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU)
7124#define GINT_PORT_POL_POL_SHIFT (0U)
7125/*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n
7126 * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to
7127 * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin
7128 * contributes to the group interrupt.
7129 */
7130#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)
7131/*! @} */
7132
7133/* The count of GINT_PORT_POL */
7134#define GINT_PORT_POL_COUNT (2U)
7135
7136/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */
7137/*! @{ */
7138#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU)
7139#define GINT_PORT_ENA_ENA_SHIFT (0U)
7140/*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the
7141 * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is
7142 * enabled and contributes to the grouped interrupt.
7143 */
7144#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)
7145/*! @} */
7146
7147/* The count of GINT_PORT_ENA */
7148#define GINT_PORT_ENA_COUNT (2U)
7149
7150
7151/*!
7152 * @}
7153 */ /* end of group GINT_Register_Masks */
7154
7155
7156/* GINT - Peripheral instance base addresses */
7157/** Peripheral GINT0 base address */
7158#define GINT0_BASE (0x40002000u)
7159/** Peripheral GINT0 base pointer */
7160#define GINT0 ((GINT_Type *)GINT0_BASE)
7161/** Peripheral GINT1 base address */
7162#define GINT1_BASE (0x40003000u)
7163/** Peripheral GINT1 base pointer */
7164#define GINT1 ((GINT_Type *)GINT1_BASE)
7165/** Array initializer of GINT peripheral base addresses */
7166#define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE }
7167/** Array initializer of GINT peripheral base pointers */
7168#define GINT_BASE_PTRS { GINT0, GINT1 }
7169/** Interrupt vectors for the GINT peripheral type */
7170#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn }
7171
7172/*!
7173 * @}
7174 */ /* end of group GINT_Peripheral_Access_Layer */
7175
7176
7177/* ----------------------------------------------------------------------------
7178 -- GPIO Peripheral Access Layer
7179 ---------------------------------------------------------------------------- */
7180
7181/*!
7182 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
7183 * @{
7184 */
7185
7186/** GPIO - Register Layout Typedef */
7187typedef struct {
7188 __IO uint8_t B[6][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
7189 uint8_t RESERVED_0[3904];
7190 __IO uint32_t W[6][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
7191 uint8_t RESERVED_1[3328];
7192 __IO uint32_t DIR[6]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */
7193 uint8_t RESERVED_2[104];
7194 __IO uint32_t MASK[6]; /**< Mask register, array offset: 0x2080, array step: 0x4 */
7195 uint8_t RESERVED_3[104];
7196 __IO uint32_t PIN[6]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */
7197 uint8_t RESERVED_4[104];
7198 __IO uint32_t MPIN[6]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */
7199 uint8_t RESERVED_5[104];
7200 __IO uint32_t SET[6]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
7201 uint8_t RESERVED_6[104];
7202 __O uint32_t CLR[6]; /**< Clear port, array offset: 0x2280, array step: 0x4 */
7203 uint8_t RESERVED_7[104];
7204 __O uint32_t NOT[6]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */
7205 uint8_t RESERVED_8[104];
7206 __O uint32_t DIRSET[6]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
7207 uint8_t RESERVED_9[104];
7208 __O uint32_t DIRCLR[6]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
7209 uint8_t RESERVED_10[104];
7210 __O uint32_t DIRNOT[6]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
7211} GPIO_Type;
7212
7213/* ----------------------------------------------------------------------------
7214 -- GPIO Register Masks
7215 ---------------------------------------------------------------------------- */
7216
7217/*!
7218 * @addtogroup GPIO_Register_Masks GPIO Register Masks
7219 * @{
7220 */
7221
7222/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
7223/*! @{ */
7224#define GPIO_B_PBYTE_MASK (0x1U)
7225#define GPIO_B_PBYTE_SHIFT (0U)
7226/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function,
7227 * except that pins configured as analog I/O always read as 0. One register for each port pin.
7228 * Supported pins depends on the specific device and package. Write: loads the pin's output bit.
7229 * One register for each port pin. Supported pins depends on the specific device and package.
7230 */
7231#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
7232/*! @} */
7233
7234/* The count of GPIO_B */
7235#define GPIO_B_COUNT (6U)
7236
7237/* The count of GPIO_B */
7238#define GPIO_B_COUNT2 (32U)
7239
7240/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
7241/*! @{ */
7242#define GPIO_W_PWORD_MASK (0xFFFFFFFFU)
7243#define GPIO_W_PWORD_SHIFT (0U)
7244/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is
7245 * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be
7246 * read. Writing any value other than 0 will set the output bit. One register for each port pin.
7247 * Supported pins depends on the specific device and package.
7248 */
7249#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
7250/*! @} */
7251
7252/* The count of GPIO_W */
7253#define GPIO_W_COUNT (6U)
7254
7255/* The count of GPIO_W */
7256#define GPIO_W_COUNT2 (32U)
7257
7258/*! @name DIR - Direction registers */
7259/*! @{ */
7260#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU)
7261#define GPIO_DIR_DIRP_SHIFT (0U)
7262/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
7263 * pins depends on the specific device and package. 0 = input. 1 = output.
7264 */
7265#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
7266/*! @} */
7267
7268/* The count of GPIO_DIR */
7269#define GPIO_DIR_COUNT (6U)
7270
7271/*! @name MASK - Mask register */
7272/*! @{ */
7273#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU)
7274#define GPIO_MASK_MASKP_SHIFT (0U)
7275/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 =
7276 * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 =
7277 * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit
7278 * not affected.
7279 */
7280#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
7281/*! @} */
7282
7283/* The count of GPIO_MASK */
7284#define GPIO_MASK_COUNT (6U)
7285
7286/*! @name PIN - Port pin register */
7287/*! @{ */
7288#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU)
7289#define GPIO_PIN_PORT_SHIFT (0U)
7290/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
7291 * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit.
7292 * 1 = Read: pin is high; write: set output bit.
7293 */
7294#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
7295/*! @} */
7296
7297/* The count of GPIO_PIN */
7298#define GPIO_PIN_COUNT (6U)
7299
7300/*! @name MPIN - Masked port register */
7301/*! @{ */
7302#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU)
7303#define GPIO_MPIN_MPORTP_SHIFT (0U)
7304/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
7305 * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK
7306 * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1
7307 * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit
7308 * if the corresponding bit in the MASK register is 0.
7309 */
7310#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
7311/*! @} */
7312
7313/* The count of GPIO_MPIN */
7314#define GPIO_MPIN_COUNT (6U)
7315
7316/*! @name SET - Write: Set register for port Read: output bits for port */
7317/*! @{ */
7318#define GPIO_SET_SETP_MASK (0xFFFFFFFFU)
7319#define GPIO_SET_SETP_SHIFT (0U)
7320/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
7321 * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output
7322 * bit; write: set output bit.
7323 */
7324#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
7325/*! @} */
7326
7327/* The count of GPIO_SET */
7328#define GPIO_SET_COUNT (6U)
7329
7330/*! @name CLR - Clear port */
7331/*! @{ */
7332#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU)
7333#define GPIO_CLR_CLRP_SHIFT (0U)
7334/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
7335 * specific device and package. 0 = No operation. 1 = Clear output bit.
7336 */
7337#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
7338/*! @} */
7339
7340/* The count of GPIO_CLR */
7341#define GPIO_CLR_COUNT (6U)
7342
7343/*! @name NOT - Toggle port */
7344/*! @{ */
7345#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU)
7346#define GPIO_NOT_NOTP_SHIFT (0U)
7347/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
7348 * specific device and package. 0 = no operation. 1 = Toggle output bit.
7349 */
7350#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
7351/*! @} */
7352
7353/* The count of GPIO_NOT */
7354#define GPIO_NOT_COUNT (6U)
7355
7356/*! @name DIRSET - Set pin direction bits for port */
7357/*! @{ */
7358#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU)
7359#define GPIO_DIRSET_DIRSETP_SHIFT (0U)
7360/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
7361 * the specific device and package. 0 = No operation. 1 = Set direction bit.
7362 */
7363#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
7364/*! @} */
7365
7366/* The count of GPIO_DIRSET */
7367#define GPIO_DIRSET_COUNT (6U)
7368
7369/*! @name DIRCLR - Clear pin direction bits for port */
7370/*! @{ */
7371#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU)
7372#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U)
7373/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
7374 * the specific device and package. 0 = No operation. 1 = Clear direction bit.
7375 */
7376#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
7377/*! @} */
7378
7379/* The count of GPIO_DIRCLR */
7380#define GPIO_DIRCLR_COUNT (6U)
7381
7382/*! @name DIRNOT - Toggle pin direction bits for port */
7383/*! @{ */
7384#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU)
7385#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U)
7386/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends
7387 * on the specific device and package. 0 = no operation. 1 = Toggle direction bit.
7388 */
7389#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
7390/*! @} */
7391
7392/* The count of GPIO_DIRNOT */
7393#define GPIO_DIRNOT_COUNT (6U)
7394
7395
7396/*!
7397 * @}
7398 */ /* end of group GPIO_Register_Masks */
7399
7400
7401/* GPIO - Peripheral instance base addresses */
7402/** Peripheral GPIO base address */
7403#define GPIO_BASE (0x4008C000u)
7404/** Peripheral GPIO base pointer */
7405#define GPIO ((GPIO_Type *)GPIO_BASE)
7406/** Array initializer of GPIO peripheral base addresses */
7407#define GPIO_BASE_ADDRS { GPIO_BASE }
7408/** Array initializer of GPIO peripheral base pointers */
7409#define GPIO_BASE_PTRS { GPIO }
7410
7411/*!
7412 * @}
7413 */ /* end of group GPIO_Peripheral_Access_Layer */
7414
7415
7416/* ----------------------------------------------------------------------------
7417 -- I2C Peripheral Access Layer
7418 ---------------------------------------------------------------------------- */
7419
7420/*!
7421 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
7422 * @{
7423 */
7424
7425/** I2C - Register Layout Typedef */
7426typedef struct {
7427 uint8_t RESERVED_0[2048];
7428 __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */
7429 __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */
7430 __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */
7431 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */
7432 __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */
7433 __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */
7434 __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */
7435 uint8_t RESERVED_1[4];
7436 __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */
7437 __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */
7438 __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */
7439 uint8_t RESERVED_2[20];
7440 __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */
7441 __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */
7442 __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */
7443 __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */
7444 uint8_t RESERVED_3[36];
7445 __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */
7446 uint8_t RESERVED_4[1912];
7447 __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
7448} I2C_Type;
7449
7450/* ----------------------------------------------------------------------------
7451 -- I2C Register Masks
7452 ---------------------------------------------------------------------------- */
7453
7454/*!
7455 * @addtogroup I2C_Register_Masks I2C Register Masks
7456 * @{
7457 */
7458
7459/*! @name CFG - Configuration for shared functions. */
7460/*! @{ */
7461#define I2C_CFG_MSTEN_MASK (0x1U)
7462#define I2C_CFG_MSTEN_SHIFT (0U)
7463/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not
7464 * changed, but the Master function is internally reset.
7465 * 0b0..Disabled. The I2C Master function is disabled.
7466 * 0b1..Enabled. The I2C Master function is enabled.
7467 */
7468#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
7469#define I2C_CFG_SLVEN_MASK (0x2U)
7470#define I2C_CFG_SLVEN_SHIFT (1U)
7471/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not
7472 * changed, but the Slave function is internally reset.
7473 * 0b0..Disabled. The I2C slave function is disabled.
7474 * 0b1..Enabled. The I2C slave function is enabled.
7475 */