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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54016/system_LPC54016.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54016/system_LPC54016.c
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1/*
2** ###################################################################
3** Processors: LPC54016JBD100
4** LPC54016JBD208
5** LPC54016JET180
6**
7** Compilers: GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9** Keil ARM C/C++ Compiler
10** MCUXpresso Compiler
11**
12** Reference manual: LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
13** Version: rev. 1.2, 2017-06-08
14** Build: b201015
15**
16** Abstract:
17** Provides a system configuration function and a global variable that
18** contains the system frequency. It configures the device and initializes
19** the oscillator (PLL) that is part of the microcontroller device.
20**
21** Copyright 2016 Freescale Semiconductor, Inc.
22** Copyright 2016-2020 NXP
23** All rights reserved.
24**
25** SPDX-License-Identifier: BSD-3-Clause
26**
27** http: www.nxp.com
28** mail: [email protected]
29**
30** Revisions:
31** - rev. 1.0 (2016-08-12)
32** Initial version.
33** - rev. 1.1 (2016-11-25)
34** Update CANFD and Classic CAN register.
35** Add MAC TIMERSTAMP registers.
36** - rev. 1.2 (2017-06-08)
37** Remove RTC_CTRL_RTC_OSC_BYPASS.
38** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
39** Remove RESET and HALT from SYSCON_AHBCLKDIV.
40**
41** ###################################################################
42*/
43
44/*!
45 * @file LPC54016
46 * @version 1.2
47 * @date 2017-06-08
48 * @brief Device specific configuration file for LPC54016 (implementation file)
49 *
50 * Provides a system configuration function and a global variable that contains
51 * the system frequency. It configures the device and initializes the oscillator
52 * (PLL) that is part of the microcontroller device.
53 */
54
55#include <stdint.h>
56#include "fsl_device_registers.h"
57
58#define NVALMAX (0x100)
59#define PVALMAX (0x20)
60#define MVALMAX (0x8000)
61#define PLL_MDEC_VAL_P (0) /* MDEC is in bits 16:0 */
62#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
63#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */
64#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
65#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */
66#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
67
68static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41,
69 42, 44, 45, 46, 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
70/* Get WATCH DOG Clk */
71static uint32_t getWdtOscFreq(void)
72{
73 uint8_t freq_sel, div_sel;
74 if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) != 0UL)
75 {
76 return 0U;
77 }
78 else
79 {
80 div_sel = (uint8_t)((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1UL) << 1UL;
81 freq_sel =
82 wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
83 return ((uint32_t)freq_sel * 50000U) / ((uint32_t)div_sel);
84 }
85}
86/* Find decoded N value for raw NDEC value */
87static uint32_t pllDecodeN(uint32_t NDEC)
88{
89 uint32_t n, x, i;
90
91 /* Find NDec */
92 switch (NDEC)
93 {
94 case 0x3FF:
95 n = 0UL;
96 break;
97 case 0x302:
98 n = 1UL;
99 break;
100 case 0x202:
101 n = 2UL;
102 break;
103 default:
104 x = 0x080UL;
105 n = 0xFFFFFFFFUL;
106 for (i = NVALMAX; i >= 3UL; i--)
107 {
108 x = (((x ^ (x >> 2UL) ^ (x >> 3UL) ^ (x >> 4UL)) & 1UL) << 7UL) | ((x >> 1UL) & 0x7FUL);
109 if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
110 {
111 /* Decoded value of NDEC */
112 n = i;
113 }
114 if (n != 0xFFFFFFFFUL)
115 {
116 break;
117 }
118 }
119 break;
120 }
121 return n;
122}
123
124/* Find decoded P value for raw PDEC value */
125static uint32_t pllDecodeP(uint32_t PDEC)
126{
127 uint32_t p, x, i;
128 /* Find PDec */
129 switch (PDEC)
130 {
131 case 0x7F:
132 p = 0UL;
133 break;
134 case 0x62:
135 p = 1UL;
136 break;
137 case 0x42:
138 p = 2UL;
139 break;
140 default:
141 x = 0x10UL;
142 p = 0xFFFFFFFFUL;
143 for (i = PVALMAX; i >= 3UL; i--)
144 {
145 x = (((x ^ (x >> 2UL)) & 1UL) << 4UL) | ((x >> 1UL) & 0xFUL);
146 if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
147 {
148 /* Decoded value of PDEC */
149 p = i;
150 }
151 if (p != 0xFFFFFFFFUL)
152 {
153 break;
154 }
155 }
156 break;
157 }
158 return p;
159}
160
161/* Find decoded M value for raw MDEC value */
162static uint32_t pllDecodeM(uint32_t MDEC)
163{
164 uint32_t m, i, x;
165
166 /* Find MDec */
167 switch (MDEC)
168 {
169 case 0x1FFFF:
170 m = 0UL;
171 break;
172 case 0x18003:
173 m = 1UL;
174 break;
175 case 0x10003:
176 m = 2UL;
177 break;
178 default:
179 x = 0x04000UL;
180 m = 0xFFFFFFFFUL;
181 for (i = MVALMAX; i >= 3UL; i--)
182 {
183 x = (((x ^ (x >> 1UL)) & 1UL) << 14UL) | ((x >> 1UL) & 0x3FFFUL);
184 if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
185 {
186 /* Decoded value of MDEC */
187 m = i;
188 }
189 if (m != 0xFFFFFFFFUL)
190 {
191 break;
192 }
193 }
194 break;
195 }
196 return m;
197}
198
199/* Get predivider (N) from PLL NDEC setting */
200static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
201{
202 uint32_t preDiv = 1;
203
204 /* Direct input is not used? */
205 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0UL)
206 {
207 /* Decode NDEC value to get (N) pre divider */
208 preDiv = pllDecodeN(nDecReg & 0x3FFUL);
209 if (preDiv == 0UL)
210 {
211 preDiv = 1;
212 }
213 }
214 /* Adjusted by 1, directi is used to bypass */
215 return preDiv;
216}
217
218/* Get postdivider (P) from PLL PDEC setting */
219static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
220{
221 uint32_t postDiv = 1;
222
223 /* Direct input is not used? */
224 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0UL)
225 {
226 /* Decode PDEC value to get (P) post divider */
227 postDiv = 2UL * pllDecodeP(pDecReg & 0x7FUL);
228 if (postDiv == 0UL)
229 {
230 postDiv = 2;
231 }
232 }
233 /* Adjusted by 1, directo is used to bypass */
234 return postDiv;
235}
236
237/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
238static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
239{
240 uint32_t mMult = 1;
241
242 /* Decode MDEC value to get (M) multiplier */
243 mMult = pllDecodeM(mDecReg & 0x1FFFFUL);
244 if (mMult == 0UL)
245 {
246 mMult = 1;
247 }
248 return mMult;
249}
250
251/* ----------------------------------------------------------------------------
252 -- Core clock
253 ---------------------------------------------------------------------------- */
254
255uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
256
257/* ----------------------------------------------------------------------------
258 -- SystemInit()
259 ---------------------------------------------------------------------------- */
260
261void SystemInit(void)
262{
263#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
264 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
265#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
266
267#if defined(__MCUXPRESSO)
268 extern void (*const g_pfnVectors[])(void);
269 SCB->VTOR = (uint32_t)&g_pfnVectors;
270#else
271 extern void *__Vectors;
272 SCB->VTOR = (uint32_t)&__Vectors;
273#endif
274 SYSCON->ARMTRACECLKDIV = 0;
275/* Optionally enable RAM banks that may be off by default at reset */
276#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
277 SYSCON->AHBCLKCTRLSET[0] =
278 SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
279
280#endif
281 SYSCON->MAINCLKSELA = 0U;
282 SYSCON->MAINCLKSELB = 0U;
283 SystemInitHook();
284}
285
286/* ----------------------------------------------------------------------------
287 -- SystemCoreClockUpdate()
288 ---------------------------------------------------------------------------- */
289
290void SystemCoreClockUpdate(void)
291{
292 uint32_t clkRate = 0;
293 uint32_t prediv, postdiv;
294 uint64_t workRate;
295
296 switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
297 {
298 case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
299 switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
300 {
301 case 0x00: /* FRO 12 MHz (fro_12m) */
302 clkRate = CLK_FRO_12MHZ;
303 break;
304 case 0x01: /* CLKIN Source (clk_in) */
305 clkRate = CLK_CLK_IN;
306 break;
307 case 0x02: /* Watchdog oscillator (wdt_clk) */
308 clkRate = getWdtOscFreq();
309 break;
310 default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
311 if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) == SYSCON_FROCTRL_SEL_MASK)
312 {
313 clkRate = CLK_FRO_96MHZ;
314 }
315 else
316 {
317 clkRate = CLK_FRO_48MHZ;
318 }
319 break;
320 }
321 break;
322 case 0x02: /* System PLL clock (pll_clk)*/
323 switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
324 {
325 case 0x00: /* FRO 12 MHz (fro_12m) */
326 clkRate = CLK_FRO_12MHZ;
327 break;
328 case 0x01: /* CLKIN Source (clk_in) */
329 clkRate = CLK_CLK_IN;
330 break;
331 case 0x02: /* Watchdog oscillator (wdt_clk) */
332 clkRate = getWdtOscFreq();
333 break;
334 case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
335 clkRate = CLK_RTC_32K_CLK;
336 break;
337 default:
338 clkRate = 0UL;
339 break;
340 }
341 if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0UL)
342 {
343 /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
344 prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
345 postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
346 /* Adjust input clock */
347 clkRate = clkRate / prediv;
348
349 /* MDEC used for rate */
350 workRate = (uint64_t)(clkRate) * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
351 clkRate = (uint32_t)(workRate / ((uint64_t)postdiv));
352 clkRate = clkRate * 2UL; /* PLL CCO output is divided by 2 before to M-Divider */
353 }
354 break;
355 case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
356 clkRate = CLK_RTC_32K_CLK;
357 break;
358 default:
359 clkRate = 0UL;
360 break;
361 }
362 SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL);
363}
364
365/* ----------------------------------------------------------------------------
366 -- SystemInitHook()
367 ---------------------------------------------------------------------------- */
368
369__attribute__((weak)) void SystemInitHook(void)
370{
371 /* Void implementation of the weak function. */
372}
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