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1/*
2** ###################################################################
3** Processors: LPC54018JBD208
4** LPC54018JET180
5**
6** Compilers: GNU C Compiler
7** IAR ANSI C/C++ Compiler for ARM
8** Keil ARM C/C++ Compiler
9** MCUXpresso Compiler
10**
11** Reference manual: LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
12** Version: rev. 1.2, 2017-06-08
13** Build: b200304
14**
15** Abstract:
16** CMSIS Peripheral Access Layer for LPC54018
17**
18** Copyright 1997-2016 Freescale Semiconductor, Inc.
19** Copyright 2016-2020 NXP
20** All rights reserved.
21**
22** SPDX-License-Identifier: BSD-3-Clause
23**
24** http: www.nxp.com
25** mail: [email protected]
26**
27** Revisions:
28** - rev. 1.0 (2016-08-12)
29** Initial version.
30** - rev. 1.1 (2016-11-25)
31** Update CANFD and Classic CAN register.
32** Add MAC TIMERSTAMP registers.
33** - rev. 1.2 (2017-06-08)
34** Remove RTC_CTRL_RTC_OSC_BYPASS.
35** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
36** Remove RESET and HALT from SYSCON_AHBCLKDIV.
37**
38** ###################################################################
39*/
40
41/*!
42 * @file LPC54018.h
43 * @version 1.2
44 * @date 2017-06-08
45 * @brief CMSIS Peripheral Access Layer for LPC54018
46 *
47 * CMSIS Peripheral Access Layer for LPC54018
48 */
49
50#ifndef _LPC54018_H_
51#define _LPC54018_H_ /**< Symbol preventing repeated inclusion */
52
53/** Memory map major version (memory maps with equal major version number are
54 * compatible) */
55#define MCU_MEM_MAP_VERSION 0x0100U
56/** Memory map minor version */
57#define MCU_MEM_MAP_VERSION_MINOR 0x0002U
58
59
60/* ----------------------------------------------------------------------------
61 -- Interrupt vector numbers
62 ---------------------------------------------------------------------------- */
63
64/*!
65 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
66 * @{
67 */
68
69/** Interrupt Number Definitions */
70#define NUMBER_OF_INT_VECTORS 73 /**< Number of interrupts in the Vector table */
71
72typedef enum IRQn {
73 /* Auxiliary constants */
74 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
75
76 /* Core interrupts */
77 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
78 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
79 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
80 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
81 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
82 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
83 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
84 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
85 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
86
87 /* Device specific interrupts */
88 WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */
89 DMA0_IRQn = 1, /**< DMA controller */
90 GINT0_IRQn = 2, /**< GPIO group 0 */
91 GINT1_IRQn = 3, /**< GPIO group 1 */
92 PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */
93 PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */
94 PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */
95 PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */
96 UTICK0_IRQn = 8, /**< Micro-tick Timer */
97 MRT0_IRQn = 9, /**< Multi-rate timer */
98 CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
99 CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
100 SCT0_IRQn = 12, /**< SCTimer/PWM */
101 CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
102 FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
103 FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
104 FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
105 FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
106 FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
107 FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
108 FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
109 FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
110 ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */
111 ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */
112 ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */
113 DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */
114 HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */
115 USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */
116 USB0_IRQn = 28, /**< USB device */
117 RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */
118 FLEXCOMM10_IRQn = 30, /**< Flexcomm Interface 10 (SPI, FLEXCOMM) */
119 Reserved47_IRQn = 31, /**< Reserved interrupt */
120 PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */
121 PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */
122 PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */
123 PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */
124 CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */
125 CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */
126 RIT_IRQn = 38, /**< Repetitive Interrupt Timer */
127 SPIFI0_IRQn = 39, /**< SPI flash interface */
128 FLEXCOMM8_IRQn = 40, /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
129 FLEXCOMM9_IRQn = 41, /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
130 SDIO_IRQn = 42, /**< SD/MMC */
131 CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */
132 CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */
133 CAN1_IRQ0_IRQn = 45, /**< CAN1 interrupt0 */
134 CAN1_IRQ1_IRQn = 46, /**< CAN1 interrupt1 */
135 USB1_IRQn = 47, /**< USB1 interrupt */
136 USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */
137 ETHERNET_IRQn = 49, /**< Ethernet */
138 ETHERNET_PMT_IRQn = 50, /**< Ethernet power management interrupt */
139 ETHERNET_MACLP_IRQn = 51, /**< Ethernet MAC interrupt */
140 Reserved68_IRQn = 52, /**< Reserved interrupt */
141 LCD_IRQn = 53, /**< LCD interrupt */
142 SHA_IRQn = 54, /**< SHA interrupt */
143 SMARTCARD0_IRQn = 55, /**< Smart card 0 interrupt */
144 SMARTCARD1_IRQn = 56 /**< Smart card 1 interrupt */
145} IRQn_Type;
146
147/*!
148 * @}
149 */ /* end of group Interrupt_vector_numbers */
150
151
152/* ----------------------------------------------------------------------------
153 -- Cortex M4 Core Configuration
154 ---------------------------------------------------------------------------- */
155
156/*!
157 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
158 * @{
159 */
160
161#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
162#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
163#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
164#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
165
166#include "core_cm4.h" /* Core Peripheral Access Layer */
167#include "system_LPC54018.h" /* Device specific configuration file */
168
169/*!
170 * @}
171 */ /* end of group Cortex_Core_Configuration */
172
173
174/* ----------------------------------------------------------------------------
175 -- Mapping Information
176 ---------------------------------------------------------------------------- */
177
178/*!
179 * @addtogroup Mapping_Information Mapping Information
180 * @{
181 */
182
183/** Mapping Information */
184/*!
185 * @addtogroup dma_request
186 * @{
187 */
188
189/*******************************************************************************
190 * Definitions
191 ******************************************************************************/
192
193/*!
194 * @brief Structure for the DMA hardware request
195 *
196 * Defines the structure for the DMA hardware request collections. The user can configure the
197 * hardware request to trigger the DMA transfer accordingly. The index
198 * of the hardware request varies according to the to SoC.
199 */
200typedef enum _dma_request_source
201{
202 kDmaRequestFlexcomm0Rx = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */
203 kDmaRequestFlexcomm0Tx = 1U, /**< Flexcomm Interface 0 TX/I2C Master */
204 kDmaRequestFlexcomm1Rx = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */
205 kDmaRequestFlexcomm1Tx = 3U, /**< Flexcomm Interface 1 TX/I2C Master */
206 kDmaRequestFlexcomm2Rx = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */
207 kDmaRequestFlexcomm2Tx = 5U, /**< Flexcomm Interface 2 TX/I2C Master */
208 kDmaRequestFlexcomm3Rx = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */
209 kDmaRequestFlexcomm3Tx = 7U, /**< Flexcomm Interface 3 TX/I2C Master */
210 kDmaRequestFlexcomm4Rx = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */
211 kDmaRequestFlexcomm4Tx = 9U, /**< Flexcomm Interface 4 TX/I2C Master */
212 kDmaRequestFlexcomm5Rx = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */
213 kDmaRequestFlexcomm5Tx = 11U, /**< Flexcomm Interface 5 TX/I2C Master */
214 kDmaRequestFlexcomm6Rx = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */
215 kDmaRequestFlexcomm6Tx = 13U, /**< Flexcomm Interface 6 TX/I2C Master */
216 kDmaRequestFlexcomm7Rx = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */
217 kDmaRequestFlexcomm7Tx = 15U, /**< Flexcomm Interface 7 TX/I2C Master */
218 kDmaRequestDMIC0 = 16U, /**< Digital microphone interface 0 channel 0 */
219 kDmaRequestDMIC1 = 17U, /**< Digital microphone interface 0 channel 1 */
220 kDmaRequestSPIFI = 18U, /**< SPI Flash Interface */
221 kDmaRequestSHA = 19U, /**< Secure Hash Algorithm */
222 kDmaRequestFlexcomm8Rx = 20U, /**< Flexcomm Interface 8 RX/I2C Slave */
223 kDmaRequestFlexcomm8Tx = 21U, /**< Flexcomm Interface 8 TX/I2C Slave */
224 kDmaRequestFlexcomm9Rx = 22U, /**< Flexcomm Interface 9 RX/I2C Slave */
225 kDmaRequestFlexcomm9Tx = 23U, /**< Flexcomm Interface 9 TX/I2C Slave */
226 kDmaRequestSMARTCARD0_RX = 24U, /**< SMARTCARD0 RX */
227 kDmaRequestSMARTCARD0_TX = 25U, /**< SMARTCARD0 TX */
228 kDmaRequestSMARTCARD1_RX = 26U, /**< SMARTCARD1 RX */
229 kDmaRequestSMARTCARD1_TX = 27U, /**< SMARTCARD1 TX */
230 kDmaRequestFlexcomm10Rx = 28U, /**< Flexcomm Interface 10 RX */
231 kDmaRequestFlexcomm10Tx = 29U, /**< Flexcomm Interface 10 TX */
232} dma_request_source_t;
233
234/* @} */
235
236
237/*!
238 * @}
239 */ /* end of group Mapping_Information */
240
241
242/* ----------------------------------------------------------------------------
243 -- Device Peripheral Access Layer
244 ---------------------------------------------------------------------------- */
245
246/*!
247 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
248 * @{
249 */
250
251
252/*
253** Start of section using anonymous unions
254*/
255
256#if defined(__ARMCC_VERSION)
257 #if (__ARMCC_VERSION >= 6010050)
258 #pragma clang diagnostic push
259 #else
260 #pragma push
261 #pragma anon_unions
262 #endif
263#elif defined(__GNUC__)
264 /* anonymous unions are enabled by default */
265#elif defined(__IAR_SYSTEMS_ICC__)
266 #pragma language=extended
267#else
268 #error Not supported compiler type
269#endif
270
271/* ----------------------------------------------------------------------------
272 -- ADC Peripheral Access Layer
273 ---------------------------------------------------------------------------- */
274
275/*!
276 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
277 * @{
278 */
279
280/** ADC - Register Layout Typedef */
281typedef struct {
282 __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
283 __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
284 __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
285 __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
286 uint8_t RESERVED_0[8];
287 __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
288 __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
289 __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
290 __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
291 __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
292 __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
293 __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
294 __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
295 __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */
296 __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */
297} ADC_Type;
298
299/* ----------------------------------------------------------------------------
300 -- ADC Register Masks
301 ---------------------------------------------------------------------------- */
302
303/*!
304 * @addtogroup ADC_Register_Masks ADC Register Masks
305 * @{
306 */
307
308/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
309/*! @{ */
310#define ADC_CTRL_CLKDIV_MASK (0xFFU)
311#define ADC_CTRL_CLKDIV_SHIFT (0U)
312/*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce
313 * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically,
314 * software should program the smallest value in this field that yields this maximum clock rate or
315 * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may
316 * be desirable. This field is ignored in the asynchronous operating mode.
317 */
318#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
319#define ADC_CTRL_ASYNMODE_MASK (0x100U)
320#define ADC_CTRL_ASYNMODE_SHIFT (8U)
321/*! ASYNMODE - Select clock mode.
322 * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in
323 * the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to
324 * eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger.
325 * In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC
326 * input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger
327 * pulse.
328 * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
329 */
330#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
331#define ADC_CTRL_RESOL_MASK (0x600U)
332#define ADC_CTRL_RESOL_SHIFT (9U)
333/*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher
334 * conversion rates. A single conversion (including one conversion in a burst or sequence) requires the
335 * selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when
336 * the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable
337 * results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate
338 * for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system
339 * clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution
340 * 0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field.
341 * 0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field.
342 * 0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field.
343 * 0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field.
344 */
345#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
346#define ADC_CTRL_BYPASSCAL_MASK (0x800U)
347#define ADC_CTRL_BYPASSCAL_SHIFT (11U)
348/*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset
349 * error is not a concern in the application.
350 * 0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for
351 * offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may
352 * be warranted periodically - especially if operating conditions have changed.
353 * 0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC -
354 * particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set.
355 */
356#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
357#define ADC_CTRL_TSAMP_MASK (0x7000U)
358#define ADC_CTRL_TSAMP_SHIFT (12U)
359/*! TSAMP - Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion
360 * is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions
361 * and the output impedance of the analog source, longer sampling times may be required. See
362 * Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to
363 * seven, by which the sample period will be extended. The total conversion time will increase by
364 * the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A
365 * complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will
366 * be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will
367 * require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock
368 * cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be
369 * extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require
370 * 22 ADC clocks.
371 */
372#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
373/*! @} */
374
375/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
376/*! @{ */
377#define ADC_INSEL_SEL_MASK (0x3U)
378#define ADC_INSEL_SEL_SHIFT (0U)
379/*! SEL - Selects the input source for channel 0. All other values are reserved.
380 * 0b00..ADC0_IN0 function.
381 * 0b11..Internal temperature sensor.
382 */
383#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
384/*! @} */
385
386/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
387/*! @{ */
388#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU)
389#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U)
390/*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this
391 * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be
392 * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1
393 * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via
394 * software command, ADC conversions will be performed on each enabled channel, in sequence,
395 * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31)
396 * is LOW. It is allowed to change this field and set bit 31 in the same write.
397 */
398#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
399#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U)
400#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U)
401/*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion
402 * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order
403 * to avoid generating a spurious trigger, it is recommended writing to this field only when
404 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
405 */
406#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
407#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U)
408#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U)
409/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In
410 * order to avoid generating a spurious trigger, it is recommended writing to this field only when
411 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
412 * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
413 * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
414 */
415#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
416#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U)
417#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U)
418/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization
419 * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a
420 * conversion. There are slightly different criteria for whether or not this bit can be set
421 * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0):
422 * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already
423 * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer).
424 * Whether this bit is set or not, a trigger pulse must be maintained for at least one system
425 * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be
426 * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse
427 * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and
428 * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be
429 * maintained for one system clock period.
430 * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled.
431 * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled.
432 */
433#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
434#define ADC_SEQ_CTRL_START_MASK (0x4000000U)
435#define ADC_SEQ_CTRL_START_SHIFT (26U)
436/*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The
437 * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this
438 * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a
439 * conversion sequence. It will consequently always read back as a zero.
440 */
441#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
442#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U)
443#define ADC_SEQ_CTRL_BURST_SHIFT (27U)
444/*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled
445 * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions
446 * can be halted by clearing this bit. The sequence currently in progress will be completed before
447 * conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
448 */
449#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
450#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U)
451#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U)
452/*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a
453 * single conversion on the next channel in the sequence instead of the default response of
454 * launching an entire sequence of conversions. Once all of the channels comprising a sequence have
455 * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled
456 * channel. Interrupt generation will still occur either after each individual conversion or at
457 * the end of the entire sequence, depending on the state of the MODE bit.
458 */
459#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
460#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U)
461#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U)
462/*! LOWPRIO - Set priority for sequence A.
463 * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
464 * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence
465 * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion
466 * currently in progress will be terminated. The A sequence that was interrupted will automatically resume
467 * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the
468 * conversion sequence will resume from that point.
469 */
470#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
471#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U)
472#define ADC_SEQ_CTRL_MODE_SHIFT (30U)
473/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence
474 * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each
475 * conversion, or the individual channel result registers at the end of the entire sequence. Impacts
476 * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which
477 * overrun conditions contribute to an overrun interrupt as described below.
478 * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC
479 * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The
480 * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger
481 * if enabled.
482 * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A
483 * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in
484 * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun
485 * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
486 */
487#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
488#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U)
489#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U)
490/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be
491 * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state
492 * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered
493 * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care
494 * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE
495 * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be
496 * triggered immediately upon being enabled.
497 * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence
498 * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is
499 * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
500 * 0b1..Enabled. Sequence n is enabled.
501 */
502#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
503/*! @} */
504
505/* The count of ADC_SEQ_CTRL */
506#define ADC_SEQ_CTRL_COUNT (2U)
507
508/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
509/*! @{ */
510#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U)
511#define ADC_SEQ_GDAT_RESULT_SHIFT (4U)
512/*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion
513 * performed under conversion sequence associated with this register. The result is a binary
514 * fraction representing the voltage on the currently-selected input channel as it falls within the
515 * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less
516 * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input
517 * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this
518 * result has not yet been read.
519 */
520#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
521#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U)
522#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U)
523/*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or
524 * within the range established by the designated threshold comparison registers (THRn_LOW and
525 * THRn_HIGH).
526 */
527#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
528#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U)
529#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U)
530/*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a
531 * crossing of the threshold level established by the designated LOW threshold comparison register
532 * (THRn_LOW) and, if so, in what direction the crossing occurred.
533 */
534#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
535#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U)
536#define ADC_SEQ_GDAT_CHN_SHIFT (26U)
537/*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000
538 * identifies channel 0, 0001 channel 1, etc.).
539 */
540#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
541#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U)
542#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U)
543/*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a
544 * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along
545 * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun
546 * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set
547 * to '0' (and if the overrun interrupt is enabled).
548 */
549#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
550#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U)
551#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U)
552/*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded
553 * into the RESULT field. It is cleared whenever this register is read. This bit will cause a
554 * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that
555 * sequence is set to 0 (and if the interrupt is enabled).
556 */
557#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
558/*! @} */
559
560/* The count of ADC_SEQ_GDAT */
561#define ADC_SEQ_GDAT_COUNT (2U)
562
563/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
564/*! @{ */
565#define ADC_DAT_RESULT_MASK (0xFFF0U)
566#define ADC_DAT_RESULT_SHIFT (4U)
567/*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed
568 * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin,
569 * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on
570 * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that
571 * the voltage on the input was close to, equal to, or greater than that on VREFP.
572 */
573#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
574#define ADC_DAT_THCMPRANGE_MASK (0x30000U)
575#define ADC_DAT_THCMPRANGE_SHIFT (16U)
576/*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion
577 * was greater than or equal to the value programmed into the designated LOW threshold register
578 * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold
579 * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value
580 * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last
581 * completed conversion was greater than the value programmed into the designated HIGH threshold
582 * register (THRn_HIGH). 0x3 = Reserved.
583 */
584#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
585#define ADC_DAT_THCMPCROSS_MASK (0xC0000U)
586#define ADC_DAT_THCMPCROSS_SHIFT (18U)
587/*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The
588 * most recent completed conversion on this channel had the same relationship (above or below) to
589 * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the
590 * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing
591 * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the
592 * previous sample on this channel was above the threshold value established by the designated LOW
593 * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward
594 * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred
595 * - i.e. the previous sample on this channel was below the threshold value established by the
596 * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
597 */
598#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
599#define ADC_DAT_CHANNEL_MASK (0x3C000000U)
600#define ADC_DAT_CHANNEL_SHIFT (26U)
601/*! CHANNEL - This field is hard-coded to contain the channel number that this particular register
602 * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1
603 * register, etc)
604 */
605#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
606#define ADC_DAT_OVERRUN_MASK (0x40000000U)
607#define ADC_DAT_OVERRUN_SHIFT (30U)
608/*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and
609 * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit
610 * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when
611 * the data related to this channel is read from either of the global SEQn_GDAT registers. This
612 * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if
613 * the overrun interrupt is enabled. While it is allowed to include the same channels in both
614 * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the
615 * data registers associated with any of the channels that are shared between the two sequences. Any
616 * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
617 */
618#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
619#define ADC_DAT_DATAVALID_MASK (0x80000000U)
620#define ADC_DAT_DATAVALID_SHIFT (31U)
621/*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is
622 * cleared whenever this register is read or when the data related to this channel is read from
623 * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in
624 * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in
625 * the data registers associated with any of the channels that are shared between the two
626 * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
627 */
628#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
629/*! @} */
630
631/* The count of ADC_DAT */
632#define ADC_DAT_COUNT (12U)
633
634/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
635/*! @{ */
636#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U)
637#define ADC_THR0_LOW_THRLOW_SHIFT (4U)
638/*! THRLOW - Low threshold value against which ADC results will be compared
639 */
640#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
641/*! @} */
642
643/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
644/*! @{ */
645#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U)
646#define ADC_THR1_LOW_THRLOW_SHIFT (4U)
647/*! THRLOW - Low threshold value against which ADC results will be compared
648 */
649#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
650/*! @} */
651
652/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
653/*! @{ */
654#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U)
655#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U)
656/*! THRHIGH - High threshold value against which ADC results will be compared
657 */
658#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
659/*! @} */
660
661/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
662/*! @{ */
663#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U)
664#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U)
665/*! THRHIGH - High threshold value against which ADC results will be compared
666 */
667#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
668/*! @} */
669
670/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
671/*! @{ */
672#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U)
673#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U)
674/*! CH0_THRSEL - Threshold select for channel 0.
675 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
676 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
677 */
678#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
679#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U)
680#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U)
681/*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0.
682 */
683#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
684#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U)
685#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U)
686/*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0.
687 */
688#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
689#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U)
690#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U)
691/*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0.
692 */
693#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
694#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U)
695#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U)
696/*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0.
697 */
698#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
699#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U)
700#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U)
701/*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0.
702 */
703#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
704#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U)
705#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U)
706/*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0.
707 */
708#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
709#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U)
710#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U)
711/*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0.
712 */
713#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
714#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U)
715#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U)
716/*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0.
717 */
718#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
719#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U)
720#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U)
721/*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0.
722 */
723#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
724#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U)
725#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U)
726/*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0.
727 */
728#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
729#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U)
730#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U)
731/*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0.
732 */
733#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
734/*! @} */
735
736/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
737/*! @{ */
738#define ADC_INTEN_SEQA_INTEN_MASK (0x1U)
739#define ADC_INTEN_SEQA_INTEN_SHIFT (0U)
740/*! SEQA_INTEN - Sequence A interrupt enable.
741 * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled.
742 * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of
743 * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of
744 * conversions, depending on the MODE bit in the SEQA_CTRL register.
745 */
746#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
747#define ADC_INTEN_SEQB_INTEN_MASK (0x2U)
748#define ADC_INTEN_SEQB_INTEN_SHIFT (1U)
749/*! SEQB_INTEN - Sequence B interrupt enable.
750 * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled.
751 * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of
752 * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of
753 * conversions, depending on the MODE bit in the SEQB_CTRL register.
754 */
755#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
756#define ADC_INTEN_OVR_INTEN_MASK (0x4U)
757#define ADC_INTEN_OVR_INTEN_SHIFT (2U)
758/*! OVR_INTEN - Overrun interrupt enable.
759 * 0b0..Disabled. The overrun interrupt is disabled.
760 * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel
761 * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular
762 * sequence is 0, then an overrun in the global data register for that sequence will also cause this
763 * interrupt/DMA trigger to be asserted.
764 */
765#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
766#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U)
767#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U)
768/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0.
769 * 0b00..Disabled.
770 * 0b01..Outside threshold.
771 * 0b10..Crossing threshold.
772 * 0b11..Reserved
773 */
774#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
775#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U)
776#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U)
777/*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0.
778 */
779#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
780#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U)
781#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U)
782/*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0.
783 */
784#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
785#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U)
786#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U)
787/*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0.
788 */
789#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
790#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U)
791#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U)
792/*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0.
793 */
794#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
795#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U)
796#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U)
797/*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0.
798 */
799#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
800#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U)
801#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U)
802/*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0.
803 */
804#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
805#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U)
806#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U)
807/*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0.
808 */
809#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
810#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U)
811#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U)
812/*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0.
813 */
814#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
815#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U)
816#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U)
817/*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0.
818 */
819#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
820#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U)
821#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U)
822/*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0.
823 */
824#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
825#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U)
826#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U)
827/*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0.
828 */
829#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
830/*! @} */
831
832/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
833/*! @{ */
834#define ADC_FLAGS_THCMP0_MASK (0x1U)
835#define ADC_FLAGS_THCMP0_SHIFT (0U)
836/*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or
837 * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by
838 * writing a 1.
839 */
840#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
841#define ADC_FLAGS_THCMP1_MASK (0x2U)
842#define ADC_FLAGS_THCMP1_SHIFT (1U)
843/*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0.
844 */
845#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
846#define ADC_FLAGS_THCMP2_MASK (0x4U)
847#define ADC_FLAGS_THCMP2_SHIFT (2U)
848/*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0.
849 */
850#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
851#define ADC_FLAGS_THCMP3_MASK (0x8U)
852#define ADC_FLAGS_THCMP3_SHIFT (3U)
853/*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0.
854 */
855#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
856#define ADC_FLAGS_THCMP4_MASK (0x10U)
857#define ADC_FLAGS_THCMP4_SHIFT (4U)
858/*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0.
859 */
860#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
861#define ADC_FLAGS_THCMP5_MASK (0x20U)
862#define ADC_FLAGS_THCMP5_SHIFT (5U)
863/*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0.
864 */
865#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
866#define ADC_FLAGS_THCMP6_MASK (0x40U)
867#define ADC_FLAGS_THCMP6_SHIFT (6U)
868/*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0.
869 */
870#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
871#define ADC_FLAGS_THCMP7_MASK (0x80U)
872#define ADC_FLAGS_THCMP7_SHIFT (7U)
873/*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0.
874 */
875#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
876#define ADC_FLAGS_THCMP8_MASK (0x100U)
877#define ADC_FLAGS_THCMP8_SHIFT (8U)
878/*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0.
879 */
880#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
881#define ADC_FLAGS_THCMP9_MASK (0x200U)
882#define ADC_FLAGS_THCMP9_SHIFT (9U)
883/*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0.
884 */
885#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
886#define ADC_FLAGS_THCMP10_MASK (0x400U)
887#define ADC_FLAGS_THCMP10_SHIFT (10U)
888/*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0.
889 */
890#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
891#define ADC_FLAGS_THCMP11_MASK (0x800U)
892#define ADC_FLAGS_THCMP11_SHIFT (11U)
893/*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0.
894 */
895#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
896#define ADC_FLAGS_OVERRUN0_MASK (0x1000U)
897#define ADC_FLAGS_OVERRUN0_SHIFT (12U)
898/*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0
899 */
900#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
901#define ADC_FLAGS_OVERRUN1_MASK (0x2000U)
902#define ADC_FLAGS_OVERRUN1_SHIFT (13U)
903/*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1
904 */
905#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
906#define ADC_FLAGS_OVERRUN2_MASK (0x4000U)
907#define ADC_FLAGS_OVERRUN2_SHIFT (14U)
908/*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2
909 */
910#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
911#define ADC_FLAGS_OVERRUN3_MASK (0x8000U)
912#define ADC_FLAGS_OVERRUN3_SHIFT (15U)
913/*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3
914 */
915#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
916#define ADC_FLAGS_OVERRUN4_MASK (0x10000U)
917#define ADC_FLAGS_OVERRUN4_SHIFT (16U)
918/*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4
919 */
920#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
921#define ADC_FLAGS_OVERRUN5_MASK (0x20000U)
922#define ADC_FLAGS_OVERRUN5_SHIFT (17U)
923/*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5
924 */
925#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
926#define ADC_FLAGS_OVERRUN6_MASK (0x40000U)
927#define ADC_FLAGS_OVERRUN6_SHIFT (18U)
928/*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6
929 */
930#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
931#define ADC_FLAGS_OVERRUN7_MASK (0x80000U)
932#define ADC_FLAGS_OVERRUN7_SHIFT (19U)
933/*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7
934 */
935#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
936#define ADC_FLAGS_OVERRUN8_MASK (0x100000U)
937#define ADC_FLAGS_OVERRUN8_SHIFT (20U)
938/*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8
939 */
940#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
941#define ADC_FLAGS_OVERRUN9_MASK (0x200000U)
942#define ADC_FLAGS_OVERRUN9_SHIFT (21U)
943/*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9
944 */
945#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
946#define ADC_FLAGS_OVERRUN10_MASK (0x400000U)
947#define ADC_FLAGS_OVERRUN10_SHIFT (22U)
948/*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10
949 */
950#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
951#define ADC_FLAGS_OVERRUN11_MASK (0x800000U)
952#define ADC_FLAGS_OVERRUN11_SHIFT (23U)
953/*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11
954 */
955#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
956#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U)
957#define ADC_FLAGS_SEQA_OVR_SHIFT (24U)
958/*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register
959 */
960#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
961#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U)
962#define ADC_FLAGS_SEQB_OVR_SHIFT (25U)
963/*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register
964 */
965#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
966#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U)
967#define ADC_FLAGS_SEQA_INT_SHIFT (28U)
968/*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0,
969 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which
970 * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared
971 * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register
972 * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be
973 * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN
974 * register.
975 */
976#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
977#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U)
978#define ADC_FLAGS_SEQB_INT_SHIFT (29U)
979/*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0,
980 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which
981 * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared
982 * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register
983 * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be
984 * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN
985 * register.
986 */
987#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
988#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U)
989#define ADC_FLAGS_THCMP_INT_SHIFT (30U)
990/*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in
991 * the lower bits of this register are set to 1 (due to an enabled out-of-range or
992 * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be
993 * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared
994 * when all of the individual threshold flags are cleared via writing 1s to those bits.
995 */
996#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
997#define ADC_FLAGS_OVR_INT_MASK (0x80000000U)
998#define ADC_FLAGS_OVR_INT_SHIFT (31U)
999/*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data
1000 * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers
1001 * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this
1002 * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all
1003 * of the individual overrun bits have been cleared via reading the corresponding data registers.
1004 */
1005#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
1006/*! @} */
1007
1008/*! @name STARTUP - ADC Startup register. */
1009/*! @{ */
1010#define ADC_STARTUP_ADC_ENA_MASK (0x1U)
1011#define ADC_STARTUP_ADC_ENA_SHIFT (0U)
1012/*! ADC_ENA - ADC Enable bit. This bit can only be set to a 1 by software. It is cleared
1013 * automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds
1014 * after the ADC is powered up (typically by altering a system-level ADC power control bit).
1015 */
1016#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
1017#define ADC_STARTUP_ADC_INIT_MASK (0x2U)
1018#define ADC_STARTUP_ADC_INIT_SHIFT (1U)
1019/*! ADC_INIT - ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine
1020 * will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not
1021 * calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is
1022 * required if a calibration is not performed. It will also reload the stored calibration value from
1023 * a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the
1024 * ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or
1025 * an ADC dummy conversion cycle is required. It should not be set during the same write that
1026 * sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically
1027 * when the 'dummy' conversion cycle completes.
1028 */
1029#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
1030/*! @} */
1031
1032/*! @name CALIB - ADC Calibration register. */
1033/*! @{ */
1034#define ADC_CALIB_CALIB_MASK (0x1U)
1035#define ADC_CALIB_CALIB_SHIFT (0U)
1036/*! CALIB - Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can
1037 * only be set to a '1' by software. It is cleared automatically when the calibration cycle
1038 * completes.
1039 */
1040#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
1041#define ADC_CALIB_CALREQD_MASK (0x2U)
1042#define ADC_CALIB_CALREQD_SHIFT (1U)
1043/*! CALREQD - Calibration required. This read-only bit indicates if calibration is required when
1044 * enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was
1045 * powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to
1046 * determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP
1047 * register) to launch the ADC initialization process which includes a 'dummy' conversion cycle.
1048 * Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks
1049 * required for calibration.
1050 */
1051#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
1052#define ADC_CALIB_CALVALUE_MASK (0x1FCU)
1053#define ADC_CALIB_CALVALUE_SHIFT (2U)
1054/*! CALVALUE - Calibration Value. This read-only field displays the calibration value established
1055 * during last calibration cycle. This value is not typically of any use to the user.
1056 */
1057#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
1058/*! @} */
1059
1060
1061/*!
1062 * @}
1063 */ /* end of group ADC_Register_Masks */
1064
1065
1066/* ADC - Peripheral instance base addresses */
1067/** Peripheral ADC0 base address */
1068#define ADC0_BASE (0x400A0000u)
1069/** Peripheral ADC0 base pointer */
1070#define ADC0 ((ADC_Type *)ADC0_BASE)
1071/** Array initializer of ADC peripheral base addresses */
1072#define ADC_BASE_ADDRS { ADC0_BASE }
1073/** Array initializer of ADC peripheral base pointers */
1074#define ADC_BASE_PTRS { ADC0 }
1075/** Interrupt vectors for the ADC peripheral type */
1076#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
1077#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn }
1078
1079/*!
1080 * @}
1081 */ /* end of group ADC_Peripheral_Access_Layer */
1082
1083
1084/* ----------------------------------------------------------------------------
1085 -- ASYNC_SYSCON Peripheral Access Layer
1086 ---------------------------------------------------------------------------- */
1087
1088/*!
1089 * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
1090 * @{
1091 */
1092
1093/** ASYNC_SYSCON - Register Layout Typedef */
1094typedef struct {
1095 __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */
1096 __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
1097 __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
1098 uint8_t RESERVED_0[4];
1099 __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */
1100 __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
1101 __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
1102 uint8_t RESERVED_1[4];
1103 __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */
1104} ASYNC_SYSCON_Type;
1105
1106/* ----------------------------------------------------------------------------
1107 -- ASYNC_SYSCON Register Masks
1108 ---------------------------------------------------------------------------- */
1109
1110/*!
1111 * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
1112 * @{
1113 */
1114
1115/*! @name ASYNCPRESETCTRL - Async peripheral reset control */
1116/*! @{ */
1117#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
1118#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
1119/*! CTIMER3 - Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
1120 */
1121#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
1122#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
1123#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
1124/*! CTIMER4 - Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
1125 */
1126#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
1127/*! @} */
1128
1129/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
1130/*! @{ */
1131#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
1132#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
1133/*! ARST_SET - Writing ones to this register sets the corresponding bit or bits in the
1134 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1135 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1136 */
1137#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
1138/*! @} */
1139
1140/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
1141/*! @{ */
1142#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
1143#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
1144/*! ARST_CLR - Writing ones to this register clears the corresponding bit or bits in the
1145 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1146 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1147 */
1148#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
1149/*! @} */
1150
1151/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
1152/*! @{ */
1153#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
1154#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
1155/*! CTIMER3 - Controls the clock for CTIMER3. 0 = Disable; 1 = Enable.
1156 */
1157#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
1158#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
1159#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
1160/*! CTIMER4 - Controls the clock for CTIMER4. 0 = Disable; 1 = Enable.
1161 */
1162#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
1163/*! @} */
1164
1165/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
1166/*! @{ */
1167#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
1168#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
1169/*! ACLK_SET - Writing ones to this register sets the corresponding bit or bits in the
1170 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1171 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1172 */
1173#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
1174/*! @} */
1175
1176/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
1177/*! @{ */
1178#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
1179#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
1180/*! ACLK_CLR - Writing ones to this register clears the corresponding bit or bits in the
1181 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1182 * ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them.
1183 */
1184#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
1185/*! @} */
1186
1187/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
1188/*! @{ */
1189#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U)
1190#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U)
1191/*! SEL - Clock source for asynchronous clock source selector A
1192 * 0b00..Main clock (main_clk)
1193 * 0b01..FRO 12 MHz (fro_12m)
1194 * 0b10..Audio PLL clock.(AUDPLL_BYPASS)
1195 * 0b11..fc6 fclk (fc6_fclk)
1196 */
1197#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
1198/*! @} */
1199
1200
1201/*!
1202 * @}
1203 */ /* end of group ASYNC_SYSCON_Register_Masks */
1204
1205
1206/* ASYNC_SYSCON - Peripheral instance base addresses */
1207/** Peripheral ASYNC_SYSCON base address */
1208#define ASYNC_SYSCON_BASE (0x40040000u)
1209/** Peripheral ASYNC_SYSCON base pointer */
1210#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
1211/** Array initializer of ASYNC_SYSCON peripheral base addresses */
1212#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE }
1213/** Array initializer of ASYNC_SYSCON peripheral base pointers */
1214#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON }
1215
1216/*!
1217 * @}
1218 */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
1219
1220
1221/* ----------------------------------------------------------------------------
1222 -- CAN Peripheral Access Layer
1223 ---------------------------------------------------------------------------- */
1224
1225/*!
1226 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
1227 * @{
1228 */
1229
1230/** CAN - Register Layout Typedef */
1231typedef struct {
1232 uint8_t RESERVED_0[12];
1233 __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */
1234 __IO uint32_t TEST; /**< Test Register, offset: 0x10 */
1235 uint8_t RESERVED_1[4];
1236 __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */
1237 __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */
1238 __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */
1239 __I uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */
1240 __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */
1241 __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */
1242 uint8_t RESERVED_2[16];
1243 __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */
1244 __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */
1245 __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */
1246 uint8_t RESERVED_3[4];
1247 __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */
1248 __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */
1249 __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */
1250 __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */
1251 uint8_t RESERVED_4[32];
1252 __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */
1253 __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */
1254 __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */
1255 uint8_t RESERVED_5[4];
1256 __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */
1257 __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */
1258 __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */
1259 __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */
1260 __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */
1261 __I uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */
1262 __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */
1263 __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */
1264 __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */
1265 __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */
1266 __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */
1267 __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */
1268 __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */
1269 __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */
1270 __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */
1271 __I uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */
1272 __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */
1273 __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */
1274 __I uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */
1275 __I uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */
1276 __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */
1277 __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */
1278 uint8_t RESERVED_6[8];
1279 __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */
1280 __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */
1281 __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */
1282 uint8_t RESERVED_7[260];
1283 __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */
1284 uint8_t RESERVED_8[508];
1285 __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */
1286 uint8_t RESERVED_9[508];
1287 __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */
1288} CAN_Type;
1289
1290/* ----------------------------------------------------------------------------
1291 -- CAN Register Masks
1292 ---------------------------------------------------------------------------- */
1293
1294/*!
1295 * @addtogroup CAN_Register_Masks CAN Register Masks
1296 * @{
1297 */
1298
1299/*! @name DBTP - Data Bit Timing Prescaler Register */
1300/*! @{ */
1301#define CAN_DBTP_DSJW_MASK (0xFU)
1302#define CAN_DBTP_DSJW_SHIFT (0U)
1303/*! DSJW - Data (re)synchronization jump width.
1304 */
1305#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK)
1306#define CAN_DBTP_DTSEG2_MASK (0xF0U)
1307#define CAN_DBTP_DTSEG2_SHIFT (4U)
1308/*! DTSEG2 - Data time segment after sample point.
1309 */
1310#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK)
1311#define CAN_DBTP_DTSEG1_MASK (0x1F00U)
1312#define CAN_DBTP_DTSEG1_SHIFT (8U)
1313/*! DTSEG1 - Data time segment before sample point.
1314 */
1315#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK)
1316#define CAN_DBTP_DBRP_MASK (0x1F0000U)
1317#define CAN_DBTP_DBRP_SHIFT (16U)
1318/*! DBRP - Data bit rate prescaler.
1319 */
1320#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK)
1321#define CAN_DBTP_TDC_MASK (0x800000U)
1322#define CAN_DBTP_TDC_SHIFT (23U)
1323/*! TDC - Transmitter delay compensation.
1324 */
1325#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK)
1326/*! @} */
1327
1328/*! @name TEST - Test Register */
1329/*! @{ */
1330#define CAN_TEST_LBCK_MASK (0x10U)
1331#define CAN_TEST_LBCK_SHIFT (4U)
1332/*! LBCK - Loop back mode.
1333 */
1334#define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)
1335#define CAN_TEST_TX_MASK (0x60U)
1336#define CAN_TEST_TX_SHIFT (5U)
1337/*! TX - Control of transmit pin.
1338 */
1339#define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)
1340#define CAN_TEST_RX_MASK (0x80U)
1341#define CAN_TEST_RX_SHIFT (7U)
1342/*! RX - Monitors the actual value of the CAN_RXD.
1343 */
1344#define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)
1345/*! @} */
1346
1347/*! @name CCCR - CC Control Register */
1348/*! @{ */
1349#define CAN_CCCR_INIT_MASK (0x1U)
1350#define CAN_CCCR_INIT_SHIFT (0U)
1351/*! INIT - Initialization.
1352 */
1353#define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)
1354#define CAN_CCCR_CCE_MASK (0x2U)
1355#define CAN_CCCR_CCE_SHIFT (1U)
1356/*! CCE - Configuration change enable.
1357 */
1358#define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)
1359#define CAN_CCCR_ASM_MASK (0x4U)
1360#define CAN_CCCR_ASM_SHIFT (2U)
1361/*! ASM - Restricted operational mode.
1362 */
1363#define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)
1364#define CAN_CCCR_CSA_MASK (0x8U)
1365#define CAN_CCCR_CSA_SHIFT (3U)
1366/*! CSA - Clock Stop Acknowledge.
1367 */
1368#define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)
1369#define CAN_CCCR_CSR_MASK (0x10U)
1370#define CAN_CCCR_CSR_SHIFT (4U)
1371/*! CSR - Clock Stop Request.
1372 */
1373#define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)
1374#define CAN_CCCR_MON_MASK (0x20U)
1375#define CAN_CCCR_MON_SHIFT (5U)
1376/*! MON - Bus monitoring mode.
1377 */
1378#define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)
1379#define CAN_CCCR_DAR_MASK (0x40U)
1380#define CAN_CCCR_DAR_SHIFT (6U)
1381/*! DAR - Disable automatic retransmission.
1382 */
1383#define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)
1384#define CAN_CCCR_TEST_MASK (0x80U)
1385#define CAN_CCCR_TEST_SHIFT (7U)
1386/*! TEST - Test mode enable.
1387 */
1388#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
1389#define CAN_CCCR_FDOE_MASK (0x100U)
1390#define CAN_CCCR_FDOE_SHIFT (8U)
1391/*! FDOE - CAN FD operation enable.
1392 */
1393#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK)
1394#define CAN_CCCR_BRSE_MASK (0x200U)
1395#define CAN_CCCR_BRSE_SHIFT (9U)
1396/*! BRSE - When CAN FD operation is disabled, this bit is not evaluated.
1397 */
1398#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK)
1399#define CAN_CCCR_PXHD_MASK (0x1000U)
1400#define CAN_CCCR_PXHD_SHIFT (12U)
1401/*! PXHD - Protocol exception handling disable.
1402 */
1403#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
1404#define CAN_CCCR_EFBI_MASK (0x2000U)
1405#define CAN_CCCR_EFBI_SHIFT (13U)
1406/*! EFBI - Edge filtering during bus integration.
1407 */
1408#define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)
1409#define CAN_CCCR_TXP_MASK (0x4000U)
1410#define CAN_CCCR_TXP_SHIFT (14U)
1411/*! TXP - Transmit pause.
1412 */
1413#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
1414#define CAN_CCCR_NISO_MASK (0x8000U)
1415#define CAN_CCCR_NISO_SHIFT (15U)
1416/*! NISO - Non ISO operation.
1417 */
1418#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK)
1419/*! @} */
1420
1421/*! @name NBTP - Nominal Bit Timing and Prescaler Register */
1422/*! @{ */
1423#define CAN_NBTP_NTSEG2_MASK (0x7FU)
1424#define CAN_NBTP_NTSEG2_SHIFT (0U)
1425/*! NTSEG2 - Nominal time segment after sample point.
1426 */
1427#define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)
1428#define CAN_NBTP_NTSEG1_MASK (0xFF00U)
1429#define CAN_NBTP_NTSEG1_SHIFT (8U)
1430/*! NTSEG1 - Nominal time segment before sample point.
1431 */
1432#define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)
1433#define CAN_NBTP_NBRP_MASK (0x1FF0000U)
1434#define CAN_NBTP_NBRP_SHIFT (16U)
1435/*! NBRP - Nominal bit rate prescaler.
1436 */
1437#define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)
1438#define CAN_NBTP_NSJW_MASK (0xFE000000U)
1439#define CAN_NBTP_NSJW_SHIFT (25U)
1440/*! NSJW - Nominal (re)synchronization jump width.
1441 */
1442#define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)
1443/*! @} */
1444
1445/*! @name TSCC - Timestamp Counter Configuration */
1446/*! @{ */
1447#define CAN_TSCC_TSS_MASK (0x3U)
1448#define CAN_TSCC_TSS_SHIFT (0U)
1449/*! TSS - Timestamp select.
1450 */
1451#define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)
1452#define CAN_TSCC_TCP_MASK (0xF0000U)
1453#define CAN_TSCC_TCP_SHIFT (16U)
1454/*! TCP - Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times.
1455 */
1456#define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)
1457/*! @} */
1458
1459/*! @name TSCV - Timestamp Counter Value */
1460/*! @{ */
1461#define CAN_TSCV_TSC_MASK (0xFFFFU)
1462#define CAN_TSCV_TSC_SHIFT (0U)
1463/*! TSC - Timestamp counter.
1464 */
1465#define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)
1466/*! @} */
1467
1468/*! @name TOCC - Timeout Counter Configuration */
1469/*! @{ */
1470#define CAN_TOCC_ETOC_MASK (0x1U)
1471#define CAN_TOCC_ETOC_SHIFT (0U)
1472/*! ETOC - Enable timeout counter.
1473 */
1474#define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)
1475#define CAN_TOCC_TOS_MASK (0x6U)
1476#define CAN_TOCC_TOS_SHIFT (1U)
1477/*! TOS - Timeout select.
1478 */
1479#define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)
1480#define CAN_TOCC_TOP_MASK (0xFFFF0000U)
1481#define CAN_TOCC_TOP_SHIFT (16U)
1482/*! TOP - Timeout period.
1483 */
1484#define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)
1485/*! @} */
1486
1487/*! @name TOCV - Timeout Counter Value */
1488/*! @{ */
1489#define CAN_TOCV_TOC_MASK (0xFFFFU)
1490#define CAN_TOCV_TOC_SHIFT (0U)
1491/*! TOC - Timeout counter.
1492 */
1493#define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)
1494/*! @} */
1495
1496/*! @name ECR - Error Counter Register */
1497/*! @{ */
1498#define CAN_ECR_TEC_MASK (0xFFU)
1499#define CAN_ECR_TEC_SHIFT (0U)
1500/*! TEC - Transmit error counter.
1501 */
1502#define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)
1503#define CAN_ECR_REC_MASK (0x7F00U)
1504#define CAN_ECR_REC_SHIFT (8U)
1505/*! REC - Receive error counter.
1506 */
1507#define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)
1508#define CAN_ECR_RP_MASK (0x8000U)
1509#define CAN_ECR_RP_SHIFT (15U)
1510/*! RP - Receive error passive.
1511 */
1512#define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)
1513#define CAN_ECR_CEL_MASK (0xFF0000U)
1514#define CAN_ECR_CEL_SHIFT (16U)
1515/*! CEL - CAN error logging.
1516 */
1517#define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)
1518/*! @} */
1519
1520/*! @name PSR - Protocol Status Register */
1521/*! @{ */
1522#define CAN_PSR_LEC_MASK (0x7U)
1523#define CAN_PSR_LEC_SHIFT (0U)
1524/*! LEC - Last error code.
1525 */
1526#define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)
1527#define CAN_PSR_ACT_MASK (0x18U)
1528#define CAN_PSR_ACT_SHIFT (3U)
1529/*! ACT - Activity.
1530 */
1531#define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)
1532#define CAN_PSR_EP_MASK (0x20U)
1533#define CAN_PSR_EP_SHIFT (5U)
1534/*! EP - Error Passive.
1535 */
1536#define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)
1537#define CAN_PSR_EW_MASK (0x40U)
1538#define CAN_PSR_EW_SHIFT (6U)
1539/*! EW - Warning status.
1540 */
1541#define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)
1542#define CAN_PSR_BO_MASK (0x80U)
1543#define CAN_PSR_BO_SHIFT (7U)
1544/*! BO - Bus Off Status.
1545 */
1546#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
1547#define CAN_PSR_DLEC_MASK (0x700U)
1548#define CAN_PSR_DLEC_SHIFT (8U)
1549/*! DLEC - Data phase last error code.
1550 */
1551#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK)
1552#define CAN_PSR_RESI_MASK (0x800U)
1553#define CAN_PSR_RESI_SHIFT (11U)
1554/*! RESI - ESI flag of the last received CAN FD message.
1555 */
1556#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK)
1557#define CAN_PSR_RBRS_MASK (0x1000U)
1558#define CAN_PSR_RBRS_SHIFT (12U)
1559/*! RBRS - BRS flag of last received CAN FD message.
1560 */
1561#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK)
1562#define CAN_PSR_RFDF_MASK (0x2000U)
1563#define CAN_PSR_RFDF_SHIFT (13U)
1564/*! RFDF - Received a CAN FD message.
1565 */
1566#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK)
1567#define CAN_PSR_PXE_MASK (0x4000U)
1568#define CAN_PSR_PXE_SHIFT (14U)
1569/*! PXE - Protocol exception event.
1570 */
1571#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
1572#define CAN_PSR_TDCV_MASK (0x7F0000U)
1573#define CAN_PSR_TDCV_SHIFT (16U)
1574/*! TDCV - Transmitter delay compensation value.
1575 */
1576#define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)
1577/*! @} */
1578
1579/*! @name TDCR - Transmitter Delay Compensator Register */
1580/*! @{ */
1581#define CAN_TDCR_TDCF_MASK (0x7FU)
1582#define CAN_TDCR_TDCF_SHIFT (0U)
1583/*! TDCF - Transmitter delay compensation filter window length.
1584 */
1585#define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)
1586#define CAN_TDCR_TDCO_MASK (0x7F00U)
1587#define CAN_TDCR_TDCO_SHIFT (8U)
1588/*! TDCO - Transmitter delay compensation offset.
1589 */
1590#define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)
1591/*! @} */
1592
1593/*! @name IR - Interrupt Register */
1594/*! @{ */
1595#define CAN_IR_RF0N_MASK (0x1U)
1596#define CAN_IR_RF0N_SHIFT (0U)
1597/*! RF0N - Rx FIFO 0 new message.
1598 */
1599#define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)
1600#define CAN_IR_RF0W_MASK (0x2U)
1601#define CAN_IR_RF0W_SHIFT (1U)
1602/*! RF0W - Rx FIFO 0 watermark reached.
1603 */
1604#define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)
1605#define CAN_IR_RF0F_MASK (0x4U)
1606#define CAN_IR_RF0F_SHIFT (2U)
1607/*! RF0F - Rx FIFO 0 full.
1608 */
1609#define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)
1610#define CAN_IR_RF0L_MASK (0x8U)
1611#define CAN_IR_RF0L_SHIFT (3U)
1612/*! RF0L - Rx FIFO 0 message lost.
1613 */
1614#define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)
1615#define CAN_IR_RF1N_MASK (0x10U)
1616#define CAN_IR_RF1N_SHIFT (4U)
1617/*! RF1N - Rx FIFO 1 new message.
1618 */
1619#define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)
1620#define CAN_IR_RF1W_MASK (0x20U)
1621#define CAN_IR_RF1W_SHIFT (5U)
1622/*! RF1W - Rx FIFO 1 watermark reached.
1623 */
1624#define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)
1625#define CAN_IR_RF1F_MASK (0x40U)
1626#define CAN_IR_RF1F_SHIFT (6U)
1627/*! RF1F - Rx FIFO 1 full.
1628 */
1629#define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)
1630#define CAN_IR_RF1L_MASK (0x80U)
1631#define CAN_IR_RF1L_SHIFT (7U)
1632/*! RF1L - Rx FIFO 1 message lost.
1633 */
1634#define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)
1635#define CAN_IR_HPM_MASK (0x100U)
1636#define CAN_IR_HPM_SHIFT (8U)
1637/*! HPM - High priority message.
1638 */
1639#define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)
1640#define CAN_IR_TC_MASK (0x200U)
1641#define CAN_IR_TC_SHIFT (9U)
1642/*! TC - Transmission completed.
1643 */
1644#define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)
1645#define CAN_IR_TCF_MASK (0x400U)
1646#define CAN_IR_TCF_SHIFT (10U)
1647/*! TCF - Transmission cancellation finished.
1648 */
1649#define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)
1650#define CAN_IR_TFE_MASK (0x800U)
1651#define CAN_IR_TFE_SHIFT (11U)
1652/*! TFE - Tx FIFO empty.
1653 */
1654#define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)
1655#define CAN_IR_TEFN_MASK (0x1000U)
1656#define CAN_IR_TEFN_SHIFT (12U)
1657/*! TEFN - Tx event FIFO new entry.
1658 */
1659#define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)
1660#define CAN_IR_TEFW_MASK (0x2000U)
1661#define CAN_IR_TEFW_SHIFT (13U)
1662/*! TEFW - Tx event FIFO watermark reached.
1663 */
1664#define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)
1665#define CAN_IR_TEFF_MASK (0x4000U)
1666#define CAN_IR_TEFF_SHIFT (14U)
1667/*! TEFF - Tx event FIFO full.
1668 */
1669#define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)
1670#define CAN_IR_TEFL_MASK (0x8000U)
1671#define CAN_IR_TEFL_SHIFT (15U)
1672/*! TEFL - Tx event FIFO element lost.
1673 */
1674#define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)
1675#define CAN_IR_TSW_MASK (0x10000U)
1676#define CAN_IR_TSW_SHIFT (16U)
1677/*! TSW - Timestamp wraparound.
1678 */
1679#define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)
1680#define CAN_IR_MRAF_MASK (0x20000U)
1681#define CAN_IR_MRAF_SHIFT (17U)
1682/*! MRAF - Message RAM access failure.
1683 */
1684#define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)
1685#define CAN_IR_TOO_MASK (0x40000U)
1686#define CAN_IR_TOO_SHIFT (18U)
1687/*! TOO - Timeout occurred.
1688 */
1689#define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)
1690#define CAN_IR_DRX_MASK (0x80000U)
1691#define CAN_IR_DRX_SHIFT (19U)
1692/*! DRX - Message stored in dedicated Rx buffer.
1693 */
1694#define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)
1695#define CAN_IR_BEC_MASK (0x100000U)
1696#define CAN_IR_BEC_SHIFT (20U)
1697/*! BEC - Bit error corrected.
1698 */
1699#define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)
1700#define CAN_IR_BEU_MASK (0x200000U)
1701#define CAN_IR_BEU_SHIFT (21U)
1702/*! BEU - Bit error uncorrected.
1703 */
1704#define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)
1705#define CAN_IR_ELO_MASK (0x400000U)
1706#define CAN_IR_ELO_SHIFT (22U)
1707/*! ELO - Error logging overflow.
1708 */
1709#define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK)
1710#define CAN_IR_EP_MASK (0x800000U)
1711#define CAN_IR_EP_SHIFT (23U)
1712/*! EP - Error passive.
1713 */
1714#define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK)
1715#define CAN_IR_EW_MASK (0x1000000U)
1716#define CAN_IR_EW_SHIFT (24U)
1717/*! EW - Warning status.
1718 */
1719#define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK)
1720#define CAN_IR_BO_MASK (0x2000000U)
1721#define CAN_IR_BO_SHIFT (25U)
1722/*! BO - Bus_Off Status.
1723 */
1724#define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK)
1725#define CAN_IR_WDI_MASK (0x4000000U)
1726#define CAN_IR_WDI_SHIFT (26U)
1727/*! WDI - Watchdog interrupt.
1728 */
1729#define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK)
1730#define CAN_IR_PEA_MASK (0x8000000U)
1731#define CAN_IR_PEA_SHIFT (27U)
1732/*! PEA - Protocol error in arbitration phase.
1733 */
1734#define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK)
1735#define CAN_IR_PED_MASK (0x10000000U)
1736#define CAN_IR_PED_SHIFT (28U)
1737/*! PED - Protocol error in data phase.
1738 */
1739#define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK)
1740#define CAN_IR_ARA_MASK (0x20000000U)
1741#define CAN_IR_ARA_SHIFT (29U)
1742/*! ARA - Access to reserved address.
1743 */
1744#define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK)
1745/*! @} */
1746
1747/*! @name IE - Interrupt Enable */
1748/*! @{ */
1749#define CAN_IE_RF0NE_MASK (0x1U)
1750#define CAN_IE_RF0NE_SHIFT (0U)
1751/*! RF0NE - Rx FIFO 0 new message interrupt enable.
1752 */
1753#define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK)
1754#define CAN_IE_RF0WE_MASK (0x2U)
1755#define CAN_IE_RF0WE_SHIFT (1U)
1756/*! RF0WE - Rx FIFO 0 watermark reached interrupt enable.
1757 */
1758#define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK)
1759#define CAN_IE_RF0FE_MASK (0x4U)
1760#define CAN_IE_RF0FE_SHIFT (2U)
1761/*! RF0FE - Rx FIFO 0 full interrupt enable.
1762 */
1763#define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK)
1764#define CAN_IE_RF0LE_MASK (0x8U)
1765#define CAN_IE_RF0LE_SHIFT (3U)
1766/*! RF0LE - Rx FIFO 0 message lost interrupt enable.
1767 */
1768#define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK)
1769#define CAN_IE_RF1NE_MASK (0x10U)
1770#define CAN_IE_RF1NE_SHIFT (4U)
1771/*! RF1NE - Rx FIFO 1 new message interrupt enable.
1772 */
1773#define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK)
1774#define CAN_IE_RF1WE_MASK (0x20U)
1775#define CAN_IE_RF1WE_SHIFT (5U)
1776/*! RF1WE - Rx FIFO 1 watermark reached interrupt enable.
1777 */
1778#define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK)
1779#define CAN_IE_RF1FE_MASK (0x40U)
1780#define CAN_IE_RF1FE_SHIFT (6U)
1781/*! RF1FE - Rx FIFO 1 full interrupt enable.
1782 */
1783#define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK)
1784#define CAN_IE_RF1LE_MASK (0x80U)
1785#define CAN_IE_RF1LE_SHIFT (7U)
1786/*! RF1LE - Rx FIFO 1 message lost interrupt enable.
1787 */
1788#define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK)
1789#define CAN_IE_HPME_MASK (0x100U)
1790#define CAN_IE_HPME_SHIFT (8U)
1791/*! HPME - High priority message interrupt enable.
1792 */
1793#define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK)
1794#define CAN_IE_TCE_MASK (0x200U)
1795#define CAN_IE_TCE_SHIFT (9U)
1796/*! TCE - Transmission completed interrupt enable.
1797 */
1798#define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK)
1799#define CAN_IE_TCFE_MASK (0x400U)
1800#define CAN_IE_TCFE_SHIFT (10U)
1801/*! TCFE - Transmission cancellation finished interrupt enable.
1802 */
1803#define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK)
1804#define CAN_IE_TFEE_MASK (0x800U)
1805#define CAN_IE_TFEE_SHIFT (11U)
1806/*! TFEE - Tx FIFO empty interrupt enable.
1807 */
1808#define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK)
1809#define CAN_IE_TEFNE_MASK (0x1000U)
1810#define CAN_IE_TEFNE_SHIFT (12U)
1811/*! TEFNE - Tx event FIFO new entry interrupt enable.
1812 */
1813#define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK)
1814#define CAN_IE_TEFWE_MASK (0x2000U)
1815#define CAN_IE_TEFWE_SHIFT (13U)
1816/*! TEFWE - Tx event FIFO watermark reached interrupt enable.
1817 */
1818#define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK)
1819#define CAN_IE_TEFFE_MASK (0x4000U)
1820#define CAN_IE_TEFFE_SHIFT (14U)
1821/*! TEFFE - Tx event FIFO full interrupt enable.
1822 */
1823#define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK)
1824#define CAN_IE_TEFLE_MASK (0x8000U)
1825#define CAN_IE_TEFLE_SHIFT (15U)
1826/*! TEFLE - Tx event FIFO element lost interrupt enable.
1827 */
1828#define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK)
1829#define CAN_IE_TSWE_MASK (0x10000U)
1830#define CAN_IE_TSWE_SHIFT (16U)
1831/*! TSWE - Timestamp wraparound interrupt enable.
1832 */
1833#define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK)
1834#define CAN_IE_MRAFE_MASK (0x20000U)
1835#define CAN_IE_MRAFE_SHIFT (17U)
1836/*! MRAFE - Message RAM access failure interrupt enable.
1837 */
1838#define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK)
1839#define CAN_IE_TOOE_MASK (0x40000U)
1840#define CAN_IE_TOOE_SHIFT (18U)
1841/*! TOOE - Timeout occurred interrupt enable.
1842 */
1843#define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK)
1844#define CAN_IE_DRXE_MASK (0x80000U)
1845#define CAN_IE_DRXE_SHIFT (19U)
1846/*! DRXE - Message stored in dedicated Rx buffer interrupt enable.
1847 */
1848#define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK)
1849#define CAN_IE_BECE_MASK (0x100000U)
1850#define CAN_IE_BECE_SHIFT (20U)
1851/*! BECE - Bit error corrected interrupt enable.
1852 */
1853#define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK)
1854#define CAN_IE_BEUE_MASK (0x200000U)
1855#define CAN_IE_BEUE_SHIFT (21U)
1856/*! BEUE - Bit error uncorrected interrupt enable.
1857 */
1858#define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK)
1859#define CAN_IE_ELOE_MASK (0x400000U)
1860#define CAN_IE_ELOE_SHIFT (22U)
1861/*! ELOE - Error logging overflow interrupt enable.
1862 */
1863#define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK)
1864#define CAN_IE_EPE_MASK (0x800000U)
1865#define CAN_IE_EPE_SHIFT (23U)
1866/*! EPE - Error passive interrupt enable.
1867 */
1868#define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK)
1869#define CAN_IE_EWE_MASK (0x1000000U)
1870#define CAN_IE_EWE_SHIFT (24U)
1871/*! EWE - Warning status interrupt enable.
1872 */
1873#define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK)
1874#define CAN_IE_BOE_MASK (0x2000000U)
1875#define CAN_IE_BOE_SHIFT (25U)
1876/*! BOE - Bus_Off Status interrupt enable.
1877 */
1878#define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK)
1879#define CAN_IE_WDIE_MASK (0x4000000U)
1880#define CAN_IE_WDIE_SHIFT (26U)
1881/*! WDIE - Watchdog interrupt enable.
1882 */
1883#define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK)
1884#define CAN_IE_PEAE_MASK (0x8000000U)
1885#define CAN_IE_PEAE_SHIFT (27U)
1886/*! PEAE - Protocol error in arbitration phase interrupt enable.
1887 */
1888#define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK)
1889#define CAN_IE_PEDE_MASK (0x10000000U)
1890#define CAN_IE_PEDE_SHIFT (28U)
1891/*! PEDE - Protocol error in data phase interrupt enable.
1892 */
1893#define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK)
1894#define CAN_IE_ARAE_MASK (0x20000000U)
1895#define CAN_IE_ARAE_SHIFT (29U)
1896/*! ARAE - Access to reserved address interrupt enable.
1897 */
1898#define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK)
1899/*! @} */
1900
1901/*! @name ILS - Interrupt Line Select */
1902/*! @{ */
1903#define CAN_ILS_RF0NL_MASK (0x1U)
1904#define CAN_ILS_RF0NL_SHIFT (0U)
1905/*! RF0NL - Rx FIFO 0 new message interrupt line.
1906 */
1907#define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK)
1908#define CAN_ILS_RF0WL_MASK (0x2U)
1909#define CAN_ILS_RF0WL_SHIFT (1U)
1910/*! RF0WL - Rx FIFO 0 watermark reached interrupt line.
1911 */
1912#define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK)
1913#define CAN_ILS_RF0FL_MASK (0x4U)
1914#define CAN_ILS_RF0FL_SHIFT (2U)
1915/*! RF0FL - Rx FIFO 0 full interrupt line.
1916 */
1917#define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK)
1918#define CAN_ILS_RF0LL_MASK (0x8U)
1919#define CAN_ILS_RF0LL_SHIFT (3U)
1920/*! RF0LL - Rx FIFO 0 message lost interrupt line.
1921 */
1922#define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK)
1923#define CAN_ILS_RF1NL_MASK (0x10U)
1924#define CAN_ILS_RF1NL_SHIFT (4U)
1925/*! RF1NL - Rx FIFO 1 new message interrupt line.
1926 */
1927#define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK)
1928#define CAN_ILS_RF1WL_MASK (0x20U)
1929#define CAN_ILS_RF1WL_SHIFT (5U)
1930/*! RF1WL - Rx FIFO 1 watermark reached interrupt line.
1931 */
1932#define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK)
1933#define CAN_ILS_RF1FL_MASK (0x40U)
1934#define CAN_ILS_RF1FL_SHIFT (6U)
1935/*! RF1FL - Rx FIFO 1 full interrupt line.
1936 */
1937#define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK)
1938#define CAN_ILS_RF1LL_MASK (0x80U)
1939#define CAN_ILS_RF1LL_SHIFT (7U)
1940/*! RF1LL - Rx FIFO 1 message lost interrupt line.
1941 */
1942#define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK)
1943#define CAN_ILS_HPML_MASK (0x100U)
1944#define CAN_ILS_HPML_SHIFT (8U)
1945/*! HPML - High priority message interrupt line.
1946 */
1947#define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK)
1948#define CAN_ILS_TCL_MASK (0x200U)
1949#define CAN_ILS_TCL_SHIFT (9U)
1950/*! TCL - Transmission completed interrupt line.
1951 */
1952#define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK)
1953#define CAN_ILS_TCFL_MASK (0x400U)
1954#define CAN_ILS_TCFL_SHIFT (10U)
1955/*! TCFL - Transmission cancellation finished interrupt line.
1956 */
1957#define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK)
1958#define CAN_ILS_TFEL_MASK (0x800U)
1959#define CAN_ILS_TFEL_SHIFT (11U)
1960/*! TFEL - Tx FIFO empty interrupt line.
1961 */
1962#define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK)
1963#define CAN_ILS_TEFNL_MASK (0x1000U)
1964#define CAN_ILS_TEFNL_SHIFT (12U)
1965/*! TEFNL - Tx event FIFO new entry interrupt line.
1966 */
1967#define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK)
1968#define CAN_ILS_TEFWL_MASK (0x2000U)
1969#define CAN_ILS_TEFWL_SHIFT (13U)
1970/*! TEFWL - Tx event FIFO watermark reached interrupt line.
1971 */
1972#define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK)
1973#define CAN_ILS_TEFFL_MASK (0x4000U)
1974#define CAN_ILS_TEFFL_SHIFT (14U)
1975/*! TEFFL - Tx event FIFO full interrupt line.
1976 */
1977#define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK)
1978#define CAN_ILS_TEFLL_MASK (0x8000U)
1979#define CAN_ILS_TEFLL_SHIFT (15U)
1980/*! TEFLL - Tx event FIFO element lost interrupt line.
1981 */
1982#define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK)
1983#define CAN_ILS_TSWL_MASK (0x10000U)
1984#define CAN_ILS_TSWL_SHIFT (16U)
1985/*! TSWL - Timestamp wraparound interrupt line.
1986 */
1987#define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK)
1988#define CAN_ILS_MRAFL_MASK (0x20000U)
1989#define CAN_ILS_MRAFL_SHIFT (17U)
1990/*! MRAFL - Message RAM access failure interrupt line.
1991 */
1992#define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK)
1993#define CAN_ILS_TOOL_MASK (0x40000U)
1994#define CAN_ILS_TOOL_SHIFT (18U)
1995/*! TOOL - Timeout occurred interrupt line.
1996 */
1997#define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK)
1998#define CAN_ILS_DRXL_MASK (0x80000U)
1999#define CAN_ILS_DRXL_SHIFT (19U)
2000/*! DRXL - Message stored in dedicated Rx buffer interrupt line.
2001 */
2002#define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK)
2003#define CAN_ILS_BECL_MASK (0x100000U)
2004#define CAN_ILS_BECL_SHIFT (20U)
2005/*! BECL - Bit error corrected interrupt line.
2006 */
2007#define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK)
2008#define CAN_ILS_BEUL_MASK (0x200000U)
2009#define CAN_ILS_BEUL_SHIFT (21U)
2010/*! BEUL - Bit error uncorrected interrupt line.
2011 */
2012#define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK)
2013#define CAN_ILS_ELOL_MASK (0x400000U)
2014#define CAN_ILS_ELOL_SHIFT (22U)
2015/*! ELOL - Error logging overflow interrupt line.
2016 */
2017#define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK)
2018#define CAN_ILS_EPL_MASK (0x800000U)
2019#define CAN_ILS_EPL_SHIFT (23U)
2020/*! EPL - Error passive interrupt line.
2021 */
2022#define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK)
2023#define CAN_ILS_EWL_MASK (0x1000000U)
2024#define CAN_ILS_EWL_SHIFT (24U)
2025/*! EWL - Warning status interrupt line.
2026 */
2027#define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK)
2028#define CAN_ILS_BOL_MASK (0x2000000U)
2029#define CAN_ILS_BOL_SHIFT (25U)
2030/*! BOL - Bus_Off Status interrupt line.
2031 */
2032#define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK)
2033#define CAN_ILS_WDIL_MASK (0x4000000U)
2034#define CAN_ILS_WDIL_SHIFT (26U)
2035/*! WDIL - Watchdog interrupt line.
2036 */
2037#define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK)
2038#define CAN_ILS_PEAL_MASK (0x8000000U)
2039#define CAN_ILS_PEAL_SHIFT (27U)
2040/*! PEAL - Protocol error in arbitration phase interrupt line.
2041 */
2042#define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK)
2043#define CAN_ILS_PEDL_MASK (0x10000000U)
2044#define CAN_ILS_PEDL_SHIFT (28U)
2045/*! PEDL - Protocol error in data phase interrupt line.
2046 */
2047#define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK)
2048#define CAN_ILS_ARAL_MASK (0x20000000U)
2049#define CAN_ILS_ARAL_SHIFT (29U)
2050/*! ARAL - Access to reserved address interrupt line.
2051 */
2052#define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK)
2053/*! @} */
2054
2055/*! @name ILE - Interrupt Line Enable */
2056/*! @{ */
2057#define CAN_ILE_EINT0_MASK (0x1U)
2058#define CAN_ILE_EINT0_SHIFT (0U)
2059/*! EINT0 - Enable interrupt line 0.
2060 */
2061#define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK)
2062#define CAN_ILE_EINT1_MASK (0x2U)
2063#define CAN_ILE_EINT1_SHIFT (1U)
2064/*! EINT1 - Enable interrupt line 1.
2065 */
2066#define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK)
2067/*! @} */
2068
2069/*! @name GFC - Global Filter Configuration */
2070/*! @{ */
2071#define CAN_GFC_RRFE_MASK (0x1U)
2072#define CAN_GFC_RRFE_SHIFT (0U)
2073/*! RRFE - Reject remote frames extended.
2074 */
2075#define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK)
2076#define CAN_GFC_RRFS_MASK (0x2U)
2077#define CAN_GFC_RRFS_SHIFT (1U)
2078/*! RRFS - Reject remote frames standard.
2079 */
2080#define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK)
2081#define CAN_GFC_ANFE_MASK (0xCU)
2082#define CAN_GFC_ANFE_SHIFT (2U)
2083/*! ANFE - Accept non-matching frames extended.
2084 */
2085#define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK)
2086#define CAN_GFC_ANFS_MASK (0x30U)
2087#define CAN_GFC_ANFS_SHIFT (4U)
2088/*! ANFS - Accept non-matching frames standard.
2089 */
2090#define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK)
2091/*! @} */
2092
2093/*! @name SIDFC - Standard ID Filter Configuration */
2094/*! @{ */
2095#define CAN_SIDFC_FLSSA_MASK (0xFFFCU)
2096#define CAN_SIDFC_FLSSA_SHIFT (2U)
2097/*! FLSSA - Filter list standard start address.
2098 */
2099#define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK)
2100#define CAN_SIDFC_LSS_MASK (0xFF0000U)
2101#define CAN_SIDFC_LSS_SHIFT (16U)
2102/*! LSS - List size standard 0 = No standard message ID filter.
2103 */
2104#define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK)
2105/*! @} */
2106
2107/*! @name XIDFC - Extended ID Filter Configuration */
2108/*! @{ */
2109#define CAN_XIDFC_FLESA_MASK (0xFFFCU)
2110#define CAN_XIDFC_FLESA_SHIFT (2U)
2111/*! FLESA - Filter list extended start address.
2112 */
2113#define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK)
2114#define CAN_XIDFC_LSE_MASK (0xFF0000U)
2115#define CAN_XIDFC_LSE_SHIFT (16U)
2116/*! LSE - List size extended 0 = No extended message ID filter.
2117 */
2118#define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK)
2119/*! @} */
2120
2121/*! @name XIDAM - Extended ID AND Mask */
2122/*! @{ */
2123#define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU)
2124#define CAN_XIDAM_EIDM_SHIFT (0U)
2125/*! EIDM - Extended ID mask.
2126 */
2127#define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK)
2128/*! @} */
2129
2130/*! @name HPMS - High Priority Message Status */
2131/*! @{ */
2132#define CAN_HPMS_BIDX_MASK (0x3FU)
2133#define CAN_HPMS_BIDX_SHIFT (0U)
2134/*! BIDX - Buffer index.
2135 */
2136#define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK)
2137#define CAN_HPMS_MSI_MASK (0xC0U)
2138#define CAN_HPMS_MSI_SHIFT (6U)
2139/*! MSI - Message storage indicator.
2140 */
2141#define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK)
2142#define CAN_HPMS_FIDX_MASK (0x7F00U)
2143#define CAN_HPMS_FIDX_SHIFT (8U)
2144/*! FIDX - Filter index.
2145 */
2146#define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK)
2147#define CAN_HPMS_FLST_MASK (0x8000U)
2148#define CAN_HPMS_FLST_SHIFT (15U)
2149/*! FLST - Filter list.
2150 */
2151#define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK)
2152/*! @} */
2153
2154/*! @name NDAT1 - New Data 1 */
2155/*! @{ */
2156#define CAN_NDAT1_ND_MASK (0xFFFFFFFFU)
2157#define CAN_NDAT1_ND_SHIFT (0U)
2158/*! ND - New Data.
2159 */
2160#define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK)
2161/*! @} */
2162
2163/*! @name NDAT2 - New Data 2 */
2164/*! @{ */
2165#define CAN_NDAT2_ND_MASK (0xFFFFFFFFU)
2166#define CAN_NDAT2_ND_SHIFT (0U)
2167/*! ND - New Data.
2168 */
2169#define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK)
2170/*! @} */
2171
2172/*! @name RXF0C - Rx FIFO 0 Configuration */
2173/*! @{ */
2174#define CAN_RXF0C_F0SA_MASK (0xFFFCU)
2175#define CAN_RXF0C_F0SA_SHIFT (2U)
2176/*! F0SA - Rx FIFO 0 start address.
2177 */
2178#define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK)
2179#define CAN_RXF0C_F0S_MASK (0x7F0000U)
2180#define CAN_RXF0C_F0S_SHIFT (16U)
2181/*! F0S - Rx FIFO 0 size.
2182 */
2183#define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK)
2184#define CAN_RXF0C_F0WM_MASK (0x7F000000U)
2185#define CAN_RXF0C_F0WM_SHIFT (24U)
2186/*! F0WM - Rx FIFO 0 watermark 0 = Watermark interrupt disabled.
2187 */
2188#define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK)
2189#define CAN_RXF0C_F0OM_MASK (0x80000000U)
2190#define CAN_RXF0C_F0OM_SHIFT (31U)
2191/*! F0OM - FIFO 0 operation mode.
2192 */
2193#define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK)
2194/*! @} */
2195
2196/*! @name RXF0S - Rx FIFO 0 Status */
2197/*! @{ */
2198#define CAN_RXF0S_F0FL_MASK (0x7FU)
2199#define CAN_RXF0S_F0FL_SHIFT (0U)
2200/*! F0FL - Rx FIFO 0 fill level.
2201 */
2202#define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK)
2203#define CAN_RXF0S_F0GI_MASK (0x3F00U)
2204#define CAN_RXF0S_F0GI_SHIFT (8U)
2205/*! F0GI - Rx FIFO 0 get index.
2206 */
2207#define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK)
2208#define CAN_RXF0S_F0PI_MASK (0x3F0000U)
2209#define CAN_RXF0S_F0PI_SHIFT (16U)
2210/*! F0PI - Rx FIFO 0 put index.
2211 */
2212#define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK)
2213#define CAN_RXF0S_F0F_MASK (0x1000000U)
2214#define CAN_RXF0S_F0F_SHIFT (24U)
2215/*! F0F - Rx FIFO 0 full.
2216 */
2217#define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK)
2218#define CAN_RXF0S_RF0L_MASK (0x2000000U)
2219#define CAN_RXF0S_RF0L_SHIFT (25U)
2220/*! RF0L - Rx FIFO 0 message lost.
2221 */
2222#define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK)
2223/*! @} */
2224
2225/*! @name RXF0A - Rx FIFO 0 Acknowledge */
2226/*! @{ */
2227#define CAN_RXF0A_F0AI_MASK (0x3FU)
2228#define CAN_RXF0A_F0AI_SHIFT (0U)
2229/*! F0AI - Rx FIFO 0 acknowledge index.
2230 */
2231#define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK)
2232/*! @} */
2233
2234/*! @name RXBC - Rx Buffer Configuration */
2235/*! @{ */
2236#define CAN_RXBC_RBSA_MASK (0xFFFCU)
2237#define CAN_RXBC_RBSA_SHIFT (2U)
2238/*! RBSA - Rx buffer start address.
2239 */
2240#define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK)
2241/*! @} */
2242
2243/*! @name RXF1C - Rx FIFO 1 Configuration */
2244/*! @{ */
2245#define CAN_RXF1C_F1SA_MASK (0xFFFCU)
2246#define CAN_RXF1C_F1SA_SHIFT (2U)
2247/*! F1SA - Rx FIFO 1 start address.
2248 */
2249#define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK)
2250#define CAN_RXF1C_F1S_MASK (0x7F0000U)
2251#define CAN_RXF1C_F1S_SHIFT (16U)
2252/*! F1S - Rx FIFO 1 size 0 = No Rx FIFO 1.
2253 */
2254#define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK)
2255#define CAN_RXF1C_F1WM_MASK (0x7F000000U)
2256#define CAN_RXF1C_F1WM_SHIFT (24U)
2257/*! F1WM - Rx FIFO 1 watermark 0 = Watermark interrupt disabled.
2258 */
2259#define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK)
2260#define CAN_RXF1C_F1OM_MASK (0x80000000U)
2261#define CAN_RXF1C_F1OM_SHIFT (31U)
2262/*! F1OM - FIFO 1 operation mode.
2263 */
2264#define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK)
2265/*! @} */
2266
2267/*! @name RXF1S - Rx FIFO 1 Status */
2268/*! @{ */
2269#define CAN_RXF1S_F1FL_MASK (0x7FU)
2270#define CAN_RXF1S_F1FL_SHIFT (0U)
2271/*! F1FL - Rx FIFO 1 fill level.
2272 */
2273#define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK)
2274#define CAN_RXF1S_F1GI_MASK (0x3F00U)
2275#define CAN_RXF1S_F1GI_SHIFT (8U)
2276/*! F1GI - Rx FIFO 1 get index.
2277 */
2278#define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK)
2279#define CAN_RXF1S_F1PI_MASK (0x3F0000U)
2280#define CAN_RXF1S_F1PI_SHIFT (16U)
2281/*! F1PI - Rx FIFO 1 put index.
2282 */
2283#define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK)
2284#define CAN_RXF1S_F1F_MASK (0x1000000U)
2285#define CAN_RXF1S_F1F_SHIFT (24U)
2286/*! F1F - Rx FIFO 1 full.
2287 */
2288#define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK)
2289#define CAN_RXF1S_RF1L_MASK (0x2000000U)
2290#define CAN_RXF1S_RF1L_SHIFT (25U)
2291/*! RF1L - Rx FIFO 1 message lost.
2292 */
2293#define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK)
2294/*! @} */
2295
2296/*! @name RXF1A - Rx FIFO 1 Acknowledge */
2297/*! @{ */
2298#define CAN_RXF1A_F1AI_MASK (0x3FU)
2299#define CAN_RXF1A_F1AI_SHIFT (0U)
2300/*! F1AI - Rx FIFO 1 acknowledge index.
2301 */
2302#define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK)
2303/*! @} */
2304
2305/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */
2306/*! @{ */
2307#define CAN_RXESC_F0DS_MASK (0x7U)
2308#define CAN_RXESC_F0DS_SHIFT (0U)
2309/*! F0DS - Rx FIFO 0 data field size.
2310 */
2311#define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK)
2312#define CAN_RXESC_F1DS_MASK (0x70U)
2313#define CAN_RXESC_F1DS_SHIFT (4U)
2314/*! F1DS - Rx FIFO 1 data field size.
2315 */
2316#define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK)
2317#define CAN_RXESC_RBDS_MASK (0x700U)
2318#define CAN_RXESC_RBDS_SHIFT (8U)
2319/*! RBDS - .
2320 */
2321#define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK)
2322/*! @} */
2323
2324/*! @name TXBC - Tx Buffer Configuration */
2325/*! @{ */
2326#define CAN_TXBC_TBSA_MASK (0xFFFCU)
2327#define CAN_TXBC_TBSA_SHIFT (2U)
2328/*! TBSA - Tx buffers start address.
2329 */
2330#define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK)
2331#define CAN_TXBC_NDTB_MASK (0x3F0000U)
2332#define CAN_TXBC_NDTB_SHIFT (16U)
2333/*! NDTB - Number of dedicated transmit buffers 0 = No dedicated Tx buffers.
2334 */
2335#define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK)
2336#define CAN_TXBC_TFQS_MASK (0x3F000000U)
2337#define CAN_TXBC_TFQS_SHIFT (24U)
2338/*! TFQS - Transmit FIFO/queue size 0 = No tx FIFO/Queue.
2339 */
2340#define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK)
2341#define CAN_TXBC_TFQM_MASK (0x40000000U)
2342#define CAN_TXBC_TFQM_SHIFT (30U)
2343/*! TFQM - Tx FIFO/queue mode.
2344 */
2345#define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK)
2346/*! @} */
2347
2348/*! @name TXFQS - Tx FIFO/Queue Status */
2349/*! @{ */
2350#define CAN_TXFQS_TFGI_MASK (0x1F00U)
2351#define CAN_TXFQS_TFGI_SHIFT (8U)
2352/*! TFGI - Tx FIFO get index.
2353 */
2354#define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK)
2355#define CAN_TXFQS_TFQPI_MASK (0x1F0000U)
2356#define CAN_TXFQS_TFQPI_SHIFT (16U)
2357/*! TFQPI - Tx FIFO/queue put index.
2358 */
2359#define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK)
2360#define CAN_TXFQS_TFQF_MASK (0x200000U)
2361#define CAN_TXFQS_TFQF_SHIFT (21U)
2362/*! TFQF - Tx FIFO/queue full.
2363 */
2364#define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK)
2365/*! @} */
2366
2367/*! @name TXESC - Tx Buffer Element Size Configuration */
2368/*! @{ */
2369#define CAN_TXESC_TBDS_MASK (0x7U)
2370#define CAN_TXESC_TBDS_SHIFT (0U)
2371/*! TBDS - Tx buffer data field size.
2372 */
2373#define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK)
2374/*! @} */
2375
2376/*! @name TXBRP - Tx Buffer Request Pending */
2377/*! @{ */
2378#define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU)
2379#define CAN_TXBRP_TRP_SHIFT (0U)
2380/*! TRP - Transmission request pending.
2381 */
2382#define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK)
2383/*! @} */
2384
2385/*! @name TXBAR - Tx Buffer Add Request */
2386/*! @{ */
2387#define CAN_TXBAR_AR_MASK (0xFFFFFFFFU)
2388#define CAN_TXBAR_AR_SHIFT (0U)
2389/*! AR - Add request.
2390 */
2391#define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK)
2392/*! @} */
2393
2394/*! @name TXBCR - Tx Buffer Cancellation Request */
2395/*! @{ */
2396#define CAN_TXBCR_CR_MASK (0xFFFFFFFFU)
2397#define CAN_TXBCR_CR_SHIFT (0U)
2398/*! CR - Cancellation request.
2399 */
2400#define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK)
2401/*! @} */
2402
2403/*! @name TXBTO - Tx Buffer Transmission Occurred */
2404/*! @{ */
2405#define CAN_TXBTO_TO_MASK (0xFFFFFFFFU)
2406#define CAN_TXBTO_TO_SHIFT (0U)
2407/*! TO - Transmission occurred.
2408 */
2409#define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK)
2410/*! @} */
2411
2412/*! @name TXBCF - Tx Buffer Cancellation Finished */
2413/*! @{ */
2414#define CAN_TXBCF_TO_MASK (0xFFFFFFFFU)
2415#define CAN_TXBCF_TO_SHIFT (0U)
2416/*! TO - Cancellation finished.
2417 */
2418#define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK)
2419/*! @} */
2420
2421/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */
2422/*! @{ */
2423#define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU)
2424#define CAN_TXBTIE_TIE_SHIFT (0U)
2425/*! TIE - Transmission interrupt enable.
2426 */
2427#define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK)
2428/*! @} */
2429
2430/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */
2431/*! @{ */
2432#define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU)
2433#define CAN_TXBCIE_CFIE_SHIFT (0U)
2434/*! CFIE - Cancellation finished interrupt enable.
2435 */
2436#define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK)
2437/*! @} */
2438
2439/*! @name TXEFC - Tx Event FIFO Configuration */
2440/*! @{ */
2441#define CAN_TXEFC_EFSA_MASK (0xFFFCU)
2442#define CAN_TXEFC_EFSA_SHIFT (2U)
2443/*! EFSA - Event FIFO start address.
2444 */
2445#define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK)
2446#define CAN_TXEFC_EFS_MASK (0x3F0000U)
2447#define CAN_TXEFC_EFS_SHIFT (16U)
2448/*! EFS - Event FIFO size 0 = Tx event FIFO disabled.
2449 */
2450#define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK)
2451#define CAN_TXEFC_EFWM_MASK (0x3F000000U)
2452#define CAN_TXEFC_EFWM_SHIFT (24U)
2453/*! EFWM - Event FIFO watermark 0 = Watermark interrupt disabled.
2454 */
2455#define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK)
2456/*! @} */
2457
2458/*! @name TXEFS - Tx Event FIFO Status */
2459/*! @{ */
2460#define CAN_TXEFS_EFFL_MASK (0x3FU)
2461#define CAN_TXEFS_EFFL_SHIFT (0U)
2462/*! EFFL - Event FIFO fill level.
2463 */
2464#define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK)
2465#define CAN_TXEFS_EFGI_MASK (0x1F00U)
2466#define CAN_TXEFS_EFGI_SHIFT (8U)
2467/*! EFGI - Event FIFO get index.
2468 */
2469#define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK)
2470#define CAN_TXEFS_EFPI_MASK (0x3F0000U)
2471#define CAN_TXEFS_EFPI_SHIFT (16U)
2472/*! EFPI - Event FIFO put index.
2473 */
2474#define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK)
2475#define CAN_TXEFS_EFF_MASK (0x1000000U)
2476#define CAN_TXEFS_EFF_SHIFT (24U)
2477/*! EFF - Event FIFO full.
2478 */
2479#define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK)
2480#define CAN_TXEFS_TEFL_MASK (0x2000000U)
2481#define CAN_TXEFS_TEFL_SHIFT (25U)
2482/*! TEFL - Tx event FIFO element lost.
2483 */
2484#define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK)
2485/*! @} */
2486
2487/*! @name TXEFA - Tx Event FIFO Acknowledge */
2488/*! @{ */
2489#define CAN_TXEFA_EFAI_MASK (0x1FU)
2490#define CAN_TXEFA_EFAI_SHIFT (0U)
2491/*! EFAI - Event FIFO acknowledge index.
2492 */
2493#define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK)
2494/*! @} */
2495
2496/*! @name MRBA - CAN Message RAM Base Address */
2497/*! @{ */
2498#define CAN_MRBA_BA_MASK (0xFFFF0000U)
2499#define CAN_MRBA_BA_SHIFT (16U)
2500/*! BA - Base address for the message RAM in the chip memory map.
2501 */
2502#define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK)
2503/*! @} */
2504
2505/*! @name ETSCC - External Timestamp Counter Configuration */
2506/*! @{ */
2507#define CAN_ETSCC_ETCP_MASK (0x7FFU)
2508#define CAN_ETSCC_ETCP_SHIFT (0U)
2509/*! ETCP - External timestamp prescaler value.
2510 */
2511#define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK)
2512#define CAN_ETSCC_ETCE_MASK (0x80000000U)
2513#define CAN_ETSCC_ETCE_SHIFT (31U)
2514/*! ETCE - External timestamp counter enable.
2515 */
2516#define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK)
2517/*! @} */
2518
2519/*! @name ETSCV - External Timestamp Counter Value */
2520/*! @{ */
2521#define CAN_ETSCV_ETSC_MASK (0xFFFFU)
2522#define CAN_ETSCV_ETSC_SHIFT (0U)
2523/*! ETSC - External timestamp counter.
2524 */
2525#define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK)
2526/*! @} */
2527
2528
2529/*!
2530 * @}
2531 */ /* end of group CAN_Register_Masks */
2532
2533
2534/* CAN - Peripheral instance base addresses */
2535/** Peripheral CAN0 base address */
2536#define CAN0_BASE (0x4009D000u)
2537/** Peripheral CAN0 base pointer */
2538#define CAN0 ((CAN_Type *)CAN0_BASE)
2539/** Peripheral CAN1 base address */
2540#define CAN1_BASE (0x4009E000u)
2541/** Peripheral CAN1 base pointer */
2542#define CAN1 ((CAN_Type *)CAN1_BASE)
2543/** Array initializer of CAN peripheral base addresses */
2544#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
2545/** Array initializer of CAN peripheral base pointers */
2546#define CAN_BASE_PTRS { CAN0, CAN1 }
2547/** Interrupt vectors for the CAN peripheral type */
2548#define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } }
2549
2550/*!
2551 * @}
2552 */ /* end of group CAN_Peripheral_Access_Layer */
2553
2554
2555/* ----------------------------------------------------------------------------
2556 -- CRC Peripheral Access Layer
2557 ---------------------------------------------------------------------------- */
2558
2559/*!
2560 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
2561 * @{
2562 */
2563
2564/** CRC - Register Layout Typedef */
2565typedef struct {
2566 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
2567 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
2568 union { /* offset: 0x8 */
2569 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
2570 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
2571 };
2572} CRC_Type;
2573
2574/* ----------------------------------------------------------------------------
2575 -- CRC Register Masks
2576 ---------------------------------------------------------------------------- */
2577
2578/*!
2579 * @addtogroup CRC_Register_Masks CRC Register Masks
2580 * @{
2581 */
2582
2583/*! @name MODE - CRC mode register */
2584/*! @{ */
2585#define CRC_MODE_CRC_POLY_MASK (0x3U)
2586#define CRC_MODE_CRC_POLY_SHIFT (0U)
2587/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
2588 */
2589#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
2590#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
2591#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
2592/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
2593 */
2594#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
2595#define CRC_MODE_CMPL_WR_MASK (0x8U)
2596#define CRC_MODE_CMPL_WR_SHIFT (3U)
2597/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
2598 */
2599#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
2600#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
2601#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
2602/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
2603 */
2604#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
2605#define CRC_MODE_CMPL_SUM_MASK (0x20U)
2606#define CRC_MODE_CMPL_SUM_SHIFT (5U)
2607/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
2608 */
2609#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
2610/*! @} */
2611
2612/*! @name SEED - CRC seed register */
2613/*! @{ */
2614#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
2615#define CRC_SEED_CRC_SEED_SHIFT (0U)
2616/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
2617 * selected bit order and 1's complement pre-processes. A write access to this register will
2618 * overrule the CRC calculation in progresses.
2619 */
2620#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
2621/*! @} */
2622
2623/*! @name SUM - CRC checksum register */
2624/*! @{ */
2625#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
2626#define CRC_SUM_CRC_SUM_SHIFT (0U)
2627/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
2628 */
2629#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
2630/*! @} */
2631
2632/*! @name WR_DATA - CRC data register */
2633/*! @{ */
2634#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
2635#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
2636/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
2637 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
2638 * accept back-to-back transactions.
2639 */
2640#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
2641/*! @} */
2642
2643
2644/*!
2645 * @}
2646 */ /* end of group CRC_Register_Masks */
2647
2648
2649/* CRC - Peripheral instance base addresses */
2650/** Peripheral CRC_ENGINE base address */
2651#define CRC_ENGINE_BASE (0x40095000u)
2652/** Peripheral CRC_ENGINE base pointer */
2653#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
2654/** Array initializer of CRC peripheral base addresses */
2655#define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
2656/** Array initializer of CRC peripheral base pointers */
2657#define CRC_BASE_PTRS { CRC_ENGINE }
2658
2659/*!
2660 * @}
2661 */ /* end of group CRC_Peripheral_Access_Layer */
2662
2663
2664/* ----------------------------------------------------------------------------
2665 -- CTIMER Peripheral Access Layer
2666 ---------------------------------------------------------------------------- */
2667
2668/*!
2669 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
2670 * @{
2671 */
2672
2673/** CTIMER - Register Layout Typedef */
2674typedef struct {
2675 __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
2676 __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
2677 __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */
2678 __IO uint32_t PR; /**< Prescale Register, offset: 0xC */
2679 __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */
2680 __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */
2681 __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
2682 __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
2683 __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
2684 __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
2685 uint8_t RESERVED_0[48];
2686 __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
2687 __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
2688 __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
2689} CTIMER_Type;
2690
2691/* ----------------------------------------------------------------------------
2692 -- CTIMER Register Masks
2693 ---------------------------------------------------------------------------- */
2694
2695/*!
2696 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
2697 * @{
2698 */
2699
2700/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
2701/*! @{ */
2702#define CTIMER_IR_MR0INT_MASK (0x1U)
2703#define CTIMER_IR_MR0INT_SHIFT (0U)
2704/*! MR0INT - Interrupt flag for match channel 0.
2705 */
2706#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
2707#define CTIMER_IR_MR1INT_MASK (0x2U)
2708#define CTIMER_IR_MR1INT_SHIFT (1U)
2709/*! MR1INT - Interrupt flag for match channel 1.
2710 */
2711#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
2712#define CTIMER_IR_MR2INT_MASK (0x4U)
2713#define CTIMER_IR_MR2INT_SHIFT (2U)
2714/*! MR2INT - Interrupt flag for match channel 2.
2715 */
2716#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
2717#define CTIMER_IR_MR3INT_MASK (0x8U)
2718#define CTIMER_IR_MR3INT_SHIFT (3U)
2719/*! MR3INT - Interrupt flag for match channel 3.
2720 */
2721#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
2722#define CTIMER_IR_CR0INT_MASK (0x10U)
2723#define CTIMER_IR_CR0INT_SHIFT (4U)
2724/*! CR0INT - Interrupt flag for capture channel 0 event.
2725 */
2726#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
2727#define CTIMER_IR_CR1INT_MASK (0x20U)
2728#define CTIMER_IR_CR1INT_SHIFT (5U)
2729/*! CR1INT - Interrupt flag for capture channel 1 event.
2730 */
2731#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
2732#define CTIMER_IR_CR2INT_MASK (0x40U)
2733#define CTIMER_IR_CR2INT_SHIFT (6U)
2734/*! CR2INT - Interrupt flag for capture channel 2 event.
2735 */
2736#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
2737#define CTIMER_IR_CR3INT_MASK (0x80U)
2738#define CTIMER_IR_CR3INT_SHIFT (7U)
2739/*! CR3INT - Interrupt flag for capture channel 3 event.
2740 */
2741#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
2742/*! @} */
2743
2744/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
2745/*! @{ */
2746#define CTIMER_TCR_CEN_MASK (0x1U)
2747#define CTIMER_TCR_CEN_SHIFT (0U)
2748/*! CEN - Counter enable.
2749 * 0b0..Disabled.The counters are disabled.
2750 * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
2751 */
2752#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
2753#define CTIMER_TCR_CRST_MASK (0x2U)
2754#define CTIMER_TCR_CRST_SHIFT (1U)
2755/*! CRST - Counter reset.
2756 * 0b0..Disabled. Do nothing.
2757 * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
2758 * the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
2759 */
2760#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
2761/*! @} */
2762
2763/*! @name TC - Timer Counter */
2764/*! @{ */
2765#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
2766#define CTIMER_TC_TCVAL_SHIFT (0U)
2767/*! TCVAL - Timer counter value.
2768 */
2769#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
2770/*! @} */
2771
2772/*! @name PR - Prescale Register */
2773/*! @{ */
2774#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
2775#define CTIMER_PR_PRVAL_SHIFT (0U)
2776/*! PRVAL - Prescale counter value.
2777 */
2778#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
2779/*! @} */
2780
2781/*! @name PC - Prescale Counter */
2782/*! @{ */
2783#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
2784#define CTIMER_PC_PCVAL_SHIFT (0U)
2785/*! PCVAL - Prescale counter value.
2786 */
2787#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
2788/*! @} */
2789
2790/*! @name MCR - Match Control Register */
2791/*! @{ */
2792#define CTIMER_MCR_MR0I_MASK (0x1U)
2793#define CTIMER_MCR_MR0I_SHIFT (0U)
2794/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
2795 */
2796#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
2797#define CTIMER_MCR_MR0R_MASK (0x2U)
2798#define CTIMER_MCR_MR0R_SHIFT (1U)
2799/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it.
2800 */
2801#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
2802#define CTIMER_MCR_MR0S_MASK (0x4U)
2803#define CTIMER_MCR_MR0S_SHIFT (2U)
2804/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
2805 */
2806#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
2807#define CTIMER_MCR_MR1I_MASK (0x8U)
2808#define CTIMER_MCR_MR1I_SHIFT (3U)
2809/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
2810 */
2811#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
2812#define CTIMER_MCR_MR1R_MASK (0x10U)
2813#define CTIMER_MCR_MR1R_SHIFT (4U)
2814/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it.
2815 */
2816#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
2817#define CTIMER_MCR_MR1S_MASK (0x20U)
2818#define CTIMER_MCR_MR1S_SHIFT (5U)
2819/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
2820 */
2821#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
2822#define CTIMER_MCR_MR2I_MASK (0x40U)
2823#define CTIMER_MCR_MR2I_SHIFT (6U)
2824/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
2825 */
2826#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
2827#define CTIMER_MCR_MR2R_MASK (0x80U)
2828#define CTIMER_MCR_MR2R_SHIFT (7U)
2829/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it.
2830 */
2831#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
2832#define CTIMER_MCR_MR2S_MASK (0x100U)
2833#define CTIMER_MCR_MR2S_SHIFT (8U)
2834/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
2835 */
2836#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
2837#define CTIMER_MCR_MR3I_MASK (0x200U)
2838#define CTIMER_MCR_MR3I_SHIFT (9U)
2839/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
2840 */
2841#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
2842#define CTIMER_MCR_MR3R_MASK (0x400U)
2843#define CTIMER_MCR_MR3R_SHIFT (10U)
2844/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it.
2845 */
2846#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
2847#define CTIMER_MCR_MR3S_MASK (0x800U)
2848#define CTIMER_MCR_MR3S_SHIFT (11U)
2849/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
2850 */
2851#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
2852#define CTIMER_MCR_MR0RL_MASK (0x1000000U)
2853#define CTIMER_MCR_MR0RL_SHIFT (24U)
2854/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
2855 * (either via a match event or a write to bit 1 of the TCR).
2856 */
2857#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
2858#define CTIMER_MCR_MR1RL_MASK (0x2000000U)
2859#define CTIMER_MCR_MR1RL_SHIFT (25U)
2860/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
2861 * (either via a match event or a write to bit 1 of the TCR).
2862 */
2863#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
2864#define CTIMER_MCR_MR2RL_MASK (0x4000000U)
2865#define CTIMER_MCR_MR2RL_SHIFT (26U)
2866/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
2867 * (either via a match event or a write to bit 1 of the TCR).
2868 */
2869#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
2870#define CTIMER_MCR_MR3RL_MASK (0x8000000U)
2871#define CTIMER_MCR_MR3RL_SHIFT (27U)
2872/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
2873 * (either via a match event or a write to bit 1 of the TCR).
2874 */
2875#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
2876/*! @} */
2877
2878/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
2879/*! @{ */
2880#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
2881#define CTIMER_MR_MATCH_SHIFT (0U)
2882/*! MATCH - Timer counter match value.
2883 */
2884#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
2885/*! @} */
2886
2887/* The count of CTIMER_MR */
2888#define CTIMER_MR_COUNT (4U)
2889
2890/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
2891/*! @{ */
2892#define CTIMER_CCR_CAP0RE_MASK (0x1U)
2893#define CTIMER_CCR_CAP0RE_SHIFT (0U)
2894/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
2895 * the contents of TC. 0 = disabled. 1 = enabled.
2896 */
2897#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
2898#define CTIMER_CCR_CAP0FE_MASK (0x2U)
2899#define CTIMER_CCR_CAP0FE_SHIFT (1U)
2900/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
2901 * the contents of TC. 0 = disabled. 1 = enabled.
2902 */
2903#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
2904#define CTIMER_CCR_CAP0I_MASK (0x4U)
2905#define CTIMER_CCR_CAP0I_SHIFT (2U)
2906/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
2907 */
2908#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
2909#define CTIMER_CCR_CAP1RE_MASK (0x8U)
2910#define CTIMER_CCR_CAP1RE_SHIFT (3U)
2911/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
2912 * the contents of TC. 0 = disabled. 1 = enabled.
2913 */
2914#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
2915#define CTIMER_CCR_CAP1FE_MASK (0x10U)
2916#define CTIMER_CCR_CAP1FE_SHIFT (4U)
2917/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
2918 * the contents of TC. 0 = disabled. 1 = enabled.
2919 */
2920#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
2921#define CTIMER_CCR_CAP1I_MASK (0x20U)
2922#define CTIMER_CCR_CAP1I_SHIFT (5U)
2923/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
2924 */
2925#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
2926#define CTIMER_CCR_CAP2RE_MASK (0x40U)
2927#define CTIMER_CCR_CAP2RE_SHIFT (6U)
2928/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
2929 * the contents of TC. 0 = disabled. 1 = enabled.
2930 */
2931#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
2932#define CTIMER_CCR_CAP2FE_MASK (0x80U)
2933#define CTIMER_CCR_CAP2FE_SHIFT (7U)
2934/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
2935 * the contents of TC. 0 = disabled. 1 = enabled.
2936 */
2937#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
2938#define CTIMER_CCR_CAP2I_MASK (0x100U)
2939#define CTIMER_CCR_CAP2I_SHIFT (8U)
2940/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
2941 */
2942#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
2943#define CTIMER_CCR_CAP3RE_MASK (0x200U)
2944#define CTIMER_CCR_CAP3RE_SHIFT (9U)
2945/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with
2946 * the contents of TC. 0 = disabled. 1 = enabled.
2947 */
2948#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
2949#define CTIMER_CCR_CAP3FE_MASK (0x400U)
2950#define CTIMER_CCR_CAP3FE_SHIFT (10U)
2951/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with
2952 * the contents of TC. 0 = disabled. 1 = enabled.
2953 */
2954#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
2955#define CTIMER_CCR_CAP3I_MASK (0x800U)
2956#define CTIMER_CCR_CAP3I_SHIFT (11U)
2957/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
2958 */
2959#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
2960/*! @} */
2961
2962/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
2963/*! @{ */
2964#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
2965#define CTIMER_CR_CAP_SHIFT (0U)
2966/*! CAP - Timer counter capture value.
2967 */
2968#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
2969/*! @} */
2970
2971/* The count of CTIMER_CR */
2972#define CTIMER_CR_COUNT (4U)
2973
2974/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
2975/*! @{ */
2976#define CTIMER_EMR_EM0_MASK (0x1U)
2977#define CTIMER_EMR_EM0_SHIFT (0U)
2978/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
2979 * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
2980 * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
2981 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2982 */
2983#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
2984#define CTIMER_EMR_EM1_MASK (0x2U)
2985#define CTIMER_EMR_EM1_SHIFT (1U)
2986/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
2987 * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
2988 * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
2989 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2990 */
2991#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
2992#define CTIMER_EMR_EM2_MASK (0x4U)
2993#define CTIMER_EMR_EM2_SHIFT (2U)
2994/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
2995 * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
2996 * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
2997 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2998 */
2999#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
3000#define CTIMER_EMR_EM3_MASK (0x8U)
3001#define CTIMER_EMR_EM3_SHIFT (3U)
3002/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
3003 * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
3004 * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
3005 * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
3006 */
3007#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
3008#define CTIMER_EMR_EMC0_MASK (0x30U)
3009#define CTIMER_EMR_EMC0_SHIFT (4U)
3010/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
3011 * 0b00..Do Nothing.
3012 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
3013 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
3014 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3015 */
3016#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
3017#define CTIMER_EMR_EMC1_MASK (0xC0U)
3018#define CTIMER_EMR_EMC1_SHIFT (6U)
3019/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
3020 * 0b00..Do Nothing.
3021 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
3022 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
3023 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3024 */
3025#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
3026#define CTIMER_EMR_EMC2_MASK (0x300U)
3027#define CTIMER_EMR_EMC2_SHIFT (8U)
3028/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
3029 * 0b00..Do Nothing.
3030 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
3031 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
3032 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3033 */
3034#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
3035#define CTIMER_EMR_EMC3_MASK (0xC00U)
3036#define CTIMER_EMR_EMC3_SHIFT (10U)
3037/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
3038 * 0b00..Do Nothing.
3039 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
3040 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
3041 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3042 */
3043#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
3044/*! @} */
3045
3046/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
3047/*! @{ */
3048#define CTIMER_CTCR_CTMODE_MASK (0x3U)
3049#define CTIMER_CTCR_CTMODE_SHIFT (0U)
3050/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
3051 * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
3052 * is incremented when the Prescale Counter matches the Prescale Register.
3053 * 0b00..Timer Mode. Incremented every rising APB bus clock edge.
3054 * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
3055 * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
3056 * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
3057 */
3058#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
3059#define CTIMER_CTCR_CINSEL_MASK (0xCU)
3060#define CTIMER_CTCR_CINSEL_SHIFT (2U)
3061/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
3062 * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
3063 * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
3064 * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
3065 * same timer.
3066 * 0b00..Channel 0. CAPn.0 for CTIMERn
3067 * 0b01..Channel 1. CAPn.1 for CTIMERn
3068 * 0b10..Channel 2. CAPn.2 for CTIMERn
3069 * 0b11..Channel 3. CAPn.3 for CTIMERn
3070 */
3071#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
3072#define CTIMER_CTCR_ENCC_MASK (0x10U)
3073#define CTIMER_CTCR_ENCC_SHIFT (4U)
3074/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
3075 * capture-edge event specified in bits 7:5 occurs.
3076 */
3077#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
3078#define CTIMER_CTCR_SELCC_MASK (0xE0U)
3079#define CTIMER_CTCR_SELCC_SHIFT (5U)
3080/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
3081 * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
3082 * 0x3 and 0x6 to 0x7 are reserved.
3083 * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
3084 * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
3085 * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
3086 * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
3087 * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
3088 * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
3089 */
3090#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
3091/*! @} */
3092
3093/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
3094/*! @{ */
3095#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
3096#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
3097/*! PWMEN0 - PWM mode enable for channel0.
3098 * 0b0..Match. CTIMERn_MAT0 is controlled by EM0.
3099 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
3100 */
3101#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
3102#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
3103#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
3104/*! PWMEN1 - PWM mode enable for channel1.
3105 * 0b0..Match. CTIMERn_MAT01 is controlled by EM1.
3106 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
3107 */
3108#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
3109#define CTIMER_PWMC_PWMEN2_MASK (0x4U)
3110#define CTIMER_PWMC_PWMEN2_SHIFT (2U)
3111/*! PWMEN2 - PWM mode enable for channel2.
3112 * 0b0..Match. CTIMERn_MAT2 is controlled by EM2.
3113 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
3114 */
3115#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
3116#define CTIMER_PWMC_PWMEN3_MASK (0x8U)
3117#define CTIMER_PWMC_PWMEN3_SHIFT (3U)
3118/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
3119 * 0b0..Match. CTIMERn_MAT3 is controlled by EM3.
3120 * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
3121 */
3122#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
3123/*! @} */
3124
3125/*! @name MSR - Match Shadow Register */
3126/*! @{ */
3127#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU)
3128#define CTIMER_MSR_SHADOWW_SHIFT (0U)
3129/*! SHADOWW - Timer counter match shadow value.
3130 */
3131#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)
3132/*! @} */
3133
3134/* The count of CTIMER_MSR */
3135#define CTIMER_MSR_COUNT (4U)
3136
3137
3138/*!
3139 * @}
3140 */ /* end of group CTIMER_Register_Masks */
3141
3142
3143/* CTIMER - Peripheral instance base addresses */
3144/** Peripheral CTIMER0 base address */
3145#define CTIMER0_BASE (0x40008000u)
3146/** Peripheral CTIMER0 base pointer */
3147#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
3148/** Peripheral CTIMER1 base address */
3149#define CTIMER1_BASE (0x40009000u)
3150/** Peripheral CTIMER1 base pointer */
3151#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
3152/** Peripheral CTIMER2 base address */
3153#define CTIMER2_BASE (0x40028000u)
3154/** Peripheral CTIMER2 base pointer */
3155#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
3156/** Peripheral CTIMER3 base address */
3157#define CTIMER3_BASE (0x40048000u)
3158/** Peripheral CTIMER3 base pointer */
3159#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
3160/** Peripheral CTIMER4 base address */
3161#define CTIMER4_BASE (0x40049000u)
3162/** Peripheral CTIMER4 base pointer */
3163#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
3164/** Array initializer of CTIMER peripheral base addresses */
3165#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
3166/** Array initializer of CTIMER peripheral base pointers */
3167#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
3168/** Interrupt vectors for the CTIMER peripheral type */
3169#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
3170
3171/*!
3172 * @}
3173 */ /* end of group CTIMER_Peripheral_Access_Layer */
3174
3175
3176/* ----------------------------------------------------------------------------
3177 -- DMA Peripheral Access Layer
3178 ---------------------------------------------------------------------------- */
3179
3180/*!
3181 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
3182 * @{
3183 */
3184
3185/** DMA - Register Layout Typedef */
3186typedef struct {
3187 __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
3188 __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
3189 __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
3190 uint8_t RESERVED_0[20];
3191 struct { /* offset: 0x20, array step: 0x5C */
3192 __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
3193 uint8_t RESERVED_0[4];
3194 __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
3195 uint8_t RESERVED_1[4];
3196 __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
3197 uint8_t RESERVED_2[4];
3198 __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
3199 uint8_t RESERVED_3[4];
3200 __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
3201 uint8_t RESERVED_4[4];
3202 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
3203 uint8_t RESERVED_5[4];
3204 __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
3205 uint8_t RESERVED_6[4];
3206 __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
3207 uint8_t RESERVED_7[4];
3208 __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
3209 uint8_t RESERVED_8[4];
3210 __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
3211 uint8_t RESERVED_9[4];
3212 __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
3213 uint8_t RESERVED_10[4];
3214 __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
3215 } COMMON[1];
3216 uint8_t RESERVED_1[900];
3217 struct { /* offset: 0x400, array step: 0x10 */
3218 __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
3219 __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
3220 __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
3221 uint8_t RESERVED_0[4];
3222 } CHANNEL[32];
3223} DMA_Type;
3224
3225/* ----------------------------------------------------------------------------
3226 -- DMA Register Masks
3227 ---------------------------------------------------------------------------- */
3228
3229/*!
3230 * @addtogroup DMA_Register_Masks DMA Register Masks
3231 * @{
3232 */
3233
3234/*! @name CTRL - DMA control. */
3235/*! @{ */
3236#define DMA_CTRL_ENABLE_MASK (0x1U)
3237#define DMA_CTRL_ENABLE_SHIFT (0U)
3238/*! ENABLE - DMA controller master enable.
3239 * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
3240 * disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
3241 * 0b1..Enabled. The DMA controller is enabled.
3242 */
3243#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
3244/*! @} */
3245
3246/*! @name INTSTAT - Interrupt status. */
3247/*! @{ */
3248#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
3249#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
3250/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
3251 * 0b0..Not pending. No enabled interrupts are pending.
3252 * 0b1..Pending. At least one enabled interrupt is pending.
3253 */
3254#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
3255#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
3256#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
3257/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
3258 * 0b0..Not pending. No error interrupts are pending.
3259 * 0b1..Pending. At least one error interrupt is pending.
3260 */
3261#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
3262/*! @} */
3263
3264/*! @name SRAMBASE - SRAM address of the channel configuration table. */
3265/*! @{ */
3266#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
3267#define DMA_SRAMBASE_OFFSET_SHIFT (9U)
3268/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
3269 * table must begin on a 512 byte boundary.
3270 */
3271#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
3272/*! @} */
3273
3274/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
3275/*! @{ */
3276#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)
3277#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
3278/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
3279 * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
3280 */
3281#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
3282/*! @} */
3283
3284/* The count of DMA_COMMON_ENABLESET */
3285#define DMA_COMMON_ENABLESET_COUNT (1U)
3286
3287/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
3288/*! @{ */
3289#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)
3290#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
3291/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
3292 * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
3293 * are reserved.
3294 */
3295#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
3296/*! @} */
3297
3298/* The count of DMA_COMMON_ENABLECLR */
3299#define DMA_COMMON_ENABLECLR_COUNT (1U)
3300
3301/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
3302/*! @{ */
3303#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)
3304#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
3305/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
3306 * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
3307 */
3308#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
3309/*! @} */
3310
3311/* The count of DMA_COMMON_ACTIVE */
3312#define DMA_COMMON_ACTIVE_COUNT (1U)
3313
3314/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
3315/*! @{ */
3316#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)
3317#define DMA_COMMON_BUSY_BSY_SHIFT (0U)
3318/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
3319 * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
3320 */
3321#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
3322/*! @} */
3323
3324/* The count of DMA_COMMON_BUSY */
3325#define DMA_COMMON_BUSY_COUNT (1U)
3326
3327/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
3328/*! @{ */
3329#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)
3330#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
3331/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
3332 * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
3333 * not active. 1 = error interrupt is active.
3334 */
3335#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
3336/*! @} */
3337
3338/* The count of DMA_COMMON_ERRINT */
3339#define DMA_COMMON_ERRINT_COUNT (1U)
3340
3341/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
3342/*! @{ */
3343#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)
3344#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
3345/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
3346 * number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
3347 * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
3348 */
3349#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
3350/*! @} */
3351
3352/* The count of DMA_COMMON_INTENSET */
3353#define DMA_COMMON_INTENSET_COUNT (1U)
3354
3355/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
3356/*! @{ */
3357#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)
3358#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
3359/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
3360 * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
3361 * reserved.
3362 */
3363#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
3364/*! @} */
3365
3366/* The count of DMA_COMMON_INTENCLR */
3367#define DMA_COMMON_INTENCLR_COUNT (1U)
3368
3369/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
3370/*! @{ */
3371#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)
3372#define DMA_COMMON_INTA_IA_SHIFT (0U)
3373/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
3374 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
3375 * interrupt A is not active. 1 = the DMA channel interrupt A is active.
3376 */
3377#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
3378/*! @} */
3379
3380/* The count of DMA_COMMON_INTA */
3381#define DMA_COMMON_INTA_COUNT (1U)
3382
3383/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
3384/*! @{ */
3385#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)
3386#define DMA_COMMON_INTB_IB_SHIFT (0U)
3387/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
3388 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
3389 * interrupt B is not active. 1 = the DMA channel interrupt B is active.
3390 */
3391#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
3392/*! @} */
3393
3394/* The count of DMA_COMMON_INTB */
3395#define DMA_COMMON_INTB_COUNT (1U)
3396
3397/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
3398/*! @{ */
3399#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)
3400#define DMA_COMMON_SETVALID_SV_SHIFT (0U)
3401/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
3402 * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
3403 * VALIDPENDING control bit for DMA channel n
3404 */
3405#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
3406/*! @} */
3407
3408/* The count of DMA_COMMON_SETVALID */
3409#define DMA_COMMON_SETVALID_COUNT (1U)
3410
3411/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
3412/*! @{ */
3413#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)
3414#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
3415/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
3416 * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
3417 * sets the TRIG bit for DMA channel n.
3418 */
3419#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
3420/*! @} */
3421
3422/* The count of DMA_COMMON_SETTRIG */
3423#define DMA_COMMON_SETTRIG_COUNT (1U)
3424
3425/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
3426/*! @{ */
3427#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)
3428#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
3429/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
3430 * 1 = aborts DMA operations on channel n.
3431 */
3432#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
3433/*! @} */
3434
3435/* The count of DMA_COMMON_ABORT */
3436#define DMA_COMMON_ABORT_COUNT (1U)
3437
3438/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
3439/*! @{ */
3440#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
3441#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
3442/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
3443 * move, any peripheral DMA request associated with that channel can be disabled to prevent any
3444 * interaction between the peripheral and the DMA controller.
3445 * 0b0..Disabled. Peripheral DMA requests are disabled.
3446 * 0b1..Enabled. Peripheral DMA requests are enabled.
3447 */
3448#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
3449#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
3450#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
3451/*! HWTRIGEN - Hardware Triggering Enable for this channel.
3452 * 0b0..Disabled. Hardware triggering is not used.
3453 * 0b1..Enabled. Use hardware triggering.
3454 */
3455#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
3456#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
3457#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
3458/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
3459 * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
3460 * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
3461 */
3462#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
3463#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
3464#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
3465/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
3466 * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
3467 * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
3468 * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
3469 * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
3470 * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
3471 * current BURSTPOWER length are completed.
3472 */
3473#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
3474#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
3475#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
3476/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
3477 * 0b0..Single transfer. Hardware trigger causes a single transfer.
3478 * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
3479 * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a
3480 * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
3481 * complete.
3482 */
3483#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
3484#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
3485#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
3486/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
3487 * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
3488 * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
3489 * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that
3490 * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:
3491 * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =
3492 * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The
3493 * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
3494 * multiple of the burst size.
3495 */
3496#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
3497#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
3498#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
3499/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
3500 * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this
3501 * could be used to read several sequential registers from a peripheral for each DMA burst,
3502 * reading the same registers again for each burst.
3503 * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
3504 * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
3505 */
3506#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
3507#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
3508#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
3509/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
3510 * 'wrapped', meaning that the destination address range for each burst will be the same. As an
3511 * example, this could be used to write several sequential registers to a peripheral for each DMA
3512 * burst, writing the same registers again for each burst.
3513 * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
3514 * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
3515 */
3516#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
3517#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
3518#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
3519/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority
3520 * levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
3521 */
3522#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
3523/*! @} */
3524
3525/* The count of DMA_CHANNEL_CFG */
3526#define DMA_CHANNEL_CFG_COUNT (32U)
3527
3528/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
3529/*! @{ */
3530#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
3531#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
3532/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the
3533 * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
3534 * 0b0..No effect. No effect on DMA operation.
3535 * 0b1..Valid pending.
3536 */
3537#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
3538#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
3539#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
3540/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is
3541 * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
3542 * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
3543 * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
3544 */
3545#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
3546/*! @} */
3547
3548/* The count of DMA_CHANNEL_CTLSTAT */
3549#define DMA_CHANNEL_CTLSTAT_COUNT (32U)
3550
3551/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
3552/*! @{ */
3553#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
3554#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
3555/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor
3556 * is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
3557 * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
3558 * 0b1..Valid. The current channel descriptor is considered valid.
3559 */
3560#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
3561#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
3562#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
3563/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current
3564 * descriptor is exhausted. Reloading allows ping-pong and linked transfers.
3565 * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
3566 * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.
3567 */
3568#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
3569#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
3570#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
3571/*! SWTRIG - Software Trigger.
3572 * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by
3573 * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
3574 * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not
3575 * be used with level triggering when TRIGBURST = 0.
3576 */
3577#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
3578#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)
3579#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)
3580/*! CLRTRIG - Clear Trigger.
3581 * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
3582 * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted
3583 */
3584#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
3585#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)
3586#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)
3587/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between
3588 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
3589 * convention, interrupt A may be used when only one interrupt flag is needed.
3590 * 0b0..No effect.
3591 * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
3592 */
3593#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
3594#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)
3595#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)
3596/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between
3597 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
3598 * convention, interrupt A may be used when only one interrupt flag is needed.
3599 * 0b0..No effect.
3600 * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
3601 */
3602#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
3603#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)
3604#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)
3605/*! WIDTH - Transfer width used for this DMA channel.
3606 * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
3607 * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
3608 * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
3609 * 0b11..Reserved. Reserved setting, do not use.
3610 */
3611#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
3612#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)
3613#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)
3614/*! SRCINC - Determines whether the source address is incremented for each DMA transfer.
3615 * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
3616 * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is
3617 * the usual case when the source is memory.
3618 * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
3619 * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
3620 */
3621#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
3622#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)
3623#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)
3624/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer.
3625 * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when
3626 * the destination is a peripheral device.
3627 * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer.
3628 * This is the usual case when the destination is memory.
3629 * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
3630 * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
3631 */
3632#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
3633#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)
3634#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)
3635/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes
3636 * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller
3637 * uses this bit field during transfer to count down. Hence, it cannot be used by software to read
3638 * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1
3639 * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of
3640 * 1,024 transfers will be performed.
3641 */
3642#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
3643/*! @} */
3644
3645/* The count of DMA_CHANNEL_XFERCFG */
3646#define DMA_CHANNEL_XFERCFG_COUNT (32U)
3647
3648
3649/*!
3650 * @}
3651 */ /* end of group DMA_Register_Masks */
3652
3653
3654/* DMA - Peripheral instance base addresses */
3655/** Peripheral DMA0 base address */
3656#define DMA0_BASE (0x40082000u)
3657/** Peripheral DMA0 base pointer */
3658#define DMA0 ((DMA_Type *)DMA0_BASE)
3659/** Array initializer of DMA peripheral base addresses */
3660#define DMA_BASE_ADDRS { DMA0_BASE }
3661/** Array initializer of DMA peripheral base pointers */
3662#define DMA_BASE_PTRS { DMA0 }
3663/** Interrupt vectors for the DMA peripheral type */
3664#define DMA_IRQS { DMA0_IRQn }
3665
3666/*!
3667 * @}
3668 */ /* end of group DMA_Peripheral_Access_Layer */
3669
3670
3671/* ----------------------------------------------------------------------------
3672 -- DMIC Peripheral Access Layer
3673 ---------------------------------------------------------------------------- */
3674
3675/*!
3676 * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
3677 * @{
3678 */
3679
3680/** DMIC - Register Layout Typedef */
3681typedef struct {
3682 struct { /* offset: 0x0, array step: 0x100 */
3683 __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */
3684 __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */
3685 __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */
3686 __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */
3687 __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */
3688 uint8_t RESERVED_0[108];
3689 __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */
3690 __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */
3691 __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */
3692 __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */
3693 __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */
3694 uint8_t RESERVED_1[108];
3695 } CHANNEL[2];
3696 uint8_t RESERVED_0[3328];
3697 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */
3698 uint8_t RESERVED_1[8];
3699 __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */
3700 __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */
3701 uint8_t RESERVED_2[108];
3702 __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */
3703 __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */
3704 __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */
3705 __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */
3706 __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */
3707 __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */
3708 __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */
3709 uint8_t RESERVED_3[96];
3710 __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */
3711} DMIC_Type;
3712
3713/* ----------------------------------------------------------------------------
3714 -- DMIC Register Masks
3715 ---------------------------------------------------------------------------- */
3716
3717/*!
3718 * @addtogroup DMIC_Register_Masks DMIC Register Masks
3719 * @{
3720 */
3721
3722/*! @name CHANNEL_OSR - Oversample Rate register 0 */
3723/*! @{ */
3724#define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU)
3725#define DMIC_CHANNEL_OSR_OSR_SHIFT (0U)
3726/*! OSR - Selects the oversample rate for the related input channel.
3727 */
3728#define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
3729/*! @} */
3730
3731/* The count of DMIC_CHANNEL_OSR */
3732#define DMIC_CHANNEL_OSR_COUNT (2U)
3733
3734/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */
3735/*! @{ */
3736#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU)
3737#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U)
3738/*! PDMDIV - PDM clock divider value. 0 = divide by 1 1 = divide by 2 2 = divide by 3 3 = divide by
3739 * 4 4 = divide by 6 5 = divide by 8 6 = divide by 12 7 = divide by 16 8 = divide by 24 9 =
3740 * divide by 32 10 = divide by 48 11 = divide by 64 12 = divide by 96 13 = divide by 128 others =
3741 * reserved.
3742 */
3743#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
3744/*! @} */
3745
3746/* The count of DMIC_CHANNEL_DIVHFCLK */
3747#define DMIC_CHANNEL_DIVHFCLK_COUNT (2U)
3748
3749/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */
3750/*! @{ */
3751#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U)
3752#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U)
3753/*! COMP - Pre-emphasis filer coefficient for 2 FS mode. 0 = Compensation = 0 1 = Compensation = 16
3754 * 2 = Compensation = 15 3 = Compensation = 13
3755 */
3756#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
3757/*! @} */
3758
3759/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
3760#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U)
3761
3762/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */
3763/*! @{ */
3764#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U)
3765#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U)
3766/*! COMP - Pre-emphasis filer coefficient for 4 FS mode. 0 = Compensation = 0 1 = Compensation = 16
3767 * 2 = Compensation = 15 3 = Compensation = 13
3768 */
3769#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
3770/*! @} */
3771
3772/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
3773#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U)
3774
3775/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */
3776/*! @{ */
3777#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU)
3778#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U)
3779/*! GAIN - Gain control, as a positive or negative (two's complement) number of bits to shift.
3780 */
3781#define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
3782/*! @} */
3783
3784/* The count of DMIC_CHANNEL_GAINSHIFT */
3785#define DMIC_CHANNEL_GAINSHIFT_COUNT (2U)
3786
3787/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */
3788/*! @{ */
3789#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U)
3790#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U)
3791/*! ENABLE - FIFO enable.
3792 * 0b0..FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being
3793 * streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a
3794 * period when the data was not needed.
3795 * 0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
3796 */
3797#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
3798#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U)
3799#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U)
3800/*! RESETN - FIFO reset.
3801 * 0b0..Reset the FIFO.
3802 * 0b1..Normal operation
3803 */
3804#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
3805#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U)
3806#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U)
3807/*! INTEN - Interrupt enable.
3808 * 0b0..FIFO level interrupts are not enabled.
3809 * 0b1..FIFO level interrupts are enabled.
3810 */
3811#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
3812#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U)
3813#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U)
3814/*! DMAEN - DMA enable
3815 * 0b0..DMA requests are not enabled.
3816 * 0b1..DMA requests based on FIFO level are enabled.
3817 */
3818#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
3819#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U)
3820#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U)
3821/*! TRIGLVL - FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If
3822 * enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then
3823 * return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 =
3824 * trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has
3825 * received two entries. 15 = trigger when the FIFO has received 16 entries (has become full).
3826 */
3827#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
3828/*! @} */
3829
3830/* The count of DMIC_CHANNEL_FIFO_CTRL */
3831#define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U)
3832
3833/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */
3834/*! @{ */
3835#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U)
3836#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U)
3837/*! INT - Interrupt flag. Asserted when FIFO data reaches the level specified in the FIFOCTRL
3838 * register. Writing a one to this bit clears the flag. Remark: note that the bus clock to the DMIC
3839 * subsystem must be running in order for an interrupt to occur.
3840 */
3841#define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
3842#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U)
3843#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U)
3844/*! OVERRUN - Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one
3845 * to this bit clears the flag. This flag does not cause an interrupt.
3846 */
3847#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
3848#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U)
3849#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U)
3850/*! UNDERRUN - Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag.
3851 */
3852#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
3853/*! @} */
3854
3855/* The count of DMIC_CHANNEL_FIFO_STATUS */
3856#define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U)
3857
3858/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */
3859/*! @{ */
3860#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU)
3861#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U)
3862/*! DATA - Data from the top of the input filter FIFO.
3863 */
3864#define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
3865/*! @} */
3866
3867/* The count of DMIC_CHANNEL_FIFO_DATA */
3868#define DMIC_CHANNEL_FIFO_DATA_COUNT (2U)
3869
3870/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */
3871/*! @{ */
3872#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U)
3873#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U)
3874/*! PHY_FALL - Capture PDM_DATA
3875 * 0b0..Capture PDM_DATA on the rising edge of PDM_CLK.
3876 * 0b1..Capture PDM_DATA on the falling edge of PDM_CLK.
3877 */
3878#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
3879#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U)
3880#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U)
3881/*! PHY_HALF - Half rate sampling
3882 * 0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
3883 * 0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.
3884 */
3885#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
3886/*! @} */
3887
3888/* The count of DMIC_CHANNEL_PHY_CTRL */
3889#define DMIC_CHANNEL_PHY_CTRL_COUNT (2U)
3890
3891/*! @name CHANNEL_DC_CTRL - DC Control register 0 */
3892/*! @{ */
3893#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U)
3894#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U)
3895/*! DCPOLE - DC block filter
3896 * 0b00..Flat response, no filter.
3897 * 0b01..155 Hz.
3898 * 0b10..78 Hz.
3899 * 0b11..39 Hz
3900 */
3901#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
3902#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U)
3903#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U)
3904/*! DCGAIN - Fine gain adjustment in the form of a number of bits to downshift.
3905 */
3906#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
3907#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
3908#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
3909/*! SATURATEAT16BIT - Selects 16-bit saturation.
3910 * 0b0..Results roll over if out range and do not saturate.
3911 * 0b1..If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
3912 */
3913#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
3914/*! @} */
3915
3916/* The count of DMIC_CHANNEL_DC_CTRL */
3917#define DMIC_CHANNEL_DC_CTRL_COUNT (2U)
3918
3919/*! @name CHANEN - Channel Enable register */
3920/*! @{ */
3921#define DMIC_CHANEN_EN_CH0_MASK (0x1U)
3922#define DMIC_CHANEN_EN_CH0_SHIFT (0U)
3923/*! EN_CH0 - Enable channel 0. When 1, PDM channel 0 is enabled.
3924 */
3925#define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
3926#define DMIC_CHANEN_EN_CH1_MASK (0x2U)
3927#define DMIC_CHANEN_EN_CH1_SHIFT (1U)
3928/*! EN_CH1 - Enable channel 1. When 1, PDM channel 1 is enabled.
3929 */
3930#define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
3931/*! @} */
3932
3933/*! @name IOCFG - I/O Configuration register */
3934/*! @{ */
3935#define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U)
3936#define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U)
3937/*! CLK_BYPASS0 - Bypass CLK0. When 1, PDM_DATA1 becomes the clock for PDM channel 0. This provides
3938 * for the possibility of an external codec taking over the PDM bus.
3939 */
3940#define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)
3941#define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U)
3942#define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U)
3943/*! CLK_BYPASS1 - Bypass CLK1. When 1, PDM_DATA1 becomes the clock for PDM channel 1. This provides
3944 * for the possibility of an external codec taking over the PDM bus.
3945 */
3946#define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)
3947#define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U)
3948#define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U)
3949/*! STEREO_DATA0 - Stereo PDM select. When 1, PDM_DATA0 is routed to both PDM channels in a
3950 * configuration that supports a single stereo digital microphone.
3951 */
3952#define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)
3953/*! @} */
3954
3955/*! @name USE2FS - Use 2FS register */
3956/*! @{ */
3957#define DMIC_USE2FS_USE2FS_MASK (0x1U)
3958#define DMIC_USE2FS_USE2FS_SHIFT (0U)
3959/*! USE2FS - Use 2FS register
3960 * 0b0..Use 1FS output for PCM data.
3961 * 0b1..Use 2FS output for PCM data.
3962 */
3963#define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
3964/*! @} */
3965
3966/*! @name HWVADGAIN - HWVAD input gain register */
3967/*! @{ */
3968#define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU)
3969#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U)
3970/*! INPUTGAIN - Shift value for input bits 0x00 -10 bits 0x01 -8 bits 0x02 -6 bits 0x03 -4 bits 0x04
3971 * -2 bits 0x05 0 bits (default) 0x06 +2 bits 0x07 +4 bits 0x08 +6 bits 0x09 +8 bits 0x0A +10
3972 * bits 0x0B +12 bits 0x0C +14 bits 0x0D to 0x0F Reserved.
3973 */
3974#define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
3975/*! @} */
3976
3977/*! @name HWVADHPFS - HWVAD filter control register */
3978/*! @{ */
3979#define DMIC_HWVADHPFS_HPFS_MASK (0x3U)
3980#define DMIC_HWVADHPFS_HPFS_SHIFT (0U)
3981/*! HPFS - High pass filter
3982 * 0b00..First filter by-pass.
3983 * 0b01..High pass filter with -3dB cut-off at 1750Hz.
3984 * 0b10..High pass filter with -3dB cut-off at 215Hz.
3985 * 0b11..Reserved.
3986 */
3987#define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
3988/*! @} */
3989
3990/*! @name HWVADST10 - HWVAD control register */
3991/*! @{ */
3992#define DMIC_HWVADST10_ST10_MASK (0x1U)
3993#define DMIC_HWVADST10_ST10_SHIFT (0U)
3994/*! ST10 - Stage 0
3995 * 0b0..Normal operation, waiting for HWVAD trigger event (stage 0).
3996 * 0b1..Reset internal interrupt flag by writing a '1' pulse.
3997 */
3998#define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
3999/*! @} */
4000
4001/*! @name HWVADRSTT - HWVAD filter reset register */
4002/*! @{ */
4003#define DMIC_HWVADRSTT_RSTT_MASK (0x1U)
4004#define DMIC_HWVADRSTT_RSTT_SHIFT (0U)
4005/*! RSTT - Writing a 1 resets all filter values
4006 */
4007#define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)
4008/*! @} */
4009
4010/*! @name HWVADTHGN - HWVAD noise estimator gain register */
4011/*! @{ */
4012#define DMIC_HWVADTHGN_THGN_MASK (0xFU)
4013#define DMIC_HWVADTHGN_THGN_SHIFT (0U)
4014/*! THGN - Gain value for the noise estimator. Values 0 to 14. 0 corresponds to a gain of 1.
4015 */
4016#define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
4017/*! @} */
4018
4019/*! @name HWVADTHGS - HWVAD signal estimator gain register */
4020/*! @{ */
4021#define DMIC_HWVADTHGS_THGS_MASK (0xFU)
4022#define DMIC_HWVADTHGS_THGS_SHIFT (0U)
4023/*! THGS - Gain value for the signal estimator. Values 0 to 14. 0 corresponds to a gain of 1.
4024 */
4025#define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
4026/*! @} */
4027
4028/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */
4029/*! @{ */
4030#define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU)
4031#define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U)
4032/*! LOWZ - Noise envelope estimator value.
4033 */
4034#define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
4035/*! @} */
4036
4037/*! @name ID - Module Identification register */
4038/*! @{ */
4039#define DMIC_ID_ID_MASK (0xFFFFFFFFU)
4040#define DMIC_ID_ID_SHIFT (0U)
4041/*! ID - Indicates module ID and the number of channels in this DMIC interface.
4042 */
4043#define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)
4044/*! @} */
4045
4046
4047/*!
4048 * @}
4049 */ /* end of group DMIC_Register_Masks */
4050
4051
4052/* DMIC - Peripheral instance base addresses */
4053/** Peripheral DMIC0 base address */
4054#define DMIC0_BASE (0x40090000u)
4055/** Peripheral DMIC0 base pointer */
4056#define DMIC0 ((DMIC_Type *)DMIC0_BASE)
4057/** Array initializer of DMIC peripheral base addresses */
4058#define DMIC_BASE_ADDRS { DMIC0_BASE }
4059/** Array initializer of DMIC peripheral base pointers */
4060#define DMIC_BASE_PTRS { DMIC0 }
4061/** Interrupt vectors for the DMIC peripheral type */
4062#define DMIC_IRQS { DMIC0_IRQn }
4063#define DMIC_HWVAD_IRQS { HWVAD0_IRQn }
4064
4065/*!
4066 * @}
4067 */ /* end of group DMIC_Peripheral_Access_Layer */
4068
4069
4070/* ----------------------------------------------------------------------------
4071 -- EMC Peripheral Access Layer
4072 ---------------------------------------------------------------------------- */
4073
4074/*!
4075 * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer
4076 * @{
4077 */
4078
4079/** EMC - Register Layout Typedef */
4080typedef struct {
4081 __IO uint32_t CONTROL; /**< Controls operation of the memory controller, offset: 0x0 */
4082 __I uint32_t STATUS; /**< Provides EMC status information, offset: 0x4 */
4083 __IO uint32_t CONFIG; /**< Configures operation of the memory controller, offset: 0x8 */
4084 uint8_t RESERVED_0[20];
4085 __IO uint32_t DYNAMICCONTROL; /**< Controls dynamic memory operation, offset: 0x20 */
4086 __IO uint32_t DYNAMICREFRESH; /**< Configures dynamic memory refresh, offset: 0x24 */
4087 __IO uint32_t DYNAMICREADCONFIG; /**< Configures dynamic memory read strategy, offset: 0x28 */
4088 uint8_t RESERVED_1[4];
4089 __IO uint32_t DYNAMICRP; /**< Precharge command period, offset: 0x30 */
4090 __IO uint32_t DYNAMICRAS; /**< Active to precharge command period, offset: 0x34 */
4091 __IO uint32_t DYNAMICSREX; /**< Self-refresh exit time, offset: 0x38 */
4092 __IO uint32_t DYNAMICAPR; /**< Last-data-out to active command time, offset: 0x3C */
4093 __IO uint32_t DYNAMICDAL; /**< Data-in to active command time, offset: 0x40 */
4094 __IO uint32_t DYNAMICWR; /**< Write recovery time, offset: 0x44 */
4095 __IO uint32_t DYNAMICRC; /**< Selects the active to active command period, offset: 0x48 */
4096 __IO uint32_t DYNAMICRFC; /**< Selects the auto-refresh period, offset: 0x4C */
4097 __IO uint32_t DYNAMICXSR; /**< Time for exit self-refresh to active command, offset: 0x50 */
4098 __IO uint32_t DYNAMICRRD; /**< Latency for active bank A to active bank B, offset: 0x54 */
4099 __IO uint32_t DYNAMICMRD; /**< Time for load mode register to active command, offset: 0x58 */
4100 uint8_t RESERVED_2[36];
4101 __IO uint32_t STATICEXTENDEDWAIT; /**< Time for long static memory read and write transfers, offset: 0x80 */
4102 uint8_t RESERVED_3[124];
4103 struct { /* offset: 0x100, array step: 0x20 */
4104 __IO uint32_t DYNAMICCONFIG; /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */
4105 __IO uint32_t DYNAMICRASCAS; /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */
4106 uint8_t RESERVED_0[24];
4107 } DYNAMIC[4];
4108 uint8_t RESERVED_4[128];
4109 struct { /* offset: 0x200, array step: 0x20 */
4110 __IO uint32_t STATICCONFIG; /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */
4111 __IO uint32_t STATICWAITWEN; /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */
4112 __IO uint32_t STATICWAITOEN; /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */
4113 __IO uint32_t STATICWAITRD; /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */
4114 __IO uint32_t STATICWAITPAGE; /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */
4115 __IO uint32_t STATICWAITWR; /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */
4116 __IO uint32_t STATICWAITTURN; /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */
4117 uint8_t RESERVED_0[4];
4118 } STATIC[4];
4119} EMC_Type;
4120
4121/* ----------------------------------------------------------------------------
4122 -- EMC Register Masks
4123 ---------------------------------------------------------------------------- */
4124
4125/*!
4126 * @addtogroup EMC_Register_Masks EMC Register Masks
4127 * @{
4128 */
4129
4130/*! @name CONTROL - Controls operation of the memory controller */
4131/*! @{ */
4132#define EMC_CONTROL_E_MASK (0x1U)
4133#define EMC_CONTROL_E_SHIFT (0U)
4134/*! E - EMC Enable.
4135 */
4136#define EMC_CONTROL_E(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK)
4137#define EMC_CONTROL_M_MASK (0x2U)
4138#define EMC_CONTROL_M_SHIFT (1U)
4139/*! M - Address mirror.
4140 */
4141#define EMC_CONTROL_M(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK)
4142#define EMC_CONTROL_L_MASK (0x4U)
4143#define EMC_CONTROL_L_SHIFT (2U)
4144/*! L - Low-power mode.
4145 */
4146#define EMC_CONTROL_L(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK)
4147/*! @} */
4148
4149/*! @name STATUS - Provides EMC status information */
4150/*! @{ */
4151#define EMC_STATUS_B_MASK (0x1U)
4152#define EMC_STATUS_B_SHIFT (0U)
4153/*! B - Busy.
4154 */
4155#define EMC_STATUS_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK)
4156#define EMC_STATUS_S_MASK (0x2U)
4157#define EMC_STATUS_S_SHIFT (1U)
4158/*! S - Write buffer status.
4159 */
4160#define EMC_STATUS_S(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK)
4161#define EMC_STATUS_SA_MASK (0x4U)
4162#define EMC_STATUS_SA_SHIFT (2U)
4163/*! SA - Self-refresh acknowledge.
4164 */
4165#define EMC_STATUS_SA(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK)
4166/*! @} */
4167
4168/*! @name CONFIG - Configures operation of the memory controller */
4169/*! @{ */
4170#define EMC_CONFIG_EM_MASK (0x1U)
4171#define EMC_CONFIG_EM_SHIFT (0U)
4172/*! EM - Endian mode.
4173 */
4174#define EMC_CONFIG_EM(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK)
4175#define EMC_CONFIG_CLKR_MASK (0x100U)
4176#define EMC_CONFIG_CLKR_SHIFT (8U)
4177/*! CLKR - This bit must contain 0 for proper operation of the EMC.
4178 */
4179#define EMC_CONFIG_CLKR(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK)
4180/*! @} */
4181
4182/*! @name DYNAMICCONTROL - Controls dynamic memory operation */
4183/*! @{ */
4184#define EMC_DYNAMICCONTROL_CE_MASK (0x1U)
4185#define EMC_DYNAMICCONTROL_CE_SHIFT (0U)
4186/*! CE - Dynamic memory clock enable.
4187 */
4188#define EMC_DYNAMICCONTROL_CE(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK)
4189#define EMC_DYNAMICCONTROL_CS_MASK (0x2U)
4190#define EMC_DYNAMICCONTROL_CS_SHIFT (1U)
4191/*! CS - Dynamic memory clock control.
4192 */
4193#define EMC_DYNAMICCONTROL_CS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK)
4194#define EMC_DYNAMICCONTROL_SR_MASK (0x4U)
4195#define EMC_DYNAMICCONTROL_SR_SHIFT (2U)
4196/*! SR - Self-refresh request, EMCSREFREQ.
4197 */
4198#define EMC_DYNAMICCONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK)
4199#define EMC_DYNAMICCONTROL_MMC_MASK (0x20U)
4200#define EMC_DYNAMICCONTROL_MMC_SHIFT (5U)
4201/*! MMC - Memory clock control.
4202 */
4203#define EMC_DYNAMICCONTROL_MMC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK)
4204#define EMC_DYNAMICCONTROL_I_MASK (0x180U)
4205#define EMC_DYNAMICCONTROL_I_SHIFT (7U)
4206/*! I - SDRAM initialization.
4207 */
4208#define EMC_DYNAMICCONTROL_I(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK)
4209/*! @} */
4210
4211/*! @name DYNAMICREFRESH - Configures dynamic memory refresh */
4212/*! @{ */
4213#define EMC_DYNAMICREFRESH_REFRESH_MASK (0x7FFU)
4214#define EMC_DYNAMICREFRESH_REFRESH_SHIFT (0U)
4215/*! REFRESH - Refresh timer.
4216 */
4217#define EMC_DYNAMICREFRESH_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK)
4218/*! @} */
4219
4220/*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */
4221/*! @{ */
4222#define EMC_DYNAMICREADCONFIG_RD_MASK (0x3U)
4223#define EMC_DYNAMICREADCONFIG_RD_SHIFT (0U)
4224/*! RD - Read data strategy.
4225 */
4226#define EMC_DYNAMICREADCONFIG_RD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK)
4227/*! @} */
4228
4229/*! @name DYNAMICRP - Precharge command period */
4230/*! @{ */
4231#define EMC_DYNAMICRP_TRP_MASK (0xFU)
4232#define EMC_DYNAMICRP_TRP_SHIFT (0U)
4233/*! TRP - Precharge command period.
4234 */
4235#define EMC_DYNAMICRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK)
4236/*! @} */
4237
4238/*! @name DYNAMICRAS - Active to precharge command period */
4239/*! @{ */
4240#define EMC_DYNAMICRAS_TRAS_MASK (0xFU)
4241#define EMC_DYNAMICRAS_TRAS_SHIFT (0U)
4242/*! TRAS - Active to precharge command period.
4243 */
4244#define EMC_DYNAMICRAS_TRAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK)
4245/*! @} */
4246
4247/*! @name DYNAMICSREX - Self-refresh exit time */
4248/*! @{ */
4249#define EMC_DYNAMICSREX_TSREX_MASK (0xFU)
4250#define EMC_DYNAMICSREX_TSREX_SHIFT (0U)
4251/*! TSREX - Self-refresh exit time.
4252 */
4253#define EMC_DYNAMICSREX_TSREX(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK)
4254/*! @} */
4255
4256/*! @name DYNAMICAPR - Last-data-out to active command time */
4257/*! @{ */
4258#define EMC_DYNAMICAPR_TAPR_MASK (0xFU)
4259#define EMC_DYNAMICAPR_TAPR_SHIFT (0U)
4260/*! TAPR - Last-data-out to active command time.
4261 */
4262#define EMC_DYNAMICAPR_TAPR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK)
4263/*! @} */
4264
4265/*! @name DYNAMICDAL - Data-in to active command time */
4266/*! @{ */
4267#define EMC_DYNAMICDAL_TDAL_MASK (0xFU)
4268#define EMC_DYNAMICDAL_TDAL_SHIFT (0U)
4269/*! TDAL - Data-in to active command.
4270 */
4271#define EMC_DYNAMICDAL_TDAL(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK)
4272/*! @} */
4273
4274/*! @name DYNAMICWR - Write recovery time */
4275/*! @{ */
4276#define EMC_DYNAMICWR_TWR_MASK (0xFU)
4277#define EMC_DYNAMICWR_TWR_SHIFT (0U)
4278/*! TWR - Write recovery time.
4279 */
4280#define EMC_DYNAMICWR_TWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK)
4281/*! @} */
4282
4283/*! @name DYNAMICRC - Selects the active to active command period */
4284/*! @{ */
4285#define EMC_DYNAMICRC_TRC_MASK (0x1FU)
4286#define EMC_DYNAMICRC_TRC_SHIFT (0U)
4287/*! TRC - Active to active command period.
4288 */
4289#define EMC_DYNAMICRC_TRC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK)
4290/*! @} */
4291
4292/*! @name DYNAMICRFC - Selects the auto-refresh period */
4293/*! @{ */
4294#define EMC_DYNAMICRFC_TRFC_MASK (0x1FU)
4295#define EMC_DYNAMICRFC_TRFC_SHIFT (0U)
4296/*! TRFC - Auto-refresh period and auto-refresh to active command period.
4297 */
4298#define EMC_DYNAMICRFC_TRFC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK)
4299/*! @} */
4300
4301/*! @name DYNAMICXSR - Time for exit self-refresh to active command */
4302/*! @{ */
4303#define EMC_DYNAMICXSR_TXSR_MASK (0x1FU)
4304#define EMC_DYNAMICXSR_TXSR_SHIFT (0U)
4305/*! TXSR - Exit self-refresh to active command time.
4306 */
4307#define EMC_DYNAMICXSR_TXSR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK)
4308/*! @} */
4309
4310/*! @name DYNAMICRRD - Latency for active bank A to active bank B */
4311/*! @{ */
4312#define EMC_DYNAMICRRD_TRRD_MASK (0xFU)
4313#define EMC_DYNAMICRRD_TRRD_SHIFT (0U)
4314/*! TRRD - Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles.
4315 */
4316#define EMC_DYNAMICRRD_TRRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK)
4317/*! @} */
4318
4319/*! @name DYNAMICMRD - Time for load mode register to active command */
4320/*! @{ */
4321#define EMC_DYNAMICMRD_TMRD_MASK (0xFU)
4322#define EMC_DYNAMICMRD_TMRD_SHIFT (0U)
4323/*! TMRD - Load mode register to active command time.
4324 */
4325#define EMC_DYNAMICMRD_TMRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK)
4326/*! @} */
4327
4328/*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */
4329/*! @{ */
4330#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU)
4331#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U)
4332/*! EXTENDEDWAIT - Extended wait time out.
4333 */
4334#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK)
4335/*! @} */
4336
4337/*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */
4338/*! @{ */
4339#define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK (0x18U)
4340#define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT (3U)
4341/*! MD - Memory device.
4342 */
4343#define EMC_DYNAMIC_DYNAMICCONFIG_MD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK)
4344#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK (0x1F80U)
4345#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT (7U)
4346/*! AM0 - See Table 933.
4347 */
4348#define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK)
4349#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK (0x4000U)
4350#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT (14U)
4351/*! AM1 - See Table 933.
4352 */
4353#define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
4354#define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK (0x80000U)
4355#define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT (19U)
4356/*! B - Buffer enable.
4357 */
4358#define EMC_DYNAMIC_DYNAMICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK)
4359#define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK (0x100000U)
4360#define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT (20U)
4361/*! P - Write protect.
4362 */
4363#define EMC_DYNAMIC_DYNAMICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK)
4364/*! @} */
4365
4366/* The count of EMC_DYNAMIC_DYNAMICCONFIG */
4367#define EMC_DYNAMIC_DYNAMICCONFIG_COUNT (4U)
4368
4369/*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */
4370/*! @{ */
4371#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK (0x3U)
4372#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT (0U)
4373/*! RAS - RAS latency (active to read/write delay).
4374 */
4375#define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK)
4376#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK (0x300U)
4377#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT (8U)
4378/*! CAS - CAS latency.
4379 */
4380#define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK)
4381/*! @} */
4382
4383/* The count of EMC_DYNAMIC_DYNAMICRASCAS */
4384#define EMC_DYNAMIC_DYNAMICRASCAS_COUNT (4U)
4385
4386/*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */
4387/*! @{ */
4388#define EMC_STATIC_STATICCONFIG_MW_MASK (0x3U)
4389#define EMC_STATIC_STATICCONFIG_MW_SHIFT (0U)
4390/*! MW - Memory width.
4391 */
4392#define EMC_STATIC_STATICCONFIG_MW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK)
4393#define EMC_STATIC_STATICCONFIG_PM_MASK (0x8U)
4394#define EMC_STATIC_STATICCONFIG_PM_SHIFT (3U)
4395/*! PM - Page mode.
4396 */
4397#define EMC_STATIC_STATICCONFIG_PM(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK)
4398#define EMC_STATIC_STATICCONFIG_PC_MASK (0x40U)
4399#define EMC_STATIC_STATICCONFIG_PC_SHIFT (6U)
4400/*! PC - Chip select polarity.
4401 */
4402#define EMC_STATIC_STATICCONFIG_PC(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK)
4403#define EMC_STATIC_STATICCONFIG_PB_MASK (0x80U)
4404#define EMC_STATIC_STATICCONFIG_PB_SHIFT (7U)
4405/*! PB - Byte lane state.
4406 */
4407#define EMC_STATIC_STATICCONFIG_PB(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK)
4408#define EMC_STATIC_STATICCONFIG_EW_MASK (0x100U)
4409#define EMC_STATIC_STATICCONFIG_EW_SHIFT (8U)
4410/*! EW - Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write
4411 * transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.
4412 */
4413#define EMC_STATIC_STATICCONFIG_EW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK)
4414#define EMC_STATIC_STATICCONFIG_B_MASK (0x80000U)
4415#define EMC_STATIC_STATICCONFIG_B_SHIFT (19U)
4416/*! B - Buffer enable [2].
4417 */
4418#define EMC_STATIC_STATICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK)
4419#define EMC_STATIC_STATICCONFIG_P_MASK (0x100000U)
4420#define EMC_STATIC_STATICCONFIG_P_SHIFT (20U)
4421/*! P - Write protect.
4422 */
4423#define EMC_STATIC_STATICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK)
4424/*! @} */
4425
4426/* The count of EMC_STATIC_STATICCONFIG */
4427#define EMC_STATIC_STATICCONFIG_COUNT (4U)
4428
4429/*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */
4430/*! @{ */
4431#define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK (0xFU)
4432#define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT (0U)
4433/*! WAITWEN - Wait write enable.
4434 */
4435#define EMC_STATIC_STATICWAITWEN_WAITWEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK)
4436/*! @} */
4437
4438/* The count of EMC_STATIC_STATICWAITWEN */
4439#define EMC_STATIC_STATICWAITWEN_COUNT (4U)
4440
4441/*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */
4442/*! @{ */
4443#define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK (0xFU)
4444#define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT (0U)
4445/*! WAITOEN - Wait output enable.
4446 */
4447#define EMC_STATIC_STATICWAITOEN_WAITOEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK)
4448/*! @} */
4449
4450/* The count of EMC_STATIC_STATICWAITOEN */
4451#define EMC_STATIC_STATICWAITOEN_COUNT (4U)
4452
4453/*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */
4454/*! @{ */
4455#define EMC_STATIC_STATICWAITRD_WAITRD_MASK (0x1FU)
4456#define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT (0U)
4457/*! WAITRD - .
4458 */
4459#define EMC_STATIC_STATICWAITRD_WAITRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK)
4460/*! @} */
4461
4462/* The count of EMC_STATIC_STATICWAITRD */
4463#define EMC_STATIC_STATICWAITRD_COUNT (4U)
4464
4465/*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */
4466/*! @{ */
4467#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK (0x1FU)
4468#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U)
4469/*! WAITPAGE - Asynchronous page mode read after the first read wait states.
4470 */
4471#define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK)
4472/*! @} */
4473
4474/* The count of EMC_STATIC_STATICWAITPAGE */
4475#define EMC_STATIC_STATICWAITPAGE_COUNT (4U)
4476
4477/*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */
4478/*! @{ */
4479#define EMC_STATIC_STATICWAITWR_WAITWR_MASK (0x1FU)
4480#define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT (0U)
4481/*! WAITWR - Write wait states.
4482 */
4483#define EMC_STATIC_STATICWAITWR_WAITWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK)
4484/*! @} */
4485
4486/* The count of EMC_STATIC_STATICWAITWR */
4487#define EMC_STATIC_STATICWAITWR_COUNT (4U)
4488
4489/*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */
4490/*! @{ */
4491#define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK (0xFU)
4492#define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U)
4493/*! WAITTURN - Bus turn-around cycles.
4494 */
4495#define EMC_STATIC_STATICWAITTURN_WAITTURN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK)
4496/*! @} */
4497
4498/* The count of EMC_STATIC_STATICWAITTURN */
4499#define EMC_STATIC_STATICWAITTURN_COUNT (4U)
4500
4501
4502/*!
4503 * @}
4504 */ /* end of group EMC_Register_Masks */
4505
4506
4507/* EMC - Peripheral instance base addresses */
4508/** Peripheral EMC base address */
4509#define EMC_BASE (0x40081000u)
4510/** Peripheral EMC base pointer */
4511#define EMC ((EMC_Type *)EMC_BASE)
4512/** Array initializer of EMC peripheral base addresses */
4513#define EMC_BASE_ADDRS { EMC_BASE }
4514/** Array initializer of EMC peripheral base pointers */
4515#define EMC_BASE_PTRS { EMC }
4516
4517/*!
4518 * @}
4519 */ /* end of group EMC_Peripheral_Access_Layer */
4520
4521
4522/* ----------------------------------------------------------------------------
4523 -- ENET Peripheral Access Layer
4524 ---------------------------------------------------------------------------- */
4525
4526/*!
4527 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
4528 * @{
4529 */
4530
4531/** ENET - Register Layout Typedef */
4532typedef struct {
4533 __IO uint32_t MAC_CONFIG; /**< MAC configuration register, offset: 0x0 */
4534 __IO uint32_t MAC_EXT_CONFIG; /**< , offset: 0x4 */
4535 __IO uint32_t MAC_FRAME_FILTER; /**< MAC frame filter register, offset: 0x8 */
4536 __IO uint32_t MAC_WD_TIMEROUT; /**< MAC watchdog Timeout register, offset: 0xC */
4537 uint8_t RESERVED_0[64];
4538 __IO uint32_t MAC_VLAN_TAG; /**< MAC vlan tag register, offset: 0x50 */
4539 uint8_t RESERVED_1[28];
4540 __IO uint32_t MAC_TX_FLOW_CTRL_Q[2]; /**< Transmit flow control register, array offset: 0x70, array step: 0x4 */
4541 uint8_t RESERVED_2[24];
4542 __IO uint32_t MAC_RX_FLOW_CTRL; /**< Receive flow control register, offset: 0x90 */
4543 uint8_t RESERVED_3[4];
4544 __IO uint32_t MAC_TXQ_PRIO_MAP; /**< , offset: 0x98 */
4545 uint8_t RESERVED_4[4];
4546 __IO uint32_t MAC_RXQ_CTRL[3]; /**< Receive Queue Control 0 register 0x0000, array offset: 0xA0, array step: 0x4 */
4547 uint8_t RESERVED_5[4];
4548 __I uint32_t MAC_INTR_STAT; /**< Interrupt status register 0x0000, offset: 0xB0 */
4549 __IO uint32_t MAC_INTR_EN; /**< Interrupt enable register 0x0000, offset: 0xB4 */
4550 __I uint32_t MAC_RXTX_STAT; /**< Receive Transmit Status register, offset: 0xB8 */
4551 uint8_t RESERVED_6[4];
4552 __IO uint32_t MAC_PMT_CRTL_STAT; /**< , offset: 0xC0 */
4553 __IO uint32_t MAC_RWAKE_FRFLT; /**< Remote wake-up frame filter, offset: 0xC4 */
4554 uint8_t RESERVED_7[8];
4555 __IO uint32_t MAC_LPI_CTRL_STAT; /**< LPI Control and Status Register, offset: 0xD0 */
4556 __IO uint32_t MAC_LPI_TIMER_CTRL; /**< LPI Timers Control register, offset: 0xD4 */
4557 __IO uint32_t MAC_LPI_ENTR_TIMR; /**< LPI entry Timer register, offset: 0xD8 */
4558 __IO uint32_t MAC_1US_TIC_COUNTR; /**< , offset: 0xDC */
4559 uint8_t RESERVED_8[48];
4560 __I uint32_t MAC_VERSION; /**< MAC version register, offset: 0x110 */
4561 __I uint32_t MAC_DBG; /**< MAC debug register, offset: 0x114 */
4562 uint8_t RESERVED_9[4];
4563 __I uint32_t MAC_HW_FEAT[3]; /**< MAC hardware feature register 0x0201, array offset: 0x11C, array step: 0x4 */
4564 uint8_t RESERVED_10[216];
4565 __IO uint32_t MAC_MDIO_ADDR; /**< MIDO address Register, offset: 0x200 */
4566 __IO uint32_t MAC_MDIO_DATA; /**< MDIO Data register, offset: 0x204 */
4567 uint8_t RESERVED_11[248];
4568 __IO uint32_t MAC_ADDR_HIGH; /**< MAC address0 high register, offset: 0x300 */
4569 __IO uint32_t MAC_ADDR_LOW; /**< MAC address0 low register, offset: 0x304 */
4570 uint8_t RESERVED_12[2040];
4571 __IO uint32_t MAC_TIMESTAMP_CTRL; /**< Time stamp control register, offset: 0xB00 */
4572 __IO uint32_t MAC_SUB_SCND_INCR; /**< Sub-second increment register, offset: 0xB04 */
4573 __I uint32_t MAC_SYS_TIME_SCND; /**< System time seconds register, offset: 0xB08 */
4574 __I uint32_t MAC_SYS_TIME_NSCND; /**< System time nanoseconds register, offset: 0xB0C */
4575 __IO uint32_t MAC_SYS_TIME_SCND_UPD; /**< , offset: 0xB10 */
4576 __IO uint32_t MAC_SYS_TIME_NSCND_UPD; /**< , offset: 0xB14 */
4577 __IO uint32_t MAC_SYS_TIMESTMP_ADDEND; /**< Time stamp addend register, offset: 0xB18 */
4578 __IO uint32_t MAC_SYS_TIME_HWORD_SCND; /**< , offset: 0xB1C */
4579 __I uint32_t MAC_SYS_TIMESTMP_STAT; /**< Time stamp status register, offset: 0xB20 */
4580 uint8_t RESERVED_13[12];
4581 __I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Tx timestamp status nanoseconds, offset: 0xB30 */
4582 __I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< Tx timestamp status seconds, offset: 0xB34 */
4583 uint8_t RESERVED_14[32];
4584 __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp ingress correction, offset: 0xB58 */
4585 __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp egress correction, offset: 0xB5C */
4586 uint8_t RESERVED_15[160];
4587 __IO uint32_t MTL_OP_MODE; /**< MTL Operation Mode Register, offset: 0xC00 */
4588 uint8_t RESERVED_16[28];
4589 __I uint32_t MTL_INTR_STAT; /**< MTL Interrupt Status register, offset: 0xC20 */
4590 uint8_t RESERVED_17[12];
4591 __IO uint32_t MTL_RXQ_DMA_MAP; /**< MTL Receive Queue and DMA Channel Mapping register, offset: 0xC30 */
4592 uint8_t RESERVED_18[204];
4593 struct { /* offset: 0xD00, array step: 0x40 */
4594 __IO uint32_t MTL_TXQX_OP_MODE; /**< MTL TxQx Operation Mode register, array offset: 0xD00, array step: 0x40 */
4595 __I uint32_t MTL_TXQX_UNDRFLW; /**< MTL TxQx Underflow register, array offset: 0xD04, array step: 0x40 */
4596 __I uint32_t MTL_TXQX_DBG; /**< MTL TxQx Debug register, array offset: 0xD08, array step: 0x40 */
4597 uint8_t RESERVED_0[4];
4598 __IO uint32_t MTL_TXQX_ETS_CTRL; /**< MTL TxQx ETS control register, only TxQ1 support, array offset: 0xD10, array step: 0x40 */
4599 __I uint32_t MTL_TXQX_ETS_STAT; /**< MTL TxQx ETS Status register, array offset: 0xD14, array step: 0x40 */
4600 __IO uint32_t MTL_TXQX_QNTM_WGHT; /**< , array offset: 0xD18, array step: 0x40 */
4601 __IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< MTL TxQx SendSlopCredit register, only TxQ1 support, array offset: 0xD1C, array step: 0x40 */
4602 __IO uint32_t MTL_TXQX_HI_CRDT; /**< MTL TxQx hiCredit register, only TxQ1 support, array offset: 0xD20, array step: 0x40 */
4603 __IO uint32_t MTL_TXQX_LO_CRDT; /**< MTL TxQx loCredit register, only TxQ1 support, array offset: 0xD24, array step: 0x40 */
4604 uint8_t RESERVED_1[4];
4605 __IO uint32_t MTL_TXQX_INTCTRL_STAT; /**< , array offset: 0xD2C, array step: 0x40 */
4606 __IO uint32_t MTL_RXQX_OP_MODE; /**< MTL RxQx Operation Mode register, array offset: 0xD30, array step: 0x40 */
4607 __I uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< MTL RxQx Missed Packet Overflow Counter register, array offset: 0xD34, array step: 0x40 */
4608 __I uint32_t MTL_RXQX_DBG; /**< MTL RxQx Debug register, array offset: 0xD38, array step: 0x40 */
4609 __IO uint32_t MTL_RXQX_CTRL; /**< MTL RxQx Control register, array offset: 0xD3C, array step: 0x40 */
4610 } MTL_QUEUE[2];
4611 uint8_t RESERVED_19[640];
4612 __IO uint32_t DMA_MODE; /**< DMA mode register, offset: 0x1000 */
4613 __IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus mode, offset: 0x1004 */
4614 __IO uint32_t DMA_INTR_STAT; /**< DMA Interrupt status, offset: 0x1008 */
4615 __I uint32_t DMA_DBG_STAT; /**< DMA Debug Status, offset: 0x100C */
4616 uint8_t RESERVED_20[240];
4617 struct { /* offset: 0x1100, array step: 0x80 */
4618 __IO uint32_t DMA_CHX_CTRL; /**< DMA Channelx Control, array offset: 0x1100, array step: 0x80 */
4619 __IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channelx Transmit Control, array offset: 0x1104, array step: 0x80 */
4620 __IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channelx Receive Control, array offset: 0x1108, array step: 0x80 */
4621 uint8_t RESERVED_0[8];
4622 __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< , array offset: 0x1114, array step: 0x80 */
4623 uint8_t RESERVED_1[4];
4624 __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< , array offset: 0x111C, array step: 0x80 */
4625 __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< , array offset: 0x1120, array step: 0x80 */
4626 uint8_t RESERVED_2[4];
4627 __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< , array offset: 0x1128, array step: 0x80 */
4628 __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< , array offset: 0x112C, array step: 0x80 */
4629 __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH; /**< Channelx Rx descriptor Ring Length, array offset: 0x1130, array step: 0x80 */
4630 __IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1134, array step: 0x80 */
4631 __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
4632 __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
4633 uint8_t RESERVED_3[4];
4634 __I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< Channelx Current Host Transmit descriptor, array offset: 0x1144, array step: 0x80 */
4635 uint8_t RESERVED_4[4];
4636 __I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< , array offset: 0x114C, array step: 0x80 */
4637 uint8_t RESERVED_5[4];
4638 __I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< , array offset: 0x1154, array step: 0x80 */
4639 uint8_t RESERVED_6[4];
4640 __I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< Channelx Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
4641 __IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: 0x1160, array step: 0x80 */
4642 uint8_t RESERVED_7[8];
4643 __IO uint32_t DMA_CHX_MISS_FRAME_CNT; /**< Channelx missed frame count., array offset: 0x116C, array step: 0x80 */
4644 uint8_t RESERVED_8[16];
4645 } DMA_CH[2];
4646} ENET_Type;
4647
4648/* ----------------------------------------------------------------------------
4649 -- ENET Register Masks
4650 ---------------------------------------------------------------------------- */
4651
4652/*!
4653 * @addtogroup ENET_Register_Masks ENET Register Masks
4654 * @{
4655 */
4656
4657/*! @name MAC_CONFIG - MAC configuration register */
4658/*! @{ */
4659#define ENET_MAC_CONFIG_RE_MASK (0x1U)
4660#define ENET_MAC_CONFIG_RE_SHIFT (0U)
4661/*! RE - Receiver Enable When this bit is set, the receiver state machine of the MAC is enabled for
4662 * receiving frames from the MII.
4663 */
4664#define ENET_MAC_CONFIG_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_RE_SHIFT)) & ENET_MAC_CONFIG_RE_MASK)
4665#define ENET_MAC_CONFIG_TE_MASK (0x2U)
4666#define ENET_MAC_CONFIG_TE_SHIFT (1U)
4667/*! TE - Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII.
4668 */
4669#define ENET_MAC_CONFIG_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_TE_SHIFT)) & ENET_MAC_CONFIG_TE_MASK)
4670#define ENET_MAC_CONFIG_PRELEN_MASK (0xCU)
4671#define ENET_MAC_CONFIG_PRELEN_SHIFT (2U)
4672/*! PRELEN - Preamble Length for Transmit packets These bits control the number of preamble bytes
4673 * that are added to the beginning of every Tx packet.
4674 */
4675#define ENET_MAC_CONFIG_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PRELEN_SHIFT)) & ENET_MAC_CONFIG_PRELEN_MASK)
4676#define ENET_MAC_CONFIG_DC_MASK (0x10U)
4677#define ENET_MAC_CONFIG_DC_SHIFT (4U)
4678/*! DC - Deferral Check When this bit is set, the deferral check function is enabled in the MAC.
4679 */
4680#define ENET_MAC_CONFIG_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DC_SHIFT)) & ENET_MAC_CONFIG_DC_MASK)
4681#define ENET_MAC_CONFIG_BL_MASK (0x60U)
4682#define ENET_MAC_CONFIG_BL_SHIFT (5U)
4683/*! BL - Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time
4684 * delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before
4685 * rescheduling a transmission attempt during retries after a collision.
4686 */
4687#define ENET_MAC_CONFIG_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BL_SHIFT)) & ENET_MAC_CONFIG_BL_MASK)
4688#define ENET_MAC_CONFIG_DR_MASK (0x100U)
4689#define ENET_MAC_CONFIG_DR_SHIFT (8U)
4690/*! DR - Disable Retry When this bit is set, the MAC will attempt only one transmission.
4691 */
4692#define ENET_MAC_CONFIG_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DR_SHIFT)) & ENET_MAC_CONFIG_DR_MASK)
4693#define ENET_MAC_CONFIG_DCRS_MASK (0x200U)
4694#define ENET_MAC_CONFIG_DCRS_SHIFT (9U)
4695/*! DCRS - Disable Carrier Sense During Transmission When this bit is set, the MAC transmitter
4696 * ignores the MII CRS signal during packet transmission in the half-duplex mode.
4697 */
4698#define ENET_MAC_CONFIG_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DCRS_SHIFT)) & ENET_MAC_CONFIG_DCRS_MASK)
4699#define ENET_MAC_CONFIG_DO_MASK (0x400U)
4700#define ENET_MAC_CONFIG_DO_SHIFT (10U)
4701/*! DO - Disable Receive Own When this bit is set, the MAC disables the reception of frames when the
4702 * gmii_txen_o is asserted in Half-Duplex mode.
4703 */
4704#define ENET_MAC_CONFIG_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DO_SHIFT)) & ENET_MAC_CONFIG_DO_MASK)
4705#define ENET_MAC_CONFIG_ECRSFD_MASK (0x800U)
4706#define ENET_MAC_CONFIG_ECRSFD_SHIFT (11U)
4707/*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set, the
4708 * MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode.
4709 */
4710#define ENET_MAC_CONFIG_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ECRSFD_SHIFT)) & ENET_MAC_CONFIG_ECRSFD_MASK)
4711#define ENET_MAC_CONFIG_LM_MASK (0x1000U)
4712#define ENET_MAC_CONFIG_LM_SHIFT (12U)
4713/*! LM - Loopback Mode When this bit is set, the MAC operates in loopback mode at MII.
4714 */
4715#define ENET_MAC_CONFIG_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_LM_SHIFT)) & ENET_MAC_CONFIG_LM_MASK)
4716#define ENET_MAC_CONFIG_DM_MASK (0x2000U)
4717#define ENET_MAC_CONFIG_DM_SHIFT (13U)
4718/*! DM - Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can
4719 * transmit and receive simultaneously.
4720 */
4721#define ENET_MAC_CONFIG_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DM_SHIFT)) & ENET_MAC_CONFIG_DM_MASK)
4722#define ENET_MAC_CONFIG_FES_MASK (0x4000U)
4723#define ENET_MAC_CONFIG_FES_SHIFT (14U)
4724/*! FES - Speed Indicates the speed in Fast Ethernet (MII) mode: This bit is reserved (RO) by
4725 * default and is enabled only when RMII/SMII is enabled during configuration.
4726 */
4727#define ENET_MAC_CONFIG_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_FES_SHIFT)) & ENET_MAC_CONFIG_FES_MASK)
4728#define ENET_MAC_CONFIG_PS_MASK (0x8000U)
4729#define ENET_MAC_CONFIG_PS_SHIFT (15U)
4730/*! PS - Portselect.
4731 */
4732#define ENET_MAC_CONFIG_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PS_SHIFT)) & ENET_MAC_CONFIG_PS_MASK)
4733#define ENET_MAC_CONFIG_JE_MASK (0x10000U)
4734#define ENET_MAC_CONFIG_JE_SHIFT (16U)
4735/*! JE - Jumbo Frame Enable When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022
4736 * bytes for tagged frames) without reporting a giant frame error in the receive frame status.
4737 */
4738#define ENET_MAC_CONFIG_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JE_SHIFT)) & ENET_MAC_CONFIG_JE_MASK)
4739#define ENET_MAC_CONFIG_JD_MASK (0x20000U)
4740#define ENET_MAC_CONFIG_JD_SHIFT (17U)
4741/*! JD - Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter,
4742 * and can transfer frames of up to 16,384 bytes.
4743 */
4744#define ENET_MAC_CONFIG_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JD_SHIFT)) & ENET_MAC_CONFIG_JD_MASK)
4745#define ENET_MAC_CONFIG_BE_MASK (0x40000U)
4746#define ENET_MAC_CONFIG_BE_SHIFT (18U)
4747/*! BE - Packet Burst Enable When this bit is set, the MAC allows packet bursting during
4748 * transmission in the MII half-duplex mode.
4749 */
4750#define ENET_MAC_CONFIG_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BE_SHIFT)) & ENET_MAC_CONFIG_BE_MASK)
4751#define ENET_MAC_CONFIG_WD_MASK (0x80000U)
4752#define ENET_MAC_CONFIG_WD_SHIFT (19U)
4753/*! WD - Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver,
4754 * and can receive frames of up to 16,384 bytes.
4755 */
4756#define ENET_MAC_CONFIG_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_WD_SHIFT)) & ENET_MAC_CONFIG_WD_MASK)
4757#define ENET_MAC_CONFIG_ACS_MASK (0x100000U)
4758#define ENET_MAC_CONFIG_ACS_SHIFT (20U)
4759/*! ACS - Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field
4760 * on the incoming packets only if the value of the length field is less than 1,536 bytes.
4761 */
4762#define ENET_MAC_CONFIG_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ACS_SHIFT)) & ENET_MAC_CONFIG_ACS_MASK)
4763#define ENET_MAC_CONFIG_CST_MASK (0x200000U)
4764#define ENET_MAC_CONFIG_CST_SHIFT (21U)
4765/*! CST - CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all
4766 * packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding
4767 * the packet to the application.
4768 */
4769#define ENET_MAC_CONFIG_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_CST_SHIFT)) & ENET_MAC_CONFIG_CST_MASK)
4770#define ENET_MAC_CONFIG_S2KP_MASK (0x400000U)
4771#define ENET_MAC_CONFIG_S2KP_SHIFT (22U)
4772/*! S2KP - IEEE 802.
4773 */
4774#define ENET_MAC_CONFIG_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_S2KP_SHIFT)) & ENET_MAC_CONFIG_S2KP_MASK)
4775#define ENET_MAC_CONFIG_GPSLCE_MASK (0x800000U)
4776#define ENET_MAC_CONFIG_GPSLCE_SHIFT (23U)
4777/*! GPSLCE - Giant Packet Size Limit Control Enable When this bit is set, the MAC considers the
4778 * value in GPSL field in MAC Ext Configuration register to declare a received packet as Giant packet.
4779 */
4780#define ENET_MAC_CONFIG_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_GPSLCE_SHIFT)) & ENET_MAC_CONFIG_GPSLCE_MASK)
4781#define ENET_MAC_CONFIG_IPG_MASK (0x7000000U)
4782#define ENET_MAC_CONFIG_IPG_SHIFT (24U)
4783/*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission.
4784 */
4785#define ENET_MAC_CONFIG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPG_SHIFT)) & ENET_MAC_CONFIG_IPG_MASK)
4786#define ENET_MAC_CONFIG_IPC_MASK (0x8000000U)
4787#define ENET_MAC_CONFIG_IPC_SHIFT (27U)
4788/*! IPC - Checksum Offload When set, this bit enables the IPv4 header checksum checking and IPv4 or
4789 * IPv6 TCP, UDP, or ICMP payload checksum checking.
4790 */
4791#define ENET_MAC_CONFIG_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPC_SHIFT)) & ENET_MAC_CONFIG_IPC_MASK)
4792/*! @} */
4793
4794/*! @name MAC_EXT_CONFIG - */
4795/*! @{ */
4796#define ENET_MAC_EXT_CONFIG_GPSL_MASK (0x3FFFU)
4797#define ENET_MAC_EXT_CONFIG_GPSL_SHIFT (0U)
4798/*! GPSL - Giant Packet Size Limit If the received packet size is greater than the value programmed
4799 * in this field in units of bytes, the MAC declares the received packet as Giant packet.
4800 */
4801#define ENET_MAC_EXT_CONFIG_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIG_GPSL_MASK)
4802#define ENET_MAC_EXT_CONFIG_DCRCC_MASK (0x10000U)
4803#define ENET_MAC_EXT_CONFIG_DCRCC_SHIFT (16U)
4804/*! DCRCC - Disable CRC Checking for Received Packets When this bit is set, the MAC receiver does
4805 * not check the CRC field in the received packets.
4806 */
4807#define ENET_MAC_EXT_CONFIG_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIG_DCRCC_MASK)
4808#define ENET_MAC_EXT_CONFIG_SPEN_MASK (0x20000U)
4809#define ENET_MAC_EXT_CONFIG_SPEN_SHIFT (17U)
4810/*! SPEN - Slow Protocol Detection Enable When this bit is set, MAC processes the Slow Protocol
4811 * packets (Ether Type 0x8809) and provides the Rx status.
4812 */
4813#define ENET_MAC_EXT_CONFIG_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIG_SPEN_MASK)
4814#define ENET_MAC_EXT_CONFIG_USP_MASK (0x40000U)
4815#define ENET_MAC_EXT_CONFIG_USP_SHIFT (18U)
4816/*! USP - Unicast Slow Protocol Packet Detect When this bit is set, the MAC detects the Slow
4817 * Protocol packets with unicast address of the station specified in the MAC Address High Table 747 and
4818 * MAC Address Low Table 748 registers.
4819 */
4820#define ENET_MAC_EXT_CONFIG_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_USP_SHIFT)) & ENET_MAC_EXT_CONFIG_USP_MASK)
4821/*! @} */
4822
4823/*! @name MAC_FRAME_FILTER - MAC frame filter register */
4824/*! @{ */
4825#define ENET_MAC_FRAME_FILTER_PR_MASK (0x1U)
4826#define ENET_MAC_FRAME_FILTER_PR_SHIFT (0U)
4827/*! PR - Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frames
4828 * regardless of its destination or source address.
4829 */
4830#define ENET_MAC_FRAME_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PR_SHIFT)) & ENET_MAC_FRAME_FILTER_PR_MASK)
4831#define ENET_MAC_FRAME_FILTER_DAIF_MASK (0x8U)
4832#define ENET_MAC_FRAME_FILTER_DAIF_SHIFT (3U)
4833/*! DAIF - DA Inverse Filtering When this bit is set, the Address Check block operates in inverse
4834 * filtering mode for the DA address comparison for both unicast and multicast frames.
4835 */
4836#define ENET_MAC_FRAME_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_DAIF_MASK)
4837#define ENET_MAC_FRAME_FILTER_PM_MASK (0x10U)
4838#define ENET_MAC_FRAME_FILTER_PM_SHIFT (4U)
4839/*! PM - Pass All Multicast When set, this bit indicates that all received frames with a multicast
4840 * destination address (first bit in the destination address field is '1') are passed.
4841 */
4842#define ENET_MAC_FRAME_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PM_SHIFT)) & ENET_MAC_FRAME_FILTER_PM_MASK)
4843#define ENET_MAC_FRAME_FILTER_DBF_MASK (0x20U)
4844#define ENET_MAC_FRAME_FILTER_DBF_SHIFT (5U)
4845/*! DBF - Disable Broadcast Frames When this bit is set, the AFM module filters all incoming broadcast frames.
4846 */
4847#define ENET_MAC_FRAME_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DBF_SHIFT)) & ENET_MAC_FRAME_FILTER_DBF_MASK)
4848#define ENET_MAC_FRAME_FILTER_PCF_MASK (0xC0U)
4849#define ENET_MAC_FRAME_FILTER_PCF_SHIFT (6U)
4850/*! PCF - Pass Control Frames These bits control the forwarding of all control frames (including
4851 * unicast and multicast PAUSE frames).
4852 */
4853#define ENET_MAC_FRAME_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PCF_SHIFT)) & ENET_MAC_FRAME_FILTER_PCF_MASK)
4854#define ENET_MAC_FRAME_FILTER_SAIF_MASK (0x100U)
4855#define ENET_MAC_FRAME_FILTER_SAIF_SHIFT (8U)
4856/*! SAIF - SA Inverse Filtering When this bit is set, the Address Check block operates in the
4857 * inverse filtering mode for SA address comparison.
4858 */
4859#define ENET_MAC_FRAME_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAIF_MASK)
4860#define ENET_MAC_FRAME_FILTER_SAF_MASK (0x200U)
4861#define ENET_MAC_FRAME_FILTER_SAF_SHIFT (9U)
4862/*! SAF - Source Address Filter Enable When this bit is set, the MAC compares the SA field of the
4863 * received packets with the values programmed in the enabled SA registers.
4864 */
4865#define ENET_MAC_FRAME_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAF_MASK)
4866#define ENET_MAC_FRAME_FILTER_RA_MASK (0x80000000U)
4867#define ENET_MAC_FRAME_FILTER_RA_SHIFT (31U)
4868/*! RA - Receive all When this bit is set, the MAC Receiver module passes to the Application all
4869 * frames received irrespective of whether they pass the address filter.
4870 */
4871#define ENET_MAC_FRAME_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_RA_SHIFT)) & ENET_MAC_FRAME_FILTER_RA_MASK)
4872/*! @} */
4873
4874/*! @name MAC_WD_TIMEROUT - MAC watchdog Timeout register */
4875/*! @{ */
4876#define ENET_MAC_WD_TIMEROUT_WTO_MASK (0xFU)
4877#define ENET_MAC_WD_TIMEROUT_WTO_SHIFT (0U)
4878/*! WTO - Watchdog Timeout When the PWE bit is set and the WD bit of the MAC Configuration register
4879 * Table 722 is reset, this field is used as watchdog timeout for a received packet.
4880 */
4881#define ENET_MAC_WD_TIMEROUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_WTO_SHIFT)) & ENET_MAC_WD_TIMEROUT_WTO_MASK)
4882#define ENET_MAC_WD_TIMEROUT_PWE_MASK (0x100U)
4883#define ENET_MAC_WD_TIMEROUT_PWE_SHIFT (8U)
4884/*! PWE - Programmable Watchdog Enable When this bit is set and the WD bit of the MAC Configuration
4885 * register Table 722 is reset, the WTO field is used as watchdog timeout for a received packet.
4886 */
4887#define ENET_MAC_WD_TIMEROUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_PWE_SHIFT)) & ENET_MAC_WD_TIMEROUT_PWE_MASK)
4888/*! @} */
4889
4890/*! @name MAC_VLAN_TAG - MAC vlan tag register */
4891/*! @{ */
4892#define ENET_MAC_VLAN_TAG_VL_MASK (0xFFFFU)
4893#define ENET_MAC_VLAN_TAG_VL_SHIFT (0U)
4894/*! VL - VLAN Tag Identifier for Receive Packets.
4895 */
4896#define ENET_MAC_VLAN_TAG_VL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VL_SHIFT)) & ENET_MAC_VLAN_TAG_VL_MASK)
4897#define ENET_MAC_VLAN_TAG_ETV_MASK (0x10000U)
4898#define ENET_MAC_VLAN_TAG_ETV_SHIFT (16U)
4899/*! ETV - Enable 12-Bit VLAN Tag Comparison.
4900 */
4901#define ENET_MAC_VLAN_TAG_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_ETV_MASK)
4902#define ENET_MAC_VLAN_TAG_VTIM_MASK (0x20000U)
4903#define ENET_MAC_VLAN_TAG_VTIM_SHIFT (17U)
4904/*! VTIM - VLAN Tag Inverse Match Enable.
4905 */
4906#define ENET_MAC_VLAN_TAG_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_VTIM_MASK)
4907#define ENET_MAC_VLAN_TAG_ESVL_MASK (0x40000U)
4908#define ENET_MAC_VLAN_TAG_ESVL_SHIFT (18U)
4909/*! ESVL - Enable S-VLAN.
4910 */
4911#define ENET_MAC_VLAN_TAG_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_ESVL_MASK)
4912#define ENET_MAC_VLAN_TAG_ERSVLM_MASK (0x80000U)
4913#define ENET_MAC_VLAN_TAG_ERSVLM_SHIFT (19U)
4914/*! ERSVLM - Enable Receive S-VLAN Match.
4915 */
4916#define ENET_MAC_VLAN_TAG_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_ERSVLM_MASK)
4917#define ENET_MAC_VLAN_TAG_DOVLTC_MASK (0x100000U)
4918#define ENET_MAC_VLAN_TAG_DOVLTC_SHIFT (20U)
4919/*! DOVLTC - Disable VLAN Type Check.
4920 */
4921#define ENET_MAC_VLAN_TAG_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_DOVLTC_MASK)
4922#define ENET_MAC_VLAN_TAG_EVLS_MASK (0x600000U)
4923#define ENET_MAC_VLAN_TAG_EVLS_SHIFT (21U)
4924/*! EVLS - Enable VLAN Tag Stripping on Receive.
4925 */
4926#define ENET_MAC_VLAN_TAG_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLS_MASK)
4927#define ENET_MAC_VLAN_TAG_EVLRXS_MASK (0x1000000U)
4928#define ENET_MAC_VLAN_TAG_EVLRXS_SHIFT (24U)
4929/*! EVLRXS - Enable VLAN Tag in Rx status.
4930 */
4931#define ENET_MAC_VLAN_TAG_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLRXS_MASK)
4932#define ENET_MAC_VLAN_TAG_VTHM_MASK (0x2000000U)
4933#define ENET_MAC_VLAN_TAG_VTHM_SHIFT (25U)
4934/*! VTHM - Disable VLAN Type Check.
4935 */
4936#define ENET_MAC_VLAN_TAG_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTHM_SHIFT)) & ENET_MAC_VLAN_TAG_VTHM_MASK)
4937#define ENET_MAC_VLAN_TAG_EDVLP_MASK (0x4000000U)
4938#define ENET_MAC_VLAN_TAG_EDVLP_SHIFT (26U)
4939/*! EDVLP - Enable Double VLAN Processing.
4940 */
4941#define ENET_MAC_VLAN_TAG_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_EDVLP_MASK)
4942#define ENET_MAC_VLAN_TAG_ERIVLT_MASK (0x8000000U)
4943#define ENET_MAC_VLAN_TAG_ERIVLT_SHIFT (27U)
4944/*! ERIVLT - Enable Inner VLAN Tag.
4945 */
4946#define ENET_MAC_VLAN_TAG_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_ERIVLT_MASK)
4947#define ENET_MAC_VLAN_TAG_EIVLS_MASK (0x30000000U)
4948#define ENET_MAC_VLAN_TAG_EIVLS_SHIFT (28U)
4949/*! EIVLS - Enable Inner VLAN Tag Stripping on Receive.
4950 */
4951#define ENET_MAC_VLAN_TAG_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLS_MASK)
4952#define ENET_MAC_VLAN_TAG_EIVLRXS_MASK (0x80000000U)
4953#define ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT (31U)
4954/*! EIVLRXS - Enable Inner VLAN Tag in Rx Status.
4955 */
4956#define ENET_MAC_VLAN_TAG_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLRXS_MASK)
4957/*! @} */
4958
4959/*! @name MAC_TX_FLOW_CTRL_Q - Transmit flow control register */
4960/*! @{ */
4961#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK (0x1U)
4962#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT (0U)
4963/*! FCB - Flow Control Busy/Backpressure Activate This register field can be read by the application
4964 * (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is
4965 * cleared to 0 by the core (Self Clear).
4966 */
4967#define ENET_MAC_TX_FLOW_CTRL_Q_FCB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK)
4968#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U)
4969#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U)
4970/*! TFE - Transmit Flow Control Enable In Full-Duplex mode, when this bit is set, the MAC enables
4971 * the flow control operation to transmit Pause frames.
4972 */
4973#define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
4974#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U)
4975#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U)
4976/*! PLT - Pause Low Threshold This field configures the threshold of the PAUSE timer at which the
4977 * input flow control signal is checked for automatic retransmission of PAUSE Frame.
4978 */
4979#define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
4980#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U)
4981#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U)
4982/*! DZPQ - Disable Zero-Quanta Pause When set, this bit disables the automatic generation of
4983 * Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer.
4984 */
4985#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
4986#define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U)
4987#define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U)
4988/*! PT - Pause time This field holds the value to be used in the Pause Time field in the transmit control frame.
4989 */
4990#define ENET_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK)
4991/*! @} */
4992
4993/* The count of ENET_MAC_TX_FLOW_CTRL_Q */
4994#define ENET_MAC_TX_FLOW_CTRL_Q_COUNT (2U)
4995
4996/*! @name MAC_RX_FLOW_CTRL - Receive flow control register */
4997/*! @{ */
4998#define ENET_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U)
4999#define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U)
5000/*! RFE - Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex
5001 * mode, the MAC decodes the received Pause packet and disables its transmitter for a specified
5002 * (Pause) time.
5003 */
5004#define ENET_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK)
5005#define ENET_MAC_RX_FLOW_CTRL_UP_MASK (0x2U)
5006#define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT (1U)
5007/*! UP - Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast
5008 * address specified in the IEEE 802.
5009 */
5010#define ENET_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK)
5011/*! @} */
5012
5013/*! @name MAC_TXQ_PRIO_MAP - */
5014/*! @{ */
5015#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK (0xFFU)
5016#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT (0U)
5017/*! PSTQ0 - Priorities Selected in Transmit Queue 0 This field holds the priorities assigned to Tx Queue 0 by the software.
5018 */
5019#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK)
5020#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK (0xFF00U)
5021#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT (8U)
5022/*! PSTQ1 - Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit.
5023 */
5024#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK)
5025/*! @} */
5026
5027/*! @name MAC_RXQ_CTRL - Receive Queue Control 0 register 0x0000 */
5028/*! @{ */
5029#define ENET_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U)
5030#define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U)
5031/*! AVCPQ - AV Untagged Control Packets Queue.
5032 */
5033#define ENET_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK)
5034#define ENET_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU)
5035#define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U)
5036/*! PSRQ0 - Priorities Selected in the Receive Queue 0.
5037 */
5038#define ENET_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK)
5039#define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U)
5040#define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U)
5041/*! RXQ0EN - Receive Queue 0 Enable.
5042 */
5043#define ENET_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK)
5044#define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU)
5045#define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U)
5046/*! RXQ1EN - Receive Queue 1 Enable.
5047 */
5048#define ENET_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK)
5049#define ENET_MAC_RXQ_CTRL_AVPTPQ_MASK (0x70U)
5050#define ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT (4U)
5051/*! AVPTPQ - AV PTP Packets Queue.
5052 */
5053#define ENET_MAC_RXQ_CTRL_AVPTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVPTPQ_MASK)
5054#define ENET_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U)
5055#define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U)
5056/*! PSRQ1 - Priorities Selected in the Receive Queue 1.
5057 */
5058#define ENET_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK)
5059#define ENET_MAC_RXQ_CTRL_UPQ_MASK (0x7000U)
5060#define ENET_MAC_RXQ_CTRL_UPQ_SHIFT (12U)
5061/*! UPQ - Untagged Packet Queue.
5062 */
5063#define ENET_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK)
5064#define ENET_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U)
5065#define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U)
5066/*! MCBCQ - Multicast and Broadcast Queue.
5067 */
5068#define ENET_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK)
5069#define ENET_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U)
5070#define ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U)
5071/*! PSRQ2 - Priorities Selected in the Receive Queue 2.
5072 */
5073#define ENET_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ2_MASK)
5074#define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U)
5075#define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U)
5076/*! MCBCQEN - Multicast and Broadcast Queue Enable.
5077 */
5078#define ENET_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK)
5079#define ENET_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U)
5080#define ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U)
5081/*! PSRQ3 - Priorities Selected in the Receive Queue 3.
5082 */
5083#define ENET_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ3_MASK)
5084/*! @} */
5085
5086/* The count of ENET_MAC_RXQ_CTRL */
5087#define ENET_MAC_RXQ_CTRL_COUNT (3U)
5088
5089/*! @name MAC_INTR_STAT - Interrupt status register 0x0000 */
5090/*! @{ */
5091#define ENET_MAC_INTR_STAT_PHYIS_MASK (0x8U)
5092#define ENET_MAC_INTR_STAT_PHYIS_SHIFT (3U)
5093/*! PHYIS - PHY Interrupt.
5094 */
5095#define ENET_MAC_INTR_STAT_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PHYIS_SHIFT)) & ENET_MAC_INTR_STAT_PHYIS_MASK)
5096#define ENET_MAC_INTR_STAT_PMTIS_MASK (0x10U)
5097#define ENET_MAC_INTR_STAT_PMTIS_SHIFT (4U)
5098/*! PMTIS - PMT Interrupt Status.
5099 */
5100#define ENET_MAC_INTR_STAT_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PMTIS_SHIFT)) & ENET_MAC_INTR_STAT_PMTIS_MASK)
5101#define ENET_MAC_INTR_STAT_LPIIS_MASK (0x20U)
5102#define ENET_MAC_INTR_STAT_LPIIS_SHIFT (5U)
5103/*! LPIIS - LPI Interrupt Status.
5104 */
5105#define ENET_MAC_INTR_STAT_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_LPIIS_SHIFT)) & ENET_MAC_INTR_STAT_LPIIS_MASK)
5106#define ENET_MAC_INTR_STAT_TSIS_MASK (0x1000U)
5107#define ENET_MAC_INTR_STAT_TSIS_SHIFT (12U)
5108/*! TSIS - Timestamp interrupt status.
5109 */
5110#define ENET_MAC_INTR_STAT_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TSIS_SHIFT)) & ENET_MAC_INTR_STAT_TSIS_MASK)
5111#define ENET_MAC_INTR_STAT_TXSTSIS_MASK (0x2000U)
5112#define ENET_MAC_INTR_STAT_TXSTSIS_SHIFT (13U)
5113/*! TXSTSIS - Transmit Status Interrupt.
5114 */
5115#define ENET_MAC_INTR_STAT_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_TXSTSIS_MASK)
5116#define ENET_MAC_INTR_STAT_RXSTSIS_MASK (0x4000U)
5117#define ENET_MAC_INTR_STAT_RXSTSIS_SHIFT (14U)
5118/*! RXSTSIS - Receive Status Interrupt.
5119 */
5120#define ENET_MAC_INTR_STAT_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_RXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_RXSTSIS_MASK)
5121/*! @} */
5122
5123/*! @name MAC_INTR_EN - Interrupt enable register 0x0000 */
5124/*! @{ */
5125#define ENET_MAC_INTR_EN_PHYIE_MASK (0x8U)
5126#define ENET_MAC_INTR_EN_PHYIE_SHIFT (3U)
5127/*! PHYIE - PHY Interrupt Enable.
5128 */
5129#define ENET_MAC_INTR_EN_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PHYIE_SHIFT)) & ENET_MAC_INTR_EN_PHYIE_MASK)
5130#define ENET_MAC_INTR_EN_PMTIE_MASK (0x10U)
5131#define ENET_MAC_INTR_EN_PMTIE_SHIFT (4U)
5132/*! PMTIE - PMT Interrupt Enable.
5133 */
5134#define ENET_MAC_INTR_EN_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PMTIE_SHIFT)) & ENET_MAC_INTR_EN_PMTIE_MASK)
5135#define ENET_MAC_INTR_EN_LPIIE_MASK (0x20U)
5136#define ENET_MAC_INTR_EN_LPIIE_SHIFT (5U)
5137/*! LPIIE - LPI Interrupt Enable.
5138 */
5139#define ENET_MAC_INTR_EN_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_LPIIE_SHIFT)) & ENET_MAC_INTR_EN_LPIIE_MASK)
5140#define ENET_MAC_INTR_EN_TSIE_MASK (0x1000U)
5141#define ENET_MAC_INTR_EN_TSIE_SHIFT (12U)
5142/*! TSIE - Timestamp Interrupt Enable.
5143 */
5144#define ENET_MAC_INTR_EN_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TSIE_SHIFT)) & ENET_MAC_INTR_EN_TSIE_MASK)
5145#define ENET_MAC_INTR_EN_TXSTSIE_MASK (0x2000U)
5146#define ENET_MAC_INTR_EN_TXSTSIE_SHIFT (13U)
5147/*! TXSTSIE - Transmit Status Interrupt Enable.
5148 */
5149#define ENET_MAC_INTR_EN_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TXSTSIE_SHIFT)) & ENET_MAC_INTR_EN_TXSTSIE_MASK)
5150#define ENET_MAC_INTR_EN_RXSTSIS_MASK (0x4000U)
5151#define ENET_MAC_INTR_EN_RXSTSIS_SHIFT (14U)
5152/*! RXSTSIS - Receive Status Interrupt Enable.
5153 */
5154#define ENET_MAC_INTR_EN_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_RXSTSIS_SHIFT)) & ENET_MAC_INTR_EN_RXSTSIS_MASK)
5155/*! @} */
5156
5157/*! @name MAC_RXTX_STAT - Receive Transmit Status register */
5158/*! @{ */
5159#define ENET_MAC_RXTX_STAT_TJT_MASK (0x1U)
5160#define ENET_MAC_RXTX_STAT_TJT_SHIFT (0U)
5161/*! TJT - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt
5162 * signal because of the setting of PHYIS bit in MAC Interrupt Status register Table 731.
5163 */
5164#define ENET_MAC_RXTX_STAT_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_TJT_SHIFT)) & ENET_MAC_RXTX_STAT_TJT_MASK)
5165#define ENET_MAC_RXTX_STAT_NCARR_MASK (0x2U)
5166#define ENET_MAC_RXTX_STAT_NCARR_SHIFT (1U)
5167/*! NCARR - No Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758, this
5168 * bit indicates that the carrier signal from the PHY is not present at the end of preamble
5169 * transmission.
5170 */
5171#define ENET_MAC_RXTX_STAT_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_NCARR_SHIFT)) & ENET_MAC_RXTX_STAT_NCARR_MASK)
5172#define ENET_MAC_RXTX_STAT_LCARR_MASK (0x4U)
5173#define ENET_MAC_RXTX_STAT_LCARR_SHIFT (2U)
5174/*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758,
5175 * this bit indicates that the loss of carrier occurred during packet transmission, that is, the
5176 * PHY Carrier signal was inactive for one or more transmission clock periods during packet
5177 * transmission.
5178 */
5179#define ENET_MAC_RXTX_STAT_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCARR_SHIFT)) & ENET_MAC_RXTX_STAT_LCARR_MASK)
5180#define ENET_MAC_RXTX_STAT_EXDEF_MASK (0x8U)
5181#define ENET_MAC_RXTX_STAT_EXDEF_SHIFT (3U)
5182/*! EXDEF - Excessive Deferral When the DTXSTS bit is set in the MTL Operation Mode register Table
5183 * 758 and the DC bit is set in the MAC Configuration register Table 758, this bit indicates that
5184 * the transmission ended because of excessive deferral of over 24,288 bit times (155,680 when
5185 * Jumbo packet is enabled).
5186 */
5187#define ENET_MAC_RXTX_STAT_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXDEF_SHIFT)) & ENET_MAC_RXTX_STAT_EXDEF_MASK)
5188#define ENET_MAC_RXTX_STAT_LCOL_MASK (0x10U)
5189#define ENET_MAC_RXTX_STAT_LCOL_SHIFT (4U)
5190/*! LCOL - Late Collision When the DTXSTS bit is set in the MTL Operation Mode register Table 758,
5191 * this bit indicates that the packet transmission aborted because a collision occurred after the
5192 * collision window (64 bytes including Preamble in MII mode).
5193 */
5194#define ENET_MAC_RXTX_STAT_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCOL_SHIFT)) & ENET_MAC_RXTX_STAT_LCOL_MASK)
5195#define ENET_MAC_RXTX_STAT_EXCOL_MASK (0x20U)
5196#define ENET_MAC_RXTX_STAT_EXCOL_SHIFT (5U)
5197/*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MTL Operation Mode register Table
5198 * 758, this bit indicates that the transmission aborted after 16 successive collisions while
5199 * attempting to transmit the current packet.
5200 */
5201#define ENET_MAC_RXTX_STAT_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXCOL_SHIFT)) & ENET_MAC_RXTX_STAT_EXCOL_MASK)
5202#define ENET_MAC_RXTX_STAT_RWT_MASK (0x100U)
5203#define ENET_MAC_RXTX_STAT_RWT_SHIFT (8U)
5204/*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048
5205 * bytes is received (10,240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the
5206 * MAC Configuration register Table 722.
5207 */
5208#define ENET_MAC_RXTX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_RWT_SHIFT)) & ENET_MAC_RXTX_STAT_RWT_MASK)
5209/*! @} */
5210
5211/*! @name MAC_PMT_CRTL_STAT - */
5212/*! @{ */
5213#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK (0x1U)
5214#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT (0U)
5215/*! PWRDWN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
5216 * entered the LPI state because of the setting of the LPIEN bit.
5217 */
5218#define ENET_MAC_PMT_CRTL_STAT_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK)
5219#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK (0x2U)
5220#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT (1U)
5221/*! MGKPKTEN - Magic Packet Enable.
5222 */
5223#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK)
5224#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK (0x4U)
5225#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT (2U)
5226/*! RWKPKTEN - Remote Wake-Up Packet Enable When this bit is set, a power management event is
5227 * generated when the MAC receives a remote wake-up packet.
5228 */
5229#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK)
5230#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK (0x20U)
5231#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT (5U)
5232/*! MGKPRCVD - Magic Packet Received.
5233 */
5234#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK)
5235#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK (0x40U)
5236#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT (6U)
5237/*! RWKPRCVD - Remote Wake-Up Packet Received.
5238 */
5239#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK)
5240#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK (0x200U)
5241#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT (9U)
5242/*! GLBLUCAST - Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF)
5243 * address recognition is detected as a remote wake-up packet.
5244 */
5245#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK)
5246#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK (0x400U)
5247#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT (10U)
5248/*! RWKPFE - Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the
5249 * MAC receiver drops all received frames until it receives the expected wake-up frame.
5250 */
5251#define ENET_MAC_PMT_CRTL_STAT_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK)
5252#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK (0x1F000000U)
5253#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT (24U)
5254/*! RWKPTR - Remote Wake-up FIFO Pointer This field gives the current value (0 to 7) of the Remote
5255 * Wake-up Packet Filter register pointer.
5256 */
5257#define ENET_MAC_PMT_CRTL_STAT_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK)
5258#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK (0x80000000U)
5259#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT (31U)
5260/*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the
5261 * remote wake-up packet filter register pointer is reset to 3'b000.
5262 */
5263#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK)
5264/*! @} */
5265
5266/*! @name MAC_RWAKE_FRFLT - Remote wake-up frame filter */
5267/*! @{ */
5268#define ENET_MAC_RWAKE_FRFLT_ADDR_MASK (0xFFFFFFFFU)
5269#define ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT (0U)
5270/*! ADDR - WKUPFMFILTER address.
5271 */
5272#define ENET_MAC_RWAKE_FRFLT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT)) & ENET_MAC_RWAKE_FRFLT_ADDR_MASK)
5273/*! @} */
5274
5275/*! @name MAC_LPI_CTRL_STAT - LPI Control and Status Register */
5276/*! @{ */
5277#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK (0x1U)
5278#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT (0U)
5279/*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
5280 * entered the LPI state because of the setting of the LPIEN bit.
5281 */
5282#define ENET_MAC_LPI_CTRL_STAT_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK)
5283#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK (0x2U)
5284#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT (1U)
5285/*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited
5286 * the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired.
5287 */
5288#define ENET_MAC_LPI_CTRL_STAT_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK)
5289#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK (0x4U)
5290#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT (2U)
5291/*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received
5292 * an LPI pattern and entered the LPI state.
5293 */
5294#define ENET_MAC_LPI_CTRL_STAT_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK)
5295#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK (0x8U)
5296#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT (3U)
5297/*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped
5298 * receiving the LPI pattern on the MII interface, exited the LPI state, and resumed the normal
5299 * reception.
5300 */
5301#define ENET_MAC_LPI_CTRL_STAT_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK)
5302#define ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK (0x100U)
5303#define ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT (8U)
5304/*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the LPI pattern on the MII interface.
5305 */
5306#define ENET_MAC_LPI_CTRL_STAT_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK)
5307#define ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK (0x200U)
5308#define ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT (9U)
5309/*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI pattern on the MII interface.
5310 */
5311#define ENET_MAC_LPI_CTRL_STAT_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK)
5312#define ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK (0x10000U)
5313#define ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT (16U)
5314/*! LPIEN - LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state.
5315 */
5316#define ENET_MAC_LPI_CTRL_STAT_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK)
5317#define ENET_MAC_LPI_CTRL_STAT_PLS_MASK (0x20000U)
5318#define ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT (17U)
5319/*! PLS - PHY Link Status This bit indicates the link status of the PHY.
5320 */
5321#define ENET_MAC_LPI_CTRL_STAT_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_PLS_MASK)
5322#define ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK (0x80000U)
5323#define ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT (19U)
5324/*! LPITXA - LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming
5325 * out of the LPI mode on the Transmit side.
5326 */
5327#define ENET_MAC_LPI_CTRL_STAT_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK)
5328#define ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK (0x100000U)
5329#define ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT (20U)
5330/*! LPIATE - LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state.
5331 */
5332#define ENET_MAC_LPI_CTRL_STAT_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK)
5333#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK (0x200000U)
5334#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT (21U)
5335/*! LPITCSE - LPI Tx Clock Stop Enable When this bit is set, the MAC asserts LPI Tx Clock Gating
5336 * Control signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be
5337 * stopped.
5338 */
5339#define ENET_MAC_LPI_CTRL_STAT_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK)
5340/*! @} */
5341
5342/*! @name MAC_LPI_TIMER_CTRL - LPI Timers Control register */
5343/*! @{ */
5344#define ENET_MAC_LPI_TIMER_CTRL_TWT_MASK (0xFFFFU)
5345#define ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT (0U)
5346/*! TWT - LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC
5347 * waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal
5348 * transmission.
5349 */
5350#define ENET_MAC_LPI_TIMER_CTRL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_TWT_MASK)
5351#define ENET_MAC_LPI_TIMER_CTRL_LST_MASK (0x3FF0000U)
5352#define ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT (16U)
5353/*! LST - LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link
5354 * status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY.
5355 */
5356#define ENET_MAC_LPI_TIMER_CTRL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_LST_MASK)
5357/*! @} */
5358
5359/*! @name MAC_LPI_ENTR_TIMR - LPI entry Timer register */
5360/*! @{ */
5361#define ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK (0xFFFF8U)
5362#define ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT (3U)
5363/*! LPIET - LPI Entry Timer This field specifies the time in microseconds the MAC will wait to enter
5364 * LPI mode, after it has transmitted all the frames.
5365 */
5366#define ENET_MAC_LPI_ENTR_TIMR_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT)) & ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK)
5367/*! @} */
5368
5369/*! @name MAC_1US_TIC_COUNTR - */
5370/*! @{ */
5371#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK (0xFFFU)
5372#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT (0U)
5373/*! TIC_1US_CNTR - 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us.
5374 */
5375#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT)) & ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK)
5376/*! @} */
5377
5378/*! @name MAC_VERSION - MAC version register */
5379/*! @{ */
5380#define ENET_MAC_VERSION_SNPVER_MASK (0xFFU)
5381#define ENET_MAC_VERSION_SNPVER_SHIFT (0U)
5382/*! SNPVER - NXP defined version.
5383 */
5384#define ENET_MAC_VERSION_SNPVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPVER_SHIFT)) & ENET_MAC_VERSION_SNPVER_MASK)
5385#define ENET_MAC_VERSION_USERVER_MASK (0xFF00U)
5386#define ENET_MAC_VERSION_USERVER_SHIFT (8U)
5387/*! USERVER - User defined version.
5388 */
5389#define ENET_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK)
5390/*! @} */
5391
5392/*! @name MAC_DBG - MAC debug register */
5393/*! @{ */
5394#define ENET_MAC_DBG_REPESTS_MASK (0x1U)
5395#define ENET_MAC_DBG_REPESTS_SHIFT (0U)
5396/*! REPESTS - MAC MII Receive Protocol Engine Status When this bit is set, it indicates that the MAC
5397 * MII receive protocol engine is actively receiving data, and it is not in the Idle state.
5398 */
5399#define ENET_MAC_DBG_REPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_REPESTS_SHIFT)) & ENET_MAC_DBG_REPESTS_MASK)
5400#define ENET_MAC_DBG_RFCFCSTS_MASK (0x6U)
5401#define ENET_MAC_DBG_RFCFCSTS_SHIFT (1U)
5402/*! RFCFCSTS - MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates
5403 * the active state of the small FIFO Read and Write controllers of the MAC Receive Packet
5404 * Controller module.
5405 */
5406#define ENET_MAC_DBG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_RFCFCSTS_SHIFT)) & ENET_MAC_DBG_RFCFCSTS_MASK)
5407#define ENET_MAC_DBG_TPESTS_MASK (0x10000U)
5408#define ENET_MAC_DBG_TPESTS_SHIFT (16U)
5409/*! TPESTS - MAC MII Transmit Protocol Engine Status When this bit is set, it indicates that the MAC
5410 * or MII transmit protocol engine is actively transmitting data, and it is not in the Idle
5411 * state.
5412 */
5413#define ENET_MAC_DBG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TPESTS_SHIFT)) & ENET_MAC_DBG_TPESTS_MASK)
5414#define ENET_MAC_DBG_TFCSTS_MASK (0x60000U)
5415#define ENET_MAC_DBG_TFCSTS_SHIFT (17U)
5416/*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module.
5417 */
5418#define ENET_MAC_DBG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TFCSTS_SHIFT)) & ENET_MAC_DBG_TFCSTS_MASK)
5419/*! @} */
5420
5421/*! @name MAC_HW_FEAT - MAC hardware feature register 0x0201 */
5422/*! @{ */
5423#define ENET_MAC_HW_FEAT_MIISEL_MASK (0x1U)
5424#define ENET_MAC_HW_FEAT_MIISEL_SHIFT (0U)
5425/*! MIISEL - 10 or 100 Mbps Support.
5426 */
5427#define ENET_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK)
5428#define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU)
5429#define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U)
5430/*! RXFIFOSIZE - MTL Receive FIFO Size.
5431 */
5432#define ENET_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK)
5433#define ENET_MAC_HW_FEAT_RXQCNT_MASK (0xFU)
5434#define ENET_MAC_HW_FEAT_RXQCNT_SHIFT (0U)
5435/*! RXQCNT - Number of MTL Receive Queues.
5436 */
5437#define ENET_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK)
5438#define ENET_MAC_HW_FEAT_HDSEL_MASK (0x4U)
5439#define ENET_MAC_HW_FEAT_HDSEL_SHIFT (2U)
5440/*! HDSEL - Half-duplex Support.
5441 */
5442#define ENET_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK)
5443#define ENET_MAC_HW_FEAT_VLHASH_MASK (0x10U)
5444#define ENET_MAC_HW_FEAT_VLHASH_SHIFT (4U)
5445/*! VLHASH - Hash Table Based Filtering option.
5446 */
5447#define ENET_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK)
5448#define ENET_MAC_HW_FEAT_SMASEL_MASK (0x20U)
5449#define ENET_MAC_HW_FEAT_SMASEL_SHIFT (5U)
5450/*! SMASEL - SMA (MDIO) Interface.
5451 */
5452#define ENET_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK)
5453#define ENET_MAC_HW_FEAT_RWKSEL_MASK (0x40U)
5454#define ENET_MAC_HW_FEAT_RWKSEL_SHIFT (6U)
5455/*! RWKSEL - PMT Remote Wake-up Packet Detection.
5456 */
5457#define ENET_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK)
5458#define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U)
5459#define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U)
5460/*! TXFIFOSIZE - MTL Transmit FIFO Size.
5461 */
5462#define ENET_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK)
5463#define ENET_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U)
5464#define ENET_MAC_HW_FEAT_TXQCNT_SHIFT (6U)
5465/*! TXQCNT - Number of MTL Transmit Queues.
5466 */
5467#define ENET_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK)
5468#define ENET_MAC_HW_FEAT_MGKSEL_MASK (0x80U)
5469#define ENET_MAC_HW_FEAT_MGKSEL_SHIFT (7U)
5470/*! MGKSEL - PMT magic packet detection.
5471 */
5472#define ENET_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK)
5473#define ENET_MAC_HW_FEAT_MMCSEL_MASK (0x100U)
5474#define ENET_MAC_HW_FEAT_MMCSEL_SHIFT (8U)
5475/*! MMCSEL - RMON Module Enable.
5476 */
5477#define ENET_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK)
5478#define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U)
5479#define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U)
5480/*! ARPOFFSEL - ARP Offload Enabled.
5481 */
5482#define ENET_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK)
5483#define ENET_MAC_HW_FEAT_OSTEN_MASK (0x800U)
5484#define ENET_MAC_HW_FEAT_OSTEN_SHIFT (11U)
5485/*! OSTEN - One-Step Timestamping Feature.
5486 */
5487#define ENET_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK)
5488#define ENET_MAC_HW_FEAT_PTOEN_MASK (0x1000U)
5489#define ENET_MAC_HW_FEAT_PTOEN_SHIFT (12U)
5490/*! PTOEN - PTP OffLoad Feature.
5491 */
5492#define ENET_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK)
5493#define ENET_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U)
5494#define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT (12U)
5495/*! RXCHCNT - Number of DMA Receive Channels.
5496 */
5497#define ENET_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK)
5498#define ENET_MAC_HW_FEAT_TSSEL_MASK (0x1000U)
5499#define ENET_MAC_HW_FEAT_TSSEL_SHIFT (12U)
5500/*! TSSEL - IEEE 1588-2008 Timestamp support .
5501 */
5502#define ENET_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK)
5503#define ENET_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U)
5504#define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U)
5505/*! ADVTHWORD - IEEE 1588 High Word Register Feature.
5506 */
5507#define ENET_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK)
5508#define ENET_MAC_HW_FEAT_EEESEL_MASK (0x2000U)
5509#define ENET_MAC_HW_FEAT_EEESEL_SHIFT (13U)
5510/*! EEESEL - Energy Efficient Ethernet Support .
5511 */
5512#define ENET_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK)
5513#define ENET_MAC_HW_FEAT_ADDR64_MASK (0xC000U)
5514#define ENET_MAC_HW_FEAT_ADDR64_SHIFT (14U)
5515/*! ADDR64 - Address width.
5516 */
5517#define ENET_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK)
5518#define ENET_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U)
5519#define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT (14U)
5520/*! TXCOESEL - Transmit Checksum Offload Support.
5521 */
5522#define ENET_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK)
5523#define ENET_MAC_HW_FEAT_DCBEN_MASK (0x10000U)
5524#define ENET_MAC_HW_FEAT_DCBEN_SHIFT (16U)
5525/*! DCBEN - Data Center Bridging feature.
5526 */
5527#define ENET_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK)
5528#define ENET_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U)
5529#define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT (16U)
5530/*! RXCOESEL - Receive Checksum Offload Support.
5531 */
5532#define ENET_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK)
5533#define ENET_MAC_HW_FEAT_SPEN_MASK (0x20000U)
5534#define ENET_MAC_HW_FEAT_SPEN_SHIFT (17U)
5535/*! SPEN - Split Header Structure feature.
5536 */
5537#define ENET_MAC_HW_FEAT_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPEN_SHIFT)) & ENET_MAC_HW_FEAT_SPEN_MASK)
5538#define ENET_MAC_HW_FEAT_TSOEN_MASK (0x40000U)
5539#define ENET_MAC_HW_FEAT_TSOEN_SHIFT (18U)
5540/*! TSOEN - TCP Segment Offload Feature.
5541 */
5542#define ENET_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK)
5543#define ENET_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U)
5544#define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT (18U)
5545/*! TXCHCNT - Number of DMA Transmit Channels.
5546 */
5547#define ENET_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK)
5548#define ENET_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U)
5549#define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT (19U)
5550/*! DBGMEMA - DMA Debug Register Feature.
5551 */
5552#define ENET_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK)
5553#define ENET_MAC_HW_FEAT_AVSEL_MASK (0x100000U)
5554#define ENET_MAC_HW_FEAT_AVSEL_SHIFT (20U)
5555/*! AVSEL - Audio Video Bridging Feature.
5556 */
5557#define ENET_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK)
5558#define ENET_MAC_HW_FEAT_LPMODEEN_MASK (0x800000U)
5559#define ENET_MAC_HW_FEAT_LPMODEEN_SHIFT (23U)
5560/*! LPMODEEN - Low Power Mode Feature Support .
5561 */
5562#define ENET_MAC_HW_FEAT_LPMODEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_LPMODEEN_SHIFT)) & ENET_MAC_HW_FEAT_LPMODEEN_MASK)
5563#define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U)
5564#define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U)
5565/*! HASHTBLSZ - Hash Table Size.
5566 */
5567#define ENET_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK)
5568#define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U)
5569#define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U)
5570/*! PPSOUTNUM - Number of PPS Outputs.
5571 */
5572#define ENET_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK)
5573#define ENET_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U)
5574#define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U)
5575/*! TSSTSSEL - Timestamp System Time Source.
5576 */
5577#define ENET_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK)
5578#define ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK (0x78000000U)
5579#define ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT (27U)
5580/*! L3_L4_FILTER - Total Number of L3 and L4 Filters .
5581 */
5582#define ENET_MAC_HW_FEAT_L3_L4_FILTER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT)) & ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK)
5583#define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U)
5584#define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U)
5585/*! ACTPHYSEL - Active PHY Selected.
5586 */
5587#define ENET_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK)
5588#define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U)
5589#define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U)
5590/*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs.
5591 */
5592#define ENET_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK)
5593/*! @} */
5594
5595/* The count of ENET_MAC_HW_FEAT */
5596#define ENET_MAC_HW_FEAT_COUNT (3U)
5597
5598/*! @name MAC_MDIO_ADDR - MIDO address Register */
5599/*! @{ */
5600#define ENET_MAC_MDIO_ADDR_MB_MASK (0x1U)
5601#define ENET_MAC_MDIO_ADDR_MB_SHIFT (0U)
5602/*! MB - MII busy.
5603 */
5604#define ENET_MAC_MDIO_ADDR_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MB_SHIFT)) & ENET_MAC_MDIO_ADDR_MB_MASK)
5605#define ENET_MAC_MDIO_ADDR_MOC_MASK (0xCU)
5606#define ENET_MAC_MDIO_ADDR_MOC_SHIFT (2U)
5607/*! MOC - MII Operation Command.
5608 */
5609#define ENET_MAC_MDIO_ADDR_MOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MOC_SHIFT)) & ENET_MAC_MDIO_ADDR_MOC_MASK)
5610#define ENET_MAC_MDIO_ADDR_CR_MASK (0xF00U)
5611#define ENET_MAC_MDIO_ADDR_CR_SHIFT (8U)
5612/*! CR - CSR Clock Range.
5613 */
5614#define ENET_MAC_MDIO_ADDR_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_CR_SHIFT)) & ENET_MAC_MDIO_ADDR_CR_MASK)
5615#define ENET_MAC_MDIO_ADDR_NTC_MASK (0x7000U)
5616#define ENET_MAC_MDIO_ADDR_NTC_SHIFT (12U)
5617/*! NTC - Number of Training Clocks This field controls the number of trailing clock cycles
5618 * generated on MDC after the end of transmission of MDIO frame.
5619 */
5620#define ENET_MAC_MDIO_ADDR_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_NTC_SHIFT)) & ENET_MAC_MDIO_ADDR_NTC_MASK)
5621#define ENET_MAC_MDIO_ADDR_RDA_MASK (0x1F0000U)
5622#define ENET_MAC_MDIO_ADDR_RDA_SHIFT (16U)
5623/*! RDA - Register/Device Address These bits select the PHY register in selected PHY device.
5624 */
5625#define ENET_MAC_MDIO_ADDR_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_RDA_SHIFT)) & ENET_MAC_MDIO_ADDR_RDA_MASK)
5626#define ENET_MAC_MDIO_ADDR_PA_MASK (0x3E00000U)
5627#define ENET_MAC_MDIO_ADDR_PA_SHIFT (21U)
5628/*! PA - Physical Layer Address This field indicates which PHY devices (out of 32 devices) the MAC is accessing.
5629 */
5630#define ENET_MAC_MDIO_ADDR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PA_SHIFT)) & ENET_MAC_MDIO_ADDR_PA_MASK)
5631#define ENET_MAC_MDIO_ADDR_BTB_MASK (0x4000000U)
5632#define ENET_MAC_MDIO_ADDR_BTB_SHIFT (26U)
5633/*! BTB - Back to Back transactions When this bit is set and the NTC has value greater than 0, then
5634 * the MAC will inform the completion of a read or write command at the end of frame transfer
5635 * (before the trailing clocks are transmitted).
5636 */
5637#define ENET_MAC_MDIO_ADDR_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_BTB_SHIFT)) & ENET_MAC_MDIO_ADDR_BTB_MASK)
5638#define ENET_MAC_MDIO_ADDR_PSE_MASK (0x8000000U)
5639#define ENET_MAC_MDIO_ADDR_PSE_SHIFT (27U)
5640/*! PSE - Preamble Suppression Enable When this bit is set, the SMA will suppress the 32-bit
5641 * preamble and transmit MDIO frames with only 1 preamble bit.
5642 */
5643#define ENET_MAC_MDIO_ADDR_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PSE_SHIFT)) & ENET_MAC_MDIO_ADDR_PSE_MASK)
5644/*! @} */
5645
5646/*! @name MAC_MDIO_DATA - MDIO Data register */
5647/*! @{ */
5648#define ENET_MAC_MDIO_DATA_MD_MASK (0xFFFFU)
5649#define ENET_MAC_MDIO_DATA_MD_SHIFT (0U)
5650/*! MD - MII Data This field contains the 16-bit data value read from the PHY after a Management
5651 * Read operation or the 16-bit data value to be written to the PHY before a Management Write
5652 * operation.
5653 */
5654#define ENET_MAC_MDIO_DATA_MD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_MD_SHIFT)) & ENET_MAC_MDIO_DATA_MD_MASK)
5655/*! @} */
5656
5657/*! @name MAC_ADDR_HIGH - MAC address0 high register */
5658/*! @{ */
5659#define ENET_MAC_ADDR_HIGH_A47_32_MASK (0xFFFFU)
5660#define ENET_MAC_ADDR_HIGH_A47_32_SHIFT (0U)
5661/*! A47_32 - MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the 6-byte first MAC address.
5662 */
5663#define ENET_MAC_ADDR_HIGH_A47_32(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_A47_32_SHIFT)) & ENET_MAC_ADDR_HIGH_A47_32_MASK)
5664#define ENET_MAC_ADDR_HIGH_DCS_MASK (0x10000U)
5665#define ENET_MAC_ADDR_HIGH_DCS_SHIFT (16U)
5666/*! DCS - DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose
5667 * DA matches the MAC Address content is routed.
5668 */
5669#define ENET_MAC_ADDR_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_DCS_SHIFT)) & ENET_MAC_ADDR_HIGH_DCS_MASK)
5670#define ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000U)
5671#define ENET_MAC_ADDR_HIGH_AE_SHIFT (31U)
5672/*! AE - Address Enable.
5673 */
5674#define ENET_MAC_ADDR_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_AE_SHIFT)) & ENET_MAC_ADDR_HIGH_AE_MASK)
5675/*! @} */
5676
5677/*! @name MAC_ADDR_LOW - MAC address0 low register */
5678/*! @{ */
5679#define ENET_MAC_ADDR_LOW_A31_0_MASK (0xFFFFFFFFU)
5680#define ENET_MAC_ADDR_LOW_A31_0_SHIFT (0U)
5681/*! A31_0 - MAC Address0 [31:0] This field contains the lower 32 bits of the 6-byte first MAC address.
5682 */
5683#define ENET_MAC_ADDR_LOW_A31_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_LOW_A31_0_SHIFT)) & ENET_MAC_ADDR_LOW_A31_0_MASK)
5684/*! @} */
5685
5686/*! @name MAC_TIMESTAMP_CTRL - Time stamp control register */
5687/*! @{ */
5688#define ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK (0x1U)
5689#define ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT (0U)
5690/*! TSENA - Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets.
5691 */
5692#define ENET_MAC_TIMESTAMP_CTRL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK)
5693#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK (0x2U)
5694#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT (1U)
5695/*! TSCFUPDT - Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp.
5696 */
5697#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK)
5698#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK (0x4U)
5699#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT (2U)
5700/*! TSINIT - Initialize Timestamp When this bit is set, the system time is initialized (overwritten)
5701 * with the value specified in the MAC Register 80 (System Time Seconds Update.
5702 */
5703#define ENET_MAC_TIMESTAMP_CTRL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK)
5704#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK (0x8U)
5705#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT (3U)
5706/*! TSUPDT - Update Timestamp When this bit is set, the system time is updated (added or subtracted)
5707 * with the value specified in MAC System Time Seconds Update Table 753 and MAC System Time
5708 * Nanoseconds Update Table 754.
5709 */
5710#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK)
5711#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK (0x10U)
5712#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT (4U)
5713/*! TSTRIG - Enable Timestamp Interrupt Trigger When this bit is set, the timestamp interrupt is
5714 * generated when the System Time becomes greater than the value written in the Target Time register.
5715 */
5716#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK)
5717#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK (0x20U)
5718#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT (5U)
5719/*! TADDREG - Update Addend Register When this bit is set, the content of the Timestamp Addend
5720 * register is updated in the PTP block for fine correction.
5721 */
5722#define ENET_MAC_TIMESTAMP_CTRL_TADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK)
5723#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK (0x100U)
5724#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT (8U)
5725/*! TSENALL - Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is
5726 * enabled for all packets received by the MAC.
5727 */
5728#define ENET_MAC_TIMESTAMP_CTRL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK)
5729#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK (0x200U)
5730#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT (9U)
5731/*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low
5732 * register rolls over after 0x3B9AC9FF value (that is, 1 nanosecond accuracy) and increments
5733 * the timestamp (High) seconds.
5734 */
5735#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)
5736#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK (0x400U)
5737#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT (10U)
5738/*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE
5739 * 1588 version 2 format is used to process the PTP packets.
5740 */
5741#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK)
5742#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK (0x800U)
5743#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT (11U)
5744/*! TSIPENA - Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver
5745 * processes the PTP packets encapsulated directly in the Ethernet packets.
5746 */
5747#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK)
5748#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK (0x1000U)
5749#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT (12U)
5750/*! TSIPV6ENA - Enable Processing of PTP Packets Sent over 1Pv6-UDP When this bit is set, the MAC
5751 * receiver processes the PTP packets encapsulated in IPv6-UDP packets.
5752 */
5753#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK)
5754#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK (0x2000U)
5755#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT (13U)
5756/*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC
5757 * receiver processes the PTP packets encapsulated in IPv4-UDP packets.
5758 */
5759#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK)
5760#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK (0x4000U)
5761#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT (14U)
5762/*! TSEVTENA - Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp
5763 * snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp).
5764 */
5765#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK)
5766#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK (0x8000U)
5767#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT (15U)
5768/*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot
5769 * is taken only for the messages that are relevant to the master node.
5770 */
5771#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK)
5772#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK (0x30000U)
5773#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT (16U)
5774/*! SNAPTYPSEL - Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14,
5775 * decide the set of PTP packet types for which snapshot needs to be taken.
5776 */
5777#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK)
5778#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK (0x40000U)
5779#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT (18U)
5780/*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC
5781 * address (that matches any MAC Address register) is used to filter the PTP packets when PTP is
5782 * directly sent over Ethernet.
5783 */
5784#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK)
5785#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK (0x1000000U)
5786#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT (24U)
5787/*! TXTTSSTSM - Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier
5788 * transmit timestamp status even if it is not read by the software.
5789 */
5790#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK)
5791#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK (0x10000000U)
5792#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT (28U)
5793/*! AV8021ASMEN - AV 802.
5794 */
5795#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK)
5796/*! @} */
5797
5798/*! @name MAC_SUB_SCND_INCR - Sub-second increment register */
5799/*! @{ */
5800#define ENET_MAC_SUB_SCND_INCR_SSINC_MASK (0xFF0000U)
5801#define ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT (16U)
5802/*! SSINC - Sub-second increment value.
5803 */
5804#define ENET_MAC_SUB_SCND_INCR_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT)) & ENET_MAC_SUB_SCND_INCR_SSINC_MASK)
5805/*! @} */
5806
5807/*! @name MAC_SYS_TIME_SCND - System time seconds register */
5808/*! @{ */
5809#define ENET_MAC_SYS_TIME_SCND_TSS_MASK (0xFFFFFFFFU)
5810#define ENET_MAC_SYS_TIME_SCND_TSS_SHIFT (0U)
5811/*! TSS - Time stamp second The value in this field indicates the current value in seconds of the
5812 * System Time maintained by the MAC.
5813 */
5814#define ENET_MAC_SYS_TIME_SCND_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_TSS_MASK)
5815/*! @} */
5816
5817/*! @name MAC_SYS_TIME_NSCND - System time nanoseconds register */
5818/*! @{ */
5819#define ENET_MAC_SYS_TIME_NSCND_TSSS_MASK (0x7FFFFFFFU)
5820#define ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT (0U)
5821/*! TSSS - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.
5822 */
5823#define ENET_MAC_SYS_TIME_NSCND_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK)
5824/*! @} */
5825
5826/*! @name MAC_SYS_TIME_SCND_UPD - */
5827/*! @{ */
5828#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK (0xFFFFFFFFU)
5829#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT (0U)
5830/*! TSS - Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time.
5831 */
5832#define ENET_MAC_SYS_TIME_SCND_UPD_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK)
5833/*! @} */
5834
5835/*! @name MAC_SYS_TIME_NSCND_UPD - */
5836/*! @{ */
5837#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK (0x7FFFFFFFU)
5838#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT (0U)
5839/*! TSSS - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.
5840 */
5841#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK)
5842#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK (0x80000000U)
5843#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT (31U)
5844/*! ADDSUB - Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register.
5845 */
5846#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK)
5847/*! @} */
5848
5849/*! @name MAC_SYS_TIMESTMP_ADDEND - Time stamp addend register */
5850/*! @{ */
5851#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK (0xFFFFFFFFU)
5852#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT (0U)
5853/*! TSAR - Time stamp addend This register indicates the 32-bit time value to be added to the
5854 * Accumulator register to achieve time synchronization.
5855 */
5856#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK)
5857/*! @} */
5858
5859/*! @name MAC_SYS_TIME_HWORD_SCND - */
5860/*! @{ */
5861#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK (0xFFFFU)
5862#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT (0U)
5863/*! TSHWR - Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value.
5864 */
5865#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT)) & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK)
5866/*! @} */
5867
5868/*! @name MAC_SYS_TIMESTMP_STAT - Time stamp status register */
5869/*! @{ */
5870#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK (0x1U)
5871#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT (0U)
5872/*! TSSOVF - Time stamp seconds overflow When set, indicates that the seconds value of the Time
5873 * stamp has overflowed beyond 0xFFFF_FFFF.
5874 */
5875#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT)) & ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK)
5876/*! @} */
5877
5878/*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Tx timestamp status nanoseconds */
5879/*! @{ */
5880#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK (0x7FFFFFFFU)
5881#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT (0U)
5882/*! TXTSSTSLO - Transmit timestamp status low.
5883 */
5884#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK)
5885#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK (0x80000000U)
5886#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT (31U)
5887/*! TXTSSTSMIS - Transmit timestamp status missed.
5888 */
5889#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK)
5890/*! @} */
5891
5892/*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Tx timestamp status seconds */
5893/*! @{ */
5894#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK (0xFFFFFFFFU)
5895#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT (0U)
5896/*! TXTSSTSHI - Transmit timestamp status high.
5897 */
5898#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK)
5899/*! @} */
5900
5901/*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp ingress correction */
5902/*! @{ */
5903#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
5904#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
5905/*! TSIC - Transmit ingress correction.
5906 */
5907#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
5908/*! @} */
5909
5910/*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp egress correction */
5911/*! @{ */
5912#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
5913#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
5914/*! TSEC - Transmit egress correction.
5915 */
5916#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
5917/*! @} */
5918
5919/*! @name MTL_OP_MODE - MTL Operation Mode Register */
5920/*! @{ */
5921#define ENET_MTL_OP_MODE_DTXSTS_MASK (0x2U)
5922#define ENET_MTL_OP_MODE_DTXSTS_SHIFT (1U)
5923/*! DTXSTS - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL.
5924 */
5925#define ENET_MTL_OP_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_DTXSTS_SHIFT)) & ENET_MTL_OP_MODE_DTXSTS_MASK)
5926#define ENET_MTL_OP_MODE_RAA_MASK (0x4U)
5927#define ENET_MTL_OP_MODE_RAA_SHIFT (2U)
5928/*! RAA - Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side.
5929 */
5930#define ENET_MTL_OP_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_RAA_SHIFT)) & ENET_MTL_OP_MODE_RAA_MASK)
5931#define ENET_MTL_OP_MODE_SCHALG_MASK (0x60U)
5932#define ENET_MTL_OP_MODE_SCHALG_SHIFT (5U)
5933/*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: 0x00: WRR
5934 * algorithm 0x1: Reserved 0x2: Reserved 0x3: Strict priority algorithm.
5935 */
5936#define ENET_MTL_OP_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_SCHALG_SHIFT)) & ENET_MTL_OP_MODE_SCHALG_MASK)
5937#define ENET_MTL_OP_MODE_CNTPRST_MASK (0x100U)
5938#define ENET_MTL_OP_MODE_CNTPRST_SHIFT (8U)
5939/*! CNTPRST - Counters Preset When this bit is set, MTL TxQ0 Underflow register (Table 762) and
5940 * MTL_TxQ1_Underflow (Table 762) registers are initialized/preset to 0x7F0.
5941 */
5942#define ENET_MTL_OP_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTPRST_SHIFT)) & ENET_MTL_OP_MODE_CNTPRST_MASK)
5943#define ENET_MTL_OP_MODE_CNTCLR_MASK (0x200U)
5944#define ENET_MTL_OP_MODE_CNTCLR_SHIFT (9U)
5945/*! CNTCLR - Counters Reset When this bit is set, all counters are reset.
5946 */
5947#define ENET_MTL_OP_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTCLR_SHIFT)) & ENET_MTL_OP_MODE_CNTCLR_MASK)
5948/*! @} */
5949
5950/*! @name MTL_INTR_STAT - MTL Interrupt Status register */
5951/*! @{ */
5952#define ENET_MTL_INTR_STAT_Q0IS_MASK (0x1U)
5953#define ENET_MTL_INTR_STAT_Q0IS_SHIFT (0U)
5954/*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0.
5955 */
5956#define ENET_MTL_INTR_STAT_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q0IS_SHIFT)) & ENET_MTL_INTR_STAT_Q0IS_MASK)
5957#define ENET_MTL_INTR_STAT_Q1IS_MASK (0x2U)
5958#define ENET_MTL_INTR_STAT_Q1IS_SHIFT (1U)
5959/*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1.
5960 */
5961#define ENET_MTL_INTR_STAT_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q1IS_SHIFT)) & ENET_MTL_INTR_STAT_Q1IS_MASK)
5962/*! @} */
5963
5964/*! @name MTL_RXQ_DMA_MAP - MTL Receive Queue and DMA Channel Mapping register */
5965/*! @{ */
5966#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK (0x1U)
5967#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT (0U)
5968/*! Q0MDMACH - Queue 0 Mapped to DMA Channel This field controls the routing of the packet received
5969 * in Queue 0 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the
5970 * Q0DDMACH field is reset.
5971 */
5972#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK)
5973#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK (0x10U)
5974#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT (4U)
5975/*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
5976 * the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC
5977 * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
5978 * Ethernet DA address.
5979 */
5980#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK)
5981#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK (0x100U)
5982#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT (8U)
5983/*! Q1MDMACH - Queue 1 Mapped to DMA Channel This field controls the routing of the received packet
5984 * in Queue 1 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the
5985 * Q1DDMACH field is reset.
5986 */
5987#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK)
5988#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK (0x1000U)
5989#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT (12U)
5990/*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
5991 * the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC
5992 * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
5993 * Ethernet DA address.
5994 */
5995#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK)
5996/*! @} */
5997
5998/*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - MTL TxQx Operation Mode register */
5999/*! @{ */
6000#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U)
6001#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U)
6002/*! FTQ - Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values.
6003 */
6004#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK)
6005#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U)
6006#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U)
6007/*! TSF - Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue.
6008 */
6009#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK)
6010#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU)
6011#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U)
6012/*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0.
6013 */
6014#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK)
6015#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U)
6016#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U)
6017/*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue.
6018 */
6019#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK)
6020#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U)
6021#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U)
6022/*! TQS - Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes.
6023 */
6024#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK)
6025/*! @} */
6026
6027/* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */
6028#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT (2U)
6029
6030/*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - MTL TxQx Underflow register */
6031/*! @{ */
6032#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU)
6033#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
6034/*! UFFRMCNT - Underflow Packet Counter This field indicates the number of packets aborted by the
6035 * controller because of Tx Queue Underflow.
6036 */
6037#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
6038#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U)
6039#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
6040/*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue
6041 * Underflow Packet Counter field overflows, that is, it has crossed the maximum count.
6042 */
6043#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
6044/*! @} */
6045
6046/* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */
6047#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT (2U)
6048
6049/*! @name MTL_QUEUE_MTL_TXQX_DBG - MTL TxQx Debug register */
6050/*! @{ */
6051#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U)
6052#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U)
6053/*! TXQPAUSED - Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it
6054 * indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because
6055 * of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue
6056 * when PFC is enabled - Reception of 802.
6057 */
6058#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK)
6059#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK (0x6U)
6060#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U)
6061/*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read
6062 * Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10:
6063 * Waiting for pending Tx Status from the MAC transmitter 11: Flushing the Tx queue because of the
6064 * Packet Abort request from the MAC.
6065 */
6066#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK)
6067#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK (0x8U)
6068#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U)
6069/*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx
6070 * Queue Write Controller is active, and it is transferring the data to the Tx Queue.
6071 */
6072#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK)
6073#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK (0x10U)
6074#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U)
6075/*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue
6076 * is not empty and some data is left for transmission.
6077 */
6078#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK)
6079#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U)
6080#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U)
6081/*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full.
6082 */
6083#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK)
6084#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK (0x70000U)
6085#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT (16U)
6086/*! PTXQ - Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue.
6087 */
6088#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK)
6089#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK (0x700000U)
6090#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT (20U)
6091/*! STSXSTSF - Number of Status Words in Tx Status FIFO of Queue This field indicates the current
6092 * number of status in the Tx Status FIFO of this queue.
6093 */
6094#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK)
6095/*! @} */
6096
6097/* The count of ENET_MTL_QUEUE_MTL_TXQX_DBG */
6098#define ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT (2U)
6099
6100/*! @name MTL_QUEUE_MTL_TXQX_ETS_CTRL - MTL TxQx ETS control register, only TxQ1 support */
6101/*! @{ */
6102#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U)
6103#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U)
6104/*! AVALG - AV Algorithm.
6105 */
6106#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK)
6107#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U)
6108#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U)
6109/*! CC - Credit Control.
6110 */
6111#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK)
6112#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U)
6113#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U)
6114/*! SLC - Credit Control.
6115 */
6116#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK)
6117/*! @} */
6118
6119/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL */
6120#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT (2U)
6121
6122/*! @name MTL_QUEUE_MTL_TXQX_ETS_STAT - MTL TxQx ETS Status register */
6123/*! @{ */
6124#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU)
6125#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U)
6126/*! ABS - Average Bits per Slot.
6127 */
6128#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK)
6129/*! @} */
6130
6131/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT */
6132#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT (2U)
6133
6134/*! @name MTL_QUEUE_MTL_TXQX_QNTM_WGHT - */
6135/*! @{ */
6136#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU)
6137#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U)
6138/*! ISCQW - Average Bits per Slot.
6139 */
6140#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)
6141/*! @} */
6142
6143/* The count of ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT */
6144#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT (2U)
6145
6146/*! @name MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT - MTL TxQx SendSlopCredit register, only TxQ1 support */
6147/*! @{ */
6148#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU)
6149#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U)
6150/*! SSC - sendSlopeCredit.
6151 */
6152#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)
6153/*! @} */
6154
6155/* The count of ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT */
6156#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U)
6157
6158/*! @name MTL_QUEUE_MTL_TXQX_HI_CRDT - MTL TxQx hiCredit register, only TxQ1 support */
6159/*! @{ */
6160#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU)
6161#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U)
6162/*! HC - hiCredit.
6163 */
6164#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK)
6165/*! @} */
6166
6167/* The count of ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT */
6168#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT (2U)
6169
6170/*! @name MTL_QUEUE_MTL_TXQX_LO_CRDT - MTL TxQx loCredit register, only TxQ1 support */
6171/*! @{ */
6172#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU)
6173#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U)
6174/*! LC - loCredit.
6175 */
6176#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK)
6177/*! @} */
6178
6179/* The count of ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT */
6180#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT (2U)
6181
6182/*! @name MTL_QUEUE_MTL_TXQX_INTCTRL_STAT - */
6183/*! @{ */
6184#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)
6185#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)
6186/*! TXUNFIS - Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue
6187 * had an underflow while transmitting the packet.
6188 */
6189#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)
6190#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)
6191#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)
6192/*! ABPSIS - Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value.
6193 */
6194#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)
6195#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)
6196#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)
6197/*! TXUIE - Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled.
6198 */
6199#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)
6200#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)
6201#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)
6202/*! ABPSIE - Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the
6203 * interrupt when the average bits per slot status is updated.
6204 */
6205#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)
6206#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)
6207#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)
6208/*! RXOVFIS - Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had
6209 * an overflow while receiving the packet.
6210 */
6211#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)
6212#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)
6213#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)
6214/*! RXOIE - Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled.
6215 */
6216#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)
6217/*! @} */
6218
6219/* The count of ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT */
6220#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_COUNT (2U)
6221
6222/*! @name MTL_QUEUE_MTL_RXQX_OP_MODE - MTL RxQx Operation Mode register */
6223/*! @{ */
6224#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U)
6225#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U)
6226/*! RTC - Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue
6227 * (in bytes): 00: 64 01: 32 10: 96 11: 128 The packet received is transferred to the
6228 * application or DMA when the packet size within the MTL Rx queue is larger than the threshold.
6229 */
6230#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK)
6231#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U)
6232#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U)
6233/*! FUP - Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized
6234 * good packets (packets with no error and length less than 64 bytes), including pad-bytes and
6235 * CRC.
6236 */
6237#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK)
6238#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U)
6239#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U)
6240/*! FEP - Forward Error Packets When this bit is reset, the Rx queue drops packets with error status
6241 * (CRC error, Mll_ER, watchdog timeout, or overflow).
6242 */
6243#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK)
6244#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U)
6245#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U)
6246/*! RSF - Receive Queue Store and Forward When this bit is set, the ethernet block on this chip
6247 * reads a packet from the Rx queue only after the complete packet has been written to it, ignoring
6248 * the RTC field of this register.
6249 */
6250#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK)
6251#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)
6252#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)
6253/*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC
6254 * does not drop the packets which only have the errors detected by the Receive Checksum Offload
6255 * engine.
6256 */
6257#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)
6258#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U)
6259#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U)
6260/*! RQS - This field indicates the size of the allocated Receive queues in blocks of 256 bytes.
6261 */
6262#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK)
6263/*! @} */
6264
6265/* The count of ENET_MTL_QUEUE_MTL_RXQX_OP_MODE */
6266#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT (2U)
6267
6268/*! @name MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT - MTL RxQx Missed Packet Overflow Counter register */
6269/*! @{ */
6270#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)
6271#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)
6272/*! OVFPKTCNT - Overflow Packet Counter This field indicates the number of packets discarded by the
6273 * Ethernet block because of Receive queue overflow.
6274 */
6275#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)
6276#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)
6277#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)
6278/*! OVFCNTOVF - Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue
6279 * Overflow Packet Counter field crossed the maximum limit.
6280 */
6281#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)
6282/*! @} */
6283
6284/* The count of ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT */
6285#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U)
6286
6287/*! @name MTL_QUEUE_MTL_RXQX_DBG - MTL RxQx Debug register */
6288/*! @{ */
6289#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK (0x1U)
6290#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U)
6291/*! RWCSTS - MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL
6292 * Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue.
6293 */
6294#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK)
6295#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK (0x6U)
6296#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U)
6297/*! RRCSTS - MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read
6298 * controller: 00: Idle state 01: Reading packet data 10: Reading packet status (or timestamp) 11:
6299 * Flushing the packet data and status.
6300 */
6301#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK)
6302#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK (0x30U)
6303#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U)
6304/*! RXQSTS - MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx
6305 * Queue: 0x0: Rx Queue empty 0x1: Rx Queue fill-level below flow-control deactivate threshold
6306 * 0x2: Rx Queue fill-level above flow-control activate threshold 0x3: Rx Queue full.
6307 */
6308#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK)
6309#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U)
6310#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT (16U)
6311/*! PRXQ - Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue.
6312 */
6313#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK)
6314/*! @} */
6315
6316/* The count of ENET_MTL_QUEUE_MTL_RXQX_DBG */
6317#define ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT (2U)
6318
6319/*! @name MTL_QUEUE_MTL_RXQX_CTRL - MTL RxQx Control register */
6320/*! @{ */
6321#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U)
6322#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U)
6323/*! RXQ_WEGT - Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0.
6324 */
6325#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK)
6326#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)
6327#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)
6328/*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration When this bit is set, the The ethernet block
6329 * drives the packet data to the ARI interface such that the entire packet data of
6330 * currently-selected queue is transmitted before switching to other queue.
6331 */
6332#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)
6333/*! @} */
6334
6335/* The count of ENET_MTL_QUEUE_MTL_RXQX_CTRL */
6336#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT (2U)
6337
6338/*! @name DMA_MODE - DMA mode register */
6339/*! @{ */
6340#define ENET_DMA_MODE_SWR_MASK (0x1U)
6341#define ENET_DMA_MODE_SWR_SHIFT (0U)
6342/*! SWR - Software Reset When this bit is set, the MAC and the OMA controller reset the logic and
6343 * all internal registers of the OMA, MTL, and MAC.
6344 */
6345#define ENET_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK)
6346#define ENET_DMA_MODE_DA_MASK (0x2U)
6347#define ENET_DMA_MODE_DA_SHIFT (1U)
6348/*! DA - DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the
6349 * Transmit and Receive paths of all channels: The Tx path has priority over the Rx path when the TXPR
6350 * bit is set.
6351 */
6352#define ENET_DMA_MODE_DA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK)
6353#define ENET_DMA_MODE_TAA_MASK (0x1CU)
6354#define ENET_DMA_MODE_TAA_SHIFT (2U)
6355/*! TAA - Transmit Arbitration Algorithm This field is used to select the arbitration algorithm for
6356 * the Transmit side when multiple Tx DMAs are selected.
6357 */
6358#define ENET_DMA_MODE_TAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK)
6359#define ENET_DMA_MODE_TXPR_MASK (0x800U)
6360#define ENET_DMA_MODE_TXPR_SHIFT (11U)
6361/*! TXPR - Transmit Priority When set, this bit indicates that the Tx DMA has higher priority than
6362 * the Rx DMA during arbitration for the system-side bus.
6363 */
6364#define ENET_DMA_MODE_TXPR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK)
6365#define ENET_DMA_MODE_PR_MASK (0x7000U)
6366#define ENET_DMA_MODE_PR_SHIFT (12U)
6367/*! PR - Priority Ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA.
6368 */
6369#define ENET_DMA_MODE_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK)
6370/*! @} */
6371
6372/*! @name DMA_SYSBUS_MODE - DMA System Bus mode */
6373/*! @{ */
6374#define ENET_DMA_SYSBUS_MODE_FB_MASK (0x1U)
6375#define ENET_DMA_SYSBUS_MODE_FB_SHIFT (0U)
6376/*! FB - Fixed Burst Length When this bit is set to 1, the AHB master will initiate burst transfers
6377 * of specified length (INCRx or SINGLE).
6378 */
6379#define ENET_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK)
6380#define ENET_DMA_SYSBUS_MODE_AAL_MASK (0x1000U)
6381#define ENET_DMA_SYSBUS_MODE_AAL_SHIFT (12U)
6382/*! AAL - Address-Aligned Beats When this bit is set to 1, the AHB master performs address-aligned
6383 * burst transfers on Read and Write channels.
6384 */
6385#define ENET_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK)
6386#define ENET_DMA_SYSBUS_MODE_MB_MASK (0x4000U)
6387#define ENET_DMA_SYSBUS_MODE_MB_SHIFT (14U)
6388/*! MB - Mixed Burst When this bit is set high and the FB bit is low, the AHB master performs
6389 * undefined bursts transfers (INCR) for burst length of 16 or more.
6390 */
6391#define ENET_DMA_SYSBUS_MODE_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK)
6392#define ENET_DMA_SYSBUS_MODE_RB_MASK (0x8000U)
6393#define ENET_DMA_SYSBUS_MODE_RB_SHIFT (15U)
6394/*! RB - Rebuild INCRx Burst When this bit is set high and the AHB master gets SPLIT, RETRY, or
6395 * EarlyBurst Termination (EBT) response, the AHB master interface rebuilds the pending beats of any
6396 * initiated burst transfer with INCRx and SINGLEtransfers.
6397 */
6398#define ENET_DMA_SYSBUS_MODE_RB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK)
6399/*! @} */
6400
6401/*! @name DMA_INTR_STAT - DMA Interrupt status */
6402/*! @{ */
6403#define ENET_DMA_INTR_STAT_DC0IS_MASK (0x1U)
6404#define ENET_DMA_INTR_STAT_DC0IS_SHIFT (0U)
6405/*! DC0IS - DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0.
6406 */
6407#define ENET_DMA_INTR_STAT_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC0IS_SHIFT)) & ENET_DMA_INTR_STAT_DC0IS_MASK)
6408#define ENET_DMA_INTR_STAT_DC1IS_MASK (0x2U)
6409#define ENET_DMA_INTR_STAT_DC1IS_SHIFT (1U)
6410/*! DC1IS - DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1.
6411 */
6412#define ENET_DMA_INTR_STAT_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC1IS_SHIFT)) & ENET_DMA_INTR_STAT_DC1IS_MASK)
6413#define ENET_DMA_INTR_STAT_MTLIS_MASK (0x10000U)
6414#define ENET_DMA_INTR_STAT_MTLIS_SHIFT (16U)
6415/*! MTLIS - MTL Interrupt Status This bit indicates an interrupt event in the MTL.
6416 */
6417#define ENET_DMA_INTR_STAT_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MTLIS_SHIFT)) & ENET_DMA_INTR_STAT_MTLIS_MASK)
6418#define ENET_DMA_INTR_STAT_MACIS_MASK (0x20000U)
6419#define ENET_DMA_INTR_STAT_MACIS_SHIFT (17U)
6420/*! MACIS - MAC Interrupt Status This bit indicates an interrupt event in the MAC.
6421 */
6422#define ENET_DMA_INTR_STAT_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MACIS_SHIFT)) & ENET_DMA_INTR_STAT_MACIS_MASK)
6423/*! @} */
6424
6425/*! @name DMA_DBG_STAT - DMA Debug Status */
6426/*! @{ */
6427#define ENET_DMA_DBG_STAT_AHSTS_MASK (0x1U)
6428#define ENET_DMA_DBG_STAT_AHSTS_SHIFT (0U)
6429/*! AHSTS - AHB Master Status When high, this bit indicates that the AHB master FSMs are in the non-idle state.
6430 */
6431#define ENET_DMA_DBG_STAT_AHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_AHSTS_SHIFT)) & ENET_DMA_DBG_STAT_AHSTS_MASK)
6432#define ENET_DMA_DBG_STAT_RPS0_MASK (0xF00U)
6433#define ENET_DMA_DBG_STAT_RPS0_SHIFT (8U)
6434/*! RPS0 - DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel
6435 * 0: 0x0: Stopped (Reset or Stop Receive Command issued) 0x1: Running (Fetching Rx Transfer )
6436 * 0x2: Reserved 0x3: Running (Waiting for Rx packet) 0x4: Suspended (Rx Unavailable) 0x5: Running
6437 * (Closing the Rx) 0x6: Timestamp write state 0x7: Running (Transferring the received packet
6438 * data from the Rx buffer to the system memory) This field does not generate an interrupt.
6439 */
6440#define ENET_DMA_DBG_STAT_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS0_SHIFT)) & ENET_DMA_DBG_STAT_RPS0_MASK)
6441#define ENET_DMA_DBG_STAT_TPS0_MASK (0xF000U)
6442#define ENET_DMA_DBG_STAT_TPS0_SHIFT (12U)
6443/*! TPS0 - DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for
6444 * Channel 0: 000: Stopped (Reset or Stop Transmit Command issued) 0x1: Running (Fetching Tx Transfer)
6445 * 0x2: Running (Waiting for status) 0x3: Running (Reading Data from system memory buffer and
6446 * queuing it to the Tx buffer (Tx FIFO)) 0x4: Timestamp write state 0x5: Reserved for future use
6447 * 0x6: Suspended (Tx Unavailable or Tx Buffer Underflow) 0x7: Running (Closing Tx ) This field
6448 * does not generate an interrupt.
6449 */
6450#define ENET_DMA_DBG_STAT_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS0_SHIFT)) & ENET_DMA_DBG_STAT_TPS0_MASK)
6451#define ENET_DMA_DBG_STAT_RPS1_MASK (0xF0000U)
6452#define ENET_DMA_DBG_STAT_RPS1_SHIFT (16U)
6453/*! RPS1 - DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1.
6454 */
6455#define ENET_DMA_DBG_STAT_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS1_SHIFT)) & ENET_DMA_DBG_STAT_RPS1_MASK)
6456#define ENET_DMA_DBG_STAT_TPS1_MASK (0xF00000U)
6457#define ENET_DMA_DBG_STAT_TPS1_SHIFT (20U)
6458/*! TPS1 - DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1.
6459 */
6460#define ENET_DMA_DBG_STAT_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS1_SHIFT)) & ENET_DMA_DBG_STAT_TPS1_MASK)
6461/*! @} */
6462
6463/*! @name DMA_CH_DMA_CHX_CTRL - DMA Channelx Control */
6464/*! @{ */
6465#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK (0x10000U)
6466#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT (16U)
6467/*! PBLx8 - 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in DMA Channel
6468 * Transmit Control Table 780 is multiplied eight times.
6469 */
6470#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK)
6471#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK (0x1C0000U)
6472#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT (18U)
6473/*! DSL - Skip Length This bit specifies the Word, Dword, or Lword number (depending on the 32- bit,
6474 * 64-bit, or 128-bit bus) to skip between two unchained s.
6475 */
6476#define ENET_DMA_CH_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK)
6477/*! @} */
6478
6479/* The count of ENET_DMA_CH_DMA_CHX_CTRL */
6480#define ENET_DMA_CH_DMA_CHX_CTRL_COUNT (2U)
6481
6482/*! @name DMA_CH_DMA_CHX_TX_CTRL - DMA Channelx Transmit Control */
6483/*! @{ */
6484#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK (0x1U)
6485#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT (0U)
6486/*! ST - Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state.
6487 */
6488#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK)
6489#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK (0xEU)
6490#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT (1U)
6491/*! TCW - Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel.
6492 */
6493#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK)
6494#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK (0x10U)
6495#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT (4U)
6496/*! OSF - Operate on Second Frame When this bit is set, it instructs the DMA to process the second
6497 * packet of the Transmit data even before the status for the first packet is obtained.
6498 */
6499#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK)
6500#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U)
6501#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U)
6502/*! TxPBL - Transmit Programmable Burst Length These bits indicate the maximum number of beats to be
6503 * transferred in one DMA data transfer.
6504 */
6505#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK)
6506/*! @} */
6507
6508/* The count of ENET_DMA_CH_DMA_CHX_TX_CTRL */
6509#define ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT (2U)
6510
6511/*! @name DMA_CH_DMA_CHX_RX_CTRL - DMA Channelx Receive Control */
6512/*! @{ */
6513#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK (0x1U)
6514#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT (0U)
6515/*! SR - Start or Stop Receive When this bit is set, the DMA tries to acquire the from the receive
6516 * list and processes the incoming packets.
6517 */
6518#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK)
6519#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK (0x7FF8U)
6520#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT (3U)
6521/*! RBSZ - Receive Buffer size This field indicates the size of the Rx buffers specified in bytes.
6522 */
6523#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK)
6524#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U)
6525#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U)
6526/*! RxPBL - Receive Programmable Burst Length These bits indicate the maximum number of beats to be
6527 * transferred in one DMA data transfer.
6528 */
6529#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK)
6530#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U)
6531#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT (31U)
6532/*! RPF - DMA Rx Channel 0 Packet Flush When this bit is set to 1, the DMA will automatically flush
6533 * the packet from the Rx Queues destined to DMA Rx Channel 0 when the DMA Rx Channel 0 is
6534 * stopped after a system bus error has occurred.
6535 */
6536#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK)
6537/*! @} */
6538
6539/* The count of ENET_DMA_CH_DMA_CHX_RX_CTRL */
6540#define ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT (2U)
6541
6542/*! @name DMA_CH_DMA_CHX_TXDESC_LIST_ADDR - */
6543/*! @{ */
6544#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK (0xFFFFFFFCU)
6545#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT (2U)
6546/*! STL - Start of transmit list This field contains the base address of the first in the Transmit list.
6547 */
6548#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK)
6549/*! @} */
6550
6551/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR */
6552#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U)
6553
6554/*! @name DMA_CH_DMA_CHX_RXDESC_LIST_ADDR - */
6555/*! @{ */
6556#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK (0xFFFFFFFCU)
6557#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT (2U)
6558/*! SRL - Start of receive list This field contains the base address of the First in the Receive list.
6559 */
6560#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK)
6561/*! @} */
6562
6563/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR */
6564#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U)
6565
6566/*! @name DMA_CH_DMA_CHX_TXDESC_TAIL_PTR - */
6567/*! @{ */
6568#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU)
6569#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U)
6570/*! TDTP - Transmit Tail Pointer This field contains the tail pointer for the Tx ring.
6571 */
6572#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)
6573/*! @} */
6574
6575/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR */
6576#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U)
6577
6578/*! @name DMA_CH_DMA_CHX_RXDESC_TAIL_PTR - */
6579/*! @{ */
6580#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU)
6581#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U)
6582/*! RDTP - Receive Tail Pointer This field contains the tail pointer for the Rx ring.
6583 */
6584#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)
6585/*! @} */
6586
6587/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR */
6588#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U)
6589
6590/*! @name DMA_CH_DMA_CHX_TXDESC_RING_LENGTH - */
6591/*! @{ */
6592#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)
6593#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
6594/*! TDRL - Transmit Ring Length This field sets the maximum number of Tx descriptors in the circular ring.
6595 */
6596#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)
6597/*! @} */
6598
6599/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH */
6600#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U)
6601
6602/*! @name DMA_CH_DMA_CHX_RXDESC_RING_LENGTH - Channelx Rx descriptor Ring Length */
6603/*! @{ */
6604#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)
6605#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)
6606/*! RDRL - Receive Ring Length This register sets the maximum number of Rx descriptors in the circular ring.
6607 */
6608#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)
6609/*! @} */
6610
6611/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH */
6612#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_COUNT (2U)
6613
6614/*! @name DMA_CH_DMA_CHX_INT_EN - Channelx Interrupt Enable */
6615/*! @{ */
6616#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK (0x1U)
6617#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT (0U)
6618/*! TIE - Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit
6619 * 16 in this register), Transmit Interrupt is enabled.
6620 */
6621#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK)
6622#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK (0x2U)
6623#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT (1U)
6624/*! TSE - Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit
6625 * 15 in this register), Transmission Stopped Interrupt is enabled.
6626 */
6627#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK)
6628#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK (0x4U)
6629#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT (2U)
6630/*! TBUE - Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary
6631 * Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled.
6632 */
6633#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK)
6634#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK (0x40U)
6635#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT (6U)
6636/*! RIE - Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16
6637 * in this register), Receive Interrupt is enabled.
6638 */
6639#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK)
6640#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK (0x80U)
6641#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT (7U)
6642/*! RBUE - Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary
6643 * Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled.
6644 */
6645#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK)
6646#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK (0x100U)
6647#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT (8U)
6648/*! RSE - Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit
6649 * 15 in this register), Receive Stopped Interrupt is enabled.
6650 */
6651#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK)
6652#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK (0x200U)
6653#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT (9U)
6654/*! RWTE - Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary
6655 * Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled.
6656 */
6657#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK)
6658#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK (0x400U)
6659#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT (10U)
6660/*! ETIE - Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary
6661 * Enable (bit 15 in this register), Early Transmit Interrupt is enabled.
6662 */
6663#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK)
6664#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK (0x800U)
6665#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT (11U)
6666/*! ERIE - Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable
6667 * (bit 16 in this register), Early Receive Interrupt is enabled.
6668 */
6669#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK)
6670#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK (0x1000U)
6671#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT (12U)
6672/*! FBEE - Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit
6673 * 15 in this register), the Fatal Bus Error Interrupt is enabled.
6674 */
6675#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK)
6676#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK (0x4000U)
6677#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT (14U)
6678/*! AIE - Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt summary is enabled.
6679 */
6680#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK)
6681#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK (0x8000U)
6682#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT (15U)
6683/*! NIE - Normal interrupt summary enable When this bit is set, a normal interrupt is enabled.
6684 */
6685#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK)
6686/*! @} */
6687
6688/* The count of ENET_DMA_CH_DMA_CHX_INT_EN */
6689#define ENET_DMA_CH_DMA_CHX_INT_EN_COUNT (2U)
6690
6691/*! @name DMA_CH_DMA_CHX_RX_INT_WDTIMER - Receive Interrupt Watchdog Timer */
6692/*! @{ */
6693#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK (0xFFU)
6694#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT (0U)
6695/*! RIWT - Receive Interrupt Watchdog Timer Count Indicates the number of system clock cycles
6696 * multiplied by 256 for which the watchdog timer is set.
6697 */
6698#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK)
6699/*! @} */
6700
6701/* The count of ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER */
6702#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_COUNT (2U)
6703
6704/*! @name DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT - Slot Function Control and Status */
6705/*! @{ */
6706#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)
6707#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)
6708/*! ESC - Enable Slot Comparison When set, this bit enables the checking of the slot numbers
6709 * programmed in the Tx descriptor with the current reference given in the RSN field.
6710 */
6711#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)
6712#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)
6713#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)
6714/*! ASC - Advance Slot Check When set, this bit enables the D MA to fetch the data from the buffer
6715 * when the slot number (SLOTNUM) programmed in the Tx descriptor is equal to the reference slot
6716 * number given in the RSN field or, ahead of the reference slot number by up to two slots This
6717 * bit is applicable only when the ESC bit is set.
6718 */
6719#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)
6720#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)
6721#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)
6722/*! RSN - Reference Slot Number This field gives the current value of the reference slot number in the DMA.
6723 */
6724#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)
6725/*! @} */
6726
6727/* The count of ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT */
6728#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U)
6729
6730/*! @name DMA_CH_DMA_CHX_CUR_HST_TXDESC - Channelx Current Host Transmit descriptor */
6731/*! @{ */
6732#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK (0xFFFFFFFFU)
6733#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT (0U)
6734/*! HTD - Host Transmit descriptor Address Pointer Cleared on Reset.
6735 */
6736#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK)
6737/*! @} */
6738
6739/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC */
6740#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_COUNT (2U)
6741
6742/*! @name DMA_CH_DMA_CHX_CUR_HST_RXDESC - */
6743/*! @{ */
6744#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK (0xFFFFFFFFU)
6745#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT (0U)
6746/*! HRD - Host Receive descriptor Address Pointer Cleared on Reset.
6747 */
6748#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK)
6749/*! @} */
6750
6751/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC */
6752#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_COUNT (2U)
6753
6754/*! @name DMA_CH_DMA_CHX_CUR_HST_TXBUF - */
6755/*! @{ */
6756#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK (0xFFFFFFFFU)
6757#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT (0U)
6758/*! HTB - Host Transmit Buffer Address Pointer Cleared on Reset.
6759 */
6760#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK)
6761/*! @} */
6762
6763/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF */
6764#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_COUNT (2U)
6765
6766/*! @name DMA_CH_DMA_CHX_CUR_HST_RXBUF - Channelx Current Application Receive Buffer Address */
6767/*! @{ */
6768#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK (0xFFFFFFFFU)
6769#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT (0U)
6770/*! HRB - Host Receive Buffer Address Pointer Cleared on Reset.
6771 */
6772#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK)
6773/*! @} */
6774
6775/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF */
6776#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_COUNT (2U)
6777
6778/*! @name DMA_CH_DMA_CHX_STAT - Channelx DMA status register */
6779/*! @{ */
6780#define ENET_DMA_CH_DMA_CHX_STAT_TI_MASK (0x1U)
6781#define ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT (0U)
6782/*! TI - Transmit Interrupt This bit indicates that the packet transmission is complete.
6783 */
6784#define ENET_DMA_CH_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK)
6785#define ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK (0x2U)
6786#define ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT (1U)
6787/*! TPS - Transmit Process Stopped This bit is set when the transmission is stopped.
6788 */
6789#define ENET_DMA_CH_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK)
6790#define ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK (0x4U)
6791#define ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT (2U)
6792/*! TBU - Transmit Buffer Unavailable This bit indicates that the application owns the next
6793 * descriptor in the transmit list, and the DMA cannot acquire it.
6794 */
6795#define ENET_DMA_CH_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK)
6796#define ENET_DMA_CH_DMA_CHX_STAT_RI_MASK (0x40U)
6797#define ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT (6U)
6798/*! RI - Receive Interrupt This bit indicates that the packet reception is complete.
6799 */
6800#define ENET_DMA_CH_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK)
6801#define ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK (0x80U)
6802#define ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT (7U)
6803/*! RBU - Receive Buffer Unavailable This bit indicates that the application owns the next in the
6804 * receive list, and the DMA cannot acquire it.
6805 */
6806#define ENET_DMA_CH_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK)
6807#define ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK (0x100U)
6808#define ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT (8U)
6809/*! RPS - Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state.
6810 */
6811#define ENET_DMA_CH_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK)
6812#define ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK (0x200U)
6813#define ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT (9U)
6814/*! RWT - Receive Watchdog time out This bit is asserted when a packet with length greater than
6815 * 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received.
6816 */
6817#define ENET_DMA_CH_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK)
6818#define ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK (0x400U)
6819#define ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT (10U)
6820/*! ETI - Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO.
6821 */
6822#define ENET_DMA_CH_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK)
6823#define ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK (0x800U)
6824#define ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT (11U)
6825/*! ERI - Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet.
6826 */
6827#define ENET_DMA_CH_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK)
6828#define ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK (0x1000U)
6829#define ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT (12U)
6830/*! FBE - Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field).
6831 */
6832#define ENET_DMA_CH_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK)
6833#define ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK (0x4000U)
6834#define ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT (14U)
6835/*! AIS - Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the
6836 * following when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable
6837 * register Table 778: Bit 1: Transmit Process Stopped Bit 7: Receive Buffer Unavailable Bit 8:
6838 * Receive Process Stopped Bit 10: Ear1y Transmit Interrupt Bit 12: Fatal Bus Error Only unmasked
6839 * bits affect the Abnormal Interrupt Summary bit.
6840 */
6841#define ENET_DMA_CH_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK)
6842#define ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK (0x8000U)
6843#define ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT (15U)
6844/*! NIS - Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the
6845 * following bits when the corresponding interrupt bits are enabled in the DMA Channel Interrupt
6846 * Enable register Table 778: Bit 0: Transmit Interrupt Bit 2: Transmit Buffer Unavailable Bit 6:
6847 * Receive Interrupt Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which
6848 * interrupt enable is set in DMA Channel Interrupt Enable register Table 778) affect the Normal
6849 * Interrupt Summary bit.
6850 */
6851#define ENET_DMA_CH_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK)
6852#define ENET_DMA_CH_DMA_CHX_STAT_EB_MASK (0x70000U)
6853#define ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT (16U)
6854/*! EB - DMA Error Bits This field indicates the type of error that caused a Bus Error.
6855 */
6856#define ENET_DMA_CH_DMA_CHX_STAT_EB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_EB_MASK)
6857/*! @} */
6858
6859/* The count of ENET_DMA_CH_DMA_CHX_STAT */
6860#define ENET_DMA_CH_DMA_CHX_STAT_COUNT (2U)
6861
6862/*! @name DMA_CH_DMA_CHX_MISS_FRAME_CNT - Channelx missed frame count. */
6863/*! @{ */
6864#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_MASK (0x7FFU)
6865#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT (0U)
6866/*! MFC - Dropped packet counters.
6867 */
6868#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT)) & ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_MASK)
6869#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U)
6870#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U)
6871/*! MFCO - Overflow status of the MFC counter.
6872 */
6873#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT)) & ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK)
6874/*! @} */
6875
6876/* The count of ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT */
6877#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_COUNT (2U)
6878
6879
6880/*!
6881 * @}
6882 */ /* end of group ENET_Register_Masks */
6883
6884
6885/* ENET - Peripheral instance base addresses */
6886/** Peripheral ENET base address */
6887#define ENET_BASE (0x40092000u)
6888/** Peripheral ENET base pointer */
6889#define ENET ((ENET_Type *)ENET_BASE)
6890/** Array initializer of ENET peripheral base addresses */
6891#define ENET_BASE_ADDRS { ENET_BASE }
6892/** Array initializer of ENET peripheral base pointers */
6893#define ENET_BASE_PTRS { ENET }
6894/** Interrupt vectors for the ENET peripheral type */
6895#define ENET_IRQS { ETHERNET_IRQn }
6896#define ENET_PMT_IRQS { ETHERNET_PMT_IRQn }
6897#define ENET_MACLP_IRQS { ETHERNET_MACLP_IRQn }
6898
6899/*!
6900 * @}
6901 */ /* end of group ENET_Peripheral_Access_Layer */
6902
6903
6904/* ----------------------------------------------------------------------------
6905 -- FLEXCOMM Peripheral Access Layer
6906 ---------------------------------------------------------------------------- */
6907
6908/*!
6909 * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
6910 * @{
6911 */
6912
6913/** FLEXCOMM - Register Layout Typedef */
6914typedef struct {
6915 uint8_t RESERVED_0[4088];
6916 __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
6917 __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */
6918} FLEXCOMM_Type;
6919
6920/* ----------------------------------------------------------------------------
6921 -- FLEXCOMM Register Masks
6922 ---------------------------------------------------------------------------- */
6923
6924/*!
6925 * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
6926 * @{
6927 */
6928
6929/*! @name PSELID - Peripheral Select and Flexcomm ID register. */
6930/*! @{ */
6931#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U)
6932#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U)
6933/*! PERSEL - Peripheral Select. This field is writable by software.
6934 * 0b000..No peripheral selected.
6935 * 0b001..USART function selected.
6936 * 0b010..SPI function selected.
6937 * 0b011..I2C function selected.
6938 * 0b100..I2S transmit function selected.
6939 * 0b101..I2S receive function selected.
6940 * 0b110..Reserved
6941 * 0b111..Reserved
6942 */
6943#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
6944#define FLEXCOMM_PSELID_LOCK_MASK (0x8U)
6945#define FLEXCOMM_PSELID_LOCK_SHIFT (3U)
6946/*! LOCK - Lock the peripheral select. This field is writable by software.
6947 * 0b0..Peripheral select can be changed by software.
6948 * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset.
6949 */
6950#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
6951#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U)
6952#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U)
6953/*! USARTPRESENT - USART present indicator. This field is Read-only.
6954 * 0b0..This Flexcomm does not include the USART function.
6955 * 0b1..This Flexcomm includes the USART function.
6956 */
6957#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
6958#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U)
6959#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U)
6960/*! SPIPRESENT - SPI present indicator. This field is Read-only.
6961 * 0b0..This Flexcomm does not include the SPI function.
6962 * 0b1..This Flexcomm includes the SPI function.
6963 */
6964#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
6965#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U)
6966#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U)
6967/*! I2CPRESENT - I2C present indicator. This field is Read-only.
6968 * 0b0..This Flexcomm does not include the I2C function.
6969 * 0b1..This Flexcomm includes the I2C function.
6970 */
6971#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
6972#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U)
6973#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U)
6974/*! I2SPRESENT - I 2S present indicator. This field is Read-only.
6975 * 0b0..This Flexcomm does not include the I2S function.
6976 * 0b1..This Flexcomm includes the I2S function.
6977 */
6978#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
6979#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U)
6980#define FLEXCOMM_PSELID_ID_SHIFT (12U)
6981/*! ID - Flexcomm ID.
6982 */
6983#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
6984/*! @} */
6985
6986/*! @name PID - Peripheral identification register. */
6987/*! @{ */
6988#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U)
6989#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U)
6990/*! Minor_Rev - Minor revision of module implementation.
6991 */
6992#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)
6993#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U)
6994#define FLEXCOMM_PID_Major_Rev_SHIFT (12U)
6995/*! Major_Rev - Major revision of module implementation.
6996 */
6997#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)
6998#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U)
6999#define FLEXCOMM_PID_ID_SHIFT (16U)
7000/*! ID - Module identifier for the selected function.
7001 */
7002#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
7003/*! @} */
7004
7005
7006/*!
7007 * @}
7008 */ /* end of group FLEXCOMM_Register_Masks */
7009
7010
7011/* FLEXCOMM - Peripheral instance base addresses */
7012/** Peripheral FLEXCOMM0 base address */
7013#define FLEXCOMM0_BASE (0x40086000u)
7014/** Peripheral FLEXCOMM0 base pointer */
7015#define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
7016/** Peripheral FLEXCOMM1 base address */
7017#define FLEXCOMM1_BASE (0x40087000u)
7018/** Peripheral FLEXCOMM1 base pointer */
7019#define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
7020/** Peripheral FLEXCOMM2 base address */
7021#define FLEXCOMM2_BASE (0x40088000u)
7022/** Peripheral FLEXCOMM2 base pointer */
7023#define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
7024/** Peripheral FLEXCOMM3 base address */
7025#define FLEXCOMM3_BASE (0x40089000u)
7026/** Peripheral FLEXCOMM3 base pointer */
7027#define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
7028/** Peripheral FLEXCOMM4 base address */
7029#define FLEXCOMM4_BASE (0x4008A000u)
7030/** Peripheral FLEXCOMM4 base pointer */
7031#define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
7032/** Peripheral FLEXCOMM5 base address */
7033#define FLEXCOMM5_BASE (0x40096000u)
7034/** Peripheral FLEXCOMM5 base pointer */
7035#define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
7036/** Peripheral FLEXCOMM6 base address */
7037#define FLEXCOMM6_BASE (0x40097000u)
7038/** Peripheral FLEXCOMM6 base pointer */
7039#define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
7040/** Peripheral FLEXCOMM7 base address */
7041#define FLEXCOMM7_BASE (0x40098000u)
7042/** Peripheral FLEXCOMM7 base pointer */
7043#define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
7044/** Peripheral FLEXCOMM8 base address */
7045#define FLEXCOMM8_BASE (0x40099000u)
7046/** Peripheral FLEXCOMM8 base pointer */
7047#define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
7048/** Peripheral FLEXCOMM9 base address */
7049#define FLEXCOMM9_BASE (0x4009A000u)
7050/** Peripheral FLEXCOMM9 base pointer */
7051#define FLEXCOMM9 ((FLEXCOMM_Type *)FLEXCOMM9_BASE)
7052/** Peripheral FLEXCOMM10 base address */
7053#define FLEXCOMM10_BASE (0x4009F000u)
7054/** Peripheral FLEXCOMM10 base pointer */
7055#define FLEXCOMM10 ((FLEXCOMM_Type *)FLEXCOMM10_BASE)
7056/** Array initializer of FLEXCOMM peripheral base addresses */
7057#define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE, FLEXCOMM10_BASE }
7058/** Array initializer of FLEXCOMM peripheral base pointers */
7059#define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9, FLEXCOMM10 }
7060/** Interrupt vectors for the FLEXCOMM peripheral type */
7061#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn, FLEXCOMM10_IRQn }
7062
7063/*!
7064 * @}
7065 */ /* end of group FLEXCOMM_Peripheral_Access_Layer */
7066
7067
7068/* ----------------------------------------------------------------------------
7069 -- GINT Peripheral Access Layer
7070 ---------------------------------------------------------------------------- */
7071
7072/*!
7073 * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer
7074 * @{
7075 */
7076
7077/** GINT - Register Layout Typedef */
7078typedef struct {
7079 __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */
7080 uint8_t RESERVED_0[28];
7081 __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */
7082 uint8_t RESERVED_1[24];
7083 __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */
7084} GINT_Type;
7085
7086/* ----------------------------------------------------------------------------
7087 -- GINT Register Masks
7088 ---------------------------------------------------------------------------- */
7089
7090/*!
7091 * @addtogroup GINT_Register_Masks GINT Register Masks
7092 * @{
7093 */
7094
7095/*! @name CTRL - GPIO grouped interrupt control register */
7096/*! @{ */
7097#define GINT_CTRL_INT_MASK (0x1U)
7098#define GINT_CTRL_INT_SHIFT (0U)
7099/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.
7100 * 0b0..No request. No interrupt request is pending.
7101 * 0b1..Request active. Interrupt request is active.
7102 */
7103#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)
7104#define GINT_CTRL_COMB_MASK (0x2U)
7105#define GINT_CTRL_COMB_SHIFT (1U)
7106/*! COMB - Combine enabled inputs for group interrupt
7107 * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).
7108 * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).
7109 */
7110#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)
7111#define GINT_CTRL_TRIG_MASK (0x4U)
7112#define GINT_CTRL_TRIG_SHIFT (2U)
7113/*! TRIG - Group interrupt trigger
7114 * 0b0..Edge-triggered.
7115 * 0b1..Level-triggered.
7116 */
7117#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)
7118/*! @} */
7119
7120/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */
7121/*! @{ */
7122#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU)
7123#define GINT_PORT_POL_POL_SHIFT (0U)
7124/*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n
7125 * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to
7126 * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin
7127 * contributes to the group interrupt.
7128 */
7129#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)
7130/*! @} */
7131
7132/* The count of GINT_PORT_POL */
7133#define GINT_PORT_POL_COUNT (2U)
7134
7135/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */
7136/*! @{ */
7137#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU)
7138#define GINT_PORT_ENA_ENA_SHIFT (0U)
7139/*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the
7140 * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is
7141 * enabled and contributes to the grouped interrupt.
7142 */
7143#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)
7144/*! @} */
7145
7146/* The count of GINT_PORT_ENA */
7147#define GINT_PORT_ENA_COUNT (2U)
7148
7149
7150/*!
7151 * @}
7152 */ /* end of group GINT_Register_Masks */
7153
7154
7155/* GINT - Peripheral instance base addresses */
7156/** Peripheral GINT0 base address */
7157#define GINT0_BASE (0x40002000u)
7158/** Peripheral GINT0 base pointer */
7159#define GINT0 ((GINT_Type *)GINT0_BASE)
7160/** Peripheral GINT1 base address */
7161#define GINT1_BASE (0x40003000u)
7162/** Peripheral GINT1 base pointer */
7163#define GINT1 ((GINT_Type *)GINT1_BASE)
7164/** Array initializer of GINT peripheral base addresses */
7165#define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE }
7166/** Array initializer of GINT peripheral base pointers */
7167#define GINT_BASE_PTRS { GINT0, GINT1 }
7168/** Interrupt vectors for the GINT peripheral type */
7169#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn }
7170
7171/*!
7172 * @}
7173 */ /* end of group GINT_Peripheral_Access_Layer */
7174
7175
7176/* ----------------------------------------------------------------------------
7177 -- GPIO Peripheral Access Layer
7178 ---------------------------------------------------------------------------- */
7179
7180/*!
7181 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
7182 * @{
7183 */
7184
7185/** GPIO - Register Layout Typedef */
7186typedef struct {
7187 __IO uint8_t B[6][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
7188 uint8_t RESERVED_0[3904];
7189 __IO uint32_t W[6][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
7190 uint8_t RESERVED_1[3328];
7191 __IO uint32_t DIR[6]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */
7192 uint8_t RESERVED_2[104];
7193 __IO uint32_t MASK[6]; /**< Mask register, array offset: 0x2080, array step: 0x4 */
7194 uint8_t RESERVED_3[104];
7195 __IO uint32_t PIN[6]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */
7196 uint8_t RESERVED_4[104];
7197 __IO uint32_t MPIN[6]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */
7198 uint8_t RESERVED_5[104];
7199 __IO uint32_t SET[6]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
7200 uint8_t RESERVED_6[104];
7201 __O uint32_t CLR[6]; /**< Clear port, array offset: 0x2280, array step: 0x4 */
7202 uint8_t RESERVED_7[104];
7203 __O uint32_t NOT[6]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */
7204 uint8_t RESERVED_8[104];
7205 __O uint32_t DIRSET[6]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
7206 uint8_t RESERVED_9[104];
7207 __O uint32_t DIRCLR[6]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
7208 uint8_t RESERVED_10[104];
7209 __O uint32_t DIRNOT[6]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
7210} GPIO_Type;
7211
7212/* ----------------------------------------------------------------------------
7213 -- GPIO Register Masks
7214 ---------------------------------------------------------------------------- */
7215
7216/*!
7217 * @addtogroup GPIO_Register_Masks GPIO Register Masks
7218 * @{
7219 */
7220
7221/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
7222/*! @{ */
7223#define GPIO_B_PBYTE_MASK (0x1U)
7224#define GPIO_B_PBYTE_SHIFT (0U)
7225/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function,
7226 * except that pins configured as analog I/O always read as 0. One register for each port pin.
7227 * Supported pins depends on the specific device and package. Write: loads the pin's output bit.
7228 * One register for each port pin. Supported pins depends on the specific device and package.
7229 */
7230#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
7231/*! @} */
7232
7233/* The count of GPIO_B */
7234#define GPIO_B_COUNT (6U)
7235
7236/* The count of GPIO_B */
7237#define GPIO_B_COUNT2 (32U)
7238
7239/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
7240/*! @{ */
7241#define GPIO_W_PWORD_MASK (0xFFFFFFFFU)
7242#define GPIO_W_PWORD_SHIFT (0U)
7243/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is
7244 * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be
7245 * read. Writing any value other than 0 will set the output bit. One register for each port pin.
7246 * Supported pins depends on the specific device and package.
7247 */
7248#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
7249/*! @} */
7250
7251/* The count of GPIO_W */
7252#define GPIO_W_COUNT (6U)
7253
7254/* The count of GPIO_W */
7255#define GPIO_W_COUNT2 (32U)
7256
7257/*! @name DIR - Direction registers */
7258/*! @{ */
7259#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU)
7260#define GPIO_DIR_DIRP_SHIFT (0U)
7261/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
7262 * pins depends on the specific device and package. 0 = input. 1 = output.
7263 */
7264#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
7265/*! @} */
7266
7267/* The count of GPIO_DIR */
7268#define GPIO_DIR_COUNT (6U)
7269
7270/*! @name MASK - Mask register */
7271/*! @{ */
7272#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU)
7273#define GPIO_MASK_MASKP_SHIFT (0U)
7274/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 =
7275 * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 =
7276 * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit
7277 * not affected.
7278 */
7279#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
7280/*! @} */
7281
7282/* The count of GPIO_MASK */
7283#define GPIO_MASK_COUNT (6U)
7284
7285/*! @name PIN - Port pin register */
7286/*! @{ */
7287#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU)
7288#define GPIO_PIN_PORT_SHIFT (0U)
7289/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
7290 * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit.
7291 * 1 = Read: pin is high; write: set output bit.
7292 */
7293#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
7294/*! @} */
7295
7296/* The count of GPIO_PIN */
7297#define GPIO_PIN_COUNT (6U)
7298
7299/*! @name MPIN - Masked port register */
7300/*! @{ */
7301#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU)
7302#define GPIO_MPIN_MPORTP_SHIFT (0U)
7303/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
7304 * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK
7305 * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1
7306 * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit
7307 * if the corresponding bit in the MASK register is 0.
7308 */
7309#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
7310/*! @} */
7311
7312/* The count of GPIO_MPIN */
7313#define GPIO_MPIN_COUNT (6U)
7314
7315/*! @name SET - Write: Set register for port Read: output bits for port */
7316/*! @{ */
7317#define GPIO_SET_SETP_MASK (0xFFFFFFFFU)
7318#define GPIO_SET_SETP_SHIFT (0U)
7319/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
7320 * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output
7321 * bit; write: set output bit.
7322 */
7323#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
7324/*! @} */
7325
7326/* The count of GPIO_SET */
7327#define GPIO_SET_COUNT (6U)
7328
7329/*! @name CLR - Clear port */
7330/*! @{ */
7331#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU)
7332#define GPIO_CLR_CLRP_SHIFT (0U)
7333/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
7334 * specific device and package. 0 = No operation. 1 = Clear output bit.
7335 */
7336#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
7337/*! @} */
7338
7339/* The count of GPIO_CLR */
7340#define GPIO_CLR_COUNT (6U)
7341
7342/*! @name NOT - Toggle port */
7343/*! @{ */
7344#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU)
7345#define GPIO_NOT_NOTP_SHIFT (0U)
7346/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
7347 * specific device and package. 0 = no operation. 1 = Toggle output bit.
7348 */
7349#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
7350/*! @} */
7351
7352/* The count of GPIO_NOT */
7353#define GPIO_NOT_COUNT (6U)
7354
7355/*! @name DIRSET - Set pin direction bits for port */
7356/*! @{ */
7357#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU)
7358#define GPIO_DIRSET_DIRSETP_SHIFT (0U)
7359/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
7360 * the specific device and package. 0 = No operation. 1 = Set direction bit.
7361 */
7362#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
7363/*! @} */
7364
7365/* The count of GPIO_DIRSET */
7366#define GPIO_DIRSET_COUNT (6U)
7367
7368/*! @name DIRCLR - Clear pin direction bits for port */
7369/*! @{ */
7370#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU)
7371#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U)
7372/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
7373 * the specific device and package. 0 = No operation. 1 = Clear direction bit.
7374 */
7375#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
7376/*! @} */
7377
7378/* The count of GPIO_DIRCLR */
7379#define GPIO_DIRCLR_COUNT (6U)
7380
7381/*! @name DIRNOT - Toggle pin direction bits for port */
7382/*! @{ */
7383#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU)
7384#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U)
7385/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends
7386 * on the specific device and package. 0 = no operation. 1 = Toggle direction bit.
7387 */
7388#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
7389/*! @} */
7390
7391/* The count of GPIO_DIRNOT */
7392#define GPIO_DIRNOT_COUNT (6U)
7393
7394
7395/*!
7396 * @}
7397 */ /* end of group GPIO_Register_Masks */
7398
7399
7400/* GPIO - Peripheral instance base addresses */
7401/** Peripheral GPIO base address */
7402#define GPIO_BASE (0x4008C000u)
7403/** Peripheral GPIO base pointer */
7404#define GPIO ((GPIO_Type *)GPIO_BASE)
7405/** Array initializer of GPIO peripheral base addresses */
7406#define GPIO_BASE_ADDRS { GPIO_BASE }
7407/** Array initializer of GPIO peripheral base pointers */
7408#define GPIO_BASE_PTRS { GPIO }
7409
7410/*!
7411 * @}
7412 */ /* end of group GPIO_Peripheral_Access_Layer */
7413
7414
7415/* ----------------------------------------------------------------------------
7416 -- I2C Peripheral Access Layer
7417 ---------------------------------------------------------------------------- */
7418
7419/*!
7420 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
7421 * @{
7422 */
7423
7424/** I2C - Register Layout Typedef */
7425typedef struct {
7426 uint8_t RESERVED_0[2048];
7427 __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */
7428 __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */
7429 __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */
7430 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */
7431 __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */
7432 __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */
7433 __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */
7434 uint8_t RESERVED_1[4];
7435 __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */
7436 __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */
7437 __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */
7438 uint8_t RESERVED_2[20];
7439 __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */
7440 __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */
7441 __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */
7442 __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */
7443 uint8_t RESERVED_3[36];
7444 __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */
7445 uint8_t RESERVED_4[1912];
7446 __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
7447} I2C_Type;
7448
7449/* ----------------------------------------------------------------------------
7450 -- I2C Register Masks
7451 ---------------------------------------------------------------------------- */
7452
7453/*!
7454 * @addtogroup I2C_Register_Masks I2C Register Masks
7455 * @{
7456 */
7457
7458/*! @name CFG - Configuration for shared functions. */
7459/*! @{ */
7460#define I2C_CFG_MSTEN_MASK (0x1U)
7461#define I2C_CFG_MSTEN_SHIFT (0U)
7462/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not
7463 * changed, but the Master function is internally reset.
7464 * 0b0..Disabled. The I2C Master function is disabled.
7465 * 0b1..Enabled. The I2C Master function is enabled.
7466 */
7467#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
7468#define I2C_CFG_SLVEN_MASK (0x2U)
7469#define I2C_CFG_SLVEN_SHIFT (1U)
7470/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not
7471 * changed, but the Slave function is internally reset.
7472 * 0b0..Disabled. The I2C slave function is disabled.
7473 * 0b1..Enabled. The I2C slave function is enabled.
7474 */
7475#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
7476#define I2C_CFG_MONEN_MASK (0x4U)
7477#define I2C_CFG_MONEN_SHIFT (2U)
7478/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not
7479 * changed, but the Monitor function is internally reset.
7480 * 0b0..Disabled. The I2C Monitor function is disabled.
7481 * 0b1..Enabled. The I2C Monitor function is enabled.
7482 */
7483#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
7484#define I2C_CFG_TIMEOUTEN_MASK (0x8U)
7485#define I2C_CFG_TIMEOUTEN_SHIFT (3U)
7486/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
7487 * 0b0..Disabled. Time-out function is disabled.