1 files changed, 86 insertions, 0 deletions

diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54113/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54113/project_template/board.c
new file mode 100644
index 000000000..32132333d
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54113/project_template/board.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include "fsl_common.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+
+#ifdef SDK_PRIMARY_CORE
+/* Address of RAM, where the image for core1 should be copied */
+#define CORE1_BOOT_ADDRESS (void *)0x20010000
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+extern uint32_t Image$$CORE1_REGION$$Base;
+extern uint32_t Image$$CORE1_REGION$$Length;
+#define CORE1_IMAGE_START &Image$$CORE1_REGION$$Base
+#elif defined(__ICCARM__)
+extern unsigned char core1_image_start[];
+#define CORE1_IMAGE_START core1_image_start
+#endif
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Clock rate on the CLKIN pin */
+const uint32_t ExtClockIn = BOARD_EXTCLKINRATE;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+status_t BOARD_InitDebugConsole(void)
+{
+#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))
+    status_t result;
+
+    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+    CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
+
+    RESET_PeripheralReset(BOARD_DEBUG_UART_RST);
+    result = DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM,
+                             BOARD_DEBUG_UART_CLK_FREQ);
+    assert(kStatus_Success == result);
+    return result;
+#else
+    return kStatus_Success;
+#endif
+}
+
+#ifdef SDK_PRIMARY_CORE
+/* Start the secondary core. */
+void BOARD_StartSecondaryCore(void)
+{
+/* Calculate size of the secondary core image - not required on MCUXpresso. MCUXpresso copies the image to RAM during
+ * startup
+ * automatically */
+#if (defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__ICCARM__))
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+    uint32_t core1_image_size = (uint32_t)&Image$$CORE1_REGION$$Length;
+#elif defined(__ICCARM__)
+#pragma section = "__sec_core"
+    uint32_t core1_image_size = (uint32_t)__section_end("__sec_core") - (uint32_t)&core1_image_start;
+#endif
+
+    /* Copy core1 application from FLASH to RAM. Primary core code is executed from FLASH, Secondary from RAM
+     * for maximal effectivity.*/
+    memcpy(CORE1_BOOT_ADDRESS, (void *)CORE1_IMAGE_START, core1_image_size);
+#endif
+    /* Boot source for Core 1 from RAM */
+    SYSCON->CPBOOT  = SYSCON_CPBOOT_BOOTADDR(*(uint32_t *)((uint8_t *)CORE1_BOOT_ADDRESS + 0x4));
+    SYSCON->CPSTACK = SYSCON_CPSTACK_STACKADDR(*(uint32_t *)CORE1_BOOT_ADDRESS);
+
+    uint32_t temp = SYSCON->CPUCTRL;
+    temp |= 0xc0c48000U;
+    SYSCON->CPUCTRL = temp | SYSCON_CPUCTRL_CM0RSTEN_MASK | SYSCON_CPUCTRL_CM0CLKEN_MASK;
+    SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CM0CLKEN_MASK) & (~SYSCON_CPUCTRL_CM0RSTEN_MASK);
+}
+#endif