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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54114/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54114/drivers/fsl_clock.h
new file mode 100644
index 000000000..68647d2f6
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54114/drivers/fsl_clock.h
@@ -0,0 +1,876 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2019 , NXP
4 * All rights reserved.
5 *
6 *
7 * SPDX-License-Identifier: BSD-3-Clause
8 */
9
10#ifndef _FSL_CLOCK_H_
11#define _FSL_CLOCK_H_
12
13#include "fsl_common.h"
14
15/*! @addtogroup clock */
16/*! @{ */
17
18/*! @file */
19
20/*******************************************************************************
21 * Definitions
22 *****************************************************************************/
23
24/*! @name Driver version */
25/*@{*/
26/*! @brief CLOCK driver version 2.5.1. */
27#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
28/*@}*/
29
30/*!
31 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
32 *
33 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
34 * would cache the recent calulation and accelerate the execution to get the
35 * right settings.
36 */
37#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
38#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
39#endif
40
41/* Definition for delay API in clock driver, users can redefine it to the real application. */
42#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
43#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (150000000UL)
44#endif
45
46/*! @brief Clock ip name array for FLEXCOMM. */
47#define FLEXCOMM_CLOCKS \
48 { \
49 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
50 kCLOCK_FlexComm6, kCLOCK_FlexComm7 \
51 }
52/*! @brief Clock ip name array for LPUART. */
53#define LPUART_CLOCKS \
54 { \
55 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
56 kCLOCK_MinUart6, kCLOCK_MinUart7 \
57 }
58
59/*! @brief Clock ip name array for BI2C. */
60#define BI2C_CLOCKS \
61 { \
62 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \
63 }
64/*! @brief Clock ip name array for LSPI. */
65#define LPSI_CLOCKS \
66 { \
67 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \
68 }
69/*! @brief Clock ip name array for FLEXI2S. */
70#define FLEXI2S_CLOCKS \
71 { \
72 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
73 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \
74 }
75/*! @brief Clock ip name array for UTICK. */
76#define UTICK_CLOCKS \
77 { \
78 kCLOCK_Utick \
79 }
80/*! @brief Clock ip name array for DMIC. */
81#define DMIC_CLOCKS \
82 { \
83 kCLOCK_DMic \
84 }
85/*! @brief Clock ip name array for DMA. */
86#define DMA_CLOCKS \
87 { \
88 kCLOCK_Dma \
89 }
90/*! @brief Clock ip name array for CT32B. */
91#define CTIMER_CLOCKS \
92 { \
93 kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
94 }
95
96/*! @brief Clock ip name array for GPIO. */
97#define GPIO_CLOCKS \
98 { \
99 kCLOCK_Gpio0, kCLOCK_Gpio1 \
100 }
101/*! @brief Clock ip name array for ADC. */
102#define ADC_CLOCKS \
103 { \
104 kCLOCK_Adc0 \
105 }
106/*! @brief Clock ip name array for MRT. */
107#define MRT_CLOCKS \
108 { \
109 kCLOCK_Mrt \
110 }
111/*! @brief Clock ip name array for MRT. */
112#define SCT_CLOCKS \
113 { \
114 kCLOCK_Sct0 \
115 }
116/*! @brief Clock ip name array for RTC. */
117#define RTC_CLOCKS \
118 { \
119 kCLOCK_Rtc \
120 }
121/*! @brief Clock ip name array for WWDT. */
122#define WWDT_CLOCKS \
123 { \
124 kCLOCK_Wwdt \
125 }
126/*! @brief Clock ip name array for CRC. */
127#define CRC_CLOCKS \
128 { \
129 kCLOCK_Crc \
130 }
131/*! @brief Clock ip name array for USBD. */
132#define USBD_CLOCKS \
133 { \
134 kCLOCK_Usbd0 \
135 }
136
137/*! @brief Clock ip name array for GINT. GINT0 & GINT1 share same slot */
138#define GINT_CLOCKS \
139 { \
140 kCLOCK_Gint, kCLOCK_Gint \
141 }
142
143/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
144/*------------------------------------------------------------------------------
145 clock_ip_name_t definition:
146------------------------------------------------------------------------------*/
147
148#define CLK_GATE_REG_OFFSET_SHIFT 8U
149#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
150#define CLK_GATE_BIT_SHIFT_SHIFT 0U
151#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
152
153#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
154 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
155 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
156
157#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
158#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
159
160#define AHB_CLK_CTRL0 0
161#define AHB_CLK_CTRL1 1
162#define ASYNC_CLK_CTRL0 2
163
164/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
165typedef enum _clock_ip_name
166{
167 kCLOCK_IpInvalid = 0U,
168 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
169 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
170 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
171 kCLOCK_Regfile = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6),
172 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),
173 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),
174 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
175 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
176 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
177 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
178 kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),
179 kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),
180 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
181 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /* GPIO_GLOBALINT0 and GPIO_GLOBALINT1 share the same slot */
182 kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
183 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
184 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
185 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
186 kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26),
187 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
188 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
189 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
190 kCLOCK_SctIpu0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 6),
191 kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
192 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
193 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
194 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
195 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
196 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
197 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
198 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
199 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
200 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
201 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
202 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
203 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
204 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
205 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
206 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
207 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
208 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
209 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
210 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
211 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
212 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
213 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
214 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
215 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
216 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
217 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
218 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
219 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
220 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
221 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
222 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
223 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
224 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
225 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
226 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
227 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
228 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
229 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
230 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
231 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
232 kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19),
233 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
234 kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
235 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
236 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
237 kCLOCK_Pvtvf0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28),
238 kCLOCK_Pvtvf1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28),
239 kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29),
240 kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
241
242 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13),
243 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14)
244} clock_ip_name_t;
245
246/*! @brief Clock name used to get clock frequency. */
247typedef enum _clock_name
248{
249 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
250 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
251 kCLOCK_FroHf, /*!< FRO48/96 */
252 kCLOCK_Fro12M, /*!< FRO12M */
253 kCLOCK_ExtClk, /*!< External Clock */
254 kCLOCK_PllOut, /*!< PLL Output */
255 kCLOCK_UsbClk, /*!< USB input */
256 kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
257 kCLOCK_Frg, /*!< Frg Clock */
258 kCLOCK_AsyncApbClk, /*!< Async APB clock */
259 kCLOCK_FlexI2S, /*!< FlexI2S clock */
260} clock_name_t;
261
262/**
263 * Clock source selections for the asynchronous APB clock
264 */
265typedef enum _async_clock_src
266{
267 kCLOCK_AsyncMainClk = 0, /*!< Main System clock */
268 kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */
269} async_clock_src_t;
270
271/*! @brief Clock Mux Switches
272 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
273 * starting from LSB upwards
274 *
275 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
276 *
277 */
278
279#define CLK_ATTACH_ID(mux, sel, pos) ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1UL) & 0xFU) << 8U) << ((pos)*12U))
280#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
281#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
282
283#define GET_ID_ITEM(connection) ((connection)&0xFFFU)
284#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
285#define GET_ID_ITEM_MUX(connection) (((uint8_t)(connection)) & 0xFFU)
286#define GET_ID_ITEM_SEL(connection) (uint8_t)(((((uint32_t)(connection)&0xF00U) >> 8U) - 1U))
287#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
288
289#define CM_MAINCLKSELA 0
290#define CM_MAINCLKSELB 1
291#define CM_CLKOUTCLKSELA 2
292#define CM_CLKOUTCLKSELB 3
293#define CM_SYSPLLCLKSEL 4
294#define CM_USBPLLCLKSEL 5
295#define CM_AUDPLLCLKSEL 6
296#define CM_SCTPLLCLKSEL 7
297#define CM_SPIFICLKSEL 8
298#define CM_ADCASYNCCLKSEL 9
299#define CM_USBCLKSEL 10
300#define CM_USB1CLKSEL 11
301#define CM_FXCOMCLKSEL0 12
302#define CM_FXCOMCLKSEL1 13
303#define CM_FXCOMCLKSEL2 14
304#define CM_FXCOMCLKSEL3 15
305#define CM_FXCOMCLKSEL4 16
306#define CM_FXCOMCLKSEL5 17
307#define CM_FXCOMCLKSEL6 18
308#define CM_FXCOMCLKSEL7 19
309#define CM_FXCOMCLKSEL8 20
310#define CM_FXCOMCLKSEL9 21
311#define CM_FXCOMCLKSEL10 22
312#define CM_FXCOMCLKSEL11 23
313#define CM_FXI2S0MCLKCLKSEL 24
314#define CM_FXI2S1MCLKCLKSEL 25
315#define CM_FRGCLKSEL 26
316#define CM_DMICCLKSEL 27
317
318#define CM_ASYNCAPB 28U
319
320typedef enum _clock_attach_id
321{
322
323 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),
324 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),
325 kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),
326 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),
327 kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),
328 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),
329
330 kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0),
331 kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),
332 kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2),
333 kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3),
334 kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7),
335
336 kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0),
337 kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1),
338
339 kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
340 kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
341 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
342 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
343
344 kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0),
345 kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1),
346 kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3),
347 kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7),
348
349 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
350 kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
351 kSYS_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
352 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
353 kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
354 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
355
356 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
357 kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
358 kSYS_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
359 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
360 kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
361 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
362
363 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
364 kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
365 kSYS_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
366 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
367 kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
368 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
369
370 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
371 kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
372 kSYS_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
373 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
374 kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
375 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
376
377 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
378 kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
379 kSYS_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
380 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
381 kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
382 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
383
384 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
385 kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
386 kSYS_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
387 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
388 kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
389 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
390
391 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
392 kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
393 kSYS_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
394 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
395 kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
396 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
397
398 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
399 kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
400 kSYS_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
401 kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
402 kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
403 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
404
405 kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0),
406 kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1),
407 kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2),
408 kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3),
409 kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7),
410
411 kFRO_HF_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 0),
412 kSYS_PLL_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 1),
413 kMAIN_CLK_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 2),
414 kNONE_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 7),
415
416 kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0),
417 kFRO_HF_to_DMIC = MUX_A(CM_DMICCLKSEL, 1),
418 kSYS_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2),
419 kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3),
420 kMAIN_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 4),
421 kWDT_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 5),
422 kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7),
423
424 kFRO_HF_to_USB_CLK = MUX_A(CM_USBCLKSEL, 0),
425 kSYS_PLL_to_USB_CLK = MUX_A(CM_USBCLKSEL, 1),
426 kMAIN_CLK_to_USB_CLK = MUX_A(CM_USBCLKSEL, 2),
427 kNONE_to_USB_CLK = MUX_A(CM_USBCLKSEL, 7),
428
429 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0),
430 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1),
431 kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2),
432 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3),
433 kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4),
434 kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5),
435 kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6),
436 kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7),
437 kNONE_to_NONE = (int)0x80000000U,
438} clock_attach_id_t;
439
440/* Clock dividers */
441typedef enum _clock_div_name
442{
443 kCLOCK_DivSystickClk = 0,
444 kCLOCK_DivTraceClk = 1,
445 kCLOCK_DivAhbClk = 32,
446 kCLOCK_DivClkOut = 33,
447 kCLOCK_DivSpifiClk = 36,
448 kCLOCK_DivAdcAsyncClk = 37,
449 kCLOCK_DivUsbClk = 38,
450 kCLOCK_DivFrg = 40,
451 kCLOCK_DivDmicClk = 42,
452 kCLOCK_DivFxI2s0MClk = 43
453} clock_div_name_t;
454
455/*******************************************************************************
456 * API
457 ******************************************************************************/
458
459#if defined(__cplusplus)
460extern "C" {
461#endif /* __cplusplus */
462
463static inline void CLOCK_EnableClock(clock_ip_name_t clk)
464{
465 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
466 if (index < 2UL)
467 {
468 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
469 }
470 else
471 {
472 ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
473 }
474}
475
476static inline void CLOCK_DisableClock(clock_ip_name_t clk)
477{
478 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
479 if (index < 2UL)
480 {
481 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
482 }
483 else
484 {
485 ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
486 }
487}
488/**
489 * @brief FLASH Access time definitions
490 */
491typedef enum _clock_flashtim
492{
493 kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clock */
494 kCLOCK_Flash2Cycle, /*!< Flash accesses use 2 CPU clocks */
495 kCLOCK_Flash3Cycle, /*!< Flash accesses use 3 CPU clocks */
496 kCLOCK_Flash4Cycle, /*!< Flash accesses use 4 CPU clocks */
497 kCLOCK_Flash5Cycle, /*!< Flash accesses use 5 CPU clocks */
498 kCLOCK_Flash6Cycle, /*!< Flash accesses use 6 CPU clocks */
499 kCLOCK_Flash7Cycle, /*!< Flash accesses use 7 CPU clocks */
500} clock_flashtim_t;
501
502/**
503 * @brief Set FLASH memory access time in clocks
504 * @param clks : Clock cycles for FLASH access
505 * @return Nothing
506 */
507static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks)
508{
509 uint32_t tmp;
510
511 tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK);
512
513 /* Don't alter lower bits */
514 SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT);
515}
516
517/**
518 * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
519 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
520 * enabled.
521 * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)
522 * @return returns success or fail status.
523 */
524status_t CLOCK_SetupFROClocking(uint32_t iFreq);
525/**
526 * @brief Configure the clock selection muxes.
527 * @param connection : Clock to be configured.
528 * @return Nothing
529 */
530void CLOCK_AttachClk(clock_attach_id_t connection);
531/**
532 * @brief Get the actual clock attach id.
533 * This fuction uses the offset in input attach id, then it reads the actual source value in
534 * the register and combine the offset to obtain an actual attach id.
535 * @param attachId : Clock attach id to get.
536 * @return Clock source value.
537 */
538clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
539/**
540 * @brief Setup peripheral clock dividers.
541 * @param div_name : Clock divider name
542 * @param divided_by_value: Value to be divided
543 * @param reset : Whether to reset the divider counter.
544 * @return Nothing
545 */
546void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
547/**
548 * @brief Set the flash wait states for the input freuqency.
549 * @param iFreq : Input frequency
550 * @return Nothing
551 */
552void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);
553/*! @brief Return Frequency of selected clock
554 * @return Frequency of selected clock
555 */
556uint32_t CLOCK_GetFreq(clock_name_t clockName);
557
558/*! @brief Return Input frequency for the Fractional baud rate generator
559 * @return Input Frequency for FRG
560 */
561uint32_t CLOCK_GetFRGInputClock(void);
562
563/*! @brief Return Input frequency for the DMIC
564 * @return Input Frequency for DMIC
565 */
566uint32_t CLOCK_GetDmicClkFreq(void);
567
568/*! @brief Return Input frequency for the FRG
569 * @return Input Frequency for FRG
570 */
571uint32_t CLOCK_GetFrgClkFreq(void);
572
573/*! @brief Set output of the Fractional baud rate generator
574 * @param freq : Desired output frequency
575 * @return Error Code 0 - fail 1 - success
576 */
577uint32_t CLOCK_SetFRGClock(uint32_t freq);
578
579/*! @brief Return Frequency of FRO 12MHz
580 * @return Frequency of FRO 12MHz
581 */
582uint32_t CLOCK_GetFro12MFreq(void);
583/*! @brief Return Frequency of External Clock
584 * @return Frequency of External Clock. If no external clock is used returns 0.
585 */
586uint32_t CLOCK_GetExtClkFreq(void);
587/*! @brief Return Frequency of Watchdog Oscillator
588 * @return Frequency of Watchdog Oscillator
589 */
590uint32_t CLOCK_GetWdtOscFreq(void);
591/*! @brief Return Frequency of High-Freq output of FRO
592 * @return Frequency of High-Freq output of FRO
593 */
594uint32_t CLOCK_GetFroHfFreq(void);
595/*! @brief Return Frequency of USB
596 * @return Frequency of USB
597 */
598uint32_t CLOCK_GetUsbClkFreq(void);
599/*! @brief Return Frequency of PLL
600 * @return Frequency of PLL
601 */
602uint32_t CLOCK_GetPllOutFreq(void);
603/*! @brief Return Frequency of 32kHz osc
604 * @return Frequency of 32kHz osc
605 */
606uint32_t CLOCK_GetOsc32KFreq(void);
607/*! @brief Return Frequency of Core System
608 * @return Frequency of Core System
609 */
610uint32_t CLOCK_GetCoreSysClkFreq(void);
611/*! @brief Return Frequency of I2S MCLK Clock
612 * @return Frequency of I2S MCLK Clock
613 */
614uint32_t CLOCK_GetI2SMClkFreq(void);
615/*! @brief Return Frequency of Flexcomm functional Clock
616 * @return Frequency of Flexcomm functional Clock
617 */
618uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
619/*! @brief Return Frequency of Adc Clock
620 * @return Frequency of Adc Clock.
621 */
622uint32_t CLOCK_GetAdcClkFreq(void);
623/*! @brief Return Asynchronous APB Clock source
624 * @return Asynchronous APB CLock source
625 */
626__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)
627{
628 return (async_clock_src_t)((uint32_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3UL));
629}
630/*! @brief Return Frequency of Asynchronous APB Clock
631 * @return Frequency of Asynchronous APB Clock Clock
632 */
633uint32_t CLOCK_GetAsyncApbClkFreq(void);
634/*! @brief Return System PLL input clock rate
635 * @return System PLL input clock rate
636 */
637uint32_t CLOCK_GetSystemPLLInClockRate(void);
638
639/*! @brief Return System PLL output clock rate
640 * @param recompute : Forces a PLL rate recomputation if true
641 * @return System PLL output clock rate
642 * @note The PLL rate is cached in the driver in a variable as
643 * the rate computation function can take some time to perform. It
644 * is recommended to use 'false' with the 'recompute' parameter.
645 */
646uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);
647
648/*! @brief Enables and disables PLL bypass mode
649 * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass
650 * @return System PLL output clock rate
651 */
652__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)
653{
654 if (bypass)
655 {
656 SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
657 }
658 else
659 {
660 SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
661 }
662}
663
664/*! @brief Check if PLL is locked or not
665 * @return true if the PLL is locked, false if not locked
666 */
667__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)
668{
669 return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0UL);
670}
671
672/*! @brief Store the current PLL rate
673 * @param rate: Current rate of the PLL
674 * @return Nothing
675 **/
676void CLOCK_SetStoredPLLClockRate(uint32_t rate);
677
678/*! @brief PLL configuration structure flags for 'flags' field
679 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
680 *
681 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
682 * configuration structure must be assigned with the expected PLL frequency. If the
683 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
684 * function and the driver will determine the PLL rate from the currently selected
685 * PLL source. This flag might be used to configure the PLL input clock more accurately
686 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
687 *
688 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
689 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
690 * are not used.<br>
691 */
692#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
693#define PLL_CONFIGFLAG_FORCENOFRACT \
694 (1U << 2U) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or \
695 SS hardware */
696
697/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency
698 * See (MF) field in the SYSPLLSSCTRL1 register in the UM.
699 */
700typedef enum _ss_progmodfm
701{
702 kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */
703 kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */
704 kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */
705 kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */
706 kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */
707 kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */
708 kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */
709 kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */
710} ss_progmodfm_t;
711
712/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth
713 * See (MR) field in the SYSPLLSSCTRL1 register in the UM.
714 */
715typedef enum _ss_progmoddp
716{
717 kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */
718 kSS_MR_K1 = (1 << 23), /*!< k = 1 */
719 kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */
720 kSS_MR_K2 = (3 << 23), /*!< k = 2 */
721 kSS_MR_K3 = (4 << 23), /*!< k = 3 */
722 kSS_MR_K4 = (5 << 23), /*!< k = 4 */
723 kSS_MR_K6 = (6 << 23), /*!< k = 6 */
724 kSS_MR_K8 = (7 << 23) /*!< k = 8 */
725} ss_progmoddp_t;
726
727/*! @brief PLL Spread Spectrum (SS) Modulation waveform control
728 * See (MC) field in the SYSPLLSSCTRL1 register in the UM.<br>
729 * Compensation for low pass filtering of the PLL to get a triangular
730 * modulation at the output of the PLL, giving a flat frequency spectrum.
731 */
732typedef enum _ss_modwvctrl
733{
734 kSS_MC_NOC = (0 << 26), /*!< no compensation */
735 kSS_MC_RECC = (2 << 26), /*!< recommended setting */
736 kSS_MC_MAXC = (3 << 26), /*!< max. compensation */
737} ss_modwvctrl_t;
738
739/*! @brief PLL configuration structure
740 *
741 * This structure can be used to configure the settings for a PLL
742 * setup structure. Fill in the desired configuration for the PLL
743 * and call the PLL setup function to fill in a PLL setup structure.
744 */
745typedef struct _pll_config
746{
747 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
748 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
749 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
750 ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using
751 PLL_CONFIGFLAG_FORCENOFRACT flag */
752 ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using
753 PLL_CONFIGFLAG_FORCENOFRACT flag */
754 ss_modwvctrl_t
755 ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
756 bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using
757 PLL_CONFIGFLAG_FORCENOFRACT flag */
758
759} pll_config_t;
760
761/*! @brief PLL setup structure flags for 'flags' field
762 * These flags control how the PLL setup function sets up the PLL
763 */
764#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */
765#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL to lock, implying the PLL will be pwoered on */
766#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */
767#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */
768
769/*! @brief PLL setup structure
770 * This structure can be used to pre-build a PLL setup configuration
771 * at run-time and quickly set the PLL to the configuration. It can be
772 * populated with the PLL setup function. If powering up or waiting
773 * for PLL lock, the PLL input clock source should be configured prior
774 * to PLL setup.
775 */
776typedef struct _pll_setup
777{
778 uint32_t syspllctrl; /*!< PLL control register SYSPLLCTRL */
779 uint32_t syspllndec; /*!< PLL NDEC register SYSPLLNDEC */
780 uint32_t syspllpdec; /*!< PLL PDEC register SYSPLLPDEC */
781 uint32_t syspllssctrl[2]; /*!< PLL SSCTL registers SYSPLLSSCTRL */
782 uint32_t pllRate; /*!< Acutal PLL rate */
783 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
784} pll_setup_t;
785
786/*! @brief PLL status definitions
787 */
788typedef enum _pll_error
789{
790 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
791 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
792 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
793 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
794 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
795 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5) /*!< Requested output rate isn't possible */
796} pll_error_t;
797
798/*! @brief USB clock source definition. */
799typedef enum _clock_usb_src
800{
801 kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */
802 kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */
803 kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
804 kCLOCK_UsbSrcNone = SYSCON_USBCLKSEL_SEL(
805 7) /*!< Use None, this may be selected in order to reduce power when no output is needed. */
806} clock_usb_src_t;
807
808/*! @brief Return System PLL output clock rate from setup structure
809 * @param pSetup : Pointer to a PLL setup structure
810 * @return System PLL output clock rate calculated from the setup structure
811 */
812uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);
813
814/*! @brief Set PLL output based on the passed PLL setup data
815 * @param pControl : Pointer to populated PLL control structure to generate setup with
816 * @param pSetup : Pointer to PLL setup structure to be filled
817 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
818 * @note Actual frequency for setup may vary from the desired frequency based on the
819 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
820 */
821pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
822
823/*! @brief Set PLL output from PLL setup structure (precise frequency)
824 * @param pSetup : Pointer to populated PLL setup structure
825 * @param flagcfg : Flag configuration for PLL config structure
826 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
827 * @note This function will power off the PLL, setup the PLL with the
828 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
829 * and adjust system voltages to the new PLL rate. The function will not
830 * alter any source clocks (ie, main systen clock) that may use the PLL,
831 * so these should be setup prior to and after exiting the function.
832 */
833pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
834
835/**
836 * @brief Set PLL output from PLL setup structure (precise frequency)
837 * @param pSetup : Pointer to populated PLL setup structure
838 * @return kStatus_PLL_Success on success, or PLL setup error code
839 * @note This function will power off the PLL, setup the PLL with the
840 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
841 * and adjust system voltages to the new PLL rate. The function will not
842 * alter any source clocks (ie, main systen clock) that may use the PLL,
843 * so these should be setup prior to and after exiting the function.
844 */
845pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);
846
847/*! @brief Set PLL output based on the multiplier and input frequency
848 * @param multiply_by : multiplier
849 * @param input_freq : Clock input frequency of the PLL
850 * @return Nothing
851 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
852 * function does not disable or enable PLL power, wait for PLL lock,
853 * or adjust system voltages. These must be done in the application.
854 * The function will not alter any source clocks (ie, main systen clock)
855 * that may use the PLL, so these should be setup prior to and after
856 * exiting the function.
857 */
858void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);
859
860/*! @brief Disable USB FS clock.
861 *
862 * Disable USB FS clock.
863 */
864static inline void CLOCK_DisableUsbfs0Clock(void)
865{
866 CLOCK_DisableClock(kCLOCK_Usbd0);
867}
868bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
869
870#if defined(__cplusplus)
871}
872#endif /* __cplusplus */
873
874/*! @} */
875
876#endif /* _FSL_CLOCK_H_ */
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