1 files changed, 374 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54605/LPC54605_features.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54605/LPC54605_features.h
new file mode 100644
index 000000000..34453b6cc
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54605/LPC54605_features.h
@@ -0,0 +1,374 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.2, 2017-06-08
+**     Build:               b191206
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2019 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**     - rev. 1.2 (2017-06-08)
+**         Remove RTC_CTRL_RTC_OSC_BYPASS.
+**         SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
+**         Remove RESET and HALT from SYSCON_AHBCLKDIV.
+**
+** ###################################################################
+*/
+#ifndef _LPC54605_FEATURES_H_
+#define _LPC54605_FEATURES_H_
+/* SOC module features */
+/* @brief ADC availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC_COUNT (1)
+/* @brief ASYNC_SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief CTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (1)
+/* @brief DMIC availability on the SoC. */
+#define FSL_FEATURE_SOC_DMIC_COUNT (1)
+/* @brief EEPROM availability on the SoC. */
+#define FSL_FEATURE_SOC_EEPROM_COUNT (1)
+/* @brief EMC availability on the SoC. */
+#define FSL_FEATURE_SOC_EMC_COUNT (1)
+/* @brief FLEXCOMM availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (10)
+/* @brief FMC availability on the SoC. */
+#define FSL_FEATURE_SOC_FMC_COUNT (1)
+/* @brief GINT availability on the SoC. */
+#define FSL_FEATURE_SOC_GINT_COUNT (2)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (1)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (10)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (2)
+/* @brief INPUTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief IOCON availability on the SoC. */
+#define FSL_FEATURE_SOC_IOCON_COUNT (1)
+/* @brief MRT availability on the SoC. */
+#define FSL_FEATURE_SOC_MRT_COUNT (1)
+/* @brief PINT availability on the SoC. */
+#define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief RIT availability on the SoC. */
+#define FSL_FEATURE_SOC_RIT_COUNT (1)
+/* @brief LPC_RNG availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_RNG_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCT availability on the SoC. */
+#define FSL_FEATURE_SOC_SCT_COUNT (1)
+/* @brief SDIF availability on the SoC. */
+#define FSL_FEATURE_SOC_SDIF_COUNT (1)
+/* @brief SMARTCARD availability on the SoC. */
+#define FSL_FEATURE_SOC_SMARTCARD_COUNT (2)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (10)
+/* @brief SPIFI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
+/* @brief SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_USART_COUNT (10)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (1)
+/* @brief USBFSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
+/* @brief USBHSD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
+/* @brief USBHSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
+/* @brief UTICK availability on the SoC. */
+#define FSL_FEATURE_SOC_UTICK_COUNT (1)
+/* @brief WWDT availability on the SoC. */
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)
+/* ADC module features */
+/* @brief Do not has input select (register INSEL). */
+#define FSL_FEATURE_ADC_HAS_NO_INSEL  (0)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0)
+/* @brief Has startup register. */
+#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1)
+/* @brief Has ADTrim register */
+#define FSL_FEATURE_ADC_HAS_TRIM_REG (0)
+/* @brief Has Calibration register. */
+#define FSL_FEATURE_ADC_HAS_CALIB_REG (1)
+/* DMA module features */
+/* @brief Number of channels */
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
+/* @brief Align size of DMA descriptor */
+#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
+/* @brief DMA head link descriptor table align size */
+#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
+/* EEPROM module features */
+/* @brief Size of the EEPROM */
+#define FSL_FEATURE_EEPROM_SIZE (0x00004000)
+/* @brief Base address of the EEPROM */
+#define FSL_FEATURE_EEPROM_BASE_ADDRESS (0x40108000)
+/* @brief Page count of the EEPROM */
+#define FSL_FEATURE_EEPROM_PAGE_COUNT (128)
+/* @brief Command number for eeprom program */
+#define FSL_FEATURE_EEPROM_PROGRAM_CMD (6)
+/* @brief EEPROM internal clock freqency */
+#define FSL_FEATURE_EEPROM_INTERNAL_FREQ (1500000)
+/* FLEXCOMM module features */
+/* @brief FLEXCOMM0 USART INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_USART_INDEX  (0)
+/* @brief FLEXCOMM0 SPI INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX  (0)
+/* @brief FLEXCOMM0 I2C INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX  (0)
+/* @brief FLEXCOMM1 USART INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_USART_INDEX  (1)
+/* @brief FLEXCOMM1 SPI INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX  (1)
+/* @brief FLEXCOMM1 I2C INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX  (1)
+/* @brief FLEXCOMM2 USART INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_USART_INDEX  (2)
+/* @brief FLEXCOMM2 SPI INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX  (2)
+/* @brief FLEXCOMM2 I2C INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX  (2)
+/* @brief FLEXCOMM3 USART INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_USART_INDEX  (3)
+/* @brief FLEXCOMM3 SPI INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX  (3)
+/* @brief FLEXCOMM3 I2C INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX  (3)
+/* @brief FLEXCOMM4 USART INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_USART_INDEX  (4)
+/* @brief FLEXCOMM4 SPI INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX  (4)
+/* @brief FLEXCOMM4 I2C INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX  (4)
+/* @brief FLEXCOMM5 USART INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_USART_INDEX  (5)
+/* @brief FLEXCOMM5 SPI INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX  (5)
+/* @brief FLEXCOMM5 I2C INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX  (5)
+/* @brief FLEXCOMM6 USART INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_USART_INDEX  (6)
+/* @brief FLEXCOMM6 SPI INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX  (6)
+/* @brief FLEXCOMM6 I2C INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX  (6)
+/* @brief FLEXCOMM7 I2S INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX  (0)
+/* @brief FLEXCOMM7 USART INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_USART_INDEX  (7)
+/* @brief FLEXCOMM7 SPI INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX  (7)
+/* @brief FLEXCOMM7 I2C INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX  (7)
+/* @brief FLEXCOMM7 I2S INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX  (1)
+/* @brief FLEXCOMM4 USART INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_USART_INDEX  (8)
+/* @brief FLEXCOMM4 SPI INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX  (8)
+/* @brief FLEXCOMM4 I2C INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_I2C_INDEX  (8)
+/* @brief FLEXCOMM5 USART INDEX 9 */
+#define FSL_FEATURE_FLEXCOMM9_USART_INDEX  (9)
+/* @brief FLEXCOMM5 SPI INDEX 9 */
+#define FSL_FEATURE_FLEXCOMM9_SPI_INDEX  (9)
+/* @brief FLEXCOMM5 I2C INDEX 9 */
+#define FSL_FEATURE_FLEXCOMM9_I2C_INDEX  (9)
+/* @brief I2S has DMIC interconnection */
+#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \
+    (((x) == FLEXCOMM0) ? (0) : \
+    (((x) == FLEXCOMM1) ? (0) : \
+    (((x) == FLEXCOMM2) ? (0) : \
+    (((x) == FLEXCOMM3) ? (0) : \
+    (((x) == FLEXCOMM4) ? (0) : \
+    (((x) == FLEXCOMM5) ? (0) : \
+    (((x) == FLEXCOMM6) ? (0) : \
+    (((x) == FLEXCOMM7) ? (1) : \
+    (((x) == FLEXCOMM8) ? (0) : \
+    (((x) == FLEXCOMM9) ? (0) : (-1)))))))))))
+/* I2S module features */
+/* @brief I2S support dual channel transfer */
+#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
+/* @brief I2S has DMIC interconnection */
+#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION  (1)
+/* IOCON module features */
+/* @brief Func bit field width */
+#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
+/* MRT module features */
+/* @brief number of channels. */
+#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS  (4)
+/* interrupt module features */
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105)
+/* PINT module features */
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
+/* RIT module features */
+/* @brief RIT has no reset control */
+#define FSL_FEATURE_RIT_HAS_NO_RESET (1)
+/* RTC module features */
+/* @brief RTC has no reset control */
+#define FSL_FEATURE_RTC_HAS_NO_RESET (1)
+/* SCT module features */
+/* @brief Number of events */
+#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (10)
+/* @brief Number of states */
+#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10)
+/* @brief Number of match capture */
+#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10)
+/* @brief Number of outputs */
+#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
+/* SDIF module features */
+/* @brief FIFO depth, every location is a WORD */
+#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS  (64)
+/* @brief Max DMA buffer size */
+#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE  (4096)
+/* @brief Max source clock in HZ */
+#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK  (52000000)
+/* SPIFI module features */
+/* @brief SPIFI start address */
+#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000)
+/* @brief SPIFI end address */
+#define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF)
+/* SYSCON module features */
+#if defined(CPU_LPC54605J256BD100) || defined(CPU_LPC54605J256ET100) || defined(CPU_LPC54605J256ET180)
+    /* @brief Pointer to ROM IAP entry functions */
+    #define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
+    /* @brief Flash page size in bytes */
+    #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256)
+    /* @brief Flash sector size in bytes */
+    #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
+    /* @brief Flash size in bytes */
+    #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (262144)
+    /* @brief IAP has Flash read & write function */
+    #define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1)
+    /* @brief IAP has EEPROM read & write function */
+    #define FSL_FEATURE_IAP_HAS_EEPROM_FUNCTION (1)
+    /* @brief IAP has read Flash signature function  */
+    #define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (0)
+    /* @brief IAP has read extended Flash signature function */
+    #define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (1)
+#elif defined(CPU_LPC54605J512BD100) || defined(CPU_LPC54605J512ET100) || defined(CPU_LPC54605J512ET180)
+    /* @brief Pointer to ROM IAP entry functions */
+    #define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
+    /* @brief Flash page size in bytes */
+    #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256)
+    /* @brief Flash sector size in bytes */
+    #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
+    /* @brief Flash size in bytes */
+    #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288)
+    /* @brief IAP has Flash read & write function */
+    #define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1)
+    /* @brief IAP has EEPROM read & write function */
+    #define FSL_FEATURE_IAP_HAS_EEPROM_FUNCTION (1)
+    /* @brief IAP has read Flash signature function  */
+    #define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (0)
+    /* @brief IAP has read extended Flash signature function */
+    #define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (1)
+#endif /* defined(CPU_LPC54605J256BD100) || defined(CPU_LPC54605J256ET100) || defined(CPU_LPC54605J256ET180) */
+/* SysTick module features */
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
+/* USB module features */
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief Number of the endpoint in USB FS */
+#define FSL_FEATURE_USB_EP_NUM (5)
+/* USBFSH module features */
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBFSH_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
+/* USBHSD module features */
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief Number of the endpoint in USB HS */
+#define FSL_FEATURE_USBHSD_EP_NUM (6)
+/* USBHSH module features */
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
+#endif /* _LPC54605_FEATURES_H_ */

diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54605/LPC54605_features.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54605/LPC54605_features.h new file mode 100644 index 000000000..34453b6cc --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54605/LPC54605_features.h
@@ -0,0 +1,374 @@
	1	/*
	2	** ###################################################################
	3	** Version: rev. 1.2, 2017-06-08
	4	** Build: b191206
	5	**
	6	** Abstract:
	7	** Chip specific module features.
	8	**
	9	** Copyright 2016 Freescale Semiconductor, Inc.
	10	** Copyright 2016-2019 NXP
	11	** All rights reserved.
	12	**
	13	** SPDX-License-Identifier: BSD-3-Clause
	14	**
	15	** http: www.nxp.com
	16	** mail: [email protected]
	17	**
	18	** Revisions:
	19	** - rev. 1.0 (2016-08-12)
	20	** Initial version.
	21	** - rev. 1.1 (2016-11-25)
	22	** Update CANFD and Classic CAN register.
	23	** Add MAC TIMERSTAMP registers.
	24	** - rev. 1.2 (2017-06-08)
	25	** Remove RTC_CTRL_RTC_OSC_BYPASS.
	26	** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
	27	** Remove RESET and HALT from SYSCON_AHBCLKDIV.
	28	**
	29	** ###################################################################
	30	*/
	31
	32	#ifndef _LPC54605_FEATURES_H_
	33	#define _LPC54605_FEATURES_H_
	34
	35	/* SOC module features */
	36
	37	/* @brief ADC availability on the SoC. */
	38	#define FSL_FEATURE_SOC_ADC_COUNT (1)
	39	/* @brief ASYNC_SYSCON availability on the SoC. */
	40	#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
	41	/* @brief CRC availability on the SoC. */
	42	#define FSL_FEATURE_SOC_CRC_COUNT (1)
	43	/* @brief CTIMER availability on the SoC. */
	44	#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
	45	/* @brief DMA availability on the SoC. */
	46	#define FSL_FEATURE_SOC_DMA_COUNT (1)
	47	/* @brief DMIC availability on the SoC. */
	48	#define FSL_FEATURE_SOC_DMIC_COUNT (1)
	49	/* @brief EEPROM availability on the SoC. */
	50	#define FSL_FEATURE_SOC_EEPROM_COUNT (1)
	51	/* @brief EMC availability on the SoC. */
	52	#define FSL_FEATURE_SOC_EMC_COUNT (1)
	53	/* @brief FLEXCOMM availability on the SoC. */
	54	#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (10)
	55	/* @brief FMC availability on the SoC. */
	56	#define FSL_FEATURE_SOC_FMC_COUNT (1)
	57	/* @brief GINT availability on the SoC. */
	58	#define FSL_FEATURE_SOC_GINT_COUNT (2)
	59	/* @brief GPIO availability on the SoC. */
	60	#define FSL_FEATURE_SOC_GPIO_COUNT (1)
	61	/* @brief I2C availability on the SoC. */
	62	#define FSL_FEATURE_SOC_I2C_COUNT (10)
	63	/* @brief I2S availability on the SoC. */
	64	#define FSL_FEATURE_SOC_I2S_COUNT (2)
	65	/* @brief INPUTMUX availability on the SoC. */
	66	#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
	67	/* @brief IOCON availability on the SoC. */
	68	#define FSL_FEATURE_SOC_IOCON_COUNT (1)
	69	/* @brief MRT availability on the SoC. */
	70	#define FSL_FEATURE_SOC_MRT_COUNT (1)
	71	/* @brief PINT availability on the SoC. */
	72	#define FSL_FEATURE_SOC_PINT_COUNT (1)
	73	/* @brief RIT availability on the SoC. */
	74	#define FSL_FEATURE_SOC_RIT_COUNT (1)
	75	/* @brief LPC_RNG availability on the SoC. */
	76	#define FSL_FEATURE_SOC_LPC_RNG_COUNT (1)
	77	/* @brief RTC availability on the SoC. */
	78	#define FSL_FEATURE_SOC_RTC_COUNT (1)
	79	/* @brief SCT availability on the SoC. */
	80	#define FSL_FEATURE_SOC_SCT_COUNT (1)
	81	/* @brief SDIF availability on the SoC. */
	82	#define FSL_FEATURE_SOC_SDIF_COUNT (1)
	83	/* @brief SMARTCARD availability on the SoC. */
	84	#define FSL_FEATURE_SOC_SMARTCARD_COUNT (2)
	85	/* @brief SPI availability on the SoC. */
	86	#define FSL_FEATURE_SOC_SPI_COUNT (10)
	87	/* @brief SPIFI availability on the SoC. */
	88	#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
	89	/* @brief SYSCON availability on the SoC. */
	90	#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
	91	/* @brief USART availability on the SoC. */
	92	#define FSL_FEATURE_SOC_USART_COUNT (10)
	93	/* @brief USB availability on the SoC. */
	94	#define FSL_FEATURE_SOC_USB_COUNT (1)
	95	/* @brief USBFSH availability on the SoC. */
	96	#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
	97	/* @brief USBHSD availability on the SoC. */
	98	#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
	99	/* @brief USBHSH availability on the SoC. */
	100	#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
	101	/* @brief UTICK availability on the SoC. */
	102	#define FSL_FEATURE_SOC_UTICK_COUNT (1)
	103	/* @brief WWDT availability on the SoC. */
	104	#define FSL_FEATURE_SOC_WWDT_COUNT (1)
	105
	106	/* ADC module features */
	107
	108	/* @brief Do not has input select (register INSEL). */
	109	#define FSL_FEATURE_ADC_HAS_NO_INSEL (0)
	110	/* @brief Has ASYNMODE bitfile in CTRL reigster. */
	111	#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
	112	/* @brief Has ASYNMODE bitfile in CTRL reigster. */
	113	#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1)
	114	/* @brief Has ASYNMODE bitfile in CTRL reigster. */
	115	#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1)
	116	/* @brief Has ASYNMODE bitfile in CTRL reigster. */
	117	#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1)
	118	/* @brief Has ASYNMODE bitfile in CTRL reigster. */
	119	#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0)
	120	/* @brief Has ASYNMODE bitfile in CTRL reigster. */
	121	#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0)
	122	/* @brief Has startup register. */
	123	#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1)
	124	/* @brief Has ADTrim register */
	125	#define FSL_FEATURE_ADC_HAS_TRIM_REG (0)
	126	/* @brief Has Calibration register. */
	127	#define FSL_FEATURE_ADC_HAS_CALIB_REG (1)
	128
	129	/* DMA module features */
	130
	131	/* @brief Number of channels */
	132	#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
	133	/* @brief Align size of DMA descriptor */
	134	#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
	135	/* @brief DMA head link descriptor table align size */
	136	#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
	137
	138	/* EEPROM module features */
	139
	140	/* @brief Size of the EEPROM */
	141	#define FSL_FEATURE_EEPROM_SIZE (0x00004000)
	142	/* @brief Base address of the EEPROM */
	143	#define FSL_FEATURE_EEPROM_BASE_ADDRESS (0x40108000)
	144	/* @brief Page count of the EEPROM */
	145	#define FSL_FEATURE_EEPROM_PAGE_COUNT (128)
	146	/* @brief Command number for eeprom program */
	147	#define FSL_FEATURE_EEPROM_PROGRAM_CMD (6)
	148	/* @brief EEPROM internal clock freqency */
	149	#define FSL_FEATURE_EEPROM_INTERNAL_FREQ (1500000)
	150
	151	/* FLEXCOMM module features */
	152
	153	/* @brief FLEXCOMM0 USART INDEX 0 */
	154	#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0)
	155	/* @brief FLEXCOMM0 SPI INDEX 0 */
	156	#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0)
	157	/* @brief FLEXCOMM0 I2C INDEX 0 */
	158	#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0)
	159	/* @brief FLEXCOMM1 USART INDEX 1 */
	160	#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1)
	161	/* @brief FLEXCOMM1 SPI INDEX 1 */
	162	#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1)
	163	/* @brief FLEXCOMM1 I2C INDEX 1 */
	164	#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1)
	165	/* @brief FLEXCOMM2 USART INDEX 2 */
	166	#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2)
	167	/* @brief FLEXCOMM2 SPI INDEX 2 */
	168	#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2)
	169	/* @brief FLEXCOMM2 I2C INDEX 2 */
	170	#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2)
	171	/* @brief FLEXCOMM3 USART INDEX 3 */
	172	#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3)
	173	/* @brief FLEXCOMM3 SPI INDEX 3 */
	174	#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3)
	175	/* @brief FLEXCOMM3 I2C INDEX 3 */
	176	#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3)
	177	/* @brief FLEXCOMM4 USART INDEX 4 */
	178	#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4)
	179	/* @brief FLEXCOMM4 SPI INDEX 4 */
	180	#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4)
	181	/* @brief FLEXCOMM4 I2C INDEX 4 */
	182	#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4)
	183	/* @brief FLEXCOMM5 USART INDEX 5 */
	184	#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5)
	185	/* @brief FLEXCOMM5 SPI INDEX 5 */
	186	#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5)
	187	/* @brief FLEXCOMM5 I2C INDEX 5 */
	188	#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5)
	189	/* @brief FLEXCOMM6 USART INDEX 6 */
	190	#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6)
	191	/* @brief FLEXCOMM6 SPI INDEX 6 */
	192	#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6)
	193	/* @brief FLEXCOMM6 I2C INDEX 6 */
	194	#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6)
	195	/* @brief FLEXCOMM7 I2S INDEX 0 */
	196	#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0)
	197	/* @brief FLEXCOMM7 USART INDEX 7 */
	198	#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7)
	199	/* @brief FLEXCOMM7 SPI INDEX 7 */
	200	#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7)
	201	/* @brief FLEXCOMM7 I2C INDEX 7 */
	202	#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7)
	203	/* @brief FLEXCOMM7 I2S INDEX 1 */
	204	#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1)
	205	/* @brief FLEXCOMM4 USART INDEX 8 */
	206	#define FSL_FEATURE_FLEXCOMM8_USART_INDEX (8)
	207	/* @brief FLEXCOMM4 SPI INDEX 8 */
	208	#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8)
	209	/* @brief FLEXCOMM4 I2C INDEX 8 */
	210	#define FSL_FEATURE_FLEXCOMM8_I2C_INDEX (8)
	211	/* @brief FLEXCOMM5 USART INDEX 9 */
	212	#define FSL_FEATURE_FLEXCOMM9_USART_INDEX (9)
	213	/* @brief FLEXCOMM5 SPI INDEX 9 */
	214	#define FSL_FEATURE_FLEXCOMM9_SPI_INDEX (9)
	215	/* @brief FLEXCOMM5 I2C INDEX 9 */
	216	#define FSL_FEATURE_FLEXCOMM9_I2C_INDEX (9)
	217	/* @brief I2S has DMIC interconnection */
	218	#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \
	219	(((x) == FLEXCOMM0) ? (0) : \
	220	(((x) == FLEXCOMM1) ? (0) : \
	221	(((x) == FLEXCOMM2) ? (0) : \
	222	(((x) == FLEXCOMM3) ? (0) : \
	223	(((x) == FLEXCOMM4) ? (0) : \
	224	(((x) == FLEXCOMM5) ? (0) : \
	225	(((x) == FLEXCOMM6) ? (0) : \
	226	(((x) == FLEXCOMM7) ? (1) : \
	227	(((x) == FLEXCOMM8) ? (0) : \
	228	(((x) == FLEXCOMM9) ? (0) : (-1)))))))))))
	229
	230	/* I2S module features */
	231
	232	/* @brief I2S support dual channel transfer */
	233	#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
	234	/* @brief I2S has DMIC interconnection */
	235	#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1)
	236
	237	/* IOCON module features */
	238
	239	/* @brief Func bit field width */
	240	#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
	241
	242	/* MRT module features */
	243
	244	/* @brief number of channels. */
	245	#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
	246
	247	/* interrupt module features */
	248
	249	/* @brief Lowest interrupt request number. */
	250	#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
	251	/* @brief Highest interrupt request number. */
	252	#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105)
	253
	254	/* PINT module features */
	255
	256	/* @brief Number of connected outputs */
	257	#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
	258
	259	/* RIT module features */
	260
	261	/* @brief RIT has no reset control */
	262	#define FSL_FEATURE_RIT_HAS_NO_RESET (1)
	263
	264	/* RTC module features */
	265
	266	/* @brief RTC has no reset control */
	267	#define FSL_FEATURE_RTC_HAS_NO_RESET (1)
	268
	269	/* SCT module features */
	270
	271	/* @brief Number of events */
	272	#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (10)
	273	/* @brief Number of states */
	274	#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10)
	275	/* @brief Number of match capture */
	276	#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10)
	277	/* @brief Number of outputs */
	278	#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
	279
	280	/* SDIF module features */
	281
	282	/* @brief FIFO depth, every location is a WORD */
	283	#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)
	284	/* @brief Max DMA buffer size */
	285	#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)
	286	/* @brief Max source clock in HZ */
	287	#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)
	288
	289	/* SPIFI module features */
	290
	291	/* @brief SPIFI start address */
	292	#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000)
	293	/* @brief SPIFI end address */
	294	#define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF)
	295
	296	/* SYSCON module features */
	297
	298	#if defined(CPU_LPC54605J256BD100) \|\| defined(CPU_LPC54605J256ET100) \|\| defined(CPU_LPC54605J256ET180)
	299	/* @brief Pointer to ROM IAP entry functions */
	300	#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
	301	/* @brief Flash page size in bytes */
	302	#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256)
	303	/* @brief Flash sector size in bytes */
	304	#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
	305	/* @brief Flash size in bytes */
	306	#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (262144)
	307	/* @brief IAP has Flash read & write function */
	308	#define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1)
	309	/* @brief IAP has EEPROM read & write function */
	310	#define FSL_FEATURE_IAP_HAS_EEPROM_FUNCTION (1)
	311	/* @brief IAP has read Flash signature function */
	312	#define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (0)
	313	/* @brief IAP has read extended Flash signature function */
	314	#define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (1)
	315	#elif defined(CPU_LPC54605J512BD100) \|\| defined(CPU_LPC54605J512ET100) \|\| defined(CPU_LPC54605J512ET180)
	316	/* @brief Pointer to ROM IAP entry functions */
	317	#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
	318	/* @brief Flash page size in bytes */
	319	#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256)
	320	/* @brief Flash sector size in bytes */
	321	#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
	322	/* @brief Flash size in bytes */
	323	#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288)
	324	/* @brief IAP has Flash read & write function */
	325	#define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1)
	326	/* @brief IAP has EEPROM read & write function */
	327	#define FSL_FEATURE_IAP_HAS_EEPROM_FUNCTION (1)
	328	/* @brief IAP has read Flash signature function */
	329	#define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (0)
	330	/* @brief IAP has read extended Flash signature function */
	331	#define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (1)
	332	#endif /* defined(CPU_LPC54605J256BD100) \|\| defined(CPU_LPC54605J256ET100) \|\| defined(CPU_LPC54605J256ET180) */
	333
	334	/* SysTick module features */
	335
	336	/* @brief Systick has external reference clock. */
	337	#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
	338	/* @brief Systick external reference clock is core clock divided by this value. */
	339	#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
	340
	341	/* USB module features */
	342
	343	/* @brief Size of the USB dedicated RAM */
	344	#define FSL_FEATURE_USB_USB_RAM (0x00002000)
	345	/* @brief Base address of the USB dedicated RAM */
	346	#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
	347	/* @brief Number of the endpoint in USB FS */
	348	#define FSL_FEATURE_USB_EP_NUM (5)
	349
	350	/* USBFSH module features */
	351
	352	/* @brief Size of the USB dedicated RAM */
	353	#define FSL_FEATURE_USBFSH_USB_RAM (0x00002000)
	354	/* @brief Base address of the USB dedicated RAM */
	355	#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
	356
	357	/* USBHSD module features */
	358
	359	/* @brief Size of the USB dedicated RAM */
	360	#define FSL_FEATURE_USBHSD_USB_RAM (0x00002000)
	361	/* @brief Base address of the USB dedicated RAM */
	362	#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
	363	/* @brief Number of the endpoint in USB HS */
	364	#define FSL_FEATURE_USBHSD_EP_NUM (6)
	365
	366	/* USBHSH module features */
	367
	368	/* @brief Size of the USB dedicated RAM */
	369	#define FSL_FEATURE_USBHSH_USB_RAM (0x00002000)
	370	/* @brief Base address of the USB dedicated RAM */
	371	#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
	372
	373	#endif /* _LPC54605_FEATURES_H_ */
	374