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1/*
2** ###################################################################
3** Processors: LPC54606J256BD100
4** LPC54606J256ET100
5** LPC54606J256ET180
6** LPC54606J512BD100
7** LPC54606J512BD208
8** LPC54606J512ET100
9**
10** Compilers: GNU C Compiler
11** IAR ANSI C/C++ Compiler for ARM
12** Keil ARM C/C++ Compiler
13** MCUXpresso Compiler
14**
15** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017
16** Version: rev. 1.2, 2017-06-08
17** Build: b200304
18**
19** Abstract:
20** CMSIS Peripheral Access Layer for LPC54606
21**
22** Copyright 1997-2016 Freescale Semiconductor, Inc.
23** Copyright 2016-2020 NXP
24** All rights reserved.
25**
26** SPDX-License-Identifier: BSD-3-Clause
27**
28** http: www.nxp.com
29** mail: [email protected]
30**
31** Revisions:
32** - rev. 1.0 (2016-08-12)
33** Initial version.
34** - rev. 1.1 (2016-11-25)
35** Update CANFD and Classic CAN register.
36** Add MAC TIMERSTAMP registers.
37** - rev. 1.2 (2017-06-08)
38** Remove RTC_CTRL_RTC_OSC_BYPASS.
39** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
40** Remove RESET and HALT from SYSCON_AHBCLKDIV.
41**
42** ###################################################################
43*/
44
45/*!
46 * @file LPC54606.h
47 * @version 1.2
48 * @date 2017-06-08
49 * @brief CMSIS Peripheral Access Layer for LPC54606
50 *
51 * CMSIS Peripheral Access Layer for LPC54606
52 */
53
54#ifndef _LPC54606_H_
55#define _LPC54606_H_ /**< Symbol preventing repeated inclusion */
56
57/** Memory map major version (memory maps with equal major version number are
58 * compatible) */
59#define MCU_MEM_MAP_VERSION 0x0100U
60/** Memory map minor version */
61#define MCU_MEM_MAP_VERSION_MINOR 0x0002U
62
63
64/* ----------------------------------------------------------------------------
65 -- Interrupt vector numbers
66 ---------------------------------------------------------------------------- */
67
68/*!
69 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
70 * @{
71 */
72
73/** Interrupt Number Definitions */
74#define NUMBER_OF_INT_VECTORS 73 /**< Number of interrupts in the Vector table */
75
76typedef enum IRQn {
77 /* Auxiliary constants */
78 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
79
80 /* Core interrupts */
81 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
82 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
83 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
84 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
85 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
86 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
87 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
88 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
89 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
90
91 /* Device specific interrupts */
92 WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */
93 DMA0_IRQn = 1, /**< DMA controller */
94 GINT0_IRQn = 2, /**< GPIO group 0 */
95 GINT1_IRQn = 3, /**< GPIO group 1 */
96 PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */
97 PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */
98 PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */
99 PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */
100 UTICK0_IRQn = 8, /**< Micro-tick Timer */
101 MRT0_IRQn = 9, /**< Multi-rate timer */
102 CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
103 CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
104 SCT0_IRQn = 12, /**< SCTimer/PWM */
105 CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
106 FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
107 FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
108 FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
109 FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
110 FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
111 FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
112 FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
113 FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
114 ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */
115 ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */
116 ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */
117 DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */
118 HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */
119 USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */
120 USB0_IRQn = 28, /**< USB device */
121 RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */
122 Reserved46_IRQn = 30, /**< Reserved interrupt */
123 Reserved47_IRQn = 31, /**< Reserved interrupt */
124 PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */
125 PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */
126 PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */
127 PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */
128 CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */
129 CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */
130 RIT_IRQn = 38, /**< Repetitive Interrupt Timer */
131 SPIFI0_IRQn = 39, /**< SPI flash interface */
132 FLEXCOMM8_IRQn = 40, /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
133 FLEXCOMM9_IRQn = 41, /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
134 SDIO_IRQn = 42, /**< SD/MMC */
135 CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */
136 CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */
137 CAN1_IRQ0_IRQn = 45, /**< CAN1 interrupt0 */
138 CAN1_IRQ1_IRQn = 46, /**< CAN1 interrupt1 */
139 USB1_IRQn = 47, /**< USB1 interrupt */
140 USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */
141 ETHERNET_IRQn = 49, /**< Ethernet */
142 ETHERNET_PMT_IRQn = 50, /**< Ethernet power management interrupt */
143 ETHERNET_MACLP_IRQn = 51, /**< Ethernet MAC interrupt */
144 EEPROM_IRQn = 52, /**< EEPROM interrupt */
145 LCD_IRQn = 53, /**< LCD interrupt */
146 SHA_IRQn = 54, /**< SHA interrupt */
147 SMARTCARD0_IRQn = 55, /**< Smart card 0 interrupt */
148 SMARTCARD1_IRQn = 56 /**< Smart card 1 interrupt */
149} IRQn_Type;
150
151/*!
152 * @}
153 */ /* end of group Interrupt_vector_numbers */
154
155
156/* ----------------------------------------------------------------------------
157 -- Cortex M4 Core Configuration
158 ---------------------------------------------------------------------------- */
159
160/*!
161 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
162 * @{
163 */
164
165#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
166#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
167#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
168#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
169
170#include "core_cm4.h" /* Core Peripheral Access Layer */
171#include "system_LPC54606.h" /* Device specific configuration file */
172
173/*!
174 * @}
175 */ /* end of group Cortex_Core_Configuration */
176
177
178/* ----------------------------------------------------------------------------
179 -- Mapping Information
180 ---------------------------------------------------------------------------- */
181
182/*!
183 * @addtogroup Mapping_Information Mapping Information
184 * @{
185 */
186
187/** Mapping Information */
188/*!
189 * @addtogroup dma_request
190 * @{
191 */
192
193/*******************************************************************************
194 * Definitions
195 ******************************************************************************/
196
197/*!
198 * @brief Structure for the DMA hardware request
199 *
200 * Defines the structure for the DMA hardware request collections. The user can configure the
201 * hardware request to trigger the DMA transfer accordingly. The index
202 * of the hardware request varies according to the to SoC.
203 */
204typedef enum _dma_request_source
205{
206 kDmaRequestFlexcomm0Rx = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */
207 kDmaRequestFlexcomm0Tx = 1U, /**< Flexcomm Interface 0 TX/I2C Master */
208 kDmaRequestFlexcomm1Rx = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */
209 kDmaRequestFlexcomm1Tx = 3U, /**< Flexcomm Interface 1 TX/I2C Master */
210 kDmaRequestFlexcomm2Rx = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */
211 kDmaRequestFlexcomm2Tx = 5U, /**< Flexcomm Interface 2 TX/I2C Master */
212 kDmaRequestFlexcomm3Rx = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */
213 kDmaRequestFlexcomm3Tx = 7U, /**< Flexcomm Interface 3 TX/I2C Master */
214 kDmaRequestFlexcomm4Rx = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */
215 kDmaRequestFlexcomm4Tx = 9U, /**< Flexcomm Interface 4 TX/I2C Master */
216 kDmaRequestFlexcomm5Rx = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */
217 kDmaRequestFlexcomm5Tx = 11U, /**< Flexcomm Interface 5 TX/I2C Master */
218 kDmaRequestFlexcomm6Rx = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */
219 kDmaRequestFlexcomm6Tx = 13U, /**< Flexcomm Interface 6 TX/I2C Master */
220 kDmaRequestFlexcomm7Rx = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */
221 kDmaRequestFlexcomm7Tx = 15U, /**< Flexcomm Interface 7 TX/I2C Master */
222 kDmaRequestDMIC0 = 16U, /**< Digital microphone interface 0 channel 0 */
223 kDmaRequestDMIC1 = 17U, /**< Digital microphone interface 0 channel 1 */
224 kDmaRequestSPIFI = 18U, /**< SPI Flash Interface */
225 kDmaRequestSHA = 19U, /**< Reserved */
226 kDmaRequestFlexcomm8Rx = 20U, /**< Flexcomm Interface 8 RX/I2C Slave */
227 kDmaRequestFlexcomm8Tx = 21U, /**< Flexcomm Interface 8 TX/I2C Slave */
228 kDmaRequestFlexcomm9Rx = 22U, /**< Flexcomm Interface 9 RX/I2C Slave */
229 kDmaRequestFlexcomm9Tx = 23U, /**< Flexcomm Interface 9 TX/I2C Slave */
230 kDmaRequestSMARTCARD0_RX = 24U, /**< SMARTCARD0 RX */
231 kDmaRequestSMARTCARD0_TX = 25U, /**< SMARTCARD0 TX */
232 kDmaRequestSMARTCARD1_RX = 26U, /**< SMARTCARD1 RX */
233 kDmaRequestSMARTCARD1_TX = 27U, /**< SMARTCARD1 TX */
234 kDmaRequestNoDMARequest28 = 28U, /**< No DMA request 28 */
235 kDmaRequestNoDMARequest29 = 29U, /**< No DMA request 29 */
236} dma_request_source_t;
237
238/* @} */
239
240
241/*!
242 * @}
243 */ /* end of group Mapping_Information */
244
245
246/* ----------------------------------------------------------------------------
247 -- Device Peripheral Access Layer
248 ---------------------------------------------------------------------------- */
249
250/*!
251 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
252 * @{
253 */
254
255
256/*
257** Start of section using anonymous unions
258*/
259
260#if defined(__ARMCC_VERSION)
261 #if (__ARMCC_VERSION >= 6010050)
262 #pragma clang diagnostic push
263 #else
264 #pragma push
265 #pragma anon_unions
266 #endif
267#elif defined(__GNUC__)
268 /* anonymous unions are enabled by default */
269#elif defined(__IAR_SYSTEMS_ICC__)
270 #pragma language=extended
271#else
272 #error Not supported compiler type
273#endif
274
275/* ----------------------------------------------------------------------------
276 -- ADC Peripheral Access Layer
277 ---------------------------------------------------------------------------- */
278
279/*!
280 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
281 * @{
282 */
283
284/** ADC - Register Layout Typedef */
285typedef struct {
286 __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
287 __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
288 __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
289 __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
290 uint8_t RESERVED_0[8];
291 __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
292 __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
293 __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
294 __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
295 __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
296 __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
297 __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
298 __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
299 __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */
300 __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */
301} ADC_Type;
302
303/* ----------------------------------------------------------------------------
304 -- ADC Register Masks
305 ---------------------------------------------------------------------------- */
306
307/*!
308 * @addtogroup ADC_Register_Masks ADC Register Masks
309 * @{
310 */
311
312/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
313/*! @{ */
314#define ADC_CTRL_CLKDIV_MASK (0xFFU)
315#define ADC_CTRL_CLKDIV_SHIFT (0U)
316/*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce
317 * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically,
318 * software should program the smallest value in this field that yields this maximum clock rate or
319 * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may
320 * be desirable. This field is ignored in the asynchronous operating mode.
321 */
322#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
323#define ADC_CTRL_ASYNMODE_MASK (0x100U)
324#define ADC_CTRL_ASYNMODE_SHIFT (8U)
325/*! ASYNMODE - Select clock mode.
326 * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in
327 * the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to
328 * eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger.
329 * In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC
330 * input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger
331 * pulse.
332 * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
333 */
334#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
335#define ADC_CTRL_RESOL_MASK (0x600U)
336#define ADC_CTRL_RESOL_SHIFT (9U)
337/*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher
338 * conversion rates. A single conversion (including one conversion in a burst or sequence) requires the
339 * selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when
340 * the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable
341 * results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate
342 * for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system
343 * clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution
344 * 0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field.
345 * 0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field.
346 * 0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field.
347 * 0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field.
348 */
349#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
350#define ADC_CTRL_BYPASSCAL_MASK (0x800U)
351#define ADC_CTRL_BYPASSCAL_SHIFT (11U)
352/*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset
353 * error is not a concern in the application.
354 * 0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for
355 * offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may
356 * be warranted periodically - especially if operating conditions have changed.
357 * 0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC -
358 * particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set.
359 */
360#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
361#define ADC_CTRL_TSAMP_MASK (0x7000U)
362#define ADC_CTRL_TSAMP_SHIFT (12U)
363/*! TSAMP - Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion
364 * is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions
365 * and the output impedance of the analog source, longer sampling times may be required. See
366 * Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to
367 * seven, by which the sample period will be extended. The total conversion time will increase by
368 * the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A
369 * complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will
370 * be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will
371 * require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock
372 * cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be
373 * extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require
374 * 22 ADC clocks.
375 */
376#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
377/*! @} */
378
379/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
380/*! @{ */
381#define ADC_INSEL_SEL_MASK (0x3U)
382#define ADC_INSEL_SEL_SHIFT (0U)
383/*! SEL - Selects the input source for channel 0. All other values are reserved.
384 * 0b00..ADC0_IN0 function.
385 * 0b11..Internal temperature sensor.
386 */
387#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
388/*! @} */
389
390/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
391/*! @{ */
392#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU)
393#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U)
394/*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this
395 * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be
396 * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1
397 * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via
398 * software command, ADC conversions will be performed on each enabled channel, in sequence,
399 * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31)
400 * is LOW. It is allowed to change this field and set bit 31 in the same write.
401 */
402#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
403#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U)
404#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U)
405/*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion
406 * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order
407 * to avoid generating a spurious trigger, it is recommended writing to this field only when
408 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
409 */
410#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
411#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U)
412#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U)
413/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In
414 * order to avoid generating a spurious trigger, it is recommended writing to this field only when
415 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
416 * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
417 * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
418 */
419#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
420#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U)
421#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U)
422/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization
423 * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a
424 * conversion. There are slightly different criteria for whether or not this bit can be set
425 * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0):
426 * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already
427 * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer).
428 * Whether this bit is set or not, a trigger pulse must be maintained for at least one system
429 * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be
430 * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse
431 * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and
432 * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be
433 * maintained for one system clock period.
434 * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled.
435 * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled.
436 */
437#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
438#define ADC_SEQ_CTRL_START_MASK (0x4000000U)
439#define ADC_SEQ_CTRL_START_SHIFT (26U)
440/*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The
441 * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this
442 * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a
443 * conversion sequence. It will consequently always read back as a zero.
444 */
445#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
446#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U)
447#define ADC_SEQ_CTRL_BURST_SHIFT (27U)
448/*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled
449 * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions
450 * can be halted by clearing this bit. The sequence currently in progress will be completed before
451 * conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
452 */
453#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
454#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U)
455#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U)
456/*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a
457 * single conversion on the next channel in the sequence instead of the default response of
458 * launching an entire sequence of conversions. Once all of the channels comprising a sequence have
459 * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled
460 * channel. Interrupt generation will still occur either after each individual conversion or at
461 * the end of the entire sequence, depending on the state of the MODE bit.
462 */
463#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
464#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U)
465#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U)
466/*! LOWPRIO - Set priority for sequence A.
467 * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
468 * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence
469 * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion
470 * currently in progress will be terminated. The A sequence that was interrupted will automatically resume
471 * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the
472 * conversion sequence will resume from that point.
473 */
474#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
475#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U)
476#define ADC_SEQ_CTRL_MODE_SHIFT (30U)
477/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence
478 * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each
479 * conversion, or the individual channel result registers at the end of the entire sequence. Impacts
480 * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which
481 * overrun conditions contribute to an overrun interrupt as described below.
482 * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC
483 * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The
484 * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger
485 * if enabled.
486 * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A
487 * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in
488 * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun
489 * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
490 */
491#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
492#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U)
493#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U)
494/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be
495 * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state
496 * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered
497 * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care
498 * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE
499 * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be
500 * triggered immediately upon being enabled.
501 * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence
502 * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is
503 * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
504 * 0b1..Enabled. Sequence n is enabled.
505 */
506#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
507/*! @} */
508
509/* The count of ADC_SEQ_CTRL */
510#define ADC_SEQ_CTRL_COUNT (2U)
511
512/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
513/*! @{ */
514#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U)
515#define ADC_SEQ_GDAT_RESULT_SHIFT (4U)
516/*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion
517 * performed under conversion sequence associated with this register. The result is a binary
518 * fraction representing the voltage on the currently-selected input channel as it falls within the
519 * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less
520 * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input
521 * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this
522 * result has not yet been read.
523 */
524#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
525#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U)
526#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U)
527/*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or
528 * within the range established by the designated threshold comparison registers (THRn_LOW and
529 * THRn_HIGH).
530 */
531#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
532#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U)
533#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U)
534/*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a
535 * crossing of the threshold level established by the designated LOW threshold comparison register
536 * (THRn_LOW) and, if so, in what direction the crossing occurred.
537 */
538#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
539#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U)
540#define ADC_SEQ_GDAT_CHN_SHIFT (26U)
541/*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000
542 * identifies channel 0, 0001 channel 1, etc.).
543 */
544#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
545#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U)
546#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U)
547/*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a
548 * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along
549 * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun
550 * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set
551 * to '0' (and if the overrun interrupt is enabled).
552 */
553#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
554#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U)
555#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U)
556/*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded
557 * into the RESULT field. It is cleared whenever this register is read. This bit will cause a
558 * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that
559 * sequence is set to 0 (and if the interrupt is enabled).
560 */
561#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
562/*! @} */
563
564/* The count of ADC_SEQ_GDAT */
565#define ADC_SEQ_GDAT_COUNT (2U)
566
567/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
568/*! @{ */
569#define ADC_DAT_RESULT_MASK (0xFFF0U)
570#define ADC_DAT_RESULT_SHIFT (4U)
571/*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed
572 * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin,
573 * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on
574 * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that
575 * the voltage on the input was close to, equal to, or greater than that on VREFP.
576 */
577#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
578#define ADC_DAT_THCMPRANGE_MASK (0x30000U)
579#define ADC_DAT_THCMPRANGE_SHIFT (16U)
580/*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion
581 * was greater than or equal to the value programmed into the designated LOW threshold register
582 * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold
583 * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value
584 * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last
585 * completed conversion was greater than the value programmed into the designated HIGH threshold
586 * register (THRn_HIGH). 0x3 = Reserved.
587 */
588#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
589#define ADC_DAT_THCMPCROSS_MASK (0xC0000U)
590#define ADC_DAT_THCMPCROSS_SHIFT (18U)
591/*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The
592 * most recent completed conversion on this channel had the same relationship (above or below) to
593 * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the
594 * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing
595 * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the
596 * previous sample on this channel was above the threshold value established by the designated LOW
597 * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward
598 * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred
599 * - i.e. the previous sample on this channel was below the threshold value established by the
600 * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
601 */
602#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
603#define ADC_DAT_CHANNEL_MASK (0x3C000000U)
604#define ADC_DAT_CHANNEL_SHIFT (26U)
605/*! CHANNEL - This field is hard-coded to contain the channel number that this particular register
606 * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1
607 * register, etc)
608 */
609#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
610#define ADC_DAT_OVERRUN_MASK (0x40000000U)
611#define ADC_DAT_OVERRUN_SHIFT (30U)
612/*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and
613 * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit
614 * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when
615 * the data related to this channel is read from either of the global SEQn_GDAT registers. This
616 * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if
617 * the overrun interrupt is enabled. While it is allowed to include the same channels in both
618 * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the
619 * data registers associated with any of the channels that are shared between the two sequences. Any
620 * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
621 */
622#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
623#define ADC_DAT_DATAVALID_MASK (0x80000000U)
624#define ADC_DAT_DATAVALID_SHIFT (31U)
625/*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is
626 * cleared whenever this register is read or when the data related to this channel is read from
627 * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in
628 * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in
629 * the data registers associated with any of the channels that are shared between the two
630 * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
631 */
632#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
633/*! @} */
634
635/* The count of ADC_DAT */
636#define ADC_DAT_COUNT (12U)
637
638/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
639/*! @{ */
640#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U)
641#define ADC_THR0_LOW_THRLOW_SHIFT (4U)
642/*! THRLOW - Low threshold value against which ADC results will be compared
643 */
644#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
645/*! @} */
646
647/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
648/*! @{ */
649#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U)
650#define ADC_THR1_LOW_THRLOW_SHIFT (4U)
651/*! THRLOW - Low threshold value against which ADC results will be compared
652 */
653#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
654/*! @} */
655
656/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
657/*! @{ */
658#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U)
659#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U)
660/*! THRHIGH - High threshold value against which ADC results will be compared
661 */
662#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
663/*! @} */
664
665/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
666/*! @{ */
667#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U)
668#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U)
669/*! THRHIGH - High threshold value against which ADC results will be compared
670 */
671#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
672/*! @} */
673
674/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
675/*! @{ */
676#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U)
677#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U)
678/*! CH0_THRSEL - Threshold select for channel 0.
679 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
680 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
681 */
682#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
683#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U)
684#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U)
685/*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0.
686 */
687#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
688#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U)
689#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U)
690/*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0.
691 */
692#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
693#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U)
694#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U)
695/*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0.
696 */
697#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
698#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U)
699#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U)
700/*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0.
701 */
702#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
703#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U)
704#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U)
705/*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0.
706 */
707#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
708#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U)
709#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U)
710/*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0.
711 */
712#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
713#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U)
714#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U)
715/*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0.
716 */
717#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
718#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U)
719#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U)
720/*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0.
721 */
722#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
723#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U)
724#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U)
725/*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0.
726 */
727#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
728#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U)
729#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U)
730/*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0.
731 */
732#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
733#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U)
734#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U)
735/*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0.
736 */
737#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
738/*! @} */
739
740/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
741/*! @{ */
742#define ADC_INTEN_SEQA_INTEN_MASK (0x1U)
743#define ADC_INTEN_SEQA_INTEN_SHIFT (0U)
744/*! SEQA_INTEN - Sequence A interrupt enable.
745 * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled.
746 * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of
747 * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of
748 * conversions, depending on the MODE bit in the SEQA_CTRL register.
749 */
750#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
751#define ADC_INTEN_SEQB_INTEN_MASK (0x2U)
752#define ADC_INTEN_SEQB_INTEN_SHIFT (1U)
753/*! SEQB_INTEN - Sequence B interrupt enable.
754 * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled.
755 * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of
756 * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of
757 * conversions, depending on the MODE bit in the SEQB_CTRL register.
758 */
759#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
760#define ADC_INTEN_OVR_INTEN_MASK (0x4U)
761#define ADC_INTEN_OVR_INTEN_SHIFT (2U)
762/*! OVR_INTEN - Overrun interrupt enable.
763 * 0b0..Disabled. The overrun interrupt is disabled.
764 * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel
765 * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular
766 * sequence is 0, then an overrun in the global data register for that sequence will also cause this
767 * interrupt/DMA trigger to be asserted.
768 */
769#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
770#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U)
771#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U)
772/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0.
773 * 0b00..Disabled.
774 * 0b01..Outside threshold.
775 * 0b10..Crossing threshold.
776 * 0b11..Reserved
777 */
778#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
779#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U)
780#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U)
781/*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0.
782 */
783#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
784#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U)
785#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U)
786/*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0.
787 */
788#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
789#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U)
790#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U)
791/*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0.
792 */
793#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
794#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U)
795#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U)
796/*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0.
797 */
798#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
799#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U)
800#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U)
801/*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0.
802 */
803#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
804#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U)
805#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U)
806/*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0.
807 */
808#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
809#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U)
810#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U)
811/*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0.
812 */
813#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
814#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U)
815#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U)
816/*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0.
817 */
818#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
819#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U)
820#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U)
821/*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0.
822 */
823#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
824#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U)
825#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U)
826/*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0.
827 */
828#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
829#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U)
830#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U)
831/*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0.
832 */
833#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
834/*! @} */
835
836/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
837/*! @{ */
838#define ADC_FLAGS_THCMP0_MASK (0x1U)
839#define ADC_FLAGS_THCMP0_SHIFT (0U)
840/*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or
841 * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by
842 * writing a 1.
843 */
844#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
845#define ADC_FLAGS_THCMP1_MASK (0x2U)
846#define ADC_FLAGS_THCMP1_SHIFT (1U)
847/*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0.
848 */
849#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
850#define ADC_FLAGS_THCMP2_MASK (0x4U)
851#define ADC_FLAGS_THCMP2_SHIFT (2U)
852/*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0.
853 */
854#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
855#define ADC_FLAGS_THCMP3_MASK (0x8U)
856#define ADC_FLAGS_THCMP3_SHIFT (3U)
857/*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0.
858 */
859#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
860#define ADC_FLAGS_THCMP4_MASK (0x10U)
861#define ADC_FLAGS_THCMP4_SHIFT (4U)
862/*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0.
863 */
864#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
865#define ADC_FLAGS_THCMP5_MASK (0x20U)
866#define ADC_FLAGS_THCMP5_SHIFT (5U)
867/*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0.
868 */
869#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
870#define ADC_FLAGS_THCMP6_MASK (0x40U)
871#define ADC_FLAGS_THCMP6_SHIFT (6U)
872/*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0.
873 */
874#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
875#define ADC_FLAGS_THCMP7_MASK (0x80U)
876#define ADC_FLAGS_THCMP7_SHIFT (7U)
877/*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0.
878 */
879#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
880#define ADC_FLAGS_THCMP8_MASK (0x100U)
881#define ADC_FLAGS_THCMP8_SHIFT (8U)
882/*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0.
883 */
884#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
885#define ADC_FLAGS_THCMP9_MASK (0x200U)
886#define ADC_FLAGS_THCMP9_SHIFT (9U)
887/*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0.
888 */
889#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
890#define ADC_FLAGS_THCMP10_MASK (0x400U)
891#define ADC_FLAGS_THCMP10_SHIFT (10U)
892/*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0.
893 */
894#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
895#define ADC_FLAGS_THCMP11_MASK (0x800U)
896#define ADC_FLAGS_THCMP11_SHIFT (11U)
897/*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0.
898 */
899#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
900#define ADC_FLAGS_OVERRUN0_MASK (0x1000U)
901#define ADC_FLAGS_OVERRUN0_SHIFT (12U)
902/*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0
903 */
904#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
905#define ADC_FLAGS_OVERRUN1_MASK (0x2000U)
906#define ADC_FLAGS_OVERRUN1_SHIFT (13U)
907/*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1
908 */
909#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
910#define ADC_FLAGS_OVERRUN2_MASK (0x4000U)
911#define ADC_FLAGS_OVERRUN2_SHIFT (14U)
912/*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2
913 */
914#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
915#define ADC_FLAGS_OVERRUN3_MASK (0x8000U)
916#define ADC_FLAGS_OVERRUN3_SHIFT (15U)
917/*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3
918 */
919#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
920#define ADC_FLAGS_OVERRUN4_MASK (0x10000U)
921#define ADC_FLAGS_OVERRUN4_SHIFT (16U)
922/*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4
923 */
924#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
925#define ADC_FLAGS_OVERRUN5_MASK (0x20000U)
926#define ADC_FLAGS_OVERRUN5_SHIFT (17U)
927/*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5
928 */
929#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
930#define ADC_FLAGS_OVERRUN6_MASK (0x40000U)
931#define ADC_FLAGS_OVERRUN6_SHIFT (18U)
932/*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6
933 */
934#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
935#define ADC_FLAGS_OVERRUN7_MASK (0x80000U)
936#define ADC_FLAGS_OVERRUN7_SHIFT (19U)
937/*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7
938 */
939#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
940#define ADC_FLAGS_OVERRUN8_MASK (0x100000U)
941#define ADC_FLAGS_OVERRUN8_SHIFT (20U)
942/*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8
943 */
944#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
945#define ADC_FLAGS_OVERRUN9_MASK (0x200000U)
946#define ADC_FLAGS_OVERRUN9_SHIFT (21U)
947/*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9
948 */
949#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
950#define ADC_FLAGS_OVERRUN10_MASK (0x400000U)
951#define ADC_FLAGS_OVERRUN10_SHIFT (22U)
952/*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10
953 */
954#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
955#define ADC_FLAGS_OVERRUN11_MASK (0x800000U)
956#define ADC_FLAGS_OVERRUN11_SHIFT (23U)
957/*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11
958 */
959#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
960#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U)
961#define ADC_FLAGS_SEQA_OVR_SHIFT (24U)
962/*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register
963 */
964#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
965#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U)
966#define ADC_FLAGS_SEQB_OVR_SHIFT (25U)
967/*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register
968 */
969#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
970#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U)
971#define ADC_FLAGS_SEQA_INT_SHIFT (28U)
972/*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0,
973 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which
974 * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared
975 * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register
976 * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be
977 * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN
978 * register.
979 */
980#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
981#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U)
982#define ADC_FLAGS_SEQB_INT_SHIFT (29U)
983/*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0,
984 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which
985 * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared
986 * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register
987 * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be
988 * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN
989 * register.
990 */
991#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
992#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U)
993#define ADC_FLAGS_THCMP_INT_SHIFT (30U)
994/*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in
995 * the lower bits of this register are set to 1 (due to an enabled out-of-range or
996 * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be
997 * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared
998 * when all of the individual threshold flags are cleared via writing 1s to those bits.
999 */
1000#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
1001#define ADC_FLAGS_OVR_INT_MASK (0x80000000U)
1002#define ADC_FLAGS_OVR_INT_SHIFT (31U)
1003/*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data
1004 * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers
1005 * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this
1006 * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all
1007 * of the individual overrun bits have been cleared via reading the corresponding data registers.
1008 */
1009#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
1010/*! @} */
1011
1012/*! @name STARTUP - ADC Startup register. */
1013/*! @{ */
1014#define ADC_STARTUP_ADC_ENA_MASK (0x1U)
1015#define ADC_STARTUP_ADC_ENA_SHIFT (0U)
1016/*! ADC_ENA - ADC Enable bit. This bit can only be set to a 1 by software. It is cleared
1017 * automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds
1018 * after the ADC is powered up (typically by altering a system-level ADC power control bit).
1019 */
1020#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
1021#define ADC_STARTUP_ADC_INIT_MASK (0x2U)
1022#define ADC_STARTUP_ADC_INIT_SHIFT (1U)
1023/*! ADC_INIT - ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine
1024 * will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not
1025 * calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is
1026 * required if a calibration is not performed. It will also reload the stored calibration value from
1027 * a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the
1028 * ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or
1029 * an ADC dummy conversion cycle is required. It should not be set during the same write that
1030 * sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically
1031 * when the 'dummy' conversion cycle completes.
1032 */
1033#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
1034/*! @} */
1035
1036/*! @name CALIB - ADC Calibration register. */
1037/*! @{ */
1038#define ADC_CALIB_CALIB_MASK (0x1U)
1039#define ADC_CALIB_CALIB_SHIFT (0U)
1040/*! CALIB - Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can
1041 * only be set to a '1' by software. It is cleared automatically when the calibration cycle
1042 * completes.
1043 */
1044#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
1045#define ADC_CALIB_CALREQD_MASK (0x2U)
1046#define ADC_CALIB_CALREQD_SHIFT (1U)
1047/*! CALREQD - Calibration required. This read-only bit indicates if calibration is required when
1048 * enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was
1049 * powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to
1050 * determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP
1051 * register) to launch the ADC initialization process which includes a 'dummy' conversion cycle.
1052 * Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks
1053 * required for calibration.
1054 */
1055#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
1056#define ADC_CALIB_CALVALUE_MASK (0x1FCU)
1057#define ADC_CALIB_CALVALUE_SHIFT (2U)
1058/*! CALVALUE - Calibration Value. This read-only field displays the calibration value established
1059 * during last calibration cycle. This value is not typically of any use to the user.
1060 */
1061#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
1062/*! @} */
1063
1064
1065/*!
1066 * @}
1067 */ /* end of group ADC_Register_Masks */
1068
1069
1070/* ADC - Peripheral instance base addresses */
1071/** Peripheral ADC0 base address */
1072#define ADC0_BASE (0x400A0000u)
1073/** Peripheral ADC0 base pointer */
1074#define ADC0 ((ADC_Type *)ADC0_BASE)
1075/** Array initializer of ADC peripheral base addresses */
1076#define ADC_BASE_ADDRS { ADC0_BASE }
1077/** Array initializer of ADC peripheral base pointers */
1078#define ADC_BASE_PTRS { ADC0 }
1079/** Interrupt vectors for the ADC peripheral type */
1080#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
1081#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn }
1082
1083/*!
1084 * @}
1085 */ /* end of group ADC_Peripheral_Access_Layer */
1086
1087
1088/* ----------------------------------------------------------------------------
1089 -- ASYNC_SYSCON Peripheral Access Layer
1090 ---------------------------------------------------------------------------- */
1091
1092/*!
1093 * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
1094 * @{
1095 */
1096
1097/** ASYNC_SYSCON - Register Layout Typedef */
1098typedef struct {
1099 __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */
1100 __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
1101 __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
1102 uint8_t RESERVED_0[4];
1103 __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */
1104 __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
1105 __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
1106 uint8_t RESERVED_1[4];
1107 __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */
1108} ASYNC_SYSCON_Type;
1109
1110/* ----------------------------------------------------------------------------
1111 -- ASYNC_SYSCON Register Masks
1112 ---------------------------------------------------------------------------- */
1113
1114/*!
1115 * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
1116 * @{
1117 */
1118
1119/*! @name ASYNCPRESETCTRL - Async peripheral reset control */
1120/*! @{ */
1121#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
1122#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
1123/*! CTIMER3 - Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
1124 */
1125#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
1126#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
1127#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
1128/*! CTIMER4 - Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
1129 */
1130#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
1131/*! @} */
1132
1133/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
1134/*! @{ */
1135#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
1136#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
1137/*! ARST_SET - Writing ones to this register sets the corresponding bit or bits in the
1138 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1139 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1140 */
1141#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
1142/*! @} */
1143
1144/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
1145/*! @{ */
1146#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
1147#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
1148/*! ARST_CLR - Writing ones to this register clears the corresponding bit or bits in the
1149 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1150 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1151 */
1152#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
1153/*! @} */
1154
1155/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
1156/*! @{ */
1157#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
1158#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
1159/*! CTIMER3 - Controls the clock for CTIMER3. 0 = Disable; 1 = Enable.
1160 */
1161#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
1162#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
1163#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
1164/*! CTIMER4 - Controls the clock for CTIMER4. 0 = Disable; 1 = Enable.
1165 */
1166#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
1167/*! @} */
1168
1169/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
1170/*! @{ */
1171#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
1172#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
1173/*! ACLK_SET - Writing ones to this register sets the corresponding bit or bits in the
1174 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1175 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1176 */
1177#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
1178/*! @} */
1179
1180/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
1181/*! @{ */
1182#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
1183#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
1184/*! ACLK_CLR - Writing ones to this register clears the corresponding bit or bits in the
1185 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1186 * ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them.
1187 */
1188#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
1189/*! @} */
1190
1191/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
1192/*! @{ */
1193#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U)
1194#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U)
1195/*! SEL - Clock source for asynchronous clock source selector A
1196 * 0b00..Main clock (main_clk)
1197 * 0b01..FRO 12 MHz (fro_12m)
1198 * 0b10..Audio PLL clock.(AUDPLL_BYPASS)
1199 * 0b11..fc6 fclk (fc6_fclk)
1200 */
1201#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
1202/*! @} */
1203
1204
1205/*!
1206 * @}
1207 */ /* end of group ASYNC_SYSCON_Register_Masks */
1208
1209
1210/* ASYNC_SYSCON - Peripheral instance base addresses */
1211/** Peripheral ASYNC_SYSCON base address */
1212#define ASYNC_SYSCON_BASE (0x40040000u)
1213/** Peripheral ASYNC_SYSCON base pointer */
1214#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
1215/** Array initializer of ASYNC_SYSCON peripheral base addresses */
1216#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE }
1217/** Array initializer of ASYNC_SYSCON peripheral base pointers */
1218#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON }
1219
1220/*!
1221 * @}
1222 */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
1223
1224
1225/* ----------------------------------------------------------------------------
1226 -- CAN Peripheral Access Layer
1227 ---------------------------------------------------------------------------- */
1228
1229/*!
1230 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
1231 * @{
1232 */
1233
1234/** CAN - Register Layout Typedef */
1235typedef struct {
1236 uint8_t RESERVED_0[16];
1237 __IO uint32_t TEST; /**< Test Register, offset: 0x10 */
1238 uint8_t RESERVED_1[4];
1239 __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */
1240 __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */
1241 __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */
1242 __IO uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */
1243 __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */
1244 __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */
1245 uint8_t RESERVED_2[16];
1246 __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */
1247 __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */
1248 __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */
1249 uint8_t RESERVED_3[4];
1250 __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */
1251 __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */
1252 __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */
1253 __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */
1254 uint8_t RESERVED_4[32];
1255 __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */
1256 __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */
1257 __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */
1258 uint8_t RESERVED_5[4];
1259 __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */
1260 __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */
1261 __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */
1262 __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */
1263 __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */
1264 __IO uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */
1265 __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */
1266 __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */
1267 __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */
1268 __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */
1269 __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */
1270 __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */
1271 __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */
1272 __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */
1273 __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */
1274 __IO uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */
1275 __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */
1276 __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */
1277 __IO uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */
1278 __IO uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */
1279 __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */
1280 __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */
1281 uint8_t RESERVED_6[8];
1282 __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */
1283 __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */
1284 __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */
1285 uint8_t RESERVED_7[260];
1286 __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */
1287 uint8_t RESERVED_8[508];
1288 __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */
1289 uint8_t RESERVED_9[508];
1290 __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */
1291} CAN_Type;
1292
1293/* ----------------------------------------------------------------------------
1294 -- CAN Register Masks
1295 ---------------------------------------------------------------------------- */
1296
1297/*!
1298 * @addtogroup CAN_Register_Masks CAN Register Masks
1299 * @{
1300 */
1301
1302/*! @name TEST - Test Register */
1303/*! @{ */
1304#define CAN_TEST_LBCK_MASK (0x10U)
1305#define CAN_TEST_LBCK_SHIFT (4U)
1306/*! LBCK - Loop back mode.
1307 */
1308#define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)
1309#define CAN_TEST_TX_MASK (0x60U)
1310#define CAN_TEST_TX_SHIFT (5U)
1311/*! TX - Control of transmit pin.
1312 */
1313#define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)
1314#define CAN_TEST_RX_MASK (0x80U)
1315#define CAN_TEST_RX_SHIFT (7U)
1316/*! RX - Monitors the actual value of the CAN_RXD.
1317 */
1318#define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)
1319/*! @} */
1320
1321/*! @name CCCR - CC Control Register */
1322/*! @{ */
1323#define CAN_CCCR_INIT_MASK (0x1U)
1324#define CAN_CCCR_INIT_SHIFT (0U)
1325/*! INIT - Initialization.
1326 */
1327#define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)
1328#define CAN_CCCR_CCE_MASK (0x2U)
1329#define CAN_CCCR_CCE_SHIFT (1U)
1330/*! CCE - Configuration change enable.
1331 */
1332#define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)
1333#define CAN_CCCR_ASM_MASK (0x4U)
1334#define CAN_CCCR_ASM_SHIFT (2U)
1335/*! ASM - Restricted operational mode.
1336 */
1337#define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)
1338#define CAN_CCCR_CSA_MASK (0x8U)
1339#define CAN_CCCR_CSA_SHIFT (3U)
1340/*! CSA - Clock Stop Acknowledge.
1341 */
1342#define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)
1343#define CAN_CCCR_CSR_MASK (0x10U)
1344#define CAN_CCCR_CSR_SHIFT (4U)
1345/*! CSR - Clock Stop Request.
1346 */
1347#define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)
1348#define CAN_CCCR_MON_MASK (0x20U)
1349#define CAN_CCCR_MON_SHIFT (5U)
1350/*! MON - Bus monitoring mode.
1351 */
1352#define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)
1353#define CAN_CCCR_DAR_MASK (0x40U)
1354#define CAN_CCCR_DAR_SHIFT (6U)
1355/*! DAR - Disable automatic retransmission.
1356 */
1357#define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)
1358#define CAN_CCCR_TEST_MASK (0x80U)
1359#define CAN_CCCR_TEST_SHIFT (7U)
1360/*! TEST - Test mode enable.
1361 */
1362#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
1363#define CAN_CCCR_PXHD_MASK (0x1000U)
1364#define CAN_CCCR_PXHD_SHIFT (12U)
1365/*! PXHD - Protocol exception handling disable.
1366 */
1367#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
1368#define CAN_CCCR_EFBI_MASK (0x2000U)
1369#define CAN_CCCR_EFBI_SHIFT (13U)
1370/*! EFBI - Edge filtering during bus integration.
1371 */
1372#define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)
1373#define CAN_CCCR_TXP_MASK (0x4000U)
1374#define CAN_CCCR_TXP_SHIFT (14U)
1375/*! TXP - Transmit pause.
1376 */
1377#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
1378/*! @} */
1379
1380/*! @name NBTP - Nominal Bit Timing and Prescaler Register */
1381/*! @{ */
1382#define CAN_NBTP_NTSEG2_MASK (0x7FU)
1383#define CAN_NBTP_NTSEG2_SHIFT (0U)
1384/*! NTSEG2 - Nominal time segment after sample point.
1385 */
1386#define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)
1387#define CAN_NBTP_NTSEG1_MASK (0xFF00U)
1388#define CAN_NBTP_NTSEG1_SHIFT (8U)
1389/*! NTSEG1 - Nominal time segment before sample point.
1390 */
1391#define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)
1392#define CAN_NBTP_NBRP_MASK (0x1FF0000U)
1393#define CAN_NBTP_NBRP_SHIFT (16U)
1394/*! NBRP - Nominal bit rate prescaler.
1395 */
1396#define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)
1397#define CAN_NBTP_NSJW_MASK (0xFE000000U)
1398#define CAN_NBTP_NSJW_SHIFT (25U)
1399/*! NSJW - Nominal (re)synchronization jump width.
1400 */
1401#define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)
1402/*! @} */
1403
1404/*! @name TSCC - Timestamp Counter Configuration */
1405/*! @{ */
1406#define CAN_TSCC_TSS_MASK (0x3U)
1407#define CAN_TSCC_TSS_SHIFT (0U)
1408/*! TSS - Timestamp select.
1409 */
1410#define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)
1411#define CAN_TSCC_TCP_MASK (0xF0000U)
1412#define CAN_TSCC_TCP_SHIFT (16U)
1413/*! TCP - Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times.
1414 */
1415#define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)
1416/*! @} */
1417
1418/*! @name TSCV - Timestamp Counter Value */
1419/*! @{ */
1420#define CAN_TSCV_TSC_MASK (0xFFFFU)
1421#define CAN_TSCV_TSC_SHIFT (0U)
1422/*! TSC - Timestamp counter.
1423 */
1424#define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)
1425/*! @} */
1426
1427/*! @name TOCC - Timeout Counter Configuration */
1428/*! @{ */
1429#define CAN_TOCC_ETOC_MASK (0x1U)
1430#define CAN_TOCC_ETOC_SHIFT (0U)
1431/*! ETOC - Enable timeout counter.
1432 */
1433#define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)
1434#define CAN_TOCC_TOS_MASK (0x6U)
1435#define CAN_TOCC_TOS_SHIFT (1U)
1436/*! TOS - Timeout select.
1437 */
1438#define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)
1439#define CAN_TOCC_TOP_MASK (0xFFFF0000U)
1440#define CAN_TOCC_TOP_SHIFT (16U)
1441/*! TOP - Timeout period.
1442 */
1443#define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)
1444/*! @} */
1445
1446/*! @name TOCV - Timeout Counter Value */
1447/*! @{ */
1448#define CAN_TOCV_TOC_MASK (0xFFFFU)
1449#define CAN_TOCV_TOC_SHIFT (0U)
1450/*! TOC - Timeout counter.
1451 */
1452#define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)
1453/*! @} */
1454
1455/*! @name ECR - Error Counter Register */
1456/*! @{ */
1457#define CAN_ECR_TEC_MASK (0xFFU)
1458#define CAN_ECR_TEC_SHIFT (0U)
1459/*! TEC - Transmit error counter.
1460 */
1461#define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)
1462#define CAN_ECR_REC_MASK (0x7F00U)
1463#define CAN_ECR_REC_SHIFT (8U)
1464/*! REC - Receive error counter.
1465 */
1466#define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)
1467#define CAN_ECR_RP_MASK (0x8000U)
1468#define CAN_ECR_RP_SHIFT (15U)
1469/*! RP - Receive error passive.
1470 */
1471#define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)
1472#define CAN_ECR_CEL_MASK (0xFF0000U)
1473#define CAN_ECR_CEL_SHIFT (16U)
1474/*! CEL - CAN error logging.
1475 */
1476#define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)
1477/*! @} */
1478
1479/*! @name PSR - Protocol Status Register */
1480/*! @{ */
1481#define CAN_PSR_LEC_MASK (0x7U)
1482#define CAN_PSR_LEC_SHIFT (0U)
1483/*! LEC - Last error code.
1484 */
1485#define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)
1486#define CAN_PSR_ACT_MASK (0x18U)
1487#define CAN_PSR_ACT_SHIFT (3U)
1488/*! ACT - Activity.
1489 */
1490#define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)
1491#define CAN_PSR_EP_MASK (0x20U)
1492#define CAN_PSR_EP_SHIFT (5U)
1493/*! EP - Error Passive.
1494 */
1495#define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)
1496#define CAN_PSR_EW_MASK (0x40U)
1497#define CAN_PSR_EW_SHIFT (6U)
1498/*! EW - Warning status.
1499 */
1500#define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)
1501#define CAN_PSR_BO_MASK (0x80U)
1502#define CAN_PSR_BO_SHIFT (7U)
1503/*! BO - Bus Off Status.
1504 */
1505#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
1506#define CAN_PSR_PXE_MASK (0x4000U)
1507#define CAN_PSR_PXE_SHIFT (14U)
1508/*! PXE - Protocol exception event.
1509 */
1510#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
1511#define CAN_PSR_TDCV_MASK (0x7F0000U)
1512#define CAN_PSR_TDCV_SHIFT (16U)
1513/*! TDCV - Transmitter delay compensation value.
1514 */
1515#define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)
1516/*! @} */
1517
1518/*! @name TDCR - Transmitter Delay Compensator Register */
1519/*! @{ */
1520#define CAN_TDCR_TDCF_MASK (0x7FU)
1521#define CAN_TDCR_TDCF_SHIFT (0U)
1522/*! TDCF - Transmitter delay compensation filter window length.
1523 */
1524#define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)
1525#define CAN_TDCR_TDCO_MASK (0x7F00U)
1526#define CAN_TDCR_TDCO_SHIFT (8U)
1527/*! TDCO - Transmitter delay compensation offset.
1528 */
1529#define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)
1530/*! @} */
1531
1532/*! @name IR - Interrupt Register */
1533/*! @{ */
1534#define CAN_IR_RF0N_MASK (0x1U)
1535#define CAN_IR_RF0N_SHIFT (0U)
1536/*! RF0N - Rx FIFO 0 new message.
1537 */
1538#define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)
1539#define CAN_IR_RF0W_MASK (0x2U)
1540#define CAN_IR_RF0W_SHIFT (1U)
1541/*! RF0W - Rx FIFO 0 watermark reached.
1542 */
1543#define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)
1544#define CAN_IR_RF0F_MASK (0x4U)
1545#define CAN_IR_RF0F_SHIFT (2U)
1546/*! RF0F - Rx FIFO 0 full.
1547 */
1548#define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)
1549#define CAN_IR_RF0L_MASK (0x8U)
1550#define CAN_IR_RF0L_SHIFT (3U)
1551/*! RF0L - Rx FIFO 0 message lost.
1552 */
1553#define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)
1554#define CAN_IR_RF1N_MASK (0x10U)
1555#define CAN_IR_RF1N_SHIFT (4U)
1556/*! RF1N - Rx FIFO 1 new message.
1557 */
1558#define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)
1559#define CAN_IR_RF1W_MASK (0x20U)
1560#define CAN_IR_RF1W_SHIFT (5U)
1561/*! RF1W - Rx FIFO 1 watermark reached.
1562 */
1563#define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)
1564#define CAN_IR_RF1F_MASK (0x40U)
1565#define CAN_IR_RF1F_SHIFT (6U)
1566/*! RF1F - Rx FIFO 1 full.
1567 */
1568#define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)
1569#define CAN_IR_RF1L_MASK (0x80U)
1570#define CAN_IR_RF1L_SHIFT (7U)
1571/*! RF1L - Rx FIFO 1 message lost.
1572 */
1573#define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)
1574#define CAN_IR_HPM_MASK (0x100U)
1575#define CAN_IR_HPM_SHIFT (8U)
1576/*! HPM - High priority message.
1577 */
1578#define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)
1579#define CAN_IR_TC_MASK (0x200U)
1580#define CAN_IR_TC_SHIFT (9U)
1581/*! TC - Transmission completed.
1582 */
1583#define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)
1584#define CAN_IR_TCF_MASK (0x400U)
1585#define CAN_IR_TCF_SHIFT (10U)
1586/*! TCF - Transmission cancellation finished.
1587 */
1588#define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)
1589#define CAN_IR_TFE_MASK (0x800U)
1590#define CAN_IR_TFE_SHIFT (11U)
1591/*! TFE - Tx FIFO empty.
1592 */
1593#define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)
1594#define CAN_IR_TEFN_MASK (0x1000U)
1595#define CAN_IR_TEFN_SHIFT (12U)
1596/*! TEFN - Tx event FIFO new entry.
1597 */
1598#define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)
1599#define CAN_IR_TEFW_MASK (0x2000U)
1600#define CAN_IR_TEFW_SHIFT (13U)
1601/*! TEFW - Tx event FIFO watermark reached.
1602 */
1603#define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)
1604#define CAN_IR_TEFF_MASK (0x4000U)
1605#define CAN_IR_TEFF_SHIFT (14U)
1606/*! TEFF - Tx event FIFO full.
1607 */
1608#define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)
1609#define CAN_IR_TEFL_MASK (0x8000U)
1610#define CAN_IR_TEFL_SHIFT (15U)
1611/*! TEFL - Tx event FIFO element lost.
1612 */
1613#define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)
1614#define CAN_IR_TSW_MASK (0x10000U)
1615#define CAN_IR_TSW_SHIFT (16U)
1616/*! TSW - Timestamp wraparound.
1617 */
1618#define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)
1619#define CAN_IR_MRAF_MASK (0x20000U)
1620#define CAN_IR_MRAF_SHIFT (17U)
1621/*! MRAF - Message RAM access failure.
1622 */
1623#define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)
1624#define CAN_IR_TOO_MASK (0x40000U)
1625#define CAN_IR_TOO_SHIFT (18U)
1626/*! TOO - Timeout occurred.
1627 */
1628#define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)
1629#define CAN_IR_DRX_MASK (0x80000U)
1630#define CAN_IR_DRX_SHIFT (19U)
1631/*! DRX - Message stored in dedicated Rx buffer.
1632 */
1633#define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)
1634#define CAN_IR_BEC_MASK (0x100000U)
1635#define CAN_IR_BEC_SHIFT (20U)
1636/*! BEC - Bit error corrected.
1637 */
1638#define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)
1639#define CAN_IR_BEU_MASK (0x200000U)
1640#define CAN_IR_BEU_SHIFT (21U)
1641/*! BEU - Bit error uncorrected.
1642 */
1643#define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)
1644#define CAN_IR_ELO_MASK (0x400000U)
1645#define CAN_IR_ELO_SHIFT (22U)
1646/*! ELO - Error logging overflow.
1647 */
1648#define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK)
1649#define CAN_IR_EP_MASK (0x800000U)
1650#define CAN_IR_EP_SHIFT (23U)
1651/*! EP - Error passive.
1652 */
1653#define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK)
1654#define CAN_IR_EW_MASK (0x1000000U)
1655#define CAN_IR_EW_SHIFT (24U)
1656/*! EW - Warning status.
1657 */
1658#define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK)
1659#define CAN_IR_BO_MASK (0x2000000U)
1660#define CAN_IR_BO_SHIFT (25U)
1661/*! BO - Bus_Off Status.
1662 */
1663#define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK)
1664#define CAN_IR_WDI_MASK (0x4000000U)
1665#define CAN_IR_WDI_SHIFT (26U)
1666/*! WDI - Watchdog interrupt.
1667 */
1668#define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK)
1669#define CAN_IR_PEA_MASK (0x8000000U)
1670#define CAN_IR_PEA_SHIFT (27U)
1671/*! PEA - Protocol error in arbitration phase.
1672 */
1673#define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK)
1674#define CAN_IR_PED_MASK (0x10000000U)
1675#define CAN_IR_PED_SHIFT (28U)
1676/*! PED - Protocol error in data phase.
1677 */
1678#define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK)
1679#define CAN_IR_ARA_MASK (0x20000000U)
1680#define CAN_IR_ARA_SHIFT (29U)
1681/*! ARA - Access to reserved address.
1682 */
1683#define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK)
1684/*! @} */
1685
1686/*! @name IE - Interrupt Enable */
1687/*! @{ */
1688#define CAN_IE_RF0NE_MASK (0x1U)
1689#define CAN_IE_RF0NE_SHIFT (0U)
1690/*! RF0NE - Rx FIFO 0 new message interrupt enable.
1691 */
1692#define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK)
1693#define CAN_IE_RF0WE_MASK (0x2U)
1694#define CAN_IE_RF0WE_SHIFT (1U)
1695/*! RF0WE - Rx FIFO 0 watermark reached interrupt enable.
1696 */
1697#define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK)
1698#define CAN_IE_RF0FE_MASK (0x4U)
1699#define CAN_IE_RF0FE_SHIFT (2U)
1700/*! RF0FE - Rx FIFO 0 full interrupt enable.
1701 */
1702#define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK)
1703#define CAN_IE_RF0LE_MASK (0x8U)
1704#define CAN_IE_RF0LE_SHIFT (3U)
1705/*! RF0LE - Rx FIFO 0 message lost interrupt enable.
1706 */
1707#define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK)
1708#define CAN_IE_RF1NE_MASK (0x10U)
1709#define CAN_IE_RF1NE_SHIFT (4U)
1710/*! RF1NE - Rx FIFO 1 new message interrupt enable.
1711 */
1712#define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK)
1713#define CAN_IE_RF1WE_MASK (0x20U)
1714#define CAN_IE_RF1WE_SHIFT (5U)
1715/*! RF1WE - Rx FIFO 1 watermark reached interrupt enable.
1716 */
1717#define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK)
1718#define CAN_IE_RF1FE_MASK (0x40U)
1719#define CAN_IE_RF1FE_SHIFT (6U)
1720/*! RF1FE - Rx FIFO 1 full interrupt enable.
1721 */
1722#define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK)
1723#define CAN_IE_RF1LE_MASK (0x80U)
1724#define CAN_IE_RF1LE_SHIFT (7U)
1725/*! RF1LE - Rx FIFO 1 message lost interrupt enable.
1726 */
1727#define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK)
1728#define CAN_IE_HPME_MASK (0x100U)
1729#define CAN_IE_HPME_SHIFT (8U)
1730/*! HPME - High priority message interrupt enable.
1731 */
1732#define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK)
1733#define CAN_IE_TCE_MASK (0x200U)
1734#define CAN_IE_TCE_SHIFT (9U)
1735/*! TCE - Transmission completed interrupt enable.
1736 */
1737#define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK)
1738#define CAN_IE_TCFE_MASK (0x400U)
1739#define CAN_IE_TCFE_SHIFT (10U)
1740/*! TCFE - Transmission cancellation finished interrupt enable.
1741 */
1742#define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK)
1743#define CAN_IE_TFEE_MASK (0x800U)
1744#define CAN_IE_TFEE_SHIFT (11U)
1745/*! TFEE - Tx FIFO empty interrupt enable.
1746 */
1747#define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK)
1748#define CAN_IE_TEFNE_MASK (0x1000U)
1749#define CAN_IE_TEFNE_SHIFT (12U)
1750/*! TEFNE - Tx event FIFO new entry interrupt enable.
1751 */
1752#define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK)
1753#define CAN_IE_TEFWE_MASK (0x2000U)
1754#define CAN_IE_TEFWE_SHIFT (13U)
1755/*! TEFWE - Tx event FIFO watermark reached interrupt enable.
1756 */
1757#define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK)
1758#define CAN_IE_TEFFE_MASK (0x4000U)
1759#define CAN_IE_TEFFE_SHIFT (14U)
1760/*! TEFFE - Tx event FIFO full interrupt enable.
1761 */
1762#define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK)
1763#define CAN_IE_TEFLE_MASK (0x8000U)
1764#define CAN_IE_TEFLE_SHIFT (15U)
1765/*! TEFLE - Tx event FIFO element lost interrupt enable.
1766 */
1767#define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK)
1768#define CAN_IE_TSWE_MASK (0x10000U)
1769#define CAN_IE_TSWE_SHIFT (16U)
1770/*! TSWE - Timestamp wraparound interrupt enable.
1771 */
1772#define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK)
1773#define CAN_IE_MRAFE_MASK (0x20000U)
1774#define CAN_IE_MRAFE_SHIFT (17U)
1775/*! MRAFE - Message RAM access failure interrupt enable.
1776 */
1777#define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK)
1778#define CAN_IE_TOOE_MASK (0x40000U)
1779#define CAN_IE_TOOE_SHIFT (18U)
1780/*! TOOE - Timeout occurred interrupt enable.
1781 */
1782#define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK)
1783#define CAN_IE_DRXE_MASK (0x80000U)
1784#define CAN_IE_DRXE_SHIFT (19U)
1785/*! DRXE - Message stored in dedicated Rx buffer interrupt enable.
1786 */
1787#define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK)
1788#define CAN_IE_BECE_MASK (0x100000U)
1789#define CAN_IE_BECE_SHIFT (20U)
1790/*! BECE - Bit error corrected interrupt enable.
1791 */
1792#define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK)
1793#define CAN_IE_BEUE_MASK (0x200000U)
1794#define CAN_IE_BEUE_SHIFT (21U)
1795/*! BEUE - Bit error uncorrected interrupt enable.
1796 */
1797#define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK)
1798#define CAN_IE_ELOE_MASK (0x400000U)
1799#define CAN_IE_ELOE_SHIFT (22U)
1800/*! ELOE - Error logging overflow interrupt enable.
1801 */
1802#define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK)
1803#define CAN_IE_EPE_MASK (0x800000U)
1804#define CAN_IE_EPE_SHIFT (23U)
1805/*! EPE - Error passive interrupt enable.
1806 */
1807#define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK)
1808#define CAN_IE_EWE_MASK (0x1000000U)
1809#define CAN_IE_EWE_SHIFT (24U)
1810/*! EWE - Warning status interrupt enable.
1811 */
1812#define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK)
1813#define CAN_IE_BOE_MASK (0x2000000U)
1814#define CAN_IE_BOE_SHIFT (25U)
1815/*! BOE - Bus_Off Status interrupt enable.
1816 */
1817#define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK)
1818#define CAN_IE_WDIE_MASK (0x4000000U)
1819#define CAN_IE_WDIE_SHIFT (26U)
1820/*! WDIE - Watchdog interrupt enable.
1821 */
1822#define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK)
1823#define CAN_IE_PEAE_MASK (0x8000000U)
1824#define CAN_IE_PEAE_SHIFT (27U)
1825/*! PEAE - Protocol error in arbitration phase interrupt enable.
1826 */
1827#define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK)
1828#define CAN_IE_PEDE_MASK (0x10000000U)
1829#define CAN_IE_PEDE_SHIFT (28U)
1830/*! PEDE - Protocol error in data phase interrupt enable.
1831 */
1832#define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK)
1833#define CAN_IE_ARAE_MASK (0x20000000U)
1834#define CAN_IE_ARAE_SHIFT (29U)
1835/*! ARAE - Access to reserved address interrupt enable.
1836 */
1837#define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK)
1838/*! @} */
1839
1840/*! @name ILS - Interrupt Line Select */
1841/*! @{ */
1842#define CAN_ILS_RF0NL_MASK (0x1U)
1843#define CAN_ILS_RF0NL_SHIFT (0U)
1844/*! RF0NL - Rx FIFO 0 new message interrupt line.
1845 */
1846#define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK)
1847#define CAN_ILS_RF0WL_MASK (0x2U)
1848#define CAN_ILS_RF0WL_SHIFT (1U)
1849/*! RF0WL - Rx FIFO 0 watermark reached interrupt line.
1850 */
1851#define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK)
1852#define CAN_ILS_RF0FL_MASK (0x4U)
1853#define CAN_ILS_RF0FL_SHIFT (2U)
1854/*! RF0FL - Rx FIFO 0 full interrupt line.
1855 */
1856#define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK)
1857#define CAN_ILS_RF0LL_MASK (0x8U)
1858#define CAN_ILS_RF0LL_SHIFT (3U)
1859/*! RF0LL - Rx FIFO 0 message lost interrupt line.
1860 */
1861#define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK)
1862#define CAN_ILS_RF1NL_MASK (0x10U)
1863#define CAN_ILS_RF1NL_SHIFT (4U)
1864/*! RF1NL - Rx FIFO 1 new message interrupt line.
1865 */
1866#define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK)
1867#define CAN_ILS_RF1WL_MASK (0x20U)
1868#define CAN_ILS_RF1WL_SHIFT (5U)
1869/*! RF1WL - Rx FIFO 1 watermark reached interrupt line.
1870 */
1871#define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK)
1872#define CAN_ILS_RF1FL_MASK (0x40U)
1873#define CAN_ILS_RF1FL_SHIFT (6U)
1874/*! RF1FL - Rx FIFO 1 full interrupt line.
1875 */
1876#define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK)
1877#define CAN_ILS_RF1LL_MASK (0x80U)
1878#define CAN_ILS_RF1LL_SHIFT (7U)
1879/*! RF1LL - Rx FIFO 1 message lost interrupt line.
1880 */
1881#define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK)
1882#define CAN_ILS_HPML_MASK (0x100U)
1883#define CAN_ILS_HPML_SHIFT (8U)
1884/*! HPML - High priority message interrupt line.
1885 */
1886#define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK)
1887#define CAN_ILS_TCL_MASK (0x200U)
1888#define CAN_ILS_TCL_SHIFT (9U)
1889/*! TCL - Transmission completed interrupt line.
1890 */
1891#define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK)
1892#define CAN_ILS_TCFL_MASK (0x400U)
1893#define CAN_ILS_TCFL_SHIFT (10U)
1894/*! TCFL - Transmission cancellation finished interrupt line.
1895 */
1896#define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK)
1897#define CAN_ILS_TFEL_MASK (0x800U)
1898#define CAN_ILS_TFEL_SHIFT (11U)
1899/*! TFEL - Tx FIFO empty interrupt line.
1900 */
1901#define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK)
1902#define CAN_ILS_TEFNL_MASK (0x1000U)
1903#define CAN_ILS_TEFNL_SHIFT (12U)
1904/*! TEFNL - Tx event FIFO new entry interrupt line.
1905 */
1906#define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK)
1907#define CAN_ILS_TEFWL_MASK (0x2000U)
1908#define CAN_ILS_TEFWL_SHIFT (13U)
1909/*! TEFWL - Tx event FIFO watermark reached interrupt line.
1910 */
1911#define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK)
1912#define CAN_ILS_TEFFL_MASK (0x4000U)
1913#define CAN_ILS_TEFFL_SHIFT (14U)
1914/*! TEFFL - Tx event FIFO full interrupt line.
1915 */
1916#define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK)
1917#define CAN_ILS_TEFLL_MASK (0x8000U)
1918#define CAN_ILS_TEFLL_SHIFT (15U)
1919/*! TEFLL - Tx event FIFO element lost interrupt line.
1920 */
1921#define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK)
1922#define CAN_ILS_TSWL_MASK (0x10000U)
1923#define CAN_ILS_TSWL_SHIFT (16U)
1924/*! TSWL - Timestamp wraparound interrupt line.
1925 */
1926#define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK)
1927#define CAN_ILS_MRAFL_MASK (0x20000U)
1928#define CAN_ILS_MRAFL_SHIFT (17U)
1929/*! MRAFL - Message RAM access failure interrupt line.
1930 */
1931#define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK)
1932#define CAN_ILS_TOOL_MASK (0x40000U)
1933#define CAN_ILS_TOOL_SHIFT (18U)
1934/*! TOOL - Timeout occurred interrupt line.
1935 */
1936#define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK)
1937#define CAN_ILS_DRXL_MASK (0x80000U)
1938#define CAN_ILS_DRXL_SHIFT (19U)
1939/*! DRXL - Message stored in dedicated Rx buffer interrupt line.
1940 */
1941#define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK)
1942#define CAN_ILS_BECL_MASK (0x100000U)
1943#define CAN_ILS_BECL_SHIFT (20U)
1944/*! BECL - Bit error corrected interrupt line.
1945 */
1946#define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK)
1947#define CAN_ILS_BEUL_MASK (0x200000U)
1948#define CAN_ILS_BEUL_SHIFT (21U)
1949/*! BEUL - Bit error uncorrected interrupt line.
1950 */
1951#define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK)
1952#define CAN_ILS_ELOL_MASK (0x400000U)
1953#define CAN_ILS_ELOL_SHIFT (22U)
1954/*! ELOL - Error logging overflow interrupt line.
1955 */
1956#define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK)
1957#define CAN_ILS_EPL_MASK (0x800000U)
1958#define CAN_ILS_EPL_SHIFT (23U)
1959/*! EPL - Error passive interrupt line.
1960 */
1961#define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK)
1962#define CAN_ILS_EWL_MASK (0x1000000U)
1963#define CAN_ILS_EWL_SHIFT (24U)
1964/*! EWL - Warning status interrupt line.
1965 */
1966#define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK)
1967#define CAN_ILS_BOL_MASK (0x2000000U)
1968#define CAN_ILS_BOL_SHIFT (25U)
1969/*! BOL - Bus_Off Status interrupt line.
1970 */
1971#define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK)
1972#define CAN_ILS_WDIL_MASK (0x4000000U)
1973#define CAN_ILS_WDIL_SHIFT (26U)
1974/*! WDIL - Watchdog interrupt line.
1975 */
1976#define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK)
1977#define CAN_ILS_PEAL_MASK (0x8000000U)
1978#define CAN_ILS_PEAL_SHIFT (27U)
1979/*! PEAL - Protocol error in arbitration phase interrupt line.
1980 */
1981#define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK)
1982#define CAN_ILS_PEDL_MASK (0x10000000U)
1983#define CAN_ILS_PEDL_SHIFT (28U)
1984/*! PEDL - Protocol error in data phase interrupt line.
1985 */
1986#define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK)
1987#define CAN_ILS_ARAL_MASK (0x20000000U)
1988#define CAN_ILS_ARAL_SHIFT (29U)
1989/*! ARAL - Access to reserved address interrupt line.
1990 */
1991#define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK)
1992/*! @} */
1993
1994/*! @name ILE - Interrupt Line Enable */
1995/*! @{ */
1996#define CAN_ILE_EINT0_MASK (0x1U)
1997#define CAN_ILE_EINT0_SHIFT (0U)
1998/*! EINT0 - Enable interrupt line 0.
1999 */
2000#define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK)
2001#define CAN_ILE_EINT1_MASK (0x2U)
2002#define CAN_ILE_EINT1_SHIFT (1U)
2003/*! EINT1 - Enable interrupt line 1.
2004 */
2005#define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK)
2006/*! @} */
2007
2008/*! @name GFC - Global Filter Configuration */
2009/*! @{ */
2010#define CAN_GFC_RRFE_MASK (0x1U)
2011#define CAN_GFC_RRFE_SHIFT (0U)
2012/*! RRFE - Reject remote frames extended.
2013 */
2014#define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK)
2015#define CAN_GFC_RRFS_MASK (0x2U)
2016#define CAN_GFC_RRFS_SHIFT (1U)
2017/*! RRFS - Reject remote frames standard.
2018 */
2019#define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK)
2020#define CAN_GFC_ANFE_MASK (0xCU)
2021#define CAN_GFC_ANFE_SHIFT (2U)
2022/*! ANFE - Accept non-matching frames extended.
2023 */
2024#define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK)
2025#define CAN_GFC_ANFS_MASK (0x30U)
2026#define CAN_GFC_ANFS_SHIFT (4U)
2027/*! ANFS - Accept non-matching frames standard.
2028 */
2029#define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK)
2030/*! @} */
2031
2032/*! @name SIDFC - Standard ID Filter Configuration */
2033/*! @{ */
2034#define CAN_SIDFC_FLSSA_MASK (0xFFFCU)
2035#define CAN_SIDFC_FLSSA_SHIFT (2U)
2036/*! FLSSA - Filter list standard start address.
2037 */
2038#define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK)
2039#define CAN_SIDFC_LSS_MASK (0xFF0000U)
2040#define CAN_SIDFC_LSS_SHIFT (16U)
2041/*! LSS - List size standard 0 = No standard message ID filter.
2042 */
2043#define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK)
2044/*! @} */
2045
2046/*! @name XIDFC - Extended ID Filter Configuration */
2047/*! @{ */
2048#define CAN_XIDFC_FLESA_MASK (0xFFFCU)
2049#define CAN_XIDFC_FLESA_SHIFT (2U)
2050/*! FLESA - Filter list extended start address.
2051 */
2052#define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK)
2053#define CAN_XIDFC_LSE_MASK (0xFF0000U)
2054#define CAN_XIDFC_LSE_SHIFT (16U)
2055/*! LSE - List size extended 0 = No extended message ID filter.
2056 */
2057#define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK)
2058/*! @} */
2059
2060/*! @name XIDAM - Extended ID AND Mask */
2061/*! @{ */
2062#define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU)
2063#define CAN_XIDAM_EIDM_SHIFT (0U)
2064/*! EIDM - Extended ID mask.
2065 */
2066#define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK)
2067/*! @} */
2068
2069/*! @name HPMS - High Priority Message Status */
2070/*! @{ */
2071#define CAN_HPMS_BIDX_MASK (0x3FU)
2072#define CAN_HPMS_BIDX_SHIFT (0U)
2073/*! BIDX - Buffer index.
2074 */
2075#define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK)
2076#define CAN_HPMS_MSI_MASK (0xC0U)
2077#define CAN_HPMS_MSI_SHIFT (6U)
2078/*! MSI - Message storage indicator.
2079 */
2080#define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK)
2081#define CAN_HPMS_FIDX_MASK (0x7F00U)
2082#define CAN_HPMS_FIDX_SHIFT (8U)
2083/*! FIDX - Filter index.
2084 */
2085#define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK)
2086#define CAN_HPMS_FLST_MASK (0x8000U)
2087#define CAN_HPMS_FLST_SHIFT (15U)
2088/*! FLST - Filter list.
2089 */
2090#define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK)
2091/*! @} */
2092
2093/*! @name NDAT1 - New Data 1 */
2094/*! @{ */
2095#define CAN_NDAT1_ND_MASK (0xFFFFFFFFU)
2096#define CAN_NDAT1_ND_SHIFT (0U)
2097/*! ND - New Data.
2098 */
2099#define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK)
2100/*! @} */
2101
2102/*! @name NDAT2 - New Data 2 */
2103/*! @{ */
2104#define CAN_NDAT2_ND_MASK (0xFFFFFFFFU)
2105#define CAN_NDAT2_ND_SHIFT (0U)
2106/*! ND - New Data.
2107 */
2108#define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK)
2109/*! @} */
2110
2111/*! @name RXF0C - Rx FIFO 0 Configuration */
2112/*! @{ */
2113#define CAN_RXF0C_F0SA_MASK (0xFFFCU)
2114#define CAN_RXF0C_F0SA_SHIFT (2U)
2115/*! F0SA - Rx FIFO 0 start address.
2116 */
2117#define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK)
2118#define CAN_RXF0C_F0S_MASK (0x7F0000U)
2119#define CAN_RXF0C_F0S_SHIFT (16U)
2120/*! F0S - Rx FIFO 0 size.
2121 */
2122#define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK)
2123#define CAN_RXF0C_F0WM_MASK (0x7F000000U)
2124#define CAN_RXF0C_F0WM_SHIFT (24U)
2125/*! F0WM - Rx FIFO 0 watermark 0 = Watermark interrupt disabled.
2126 */
2127#define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK)
2128#define CAN_RXF0C_F0OM_MASK (0x80000000U)
2129#define CAN_RXF0C_F0OM_SHIFT (31U)
2130/*! F0OM - FIFO 0 operation mode.
2131 */
2132#define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK)
2133/*! @} */
2134
2135/*! @name RXF0S - Rx FIFO 0 Status */
2136/*! @{ */
2137#define CAN_RXF0S_F0FL_MASK (0x7FU)
2138#define CAN_RXF0S_F0FL_SHIFT (0U)
2139/*! F0FL - Rx FIFO 0 fill level.
2140 */
2141#define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK)
2142#define CAN_RXF0S_F0GI_MASK (0x3F00U)
2143#define CAN_RXF0S_F0GI_SHIFT (8U)
2144/*! F0GI - Rx FIFO 0 get index.
2145 */
2146#define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK)
2147#define CAN_RXF0S_F0PI_MASK (0x3F0000U)
2148#define CAN_RXF0S_F0PI_SHIFT (16U)
2149/*! F0PI - Rx FIFO 0 put index.
2150 */
2151#define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK)
2152#define CAN_RXF0S_F0F_MASK (0x1000000U)
2153#define CAN_RXF0S_F0F_SHIFT (24U)
2154/*! F0F - Rx FIFO 0 full.
2155 */
2156#define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK)
2157#define CAN_RXF0S_RF0L_MASK (0x2000000U)
2158#define CAN_RXF0S_RF0L_SHIFT (25U)
2159/*! RF0L - Rx FIFO 0 message lost.
2160 */
2161#define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK)
2162/*! @} */
2163
2164/*! @name RXF0A - Rx FIFO 0 Acknowledge */
2165/*! @{ */
2166#define CAN_RXF0A_F0AI_MASK (0x3FU)
2167#define CAN_RXF0A_F0AI_SHIFT (0U)
2168/*! F0AI - Rx FIFO 0 acknowledge index.
2169 */
2170#define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK)
2171/*! @} */
2172
2173/*! @name RXBC - Rx Buffer Configuration */
2174/*! @{ */
2175#define CAN_RXBC_RBSA_MASK (0xFFFCU)
2176#define CAN_RXBC_RBSA_SHIFT (2U)
2177/*! RBSA - Rx buffer start address.
2178 */
2179#define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK)
2180/*! @} */
2181
2182/*! @name RXF1C - Rx FIFO 1 Configuration */
2183/*! @{ */
2184#define CAN_RXF1C_F1SA_MASK (0xFFFCU)
2185#define CAN_RXF1C_F1SA_SHIFT (2U)
2186/*! F1SA - Rx FIFO 1 start address.
2187 */
2188#define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK)
2189#define CAN_RXF1C_F1S_MASK (0x7F0000U)
2190#define CAN_RXF1C_F1S_SHIFT (16U)
2191/*! F1S - Rx FIFO 1 size 0 = No Rx FIFO 1.
2192 */
2193#define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK)
2194#define CAN_RXF1C_F1WM_MASK (0x7F000000U)
2195#define CAN_RXF1C_F1WM_SHIFT (24U)
2196/*! F1WM - Rx FIFO 1 watermark 0 = Watermark interrupt disabled.
2197 */
2198#define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK)
2199#define CAN_RXF1C_F1OM_MASK (0x80000000U)
2200#define CAN_RXF1C_F1OM_SHIFT (31U)
2201/*! F1OM - FIFO 1 operation mode.
2202 */
2203#define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK)
2204/*! @} */
2205
2206/*! @name RXF1S - Rx FIFO 1 Status */
2207/*! @{ */
2208#define CAN_RXF1S_F1FL_MASK (0x7FU)
2209#define CAN_RXF1S_F1FL_SHIFT (0U)
2210/*! F1FL - Rx FIFO 1 fill level.
2211 */
2212#define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK)
2213#define CAN_RXF1S_F1GI_MASK (0x3F00U)
2214#define CAN_RXF1S_F1GI_SHIFT (8U)
2215/*! F1GI - Rx FIFO 1 get index.
2216 */
2217#define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK)
2218#define CAN_RXF1S_F1PI_MASK (0x3F0000U)
2219#define CAN_RXF1S_F1PI_SHIFT (16U)
2220/*! F1PI - Rx FIFO 1 put index.
2221 */
2222#define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK)
2223#define CAN_RXF1S_F1F_MASK (0x1000000U)
2224#define CAN_RXF1S_F1F_SHIFT (24U)
2225/*! F1F - Rx FIFO 1 full.
2226 */
2227#define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK)
2228#define CAN_RXF1S_RF1L_MASK (0x2000000U)
2229#define CAN_RXF1S_RF1L_SHIFT (25U)
2230/*! RF1L - Rx FIFO 1 message lost.
2231 */
2232#define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK)
2233/*! @} */
2234
2235/*! @name RXF1A - Rx FIFO 1 Acknowledge */
2236/*! @{ */
2237#define CAN_RXF1A_F1AI_MASK (0x3FU)
2238#define CAN_RXF1A_F1AI_SHIFT (0U)
2239/*! F1AI - Rx FIFO 1 acknowledge index.
2240 */
2241#define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK)
2242/*! @} */
2243
2244/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */
2245/*! @{ */
2246#define CAN_RXESC_F0DS_MASK (0x7U)
2247#define CAN_RXESC_F0DS_SHIFT (0U)
2248/*! F0DS - Rx FIFO 0 data field size.
2249 */
2250#define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK)
2251#define CAN_RXESC_F1DS_MASK (0x70U)
2252#define CAN_RXESC_F1DS_SHIFT (4U)
2253/*! F1DS - Rx FIFO 1 data field size.
2254 */
2255#define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK)
2256#define CAN_RXESC_RBDS_MASK (0x700U)
2257#define CAN_RXESC_RBDS_SHIFT (8U)
2258/*! RBDS - .
2259 */
2260#define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK)
2261/*! @} */
2262
2263/*! @name TXBC - Tx Buffer Configuration */
2264/*! @{ */
2265#define CAN_TXBC_TBSA_MASK (0xFFFCU)
2266#define CAN_TXBC_TBSA_SHIFT (2U)
2267/*! TBSA - Tx buffers start address.
2268 */
2269#define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK)
2270#define CAN_TXBC_NDTB_MASK (0x3F0000U)
2271#define CAN_TXBC_NDTB_SHIFT (16U)
2272/*! NDTB - Number of dedicated transmit buffers 0 = No dedicated Tx buffers.
2273 */
2274#define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK)
2275#define CAN_TXBC_TFQS_MASK (0x3F000000U)
2276#define CAN_TXBC_TFQS_SHIFT (24U)
2277/*! TFQS - Transmit FIFO/queue size 0 = No tx FIFO/Queue.
2278 */
2279#define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK)
2280#define CAN_TXBC_TFQM_MASK (0x40000000U)
2281#define CAN_TXBC_TFQM_SHIFT (30U)
2282/*! TFQM - Tx FIFO/queue mode.
2283 */
2284#define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK)
2285/*! @} */
2286
2287/*! @name TXFQS - Tx FIFO/Queue Status */
2288/*! @{ */
2289#define CAN_TXFQS_TFGI_MASK (0x1F00U)
2290#define CAN_TXFQS_TFGI_SHIFT (8U)
2291/*! TFGI - Tx FIFO get index.
2292 */
2293#define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK)
2294#define CAN_TXFQS_TFQPI_MASK (0x1F0000U)
2295#define CAN_TXFQS_TFQPI_SHIFT (16U)
2296/*! TFQPI - Tx FIFO/queue put index.
2297 */
2298#define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK)
2299#define CAN_TXFQS_TFQF_MASK (0x200000U)
2300#define CAN_TXFQS_TFQF_SHIFT (21U)
2301/*! TFQF - Tx FIFO/queue full.
2302 */
2303#define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK)
2304/*! @} */
2305
2306/*! @name TXESC - Tx Buffer Element Size Configuration */
2307/*! @{ */
2308#define CAN_TXESC_TBDS_MASK (0x7U)
2309#define CAN_TXESC_TBDS_SHIFT (0U)
2310/*! TBDS - Tx buffer data field size.
2311 */
2312#define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK)
2313/*! @} */
2314
2315/*! @name TXBRP - Tx Buffer Request Pending */
2316/*! @{ */
2317#define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU)
2318#define CAN_TXBRP_TRP_SHIFT (0U)
2319/*! TRP - Transmission request pending.
2320 */
2321#define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK)
2322/*! @} */
2323
2324/*! @name TXBAR - Tx Buffer Add Request */
2325/*! @{ */
2326#define CAN_TXBAR_AR_MASK (0xFFFFFFFFU)
2327#define CAN_TXBAR_AR_SHIFT (0U)
2328/*! AR - Add request.
2329 */
2330#define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK)
2331/*! @} */
2332
2333/*! @name TXBCR - Tx Buffer Cancellation Request */
2334/*! @{ */
2335#define CAN_TXBCR_CR_MASK (0xFFFFFFFFU)
2336#define CAN_TXBCR_CR_SHIFT (0U)
2337/*! CR - Cancellation request.
2338 */
2339#define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK)
2340/*! @} */
2341
2342/*! @name TXBTO - Tx Buffer Transmission Occurred */
2343/*! @{ */
2344#define CAN_TXBTO_TO_MASK (0xFFFFFFFFU)
2345#define CAN_TXBTO_TO_SHIFT (0U)
2346/*! TO - Transmission occurred.
2347 */
2348#define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK)
2349/*! @} */
2350
2351/*! @name TXBCF - Tx Buffer Cancellation Finished */
2352/*! @{ */
2353#define CAN_TXBCF_TO_MASK (0xFFFFFFFFU)
2354#define CAN_TXBCF_TO_SHIFT (0U)
2355/*! TO - Cancellation finished.
2356 */
2357#define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK)
2358/*! @} */
2359
2360/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */
2361/*! @{ */
2362#define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU)
2363#define CAN_TXBTIE_TIE_SHIFT (0U)
2364/*! TIE - Transmission interrupt enable.
2365 */
2366#define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK)
2367/*! @} */
2368
2369/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */
2370/*! @{ */
2371#define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU)
2372#define CAN_TXBCIE_CFIE_SHIFT (0U)
2373/*! CFIE - Cancellation finished interrupt enable.
2374 */
2375#define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK)
2376/*! @} */
2377
2378/*! @name TXEFC - Tx Event FIFO Configuration */
2379/*! @{ */
2380#define CAN_TXEFC_EFSA_MASK (0xFFFCU)
2381#define CAN_TXEFC_EFSA_SHIFT (2U)
2382/*! EFSA - Event FIFO start address.
2383 */
2384#define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK)
2385#define CAN_TXEFC_EFS_MASK (0x3F0000U)
2386#define CAN_TXEFC_EFS_SHIFT (16U)
2387/*! EFS - Event FIFO size 0 = Tx event FIFO disabled.
2388 */
2389#define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK)
2390#define CAN_TXEFC_EFWM_MASK (0x3F000000U)
2391#define CAN_TXEFC_EFWM_SHIFT (24U)
2392/*! EFWM - Event FIFO watermark 0 = Watermark interrupt disabled.
2393 */
2394#define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK)
2395/*! @} */
2396
2397/*! @name TXEFS - Tx Event FIFO Status */
2398/*! @{ */
2399#define CAN_TXEFS_EFFL_MASK (0x3FU)
2400#define CAN_TXEFS_EFFL_SHIFT (0U)
2401/*! EFFL - Event FIFO fill level.
2402 */
2403#define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK)
2404#define CAN_TXEFS_EFGI_MASK (0x1F00U)
2405#define CAN_TXEFS_EFGI_SHIFT (8U)
2406/*! EFGI - Event FIFO get index.
2407 */
2408#define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK)
2409#define CAN_TXEFS_EFPI_MASK (0x3F0000U)
2410#define CAN_TXEFS_EFPI_SHIFT (16U)
2411/*! EFPI - Event FIFO put index.
2412 */
2413#define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK)
2414#define CAN_TXEFS_EFF_MASK (0x1000000U)
2415#define CAN_TXEFS_EFF_SHIFT (24U)
2416/*! EFF - Event FIFO full.
2417 */
2418#define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK)
2419#define CAN_TXEFS_TEFL_MASK (0x2000000U)
2420#define CAN_TXEFS_TEFL_SHIFT (25U)
2421/*! TEFL - Tx event FIFO element lost.
2422 */
2423#define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK)
2424/*! @} */
2425
2426/*! @name TXEFA - Tx Event FIFO Acknowledge */
2427/*! @{ */
2428#define CAN_TXEFA_EFAI_MASK (0x1FU)
2429#define CAN_TXEFA_EFAI_SHIFT (0U)
2430/*! EFAI - Event FIFO acknowledge index.
2431 */
2432#define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK)
2433/*! @} */
2434
2435/*! @name MRBA - CAN Message RAM Base Address */
2436/*! @{ */
2437#define CAN_MRBA_BA_MASK (0xFFFF0000U)
2438#define CAN_MRBA_BA_SHIFT (16U)
2439/*! BA - Base address for the message RAM in the chip memory map.
2440 */
2441#define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK)
2442/*! @} */
2443
2444/*! @name ETSCC - External Timestamp Counter Configuration */
2445/*! @{ */
2446#define CAN_ETSCC_ETCP_MASK (0x7FFU)
2447#define CAN_ETSCC_ETCP_SHIFT (0U)
2448/*! ETCP - External timestamp prescaler value.
2449 */
2450#define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK)
2451#define CAN_ETSCC_ETCE_MASK (0x80000000U)
2452#define CAN_ETSCC_ETCE_SHIFT (31U)
2453/*! ETCE - External timestamp counter enable.
2454 */
2455#define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK)
2456/*! @} */
2457
2458/*! @name ETSCV - External Timestamp Counter Value */
2459/*! @{ */
2460#define CAN_ETSCV_ETSC_MASK (0xFFFFU)
2461#define CAN_ETSCV_ETSC_SHIFT (0U)
2462/*! ETSC - External timestamp counter.
2463 */
2464#define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK)
2465/*! @} */
2466
2467
2468/*!
2469 * @}
2470 */ /* end of group CAN_Register_Masks */
2471
2472
2473/* CAN - Peripheral instance base addresses */
2474/** Peripheral CAN0 base address */
2475#define CAN0_BASE (0x4009D000u)
2476/** Peripheral CAN0 base pointer */
2477#define CAN0 ((CAN_Type *)CAN0_BASE)
2478/** Peripheral CAN1 base address */
2479#define CAN1_BASE (0x4009E000u)
2480/** Peripheral CAN1 base pointer */
2481#define CAN1 ((CAN_Type *)CAN1_BASE)
2482/** Array initializer of CAN peripheral base addresses */
2483#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
2484/** Array initializer of CAN peripheral base pointers */
2485#define CAN_BASE_PTRS { CAN0, CAN1 }
2486/** Interrupt vectors for the CAN peripheral type */
2487#define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } }
2488
2489/*!
2490 * @}
2491 */ /* end of group CAN_Peripheral_Access_Layer */
2492
2493
2494/* ----------------------------------------------------------------------------
2495 -- CRC Peripheral Access Layer
2496 ---------------------------------------------------------------------------- */
2497
2498/*!
2499 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
2500 * @{
2501 */
2502
2503/** CRC - Register Layout Typedef */
2504typedef struct {
2505 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
2506 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
2507 union { /* offset: 0x8 */
2508 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
2509 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
2510 };
2511} CRC_Type;
2512
2513/* ----------------------------------------------------------------------------
2514 -- CRC Register Masks
2515 ---------------------------------------------------------------------------- */
2516
2517/*!
2518 * @addtogroup CRC_Register_Masks CRC Register Masks
2519 * @{
2520 */
2521
2522/*! @name MODE - CRC mode register */
2523/*! @{ */
2524#define CRC_MODE_CRC_POLY_MASK (0x3U)
2525#define CRC_MODE_CRC_POLY_SHIFT (0U)
2526/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
2527 */
2528#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
2529#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
2530#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
2531/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
2532 */
2533#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
2534#define CRC_MODE_CMPL_WR_MASK (0x8U)
2535#define CRC_MODE_CMPL_WR_SHIFT (3U)
2536/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
2537 */
2538#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
2539#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
2540#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
2541/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
2542 */
2543#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
2544#define CRC_MODE_CMPL_SUM_MASK (0x20U)
2545#define CRC_MODE_CMPL_SUM_SHIFT (5U)
2546/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
2547 */
2548#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
2549/*! @} */
2550
2551/*! @name SEED - CRC seed register */
2552/*! @{ */
2553#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
2554#define CRC_SEED_CRC_SEED_SHIFT (0U)
2555/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
2556 * selected bit order and 1's complement pre-processes. A write access to this register will
2557 * overrule the CRC calculation in progresses.
2558 */
2559#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
2560/*! @} */
2561
2562/*! @name SUM - CRC checksum register */
2563/*! @{ */
2564#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
2565#define CRC_SUM_CRC_SUM_SHIFT (0U)
2566/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
2567 */
2568#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
2569/*! @} */
2570
2571/*! @name WR_DATA - CRC data register */
2572/*! @{ */
2573#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
2574#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
2575/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
2576 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
2577 * accept back-to-back transactions.
2578 */
2579#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
2580/*! @} */
2581
2582
2583/*!
2584 * @}
2585 */ /* end of group CRC_Register_Masks */
2586
2587
2588/* CRC - Peripheral instance base addresses */
2589/** Peripheral CRC_ENGINE base address */
2590#define CRC_ENGINE_BASE (0x40095000u)
2591/** Peripheral CRC_ENGINE base pointer */
2592#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
2593/** Array initializer of CRC peripheral base addresses */
2594#define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
2595/** Array initializer of CRC peripheral base pointers */
2596#define CRC_BASE_PTRS { CRC_ENGINE }
2597
2598/*!
2599 * @}
2600 */ /* end of group CRC_Peripheral_Access_Layer */
2601
2602
2603/* ----------------------------------------------------------------------------
2604 -- CTIMER Peripheral Access Layer
2605 ---------------------------------------------------------------------------- */
2606
2607/*!
2608 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
2609 * @{
2610 */
2611
2612/** CTIMER - Register Layout Typedef */
2613typedef struct {
2614 __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
2615 __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
2616 __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */
2617 __IO uint32_t PR; /**< Prescale Register, offset: 0xC */
2618 __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */
2619 __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */
2620 __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
2621 __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
2622 __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
2623 __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
2624 uint8_t RESERVED_0[48];
2625 __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
2626 __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
2627 __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
2628} CTIMER_Type;
2629
2630/* ----------------------------------------------------------------------------
2631 -- CTIMER Register Masks
2632 ---------------------------------------------------------------------------- */
2633
2634/*!
2635 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
2636 * @{
2637 */
2638
2639/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
2640/*! @{ */
2641#define CTIMER_IR_MR0INT_MASK (0x1U)
2642#define CTIMER_IR_MR0INT_SHIFT (0U)
2643/*! MR0INT - Interrupt flag for match channel 0.
2644 */
2645#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
2646#define CTIMER_IR_MR1INT_MASK (0x2U)
2647#define CTIMER_IR_MR1INT_SHIFT (1U)
2648/*! MR1INT - Interrupt flag for match channel 1.
2649 */
2650#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
2651#define CTIMER_IR_MR2INT_MASK (0x4U)
2652#define CTIMER_IR_MR2INT_SHIFT (2U)
2653/*! MR2INT - Interrupt flag for match channel 2.
2654 */
2655#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
2656#define CTIMER_IR_MR3INT_MASK (0x8U)
2657#define CTIMER_IR_MR3INT_SHIFT (3U)
2658/*! MR3INT - Interrupt flag for match channel 3.
2659 */
2660#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
2661#define CTIMER_IR_CR0INT_MASK (0x10U)
2662#define CTIMER_IR_CR0INT_SHIFT (4U)
2663/*! CR0INT - Interrupt flag for capture channel 0 event.
2664 */
2665#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
2666#define CTIMER_IR_CR1INT_MASK (0x20U)
2667#define CTIMER_IR_CR1INT_SHIFT (5U)
2668/*! CR1INT - Interrupt flag for capture channel 1 event.
2669 */
2670#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
2671#define CTIMER_IR_CR2INT_MASK (0x40U)
2672#define CTIMER_IR_CR2INT_SHIFT (6U)
2673/*! CR2INT - Interrupt flag for capture channel 2 event.
2674 */
2675#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
2676#define CTIMER_IR_CR3INT_MASK (0x80U)
2677#define CTIMER_IR_CR3INT_SHIFT (7U)
2678/*! CR3INT - Interrupt flag for capture channel 3 event.
2679 */
2680#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
2681/*! @} */
2682
2683/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
2684/*! @{ */
2685#define CTIMER_TCR_CEN_MASK (0x1U)
2686#define CTIMER_TCR_CEN_SHIFT (0U)
2687/*! CEN - Counter enable.
2688 * 0b0..Disabled.The counters are disabled.
2689 * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
2690 */
2691#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
2692#define CTIMER_TCR_CRST_MASK (0x2U)
2693#define CTIMER_TCR_CRST_SHIFT (1U)
2694/*! CRST - Counter reset.
2695 * 0b0..Disabled. Do nothing.
2696 * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
2697 * the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
2698 */
2699#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
2700/*! @} */
2701
2702/*! @name TC - Timer Counter */
2703/*! @{ */
2704#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
2705#define CTIMER_TC_TCVAL_SHIFT (0U)
2706/*! TCVAL - Timer counter value.
2707 */
2708#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
2709/*! @} */
2710
2711/*! @name PR - Prescale Register */
2712/*! @{ */
2713#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
2714#define CTIMER_PR_PRVAL_SHIFT (0U)
2715/*! PRVAL - Prescale counter value.
2716 */
2717#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
2718/*! @} */
2719
2720/*! @name PC - Prescale Counter */
2721/*! @{ */
2722#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
2723#define CTIMER_PC_PCVAL_SHIFT (0U)
2724/*! PCVAL - Prescale counter value.
2725 */
2726#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
2727/*! @} */
2728
2729/*! @name MCR - Match Control Register */
2730/*! @{ */
2731#define CTIMER_MCR_MR0I_MASK (0x1U)
2732#define CTIMER_MCR_MR0I_SHIFT (0U)
2733/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
2734 */
2735#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
2736#define CTIMER_MCR_MR0R_MASK (0x2U)
2737#define CTIMER_MCR_MR0R_SHIFT (1U)
2738/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it.
2739 */
2740#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
2741#define CTIMER_MCR_MR0S_MASK (0x4U)
2742#define CTIMER_MCR_MR0S_SHIFT (2U)
2743/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
2744 */
2745#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
2746#define CTIMER_MCR_MR1I_MASK (0x8U)
2747#define CTIMER_MCR_MR1I_SHIFT (3U)
2748/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
2749 */
2750#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
2751#define CTIMER_MCR_MR1R_MASK (0x10U)
2752#define CTIMER_MCR_MR1R_SHIFT (4U)
2753/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it.
2754 */
2755#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
2756#define CTIMER_MCR_MR1S_MASK (0x20U)
2757#define CTIMER_MCR_MR1S_SHIFT (5U)
2758/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
2759 */
2760#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
2761#define CTIMER_MCR_MR2I_MASK (0x40U)
2762#define CTIMER_MCR_MR2I_SHIFT (6U)
2763/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
2764 */
2765#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
2766#define CTIMER_MCR_MR2R_MASK (0x80U)
2767#define CTIMER_MCR_MR2R_SHIFT (7U)
2768/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it.
2769 */
2770#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
2771#define CTIMER_MCR_MR2S_MASK (0x100U)
2772#define CTIMER_MCR_MR2S_SHIFT (8U)
2773/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
2774 */
2775#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
2776#define CTIMER_MCR_MR3I_MASK (0x200U)
2777#define CTIMER_MCR_MR3I_SHIFT (9U)
2778/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
2779 */
2780#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
2781#define CTIMER_MCR_MR3R_MASK (0x400U)
2782#define CTIMER_MCR_MR3R_SHIFT (10U)
2783/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it.
2784 */
2785#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
2786#define CTIMER_MCR_MR3S_MASK (0x800U)
2787#define CTIMER_MCR_MR3S_SHIFT (11U)
2788/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
2789 */
2790#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
2791#define CTIMER_MCR_MR0RL_MASK (0x1000000U)
2792#define CTIMER_MCR_MR0RL_SHIFT (24U)
2793/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
2794 * (either via a match event or a write to bit 1 of the TCR).
2795 */
2796#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
2797#define CTIMER_MCR_MR1RL_MASK (0x2000000U)
2798#define CTIMER_MCR_MR1RL_SHIFT (25U)
2799/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
2800 * (either via a match event or a write to bit 1 of the TCR).
2801 */
2802#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
2803#define CTIMER_MCR_MR2RL_MASK (0x4000000U)
2804#define CTIMER_MCR_MR2RL_SHIFT (26U)
2805/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
2806 * (either via a match event or a write to bit 1 of the TCR).
2807 */
2808#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
2809#define CTIMER_MCR_MR3RL_MASK (0x8000000U)
2810#define CTIMER_MCR_MR3RL_SHIFT (27U)
2811/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
2812 * (either via a match event or a write to bit 1 of the TCR).
2813 */
2814#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
2815/*! @} */
2816
2817/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
2818/*! @{ */
2819#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
2820#define CTIMER_MR_MATCH_SHIFT (0U)
2821/*! MATCH - Timer counter match value.
2822 */
2823#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
2824/*! @} */
2825
2826/* The count of CTIMER_MR */
2827#define CTIMER_MR_COUNT (4U)
2828
2829/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
2830/*! @{ */
2831#define CTIMER_CCR_CAP0RE_MASK (0x1U)
2832#define CTIMER_CCR_CAP0RE_SHIFT (0U)
2833/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
2834 * the contents of TC. 0 = disabled. 1 = enabled.
2835 */
2836#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
2837#define CTIMER_CCR_CAP0FE_MASK (0x2U)
2838#define CTIMER_CCR_CAP0FE_SHIFT (1U)
2839/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
2840 * the contents of TC. 0 = disabled. 1 = enabled.
2841 */
2842#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
2843#define CTIMER_CCR_CAP0I_MASK (0x4U)
2844#define CTIMER_CCR_CAP0I_SHIFT (2U)
2845/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
2846 */
2847#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
2848#define CTIMER_CCR_CAP1RE_MASK (0x8U)
2849#define CTIMER_CCR_CAP1RE_SHIFT (3U)
2850/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
2851 * the contents of TC. 0 = disabled. 1 = enabled.
2852 */
2853#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
2854#define CTIMER_CCR_CAP1FE_MASK (0x10U)
2855#define CTIMER_CCR_CAP1FE_SHIFT (4U)
2856/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
2857 * the contents of TC. 0 = disabled. 1 = enabled.
2858 */
2859#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
2860#define CTIMER_CCR_CAP1I_MASK (0x20U)
2861#define CTIMER_CCR_CAP1I_SHIFT (5U)
2862/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
2863 */
2864#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
2865#define CTIMER_CCR_CAP2RE_MASK (0x40U)
2866#define CTIMER_CCR_CAP2RE_SHIFT (6U)
2867/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
2868 * the contents of TC. 0 = disabled. 1 = enabled.
2869 */
2870#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
2871#define CTIMER_CCR_CAP2FE_MASK (0x80U)
2872#define CTIMER_CCR_CAP2FE_SHIFT (7U)
2873/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
2874 * the contents of TC. 0 = disabled. 1 = enabled.
2875 */
2876#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
2877#define CTIMER_CCR_CAP2I_MASK (0x100U)
2878#define CTIMER_CCR_CAP2I_SHIFT (8U)
2879/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
2880 */
2881#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
2882#define CTIMER_CCR_CAP3RE_MASK (0x200U)
2883#define CTIMER_CCR_CAP3RE_SHIFT (9U)
2884/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with
2885 * the contents of TC. 0 = disabled. 1 = enabled.
2886 */
2887#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
2888#define CTIMER_CCR_CAP3FE_MASK (0x400U)
2889#define CTIMER_CCR_CAP3FE_SHIFT (10U)
2890/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with
2891 * the contents of TC. 0 = disabled. 1 = enabled.
2892 */
2893#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
2894#define CTIMER_CCR_CAP3I_MASK (0x800U)
2895#define CTIMER_CCR_CAP3I_SHIFT (11U)
2896/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
2897 */
2898#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
2899/*! @} */
2900
2901/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
2902/*! @{ */
2903#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
2904#define CTIMER_CR_CAP_SHIFT (0U)
2905/*! CAP - Timer counter capture value.
2906 */
2907#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
2908/*! @} */
2909
2910/* The count of CTIMER_CR */
2911#define CTIMER_CR_COUNT (4U)
2912
2913/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
2914/*! @{ */
2915#define CTIMER_EMR_EM0_MASK (0x1U)
2916#define CTIMER_EMR_EM0_SHIFT (0U)
2917/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
2918 * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
2919 * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
2920 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2921 */
2922#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
2923#define CTIMER_EMR_EM1_MASK (0x2U)
2924#define CTIMER_EMR_EM1_SHIFT (1U)
2925/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
2926 * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
2927 * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
2928 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2929 */
2930#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
2931#define CTIMER_EMR_EM2_MASK (0x4U)
2932#define CTIMER_EMR_EM2_SHIFT (2U)
2933/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
2934 * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
2935 * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
2936 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2937 */
2938#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
2939#define CTIMER_EMR_EM3_MASK (0x8U)
2940#define CTIMER_EMR_EM3_SHIFT (3U)
2941/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
2942 * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
2943 * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
2944 * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2945 */
2946#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
2947#define CTIMER_EMR_EMC0_MASK (0x30U)
2948#define CTIMER_EMR_EMC0_SHIFT (4U)
2949/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
2950 * 0b00..Do Nothing.
2951 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
2952 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
2953 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
2954 */
2955#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
2956#define CTIMER_EMR_EMC1_MASK (0xC0U)
2957#define CTIMER_EMR_EMC1_SHIFT (6U)
2958/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
2959 * 0b00..Do Nothing.
2960 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
2961 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
2962 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
2963 */
2964#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
2965#define CTIMER_EMR_EMC2_MASK (0x300U)
2966#define CTIMER_EMR_EMC2_SHIFT (8U)
2967/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
2968 * 0b00..Do Nothing.
2969 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
2970 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
2971 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
2972 */
2973#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
2974#define CTIMER_EMR_EMC3_MASK (0xC00U)
2975#define CTIMER_EMR_EMC3_SHIFT (10U)
2976/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
2977 * 0b00..Do Nothing.
2978 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
2979 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
2980 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
2981 */
2982#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
2983/*! @} */
2984
2985/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
2986/*! @{ */
2987#define CTIMER_CTCR_CTMODE_MASK (0x3U)
2988#define CTIMER_CTCR_CTMODE_SHIFT (0U)
2989/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
2990 * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
2991 * is incremented when the Prescale Counter matches the Prescale Register.
2992 * 0b00..Timer Mode. Incremented every rising APB bus clock edge.
2993 * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
2994 * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
2995 * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
2996 */
2997#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
2998#define CTIMER_CTCR_CINSEL_MASK (0xCU)
2999#define CTIMER_CTCR_CINSEL_SHIFT (2U)
3000/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
3001 * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
3002 * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
3003 * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
3004 * same timer.
3005 * 0b00..Channel 0. CAPn.0 for CTIMERn
3006 * 0b01..Channel 1. CAPn.1 for CTIMERn
3007 * 0b10..Channel 2. CAPn.2 for CTIMERn
3008 * 0b11..Channel 3. CAPn.3 for CTIMERn
3009 */
3010#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
3011#define CTIMER_CTCR_ENCC_MASK (0x10U)
3012#define CTIMER_CTCR_ENCC_SHIFT (4U)
3013/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
3014 * capture-edge event specified in bits 7:5 occurs.
3015 */
3016#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
3017#define CTIMER_CTCR_SELCC_MASK (0xE0U)
3018#define CTIMER_CTCR_SELCC_SHIFT (5U)
3019/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
3020 * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
3021 * 0x3 and 0x6 to 0x7 are reserved.
3022 * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
3023 * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
3024 * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
3025 * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
3026 * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
3027 * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
3028 */
3029#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
3030/*! @} */
3031
3032/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
3033/*! @{ */
3034#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
3035#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
3036/*! PWMEN0 - PWM mode enable for channel0.
3037 * 0b0..Match. CTIMERn_MAT0 is controlled by EM0.
3038 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
3039 */
3040#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
3041#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
3042#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
3043/*! PWMEN1 - PWM mode enable for channel1.
3044 * 0b0..Match. CTIMERn_MAT01 is controlled by EM1.
3045 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
3046 */
3047#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
3048#define CTIMER_PWMC_PWMEN2_MASK (0x4U)
3049#define CTIMER_PWMC_PWMEN2_SHIFT (2U)
3050/*! PWMEN2 - PWM mode enable for channel2.
3051 * 0b0..Match. CTIMERn_MAT2 is controlled by EM2.
3052 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
3053 */
3054#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
3055#define CTIMER_PWMC_PWMEN3_MASK (0x8U)
3056#define CTIMER_PWMC_PWMEN3_SHIFT (3U)
3057/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
3058 * 0b0..Match. CTIMERn_MAT3 is controlled by EM3.
3059 * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
3060 */
3061#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
3062/*! @} */
3063
3064/*! @name MSR - Match Shadow Register */
3065/*! @{ */
3066#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU)
3067#define CTIMER_MSR_SHADOWW_SHIFT (0U)
3068/*! SHADOWW - Timer counter match shadow value.
3069 */
3070#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)
3071/*! @} */
3072
3073/* The count of CTIMER_MSR */
3074#define CTIMER_MSR_COUNT (4U)
3075
3076
3077/*!
3078 * @}
3079 */ /* end of group CTIMER_Register_Masks */
3080
3081
3082/* CTIMER - Peripheral instance base addresses */
3083/** Peripheral CTIMER0 base address */
3084#define CTIMER0_BASE (0x40008000u)
3085/** Peripheral CTIMER0 base pointer */
3086#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
3087/** Peripheral CTIMER1 base address */
3088#define CTIMER1_BASE (0x40009000u)
3089/** Peripheral CTIMER1 base pointer */
3090#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
3091/** Peripheral CTIMER2 base address */
3092#define CTIMER2_BASE (0x40028000u)
3093/** Peripheral CTIMER2 base pointer */
3094#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
3095/** Peripheral CTIMER3 base address */
3096#define CTIMER3_BASE (0x40048000u)
3097/** Peripheral CTIMER3 base pointer */
3098#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
3099/** Peripheral CTIMER4 base address */
3100#define CTIMER4_BASE (0x40049000u)
3101/** Peripheral CTIMER4 base pointer */
3102#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
3103/** Array initializer of CTIMER peripheral base addresses */
3104#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
3105/** Array initializer of CTIMER peripheral base pointers */
3106#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
3107/** Interrupt vectors for the CTIMER peripheral type */
3108#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
3109
3110/*!
3111 * @}
3112 */ /* end of group CTIMER_Peripheral_Access_Layer */
3113
3114
3115/* ----------------------------------------------------------------------------
3116 -- DMA Peripheral Access Layer
3117 ---------------------------------------------------------------------------- */
3118
3119/*!
3120 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
3121 * @{
3122 */
3123
3124/** DMA - Register Layout Typedef */
3125typedef struct {
3126 __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
3127 __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
3128 __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
3129 uint8_t RESERVED_0[20];
3130 struct { /* offset: 0x20, array step: 0x5C */
3131 __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
3132 uint8_t RESERVED_0[4];
3133 __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
3134 uint8_t RESERVED_1[4];
3135 __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
3136 uint8_t RESERVED_2[4];
3137 __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
3138 uint8_t RESERVED_3[4];
3139 __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
3140 uint8_t RESERVED_4[4];
3141 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
3142 uint8_t RESERVED_5[4];
3143 __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
3144 uint8_t RESERVED_6[4];
3145 __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
3146 uint8_t RESERVED_7[4];
3147 __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
3148 uint8_t RESERVED_8[4];
3149 __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
3150 uint8_t RESERVED_9[4];
3151 __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
3152 uint8_t RESERVED_10[4];
3153 __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
3154 } COMMON[1];
3155 uint8_t RESERVED_1[900];
3156 struct { /* offset: 0x400, array step: 0x10 */
3157 __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
3158 __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
3159 __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
3160 uint8_t RESERVED_0[4];
3161 } CHANNEL[30];
3162} DMA_Type;
3163
3164/* ----------------------------------------------------------------------------
3165 -- DMA Register Masks
3166 ---------------------------------------------------------------------------- */
3167
3168/*!
3169 * @addtogroup DMA_Register_Masks DMA Register Masks
3170 * @{
3171 */
3172
3173/*! @name CTRL - DMA control. */
3174/*! @{ */
3175#define DMA_CTRL_ENABLE_MASK (0x1U)
3176#define DMA_CTRL_ENABLE_SHIFT (0U)
3177/*! ENABLE - DMA controller master enable.
3178 * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
3179 * disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
3180 * 0b1..Enabled. The DMA controller is enabled.
3181 */
3182#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
3183/*! @} */
3184
3185/*! @name INTSTAT - Interrupt status. */
3186/*! @{ */
3187#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
3188#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
3189/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
3190 * 0b0..Not pending. No enabled interrupts are pending.
3191 * 0b1..Pending. At least one enabled interrupt is pending.
3192 */
3193#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
3194#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
3195#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
3196/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
3197 * 0b0..Not pending. No error interrupts are pending.
3198 * 0b1..Pending. At least one error interrupt is pending.
3199 */
3200#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
3201/*! @} */
3202
3203/*! @name SRAMBASE - SRAM address of the channel configuration table. */
3204/*! @{ */
3205#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
3206#define DMA_SRAMBASE_OFFSET_SHIFT (9U)
3207/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
3208 * table must begin on a 512 byte boundary.
3209 */
3210#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
3211/*! @} */
3212
3213/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
3214/*! @{ */
3215#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)
3216#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
3217/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
3218 * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
3219 */
3220#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
3221/*! @} */
3222
3223/* The count of DMA_COMMON_ENABLESET */
3224#define DMA_COMMON_ENABLESET_COUNT (1U)
3225
3226/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
3227/*! @{ */
3228#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)
3229#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
3230/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
3231 * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
3232 * are reserved.
3233 */
3234#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
3235/*! @} */
3236
3237/* The count of DMA_COMMON_ENABLECLR */
3238#define DMA_COMMON_ENABLECLR_COUNT (1U)
3239
3240/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
3241/*! @{ */
3242#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)
3243#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
3244/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
3245 * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
3246 */
3247#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
3248/*! @} */
3249
3250/* The count of DMA_COMMON_ACTIVE */
3251#define DMA_COMMON_ACTIVE_COUNT (1U)
3252
3253/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
3254/*! @{ */
3255#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)
3256#define DMA_COMMON_BUSY_BSY_SHIFT (0U)
3257/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
3258 * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
3259 */
3260#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
3261/*! @} */
3262
3263/* The count of DMA_COMMON_BUSY */
3264#define DMA_COMMON_BUSY_COUNT (1U)
3265
3266/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
3267/*! @{ */
3268#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)
3269#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
3270/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
3271 * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
3272 * not active. 1 = error interrupt is active.
3273 */
3274#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
3275/*! @} */
3276
3277/* The count of DMA_COMMON_ERRINT */
3278#define DMA_COMMON_ERRINT_COUNT (1U)
3279
3280/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
3281/*! @{ */
3282#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)
3283#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
3284/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
3285 * number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
3286 * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
3287 */
3288#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
3289/*! @} */
3290
3291/* The count of DMA_COMMON_INTENSET */
3292#define DMA_COMMON_INTENSET_COUNT (1U)
3293
3294/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
3295/*! @{ */
3296#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)
3297#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
3298/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
3299 * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
3300 * reserved.
3301 */
3302#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
3303/*! @} */
3304
3305/* The count of DMA_COMMON_INTENCLR */
3306#define DMA_COMMON_INTENCLR_COUNT (1U)
3307
3308/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
3309/*! @{ */
3310#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)
3311#define DMA_COMMON_INTA_IA_SHIFT (0U)
3312/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
3313 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
3314 * interrupt A is not active. 1 = the DMA channel interrupt A is active.
3315 */
3316#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
3317/*! @} */
3318
3319/* The count of DMA_COMMON_INTA */
3320#define DMA_COMMON_INTA_COUNT (1U)
3321
3322/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
3323/*! @{ */
3324#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)
3325#define DMA_COMMON_INTB_IB_SHIFT (0U)
3326/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
3327 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
3328 * interrupt B is not active. 1 = the DMA channel interrupt B is active.
3329 */
3330#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
3331/*! @} */
3332
3333/* The count of DMA_COMMON_INTB */
3334#define DMA_COMMON_INTB_COUNT (1U)
3335
3336/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
3337/*! @{ */
3338#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)
3339#define DMA_COMMON_SETVALID_SV_SHIFT (0U)
3340/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
3341 * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
3342 * VALIDPENDING control bit for DMA channel n
3343 */
3344#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
3345/*! @} */
3346
3347/* The count of DMA_COMMON_SETVALID */
3348#define DMA_COMMON_SETVALID_COUNT (1U)
3349
3350/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
3351/*! @{ */
3352#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)
3353#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
3354/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
3355 * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
3356 * sets the TRIG bit for DMA channel n.
3357 */
3358#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
3359/*! @} */
3360
3361/* The count of DMA_COMMON_SETTRIG */
3362#define DMA_COMMON_SETTRIG_COUNT (1U)
3363
3364/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
3365/*! @{ */
3366#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)
3367#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
3368/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
3369 * 1 = aborts DMA operations on channel n.
3370 */
3371#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
3372/*! @} */
3373
3374/* The count of DMA_COMMON_ABORT */
3375#define DMA_COMMON_ABORT_COUNT (1U)
3376
3377/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
3378/*! @{ */
3379#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
3380#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
3381/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
3382 * move, any peripheral DMA request associated with that channel can be disabled to prevent any
3383 * interaction between the peripheral and the DMA controller.
3384 * 0b0..Disabled. Peripheral DMA requests are disabled.
3385 * 0b1..Enabled. Peripheral DMA requests are enabled.
3386 */
3387#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
3388#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
3389#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
3390/*! HWTRIGEN - Hardware Triggering Enable for this channel.
3391 * 0b0..Disabled. Hardware triggering is not used.
3392 * 0b1..Enabled. Use hardware triggering.
3393 */
3394#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
3395#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
3396#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
3397/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
3398 * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
3399 * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
3400 */
3401#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
3402#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
3403#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
3404/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
3405 * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
3406 * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
3407 * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
3408 * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
3409 * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
3410 * current BURSTPOWER length are completed.
3411 */
3412#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
3413#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
3414#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
3415/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
3416 * 0b0..Single transfer. Hardware trigger causes a single transfer.
3417 * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
3418 * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a
3419 * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
3420 * complete.
3421 */
3422#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
3423#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
3424#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
3425/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
3426 * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
3427 * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
3428 * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that
3429 * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:
3430 * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =
3431 * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The
3432 * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
3433 * multiple of the burst size.
3434 */
3435#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
3436#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
3437#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
3438/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
3439 * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this
3440 * could be used to read several sequential registers from a peripheral for each DMA burst,
3441 * reading the same registers again for each burst.
3442 * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
3443 * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
3444 */
3445#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
3446#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
3447#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
3448/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
3449 * 'wrapped', meaning that the destination address range for each burst will be the same. As an
3450 * example, this could be used to write several sequential registers to a peripheral for each DMA
3451 * burst, writing the same registers again for each burst.
3452 * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
3453 * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
3454 */
3455#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
3456#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
3457#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
3458/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority
3459 * levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
3460 */
3461#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
3462/*! @} */
3463
3464/* The count of DMA_CHANNEL_CFG */
3465#define DMA_CHANNEL_CFG_COUNT (30U)
3466
3467/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
3468/*! @{ */
3469#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
3470#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
3471/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the
3472 * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
3473 * 0b0..No effect. No effect on DMA operation.
3474 * 0b1..Valid pending.
3475 */
3476#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
3477#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
3478#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
3479/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is
3480 * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
3481 * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
3482 * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
3483 */
3484#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
3485/*! @} */
3486
3487/* The count of DMA_CHANNEL_CTLSTAT */
3488#define DMA_CHANNEL_CTLSTAT_COUNT (30U)
3489
3490/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
3491/*! @{ */
3492#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
3493#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
3494/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor
3495 * is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
3496 * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
3497 * 0b1..Valid. The current channel descriptor is considered valid.
3498 */
3499#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
3500#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
3501#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
3502/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current
3503 * descriptor is exhausted. Reloading allows ping-pong and linked transfers.
3504 * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
3505 * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.
3506 */
3507#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
3508#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
3509#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
3510/*! SWTRIG - Software Trigger.
3511 * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by
3512 * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
3513 * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not
3514 * be used with level triggering when TRIGBURST = 0.
3515 */
3516#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
3517#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)
3518#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)
3519/*! CLRTRIG - Clear Trigger.
3520 * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
3521 * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted
3522 */
3523#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
3524#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)
3525#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)
3526/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between
3527 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
3528 * convention, interrupt A may be used when only one interrupt flag is needed.
3529 * 0b0..No effect.
3530 * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
3531 */
3532#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
3533#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)
3534#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)
3535/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between
3536 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
3537 * convention, interrupt A may be used when only one interrupt flag is needed.
3538 * 0b0..No effect.
3539 * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
3540 */
3541#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
3542#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)
3543#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)
3544/*! WIDTH - Transfer width used for this DMA channel.
3545 * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
3546 * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
3547 * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
3548 * 0b11..Reserved. Reserved setting, do not use.
3549 */
3550#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
3551#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)
3552#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)
3553/*! SRCINC - Determines whether the source address is incremented for each DMA transfer.
3554 * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
3555 * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is
3556 * the usual case when the source is memory.
3557 * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
3558 * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
3559 */
3560#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
3561#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)
3562#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)
3563/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer.
3564 * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when
3565 * the destination is a peripheral device.
3566 * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer.
3567 * This is the usual case when the destination is memory.
3568 * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
3569 * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
3570 */
3571#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
3572#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)
3573#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)
3574/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes
3575 * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller
3576 * uses this bit field during transfer to count down. Hence, it cannot be used by software to read
3577 * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1
3578 * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of
3579 * 1,024 transfers will be performed.
3580 */
3581#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
3582/*! @} */
3583
3584/* The count of DMA_CHANNEL_XFERCFG */
3585#define DMA_CHANNEL_XFERCFG_COUNT (30U)
3586
3587
3588/*!
3589 * @}
3590 */ /* end of group DMA_Register_Masks */
3591
3592
3593/* DMA - Peripheral instance base addresses */
3594/** Peripheral DMA0 base address */
3595#define DMA0_BASE (0x40082000u)
3596/** Peripheral DMA0 base pointer */
3597#define DMA0 ((DMA_Type *)DMA0_BASE)
3598/** Array initializer of DMA peripheral base addresses */
3599#define DMA_BASE_ADDRS { DMA0_BASE }
3600/** Array initializer of DMA peripheral base pointers */
3601#define DMA_BASE_PTRS { DMA0 }
3602/** Interrupt vectors for the DMA peripheral type */
3603#define DMA_IRQS { DMA0_IRQn }
3604
3605/*!
3606 * @}
3607 */ /* end of group DMA_Peripheral_Access_Layer */
3608
3609
3610/* ----------------------------------------------------------------------------
3611 -- DMIC Peripheral Access Layer
3612 ---------------------------------------------------------------------------- */
3613
3614/*!
3615 * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
3616 * @{
3617 */
3618
3619/** DMIC - Register Layout Typedef */
3620typedef struct {
3621 struct { /* offset: 0x0, array step: 0x100 */
3622 __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */
3623 __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */
3624 __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */
3625 __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */
3626 __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */
3627 uint8_t RESERVED_0[108];
3628 __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */
3629 __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */
3630 __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */
3631 __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */
3632 __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */
3633 uint8_t RESERVED_1[108];
3634 } CHANNEL[2];
3635 uint8_t RESERVED_0[3328];
3636 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */
3637 uint8_t RESERVED_1[8];
3638 __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */
3639 __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */
3640 uint8_t RESERVED_2[108];
3641 __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */
3642 __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */
3643 __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */
3644 __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */
3645 __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */
3646 __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */
3647 __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */
3648 uint8_t RESERVED_3[96];
3649 __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */
3650} DMIC_Type;
3651
3652/* ----------------------------------------------------------------------------
3653 -- DMIC Register Masks
3654 ---------------------------------------------------------------------------- */
3655
3656/*!
3657 * @addtogroup DMIC_Register_Masks DMIC Register Masks
3658 * @{
3659 */
3660
3661/*! @name CHANNEL_OSR - Oversample Rate register 0 */
3662/*! @{ */
3663#define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU)
3664#define DMIC_CHANNEL_OSR_OSR_SHIFT (0U)
3665/*! OSR - Selects the oversample rate for the related input channel.
3666 */
3667#define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
3668/*! @} */
3669
3670/* The count of DMIC_CHANNEL_OSR */
3671#define DMIC_CHANNEL_OSR_COUNT (2U)
3672
3673/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */
3674/*! @{ */
3675#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU)
3676#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U)
3677/*! PDMDIV - PDM clock divider value. 0 = divide by 1 1 = divide by 2 2 = divide by 3 3 = divide by
3678 * 4 4 = divide by 6 5 = divide by 8 6 = divide by 12 7 = divide by 16 8 = divide by 24 9 =
3679 * divide by 32 10 = divide by 48 11 = divide by 64 12 = divide by 96 13 = divide by 128 others =
3680 * reserved.
3681 */
3682#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
3683/*! @} */
3684
3685/* The count of DMIC_CHANNEL_DIVHFCLK */
3686#define DMIC_CHANNEL_DIVHFCLK_COUNT (2U)
3687
3688/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */
3689/*! @{ */
3690#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U)
3691#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U)
3692/*! COMP - Pre-emphasis filer coefficient for 2 FS mode. 0 = Compensation = 0 1 = Compensation = 16
3693 * 2 = Compensation = 15 3 = Compensation = 13
3694 */
3695#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
3696/*! @} */
3697
3698/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
3699#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U)
3700
3701/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */
3702/*! @{ */
3703#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U)
3704#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U)
3705/*! COMP - Pre-emphasis filer coefficient for 4 FS mode. 0 = Compensation = 0 1 = Compensation = 16
3706 * 2 = Compensation = 15 3 = Compensation = 13
3707 */
3708#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
3709/*! @} */
3710
3711/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
3712#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U)
3713
3714/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */
3715/*! @{ */
3716#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU)
3717#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U)
3718/*! GAIN - Gain control, as a positive or negative (two's complement) number of bits to shift.
3719 */
3720#define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
3721/*! @} */
3722
3723/* The count of DMIC_CHANNEL_GAINSHIFT */
3724#define DMIC_CHANNEL_GAINSHIFT_COUNT (2U)
3725
3726/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */
3727/*! @{ */
3728#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U)
3729#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U)
3730/*! ENABLE - FIFO enable.
3731 * 0b0..FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being
3732 * streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a
3733 * period when the data was not needed.
3734 * 0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
3735 */
3736#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
3737#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U)
3738#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U)
3739/*! RESETN - FIFO reset.
3740 * 0b0..Reset the FIFO.
3741 * 0b1..Normal operation
3742 */
3743#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
3744#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U)
3745#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U)
3746/*! INTEN - Interrupt enable.
3747 * 0b0..FIFO level interrupts are not enabled.
3748 * 0b1..FIFO level interrupts are enabled.
3749 */
3750#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
3751#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U)
3752#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U)
3753/*! DMAEN - DMA enable
3754 * 0b0..DMA requests are not enabled.
3755 * 0b1..DMA requests based on FIFO level are enabled.
3756 */
3757#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
3758#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U)
3759#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U)
3760/*! TRIGLVL - FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If
3761 * enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then
3762 * return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 =
3763 * trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has
3764 * received two entries. 15 = trigger when the FIFO has received 16 entries (has become full).
3765 */
3766#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
3767/*! @} */
3768
3769/* The count of DMIC_CHANNEL_FIFO_CTRL */
3770#define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U)
3771
3772/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */
3773/*! @{ */
3774#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U)
3775#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U)
3776/*! INT - Interrupt flag. Asserted when FIFO data reaches the level specified in the FIFOCTRL
3777 * register. Writing a one to this bit clears the flag. Remark: note that the bus clock to the DMIC
3778 * subsystem must be running in order for an interrupt to occur.
3779 */
3780#define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
3781#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U)
3782#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U)
3783/*! OVERRUN - Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one
3784 * to this bit clears the flag. This flag does not cause an interrupt.
3785 */
3786#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
3787#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U)
3788#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U)
3789/*! UNDERRUN - Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag.
3790 */
3791#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
3792/*! @} */
3793
3794/* The count of DMIC_CHANNEL_FIFO_STATUS */
3795#define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U)
3796
3797/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */
3798/*! @{ */
3799#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU)
3800#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U)
3801/*! DATA - Data from the top of the input filter FIFO.
3802 */
3803#define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
3804/*! @} */
3805
3806/* The count of DMIC_CHANNEL_FIFO_DATA */
3807#define DMIC_CHANNEL_FIFO_DATA_COUNT (2U)
3808
3809/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */
3810/*! @{ */
3811#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U)
3812#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U)
3813/*! PHY_FALL - Capture PDM_DATA
3814 * 0b0..Capture PDM_DATA on the rising edge of PDM_CLK.
3815 * 0b1..Capture PDM_DATA on the falling edge of PDM_CLK.
3816 */
3817#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
3818#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U)
3819#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U)
3820/*! PHY_HALF - Half rate sampling
3821 * 0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
3822 * 0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.
3823 */
3824#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
3825/*! @} */
3826
3827/* The count of DMIC_CHANNEL_PHY_CTRL */
3828#define DMIC_CHANNEL_PHY_CTRL_COUNT (2U)
3829
3830/*! @name CHANNEL_DC_CTRL - DC Control register 0 */
3831/*! @{ */
3832#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U)
3833#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U)
3834/*! DCPOLE - DC block filter
3835 * 0b00..Flat response, no filter.
3836 * 0b01..155 Hz.
3837 * 0b10..78 Hz.
3838 * 0b11..39 Hz
3839 */
3840#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
3841#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U)
3842#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U)
3843/*! DCGAIN - Fine gain adjustment in the form of a number of bits to downshift.
3844 */
3845#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
3846#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
3847#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
3848/*! SATURATEAT16BIT - Selects 16-bit saturation.
3849 * 0b0..Results roll over if out range and do not saturate.
3850 * 0b1..If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
3851 */
3852#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
3853/*! @} */
3854
3855/* The count of DMIC_CHANNEL_DC_CTRL */
3856#define DMIC_CHANNEL_DC_CTRL_COUNT (2U)
3857
3858/*! @name CHANEN - Channel Enable register */
3859/*! @{ */
3860#define DMIC_CHANEN_EN_CH0_MASK (0x1U)
3861#define DMIC_CHANEN_EN_CH0_SHIFT (0U)
3862/*! EN_CH0 - Enable channel 0. When 1, PDM channel 0 is enabled.
3863 */
3864#define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
3865#define DMIC_CHANEN_EN_CH1_MASK (0x2U)
3866#define DMIC_CHANEN_EN_CH1_SHIFT (1U)
3867/*! EN_CH1 - Enable channel 1. When 1, PDM channel 1 is enabled.
3868 */
3869#define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
3870/*! @} */
3871
3872/*! @name IOCFG - I/O Configuration register */
3873/*! @{ */
3874#define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U)
3875#define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U)
3876/*! CLK_BYPASS0 - Bypass CLK0. When 1, PDM_DATA1 becomes the clock for PDM channel 0. This provides
3877 * for the possibility of an external codec taking over the PDM bus.
3878 */
3879#define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)
3880#define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U)
3881#define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U)
3882/*! CLK_BYPASS1 - Bypass CLK1. When 1, PDM_DATA1 becomes the clock for PDM channel 1. This provides
3883 * for the possibility of an external codec taking over the PDM bus.
3884 */
3885#define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)
3886#define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U)
3887#define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U)
3888/*! STEREO_DATA0 - Stereo PDM select. When 1, PDM_DATA0 is routed to both PDM channels in a
3889 * configuration that supports a single stereo digital microphone.
3890 */
3891#define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)
3892/*! @} */
3893
3894/*! @name USE2FS - Use 2FS register */
3895/*! @{ */
3896#define DMIC_USE2FS_USE2FS_MASK (0x1U)
3897#define DMIC_USE2FS_USE2FS_SHIFT (0U)
3898/*! USE2FS - Use 2FS register
3899 * 0b0..Use 1FS output for PCM data.
3900 * 0b1..Use 2FS output for PCM data.
3901 */
3902#define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
3903/*! @} */
3904
3905/*! @name HWVADGAIN - HWVAD input gain register */
3906/*! @{ */
3907#define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU)
3908#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U)
3909/*! INPUTGAIN - Shift value for input bits 0x00 -10 bits 0x01 -8 bits 0x02 -6 bits 0x03 -4 bits 0x04
3910 * -2 bits 0x05 0 bits (default) 0x06 +2 bits 0x07 +4 bits 0x08 +6 bits 0x09 +8 bits 0x0A +10
3911 * bits 0x0B +12 bits 0x0C +14 bits 0x0D to 0x0F Reserved.
3912 */
3913#define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
3914/*! @} */
3915
3916/*! @name HWVADHPFS - HWVAD filter control register */
3917/*! @{ */
3918#define DMIC_HWVADHPFS_HPFS_MASK (0x3U)
3919#define DMIC_HWVADHPFS_HPFS_SHIFT (0U)
3920/*! HPFS - High pass filter
3921 * 0b00..First filter by-pass.
3922 * 0b01..High pass filter with -3dB cut-off at 1750Hz.
3923 * 0b10..High pass filter with -3dB cut-off at 215Hz.
3924 * 0b11..Reserved.
3925 */
3926#define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
3927/*! @} */
3928
3929/*! @name HWVADST10 - HWVAD control register */
3930/*! @{ */
3931#define DMIC_HWVADST10_ST10_MASK (0x1U)
3932#define DMIC_HWVADST10_ST10_SHIFT (0U)
3933/*! ST10 - Stage 0
3934 * 0b0..Normal operation, waiting for HWVAD trigger event (stage 0).
3935 * 0b1..Reset internal interrupt flag by writing a '1' pulse.
3936 */
3937#define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
3938/*! @} */
3939
3940/*! @name HWVADRSTT - HWVAD filter reset register */
3941/*! @{ */
3942#define DMIC_HWVADRSTT_RSTT_MASK (0x1U)
3943#define DMIC_HWVADRSTT_RSTT_SHIFT (0U)
3944/*! RSTT - Writing a 1 resets all filter values
3945 */
3946#define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)
3947/*! @} */
3948
3949/*! @name HWVADTHGN - HWVAD noise estimator gain register */
3950/*! @{ */
3951#define DMIC_HWVADTHGN_THGN_MASK (0xFU)
3952#define DMIC_HWVADTHGN_THGN_SHIFT (0U)
3953/*! THGN - Gain value for the noise estimator. Values 0 to 14. 0 corresponds to a gain of 1.
3954 */
3955#define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
3956/*! @} */
3957
3958/*! @name HWVADTHGS - HWVAD signal estimator gain register */
3959/*! @{ */
3960#define DMIC_HWVADTHGS_THGS_MASK (0xFU)
3961#define DMIC_HWVADTHGS_THGS_SHIFT (0U)
3962/*! THGS - Gain value for the signal estimator. Values 0 to 14. 0 corresponds to a gain of 1.
3963 */
3964#define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
3965/*! @} */
3966
3967/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */
3968/*! @{ */
3969#define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU)
3970#define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U)
3971/*! LOWZ - Noise envelope estimator value.
3972 */
3973#define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
3974/*! @} */
3975
3976/*! @name ID - Module Identification register */
3977/*! @{ */
3978#define DMIC_ID_ID_MASK (0xFFFFFFFFU)
3979#define DMIC_ID_ID_SHIFT (0U)
3980/*! ID - Indicates module ID and the number of channels in this DMIC interface.
3981 */
3982#define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)
3983/*! @} */
3984
3985
3986/*!
3987 * @}
3988 */ /* end of group DMIC_Register_Masks */
3989
3990
3991/* DMIC - Peripheral instance base addresses */
3992/** Peripheral DMIC0 base address */
3993#define DMIC0_BASE (0x40090000u)
3994/** Peripheral DMIC0 base pointer */
3995#define DMIC0 ((DMIC_Type *)DMIC0_BASE)
3996/** Array initializer of DMIC peripheral base addresses */
3997#define DMIC_BASE_ADDRS { DMIC0_BASE }
3998/** Array initializer of DMIC peripheral base pointers */
3999#define DMIC_BASE_PTRS { DMIC0 }
4000/** Interrupt vectors for the DMIC peripheral type */
4001#define DMIC_IRQS { DMIC0_IRQn }
4002#define DMIC_HWVAD_IRQS { HWVAD0_IRQn }
4003
4004/*!
4005 * @}
4006 */ /* end of group DMIC_Peripheral_Access_Layer */
4007
4008
4009/* ----------------------------------------------------------------------------
4010 -- EEPROM Peripheral Access Layer
4011 ---------------------------------------------------------------------------- */
4012
4013/*!
4014 * @addtogroup EEPROM_Peripheral_Access_Layer EEPROM Peripheral Access Layer
4015 * @{
4016 */
4017
4018/** EEPROM - Register Layout Typedef */
4019typedef struct {
4020 __IO uint32_t CMD; /**< EEPROM command register, offset: 0x0 */
4021 uint8_t RESERVED_0[4];
4022 __IO uint32_t RWSTATE; /**< EEPROM read wait state register, offset: 0x8 */
4023 __IO uint32_t AUTOPROG; /**< EEPROM auto programming register, offset: 0xC */
4024 __IO uint32_t WSTATE; /**< EEPROM wait state register, offset: 0x10 */
4025 __IO uint32_t CLKDIV; /**< EEPROM clock divider register, offset: 0x14 */
4026 __IO uint32_t PWRDWN; /**< EEPROM power-down register, offset: 0x18 */
4027 uint8_t RESERVED_1[4028];
4028 __O uint32_t INTENCLR; /**< EEPROM interrupt enable clear, offset: 0xFD8 */
4029 __O uint32_t INTENSET; /**< EEPROM interrupt enable set, offset: 0xFDC */
4030 __I uint32_t INTSTAT; /**< EEPROM interrupt status, offset: 0xFE0 */
4031 __I uint32_t INTEN; /**< EEPROM interrupt enable, offset: 0xFE4 */
4032 __O uint32_t INTSTATCLR; /**< EEPROM interrupt status clear, offset: 0xFE8 */
4033 __O uint32_t INTSTATSET; /**< EEPROM interrupt status set, offset: 0xFEC */
4034} EEPROM_Type;
4035
4036/* ----------------------------------------------------------------------------
4037 -- EEPROM Register Masks
4038 ---------------------------------------------------------------------------- */
4039
4040/*!
4041 * @addtogroup EEPROM_Register_Masks EEPROM Register Masks
4042 * @{
4043 */
4044
4045/*! @name CMD - EEPROM command register */
4046/*! @{ */
4047#define EEPROM_CMD_CMD_MASK (0x7U)
4048#define EEPROM_CMD_CMD_SHIFT (0U)
4049/*! CMD - Command.
4050 */
4051#define EEPROM_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_CMD_CMD_SHIFT)) & EEPROM_CMD_CMD_MASK)
4052/*! @} */
4053
4054/*! @name RWSTATE - EEPROM read wait state register */
4055/*! @{ */
4056#define EEPROM_RWSTATE_RPHASE2_MASK (0xFFU)
4057#define EEPROM_RWSTATE_RPHASE2_SHIFT (0U)
4058/*! RPHASE2 - Wait states 2 (minus 1 encoded).
4059 */
4060#define EEPROM_RWSTATE_RPHASE2(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE2_SHIFT)) & EEPROM_RWSTATE_RPHASE2_MASK)
4061#define EEPROM_RWSTATE_RPHASE1_MASK (0xFF00U)
4062#define EEPROM_RWSTATE_RPHASE1_SHIFT (8U)
4063/*! RPHASE1 - Wait states 1 (minus 1 encoded).
4064 */
4065#define EEPROM_RWSTATE_RPHASE1(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE1_SHIFT)) & EEPROM_RWSTATE_RPHASE1_MASK)
4066/*! @} */
4067
4068/*! @name AUTOPROG - EEPROM auto programming register */
4069/*! @{ */
4070#define EEPROM_AUTOPROG_AUTOPROG_MASK (0x3U)
4071#define EEPROM_AUTOPROG_AUTOPROG_SHIFT (0U)
4072/*! AUTOPROG - Auto programming mode: 00 = auto programming off 01 = erase/program cycle is
4073 * triggered after 1 word is written 10 = erase/program cycle is triggered after a write to AHB address
4074 * ending with .
4075 */
4076#define EEPROM_AUTOPROG_AUTOPROG(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_AUTOPROG_AUTOPROG_SHIFT)) & EEPROM_AUTOPROG_AUTOPROG_MASK)
4077/*! @} */
4078
4079/*! @name WSTATE - EEPROM wait state register */
4080/*! @{ */
4081#define EEPROM_WSTATE_PHASE3_MASK (0xFFU)
4082#define EEPROM_WSTATE_PHASE3_SHIFT (0U)
4083/*! PHASE3 - Wait states for phase 3 (minus 1 encoded).
4084 */
4085#define EEPROM_WSTATE_PHASE3(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE3_SHIFT)) & EEPROM_WSTATE_PHASE3_MASK)
4086#define EEPROM_WSTATE_PHASE2_MASK (0xFF00U)
4087#define EEPROM_WSTATE_PHASE2_SHIFT (8U)
4088/*! PHASE2 - Wait states for phase 2 (minus 1 encoded).
4089 */
4090#define EEPROM_WSTATE_PHASE2(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE2_SHIFT)) & EEPROM_WSTATE_PHASE2_MASK)
4091#define EEPROM_WSTATE_PHASE1_MASK (0xFF0000U)
4092#define EEPROM_WSTATE_PHASE1_SHIFT (16U)
4093/*! PHASE1 - Wait states for phase 1 (minus 1 encoded).
4094 */
4095#define EEPROM_WSTATE_PHASE1(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE1_SHIFT)) & EEPROM_WSTATE_PHASE1_MASK)
4096#define EEPROM_WSTATE_LCK_PARWEP_MASK (0x80000000U)
4097#define EEPROM_WSTATE_LCK_PARWEP_SHIFT (31U)
4098/*! LCK_PARWEP - Lock timing parameters for write, erase and program operation 0 = WSTATE and CLKDIV
4099 * registers have R/W access 1 = WSTATE and CLKDIV registers have R only access.
4100 */
4101#define EEPROM_WSTATE_LCK_PARWEP(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_LCK_PARWEP_SHIFT)) & EEPROM_WSTATE_LCK_PARWEP_MASK)
4102/*! @} */
4103
4104/*! @name CLKDIV - EEPROM clock divider register */
4105/*! @{ */
4106#define EEPROM_CLKDIV_CLKDIV_MASK (0xFFFFU)
4107#define EEPROM_CLKDIV_CLKDIV_SHIFT (0U)
4108/*! CLKDIV - Division factor (minus 1 encoded).
4109 */
4110#define EEPROM_CLKDIV_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_CLKDIV_CLKDIV_SHIFT)) & EEPROM_CLKDIV_CLKDIV_MASK)
4111/*! @} */
4112
4113/*! @name PWRDWN - EEPROM power-down register */
4114/*! @{ */
4115#define EEPROM_PWRDWN_PWRDWN_MASK (0x1U)
4116#define EEPROM_PWRDWN_PWRDWN_SHIFT (0U)
4117/*! PWRDWN - Power down mode bit.
4118 */
4119#define EEPROM_PWRDWN_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_PWRDWN_PWRDWN_SHIFT)) & EEPROM_PWRDWN_PWRDWN_MASK)
4120/*! @} */
4121
4122/*! @name INTENCLR - EEPROM interrupt enable clear */
4123/*! @{ */
4124#define EEPROM_INTENCLR_PROG_CLR_EN_MASK (0x4U)
4125#define EEPROM_INTENCLR_PROG_CLR_EN_SHIFT (2U)
4126/*! PROG_CLR_EN - Clear program operation finished interrupt enable bit for EEPROM.
4127 */
4128#define EEPROM_INTENCLR_PROG_CLR_EN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENCLR_PROG_CLR_EN_SHIFT)) & EEPROM_INTENCLR_PROG_CLR_EN_MASK)
4129/*! @} */
4130
4131/*! @name INTENSET - EEPROM interrupt enable set */
4132/*! @{ */
4133#define EEPROM_INTENSET_PROG_SET_EN_MASK (0x4U)
4134#define EEPROM_INTENSET_PROG_SET_EN_SHIFT (2U)
4135/*! PROG_SET_EN - Set program operation finished interrupt enable bit for EEPROM device 1.
4136 */
4137#define EEPROM_INTENSET_PROG_SET_EN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENSET_PROG_SET_EN_SHIFT)) & EEPROM_INTENSET_PROG_SET_EN_MASK)
4138/*! @} */
4139
4140/*! @name INTSTAT - EEPROM interrupt status */
4141/*! @{ */
4142#define EEPROM_INTSTAT_END_OF_PROG_MASK (0x4U)
4143#define EEPROM_INTSTAT_END_OF_PROG_SHIFT (2U)
4144/*! END_OF_PROG - EEPROM program operation finished interrupt status bit.
4145 */
4146#define EEPROM_INTSTAT_END_OF_PROG(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTAT_END_OF_PROG_SHIFT)) & EEPROM_INTSTAT_END_OF_PROG_MASK)
4147/*! @} */
4148
4149/*! @name INTEN - EEPROM interrupt enable */
4150/*! @{ */
4151#define EEPROM_INTEN_EE_PROG_DONE_MASK (0x4U)
4152#define EEPROM_INTEN_EE_PROG_DONE_SHIFT (2U)
4153/*! EE_PROG_DONE - EEPROM program operation finished interrupt enable bit.
4154 */
4155#define EEPROM_INTEN_EE_PROG_DONE(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTEN_EE_PROG_DONE_SHIFT)) & EEPROM_INTEN_EE_PROG_DONE_MASK)
4156/*! @} */
4157
4158/*! @name INTSTATCLR - EEPROM interrupt status clear */
4159/*! @{ */
4160#define EEPROM_INTSTATCLR_PROG_CLR_ST_MASK (0x4U)
4161#define EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT (2U)
4162/*! PROG_CLR_ST - Clear program operation finished interrupt status bit for EEPROM device.
4163 */
4164#define EEPROM_INTSTATCLR_PROG_CLR_ST(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT)) & EEPROM_INTSTATCLR_PROG_CLR_ST_MASK)
4165/*! @} */
4166
4167/*! @name INTSTATSET - EEPROM interrupt status set */
4168/*! @{ */
4169#define EEPROM_INTSTATSET_PROG_SET_ST_MASK (0x4U)
4170#define EEPROM_INTSTATSET_PROG_SET_ST_SHIFT (2U)
4171/*! PROG_SET_ST - Set program operation finished interrupt status bit for EEPROM device.
4172 */
4173#define EEPROM_INTSTATSET_PROG_SET_ST(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATSET_PROG_SET_ST_SHIFT)) & EEPROM_INTSTATSET_PROG_SET_ST_MASK)
4174/*! @} */
4175
4176
4177/*!
4178 * @}
4179 */ /* end of group EEPROM_Register_Masks */
4180
4181
4182/* EEPROM - Peripheral instance base addresses */
4183/** Peripheral EEPROM base address */
4184#define EEPROM_BASE (0x40014000u)
4185/** Peripheral EEPROM base pointer */
4186#define EEPROM ((EEPROM_Type *)EEPROM_BASE)
4187/** Array initializer of EEPROM peripheral base addresses */
4188#define EEPROM_BASE_ADDRS { EEPROM_BASE }
4189/** Array initializer of EEPROM peripheral base pointers */
4190#define EEPROM_BASE_PTRS { EEPROM }
4191/** Interrupt vectors for the EEPROM peripheral type */
4192#define EEPROM_IRQS { EEPROM_IRQn }
4193
4194/*!
4195 * @}
4196 */ /* end of group EEPROM_Peripheral_Access_Layer */
4197
4198
4199/* ----------------------------------------------------------------------------
4200 -- EMC Peripheral Access Layer
4201 ---------------------------------------------------------------------------- */
4202
4203/*!
4204 * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer
4205 * @{
4206 */
4207
4208/** EMC - Register Layout Typedef */
4209typedef struct {
4210 __IO uint32_t CONTROL; /**< Controls operation of the memory controller, offset: 0x0 */
4211 __I uint32_t STATUS; /**< Provides EMC status information, offset: 0x4 */
4212 __IO uint32_t CONFIG; /**< Configures operation of the memory controller, offset: 0x8 */
4213 uint8_t RESERVED_0[20];
4214 __IO uint32_t DYNAMICCONTROL; /**< Controls dynamic memory operation, offset: 0x20 */
4215 __IO uint32_t DYNAMICREFRESH; /**< Configures dynamic memory refresh, offset: 0x24 */
4216 __IO uint32_t DYNAMICREADCONFIG; /**< Configures dynamic memory read strategy, offset: 0x28 */
4217 uint8_t RESERVED_1[4];
4218 __IO uint32_t DYNAMICRP; /**< Precharge command period, offset: 0x30 */
4219 __IO uint32_t DYNAMICRAS; /**< Active to precharge command period, offset: 0x34 */
4220 __IO uint32_t DYNAMICSREX; /**< Self-refresh exit time, offset: 0x38 */
4221 __IO uint32_t DYNAMICAPR; /**< Last-data-out to active command time, offset: 0x3C */
4222 __IO uint32_t DYNAMICDAL; /**< Data-in to active command time, offset: 0x40 */
4223 __IO uint32_t DYNAMICWR; /**< Write recovery time, offset: 0x44 */
4224 __IO uint32_t DYNAMICRC; /**< Selects the active to active command period, offset: 0x48 */
4225 __IO uint32_t DYNAMICRFC; /**< Selects the auto-refresh period, offset: 0x4C */
4226 __IO uint32_t DYNAMICXSR; /**< Time for exit self-refresh to active command, offset: 0x50 */
4227 __IO uint32_t DYNAMICRRD; /**< Latency for active bank A to active bank B, offset: 0x54 */
4228 __IO uint32_t DYNAMICMRD; /**< Time for load mode register to active command, offset: 0x58 */
4229 uint8_t RESERVED_2[36];
4230 __IO uint32_t STATICEXTENDEDWAIT; /**< Time for long static memory read and write transfers, offset: 0x80 */
4231 uint8_t RESERVED_3[124];
4232 struct { /* offset: 0x100, array step: 0x20 */
4233 __IO uint32_t DYNAMICCONFIG; /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */
4234 __IO uint32_t DYNAMICRASCAS; /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */
4235 uint8_t RESERVED_0[24];
4236 } DYNAMIC[4];
4237 uint8_t RESERVED_4[128];
4238 struct { /* offset: 0x200, array step: 0x20 */
4239 __IO uint32_t STATICCONFIG; /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */
4240 __IO uint32_t STATICWAITWEN; /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */
4241 __IO uint32_t STATICWAITOEN; /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */
4242 __IO uint32_t STATICWAITRD; /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */
4243 __IO uint32_t STATICWAITPAGE; /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */
4244 __IO uint32_t STATICWAITWR; /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */
4245 __IO uint32_t STATICWAITTURN; /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */
4246 uint8_t RESERVED_0[4];
4247 } STATIC[4];
4248} EMC_Type;
4249
4250/* ----------------------------------------------------------------------------
4251 -- EMC Register Masks
4252 ---------------------------------------------------------------------------- */
4253
4254/*!
4255 * @addtogroup EMC_Register_Masks EMC Register Masks
4256 * @{
4257 */
4258
4259/*! @name CONTROL - Controls operation of the memory controller */
4260/*! @{ */
4261#define EMC_CONTROL_E_MASK (0x1U)
4262#define EMC_CONTROL_E_SHIFT (0U)
4263/*! E - EMC Enable.
4264 */
4265#define EMC_CONTROL_E(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK)
4266#define EMC_CONTROL_M_MASK (0x2U)
4267#define EMC_CONTROL_M_SHIFT (1U)
4268/*! M - Address mirror.
4269 */
4270#define EMC_CONTROL_M(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK)
4271#define EMC_CONTROL_L_MASK (0x4U)
4272#define EMC_CONTROL_L_SHIFT (2U)
4273/*! L - Low-power mode.
4274 */
4275#define EMC_CONTROL_L(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK)
4276/*! @} */
4277
4278/*! @name STATUS - Provides EMC status information */
4279/*! @{ */
4280#define EMC_STATUS_B_MASK (0x1U)
4281#define EMC_STATUS_B_SHIFT (0U)
4282/*! B - Busy.
4283 */
4284#define EMC_STATUS_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK)
4285#define EMC_STATUS_S_MASK (0x2U)
4286#define EMC_STATUS_S_SHIFT (1U)
4287/*! S - Write buffer status.
4288 */
4289#define EMC_STATUS_S(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK)
4290#define EMC_STATUS_SA_MASK (0x4U)
4291#define EMC_STATUS_SA_SHIFT (2U)
4292/*! SA - Self-refresh acknowledge.
4293 */
4294#define EMC_STATUS_SA(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK)
4295/*! @} */
4296
4297/*! @name CONFIG - Configures operation of the memory controller */
4298/*! @{ */
4299#define EMC_CONFIG_EM_MASK (0x1U)
4300#define EMC_CONFIG_EM_SHIFT (0U)
4301/*! EM - Endian mode.
4302 */
4303#define EMC_CONFIG_EM(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK)
4304#define EMC_CONFIG_CLKR_MASK (0x100U)
4305#define EMC_CONFIG_CLKR_SHIFT (8U)
4306/*! CLKR - This bit must contain 0 for proper operation of the EMC.
4307 */
4308#define EMC_CONFIG_CLKR(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK)
4309/*! @} */
4310
4311/*! @name DYNAMICCONTROL - Controls dynamic memory operation */
4312/*! @{ */
4313#define EMC_DYNAMICCONTROL_CE_MASK (0x1U)
4314#define EMC_DYNAMICCONTROL_CE_SHIFT (0U)
4315/*! CE - Dynamic memory clock enable.
4316 */
4317#define EMC_DYNAMICCONTROL_CE(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK)
4318#define EMC_DYNAMICCONTROL_CS_MASK (0x2U)
4319#define EMC_DYNAMICCONTROL_CS_SHIFT (1U)
4320/*! CS - Dynamic memory clock control.
4321 */
4322#define EMC_DYNAMICCONTROL_CS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK)
4323#define EMC_DYNAMICCONTROL_SR_MASK (0x4U)
4324#define EMC_DYNAMICCONTROL_SR_SHIFT (2U)
4325/*! SR - Self-refresh request, EMCSREFREQ.
4326 */
4327#define EMC_DYNAMICCONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK)
4328#define EMC_DYNAMICCONTROL_MMC_MASK (0x20U)
4329#define EMC_DYNAMICCONTROL_MMC_SHIFT (5U)
4330/*! MMC - Memory clock control.
4331 */
4332#define EMC_DYNAMICCONTROL_MMC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK)
4333#define EMC_DYNAMICCONTROL_I_MASK (0x180U)
4334#define EMC_DYNAMICCONTROL_I_SHIFT (7U)
4335/*! I - SDRAM initialization.
4336 */
4337#define EMC_DYNAMICCONTROL_I(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK)
4338/*! @} */
4339
4340/*! @name DYNAMICREFRESH - Configures dynamic memory refresh */
4341/*! @{ */
4342#define EMC_DYNAMICREFRESH_REFRESH_MASK (0x7FFU)
4343#define EMC_DYNAMICREFRESH_REFRESH_SHIFT (0U)
4344/*! REFRESH - Refresh timer.
4345 */
4346#define EMC_DYNAMICREFRESH_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK)
4347/*! @} */
4348
4349/*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */
4350/*! @{ */
4351#define EMC_DYNAMICREADCONFIG_RD_MASK (0x3U)
4352#define EMC_DYNAMICREADCONFIG_RD_SHIFT (0U)
4353/*! RD - Read data strategy.
4354 */
4355#define EMC_DYNAMICREADCONFIG_RD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK)
4356/*! @} */
4357
4358/*! @name DYNAMICRP - Precharge command period */
4359/*! @{ */
4360#define EMC_DYNAMICRP_TRP_MASK (0xFU)
4361#define EMC_DYNAMICRP_TRP_SHIFT (0U)
4362/*! TRP - Precharge command period.
4363 */
4364#define EMC_DYNAMICRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK)
4365/*! @} */
4366
4367/*! @name DYNAMICRAS - Active to precharge command period */
4368/*! @{ */
4369#define EMC_DYNAMICRAS_TRAS_MASK (0xFU)
4370#define EMC_DYNAMICRAS_TRAS_SHIFT (0U)
4371/*! TRAS - Active to precharge command period.
4372 */
4373#define EMC_DYNAMICRAS_TRAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK)
4374/*! @} */
4375
4376/*! @name DYNAMICSREX - Self-refresh exit time */
4377/*! @{ */
4378#define EMC_DYNAMICSREX_TSREX_MASK (0xFU)
4379#define EMC_DYNAMICSREX_TSREX_SHIFT (0U)
4380/*! TSREX - Self-refresh exit time.
4381 */
4382#define EMC_DYNAMICSREX_TSREX(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK)
4383/*! @} */
4384
4385/*! @name DYNAMICAPR - Last-data-out to active command time */
4386/*! @{ */
4387#define EMC_DYNAMICAPR_TAPR_MASK (0xFU)
4388#define EMC_DYNAMICAPR_TAPR_SHIFT (0U)
4389/*! TAPR - Last-data-out to active command time.
4390 */
4391#define EMC_DYNAMICAPR_TAPR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK)
4392/*! @} */
4393
4394/*! @name DYNAMICDAL - Data-in to active command time */
4395/*! @{ */
4396#define EMC_DYNAMICDAL_TDAL_MASK (0xFU)
4397#define EMC_DYNAMICDAL_TDAL_SHIFT (0U)
4398/*! TDAL - Data-in to active command.
4399 */
4400#define EMC_DYNAMICDAL_TDAL(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK)
4401/*! @} */
4402
4403/*! @name DYNAMICWR - Write recovery time */
4404/*! @{ */
4405#define EMC_DYNAMICWR_TWR_MASK (0xFU)
4406#define EMC_DYNAMICWR_TWR_SHIFT (0U)
4407/*! TWR - Write recovery time.
4408 */
4409#define EMC_DYNAMICWR_TWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK)
4410/*! @} */
4411
4412/*! @name DYNAMICRC - Selects the active to active command period */
4413/*! @{ */
4414#define EMC_DYNAMICRC_TRC_MASK (0x1FU)
4415#define EMC_DYNAMICRC_TRC_SHIFT (0U)
4416/*! TRC - Active to active command period.
4417 */
4418#define EMC_DYNAMICRC_TRC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK)
4419/*! @} */
4420
4421/*! @name DYNAMICRFC - Selects the auto-refresh period */
4422/*! @{ */
4423#define EMC_DYNAMICRFC_TRFC_MASK (0x1FU)
4424#define EMC_DYNAMICRFC_TRFC_SHIFT (0U)
4425/*! TRFC - Auto-refresh period and auto-refresh to active command period.
4426 */
4427#define EMC_DYNAMICRFC_TRFC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK)
4428/*! @} */
4429
4430/*! @name DYNAMICXSR - Time for exit self-refresh to active command */
4431/*! @{ */
4432#define EMC_DYNAMICXSR_TXSR_MASK (0x1FU)
4433#define EMC_DYNAMICXSR_TXSR_SHIFT (0U)
4434/*! TXSR - Exit self-refresh to active command time.
4435 */
4436#define EMC_DYNAMICXSR_TXSR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK)
4437/*! @} */
4438
4439/*! @name DYNAMICRRD - Latency for active bank A to active bank B */
4440/*! @{ */
4441#define EMC_DYNAMICRRD_TRRD_MASK (0xFU)
4442#define EMC_DYNAMICRRD_TRRD_SHIFT (0U)
4443/*! TRRD - Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles.
4444 */
4445#define EMC_DYNAMICRRD_TRRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK)
4446/*! @} */
4447
4448/*! @name DYNAMICMRD - Time for load mode register to active command */
4449/*! @{ */
4450#define EMC_DYNAMICMRD_TMRD_MASK (0xFU)
4451#define EMC_DYNAMICMRD_TMRD_SHIFT (0U)
4452/*! TMRD - Load mode register to active command time.
4453 */
4454#define EMC_DYNAMICMRD_TMRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK)
4455/*! @} */
4456
4457/*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */
4458/*! @{ */
4459#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU)
4460#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U)
4461/*! EXTENDEDWAIT - Extended wait time out.
4462 */
4463#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK)
4464/*! @} */
4465
4466/*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */
4467/*! @{ */
4468#define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK (0x18U)
4469#define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT (3U)
4470/*! MD - Memory device.
4471 */
4472#define EMC_DYNAMIC_DYNAMICCONFIG_MD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK)
4473#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK (0x1F80U)
4474#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT (7U)
4475/*! AM0 - See Table 933.
4476 */
4477#define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK)
4478#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK (0x4000U)
4479#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT (14U)
4480/*! AM1 - See Table 933.
4481 */
4482#define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
4483#define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK (0x80000U)
4484#define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT (19U)
4485/*! B - Buffer enable.
4486 */
4487#define EMC_DYNAMIC_DYNAMICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK)
4488#define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK (0x100000U)
4489#define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT (20U)
4490/*! P - Write protect.
4491 */
4492#define EMC_DYNAMIC_DYNAMICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK)
4493/*! @} */
4494
4495/* The count of EMC_DYNAMIC_DYNAMICCONFIG */
4496#define EMC_DYNAMIC_DYNAMICCONFIG_COUNT (4U)
4497
4498/*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */
4499/*! @{ */
4500#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK (0x3U)
4501#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT (0U)
4502/*! RAS - RAS latency (active to read/write delay).
4503 */
4504#define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK)
4505#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK (0x300U)
4506#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT (8U)
4507/*! CAS - CAS latency.
4508 */
4509#define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK)
4510/*! @} */
4511
4512/* The count of EMC_DYNAMIC_DYNAMICRASCAS */
4513#define EMC_DYNAMIC_DYNAMICRASCAS_COUNT (4U)
4514
4515/*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */
4516/*! @{ */
4517#define EMC_STATIC_STATICCONFIG_MW_MASK (0x3U)
4518#define EMC_STATIC_STATICCONFIG_MW_SHIFT (0U)
4519/*! MW - Memory width.
4520 */
4521#define EMC_STATIC_STATICCONFIG_MW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK)
4522#define EMC_STATIC_STATICCONFIG_PM_MASK (0x8U)
4523#define EMC_STATIC_STATICCONFIG_PM_SHIFT (3U)
4524/*! PM - Page mode.
4525 */
4526#define EMC_STATIC_STATICCONFIG_PM(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK)
4527#define EMC_STATIC_STATICCONFIG_PC_MASK (0x40U)
4528#define EMC_STATIC_STATICCONFIG_PC_SHIFT (6U)
4529/*! PC - Chip select polarity.
4530 */
4531#define EMC_STATIC_STATICCONFIG_PC(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK)
4532#define EMC_STATIC_STATICCONFIG_PB_MASK (0x80U)
4533#define EMC_STATIC_STATICCONFIG_PB_SHIFT (7U)
4534/*! PB - Byte lane state.
4535 */
4536#define EMC_STATIC_STATICCONFIG_PB(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK)
4537#define EMC_STATIC_STATICCONFIG_EW_MASK (0x100U)
4538#define EMC_STATIC_STATICCONFIG_EW_SHIFT (8U)
4539/*! EW - Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write
4540 * transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.
4541 */
4542#define EMC_STATIC_STATICCONFIG_EW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK)
4543#define EMC_STATIC_STATICCONFIG_B_MASK (0x80000U)
4544#define EMC_STATIC_STATICCONFIG_B_SHIFT (19U)
4545/*! B - Buffer enable [2].
4546 */
4547#define EMC_STATIC_STATICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK)
4548#define EMC_STATIC_STATICCONFIG_P_MASK (0x100000U)
4549#define EMC_STATIC_STATICCONFIG_P_SHIFT (20U)
4550/*! P - Write protect.
4551 */
4552#define EMC_STATIC_STATICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK)
4553/*! @} */
4554
4555/* The count of EMC_STATIC_STATICCONFIG */
4556#define EMC_STATIC_STATICCONFIG_COUNT (4U)
4557
4558/*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */
4559/*! @{ */
4560#define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK (0xFU)
4561#define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT (0U)
4562/*! WAITWEN - Wait write enable.
4563 */
4564#define EMC_STATIC_STATICWAITWEN_WAITWEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK)
4565/*! @} */
4566
4567/* The count of EMC_STATIC_STATICWAITWEN */
4568#define EMC_STATIC_STATICWAITWEN_COUNT (4U)
4569
4570/*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */
4571/*! @{ */
4572#define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK (0xFU)
4573#define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT (0U)
4574/*! WAITOEN - Wait output enable.
4575 */
4576#define EMC_STATIC_STATICWAITOEN_WAITOEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK)
4577/*! @} */
4578
4579/* The count of EMC_STATIC_STATICWAITOEN */
4580#define EMC_STATIC_STATICWAITOEN_COUNT (4U)
4581
4582/*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */
4583/*! @{ */
4584#define EMC_STATIC_STATICWAITRD_WAITRD_MASK (0x1FU)
4585#define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT (0U)
4586/*! WAITRD - .
4587 */
4588#define EMC_STATIC_STATICWAITRD_WAITRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK)
4589/*! @} */
4590
4591/* The count of EMC_STATIC_STATICWAITRD */
4592#define EMC_STATIC_STATICWAITRD_COUNT (4U)
4593
4594/*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */
4595/*! @{ */
4596#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK (0x1FU)
4597#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U)
4598/*! WAITPAGE - Asynchronous page mode read after the first read wait states.
4599 */
4600#define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK)
4601/*! @} */
4602
4603/* The count of EMC_STATIC_STATICWAITPAGE */
4604#define EMC_STATIC_STATICWAITPAGE_COUNT (4U)
4605
4606/*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */
4607/*! @{ */
4608#define EMC_STATIC_STATICWAITWR_WAITWR_MASK (0x1FU)
4609#define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT (0U)
4610/*! WAITWR - Write wait states.
4611 */
4612#define EMC_STATIC_STATICWAITWR_WAITWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK)
4613/*! @} */
4614
4615/* The count of EMC_STATIC_STATICWAITWR */
4616#define EMC_STATIC_STATICWAITWR_COUNT (4U)
4617
4618/*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */
4619/*! @{ */
4620#define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK (0xFU)
4621#define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U)
4622/*! WAITTURN - Bus turn-around cycles.
4623 */
4624#define EMC_STATIC_STATICWAITTURN_WAITTURN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK)
4625/*! @} */
4626
4627/* The count of EMC_STATIC_STATICWAITTURN */
4628#define EMC_STATIC_STATICWAITTURN_COUNT (4U)
4629
4630
4631/*!
4632 * @}
4633 */ /* end of group EMC_Register_Masks */
4634
4635
4636/* EMC - Peripheral instance base addresses */
4637/** Peripheral EMC base address */
4638#define EMC_BASE (0x40081000u)
4639/** Peripheral EMC base pointer */
4640#define EMC ((EMC_Type *)EMC_BASE)
4641/** Array initializer of EMC peripheral base addresses */
4642#define EMC_BASE_ADDRS { EMC_BASE }
4643/** Array initializer of EMC peripheral base pointers */
4644#define EMC_BASE_PTRS { EMC }
4645
4646/*!
4647 * @}
4648 */ /* end of group EMC_Peripheral_Access_Layer */
4649
4650
4651/* ----------------------------------------------------------------------------
4652 -- ENET Peripheral Access Layer
4653 ---------------------------------------------------------------------------- */
4654
4655/*!
4656 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
4657 * @{
4658 */
4659
4660/** ENET - Register Layout Typedef */
4661typedef struct {
4662 __IO uint32_t MAC_CONFIG; /**< MAC configuration register, offset: 0x0 */
4663 __IO uint32_t MAC_EXT_CONFIG; /**< , offset: 0x4 */
4664 __IO uint32_t MAC_FRAME_FILTER; /**< MAC frame filter register, offset: 0x8 */
4665 __IO uint32_t MAC_WD_TIMEROUT; /**< MAC watchdog Timeout register, offset: 0xC */
4666 uint8_t RESERVED_0[64];
4667 __IO uint32_t MAC_VLAN_TAG; /**< MAC vlan tag register, offset: 0x50 */
4668 uint8_t RESERVED_1[28];
4669 __IO uint32_t MAC_TX_FLOW_CTRL_Q[2]; /**< Transmit flow control register, array offset: 0x70, array step: 0x4 */
4670 uint8_t RESERVED_2[24];
4671 __IO uint32_t MAC_RX_FLOW_CTRL; /**< Receive flow control register, offset: 0x90 */
4672 uint8_t RESERVED_3[4];
4673 __IO uint32_t MAC_TXQ_PRIO_MAP; /**< , offset: 0x98 */
4674 uint8_t RESERVED_4[4];
4675 __IO uint32_t MAC_RXQ_CTRL[3]; /**< Receive Queue Control 0 register 0x0000, array offset: 0xA0, array step: 0x4 */
4676 uint8_t RESERVED_5[4];
4677 __I uint32_t MAC_INTR_STAT; /**< Interrupt status register 0x0000, offset: 0xB0 */
4678 __IO uint32_t MAC_INTR_EN; /**< Interrupt enable register 0x0000, offset: 0xB4 */
4679 __I uint32_t MAC_RXTX_STAT; /**< Receive Transmit Status register, offset: 0xB8 */
4680 uint8_t RESERVED_6[4];
4681 __IO uint32_t MAC_PMT_CRTL_STAT; /**< , offset: 0xC0 */
4682 __IO uint32_t MAC_RWAKE_FRFLT; /**< Remote wake-up frame filter, offset: 0xC4 */
4683 uint8_t RESERVED_7[8];
4684 __IO uint32_t MAC_LPI_CTRL_STAT; /**< LPI Control and Status Register, offset: 0xD0 */
4685 __IO uint32_t MAC_LPI_TIMER_CTRL; /**< LPI Timers Control register, offset: 0xD4 */
4686 __IO uint32_t MAC_LPI_ENTR_TIMR; /**< LPI entry Timer register, offset: 0xD8 */
4687 __IO uint32_t MAC_1US_TIC_COUNTR; /**< , offset: 0xDC */
4688 uint8_t RESERVED_8[48];
4689 __IO uint32_t MAC_VERSION; /**< MAC version register, offset: 0x110 */
4690 __I uint32_t MAC_DBG; /**< MAC debug register, offset: 0x114 */
4691 uint8_t RESERVED_9[4];
4692 __IO uint32_t MAC_HW_FEAT[3]; /**< MAC hardware feature register 0x0201, array offset: 0x11C, array step: 0x4 */
4693 uint8_t RESERVED_10[216];
4694 __IO uint32_t MAC_MDIO_ADDR; /**< MIDO address Register, offset: 0x200 */
4695 __IO uint32_t MAC_MDIO_DATA; /**< MDIO Data register, offset: 0x204 */
4696 uint8_t RESERVED_11[248];
4697 __IO uint32_t MAC_ADDR_HIGH; /**< MAC address0 high register, offset: 0x300 */
4698 __IO uint32_t MAC_ADDR_LOW; /**< MAC address0 low register, offset: 0x304 */
4699 uint8_t RESERVED_12[2040];
4700 __IO uint32_t MAC_TIMESTAMP_CTRL; /**< Time stamp control register, offset: 0xB00 */
4701 __IO uint32_t MAC_SUB_SCND_INCR; /**< Sub-second increment register, offset: 0xB04 */
4702 __I uint32_t MAC_SYS_TIME_SCND; /**< System time seconds register, offset: 0xB08 */
4703 __I uint32_t MAC_SYS_TIME_NSCND; /**< System time nanoseconds register, offset: 0xB0C */
4704 __IO uint32_t MAC_SYS_TIME_SCND_UPD; /**< , offset: 0xB10 */
4705 __IO uint32_t MAC_SYS_TIME_NSCND_UPD; /**< , offset: 0xB14 */
4706 __IO uint32_t MAC_SYS_TIMESTMP_ADDEND; /**< Time stamp addend register, offset: 0xB18 */
4707 __IO uint32_t MAC_SYS_TIME_HWORD_SCND; /**< , offset: 0xB1C */
4708 __I uint32_t MAC_SYS_TIMESTMP_STAT; /**< Time stamp status register, offset: 0xB20 */
4709 uint8_t RESERVED_13[12];
4710 __I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Tx timestamp status nanoseconds, offset: 0xB30 */
4711 __I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< Tx timestamp status seconds, offset: 0xB34 */
4712 uint8_t RESERVED_14[32];
4713 __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp ingress correction, offset: 0xB58 */
4714 __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp egress correction, offset: 0xB5C */
4715 uint8_t RESERVED_15[160];
4716 __IO uint32_t MTL_OP_MODE; /**< MTL Operation Mode Register, offset: 0xC00 */
4717 uint8_t RESERVED_16[28];
4718 __I uint32_t MTL_INTR_STAT; /**< MTL Interrupt Status register, offset: 0xC20 */
4719 uint8_t RESERVED_17[12];
4720 __IO uint32_t MTL_RXQ_DMA_MAP; /**< MTL Receive Queue and DMA Channel Mapping register, offset: 0xC30 */
4721 uint8_t RESERVED_18[204];
4722 struct { /* offset: 0xD00, array step: 0x40 */
4723 __IO uint32_t MTL_TXQX_OP_MODE; /**< MTL TxQx Operation Mode register, array offset: 0xD00, array step: 0x40 */
4724 __I uint32_t MTL_TXQX_UNDRFLW; /**< MTL TxQx Underflow register, array offset: 0xD04, array step: 0x40 */
4725 __I uint32_t MTL_TXQX_DBG; /**< MTL TxQx Debug register, array offset: 0xD08, array step: 0x40 */
4726 uint8_t RESERVED_0[4];
4727 __IO uint32_t MTL_TXQX_ETS_CTRL; /**< MTL TxQx ETS control register, only TxQ1 support, array offset: 0xD10, array step: 0x40 */
4728 __IO uint32_t MTL_TXQX_ETS_STAT; /**< MTL TxQx ETS Status register, array offset: 0xD14, array step: 0x40 */
4729 __IO uint32_t MTL_TXQX_QNTM_WGHT; /**< , array offset: 0xD18, array step: 0x40 */
4730 __IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< MTL TxQx SendSlopCredit register, only TxQ1 support, array offset: 0xD1C, array step: 0x40 */
4731 __IO uint32_t MTL_TXQX_HI_CRDT; /**< MTL TxQx hiCredit register, only TxQ1 support, array offset: 0xD20, array step: 0x40 */
4732 __IO uint32_t MTL_TXQX_LO_CRDT; /**< MTL TxQx loCredit register, only TxQ1 support, array offset: 0xD24, array step: 0x40 */
4733 uint8_t RESERVED_1[4];
4734 __IO uint32_t MTL_TXQX_INTCTRL_STAT; /**< , array offset: 0xD2C, array step: 0x40 */
4735 __IO uint32_t MTL_RXQX_OP_MODE; /**< MTL RxQx Operation Mode register, array offset: 0xD30, array step: 0x40 */
4736 __IO uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< MTL RxQx Missed Packet Overflow Counter register, array offset: 0xD34, array step: 0x40 */
4737 __IO uint32_t MTL_RXQX_DBG; /**< MTL RxQx Debug register, array offset: 0xD38, array step: 0x40 */
4738 __IO uint32_t MTL_RXQX_CTRL; /**< MTL RxQx Control register, array offset: 0xD3C, array step: 0x40 */
4739 } MTL_QUEUE[2];
4740 uint8_t RESERVED_19[640];
4741 __IO uint32_t DMA_MODE; /**< DMA mode register, offset: 0x1000 */
4742 __IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus mode, offset: 0x1004 */
4743 __IO uint32_t DMA_INTR_STAT; /**< DMA Interrupt status, offset: 0x1008 */
4744 __IO uint32_t DMA_DBG_STAT; /**< DMA Debug Status, offset: 0x100C */
4745 uint8_t RESERVED_20[240];
4746 struct { /* offset: 0x1100, array step: 0x80 */
4747 __IO uint32_t DMA_CHX_CTRL; /**< DMA Channelx Control, array offset: 0x1100, array step: 0x80 */
4748 __IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channelx Transmit Control, array offset: 0x1104, array step: 0x80 */
4749 __IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channelx Receive Control, array offset: 0x1108, array step: 0x80 */
4750 uint8_t RESERVED_0[8];
4751 __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< , array offset: 0x1114, array step: 0x80 */
4752 uint8_t RESERVED_1[4];
4753 __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< , array offset: 0x111C, array step: 0x80 */
4754 __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< , array offset: 0x1120, array step: 0x80 */
4755 uint8_t RESERVED_2[4];
4756 __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< , array offset: 0x1128, array step: 0x80 */
4757 __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< , array offset: 0x112C, array step: 0x80 */
4758 __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH; /**< Channelx Rx descriptor Ring Length, array offset: 0x1130, array step: 0x80 */
4759 __IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1134, array step: 0x80 */
4760 __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
4761 __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
4762 uint8_t RESERVED_3[4];
4763 __I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< Channelx Current Host Transmit descriptor, array offset: 0x1144, array step: 0x80 */
4764 uint8_t RESERVED_4[4];
4765 __I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< , array offset: 0x114C, array step: 0x80 */
4766 uint8_t RESERVED_5[4];
4767 __I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< , array offset: 0x1154, array step: 0x80 */
4768 uint8_t RESERVED_6[4];
4769 __I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< Channelx Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
4770 __IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: 0x1160, array step: 0x80 */
4771 uint8_t RESERVED_7[28];
4772 } DMA_CH[2];
4773} ENET_Type;
4774
4775/* ----------------------------------------------------------------------------
4776 -- ENET Register Masks
4777 ---------------------------------------------------------------------------- */
4778
4779/*!
4780 * @addtogroup ENET_Register_Masks ENET Register Masks
4781 * @{
4782 */
4783
4784/*! @name MAC_CONFIG - MAC configuration register */
4785/*! @{ */
4786#define ENET_MAC_CONFIG_RE_MASK (0x1U)
4787#define ENET_MAC_CONFIG_RE_SHIFT (0U)
4788/*! RE - Receiver Enable When this bit is set, the receiver state machine of the MAC is enabled for
4789 * receiving frames from the MII.
4790 */
4791#define ENET_MAC_CONFIG_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_RE_SHIFT)) & ENET_MAC_CONFIG_RE_MASK)
4792#define ENET_MAC_CONFIG_TE_MASK (0x2U)
4793#define ENET_MAC_CONFIG_TE_SHIFT (1U)
4794/*! TE - Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII.
4795 */
4796#define ENET_MAC_CONFIG_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_TE_SHIFT)) & ENET_MAC_CONFIG_TE_MASK)
4797#define ENET_MAC_CONFIG_PRELEN_MASK (0xCU)
4798#define ENET_MAC_CONFIG_PRELEN_SHIFT (2U)
4799/*! PRELEN - Preamble Length for Transmit packets These bits control the number of preamble bytes
4800 * that are added to the beginning of every Tx packet.
4801 */
4802#define ENET_MAC_CONFIG_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PRELEN_SHIFT)) & ENET_MAC_CONFIG_PRELEN_MASK)
4803#define ENET_MAC_CONFIG_DC_MASK (0x10U)
4804#define ENET_MAC_CONFIG_DC_SHIFT (4U)
4805/*! DC - Deferral Check When this bit is set, the deferral check function is enabled in the MAC.
4806 */
4807#define ENET_MAC_CONFIG_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DC_SHIFT)) & ENET_MAC_CONFIG_DC_MASK)
4808#define ENET_MAC_CONFIG_BL_MASK (0x60U)
4809#define ENET_MAC_CONFIG_BL_SHIFT (5U)
4810/*! BL - Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time
4811 * delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before
4812 * rescheduling a transmission attempt during retries after a collision.
4813 */
4814#define ENET_MAC_CONFIG_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BL_SHIFT)) & ENET_MAC_CONFIG_BL_MASK)
4815#define ENET_MAC_CONFIG_DR_MASK (0x100U)
4816#define ENET_MAC_CONFIG_DR_SHIFT (8U)
4817/*! DR - Disable Retry When this bit is set, the MAC will attempt only one transmission.
4818 */
4819#define ENET_MAC_CONFIG_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DR_SHIFT)) & ENET_MAC_CONFIG_DR_MASK)
4820#define ENET_MAC_CONFIG_DCRS_MASK (0x200U)
4821#define ENET_MAC_CONFIG_DCRS_SHIFT (9U)
4822/*! DCRS - Disable Carrier Sense During Transmission When this bit is set, the MAC transmitter
4823 * ignores the MII CRS signal during packet transmission in the half-duplex mode.
4824 */
4825#define ENET_MAC_CONFIG_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DCRS_SHIFT)) & ENET_MAC_CONFIG_DCRS_MASK)
4826#define ENET_MAC_CONFIG_DO_MASK (0x400U)
4827#define ENET_MAC_CONFIG_DO_SHIFT (10U)
4828/*! DO - Disable Receive Own When this bit is set, the MAC disables the reception of frames when the
4829 * gmii_txen_o is asserted in Half-Duplex mode.
4830 */
4831#define ENET_MAC_CONFIG_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DO_SHIFT)) & ENET_MAC_CONFIG_DO_MASK)
4832#define ENET_MAC_CONFIG_ECRSFD_MASK (0x800U)
4833#define ENET_MAC_CONFIG_ECRSFD_SHIFT (11U)
4834/*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set, the
4835 * MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode.
4836 */
4837#define ENET_MAC_CONFIG_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ECRSFD_SHIFT)) & ENET_MAC_CONFIG_ECRSFD_MASK)
4838#define ENET_MAC_CONFIG_LM_MASK (0x1000U)
4839#define ENET_MAC_CONFIG_LM_SHIFT (12U)
4840/*! LM - Loopback Mode When this bit is set, the MAC operates in loopback mode at MII.
4841 */
4842#define ENET_MAC_CONFIG_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_LM_SHIFT)) & ENET_MAC_CONFIG_LM_MASK)
4843#define ENET_MAC_CONFIG_DM_MASK (0x2000U)
4844#define ENET_MAC_CONFIG_DM_SHIFT (13U)
4845/*! DM - Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can
4846 * transmit and receive simultaneously.
4847 */
4848#define ENET_MAC_CONFIG_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DM_SHIFT)) & ENET_MAC_CONFIG_DM_MASK)
4849#define ENET_MAC_CONFIG_FES_MASK (0x4000U)
4850#define ENET_MAC_CONFIG_FES_SHIFT (14U)
4851/*! FES - Speed Indicates the speed in Fast Ethernet (MII) mode: This bit is reserved (RO) by
4852 * default and is enabled only when RMII/SMII is enabled during configuration.
4853 */
4854#define ENET_MAC_CONFIG_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_FES_SHIFT)) & ENET_MAC_CONFIG_FES_MASK)
4855#define ENET_MAC_CONFIG_PS_MASK (0x8000U)
4856#define ENET_MAC_CONFIG_PS_SHIFT (15U)
4857/*! PS - Portselect.
4858 */
4859#define ENET_MAC_CONFIG_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PS_SHIFT)) & ENET_MAC_CONFIG_PS_MASK)
4860#define ENET_MAC_CONFIG_JE_MASK (0x10000U)
4861#define ENET_MAC_CONFIG_JE_SHIFT (16U)
4862/*! JE - Jumbo Frame Enable When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022
4863 * bytes for tagged frames) without reporting a giant frame error in the receive frame status.
4864 */
4865#define ENET_MAC_CONFIG_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JE_SHIFT)) & ENET_MAC_CONFIG_JE_MASK)
4866#define ENET_MAC_CONFIG_JD_MASK (0x20000U)
4867#define ENET_MAC_CONFIG_JD_SHIFT (17U)
4868/*! JD - Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter,
4869 * and can transfer frames of up to 16,384 bytes.
4870 */
4871#define ENET_MAC_CONFIG_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JD_SHIFT)) & ENET_MAC_CONFIG_JD_MASK)
4872#define ENET_MAC_CONFIG_BE_MASK (0x40000U)
4873#define ENET_MAC_CONFIG_BE_SHIFT (18U)
4874/*! BE - Packet Burst Enable When this bit is set, the MAC allows packet bursting during
4875 * transmission in the MII half-duplex mode.
4876 */
4877#define ENET_MAC_CONFIG_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BE_SHIFT)) & ENET_MAC_CONFIG_BE_MASK)
4878#define ENET_MAC_CONFIG_WD_MASK (0x80000U)
4879#define ENET_MAC_CONFIG_WD_SHIFT (19U)
4880/*! WD - Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver,
4881 * and can receive frames of up to 16,384 bytes.
4882 */
4883#define ENET_MAC_CONFIG_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_WD_SHIFT)) & ENET_MAC_CONFIG_WD_MASK)
4884#define ENET_MAC_CONFIG_ACS_MASK (0x100000U)
4885#define ENET_MAC_CONFIG_ACS_SHIFT (20U)
4886/*! ACS - Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field
4887 * on the incoming packets only if the value of the length field is less than 1,536 bytes.
4888 */
4889#define ENET_MAC_CONFIG_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ACS_SHIFT)) & ENET_MAC_CONFIG_ACS_MASK)
4890#define ENET_MAC_CONFIG_CST_MASK (0x200000U)
4891#define ENET_MAC_CONFIG_CST_SHIFT (21U)
4892/*! CST - CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all
4893 * packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding
4894 * the packet to the application.
4895 */
4896#define ENET_MAC_CONFIG_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_CST_SHIFT)) & ENET_MAC_CONFIG_CST_MASK)
4897#define ENET_MAC_CONFIG_S2KP_MASK (0x400000U)
4898#define ENET_MAC_CONFIG_S2KP_SHIFT (22U)
4899/*! S2KP - IEEE 802.
4900 */
4901#define ENET_MAC_CONFIG_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_S2KP_SHIFT)) & ENET_MAC_CONFIG_S2KP_MASK)
4902#define ENET_MAC_CONFIG_GPSLCE_MASK (0x800000U)
4903#define ENET_MAC_CONFIG_GPSLCE_SHIFT (23U)
4904/*! GPSLCE - Giant Packet Size Limit Control Enable When this bit is set, the MAC considers the
4905 * value in GPSL field in MAC Ext Configuration register to declare a received packet as Giant packet.
4906 */
4907#define ENET_MAC_CONFIG_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_GPSLCE_SHIFT)) & ENET_MAC_CONFIG_GPSLCE_MASK)
4908#define ENET_MAC_CONFIG_IPG_MASK (0x7000000U)
4909#define ENET_MAC_CONFIG_IPG_SHIFT (24U)
4910/*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission.
4911 */
4912#define ENET_MAC_CONFIG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPG_SHIFT)) & ENET_MAC_CONFIG_IPG_MASK)
4913#define ENET_MAC_CONFIG_IPC_MASK (0x8000000U)
4914#define ENET_MAC_CONFIG_IPC_SHIFT (27U)
4915/*! IPC - Checksum Offload When set, this bit enables the IPv4 header checksum checking and IPv4 or
4916 * IPv6 TCP, UDP, or ICMP payload checksum checking.
4917 */
4918#define ENET_MAC_CONFIG_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPC_SHIFT)) & ENET_MAC_CONFIG_IPC_MASK)
4919/*! @} */
4920
4921/*! @name MAC_EXT_CONFIG - */
4922/*! @{ */
4923#define ENET_MAC_EXT_CONFIG_GPSL_MASK (0x3FFFU)
4924#define ENET_MAC_EXT_CONFIG_GPSL_SHIFT (0U)
4925/*! GPSL - Giant Packet Size Limit If the received packet size is greater than the value programmed
4926 * in this field in units of bytes, the MAC declares the received packet as Giant packet.
4927 */
4928#define ENET_MAC_EXT_CONFIG_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIG_GPSL_MASK)
4929#define ENET_MAC_EXT_CONFIG_DCRCC_MASK (0x10000U)
4930#define ENET_MAC_EXT_CONFIG_DCRCC_SHIFT (16U)
4931/*! DCRCC - Disable CRC Checking for Received Packets When this bit is set, the MAC receiver does
4932 * not check the CRC field in the received packets.
4933 */
4934#define ENET_MAC_EXT_CONFIG_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIG_DCRCC_MASK)
4935#define ENET_MAC_EXT_CONFIG_SPEN_MASK (0x20000U)
4936#define ENET_MAC_EXT_CONFIG_SPEN_SHIFT (17U)
4937/*! SPEN - Slow Protocol Detection Enable When this bit is set, MAC processes the Slow Protocol
4938 * packets (Ether Type 0x8809) and provides the Rx status.
4939 */
4940#define ENET_MAC_EXT_CONFIG_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIG_SPEN_MASK)
4941#define ENET_MAC_EXT_CONFIG_USP_MASK (0x40000U)
4942#define ENET_MAC_EXT_CONFIG_USP_SHIFT (18U)
4943/*! USP - Unicast Slow Protocol Packet Detect When this bit is set, the MAC detects the Slow
4944 * Protocol packets with unicast address of the station specified in the MAC Address High Table 747 and
4945 * MAC Address Low Table 748 registers.
4946 */
4947#define ENET_MAC_EXT_CONFIG_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_USP_SHIFT)) & ENET_MAC_EXT_CONFIG_USP_MASK)
4948/*! @} */
4949
4950/*! @name MAC_FRAME_FILTER - MAC frame filter register */
4951/*! @{ */
4952#define ENET_MAC_FRAME_FILTER_PR_MASK (0x1U)
4953#define ENET_MAC_FRAME_FILTER_PR_SHIFT (0U)
4954/*! PR - Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frames
4955 * regardless of its destination or source address.
4956 */
4957#define ENET_MAC_FRAME_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PR_SHIFT)) & ENET_MAC_FRAME_FILTER_PR_MASK)
4958#define ENET_MAC_FRAME_FILTER_DAIF_MASK (0x8U)
4959#define ENET_MAC_FRAME_FILTER_DAIF_SHIFT (3U)
4960/*! DAIF - DA Inverse Filtering When this bit is set, the Address Check block operates in inverse
4961 * filtering mode for the DA address comparison for both unicast and multicast frames.
4962 */
4963#define ENET_MAC_FRAME_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_DAIF_MASK)
4964#define ENET_MAC_FRAME_FILTER_PM_MASK (0x10U)
4965#define ENET_MAC_FRAME_FILTER_PM_SHIFT (4U)
4966/*! PM - Pass All Multicast When set, this bit indicates that all received frames with a multicast
4967 * destination address (first bit in the destination address field is '1') are passed.
4968 */
4969#define ENET_MAC_FRAME_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PM_SHIFT)) & ENET_MAC_FRAME_FILTER_PM_MASK)
4970#define ENET_MAC_FRAME_FILTER_DBF_MASK (0x20U)
4971#define ENET_MAC_FRAME_FILTER_DBF_SHIFT (5U)
4972/*! DBF - Disable Broadcast Frames When this bit is set, the AFM module filters all incoming broadcast frames.
4973 */
4974#define ENET_MAC_FRAME_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DBF_SHIFT)) & ENET_MAC_FRAME_FILTER_DBF_MASK)
4975#define ENET_MAC_FRAME_FILTER_PCF_MASK (0xC0U)
4976#define ENET_MAC_FRAME_FILTER_PCF_SHIFT (6U)
4977/*! PCF - Pass Control Frames These bits control the forwarding of all control frames (including
4978 * unicast and multicast PAUSE frames).
4979 */
4980#define ENET_MAC_FRAME_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PCF_SHIFT)) & ENET_MAC_FRAME_FILTER_PCF_MASK)
4981#define ENET_MAC_FRAME_FILTER_SAIF_MASK (0x100U)
4982#define ENET_MAC_FRAME_FILTER_SAIF_SHIFT (8U)
4983/*! SAIF - SA Inverse Filtering When this bit is set, the Address Check block operates in the
4984 * inverse filtering mode for SA address comparison.
4985 */
4986#define ENET_MAC_FRAME_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAIF_MASK)
4987#define ENET_MAC_FRAME_FILTER_SAF_MASK (0x200U)
4988#define ENET_MAC_FRAME_FILTER_SAF_SHIFT (9U)
4989/*! SAF - Source Address Filter Enable When this bit is set, the MAC compares the SA field of the
4990 * received packets with the values programmed in the enabled SA registers.
4991 */
4992#define ENET_MAC_FRAME_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAF_MASK)
4993#define ENET_MAC_FRAME_FILTER_RA_MASK (0x80000000U)
4994#define ENET_MAC_FRAME_FILTER_RA_SHIFT (31U)
4995/*! RA - Receive all When this bit is set, the MAC Receiver module passes to the Application all
4996 * frames received irrespective of whether they pass the address filter.
4997 */
4998#define ENET_MAC_FRAME_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_RA_SHIFT)) & ENET_MAC_FRAME_FILTER_RA_MASK)
4999/*! @} */
5000
5001/*! @name MAC_WD_TIMEROUT - MAC watchdog Timeout register */
5002/*! @{ */
5003#define ENET_MAC_WD_TIMEROUT_WTO_MASK (0xFU)
5004#define ENET_MAC_WD_TIMEROUT_WTO_SHIFT (0U)
5005/*! WTO - Watchdog Timeout When the PWE bit is set and the WD bit of the MAC Configuration register
5006 * Table 722 is reset, this field is used as watchdog timeout for a received packet.
5007 */
5008#define ENET_MAC_WD_TIMEROUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_WTO_SHIFT)) & ENET_MAC_WD_TIMEROUT_WTO_MASK)
5009#define ENET_MAC_WD_TIMEROUT_PWE_MASK (0x100U)
5010#define ENET_MAC_WD_TIMEROUT_PWE_SHIFT (8U)
5011/*! PWE - Programmable Watchdog Enable When this bit is set and the WD bit of the MAC Configuration
5012 * register Table 722 is reset, the WTO field is used as watchdog timeout for a received packet.
5013 */
5014#define ENET_MAC_WD_TIMEROUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_PWE_SHIFT)) & ENET_MAC_WD_TIMEROUT_PWE_MASK)
5015/*! @} */
5016
5017/*! @name MAC_VLAN_TAG - MAC vlan tag register */
5018/*! @{ */
5019#define ENET_MAC_VLAN_TAG_VL_MASK (0xFFFFU)
5020#define ENET_MAC_VLAN_TAG_VL_SHIFT (0U)
5021/*! VL - VLAN Tag Identifier for Receive Packets.
5022 */
5023#define ENET_MAC_VLAN_TAG_VL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VL_SHIFT)) & ENET_MAC_VLAN_TAG_VL_MASK)
5024#define ENET_MAC_VLAN_TAG_ETV_MASK (0x10000U)
5025#define ENET_MAC_VLAN_TAG_ETV_SHIFT (16U)
5026/*! ETV - Enable 12-Bit VLAN Tag Comparison.
5027 */
5028#define ENET_MAC_VLAN_TAG_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_ETV_MASK)
5029#define ENET_MAC_VLAN_TAG_VTIM_MASK (0x20000U)
5030#define ENET_MAC_VLAN_TAG_VTIM_SHIFT (17U)
5031/*! VTIM - VLAN Tag Inverse Match Enable.
5032 */
5033#define ENET_MAC_VLAN_TAG_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_VTIM_MASK)
5034#define ENET_MAC_VLAN_TAG_ESVL_MASK (0x40000U)
5035#define ENET_MAC_VLAN_TAG_ESVL_SHIFT (18U)
5036/*! ESVL - Enable S-VLAN.
5037 */
5038#define ENET_MAC_VLAN_TAG_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_ESVL_MASK)
5039#define ENET_MAC_VLAN_TAG_ERSVLM_MASK (0x80000U)
5040#define ENET_MAC_VLAN_TAG_ERSVLM_SHIFT (19U)
5041/*! ERSVLM - Enable Receive S-VLAN Match.
5042 */
5043#define ENET_MAC_VLAN_TAG_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_ERSVLM_MASK)
5044#define ENET_MAC_VLAN_TAG_DOVLTC_MASK (0x100000U)
5045#define ENET_MAC_VLAN_TAG_DOVLTC_SHIFT (20U)
5046/*! DOVLTC - Disable VLAN Type Check.
5047 */
5048#define ENET_MAC_VLAN_TAG_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_DOVLTC_MASK)
5049#define ENET_MAC_VLAN_TAG_EVLS_MASK (0x600000U)
5050#define ENET_MAC_VLAN_TAG_EVLS_SHIFT (21U)
5051/*! EVLS - Enable VLAN Tag Stripping on Receive.
5052 */
5053#define ENET_MAC_VLAN_TAG_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLS_MASK)
5054#define ENET_MAC_VLAN_TAG_EVLRXS_MASK (0x1000000U)
5055#define ENET_MAC_VLAN_TAG_EVLRXS_SHIFT (24U)
5056/*! EVLRXS - Enable VLAN Tag in Rx status.
5057 */
5058#define ENET_MAC_VLAN_TAG_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLRXS_MASK)
5059#define ENET_MAC_VLAN_TAG_VTHM_MASK (0x2000000U)
5060#define ENET_MAC_VLAN_TAG_VTHM_SHIFT (25U)
5061/*! VTHM - Disable VLAN Type Check.
5062 */
5063#define ENET_MAC_VLAN_TAG_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTHM_SHIFT)) & ENET_MAC_VLAN_TAG_VTHM_MASK)
5064#define ENET_MAC_VLAN_TAG_EDVLP_MASK (0x4000000U)
5065#define ENET_MAC_VLAN_TAG_EDVLP_SHIFT (26U)
5066/*! EDVLP - Enable Double VLAN Processing.
5067 */
5068#define ENET_MAC_VLAN_TAG_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_EDVLP_MASK)
5069#define ENET_MAC_VLAN_TAG_ERIVLT_MASK (0x8000000U)
5070#define ENET_MAC_VLAN_TAG_ERIVLT_SHIFT (27U)
5071/*! ERIVLT - Enable Inner VLAN Tag.
5072 */
5073#define ENET_MAC_VLAN_TAG_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_ERIVLT_MASK)
5074#define ENET_MAC_VLAN_TAG_EIVLS_MASK (0x30000000U)
5075#define ENET_MAC_VLAN_TAG_EIVLS_SHIFT (28U)
5076/*! EIVLS - Enable Inner VLAN Tag Stripping on Receive.
5077 */
5078#define ENET_MAC_VLAN_TAG_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLS_MASK)
5079#define ENET_MAC_VLAN_TAG_EIVLRXS_MASK (0x80000000U)
5080#define ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT (31U)
5081/*! EIVLRXS - Enable Inner VLAN Tag in Rx Status.
5082 */
5083#define ENET_MAC_VLAN_TAG_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLRXS_MASK)
5084/*! @} */
5085
5086/*! @name MAC_TX_FLOW_CTRL_Q - Transmit flow control register */
5087/*! @{ */
5088#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK (0x1U)
5089#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT (0U)
5090/*! FCB - Flow Control Busy/Backpressure Activate This register field can be read by the application
5091 * (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is
5092 * cleared to 0 by the core (Self Clear).
5093 */
5094#define ENET_MAC_TX_FLOW_CTRL_Q_FCB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK)
5095#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U)
5096#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U)
5097/*! TFE - Transmit Flow Control Enable In Full-Duplex mode, when this bit is set, the MAC enables
5098 * the flow control operation to transmit Pause frames.
5099 */
5100#define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
5101#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U)
5102#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U)
5103/*! PLT - Pause Low Threshold This field configures the threshold of the PAUSE timer at which the
5104 * input flow control signal is checked for automatic retransmission of PAUSE Frame.
5105 */
5106#define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
5107#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U)
5108#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U)
5109/*! DZPQ - Disable Zero-Quanta Pause When set, this bit disables the automatic generation of
5110 * Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer.
5111 */
5112#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
5113#define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U)
5114#define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U)
5115/*! PT - Pause time This field holds the value to be used in the Pause Time field in the transmit control frame.
5116 */
5117#define ENET_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK)
5118/*! @} */
5119
5120/* The count of ENET_MAC_TX_FLOW_CTRL_Q */
5121#define ENET_MAC_TX_FLOW_CTRL_Q_COUNT (2U)
5122
5123/*! @name MAC_RX_FLOW_CTRL - Receive flow control register */
5124/*! @{ */
5125#define ENET_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U)
5126#define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U)
5127/*! RFE - Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex
5128 * mode, the MAC decodes the received Pause packet and disables its transmitter for a specified
5129 * (Pause) time.
5130 */
5131#define ENET_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK)
5132#define ENET_MAC_RX_FLOW_CTRL_UP_MASK (0x2U)
5133#define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT (1U)
5134/*! UP - Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast
5135 * address specified in the IEEE 802.
5136 */
5137#define ENET_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK)
5138/*! @} */
5139
5140/*! @name MAC_TXQ_PRIO_MAP - */
5141/*! @{ */
5142#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK (0xFFU)
5143#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT (0U)
5144/*! PSTQ0 - Priorities Selected in Transmit Queue 0 This field holds the priorities assigned to Tx Queue 0 by the software.
5145 */
5146#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK)
5147#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK (0xFF00U)
5148#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT (8U)
5149/*! PSTQ1 - Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit.
5150 */
5151#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK)
5152/*! @} */
5153
5154/*! @name MAC_RXQ_CTRL - Receive Queue Control 0 register 0x0000 */
5155/*! @{ */
5156#define ENET_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U)
5157#define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U)
5158/*! AVCPQ - AV Untagged Control Packets Queue.
5159 */
5160#define ENET_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK)
5161#define ENET_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU)
5162#define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U)
5163/*! PSRQ0 - Priorities Selected in the Receive Queue 0.
5164 */
5165#define ENET_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK)
5166#define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U)
5167#define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U)
5168/*! RXQ0EN - Receive Queue 0 Enable.
5169 */
5170#define ENET_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK)
5171#define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU)
5172#define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U)
5173/*! RXQ1EN - Receive Queue 1 Enable.
5174 */
5175#define ENET_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK)
5176#define ENET_MAC_RXQ_CTRL_AVPTPQ_MASK (0x70U)
5177#define ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT (4U)
5178/*! AVPTPQ - AV PTP Packets Queue.
5179 */
5180#define ENET_MAC_RXQ_CTRL_AVPTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVPTPQ_MASK)
5181#define ENET_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U)
5182#define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U)
5183/*! PSRQ1 - Priorities Selected in the Receive Queue 1.
5184 */
5185#define ENET_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK)
5186#define ENET_MAC_RXQ_CTRL_UPQ_MASK (0x7000U)
5187#define ENET_MAC_RXQ_CTRL_UPQ_SHIFT (12U)
5188/*! UPQ - Untagged Packet Queue.
5189 */
5190#define ENET_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK)
5191#define ENET_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U)
5192#define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U)
5193/*! MCBCQ - Multicast and Broadcast Queue.
5194 */
5195#define ENET_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK)
5196#define ENET_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U)
5197#define ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U)
5198/*! PSRQ2 - Priorities Selected in the Receive Queue 2.
5199 */
5200#define ENET_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ2_MASK)
5201#define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U)
5202#define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U)
5203/*! MCBCQEN - Multicast and Broadcast Queue Enable.
5204 */
5205#define ENET_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK)
5206#define ENET_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U)
5207#define ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U)
5208/*! PSRQ3 - Priorities Selected in the Receive Queue 3.
5209 */
5210#define ENET_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ3_MASK)
5211/*! @} */
5212
5213/* The count of ENET_MAC_RXQ_CTRL */
5214#define ENET_MAC_RXQ_CTRL_COUNT (3U)
5215
5216/*! @name MAC_INTR_STAT - Interrupt status register 0x0000 */
5217/*! @{ */
5218#define ENET_MAC_INTR_STAT_PHYIS_MASK (0x8U)
5219#define ENET_MAC_INTR_STAT_PHYIS_SHIFT (3U)
5220/*! PHYIS - PHY Interrupt.
5221 */
5222#define ENET_MAC_INTR_STAT_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PHYIS_SHIFT)) & ENET_MAC_INTR_STAT_PHYIS_MASK)
5223#define ENET_MAC_INTR_STAT_PMTIS_MASK (0x10U)
5224#define ENET_MAC_INTR_STAT_PMTIS_SHIFT (4U)
5225/*! PMTIS - PMT Interrupt Status.
5226 */
5227#define ENET_MAC_INTR_STAT_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PMTIS_SHIFT)) & ENET_MAC_INTR_STAT_PMTIS_MASK)
5228#define ENET_MAC_INTR_STAT_LPIIS_MASK (0x20U)
5229#define ENET_MAC_INTR_STAT_LPIIS_SHIFT (5U)
5230/*! LPIIS - LPI Interrupt Status.
5231 */
5232#define ENET_MAC_INTR_STAT_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_LPIIS_SHIFT)) & ENET_MAC_INTR_STAT_LPIIS_MASK)
5233#define ENET_MAC_INTR_STAT_TSIS_MASK (0x1000U)
5234#define ENET_MAC_INTR_STAT_TSIS_SHIFT (12U)
5235/*! TSIS - Timestamp interrupt status.
5236 */
5237#define ENET_MAC_INTR_STAT_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TSIS_SHIFT)) & ENET_MAC_INTR_STAT_TSIS_MASK)
5238#define ENET_MAC_INTR_STAT_TXSTSIS_MASK (0x2000U)
5239#define ENET_MAC_INTR_STAT_TXSTSIS_SHIFT (13U)
5240/*! TXSTSIS - Transmit Status Interrupt.
5241 */
5242#define ENET_MAC_INTR_STAT_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_TXSTSIS_MASK)
5243#define ENET_MAC_INTR_STAT_RXSTSIS_MASK (0x4000U)
5244#define ENET_MAC_INTR_STAT_RXSTSIS_SHIFT (14U)
5245/*! RXSTSIS - Receive Status Interrupt.
5246 */
5247#define ENET_MAC_INTR_STAT_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_RXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_RXSTSIS_MASK)
5248/*! @} */
5249
5250/*! @name MAC_INTR_EN - Interrupt enable register 0x0000 */
5251/*! @{ */
5252#define ENET_MAC_INTR_EN_PHYIE_MASK (0x8U)
5253#define ENET_MAC_INTR_EN_PHYIE_SHIFT (3U)
5254/*! PHYIE - PHY Interrupt Enable.
5255 */
5256#define ENET_MAC_INTR_EN_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PHYIE_SHIFT)) & ENET_MAC_INTR_EN_PHYIE_MASK)
5257#define ENET_MAC_INTR_EN_PMTIE_MASK (0x10U)
5258#define ENET_MAC_INTR_EN_PMTIE_SHIFT (4U)
5259/*! PMTIE - PMT Interrupt Enable.
5260 */
5261#define ENET_MAC_INTR_EN_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PMTIE_SHIFT)) & ENET_MAC_INTR_EN_PMTIE_MASK)
5262#define ENET_MAC_INTR_EN_LPIIE_MASK (0x20U)
5263#define ENET_MAC_INTR_EN_LPIIE_SHIFT (5U)
5264/*! LPIIE - LPI Interrupt Enable.
5265 */
5266#define ENET_MAC_INTR_EN_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_LPIIE_SHIFT)) & ENET_MAC_INTR_EN_LPIIE_MASK)
5267#define ENET_MAC_INTR_EN_TSIE_MASK (0x1000U)
5268#define ENET_MAC_INTR_EN_TSIE_SHIFT (12U)
5269/*! TSIE - Timestamp Interrupt Enable.
5270 */
5271#define ENET_MAC_INTR_EN_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TSIE_SHIFT)) & ENET_MAC_INTR_EN_TSIE_MASK)
5272#define ENET_MAC_INTR_EN_TXSTSIE_MASK (0x2000U)
5273#define ENET_MAC_INTR_EN_TXSTSIE_SHIFT (13U)
5274/*! TXSTSIE - Transmit Status Interrupt Enable.
5275 */
5276#define ENET_MAC_INTR_EN_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TXSTSIE_SHIFT)) & ENET_MAC_INTR_EN_TXSTSIE_MASK)
5277#define ENET_MAC_INTR_EN_RXSTSIS_MASK (0x4000U)
5278#define ENET_MAC_INTR_EN_RXSTSIS_SHIFT (14U)
5279/*! RXSTSIS - Receive Status Interrupt Enable.
5280 */
5281#define ENET_MAC_INTR_EN_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_RXSTSIS_SHIFT)) & ENET_MAC_INTR_EN_RXSTSIS_MASK)
5282/*! @} */
5283
5284/*! @name MAC_RXTX_STAT - Receive Transmit Status register */
5285/*! @{ */
5286#define ENET_MAC_RXTX_STAT_TJT_MASK (0x1U)
5287#define ENET_MAC_RXTX_STAT_TJT_SHIFT (0U)
5288/*! TJT - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt
5289 * signal because of the setting of PHYIS bit in MAC Interrupt Status register Table 731.
5290 */
5291#define ENET_MAC_RXTX_STAT_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_TJT_SHIFT)) & ENET_MAC_RXTX_STAT_TJT_MASK)
5292#define ENET_MAC_RXTX_STAT_NCARR_MASK (0x2U)
5293#define ENET_MAC_RXTX_STAT_NCARR_SHIFT (1U)
5294/*! NCARR - No Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758, this
5295 * bit indicates that the carrier signal from the PHY is not present at the end of preamble
5296 * transmission.
5297 */
5298#define ENET_MAC_RXTX_STAT_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_NCARR_SHIFT)) & ENET_MAC_RXTX_STAT_NCARR_MASK)
5299#define ENET_MAC_RXTX_STAT_LCARR_MASK (0x4U)
5300#define ENET_MAC_RXTX_STAT_LCARR_SHIFT (2U)
5301/*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758,
5302 * this bit indicates that the loss of carrier occurred during packet transmission, that is, the
5303 * PHY Carrier signal was inactive for one or more transmission clock periods during packet
5304 * transmission.
5305 */
5306#define ENET_MAC_RXTX_STAT_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCARR_SHIFT)) & ENET_MAC_RXTX_STAT_LCARR_MASK)
5307#define ENET_MAC_RXTX_STAT_EXDEF_MASK (0x8U)
5308#define ENET_MAC_RXTX_STAT_EXDEF_SHIFT (3U)
5309/*! EXDEF - Excessive Deferral When the DTXSTS bit is set in the MTL Operation Mode register Table
5310 * 758 and the DC bit is set in the MAC Configuration register Table 758, this bit indicates that
5311 * the transmission ended because of excessive deferral of over 24,288 bit times (155,680 when
5312 * Jumbo packet is enabled).
5313 */
5314#define ENET_MAC_RXTX_STAT_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXDEF_SHIFT)) & ENET_MAC_RXTX_STAT_EXDEF_MASK)
5315#define ENET_MAC_RXTX_STAT_LCOL_MASK (0x10U)
5316#define ENET_MAC_RXTX_STAT_LCOL_SHIFT (4U)
5317/*! LCOL - Late Collision When the DTXSTS bit is set in the MTL Operation Mode register Table 758,
5318 * this bit indicates that the packet transmission aborted because a collision occurred after the
5319 * collision window (64 bytes including Preamble in MII mode).
5320 */
5321#define ENET_MAC_RXTX_STAT_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCOL_SHIFT)) & ENET_MAC_RXTX_STAT_LCOL_MASK)
5322#define ENET_MAC_RXTX_STAT_EXCOL_MASK (0x20U)
5323#define ENET_MAC_RXTX_STAT_EXCOL_SHIFT (5U)
5324/*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MTL Operation Mode register Table
5325 * 758, this bit indicates that the transmission aborted after 16 successive collisions while
5326 * attempting to transmit the current packet.
5327 */
5328#define ENET_MAC_RXTX_STAT_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXCOL_SHIFT)) & ENET_MAC_RXTX_STAT_EXCOL_MASK)
5329#define ENET_MAC_RXTX_STAT_RWT_MASK (0x100U)
5330#define ENET_MAC_RXTX_STAT_RWT_SHIFT (8U)
5331/*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048
5332 * bytes is received (10,240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the
5333 * MAC Configuration register Table 722.
5334 */
5335#define ENET_MAC_RXTX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_RWT_SHIFT)) & ENET_MAC_RXTX_STAT_RWT_MASK)
5336/*! @} */
5337
5338/*! @name MAC_PMT_CRTL_STAT - */
5339/*! @{ */
5340#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK (0x1U)
5341#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT (0U)
5342/*! PWRDWN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
5343 * entered the LPI state because of the setting of the LPIEN bit.
5344 */
5345#define ENET_MAC_PMT_CRTL_STAT_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK)
5346#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK (0x2U)
5347#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT (1U)
5348/*! MGKPKTEN - Magic Packet Enable.
5349 */
5350#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK)
5351#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK (0x4U)
5352#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT (2U)
5353/*! RWKPKTEN - Remote Wake-Up Packet Enable When this bit is set, a power management event is
5354 * generated when the MAC receives a remote wake-up packet.
5355 */
5356#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK)
5357#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK (0x20U)
5358#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT (5U)
5359/*! MGKPRCVD - Magic Packet Received.
5360 */
5361#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK)
5362#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK (0x40U)
5363#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT (6U)
5364/*! RWKPRCVD - Remote Wake-Up Packet Received.
5365 */
5366#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK)
5367#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK (0x200U)
5368#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT (9U)
5369/*! GLBLUCAST - Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF)
5370 * address recognition is detected as a remote wake-up packet.
5371 */
5372#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK)
5373#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK (0x400U)
5374#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT (10U)
5375/*! RWKPFE - Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the
5376 * MAC receiver drops all received frames until it receives the expected wake-up frame.
5377 */
5378#define ENET_MAC_PMT_CRTL_STAT_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK)
5379#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK (0x1F000000U)
5380#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT (24U)
5381/*! RWKPTR - Remote Wake-up FIFO Pointer This field gives the current value (0 to 7) of the Remote
5382 * Wake-up Packet Filter register pointer.
5383 */
5384#define ENET_MAC_PMT_CRTL_STAT_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK)
5385#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK (0x80000000U)
5386#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT (31U)
5387/*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the
5388 * remote wake-up packet filter register pointer is reset to 3'b000.
5389 */
5390#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK)
5391/*! @} */
5392
5393/*! @name MAC_RWAKE_FRFLT - Remote wake-up frame filter */
5394/*! @{ */
5395#define ENET_MAC_RWAKE_FRFLT_ADDR_MASK (0xFFFFFFFFU)
5396#define ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT (0U)
5397/*! ADDR - WKUPFMFILTER address.
5398 */
5399#define ENET_MAC_RWAKE_FRFLT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT)) & ENET_MAC_RWAKE_FRFLT_ADDR_MASK)
5400/*! @} */
5401
5402/*! @name MAC_LPI_CTRL_STAT - LPI Control and Status Register */
5403/*! @{ */
5404#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK (0x1U)
5405#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT (0U)
5406/*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
5407 * entered the LPI state because of the setting of the LPIEN bit.
5408 */
5409#define ENET_MAC_LPI_CTRL_STAT_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK)
5410#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK (0x2U)
5411#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT (1U)
5412/*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited
5413 * the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired.
5414 */
5415#define ENET_MAC_LPI_CTRL_STAT_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK)
5416#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK (0x4U)
5417#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT (2U)
5418/*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received
5419 * an LPI pattern and entered the LPI state.
5420 */
5421#define ENET_MAC_LPI_CTRL_STAT_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK)
5422#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK (0x8U)
5423#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT (3U)
5424/*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped
5425 * receiving the LPI pattern on the MII interface, exited the LPI state, and resumed the normal
5426 * reception.
5427 */
5428#define ENET_MAC_LPI_CTRL_STAT_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK)
5429#define ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK (0x100U)
5430#define ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT (8U)
5431/*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the LPI pattern on the MII interface.
5432 */
5433#define ENET_MAC_LPI_CTRL_STAT_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK)
5434#define ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK (0x200U)
5435#define ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT (9U)
5436/*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI pattern on the MII interface.
5437 */
5438#define ENET_MAC_LPI_CTRL_STAT_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK)
5439#define ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK (0x10000U)
5440#define ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT (16U)
5441/*! LPIEN - LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state.
5442 */
5443#define ENET_MAC_LPI_CTRL_STAT_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK)
5444#define ENET_MAC_LPI_CTRL_STAT_PLS_MASK (0x20000U)
5445#define ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT (17U)
5446/*! PLS - PHY Link Status This bit indicates the link status of the PHY.
5447 */
5448#define ENET_MAC_LPI_CTRL_STAT_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_PLS_MASK)
5449#define ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK (0x80000U)
5450#define ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT (19U)
5451/*! LPITXA - LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming
5452 * out of the LPI mode on the Transmit side.
5453 */
5454#define ENET_MAC_LPI_CTRL_STAT_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK)
5455#define ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK (0x100000U)
5456#define ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT (20U)
5457/*! LPIATE - LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state.
5458 */
5459#define ENET_MAC_LPI_CTRL_STAT_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK)
5460#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK (0x200000U)
5461#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT (21U)
5462/*! LPITCSE - LPI Tx Clock Stop Enable When this bit is set, the MAC asserts LPI Tx Clock Gating
5463 * Control signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be
5464 * stopped.
5465 */
5466#define ENET_MAC_LPI_CTRL_STAT_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK)
5467/*! @} */
5468
5469/*! @name MAC_LPI_TIMER_CTRL - LPI Timers Control register */
5470/*! @{ */
5471#define ENET_MAC_LPI_TIMER_CTRL_TWT_MASK (0xFFFFU)
5472#define ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT (0U)
5473/*! TWT - LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC
5474 * waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal
5475 * transmission.
5476 */
5477#define ENET_MAC_LPI_TIMER_CTRL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_TWT_MASK)
5478#define ENET_MAC_LPI_TIMER_CTRL_LST_MASK (0x3FF0000U)
5479#define ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT (16U)
5480/*! LST - LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link
5481 * status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY.
5482 */
5483#define ENET_MAC_LPI_TIMER_CTRL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_LST_MASK)
5484/*! @} */
5485
5486/*! @name MAC_LPI_ENTR_TIMR - LPI entry Timer register */
5487/*! @{ */
5488#define ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK (0xFFFF8U)
5489#define ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT (3U)
5490/*! LPIET - LPI Entry Timer This field specifies the time in microseconds the MAC will wait to enter
5491 * LPI mode, after it has transmitted all the frames.
5492 */
5493#define ENET_MAC_LPI_ENTR_TIMR_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT)) & ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK)
5494/*! @} */
5495
5496/*! @name MAC_1US_TIC_COUNTR - */
5497/*! @{ */
5498#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK (0xFFFU)
5499#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT (0U)
5500/*! TIC_1US_CNTR - 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us.
5501 */
5502#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT)) & ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK)
5503/*! @} */
5504
5505/*! @name MAC_VERSION - MAC version register */
5506/*! @{ */
5507#define ENET_MAC_VERSION_SNPVER_MASK (0xFFU)
5508#define ENET_MAC_VERSION_SNPVER_SHIFT (0U)
5509/*! SNPVER - NXP defined version.
5510 */
5511#define ENET_MAC_VERSION_SNPVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPVER_SHIFT)) & ENET_MAC_VERSION_SNPVER_MASK)
5512#define ENET_MAC_VERSION_USERVER_MASK (0xFF00U)
5513#define ENET_MAC_VERSION_USERVER_SHIFT (8U)
5514/*! USERVER - User defined version.
5515 */
5516#define ENET_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK)
5517/*! @} */
5518
5519/*! @name MAC_DBG - MAC debug register */
5520/*! @{ */
5521#define ENET_MAC_DBG_REPESTS_MASK (0x1U)
5522#define ENET_MAC_DBG_REPESTS_SHIFT (0U)
5523/*! REPESTS - MAC MII Receive Protocol Engine Status When this bit is set, it indicates that the MAC
5524 * MII receive protocol engine is actively receiving data, and it is not in the Idle state.
5525 */
5526#define ENET_MAC_DBG_REPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_REPESTS_SHIFT)) & ENET_MAC_DBG_REPESTS_MASK)
5527#define ENET_MAC_DBG_RFCFCSTS_MASK (0x6U)
5528#define ENET_MAC_DBG_RFCFCSTS_SHIFT (1U)
5529/*! RFCFCSTS - MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates
5530 * the active state of the small FIFO Read and Write controllers of the MAC Receive Packet
5531 * Controller module.
5532 */
5533#define ENET_MAC_DBG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_RFCFCSTS_SHIFT)) & ENET_MAC_DBG_RFCFCSTS_MASK)
5534#define ENET_MAC_DBG_TPESTS_MASK (0x10000U)
5535#define ENET_MAC_DBG_TPESTS_SHIFT (16U)
5536/*! TPESTS - MAC MII Transmit Protocol Engine Status When this bit is set, it indicates that the MAC
5537 * or MII transmit protocol engine is actively transmitting data, and it is not in the Idle
5538 * state.
5539 */
5540#define ENET_MAC_DBG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TPESTS_SHIFT)) & ENET_MAC_DBG_TPESTS_MASK)
5541#define ENET_MAC_DBG_TFCSTS_MASK (0x60000U)
5542#define ENET_MAC_DBG_TFCSTS_SHIFT (17U)
5543/*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module.
5544 */
5545#define ENET_MAC_DBG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TFCSTS_SHIFT)) & ENET_MAC_DBG_TFCSTS_MASK)
5546/*! @} */
5547
5548/*! @name MAC_HW_FEAT - MAC hardware feature register 0x0201 */
5549/*! @{ */
5550#define ENET_MAC_HW_FEAT_MIISEL_MASK (0x1U)
5551#define ENET_MAC_HW_FEAT_MIISEL_SHIFT (0U)
5552/*! MIISEL - 10 or 100 Mbps Support.
5553 */
5554#define ENET_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK)
5555#define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU)
5556#define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U)
5557/*! RXFIFOSIZE - MTL Receive FIFO Size.
5558 */
5559#define ENET_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK)
5560#define ENET_MAC_HW_FEAT_RXQCNT_MASK (0xFU)
5561#define ENET_MAC_HW_FEAT_RXQCNT_SHIFT (0U)
5562/*! RXQCNT - Number of MTL Receive Queues.
5563 */
5564#define ENET_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK)
5565#define ENET_MAC_HW_FEAT_HDSEL_MASK (0x4U)
5566#define ENET_MAC_HW_FEAT_HDSEL_SHIFT (2U)
5567/*! HDSEL - Half-duplex Support.
5568 */
5569#define ENET_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK)
5570#define ENET_MAC_HW_FEAT_VLHASH_MASK (0x10U)
5571#define ENET_MAC_HW_FEAT_VLHASH_SHIFT (4U)
5572/*! VLHASH - Hash Table Based Filtering option.
5573 */
5574#define ENET_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK)
5575#define ENET_MAC_HW_FEAT_SMASEL_MASK (0x20U)
5576#define ENET_MAC_HW_FEAT_SMASEL_SHIFT (5U)
5577/*! SMASEL - SMA (MDIO) Interface.
5578 */
5579#define ENET_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK)
5580#define ENET_MAC_HW_FEAT_RWKSEL_MASK (0x40U)
5581#define ENET_MAC_HW_FEAT_RWKSEL_SHIFT (6U)
5582/*! RWKSEL - PMT Remote Wake-up Packet Detection.
5583 */
5584#define ENET_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK)
5585#define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U)
5586#define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U)
5587/*! TXFIFOSIZE - MTL Transmit FIFO Size.
5588 */
5589#define ENET_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK)
5590#define ENET_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U)
5591#define ENET_MAC_HW_FEAT_TXQCNT_SHIFT (6U)
5592/*! TXQCNT - Number of MTL Transmit Queues.
5593 */
5594#define ENET_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK)
5595#define ENET_MAC_HW_FEAT_MGKSEL_MASK (0x80U)
5596#define ENET_MAC_HW_FEAT_MGKSEL_SHIFT (7U)
5597/*! MGKSEL - PMT magic packet detection.
5598 */
5599#define ENET_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK)
5600#define ENET_MAC_HW_FEAT_MMCSEL_MASK (0x100U)
5601#define ENET_MAC_HW_FEAT_MMCSEL_SHIFT (8U)
5602/*! MMCSEL - RMON Module Enable.
5603 */
5604#define ENET_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK)
5605#define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U)
5606#define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U)
5607/*! ARPOFFSEL - ARP Offload Enabled.
5608 */
5609#define ENET_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK)
5610#define ENET_MAC_HW_FEAT_OSTEN_MASK (0x800U)
5611#define ENET_MAC_HW_FEAT_OSTEN_SHIFT (11U)
5612/*! OSTEN - One-Step Timestamping Feature.
5613 */
5614#define ENET_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK)
5615#define ENET_MAC_HW_FEAT_PTOEN_MASK (0x1000U)
5616#define ENET_MAC_HW_FEAT_PTOEN_SHIFT (12U)
5617/*! PTOEN - PTP OffLoad Feature.
5618 */
5619#define ENET_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK)
5620#define ENET_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U)
5621#define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT (12U)
5622/*! RXCHCNT - Number of DMA Receive Channels.
5623 */
5624#define ENET_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK)
5625#define ENET_MAC_HW_FEAT_TSSEL_MASK (0x1000U)
5626#define ENET_MAC_HW_FEAT_TSSEL_SHIFT (12U)
5627/*! TSSEL - IEEE 1588-2008 Timestamp support .
5628 */
5629#define ENET_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK)
5630#define ENET_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U)
5631#define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U)
5632/*! ADVTHWORD - IEEE 1588 High Word Register Feature.
5633 */
5634#define ENET_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK)
5635#define ENET_MAC_HW_FEAT_EEESEL_MASK (0x2000U)
5636#define ENET_MAC_HW_FEAT_EEESEL_SHIFT (13U)
5637/*! EEESEL - Energy Efficient Ethernet Support .
5638 */
5639#define ENET_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK)
5640#define ENET_MAC_HW_FEAT_ADDR64_MASK (0xC000U)
5641#define ENET_MAC_HW_FEAT_ADDR64_SHIFT (14U)
5642/*! ADDR64 - Address width.
5643 */
5644#define ENET_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK)
5645#define ENET_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U)
5646#define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT (14U)
5647/*! TXCOESEL - Transmit Checksum Offload Support.
5648 */
5649#define ENET_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK)
5650#define ENET_MAC_HW_FEAT_DCBEN_MASK (0x10000U)
5651#define ENET_MAC_HW_FEAT_DCBEN_SHIFT (16U)
5652/*! DCBEN - Data Center Bridging feature.
5653 */
5654#define ENET_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK)
5655#define ENET_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U)
5656#define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT (16U)
5657/*! RXCOESEL - Receive Checksum Offload Support.
5658 */
5659#define ENET_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK)
5660#define ENET_MAC_HW_FEAT_SPEN_MASK (0x20000U)
5661#define ENET_MAC_HW_FEAT_SPEN_SHIFT (17U)
5662/*! SPEN - Split Header Structure feature.
5663 */
5664#define ENET_MAC_HW_FEAT_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPEN_SHIFT)) & ENET_MAC_HW_FEAT_SPEN_MASK)
5665#define ENET_MAC_HW_FEAT_TSOEN_MASK (0x40000U)
5666#define ENET_MAC_HW_FEAT_TSOEN_SHIFT (18U)
5667/*! TSOEN - TCP Segment Offload Feature.
5668 */
5669#define ENET_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK)
5670#define ENET_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U)
5671#define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT (18U)
5672/*! TXCHCNT - Number of DMA Transmit Channels.
5673 */
5674#define ENET_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK)
5675#define ENET_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U)
5676#define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT (19U)
5677/*! DBGMEMA - DMA Debug Register Feature.
5678 */
5679#define ENET_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK)
5680#define ENET_MAC_HW_FEAT_AVSEL_MASK (0x100000U)
5681#define ENET_MAC_HW_FEAT_AVSEL_SHIFT (20U)
5682/*! AVSEL - Audio Video Bridging Feature.
5683 */
5684#define ENET_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK)
5685#define ENET_MAC_HW_FEAT_LPMODEEN_MASK (0x800000U)
5686#define ENET_MAC_HW_FEAT_LPMODEEN_SHIFT (23U)
5687/*! LPMODEEN - Low Power Mode Feature Support .
5688 */
5689#define ENET_MAC_HW_FEAT_LPMODEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_LPMODEEN_SHIFT)) & ENET_MAC_HW_FEAT_LPMODEEN_MASK)
5690#define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U)
5691#define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U)
5692/*! HASHTBLSZ - Hash Table Size.
5693 */
5694#define ENET_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK)
5695#define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U)
5696#define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U)
5697/*! PPSOUTNUM - Number of PPS Outputs.
5698 */
5699#define ENET_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK)
5700#define ENET_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U)
5701#define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U)
5702/*! TSSTSSEL - Timestamp System Time Source.
5703 */
5704#define ENET_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK)
5705#define ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK (0x78000000U)
5706#define ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT (27U)
5707/*! L3_L4_FILTER - Total Number of L3 and L4 Filters .
5708 */
5709#define ENET_MAC_HW_FEAT_L3_L4_FILTER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT)) & ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK)
5710#define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U)
5711#define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U)
5712/*! ACTPHYSEL - Active PHY Selected.
5713 */
5714#define ENET_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK)
5715#define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U)
5716#define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U)
5717/*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs.
5718 */
5719#define ENET_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK)
5720/*! @} */
5721
5722/* The count of ENET_MAC_HW_FEAT */
5723#define ENET_MAC_HW_FEAT_COUNT (3U)
5724
5725/*! @name MAC_MDIO_ADDR - MIDO address Register */
5726/*! @{ */
5727#define ENET_MAC_MDIO_ADDR_MB_MASK (0x1U)
5728#define ENET_MAC_MDIO_ADDR_MB_SHIFT (0U)
5729/*! MB - MII busy.
5730 */
5731#define ENET_MAC_MDIO_ADDR_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MB_SHIFT)) & ENET_MAC_MDIO_ADDR_MB_MASK)
5732#define ENET_MAC_MDIO_ADDR_MOC_MASK (0xCU)
5733#define ENET_MAC_MDIO_ADDR_MOC_SHIFT (2U)
5734/*! MOC - MII Operation Command.
5735 */
5736#define ENET_MAC_MDIO_ADDR_MOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MOC_SHIFT)) & ENET_MAC_MDIO_ADDR_MOC_MASK)
5737#define ENET_MAC_MDIO_ADDR_CR_MASK (0xF00U)
5738#define ENET_MAC_MDIO_ADDR_CR_SHIFT (8U)
5739/*! CR - CSR Clock Range.
5740 */
5741#define ENET_MAC_MDIO_ADDR_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_CR_SHIFT)) & ENET_MAC_MDIO_ADDR_CR_MASK)
5742#define ENET_MAC_MDIO_ADDR_NTC_MASK (0x7000U)
5743#define ENET_MAC_MDIO_ADDR_NTC_SHIFT (12U)
5744/*! NTC - Number of Training Clocks This field controls the number of trailing clock cycles
5745 * generated on MDC after the end of transmission of MDIO frame.
5746 */
5747#define ENET_MAC_MDIO_ADDR_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_NTC_SHIFT)) & ENET_MAC_MDIO_ADDR_NTC_MASK)
5748#define ENET_MAC_MDIO_ADDR_RDA_MASK (0x1F0000U)
5749#define ENET_MAC_MDIO_ADDR_RDA_SHIFT (16U)
5750/*! RDA - Register/Device Address These bits select the PHY register in selected PHY device.
5751 */
5752#define ENET_MAC_MDIO_ADDR_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_RDA_SHIFT)) & ENET_MAC_MDIO_ADDR_RDA_MASK)
5753#define ENET_MAC_MDIO_ADDR_PA_MASK (0x3E00000U)
5754#define ENET_MAC_MDIO_ADDR_PA_SHIFT (21U)
5755/*! PA - Physical Layer Address This field indicates which PHY devices (out of 32 devices) the MAC is accessing.
5756 */
5757#define ENET_MAC_MDIO_ADDR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PA_SHIFT)) & ENET_MAC_MDIO_ADDR_PA_MASK)
5758#define ENET_MAC_MDIO_ADDR_BTB_MASK (0x4000000U)
5759#define ENET_MAC_MDIO_ADDR_BTB_SHIFT (26U)
5760/*! BTB - Back to Back transactions When this bit is set and the NTC has value greater than 0, then
5761 * the MAC will inform the completion of a read or write command at the end of frame transfer
5762 * (before the trailing clocks are transmitted).
5763 */
5764#define ENET_MAC_MDIO_ADDR_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_BTB_SHIFT)) & ENET_MAC_MDIO_ADDR_BTB_MASK)
5765#define ENET_MAC_MDIO_ADDR_PSE_MASK (0x8000000U)
5766#define ENET_MAC_MDIO_ADDR_PSE_SHIFT (27U)
5767/*! PSE - Preamble Suppression Enable When this bit is set, the SMA will suppress the 32-bit
5768 * preamble and transmit MDIO frames with only 1 preamble bit.
5769 */
5770#define ENET_MAC_MDIO_ADDR_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PSE_SHIFT)) & ENET_MAC_MDIO_ADDR_PSE_MASK)
5771/*! @} */
5772
5773/*! @name MAC_MDIO_DATA - MDIO Data register */
5774/*! @{ */
5775#define ENET_MAC_MDIO_DATA_MD_MASK (0xFFFFU)
5776#define ENET_MAC_MDIO_DATA_MD_SHIFT (0U)
5777/*! MD - MII Data This field contains the 16-bit data value read from the PHY after a Management
5778 * Read operation or the 16-bit data value to be written to the PHY before a Management Write
5779 * operation.
5780 */
5781#define ENET_MAC_MDIO_DATA_MD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_MD_SHIFT)) & ENET_MAC_MDIO_DATA_MD_MASK)
5782/*! @} */
5783
5784/*! @name MAC_ADDR_HIGH - MAC address0 high register */
5785/*! @{ */
5786#define ENET_MAC_ADDR_HIGH_A47_32_MASK (0xFFFFU)
5787#define ENET_MAC_ADDR_HIGH_A47_32_SHIFT (0U)
5788/*! A47_32 - MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the 6-byte first MAC address.
5789 */
5790#define ENET_MAC_ADDR_HIGH_A47_32(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_A47_32_SHIFT)) & ENET_MAC_ADDR_HIGH_A47_32_MASK)
5791#define ENET_MAC_ADDR_HIGH_DCS_MASK (0x10000U)
5792#define ENET_MAC_ADDR_HIGH_DCS_SHIFT (16U)
5793/*! DCS - DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose
5794 * DA matches the MAC Address content is routed.
5795 */
5796#define ENET_MAC_ADDR_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_DCS_SHIFT)) & ENET_MAC_ADDR_HIGH_DCS_MASK)
5797#define ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000U)
5798#define ENET_MAC_ADDR_HIGH_AE_SHIFT (31U)
5799/*! AE - Address Enable.
5800 */
5801#define ENET_MAC_ADDR_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_AE_SHIFT)) & ENET_MAC_ADDR_HIGH_AE_MASK)
5802/*! @} */
5803
5804/*! @name MAC_ADDR_LOW - MAC address0 low register */
5805/*! @{ */
5806#define ENET_MAC_ADDR_LOW_A31_0_MASK (0xFFFFFFFFU)
5807#define ENET_MAC_ADDR_LOW_A31_0_SHIFT (0U)
5808/*! A31_0 - MAC Address0 [31:0] This field contains the lower 32 bits of the 6-byte first MAC address.
5809 */
5810#define ENET_MAC_ADDR_LOW_A31_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_LOW_A31_0_SHIFT)) & ENET_MAC_ADDR_LOW_A31_0_MASK)
5811/*! @} */
5812
5813/*! @name MAC_TIMESTAMP_CTRL - Time stamp control register */
5814/*! @{ */
5815#define ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK (0x1U)
5816#define ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT (0U)
5817/*! TSENA - Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets.
5818 */
5819#define ENET_MAC_TIMESTAMP_CTRL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK)
5820#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK (0x2U)
5821#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT (1U)
5822/*! TSCFUPDT - Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp.
5823 */
5824#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK)
5825#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK (0x4U)
5826#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT (2U)
5827/*! TSINIT - Initialize Timestamp When this bit is set, the system time is initialized (overwritten)
5828 * with the value specified in the MAC Register 80 (System Time Seconds Update.
5829 */
5830#define ENET_MAC_TIMESTAMP_CTRL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK)
5831#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK (0x8U)
5832#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT (3U)
5833/*! TSUPDT - Update Timestamp When this bit is set, the system time is updated (added or subtracted)
5834 * with the value specified in MAC System Time Seconds Update Table 753 and MAC System Time
5835 * Nanoseconds Update Table 754.
5836 */
5837#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK)
5838#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK (0x10U)
5839#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT (4U)
5840/*! TSTRIG - Enable Timestamp Interrupt Trigger When this bit is set, the timestamp interrupt is
5841 * generated when the System Time becomes greater than the value written in the Target Time register.
5842 */
5843#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK)
5844#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK (0x20U)
5845#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT (5U)
5846/*! TADDREG - Update Addend Register When this bit is set, the content of the Timestamp Addend
5847 * register is updated in the PTP block for fine correction.
5848 */
5849#define ENET_MAC_TIMESTAMP_CTRL_TADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK)
5850#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK (0x100U)
5851#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT (8U)
5852/*! TSENALL - Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is
5853 * enabled for all packets received by the MAC.
5854 */
5855#define ENET_MAC_TIMESTAMP_CTRL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK)
5856#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK (0x200U)
5857#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT (9U)
5858/*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low
5859 * register rolls over after 0x3B9AC9FF value (that is, 1 nanosecond accuracy) and increments
5860 * the timestamp (High) seconds.
5861 */
5862#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)
5863#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK (0x400U)
5864#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT (10U)
5865/*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE
5866 * 1588 version 2 format is used to process the PTP packets.
5867 */
5868#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK)
5869#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK (0x800U)
5870#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT (11U)
5871/*! TSIPENA - Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver
5872 * processes the PTP packets encapsulated directly in the Ethernet packets.
5873 */
5874#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK)
5875#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK (0x1000U)
5876#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT (12U)
5877/*! TSIPV6ENA - Enable Processing of PTP Packets Sent over 1Pv6-UDP When this bit is set, the MAC
5878 * receiver processes the PTP packets encapsulated in IPv6-UDP packets.
5879 */
5880#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK)
5881#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK (0x2000U)
5882#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT (13U)
5883/*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC
5884 * receiver processes the PTP packets encapsulated in IPv4-UDP packets.
5885 */
5886#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK)
5887#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK (0x4000U)
5888#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT (14U)
5889/*! TSEVTENA - Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp
5890 * snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp).
5891 */
5892#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK)
5893#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK (0x8000U)
5894#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT (15U)
5895/*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot
5896 * is taken only for the messages that are relevant to the master node.
5897 */
5898#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK)
5899#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK (0x30000U)
5900#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT (16U)
5901/*! SNAPTYPSEL - Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14,
5902 * decide the set of PTP packet types for which snapshot needs to be taken.
5903 */
5904#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK)
5905#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK (0x40000U)
5906#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT (18U)
5907/*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC
5908 * address (that matches any MAC Address register) is used to filter the PTP packets when PTP is
5909 * directly sent over Ethernet.
5910 */
5911#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK)
5912#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK (0x1000000U)
5913#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT (24U)
5914/*! TXTTSSTSM - Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier
5915 * transmit timestamp status even if it is not read by the software.
5916 */
5917#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK)
5918#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK (0x10000000U)
5919#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT (28U)
5920/*! AV8021ASMEN - AV 802.
5921 */
5922#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK)
5923/*! @} */
5924
5925/*! @name MAC_SUB_SCND_INCR - Sub-second increment register */
5926/*! @{ */
5927#define ENET_MAC_SUB_SCND_INCR_SSINC_MASK (0xFF0000U)
5928#define ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT (16U)
5929/*! SSINC - Sub-second increment value.
5930 */
5931#define ENET_MAC_SUB_SCND_INCR_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT)) & ENET_MAC_SUB_SCND_INCR_SSINC_MASK)
5932/*! @} */
5933
5934/*! @name MAC_SYS_TIME_SCND - System time seconds register */
5935/*! @{ */
5936#define ENET_MAC_SYS_TIME_SCND_TSS_MASK (0xFFFFFFFFU)
5937#define ENET_MAC_SYS_TIME_SCND_TSS_SHIFT (0U)
5938/*! TSS - Time stamp second The value in this field indicates the current value in seconds of the
5939 * System Time maintained by the MAC.
5940 */
5941#define ENET_MAC_SYS_TIME_SCND_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_TSS_MASK)
5942/*! @} */
5943
5944/*! @name MAC_SYS_TIME_NSCND - System time nanoseconds register */
5945/*! @{ */
5946#define ENET_MAC_SYS_TIME_NSCND_TSSS_MASK (0x7FFFFFFFU)
5947#define ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT (0U)
5948/*! TSSS - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.
5949 */
5950#define ENET_MAC_SYS_TIME_NSCND_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK)
5951/*! @} */
5952
5953/*! @name MAC_SYS_TIME_SCND_UPD - */
5954/*! @{ */
5955#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK (0xFFFFFFFFU)
5956#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT (0U)
5957/*! TSS - Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time.
5958 */
5959#define ENET_MAC_SYS_TIME_SCND_UPD_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK)
5960/*! @} */
5961
5962/*! @name MAC_SYS_TIME_NSCND_UPD - */
5963/*! @{ */
5964#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK (0x7FFFFFFFU)
5965#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT (0U)
5966/*! TSSS - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.
5967 */
5968#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK)
5969#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK (0x80000000U)
5970#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT (31U)
5971/*! ADDSUB - Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register.
5972 */
5973#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK)
5974/*! @} */
5975
5976/*! @name MAC_SYS_TIMESTMP_ADDEND - Time stamp addend register */
5977/*! @{ */
5978#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK (0xFFFFFFFFU)
5979#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT (0U)
5980/*! TSAR - Time stamp addend This register indicates the 32-bit time value to be added to the
5981 * Accumulator register to achieve time synchronization.
5982 */
5983#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK)
5984/*! @} */
5985
5986/*! @name MAC_SYS_TIME_HWORD_SCND - */
5987/*! @{ */
5988#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK (0xFFFFU)
5989#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT (0U)
5990/*! TSHWR - Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value.
5991 */
5992#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT)) & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK)
5993/*! @} */
5994
5995/*! @name MAC_SYS_TIMESTMP_STAT - Time stamp status register */
5996/*! @{ */
5997#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK (0x1U)
5998#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT (0U)
5999/*! TSSOVF - Time stamp seconds overflow When set, indicates that the seconds value of the Time
6000 * stamp has overflowed beyond 0xFFFF_FFFF.
6001 */
6002#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT)) & ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK)
6003/*! @} */
6004
6005/*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Tx timestamp status nanoseconds */
6006/*! @{ */
6007#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK (0x7FFFFFFFU)
6008#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT (0U)
6009/*! TXTSSTSLO - Transmit timestamp status low.
6010 */
6011#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK)
6012#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK (0x80000000U)
6013#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT (31U)
6014/*! TXTSSTSMIS - Transmit timestamp status missed.
6015 */
6016#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK)
6017/*! @} */
6018
6019/*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Tx timestamp status seconds */
6020/*! @{ */
6021#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK (0xFFFFFFFFU)
6022#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT (0U)
6023/*! TXTSSTSHI - Transmit timestamp status high.
6024 */
6025#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK)
6026/*! @} */
6027
6028/*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp ingress correction */
6029/*! @{ */
6030#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
6031#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
6032/*! TSIC - Transmit ingress correction.
6033 */
6034#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
6035/*! @} */
6036
6037/*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp egress correction */
6038/*! @{ */
6039#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
6040#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
6041/*! TSEC - Transmit egress correction.
6042 */
6043#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
6044/*! @} */
6045
6046/*! @name MTL_OP_MODE - MTL Operation Mode Register */
6047/*! @{ */
6048#define ENET_MTL_OP_MODE_DTXSTS_MASK (0x2U)
6049#define ENET_MTL_OP_MODE_DTXSTS_SHIFT (1U)
6050/*! DTXSTS - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL.
6051 */
6052#define ENET_MTL_OP_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_DTXSTS_SHIFT)) & ENET_MTL_OP_MODE_DTXSTS_MASK)
6053#define ENET_MTL_OP_MODE_RAA_MASK (0x4U)
6054#define ENET_MTL_OP_MODE_RAA_SHIFT (2U)
6055/*! RAA - Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side.
6056 */
6057#define ENET_MTL_OP_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_RAA_SHIFT)) & ENET_MTL_OP_MODE_RAA_MASK)
6058#define ENET_MTL_OP_MODE_SCHALG_MASK (0x60U)
6059#define ENET_MTL_OP_MODE_SCHALG_SHIFT (5U)
6060/*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: 0x00: WRR
6061 * algorithm 0x1: Reserved 0x2: Reserved 0x3: Strict priority algorithm.
6062 */
6063#define ENET_MTL_OP_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_SCHALG_SHIFT)) & ENET_MTL_OP_MODE_SCHALG_MASK)
6064#define ENET_MTL_OP_MODE_CNTPRST_MASK (0x100U)
6065#define ENET_MTL_OP_MODE_CNTPRST_SHIFT (8U)
6066/*! CNTPRST - Counters Preset When this bit is set, MTL TxQ0 Underflow register (Table 762) and
6067 * MTL_TxQ1_Underflow (Table 762) registers are initialized/preset to 0x7F0.
6068 */
6069#define ENET_MTL_OP_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTPRST_SHIFT)) & ENET_MTL_OP_MODE_CNTPRST_MASK)
6070#define ENET_MTL_OP_MODE_CNTCLR_MASK (0x200U)
6071#define ENET_MTL_OP_MODE_CNTCLR_SHIFT (9U)
6072/*! CNTCLR - Counters Reset When this bit is set, all counters are reset.
6073 */
6074#define ENET_MTL_OP_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTCLR_SHIFT)) & ENET_MTL_OP_MODE_CNTCLR_MASK)
6075/*! @} */
6076
6077/*! @name MTL_INTR_STAT - MTL Interrupt Status register */
6078/*! @{ */
6079#define ENET_MTL_INTR_STAT_Q0IS_MASK (0x1U)
6080#define ENET_MTL_INTR_STAT_Q0IS_SHIFT (0U)
6081/*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0.
6082 */
6083#define ENET_MTL_INTR_STAT_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q0IS_SHIFT)) & ENET_MTL_INTR_STAT_Q0IS_MASK)
6084#define ENET_MTL_INTR_STAT_Q1IS_MASK (0x2U)
6085#define ENET_MTL_INTR_STAT_Q1IS_SHIFT (1U)
6086/*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1.
6087 */
6088#define ENET_MTL_INTR_STAT_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q1IS_SHIFT)) & ENET_MTL_INTR_STAT_Q1IS_MASK)
6089/*! @} */
6090
6091/*! @name MTL_RXQ_DMA_MAP - MTL Receive Queue and DMA Channel Mapping register */
6092/*! @{ */
6093#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK (0x1U)
6094#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT (0U)
6095/*! Q0MDMACH - Queue 0 Mapped to DMA Channel This field controls the routing of the packet received
6096 * in Queue 0 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the
6097 * Q0DDMACH field is reset.
6098 */
6099#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK)
6100#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK (0x10U)
6101#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT (4U)
6102/*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
6103 * the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC
6104 * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
6105 * Ethernet DA address.
6106 */
6107#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK)
6108#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK (0x100U)
6109#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT (8U)
6110/*! Q1MDMACH - Queue 1 Mapped to DMA Channel This field controls the routing of the received packet
6111 * in Queue 1 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the
6112 * Q1DDMACH field is reset.
6113 */
6114#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK)
6115#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK (0x1000U)
6116#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT (12U)
6117/*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
6118 * the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC
6119 * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
6120 * Ethernet DA address.
6121 */
6122#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK)
6123/*! @} */
6124
6125/*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - MTL TxQx Operation Mode register */
6126/*! @{ */
6127#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U)
6128#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U)
6129/*! FTQ - Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values.
6130 */
6131#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK)
6132#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U)
6133#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U)
6134/*! TSF - Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue.
6135 */
6136#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK)
6137#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU)
6138#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U)
6139/*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0.
6140 */
6141#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK)
6142#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U)
6143#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U)
6144/*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue.
6145 */
6146#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK)
6147#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U)
6148#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U)
6149/*! TQS - Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes.
6150 */
6151#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK)
6152/*! @} */
6153
6154/* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */
6155#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT (2U)
6156
6157/*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - MTL TxQx Underflow register */
6158/*! @{ */
6159#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU)
6160#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
6161/*! UFFRMCNT - Underflow Packet Counter This field indicates the number of packets aborted by the
6162 * controller because of Tx Queue Underflow.
6163 */
6164#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
6165#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U)
6166#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
6167/*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue
6168 * Underflow Packet Counter field overflows, that is, it has crossed the maximum count.
6169 */
6170#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
6171/*! @} */
6172
6173/* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */
6174#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT (2U)
6175
6176/*! @name MTL_QUEUE_MTL_TXQX_DBG - MTL TxQx Debug register */
6177/*! @{ */
6178#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U)
6179#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U)
6180/*! TXQPAUSED - Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it
6181 * indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because
6182 * of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue
6183 * when PFC is enabled - Reception of 802.
6184 */
6185#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK)
6186#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK (0x6U)
6187#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U)
6188/*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read
6189 * Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10:
6190 * Waiting for pending Tx Status from the MAC transmitter 11: Flushing the Tx queue because of the
6191 * Packet Abort request from the MAC.
6192 */
6193#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK)
6194#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK (0x8U)
6195#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U)
6196/*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx
6197 * Queue Write Controller is active, and it is transferring the data to the Tx Queue.
6198 */
6199#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK)
6200#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK (0x10U)
6201#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U)
6202/*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue
6203 * is not empty and some data is left for transmission.
6204 */
6205#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK)
6206#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U)
6207#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U)
6208/*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full.
6209 */
6210#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK)
6211#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK (0x70000U)
6212#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT (16U)
6213/*! PTXQ - Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue.
6214 */
6215#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK)
6216#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK (0x700000U)
6217#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT (20U)
6218/*! STSXSTSF - Number of Status Words in Tx Status FIFO of Queue This field indicates the current
6219 * number of status in the Tx Status FIFO of this queue.
6220 */
6221#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK)
6222/*! @} */
6223
6224/* The count of ENET_MTL_QUEUE_MTL_TXQX_DBG */
6225#define ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT (2U)
6226
6227/*! @name MTL_QUEUE_MTL_TXQX_ETS_CTRL - MTL TxQx ETS control register, only TxQ1 support */
6228/*! @{ */
6229#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U)
6230#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U)
6231/*! AVALG - AV Algorithm.
6232 */
6233#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK)
6234#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U)
6235#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U)
6236/*! CC - Credit Control.
6237 */
6238#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK)
6239#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U)
6240#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U)
6241/*! SLC - Credit Control.
6242 */
6243#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK)
6244/*! @} */
6245
6246/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL */
6247#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT (2U)
6248
6249/*! @name MTL_QUEUE_MTL_TXQX_ETS_STAT - MTL TxQx ETS Status register */
6250/*! @{ */
6251#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU)
6252#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U)
6253/*! ABS - Average Bits per Slot.
6254 */
6255#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK)
6256/*! @} */
6257
6258/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT */
6259#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT (2U)
6260
6261/*! @name MTL_QUEUE_MTL_TXQX_QNTM_WGHT - */
6262/*! @{ */
6263#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU)
6264#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U)
6265/*! ISCQW - Average Bits per Slot.
6266 */
6267#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)
6268/*! @} */
6269
6270/* The count of ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT */
6271#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT (2U)
6272
6273/*! @name MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT - MTL TxQx SendSlopCredit register, only TxQ1 support */
6274/*! @{ */
6275#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU)
6276#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U)
6277/*! SSC - sendSlopeCredit.
6278 */
6279#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)
6280/*! @} */
6281
6282/* The count of ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT */
6283#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U)
6284
6285/*! @name MTL_QUEUE_MTL_TXQX_HI_CRDT - MTL TxQx hiCredit register, only TxQ1 support */
6286/*! @{ */
6287#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU)
6288#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U)
6289/*! HC - hiCredit.
6290 */
6291#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK)
6292/*! @} */
6293
6294/* The count of ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT */
6295#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT (2U)
6296
6297/*! @name MTL_QUEUE_MTL_TXQX_LO_CRDT - MTL TxQx loCredit register, only TxQ1 support */
6298/*! @{ */
6299#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU)
6300#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U)
6301/*! LC - loCredit.
6302 */
6303#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK)
6304/*! @} */
6305
6306/* The count of ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT */
6307#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT (2U)
6308
6309/*! @name MTL_QUEUE_MTL_TXQX_INTCTRL_STAT - */
6310/*! @{ */
6311#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)
6312#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)
6313/*! TXUNFIS - Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue
6314 * had an underflow while transmitting the packet.
6315 */
6316#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)
6317#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)
6318#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)
6319/*! ABPSIS - Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value.
6320 */
6321#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)
6322#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)
6323#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)
6324/*! TXUIE - Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled.
6325 */
6326#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)
6327#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)
6328#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)
6329/*! ABPSIE - Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the
6330 * interrupt when the average bits per slot status is updated.
6331 */
6332#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)
6333#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)
6334#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)
6335/*! RXOVFIS - Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had
6336 * an overflow while receiving the packet.
6337 */
6338#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)
6339#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)
6340#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)
6341/*! RXOIE - Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled.
6342 */
6343#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)
6344/*! @} */
6345
6346/* The count of ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT */
6347#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_COUNT (2U)
6348
6349/*! @name MTL_QUEUE_MTL_RXQX_OP_MODE - MTL RxQx Operation Mode register */
6350/*! @{ */
6351#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U)
6352#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U)
6353/*! RTC - Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue
6354 * (in bytes): 00: 64 01: 32 10: 96 11: 128 The packet received is transferred to the
6355 * application or DMA when the packet size within the MTL Rx queue is larger than the threshold.
6356 */
6357#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK)
6358#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U)
6359#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U)
6360/*! FUP - Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized
6361 * good packets (packets with no error and length less than 64 bytes), including pad-bytes and
6362 * CRC.
6363 */
6364#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK)
6365#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U)
6366#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U)
6367/*! FEP - Forward Error Packets When this bit is reset, the Rx queue drops packets with error status
6368 * (CRC error, Mll_ER, watchdog timeout, or overflow).
6369 */
6370#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK)
6371#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U)
6372#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U)
6373/*! RSF - Receive Queue Store and Forward When this bit is set, the ethernet block on this chip
6374 * reads a packet from the Rx queue only after the complete packet has been written to it, ignoring
6375 * the RTC field of this register.
6376 */
6377#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK)
6378#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)
6379#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)
6380/*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC
6381 * does not drop the packets which only have the errors detected by the Receive Checksum Offload
6382 * engine.
6383 */
6384#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)
6385#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U)
6386#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U)
6387/*! RQS - This field indicates the size of the allocated Receive queues in blocks of 256 bytes.
6388 */
6389#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK)
6390/*! @} */
6391
6392/* The count of ENET_MTL_QUEUE_MTL_RXQX_OP_MODE */
6393#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT (2U)
6394
6395/*! @name MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT - MTL RxQx Missed Packet Overflow Counter register */
6396/*! @{ */
6397#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)
6398#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)
6399/*! OVFPKTCNT - Overflow Packet Counter This field indicates the number of packets discarded by the
6400 * Ethernet block because of Receive queue overflow.
6401 */
6402#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)
6403#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)
6404#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)
6405/*! OVFCNTOVF - Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue
6406 * Overflow Packet Counter field crossed the maximum limit.
6407 */
6408#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)
6409/*! @} */
6410
6411/* The count of ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT */
6412#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U)
6413
6414/*! @name MTL_QUEUE_MTL_RXQX_DBG - MTL RxQx Debug register */
6415/*! @{ */
6416#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK (0x1U)
6417#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U)
6418/*! RWCSTS - MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL
6419 * Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue.
6420 */
6421#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK)
6422#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK (0x6U)
6423#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U)
6424/*! RRCSTS - MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read
6425 * controller: 00: Idle state 01: Reading packet data 10: Reading packet status (or timestamp) 11:
6426 * Flushing the packet data and status.
6427 */
6428#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK)
6429#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK (0x30U)
6430#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U)
6431/*! RXQSTS - MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx
6432 * Queue: 0x0: Rx Queue empty 0x1: Rx Queue fill-level below flow-control deactivate threshold
6433 * 0x2: Rx Queue fill-level above flow-control activate threshold 0x3: Rx Queue full.
6434 */
6435#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK)
6436#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U)
6437#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT (16U)
6438/*! PRXQ - Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue.
6439 */
6440#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK)
6441/*! @} */
6442
6443/* The count of ENET_MTL_QUEUE_MTL_RXQX_DBG */
6444#define ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT (2U)
6445
6446/*! @name MTL_QUEUE_MTL_RXQX_CTRL - MTL RxQx Control register */
6447/*! @{ */
6448#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U)
6449#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U)
6450/*! RXQ_WEGT - Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0.
6451 */
6452#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK)
6453#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)
6454#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)
6455/*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration When this bit is set, the The ethernet block
6456 * drives the packet data to the ARI interface such that the entire packet data of
6457 * currently-selected queue is transmitted before switching to other queue.
6458 */
6459#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)
6460/*! @} */
6461
6462/* The count of ENET_MTL_QUEUE_MTL_RXQX_CTRL */
6463#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT (2U)
6464
6465/*! @name DMA_MODE - DMA mode register */
6466/*! @{ */
6467#define ENET_DMA_MODE_SWR_MASK (0x1U)
6468#define ENET_DMA_MODE_SWR_SHIFT (0U)
6469/*! SWR - Software Reset When this bit is set, the MAC and the OMA controller reset the logic and
6470 * all internal registers of the OMA, MTL, and MAC.
6471 */
6472#define ENET_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK)
6473#define ENET_DMA_MODE_DA_MASK (0x2U)
6474#define ENET_DMA_MODE_DA_SHIFT (1U)
6475/*! DA - DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the
6476 * Transmit and Receive paths of all channels: The Tx path has priority over the Rx path when the TXPR
6477 * bit is set.
6478 */
6479#define ENET_DMA_MODE_DA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK)
6480#define ENET_DMA_MODE_TAA_MASK (0x1CU)
6481#define ENET_DMA_MODE_TAA_SHIFT (2U)
6482/*! TAA - Transmit Arbitration Algorithm This field is used to select the arbitration algorithm for
6483 * the Transmit side when multiple Tx DMAs are selected.
6484 */
6485#define ENET_DMA_MODE_TAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK)
6486#define ENET_DMA_MODE_TXPR_MASK (0x800U)
6487#define ENET_DMA_MODE_TXPR_SHIFT (11U)
6488/*! TXPR - Transmit Priority When set, this bit indicates that the Tx DMA has higher priority than
6489 * the Rx DMA during arbitration for the system-side bus.
6490 */
6491#define ENET_DMA_MODE_TXPR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK)
6492#define ENET_DMA_MODE_PR_MASK (0x7000U)
6493#define ENET_DMA_MODE_PR_SHIFT (12U)
6494/*! PR - Priority Ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA.
6495 */
6496#define ENET_DMA_MODE_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK)
6497/*! @} */
6498
6499/*! @name DMA_SYSBUS_MODE - DMA System Bus mode */
6500/*! @{ */
6501#define ENET_DMA_SYSBUS_MODE_FB_MASK (0x1U)
6502#define ENET_DMA_SYSBUS_MODE_FB_SHIFT (0U)
6503/*! FB - Fixed Burst Length When this bit is set to 1, the AHB master will initiate burst transfers
6504 * of specified length (INCRx or SINGLE).
6505 */
6506#define ENET_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK)
6507#define ENET_DMA_SYSBUS_MODE_AAL_MASK (0x1000U)
6508#define ENET_DMA_SYSBUS_MODE_AAL_SHIFT (12U)
6509/*! AAL - Address-Aligned Beats When this bit is set to 1, the AHB master performs address-aligned
6510 * burst transfers on Read and Write channels.
6511 */
6512#define ENET_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK)
6513#define ENET_DMA_SYSBUS_MODE_MB_MASK (0x4000U)
6514#define ENET_DMA_SYSBUS_MODE_MB_SHIFT (14U)
6515/*! MB - Mixed Burst When this bit is set high and the FB bit is low, the AHB master performs
6516 * undefined bursts transfers (INCR) for burst length of 16 or more.
6517 */
6518#define ENET_DMA_SYSBUS_MODE_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK)
6519#define ENET_DMA_SYSBUS_MODE_RB_MASK (0x8000U)
6520#define ENET_DMA_SYSBUS_MODE_RB_SHIFT (15U)
6521/*! RB - Rebuild INCRx Burst When this bit is set high and the AHB master gets SPLIT, RETRY, or
6522 * EarlyBurst Termination (EBT) response, the AHB master interface rebuilds the pending beats of any
6523 * initiated burst transfer with INCRx and SINGLEtransfers.
6524 */
6525#define ENET_DMA_SYSBUS_MODE_RB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK)
6526/*! @} */
6527
6528/*! @name DMA_INTR_STAT - DMA Interrupt status */
6529/*! @{ */
6530#define ENET_DMA_INTR_STAT_DC0IS_MASK (0x1U)
6531#define ENET_DMA_INTR_STAT_DC0IS_SHIFT (0U)
6532/*! DC0IS - DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0.
6533 */
6534#define ENET_DMA_INTR_STAT_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC0IS_SHIFT)) & ENET_DMA_INTR_STAT_DC0IS_MASK)
6535#define ENET_DMA_INTR_STAT_DC1IS_MASK (0x2U)
6536#define ENET_DMA_INTR_STAT_DC1IS_SHIFT (1U)
6537/*! DC1IS - DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1.
6538 */
6539#define ENET_DMA_INTR_STAT_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC1IS_SHIFT)) & ENET_DMA_INTR_STAT_DC1IS_MASK)
6540#define ENET_DMA_INTR_STAT_MTLIS_MASK (0x10000U)
6541#define ENET_DMA_INTR_STAT_MTLIS_SHIFT (16U)
6542/*! MTLIS - MTL Interrupt Status This bit indicates an interrupt event in the MTL.
6543 */
6544#define ENET_DMA_INTR_STAT_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MTLIS_SHIFT)) & ENET_DMA_INTR_STAT_MTLIS_MASK)
6545#define ENET_DMA_INTR_STAT_MACIS_MASK (0x20000U)
6546#define ENET_DMA_INTR_STAT_MACIS_SHIFT (17U)
6547/*! MACIS - MAC Interrupt Status This bit indicates an interrupt event in the MAC.
6548 */
6549#define ENET_DMA_INTR_STAT_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MACIS_SHIFT)) & ENET_DMA_INTR_STAT_MACIS_MASK)
6550/*! @} */
6551
6552/*! @name DMA_DBG_STAT - DMA Debug Status */
6553/*! @{ */
6554#define ENET_DMA_DBG_STAT_AHSTS_MASK (0x1U)
6555#define ENET_DMA_DBG_STAT_AHSTS_SHIFT (0U)
6556/*! AHSTS - AHB Master Status When high, this bit indicates that the AHB master FSMs are in the non-idle state.
6557 */
6558#define ENET_DMA_DBG_STAT_AHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_AHSTS_SHIFT)) & ENET_DMA_DBG_STAT_AHSTS_MASK)
6559#define ENET_DMA_DBG_STAT_RPS0_MASK (0xF00U)
6560#define ENET_DMA_DBG_STAT_RPS0_SHIFT (8U)
6561/*! RPS0 - DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel
6562 * 0: 0x0: Stopped (Reset or Stop Receive Command issued) 0x1: Running (Fetching Rx Transfer )
6563 * 0x2: Reserved 0x3: Running (Waiting for Rx packet) 0x4: Suspended (Rx Unavailable) 0x5: Running
6564 * (Closing the Rx) 0x6: Timestamp write state 0x7: Running (Transferring the received packet
6565 * data from the Rx buffer to the system memory) This field does not generate an interrupt.
6566 */
6567#define ENET_DMA_DBG_STAT_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS0_SHIFT)) & ENET_DMA_DBG_STAT_RPS0_MASK)
6568#define ENET_DMA_DBG_STAT_TPS0_MASK (0xF000U)
6569#define ENET_DMA_DBG_STAT_TPS0_SHIFT (12U)
6570/*! TPS0 - DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for
6571 * Channel 0: 000: Stopped (Reset or Stop Transmit Command issued) 0x1: Running (Fetching Tx Transfer)
6572 * 0x2: Running (Waiting for status) 0x3: Running (Reading Data from system memory buffer and
6573 * queuing it to the Tx buffer (Tx FIFO)) 0x4: Timestamp write state 0x5: Reserved for future use
6574 * 0x6: Suspended (Tx Unavailable or Tx Buffer Underflow) 0x7: Running (Closing Tx ) This field
6575 * does not generate an interrupt.
6576 */
6577#define ENET_DMA_DBG_STAT_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS0_SHIFT)) & ENET_DMA_DBG_STAT_TPS0_MASK)
6578#define ENET_DMA_DBG_STAT_RPS1_MASK (0xF0000U)
6579#define ENET_DMA_DBG_STAT_RPS1_SHIFT (16U)
6580/*! RPS1 - DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1.
6581 */
6582#define ENET_DMA_DBG_STAT_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS1_SHIFT)) & ENET_DMA_DBG_STAT_RPS1_MASK)
6583#define ENET_DMA_DBG_STAT_TPS1_MASK (0xF00000U)
6584#define ENET_DMA_DBG_STAT_TPS1_SHIFT (20U)
6585/*! TPS1 - DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1.
6586 */
6587#define ENET_DMA_DBG_STAT_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS1_SHIFT)) & ENET_DMA_DBG_STAT_TPS1_MASK)
6588/*! @} */
6589
6590/*! @name DMA_CH_DMA_CHX_CTRL - DMA Channelx Control */
6591/*! @{ */
6592#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK (0x10000U)
6593#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT (16U)
6594/*! PBLx8 - 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in DMA Channel
6595 * Transmit Control Table 780 is multiplied eight times.
6596 */
6597#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK)
6598#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK (0x1C0000U)
6599#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT (18U)
6600/*! DSL - Skip Length This bit specifies the Word, Dword, or Lword number (depending on the 32- bit,
6601 * 64-bit, or 128-bit bus) to skip between two unchained s.
6602 */
6603#define ENET_DMA_CH_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK)
6604/*! @} */
6605
6606/* The count of ENET_DMA_CH_DMA_CHX_CTRL */
6607#define ENET_DMA_CH_DMA_CHX_CTRL_COUNT (2U)
6608
6609/*! @name DMA_CH_DMA_CHX_TX_CTRL - DMA Channelx Transmit Control */
6610/*! @{ */
6611#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK (0x1U)
6612#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT (0U)
6613/*! ST - Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state.
6614 */
6615#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK)
6616#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK (0xEU)
6617#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT (1U)
6618/*! TCW - Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel.
6619 */
6620#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK)
6621#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK (0x10U)
6622#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT (4U)
6623/*! OSF - Operate on Second Frame When this bit is set, it instructs the DMA to process the second
6624 * packet of the Transmit data even before the status for the first packet is obtained.
6625 */
6626#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK)
6627#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U)
6628#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U)
6629/*! TxPBL - Transmit Programmable Burst Length These bits indicate the maximum number of beats to be
6630 * transferred in one DMA data transfer.
6631 */
6632#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK)
6633/*! @} */
6634
6635/* The count of ENET_DMA_CH_DMA_CHX_TX_CTRL */
6636#define ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT (2U)
6637
6638/*! @name DMA_CH_DMA_CHX_RX_CTRL - DMA Channelx Receive Control */
6639/*! @{ */
6640#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK (0x1U)
6641#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT (0U)
6642/*! SR - Start or Stop Receive When this bit is set, the DMA tries to acquire the from the receive
6643 * list and processes the incoming packets.
6644 */
6645#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK)
6646#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK (0x7FF8U)
6647#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT (3U)
6648/*! RBSZ - Receive Buffer size This field indicates the size of the Rx buffers specified in bytes.
6649 */
6650#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK)
6651#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U)
6652#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U)
6653/*! RxPBL - Receive Programmable Burst Length These bits indicate the maximum number of beats to be
6654 * transferred in one DMA data transfer.
6655 */
6656#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK)
6657#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U)
6658#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT (31U)
6659/*! RPF - DMA Rx Channel 0 Packet Flush When this bit is set to 1, the DMA will automatically flush
6660 * the packet from the Rx Queues destined to DMA Rx Channel 0 when the DMA Rx Channel 0 is
6661 * stopped after a system bus error has occurred.
6662 */
6663#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK)
6664/*! @} */
6665
6666/* The count of ENET_DMA_CH_DMA_CHX_RX_CTRL */
6667#define ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT (2U)
6668
6669/*! @name DMA_CH_DMA_CHX_TXDESC_LIST_ADDR - */
6670/*! @{ */
6671#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK (0xFFFFFFFCU)
6672#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT (2U)
6673/*! STL - Start of transmit list This field contains the base address of the first in the Transmit list.
6674 */
6675#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK)
6676/*! @} */
6677
6678/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR */
6679#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U)
6680
6681/*! @name DMA_CH_DMA_CHX_RXDESC_LIST_ADDR - */
6682/*! @{ */
6683#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK (0xFFFFFFFCU)
6684#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT (2U)
6685/*! SRL - Start of receive list This field contains the base address of the First in the Receive list.
6686 */
6687#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK)
6688/*! @} */
6689
6690/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR */
6691#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U)
6692
6693/*! @name DMA_CH_DMA_CHX_TXDESC_TAIL_PTR - */
6694/*! @{ */
6695#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU)
6696#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U)
6697/*! TDTP - Transmit Tail Pointer This field contains the tail pointer for the Tx ring.
6698 */
6699#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)
6700/*! @} */
6701
6702/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR */
6703#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U)
6704
6705/*! @name DMA_CH_DMA_CHX_RXDESC_TAIL_PTR - */
6706/*! @{ */
6707#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU)
6708#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U)
6709/*! RDTP - Receive Tail Pointer This field contains the tail pointer for the Rx ring.
6710 */
6711#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)
6712/*! @} */
6713
6714/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR */
6715#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U)
6716
6717/*! @name DMA_CH_DMA_CHX_TXDESC_RING_LENGTH - */
6718/*! @{ */
6719#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)
6720#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
6721/*! TDRL - Transmit Ring Length This field sets the maximum number of Tx descriptors in the circular ring.
6722 */
6723#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)
6724/*! @} */
6725
6726/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH */
6727#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U)
6728
6729/*! @name DMA_CH_DMA_CHX_RXDESC_RING_LENGTH - Channelx Rx descriptor Ring Length */
6730/*! @{ */
6731#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)
6732#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)
6733/*! RDRL - Receive Ring Length This register sets the maximum number of Rx descriptors in the circular ring.
6734 */
6735#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)
6736/*! @} */
6737
6738/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH */
6739#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_COUNT (2U)
6740
6741/*! @name DMA_CH_DMA_CHX_INT_EN - Channelx Interrupt Enable */
6742/*! @{ */
6743#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK (0x1U)
6744#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT (0U)
6745/*! TIE - Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit
6746 * 16 in this register), Transmit Interrupt is enabled.
6747 */
6748#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK)
6749#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK (0x2U)
6750#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT (1U)
6751/*! TSE - Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit
6752 * 15 in this register), Transmission Stopped Interrupt is enabled.
6753 */
6754#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK)
6755#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK (0x4U)
6756#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT (2U)
6757/*! TBUE - Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary
6758 * Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled.
6759 */
6760#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK)
6761#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK (0x40U)
6762#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT (6U)
6763/*! RIE - Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16
6764 * in this register), Receive Interrupt is enabled.
6765 */
6766#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK)
6767#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK (0x80U)
6768#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT (7U)
6769/*! RBUE - Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary
6770 * Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled.
6771 */
6772#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK)
6773#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK (0x100U)
6774#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT (8U)
6775/*! RSE - Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit
6776 * 15 in this register), Receive Stopped Interrupt is enabled.
6777 */
6778#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK)
6779#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK (0x200U)
6780#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT (9U)
6781/*! RWTE - Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary
6782 * Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled.
6783 */
6784#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK)
6785#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK (0x400U)
6786#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT (10U)
6787/*! ETIE - Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary
6788 * Enable (bit 15 in this register), Early Transmit Interrupt is enabled.
6789 */
6790#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK)
6791#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK (0x800U)
6792#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT (11U)
6793/*! ERIE - Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable
6794 * (bit 16 in this register), Early Receive Interrupt is enabled.
6795 */
6796#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK)
6797#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK (0x1000U)
6798#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT (12U)
6799/*! FBEE - Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit
6800 * 15 in this register), the Fatal Bus Error Interrupt is enabled.
6801 */
6802#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK)
6803#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK (0x4000U)
6804#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT (14U)
6805/*! AIE - Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt summary is enabled.
6806 */