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1/*
2** ###################################################################
3** Processors: LPC54607J256BD208
4** LPC54607J256ET180
5** LPC54607J512ET180
6**
7** Compilers: GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9** Keil ARM C/C++ Compiler
10** MCUXpresso Compiler
11**
12** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017
13** Version: rev. 1.2, 2017-06-08
14** Build: b200304
15**
16** Abstract:
17** CMSIS Peripheral Access Layer for LPC54607
18**
19** Copyright 1997-2016 Freescale Semiconductor, Inc.
20** Copyright 2016-2020 NXP
21** All rights reserved.
22**
23** SPDX-License-Identifier: BSD-3-Clause
24**
25** http: www.nxp.com
26** mail: [email protected]
27**
28** Revisions:
29** - rev. 1.0 (2016-08-12)
30** Initial version.
31** - rev. 1.1 (2016-11-25)
32** Update CANFD and Classic CAN register.
33** Add MAC TIMERSTAMP registers.
34** - rev. 1.2 (2017-06-08)
35** Remove RTC_CTRL_RTC_OSC_BYPASS.
36** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
37** Remove RESET and HALT from SYSCON_AHBCLKDIV.
38**
39** ###################################################################
40*/
41
42/*!
43 * @file LPC54607.h
44 * @version 1.2
45 * @date 2017-06-08
46 * @brief CMSIS Peripheral Access Layer for LPC54607
47 *
48 * CMSIS Peripheral Access Layer for LPC54607
49 */
50
51#ifndef _LPC54607_H_
52#define _LPC54607_H_ /**< Symbol preventing repeated inclusion */
53
54/** Memory map major version (memory maps with equal major version number are
55 * compatible) */
56#define MCU_MEM_MAP_VERSION 0x0100U
57/** Memory map minor version */
58#define MCU_MEM_MAP_VERSION_MINOR 0x0002U
59
60
61/* ----------------------------------------------------------------------------
62 -- Interrupt vector numbers
63 ---------------------------------------------------------------------------- */
64
65/*!
66 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
67 * @{
68 */
69
70/** Interrupt Number Definitions */
71#define NUMBER_OF_INT_VECTORS 73 /**< Number of interrupts in the Vector table */
72
73typedef enum IRQn {
74 /* Auxiliary constants */
75 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
76
77 /* Core interrupts */
78 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
79 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
80 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
81 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
82 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
83 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
84 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
85 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
86 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
87
88 /* Device specific interrupts */
89 WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */
90 DMA0_IRQn = 1, /**< DMA controller */
91 GINT0_IRQn = 2, /**< GPIO group 0 */
92 GINT1_IRQn = 3, /**< GPIO group 1 */
93 PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */
94 PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */
95 PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */
96 PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */
97 UTICK0_IRQn = 8, /**< Micro-tick Timer */
98 MRT0_IRQn = 9, /**< Multi-rate timer */
99 CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
100 CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
101 SCT0_IRQn = 12, /**< SCTimer/PWM */
102 CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
103 FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
104 FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
105 FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
106 FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
107 FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
108 FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
109 FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
110 FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
111 ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */
112 ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */
113 ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */
114 DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */
115 HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */
116 USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */
117 USB0_IRQn = 28, /**< USB device */
118 RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */
119 Reserved46_IRQn = 30, /**< Reserved interrupt */
120 Reserved47_IRQn = 31, /**< Reserved interrupt */
121 PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */
122 PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */
123 PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */
124 PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */
125 CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */
126 CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */
127 RIT_IRQn = 38, /**< Repetitive Interrupt Timer */
128 SPIFI0_IRQn = 39, /**< SPI flash interface */
129 FLEXCOMM8_IRQn = 40, /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
130 FLEXCOMM9_IRQn = 41, /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
131 SDIO_IRQn = 42, /**< SD/MMC */
132 CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */
133 CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */
134 CAN1_IRQ0_IRQn = 45, /**< CAN1 interrupt0 */
135 CAN1_IRQ1_IRQn = 46, /**< CAN1 interrupt1 */
136 USB1_IRQn = 47, /**< USB1 interrupt */
137 USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */
138 ETHERNET_IRQn = 49, /**< Ethernet */
139 ETHERNET_PMT_IRQn = 50, /**< Ethernet power management interrupt */
140 ETHERNET_MACLP_IRQn = 51, /**< Ethernet MAC interrupt */
141 EEPROM_IRQn = 52, /**< EEPROM interrupt */
142 LCD_IRQn = 53, /**< LCD interrupt */
143 SHA_IRQn = 54, /**< SHA interrupt */
144 SMARTCARD0_IRQn = 55, /**< Smart card 0 interrupt */
145 SMARTCARD1_IRQn = 56 /**< Smart card 1 interrupt */
146} IRQn_Type;
147
148/*!
149 * @}
150 */ /* end of group Interrupt_vector_numbers */
151
152
153/* ----------------------------------------------------------------------------
154 -- Cortex M4 Core Configuration
155 ---------------------------------------------------------------------------- */
156
157/*!
158 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
159 * @{
160 */
161
162#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
163#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
164#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
165#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
166
167#include "core_cm4.h" /* Core Peripheral Access Layer */
168#include "system_LPC54607.h" /* Device specific configuration file */
169
170/*!
171 * @}
172 */ /* end of group Cortex_Core_Configuration */
173
174
175/* ----------------------------------------------------------------------------
176 -- Mapping Information
177 ---------------------------------------------------------------------------- */
178
179/*!
180 * @addtogroup Mapping_Information Mapping Information
181 * @{
182 */
183
184/** Mapping Information */
185/*!
186 * @addtogroup dma_request
187 * @{
188 */
189
190/*******************************************************************************
191 * Definitions
192 ******************************************************************************/
193
194/*!
195 * @brief Structure for the DMA hardware request
196 *
197 * Defines the structure for the DMA hardware request collections. The user can configure the
198 * hardware request to trigger the DMA transfer accordingly. The index
199 * of the hardware request varies according to the to SoC.
200 */
201typedef enum _dma_request_source
202{
203 kDmaRequestFlexcomm0Rx = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */
204 kDmaRequestFlexcomm0Tx = 1U, /**< Flexcomm Interface 0 TX/I2C Master */
205 kDmaRequestFlexcomm1Rx = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */
206 kDmaRequestFlexcomm1Tx = 3U, /**< Flexcomm Interface 1 TX/I2C Master */
207 kDmaRequestFlexcomm2Rx = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */
208 kDmaRequestFlexcomm2Tx = 5U, /**< Flexcomm Interface 2 TX/I2C Master */
209 kDmaRequestFlexcomm3Rx = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */
210 kDmaRequestFlexcomm3Tx = 7U, /**< Flexcomm Interface 3 TX/I2C Master */
211 kDmaRequestFlexcomm4Rx = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */
212 kDmaRequestFlexcomm4Tx = 9U, /**< Flexcomm Interface 4 TX/I2C Master */
213 kDmaRequestFlexcomm5Rx = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */
214 kDmaRequestFlexcomm5Tx = 11U, /**< Flexcomm Interface 5 TX/I2C Master */
215 kDmaRequestFlexcomm6Rx = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */
216 kDmaRequestFlexcomm6Tx = 13U, /**< Flexcomm Interface 6 TX/I2C Master */
217 kDmaRequestFlexcomm7Rx = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */
218 kDmaRequestFlexcomm7Tx = 15U, /**< Flexcomm Interface 7 TX/I2C Master */
219 kDmaRequestDMIC0 = 16U, /**< Digital microphone interface 0 channel 0 */
220 kDmaRequestDMIC1 = 17U, /**< Digital microphone interface 0 channel 1 */
221 kDmaRequestSPIFI = 18U, /**< SPI Flash Interface */
222 kDmaRequestSHA = 19U, /**< Reserved */
223 kDmaRequestFlexcomm8Rx = 20U, /**< Flexcomm Interface 8 RX/I2C Slave */
224 kDmaRequestFlexcomm8Tx = 21U, /**< Flexcomm Interface 8 TX/I2C Slave */
225 kDmaRequestFlexcomm9Rx = 22U, /**< Flexcomm Interface 9 RX/I2C Slave */
226 kDmaRequestFlexcomm9Tx = 23U, /**< Flexcomm Interface 9 TX/I2C Slave */
227 kDmaRequestSMARTCARD0_RX = 24U, /**< SMARTCARD0 RX */
228 kDmaRequestSMARTCARD0_TX = 25U, /**< SMARTCARD0 TX */
229 kDmaRequestSMARTCARD1_RX = 26U, /**< SMARTCARD1 RX */
230 kDmaRequestSMARTCARD1_TX = 27U, /**< SMARTCARD1 TX */
231 kDmaRequestNoDMARequest28 = 28U, /**< No DMA request 28 */
232 kDmaRequestNoDMARequest29 = 29U, /**< No DMA request 29 */
233} dma_request_source_t;
234
235/* @} */
236
237
238/*!
239 * @}
240 */ /* end of group Mapping_Information */
241
242
243/* ----------------------------------------------------------------------------
244 -- Device Peripheral Access Layer
245 ---------------------------------------------------------------------------- */
246
247/*!
248 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
249 * @{
250 */
251
252
253/*
254** Start of section using anonymous unions
255*/
256
257#if defined(__ARMCC_VERSION)
258 #if (__ARMCC_VERSION >= 6010050)
259 #pragma clang diagnostic push
260 #else
261 #pragma push
262 #pragma anon_unions
263 #endif
264#elif defined(__GNUC__)
265 /* anonymous unions are enabled by default */
266#elif defined(__IAR_SYSTEMS_ICC__)
267 #pragma language=extended
268#else
269 #error Not supported compiler type
270#endif
271
272/* ----------------------------------------------------------------------------
273 -- ADC Peripheral Access Layer
274 ---------------------------------------------------------------------------- */
275
276/*!
277 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
278 * @{
279 */
280
281/** ADC - Register Layout Typedef */
282typedef struct {
283 __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
284 __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
285 __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
286 __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
287 uint8_t RESERVED_0[8];
288 __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
289 __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
290 __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
291 __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
292 __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
293 __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
294 __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
295 __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
296 __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */
297 __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */
298} ADC_Type;
299
300/* ----------------------------------------------------------------------------
301 -- ADC Register Masks
302 ---------------------------------------------------------------------------- */
303
304/*!
305 * @addtogroup ADC_Register_Masks ADC Register Masks
306 * @{
307 */
308
309/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
310/*! @{ */
311#define ADC_CTRL_CLKDIV_MASK (0xFFU)
312#define ADC_CTRL_CLKDIV_SHIFT (0U)
313/*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce
314 * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically,
315 * software should program the smallest value in this field that yields this maximum clock rate or
316 * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may
317 * be desirable. This field is ignored in the asynchronous operating mode.
318 */
319#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
320#define ADC_CTRL_ASYNMODE_MASK (0x100U)
321#define ADC_CTRL_ASYNMODE_SHIFT (8U)
322/*! ASYNMODE - Select clock mode.
323 * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in
324 * the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to
325 * eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger.
326 * In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC
327 * input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger
328 * pulse.
329 * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
330 */
331#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
332#define ADC_CTRL_RESOL_MASK (0x600U)
333#define ADC_CTRL_RESOL_SHIFT (9U)
334/*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher
335 * conversion rates. A single conversion (including one conversion in a burst or sequence) requires the
336 * selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when
337 * the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable
338 * results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate
339 * for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system
340 * clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution
341 * 0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field.
342 * 0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field.
343 * 0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field.
344 * 0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field.
345 */
346#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
347#define ADC_CTRL_BYPASSCAL_MASK (0x800U)
348#define ADC_CTRL_BYPASSCAL_SHIFT (11U)
349/*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset
350 * error is not a concern in the application.
351 * 0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for
352 * offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may
353 * be warranted periodically - especially if operating conditions have changed.
354 * 0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC -
355 * particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set.
356 */
357#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
358#define ADC_CTRL_TSAMP_MASK (0x7000U)
359#define ADC_CTRL_TSAMP_SHIFT (12U)
360/*! TSAMP - Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion
361 * is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions
362 * and the output impedance of the analog source, longer sampling times may be required. See
363 * Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to
364 * seven, by which the sample period will be extended. The total conversion time will increase by
365 * the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A
366 * complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will
367 * be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will
368 * require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock
369 * cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be
370 * extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require
371 * 22 ADC clocks.
372 */
373#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
374/*! @} */
375
376/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
377/*! @{ */
378#define ADC_INSEL_SEL_MASK (0x3U)
379#define ADC_INSEL_SEL_SHIFT (0U)
380/*! SEL - Selects the input source for channel 0. All other values are reserved.
381 * 0b00..ADC0_IN0 function.
382 * 0b11..Internal temperature sensor.
383 */
384#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
385/*! @} */
386
387/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
388/*! @{ */
389#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU)
390#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U)
391/*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this
392 * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be
393 * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1
394 * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via
395 * software command, ADC conversions will be performed on each enabled channel, in sequence,
396 * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31)
397 * is LOW. It is allowed to change this field and set bit 31 in the same write.
398 */
399#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
400#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U)
401#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U)
402/*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion
403 * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order
404 * to avoid generating a spurious trigger, it is recommended writing to this field only when
405 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
406 */
407#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
408#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U)
409#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U)
410/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In
411 * order to avoid generating a spurious trigger, it is recommended writing to this field only when
412 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
413 * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
414 * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
415 */
416#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
417#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U)
418#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U)
419/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization
420 * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a
421 * conversion. There are slightly different criteria for whether or not this bit can be set
422 * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0):
423 * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already
424 * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer).
425 * Whether this bit is set or not, a trigger pulse must be maintained for at least one system
426 * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be
427 * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse
428 * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and
429 * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be
430 * maintained for one system clock period.
431 * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled.
432 * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled.
433 */
434#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
435#define ADC_SEQ_CTRL_START_MASK (0x4000000U)
436#define ADC_SEQ_CTRL_START_SHIFT (26U)
437/*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The
438 * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this
439 * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a
440 * conversion sequence. It will consequently always read back as a zero.
441 */
442#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
443#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U)
444#define ADC_SEQ_CTRL_BURST_SHIFT (27U)
445/*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled
446 * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions
447 * can be halted by clearing this bit. The sequence currently in progress will be completed before
448 * conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
449 */
450#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
451#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U)
452#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U)
453/*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a
454 * single conversion on the next channel in the sequence instead of the default response of
455 * launching an entire sequence of conversions. Once all of the channels comprising a sequence have
456 * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled
457 * channel. Interrupt generation will still occur either after each individual conversion or at
458 * the end of the entire sequence, depending on the state of the MODE bit.
459 */
460#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
461#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U)
462#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U)
463/*! LOWPRIO - Set priority for sequence A.
464 * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
465 * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence
466 * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion
467 * currently in progress will be terminated. The A sequence that was interrupted will automatically resume
468 * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the
469 * conversion sequence will resume from that point.
470 */
471#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
472#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U)
473#define ADC_SEQ_CTRL_MODE_SHIFT (30U)
474/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence
475 * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each
476 * conversion, or the individual channel result registers at the end of the entire sequence. Impacts
477 * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which
478 * overrun conditions contribute to an overrun interrupt as described below.
479 * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC
480 * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The
481 * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger
482 * if enabled.
483 * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A
484 * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in
485 * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun
486 * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
487 */
488#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
489#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U)
490#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U)
491/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be
492 * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state
493 * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered
494 * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care
495 * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE
496 * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be
497 * triggered immediately upon being enabled.
498 * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence
499 * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is
500 * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
501 * 0b1..Enabled. Sequence n is enabled.
502 */
503#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
504/*! @} */
505
506/* The count of ADC_SEQ_CTRL */
507#define ADC_SEQ_CTRL_COUNT (2U)
508
509/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
510/*! @{ */
511#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U)
512#define ADC_SEQ_GDAT_RESULT_SHIFT (4U)
513/*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion
514 * performed under conversion sequence associated with this register. The result is a binary
515 * fraction representing the voltage on the currently-selected input channel as it falls within the
516 * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less
517 * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input
518 * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this
519 * result has not yet been read.
520 */
521#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
522#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U)
523#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U)
524/*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or
525 * within the range established by the designated threshold comparison registers (THRn_LOW and
526 * THRn_HIGH).
527 */
528#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
529#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U)
530#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U)
531/*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a
532 * crossing of the threshold level established by the designated LOW threshold comparison register
533 * (THRn_LOW) and, if so, in what direction the crossing occurred.
534 */
535#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
536#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U)
537#define ADC_SEQ_GDAT_CHN_SHIFT (26U)
538/*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000
539 * identifies channel 0, 0001 channel 1, etc.).
540 */
541#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
542#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U)
543#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U)
544/*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a
545 * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along
546 * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun
547 * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set
548 * to '0' (and if the overrun interrupt is enabled).
549 */
550#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
551#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U)
552#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U)
553/*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded
554 * into the RESULT field. It is cleared whenever this register is read. This bit will cause a
555 * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that
556 * sequence is set to 0 (and if the interrupt is enabled).
557 */
558#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
559/*! @} */
560
561/* The count of ADC_SEQ_GDAT */
562#define ADC_SEQ_GDAT_COUNT (2U)
563
564/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
565/*! @{ */
566#define ADC_DAT_RESULT_MASK (0xFFF0U)
567#define ADC_DAT_RESULT_SHIFT (4U)
568/*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed
569 * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin,
570 * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on
571 * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that
572 * the voltage on the input was close to, equal to, or greater than that on VREFP.
573 */
574#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
575#define ADC_DAT_THCMPRANGE_MASK (0x30000U)
576#define ADC_DAT_THCMPRANGE_SHIFT (16U)
577/*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion
578 * was greater than or equal to the value programmed into the designated LOW threshold register
579 * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold
580 * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value
581 * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last
582 * completed conversion was greater than the value programmed into the designated HIGH threshold
583 * register (THRn_HIGH). 0x3 = Reserved.
584 */
585#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
586#define ADC_DAT_THCMPCROSS_MASK (0xC0000U)
587#define ADC_DAT_THCMPCROSS_SHIFT (18U)
588/*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The
589 * most recent completed conversion on this channel had the same relationship (above or below) to
590 * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the
591 * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing
592 * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the
593 * previous sample on this channel was above the threshold value established by the designated LOW
594 * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward
595 * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred
596 * - i.e. the previous sample on this channel was below the threshold value established by the
597 * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
598 */
599#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
600#define ADC_DAT_CHANNEL_MASK (0x3C000000U)
601#define ADC_DAT_CHANNEL_SHIFT (26U)
602/*! CHANNEL - This field is hard-coded to contain the channel number that this particular register
603 * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1
604 * register, etc)
605 */
606#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
607#define ADC_DAT_OVERRUN_MASK (0x40000000U)
608#define ADC_DAT_OVERRUN_SHIFT (30U)
609/*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and
610 * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit
611 * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when
612 * the data related to this channel is read from either of the global SEQn_GDAT registers. This
613 * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if
614 * the overrun interrupt is enabled. While it is allowed to include the same channels in both
615 * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the
616 * data registers associated with any of the channels that are shared between the two sequences. Any
617 * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
618 */
619#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
620#define ADC_DAT_DATAVALID_MASK (0x80000000U)
621#define ADC_DAT_DATAVALID_SHIFT (31U)
622/*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is
623 * cleared whenever this register is read or when the data related to this channel is read from
624 * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in
625 * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in
626 * the data registers associated with any of the channels that are shared between the two
627 * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
628 */
629#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
630/*! @} */
631
632/* The count of ADC_DAT */
633#define ADC_DAT_COUNT (12U)
634
635/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
636/*! @{ */
637#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U)
638#define ADC_THR0_LOW_THRLOW_SHIFT (4U)
639/*! THRLOW - Low threshold value against which ADC results will be compared
640 */
641#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
642/*! @} */
643
644/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
645/*! @{ */
646#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U)
647#define ADC_THR1_LOW_THRLOW_SHIFT (4U)
648/*! THRLOW - Low threshold value against which ADC results will be compared
649 */
650#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
651/*! @} */
652
653/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
654/*! @{ */
655#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U)
656#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U)
657/*! THRHIGH - High threshold value against which ADC results will be compared
658 */
659#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
660/*! @} */
661
662/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
663/*! @{ */
664#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U)
665#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U)
666/*! THRHIGH - High threshold value against which ADC results will be compared
667 */
668#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
669/*! @} */
670
671/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
672/*! @{ */
673#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U)
674#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U)
675/*! CH0_THRSEL - Threshold select for channel 0.
676 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
677 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
678 */
679#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
680#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U)
681#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U)
682/*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0.
683 */
684#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
685#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U)
686#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U)
687/*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0.
688 */
689#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
690#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U)
691#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U)
692/*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0.
693 */
694#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
695#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U)
696#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U)
697/*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0.
698 */
699#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
700#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U)
701#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U)
702/*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0.
703 */
704#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
705#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U)
706#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U)
707/*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0.
708 */
709#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
710#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U)
711#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U)
712/*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0.
713 */
714#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
715#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U)
716#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U)
717/*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0.
718 */
719#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
720#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U)
721#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U)
722/*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0.
723 */
724#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
725#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U)
726#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U)
727/*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0.
728 */
729#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
730#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U)
731#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U)
732/*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0.
733 */
734#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
735/*! @} */
736
737/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
738/*! @{ */
739#define ADC_INTEN_SEQA_INTEN_MASK (0x1U)
740#define ADC_INTEN_SEQA_INTEN_SHIFT (0U)
741/*! SEQA_INTEN - Sequence A interrupt enable.
742 * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled.
743 * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of
744 * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of
745 * conversions, depending on the MODE bit in the SEQA_CTRL register.
746 */
747#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
748#define ADC_INTEN_SEQB_INTEN_MASK (0x2U)
749#define ADC_INTEN_SEQB_INTEN_SHIFT (1U)
750/*! SEQB_INTEN - Sequence B interrupt enable.
751 * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled.
752 * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of
753 * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of
754 * conversions, depending on the MODE bit in the SEQB_CTRL register.
755 */
756#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
757#define ADC_INTEN_OVR_INTEN_MASK (0x4U)
758#define ADC_INTEN_OVR_INTEN_SHIFT (2U)
759/*! OVR_INTEN - Overrun interrupt enable.
760 * 0b0..Disabled. The overrun interrupt is disabled.
761 * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel
762 * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular
763 * sequence is 0, then an overrun in the global data register for that sequence will also cause this
764 * interrupt/DMA trigger to be asserted.
765 */
766#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
767#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U)
768#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U)
769/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0.
770 * 0b00..Disabled.
771 * 0b01..Outside threshold.
772 * 0b10..Crossing threshold.
773 * 0b11..Reserved
774 */
775#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
776#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U)
777#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U)
778/*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0.
779 */
780#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
781#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U)
782#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U)
783/*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0.
784 */
785#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
786#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U)
787#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U)
788/*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0.
789 */
790#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
791#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U)
792#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U)
793/*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0.
794 */
795#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
796#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U)
797#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U)
798/*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0.
799 */
800#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
801#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U)
802#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U)
803/*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0.
804 */
805#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
806#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U)
807#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U)
808/*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0.
809 */
810#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
811#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U)
812#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U)
813/*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0.
814 */
815#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
816#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U)
817#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U)
818/*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0.
819 */
820#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
821#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U)
822#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U)
823/*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0.
824 */
825#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
826#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U)
827#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U)
828/*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0.
829 */
830#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
831/*! @} */
832
833/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
834/*! @{ */
835#define ADC_FLAGS_THCMP0_MASK (0x1U)
836#define ADC_FLAGS_THCMP0_SHIFT (0U)
837/*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or
838 * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by
839 * writing a 1.
840 */
841#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
842#define ADC_FLAGS_THCMP1_MASK (0x2U)
843#define ADC_FLAGS_THCMP1_SHIFT (1U)
844/*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0.
845 */
846#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
847#define ADC_FLAGS_THCMP2_MASK (0x4U)
848#define ADC_FLAGS_THCMP2_SHIFT (2U)
849/*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0.
850 */
851#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
852#define ADC_FLAGS_THCMP3_MASK (0x8U)
853#define ADC_FLAGS_THCMP3_SHIFT (3U)
854/*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0.
855 */
856#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
857#define ADC_FLAGS_THCMP4_MASK (0x10U)
858#define ADC_FLAGS_THCMP4_SHIFT (4U)
859/*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0.
860 */
861#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
862#define ADC_FLAGS_THCMP5_MASK (0x20U)
863#define ADC_FLAGS_THCMP5_SHIFT (5U)
864/*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0.
865 */
866#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
867#define ADC_FLAGS_THCMP6_MASK (0x40U)
868#define ADC_FLAGS_THCMP6_SHIFT (6U)
869/*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0.
870 */
871#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
872#define ADC_FLAGS_THCMP7_MASK (0x80U)
873#define ADC_FLAGS_THCMP7_SHIFT (7U)
874/*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0.
875 */
876#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
877#define ADC_FLAGS_THCMP8_MASK (0x100U)
878#define ADC_FLAGS_THCMP8_SHIFT (8U)
879/*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0.
880 */
881#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
882#define ADC_FLAGS_THCMP9_MASK (0x200U)
883#define ADC_FLAGS_THCMP9_SHIFT (9U)
884/*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0.
885 */
886#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
887#define ADC_FLAGS_THCMP10_MASK (0x400U)
888#define ADC_FLAGS_THCMP10_SHIFT (10U)
889/*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0.
890 */
891#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
892#define ADC_FLAGS_THCMP11_MASK (0x800U)
893#define ADC_FLAGS_THCMP11_SHIFT (11U)
894/*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0.
895 */
896#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
897#define ADC_FLAGS_OVERRUN0_MASK (0x1000U)
898#define ADC_FLAGS_OVERRUN0_SHIFT (12U)
899/*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0
900 */
901#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
902#define ADC_FLAGS_OVERRUN1_MASK (0x2000U)
903#define ADC_FLAGS_OVERRUN1_SHIFT (13U)
904/*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1
905 */
906#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
907#define ADC_FLAGS_OVERRUN2_MASK (0x4000U)
908#define ADC_FLAGS_OVERRUN2_SHIFT (14U)
909/*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2
910 */
911#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
912#define ADC_FLAGS_OVERRUN3_MASK (0x8000U)
913#define ADC_FLAGS_OVERRUN3_SHIFT (15U)
914/*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3
915 */
916#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
917#define ADC_FLAGS_OVERRUN4_MASK (0x10000U)
918#define ADC_FLAGS_OVERRUN4_SHIFT (16U)
919/*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4
920 */
921#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
922#define ADC_FLAGS_OVERRUN5_MASK (0x20000U)
923#define ADC_FLAGS_OVERRUN5_SHIFT (17U)
924/*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5
925 */
926#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
927#define ADC_FLAGS_OVERRUN6_MASK (0x40000U)
928#define ADC_FLAGS_OVERRUN6_SHIFT (18U)
929/*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6
930 */
931#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
932#define ADC_FLAGS_OVERRUN7_MASK (0x80000U)
933#define ADC_FLAGS_OVERRUN7_SHIFT (19U)
934/*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7
935 */
936#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
937#define ADC_FLAGS_OVERRUN8_MASK (0x100000U)
938#define ADC_FLAGS_OVERRUN8_SHIFT (20U)
939/*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8
940 */
941#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
942#define ADC_FLAGS_OVERRUN9_MASK (0x200000U)
943#define ADC_FLAGS_OVERRUN9_SHIFT (21U)
944/*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9
945 */
946#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
947#define ADC_FLAGS_OVERRUN10_MASK (0x400000U)
948#define ADC_FLAGS_OVERRUN10_SHIFT (22U)
949/*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10
950 */
951#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
952#define ADC_FLAGS_OVERRUN11_MASK (0x800000U)
953#define ADC_FLAGS_OVERRUN11_SHIFT (23U)
954/*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11
955 */
956#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
957#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U)
958#define ADC_FLAGS_SEQA_OVR_SHIFT (24U)
959/*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register
960 */
961#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
962#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U)
963#define ADC_FLAGS_SEQB_OVR_SHIFT (25U)
964/*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register
965 */
966#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
967#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U)
968#define ADC_FLAGS_SEQA_INT_SHIFT (28U)
969/*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0,
970 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which
971 * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared
972 * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register
973 * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be
974 * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN
975 * register.
976 */
977#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
978#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U)
979#define ADC_FLAGS_SEQB_INT_SHIFT (29U)
980/*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0,
981 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which
982 * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared
983 * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register
984 * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be
985 * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN
986 * register.
987 */
988#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
989#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U)
990#define ADC_FLAGS_THCMP_INT_SHIFT (30U)
991/*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in
992 * the lower bits of this register are set to 1 (due to an enabled out-of-range or
993 * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be
994 * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared
995 * when all of the individual threshold flags are cleared via writing 1s to those bits.
996 */
997#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
998#define ADC_FLAGS_OVR_INT_MASK (0x80000000U)
999#define ADC_FLAGS_OVR_INT_SHIFT (31U)
1000/*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data
1001 * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers
1002 * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this
1003 * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all
1004 * of the individual overrun bits have been cleared via reading the corresponding data registers.
1005 */
1006#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
1007/*! @} */
1008
1009/*! @name STARTUP - ADC Startup register. */
1010/*! @{ */
1011#define ADC_STARTUP_ADC_ENA_MASK (0x1U)
1012#define ADC_STARTUP_ADC_ENA_SHIFT (0U)
1013/*! ADC_ENA - ADC Enable bit. This bit can only be set to a 1 by software. It is cleared
1014 * automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds
1015 * after the ADC is powered up (typically by altering a system-level ADC power control bit).
1016 */
1017#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
1018#define ADC_STARTUP_ADC_INIT_MASK (0x2U)
1019#define ADC_STARTUP_ADC_INIT_SHIFT (1U)
1020/*! ADC_INIT - ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine
1021 * will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not
1022 * calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is
1023 * required if a calibration is not performed. It will also reload the stored calibration value from
1024 * a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the
1025 * ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or
1026 * an ADC dummy conversion cycle is required. It should not be set during the same write that
1027 * sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically
1028 * when the 'dummy' conversion cycle completes.
1029 */
1030#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
1031/*! @} */
1032
1033/*! @name CALIB - ADC Calibration register. */
1034/*! @{ */
1035#define ADC_CALIB_CALIB_MASK (0x1U)
1036#define ADC_CALIB_CALIB_SHIFT (0U)
1037/*! CALIB - Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can
1038 * only be set to a '1' by software. It is cleared automatically when the calibration cycle
1039 * completes.
1040 */
1041#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
1042#define ADC_CALIB_CALREQD_MASK (0x2U)
1043#define ADC_CALIB_CALREQD_SHIFT (1U)
1044/*! CALREQD - Calibration required. This read-only bit indicates if calibration is required when
1045 * enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was
1046 * powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to
1047 * determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP
1048 * register) to launch the ADC initialization process which includes a 'dummy' conversion cycle.
1049 * Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks
1050 * required for calibration.
1051 */
1052#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
1053#define ADC_CALIB_CALVALUE_MASK (0x1FCU)
1054#define ADC_CALIB_CALVALUE_SHIFT (2U)
1055/*! CALVALUE - Calibration Value. This read-only field displays the calibration value established
1056 * during last calibration cycle. This value is not typically of any use to the user.
1057 */
1058#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
1059/*! @} */
1060
1061
1062/*!
1063 * @}
1064 */ /* end of group ADC_Register_Masks */
1065
1066
1067/* ADC - Peripheral instance base addresses */
1068/** Peripheral ADC0 base address */
1069#define ADC0_BASE (0x400A0000u)
1070/** Peripheral ADC0 base pointer */
1071#define ADC0 ((ADC_Type *)ADC0_BASE)
1072/** Array initializer of ADC peripheral base addresses */
1073#define ADC_BASE_ADDRS { ADC0_BASE }
1074/** Array initializer of ADC peripheral base pointers */
1075#define ADC_BASE_PTRS { ADC0 }
1076/** Interrupt vectors for the ADC peripheral type */
1077#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
1078#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn }
1079
1080/*!
1081 * @}
1082 */ /* end of group ADC_Peripheral_Access_Layer */
1083
1084
1085/* ----------------------------------------------------------------------------
1086 -- ASYNC_SYSCON Peripheral Access Layer
1087 ---------------------------------------------------------------------------- */
1088
1089/*!
1090 * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
1091 * @{
1092 */
1093
1094/** ASYNC_SYSCON - Register Layout Typedef */
1095typedef struct {
1096 __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */
1097 __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
1098 __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
1099 uint8_t RESERVED_0[4];
1100 __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */
1101 __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
1102 __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
1103 uint8_t RESERVED_1[4];
1104 __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */
1105} ASYNC_SYSCON_Type;
1106
1107/* ----------------------------------------------------------------------------
1108 -- ASYNC_SYSCON Register Masks
1109 ---------------------------------------------------------------------------- */
1110
1111/*!
1112 * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
1113 * @{
1114 */
1115
1116/*! @name ASYNCPRESETCTRL - Async peripheral reset control */
1117/*! @{ */
1118#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
1119#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
1120/*! CTIMER3 - Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
1121 */
1122#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
1123#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
1124#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
1125/*! CTIMER4 - Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
1126 */
1127#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
1128/*! @} */
1129
1130/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
1131/*! @{ */
1132#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
1133#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
1134/*! ARST_SET - Writing ones to this register sets the corresponding bit or bits in the
1135 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1136 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1137 */
1138#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
1139/*! @} */
1140
1141/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
1142/*! @{ */
1143#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
1144#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
1145/*! ARST_CLR - Writing ones to this register clears the corresponding bit or bits in the
1146 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1147 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1148 */
1149#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
1150/*! @} */
1151
1152/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
1153/*! @{ */
1154#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
1155#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
1156/*! CTIMER3 - Controls the clock for CTIMER3. 0 = Disable; 1 = Enable.
1157 */
1158#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
1159#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
1160#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
1161/*! CTIMER4 - Controls the clock for CTIMER4. 0 = Disable; 1 = Enable.
1162 */
1163#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
1164/*! @} */
1165
1166/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
1167/*! @{ */
1168#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
1169#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
1170/*! ACLK_SET - Writing ones to this register sets the corresponding bit or bits in the
1171 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1172 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1173 */
1174#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
1175/*! @} */
1176
1177/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
1178/*! @{ */
1179#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
1180#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
1181/*! ACLK_CLR - Writing ones to this register clears the corresponding bit or bits in the
1182 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1183 * ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them.
1184 */
1185#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
1186/*! @} */
1187
1188/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
1189/*! @{ */
1190#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U)
1191#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U)
1192/*! SEL - Clock source for asynchronous clock source selector A
1193 * 0b00..Main clock (main_clk)
1194 * 0b01..FRO 12 MHz (fro_12m)
1195 * 0b10..Audio PLL clock.(AUDPLL_BYPASS)
1196 * 0b11..fc6 fclk (fc6_fclk)
1197 */
1198#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
1199/*! @} */
1200
1201
1202/*!
1203 * @}
1204 */ /* end of group ASYNC_SYSCON_Register_Masks */
1205
1206
1207/* ASYNC_SYSCON - Peripheral instance base addresses */
1208/** Peripheral ASYNC_SYSCON base address */
1209#define ASYNC_SYSCON_BASE (0x40040000u)
1210/** Peripheral ASYNC_SYSCON base pointer */
1211#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
1212/** Array initializer of ASYNC_SYSCON peripheral base addresses */
1213#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE }
1214/** Array initializer of ASYNC_SYSCON peripheral base pointers */
1215#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON }
1216
1217/*!
1218 * @}
1219 */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
1220
1221
1222/* ----------------------------------------------------------------------------
1223 -- CRC Peripheral Access Layer
1224 ---------------------------------------------------------------------------- */
1225
1226/*!
1227 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
1228 * @{
1229 */
1230
1231/** CRC - Register Layout Typedef */
1232typedef struct {
1233 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
1234 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
1235 union { /* offset: 0x8 */
1236 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
1237 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
1238 };
1239} CRC_Type;
1240
1241/* ----------------------------------------------------------------------------
1242 -- CRC Register Masks
1243 ---------------------------------------------------------------------------- */
1244
1245/*!
1246 * @addtogroup CRC_Register_Masks CRC Register Masks
1247 * @{
1248 */
1249
1250/*! @name MODE - CRC mode register */
1251/*! @{ */
1252#define CRC_MODE_CRC_POLY_MASK (0x3U)
1253#define CRC_MODE_CRC_POLY_SHIFT (0U)
1254/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
1255 */
1256#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
1257#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
1258#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
1259/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
1260 */
1261#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
1262#define CRC_MODE_CMPL_WR_MASK (0x8U)
1263#define CRC_MODE_CMPL_WR_SHIFT (3U)
1264/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
1265 */
1266#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
1267#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
1268#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
1269/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
1270 */
1271#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
1272#define CRC_MODE_CMPL_SUM_MASK (0x20U)
1273#define CRC_MODE_CMPL_SUM_SHIFT (5U)
1274/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
1275 */
1276#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
1277/*! @} */
1278
1279/*! @name SEED - CRC seed register */
1280/*! @{ */
1281#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
1282#define CRC_SEED_CRC_SEED_SHIFT (0U)
1283/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
1284 * selected bit order and 1's complement pre-processes. A write access to this register will
1285 * overrule the CRC calculation in progresses.
1286 */
1287#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
1288/*! @} */
1289
1290/*! @name SUM - CRC checksum register */
1291/*! @{ */
1292#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
1293#define CRC_SUM_CRC_SUM_SHIFT (0U)
1294/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
1295 */
1296#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
1297/*! @} */
1298
1299/*! @name WR_DATA - CRC data register */
1300/*! @{ */
1301#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
1302#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
1303/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
1304 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
1305 * accept back-to-back transactions.
1306 */
1307#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
1308/*! @} */
1309
1310
1311/*!
1312 * @}
1313 */ /* end of group CRC_Register_Masks */
1314
1315
1316/* CRC - Peripheral instance base addresses */
1317/** Peripheral CRC_ENGINE base address */
1318#define CRC_ENGINE_BASE (0x40095000u)
1319/** Peripheral CRC_ENGINE base pointer */
1320#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
1321/** Array initializer of CRC peripheral base addresses */
1322#define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
1323/** Array initializer of CRC peripheral base pointers */
1324#define CRC_BASE_PTRS { CRC_ENGINE }
1325
1326/*!
1327 * @}
1328 */ /* end of group CRC_Peripheral_Access_Layer */
1329
1330
1331/* ----------------------------------------------------------------------------
1332 -- CTIMER Peripheral Access Layer
1333 ---------------------------------------------------------------------------- */
1334
1335/*!
1336 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
1337 * @{
1338 */
1339
1340/** CTIMER - Register Layout Typedef */
1341typedef struct {
1342 __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
1343 __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
1344 __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */
1345 __IO uint32_t PR; /**< Prescale Register, offset: 0xC */
1346 __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */
1347 __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */
1348 __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
1349 __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
1350 __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
1351 __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
1352 uint8_t RESERVED_0[48];
1353 __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
1354 __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
1355 __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
1356} CTIMER_Type;
1357
1358/* ----------------------------------------------------------------------------
1359 -- CTIMER Register Masks
1360 ---------------------------------------------------------------------------- */
1361
1362/*!
1363 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
1364 * @{
1365 */
1366
1367/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
1368/*! @{ */
1369#define CTIMER_IR_MR0INT_MASK (0x1U)
1370#define CTIMER_IR_MR0INT_SHIFT (0U)
1371/*! MR0INT - Interrupt flag for match channel 0.
1372 */
1373#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
1374#define CTIMER_IR_MR1INT_MASK (0x2U)
1375#define CTIMER_IR_MR1INT_SHIFT (1U)
1376/*! MR1INT - Interrupt flag for match channel 1.
1377 */
1378#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
1379#define CTIMER_IR_MR2INT_MASK (0x4U)
1380#define CTIMER_IR_MR2INT_SHIFT (2U)
1381/*! MR2INT - Interrupt flag for match channel 2.
1382 */
1383#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
1384#define CTIMER_IR_MR3INT_MASK (0x8U)
1385#define CTIMER_IR_MR3INT_SHIFT (3U)
1386/*! MR3INT - Interrupt flag for match channel 3.
1387 */
1388#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
1389#define CTIMER_IR_CR0INT_MASK (0x10U)
1390#define CTIMER_IR_CR0INT_SHIFT (4U)
1391/*! CR0INT - Interrupt flag for capture channel 0 event.
1392 */
1393#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
1394#define CTIMER_IR_CR1INT_MASK (0x20U)
1395#define CTIMER_IR_CR1INT_SHIFT (5U)
1396/*! CR1INT - Interrupt flag for capture channel 1 event.
1397 */
1398#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
1399#define CTIMER_IR_CR2INT_MASK (0x40U)
1400#define CTIMER_IR_CR2INT_SHIFT (6U)
1401/*! CR2INT - Interrupt flag for capture channel 2 event.
1402 */
1403#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
1404#define CTIMER_IR_CR3INT_MASK (0x80U)
1405#define CTIMER_IR_CR3INT_SHIFT (7U)
1406/*! CR3INT - Interrupt flag for capture channel 3 event.
1407 */
1408#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
1409/*! @} */
1410
1411/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
1412/*! @{ */
1413#define CTIMER_TCR_CEN_MASK (0x1U)
1414#define CTIMER_TCR_CEN_SHIFT (0U)
1415/*! CEN - Counter enable.
1416 * 0b0..Disabled.The counters are disabled.
1417 * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
1418 */
1419#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
1420#define CTIMER_TCR_CRST_MASK (0x2U)
1421#define CTIMER_TCR_CRST_SHIFT (1U)
1422/*! CRST - Counter reset.
1423 * 0b0..Disabled. Do nothing.
1424 * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
1425 * the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
1426 */
1427#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
1428/*! @} */
1429
1430/*! @name TC - Timer Counter */
1431/*! @{ */
1432#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
1433#define CTIMER_TC_TCVAL_SHIFT (0U)
1434/*! TCVAL - Timer counter value.
1435 */
1436#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
1437/*! @} */
1438
1439/*! @name PR - Prescale Register */
1440/*! @{ */
1441#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
1442#define CTIMER_PR_PRVAL_SHIFT (0U)
1443/*! PRVAL - Prescale counter value.
1444 */
1445#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
1446/*! @} */
1447
1448/*! @name PC - Prescale Counter */
1449/*! @{ */
1450#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
1451#define CTIMER_PC_PCVAL_SHIFT (0U)
1452/*! PCVAL - Prescale counter value.
1453 */
1454#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
1455/*! @} */
1456
1457/*! @name MCR - Match Control Register */
1458/*! @{ */
1459#define CTIMER_MCR_MR0I_MASK (0x1U)
1460#define CTIMER_MCR_MR0I_SHIFT (0U)
1461/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
1462 */
1463#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
1464#define CTIMER_MCR_MR0R_MASK (0x2U)
1465#define CTIMER_MCR_MR0R_SHIFT (1U)
1466/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it.
1467 */
1468#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
1469#define CTIMER_MCR_MR0S_MASK (0x4U)
1470#define CTIMER_MCR_MR0S_SHIFT (2U)
1471/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
1472 */
1473#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
1474#define CTIMER_MCR_MR1I_MASK (0x8U)
1475#define CTIMER_MCR_MR1I_SHIFT (3U)
1476/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
1477 */
1478#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
1479#define CTIMER_MCR_MR1R_MASK (0x10U)
1480#define CTIMER_MCR_MR1R_SHIFT (4U)
1481/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it.
1482 */
1483#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
1484#define CTIMER_MCR_MR1S_MASK (0x20U)
1485#define CTIMER_MCR_MR1S_SHIFT (5U)
1486/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
1487 */
1488#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
1489#define CTIMER_MCR_MR2I_MASK (0x40U)
1490#define CTIMER_MCR_MR2I_SHIFT (6U)
1491/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
1492 */
1493#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
1494#define CTIMER_MCR_MR2R_MASK (0x80U)
1495#define CTIMER_MCR_MR2R_SHIFT (7U)
1496/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it.
1497 */
1498#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
1499#define CTIMER_MCR_MR2S_MASK (0x100U)
1500#define CTIMER_MCR_MR2S_SHIFT (8U)
1501/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
1502 */
1503#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
1504#define CTIMER_MCR_MR3I_MASK (0x200U)
1505#define CTIMER_MCR_MR3I_SHIFT (9U)
1506/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
1507 */
1508#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
1509#define CTIMER_MCR_MR3R_MASK (0x400U)
1510#define CTIMER_MCR_MR3R_SHIFT (10U)
1511/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it.
1512 */
1513#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
1514#define CTIMER_MCR_MR3S_MASK (0x800U)
1515#define CTIMER_MCR_MR3S_SHIFT (11U)
1516/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
1517 */
1518#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
1519#define CTIMER_MCR_MR0RL_MASK (0x1000000U)
1520#define CTIMER_MCR_MR0RL_SHIFT (24U)
1521/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
1522 * (either via a match event or a write to bit 1 of the TCR).
1523 */
1524#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
1525#define CTIMER_MCR_MR1RL_MASK (0x2000000U)
1526#define CTIMER_MCR_MR1RL_SHIFT (25U)
1527/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
1528 * (either via a match event or a write to bit 1 of the TCR).
1529 */
1530#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
1531#define CTIMER_MCR_MR2RL_MASK (0x4000000U)
1532#define CTIMER_MCR_MR2RL_SHIFT (26U)
1533/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
1534 * (either via a match event or a write to bit 1 of the TCR).
1535 */
1536#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
1537#define CTIMER_MCR_MR3RL_MASK (0x8000000U)
1538#define CTIMER_MCR_MR3RL_SHIFT (27U)
1539/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
1540 * (either via a match event or a write to bit 1 of the TCR).
1541 */
1542#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
1543/*! @} */
1544
1545/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
1546/*! @{ */
1547#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
1548#define CTIMER_MR_MATCH_SHIFT (0U)
1549/*! MATCH - Timer counter match value.
1550 */
1551#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
1552/*! @} */
1553
1554/* The count of CTIMER_MR */
1555#define CTIMER_MR_COUNT (4U)
1556
1557/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
1558/*! @{ */
1559#define CTIMER_CCR_CAP0RE_MASK (0x1U)
1560#define CTIMER_CCR_CAP0RE_SHIFT (0U)
1561/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
1562 * the contents of TC. 0 = disabled. 1 = enabled.
1563 */
1564#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
1565#define CTIMER_CCR_CAP0FE_MASK (0x2U)
1566#define CTIMER_CCR_CAP0FE_SHIFT (1U)
1567/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
1568 * the contents of TC. 0 = disabled. 1 = enabled.
1569 */
1570#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
1571#define CTIMER_CCR_CAP0I_MASK (0x4U)
1572#define CTIMER_CCR_CAP0I_SHIFT (2U)
1573/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
1574 */
1575#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
1576#define CTIMER_CCR_CAP1RE_MASK (0x8U)
1577#define CTIMER_CCR_CAP1RE_SHIFT (3U)
1578/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
1579 * the contents of TC. 0 = disabled. 1 = enabled.
1580 */
1581#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
1582#define CTIMER_CCR_CAP1FE_MASK (0x10U)
1583#define CTIMER_CCR_CAP1FE_SHIFT (4U)
1584/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
1585 * the contents of TC. 0 = disabled. 1 = enabled.
1586 */
1587#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
1588#define CTIMER_CCR_CAP1I_MASK (0x20U)
1589#define CTIMER_CCR_CAP1I_SHIFT (5U)
1590/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
1591 */
1592#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
1593#define CTIMER_CCR_CAP2RE_MASK (0x40U)
1594#define CTIMER_CCR_CAP2RE_SHIFT (6U)
1595/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
1596 * the contents of TC. 0 = disabled. 1 = enabled.
1597 */
1598#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
1599#define CTIMER_CCR_CAP2FE_MASK (0x80U)
1600#define CTIMER_CCR_CAP2FE_SHIFT (7U)
1601/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
1602 * the contents of TC. 0 = disabled. 1 = enabled.
1603 */
1604#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
1605#define CTIMER_CCR_CAP2I_MASK (0x100U)
1606#define CTIMER_CCR_CAP2I_SHIFT (8U)
1607/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
1608 */
1609#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
1610#define CTIMER_CCR_CAP3RE_MASK (0x200U)
1611#define CTIMER_CCR_CAP3RE_SHIFT (9U)
1612/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with
1613 * the contents of TC. 0 = disabled. 1 = enabled.
1614 */
1615#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
1616#define CTIMER_CCR_CAP3FE_MASK (0x400U)
1617#define CTIMER_CCR_CAP3FE_SHIFT (10U)
1618/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with
1619 * the contents of TC. 0 = disabled. 1 = enabled.
1620 */
1621#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
1622#define CTIMER_CCR_CAP3I_MASK (0x800U)
1623#define CTIMER_CCR_CAP3I_SHIFT (11U)
1624/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
1625 */
1626#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
1627/*! @} */
1628
1629/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
1630/*! @{ */
1631#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
1632#define CTIMER_CR_CAP_SHIFT (0U)
1633/*! CAP - Timer counter capture value.
1634 */
1635#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
1636/*! @} */
1637
1638/* The count of CTIMER_CR */
1639#define CTIMER_CR_COUNT (4U)
1640
1641/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
1642/*! @{ */
1643#define CTIMER_EMR_EM0_MASK (0x1U)
1644#define CTIMER_EMR_EM0_SHIFT (0U)
1645/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
1646 * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
1647 * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
1648 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1649 */
1650#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
1651#define CTIMER_EMR_EM1_MASK (0x2U)
1652#define CTIMER_EMR_EM1_SHIFT (1U)
1653/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
1654 * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
1655 * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
1656 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1657 */
1658#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
1659#define CTIMER_EMR_EM2_MASK (0x4U)
1660#define CTIMER_EMR_EM2_SHIFT (2U)
1661/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
1662 * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
1663 * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
1664 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1665 */
1666#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
1667#define CTIMER_EMR_EM3_MASK (0x8U)
1668#define CTIMER_EMR_EM3_SHIFT (3U)
1669/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
1670 * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
1671 * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
1672 * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1673 */
1674#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
1675#define CTIMER_EMR_EMC0_MASK (0x30U)
1676#define CTIMER_EMR_EMC0_SHIFT (4U)
1677/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
1678 * 0b00..Do Nothing.
1679 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
1680 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
1681 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
1682 */
1683#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
1684#define CTIMER_EMR_EMC1_MASK (0xC0U)
1685#define CTIMER_EMR_EMC1_SHIFT (6U)
1686/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
1687 * 0b00..Do Nothing.
1688 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
1689 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
1690 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
1691 */
1692#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
1693#define CTIMER_EMR_EMC2_MASK (0x300U)
1694#define CTIMER_EMR_EMC2_SHIFT (8U)
1695/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
1696 * 0b00..Do Nothing.
1697 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
1698 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
1699 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
1700 */
1701#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
1702#define CTIMER_EMR_EMC3_MASK (0xC00U)
1703#define CTIMER_EMR_EMC3_SHIFT (10U)
1704/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
1705 * 0b00..Do Nothing.
1706 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
1707 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
1708 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
1709 */
1710#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
1711/*! @} */
1712
1713/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
1714/*! @{ */
1715#define CTIMER_CTCR_CTMODE_MASK (0x3U)
1716#define CTIMER_CTCR_CTMODE_SHIFT (0U)
1717/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
1718 * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
1719 * is incremented when the Prescale Counter matches the Prescale Register.
1720 * 0b00..Timer Mode. Incremented every rising APB bus clock edge.
1721 * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
1722 * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
1723 * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
1724 */
1725#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
1726#define CTIMER_CTCR_CINSEL_MASK (0xCU)
1727#define CTIMER_CTCR_CINSEL_SHIFT (2U)
1728/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
1729 * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
1730 * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
1731 * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
1732 * same timer.
1733 * 0b00..Channel 0. CAPn.0 for CTIMERn
1734 * 0b01..Channel 1. CAPn.1 for CTIMERn
1735 * 0b10..Channel 2. CAPn.2 for CTIMERn
1736 * 0b11..Channel 3. CAPn.3 for CTIMERn
1737 */
1738#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
1739#define CTIMER_CTCR_ENCC_MASK (0x10U)
1740#define CTIMER_CTCR_ENCC_SHIFT (4U)
1741/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
1742 * capture-edge event specified in bits 7:5 occurs.
1743 */
1744#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
1745#define CTIMER_CTCR_SELCC_MASK (0xE0U)
1746#define CTIMER_CTCR_SELCC_SHIFT (5U)
1747/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
1748 * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
1749 * 0x3 and 0x6 to 0x7 are reserved.
1750 * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
1751 * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
1752 * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
1753 * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
1754 * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
1755 * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
1756 */
1757#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
1758/*! @} */
1759
1760/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
1761/*! @{ */
1762#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
1763#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
1764/*! PWMEN0 - PWM mode enable for channel0.
1765 * 0b0..Match. CTIMERn_MAT0 is controlled by EM0.
1766 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
1767 */
1768#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
1769#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
1770#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
1771/*! PWMEN1 - PWM mode enable for channel1.
1772 * 0b0..Match. CTIMERn_MAT01 is controlled by EM1.
1773 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
1774 */
1775#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
1776#define CTIMER_PWMC_PWMEN2_MASK (0x4U)
1777#define CTIMER_PWMC_PWMEN2_SHIFT (2U)
1778/*! PWMEN2 - PWM mode enable for channel2.
1779 * 0b0..Match. CTIMERn_MAT2 is controlled by EM2.
1780 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
1781 */
1782#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
1783#define CTIMER_PWMC_PWMEN3_MASK (0x8U)
1784#define CTIMER_PWMC_PWMEN3_SHIFT (3U)
1785/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
1786 * 0b0..Match. CTIMERn_MAT3 is controlled by EM3.
1787 * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
1788 */
1789#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
1790/*! @} */
1791
1792/*! @name MSR - Match Shadow Register */
1793/*! @{ */
1794#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU)
1795#define CTIMER_MSR_SHADOWW_SHIFT (0U)
1796/*! SHADOWW - Timer counter match shadow value.
1797 */
1798#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)
1799/*! @} */
1800
1801/* The count of CTIMER_MSR */
1802#define CTIMER_MSR_COUNT (4U)
1803
1804
1805/*!
1806 * @}
1807 */ /* end of group CTIMER_Register_Masks */
1808
1809
1810/* CTIMER - Peripheral instance base addresses */
1811/** Peripheral CTIMER0 base address */
1812#define CTIMER0_BASE (0x40008000u)
1813/** Peripheral CTIMER0 base pointer */
1814#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
1815/** Peripheral CTIMER1 base address */
1816#define CTIMER1_BASE (0x40009000u)
1817/** Peripheral CTIMER1 base pointer */
1818#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
1819/** Peripheral CTIMER2 base address */
1820#define CTIMER2_BASE (0x40028000u)
1821/** Peripheral CTIMER2 base pointer */
1822#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
1823/** Peripheral CTIMER3 base address */
1824#define CTIMER3_BASE (0x40048000u)
1825/** Peripheral CTIMER3 base pointer */
1826#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
1827/** Peripheral CTIMER4 base address */
1828#define CTIMER4_BASE (0x40049000u)
1829/** Peripheral CTIMER4 base pointer */
1830#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
1831/** Array initializer of CTIMER peripheral base addresses */
1832#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
1833/** Array initializer of CTIMER peripheral base pointers */
1834#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
1835/** Interrupt vectors for the CTIMER peripheral type */
1836#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
1837
1838/*!
1839 * @}
1840 */ /* end of group CTIMER_Peripheral_Access_Layer */
1841
1842
1843/* ----------------------------------------------------------------------------
1844 -- DMA Peripheral Access Layer
1845 ---------------------------------------------------------------------------- */
1846
1847/*!
1848 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
1849 * @{
1850 */
1851
1852/** DMA - Register Layout Typedef */
1853typedef struct {
1854 __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
1855 __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
1856 __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
1857 uint8_t RESERVED_0[20];
1858 struct { /* offset: 0x20, array step: 0x5C */
1859 __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
1860 uint8_t RESERVED_0[4];
1861 __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
1862 uint8_t RESERVED_1[4];
1863 __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
1864 uint8_t RESERVED_2[4];
1865 __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
1866 uint8_t RESERVED_3[4];
1867 __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
1868 uint8_t RESERVED_4[4];
1869 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
1870 uint8_t RESERVED_5[4];
1871 __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
1872 uint8_t RESERVED_6[4];
1873 __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
1874 uint8_t RESERVED_7[4];
1875 __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
1876 uint8_t RESERVED_8[4];
1877 __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
1878 uint8_t RESERVED_9[4];
1879 __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
1880 uint8_t RESERVED_10[4];
1881 __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
1882 } COMMON[1];
1883 uint8_t RESERVED_1[900];
1884 struct { /* offset: 0x400, array step: 0x10 */
1885 __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
1886 __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
1887 __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
1888 uint8_t RESERVED_0[4];
1889 } CHANNEL[30];
1890} DMA_Type;
1891
1892/* ----------------------------------------------------------------------------
1893 -- DMA Register Masks
1894 ---------------------------------------------------------------------------- */
1895
1896/*!
1897 * @addtogroup DMA_Register_Masks DMA Register Masks
1898 * @{
1899 */
1900
1901/*! @name CTRL - DMA control. */
1902/*! @{ */
1903#define DMA_CTRL_ENABLE_MASK (0x1U)
1904#define DMA_CTRL_ENABLE_SHIFT (0U)
1905/*! ENABLE - DMA controller master enable.
1906 * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
1907 * disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
1908 * 0b1..Enabled. The DMA controller is enabled.
1909 */
1910#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
1911/*! @} */
1912
1913/*! @name INTSTAT - Interrupt status. */
1914/*! @{ */
1915#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
1916#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
1917/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
1918 * 0b0..Not pending. No enabled interrupts are pending.
1919 * 0b1..Pending. At least one enabled interrupt is pending.
1920 */
1921#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
1922#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
1923#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
1924/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
1925 * 0b0..Not pending. No error interrupts are pending.
1926 * 0b1..Pending. At least one error interrupt is pending.
1927 */
1928#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
1929/*! @} */
1930
1931/*! @name SRAMBASE - SRAM address of the channel configuration table. */
1932/*! @{ */
1933#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
1934#define DMA_SRAMBASE_OFFSET_SHIFT (9U)
1935/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
1936 * table must begin on a 512 byte boundary.
1937 */
1938#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
1939/*! @} */
1940
1941/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
1942/*! @{ */
1943#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)
1944#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
1945/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
1946 * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
1947 */
1948#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
1949/*! @} */
1950
1951/* The count of DMA_COMMON_ENABLESET */
1952#define DMA_COMMON_ENABLESET_COUNT (1U)
1953
1954/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
1955/*! @{ */
1956#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)
1957#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
1958/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
1959 * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
1960 * are reserved.
1961 */
1962#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
1963/*! @} */
1964
1965/* The count of DMA_COMMON_ENABLECLR */
1966#define DMA_COMMON_ENABLECLR_COUNT (1U)
1967
1968/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
1969/*! @{ */
1970#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)
1971#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
1972/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
1973 * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
1974 */
1975#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
1976/*! @} */
1977
1978/* The count of DMA_COMMON_ACTIVE */
1979#define DMA_COMMON_ACTIVE_COUNT (1U)
1980
1981/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
1982/*! @{ */
1983#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)
1984#define DMA_COMMON_BUSY_BSY_SHIFT (0U)
1985/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
1986 * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
1987 */
1988#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
1989/*! @} */
1990
1991/* The count of DMA_COMMON_BUSY */
1992#define DMA_COMMON_BUSY_COUNT (1U)
1993
1994/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
1995/*! @{ */
1996#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)
1997#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
1998/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
1999 * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
2000 * not active. 1 = error interrupt is active.
2001 */
2002#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
2003/*! @} */
2004
2005/* The count of DMA_COMMON_ERRINT */
2006#define DMA_COMMON_ERRINT_COUNT (1U)
2007
2008/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
2009/*! @{ */
2010#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)
2011#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
2012/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
2013 * number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
2014 * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
2015 */
2016#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
2017/*! @} */
2018
2019/* The count of DMA_COMMON_INTENSET */
2020#define DMA_COMMON_INTENSET_COUNT (1U)
2021
2022/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
2023/*! @{ */
2024#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)
2025#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
2026/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
2027 * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
2028 * reserved.
2029 */
2030#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
2031/*! @} */
2032
2033/* The count of DMA_COMMON_INTENCLR */
2034#define DMA_COMMON_INTENCLR_COUNT (1U)
2035
2036/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
2037/*! @{ */
2038#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)
2039#define DMA_COMMON_INTA_IA_SHIFT (0U)
2040/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
2041 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
2042 * interrupt A is not active. 1 = the DMA channel interrupt A is active.
2043 */
2044#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
2045/*! @} */
2046
2047/* The count of DMA_COMMON_INTA */
2048#define DMA_COMMON_INTA_COUNT (1U)
2049
2050/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
2051/*! @{ */
2052#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)
2053#define DMA_COMMON_INTB_IB_SHIFT (0U)
2054/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
2055 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
2056 * interrupt B is not active. 1 = the DMA channel interrupt B is active.
2057 */
2058#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
2059/*! @} */
2060
2061/* The count of DMA_COMMON_INTB */
2062#define DMA_COMMON_INTB_COUNT (1U)
2063
2064/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
2065/*! @{ */
2066#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)
2067#define DMA_COMMON_SETVALID_SV_SHIFT (0U)
2068/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
2069 * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
2070 * VALIDPENDING control bit for DMA channel n
2071 */
2072#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
2073/*! @} */
2074
2075/* The count of DMA_COMMON_SETVALID */
2076#define DMA_COMMON_SETVALID_COUNT (1U)
2077
2078/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
2079/*! @{ */
2080#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)
2081#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
2082/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
2083 * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
2084 * sets the TRIG bit for DMA channel n.
2085 */
2086#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
2087/*! @} */
2088
2089/* The count of DMA_COMMON_SETTRIG */
2090#define DMA_COMMON_SETTRIG_COUNT (1U)
2091
2092/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
2093/*! @{ */
2094#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)
2095#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
2096/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
2097 * 1 = aborts DMA operations on channel n.
2098 */
2099#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
2100/*! @} */
2101
2102/* The count of DMA_COMMON_ABORT */
2103#define DMA_COMMON_ABORT_COUNT (1U)
2104
2105/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
2106/*! @{ */
2107#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
2108#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
2109/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
2110 * move, any peripheral DMA request associated with that channel can be disabled to prevent any
2111 * interaction between the peripheral and the DMA controller.
2112 * 0b0..Disabled. Peripheral DMA requests are disabled.
2113 * 0b1..Enabled. Peripheral DMA requests are enabled.
2114 */
2115#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
2116#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
2117#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
2118/*! HWTRIGEN - Hardware Triggering Enable for this channel.
2119 * 0b0..Disabled. Hardware triggering is not used.
2120 * 0b1..Enabled. Use hardware triggering.
2121 */
2122#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
2123#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
2124#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
2125/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
2126 * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
2127 * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
2128 */
2129#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
2130#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
2131#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
2132/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
2133 * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
2134 * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
2135 * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
2136 * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
2137 * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
2138 * current BURSTPOWER length are completed.
2139 */
2140#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
2141#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
2142#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
2143/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
2144 * 0b0..Single transfer. Hardware trigger causes a single transfer.
2145 * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
2146 * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a
2147 * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
2148 * complete.
2149 */
2150#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
2151#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
2152#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
2153/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
2154 * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
2155 * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
2156 * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that
2157 * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:
2158 * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =
2159 * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The
2160 * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
2161 * multiple of the burst size.
2162 */
2163#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
2164#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
2165#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
2166/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
2167 * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this
2168 * could be used to read several sequential registers from a peripheral for each DMA burst,
2169 * reading the same registers again for each burst.
2170 * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
2171 * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
2172 */
2173#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
2174#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
2175#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
2176/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
2177 * 'wrapped', meaning that the destination address range for each burst will be the same. As an
2178 * example, this could be used to write several sequential registers to a peripheral for each DMA
2179 * burst, writing the same registers again for each burst.
2180 * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
2181 * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
2182 */
2183#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
2184#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
2185#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
2186/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority
2187 * levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
2188 */
2189#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
2190/*! @} */
2191
2192/* The count of DMA_CHANNEL_CFG */
2193#define DMA_CHANNEL_CFG_COUNT (30U)
2194
2195/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
2196/*! @{ */
2197#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
2198#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
2199/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the
2200 * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
2201 * 0b0..No effect. No effect on DMA operation.
2202 * 0b1..Valid pending.
2203 */
2204#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
2205#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
2206#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
2207/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is
2208 * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2209 * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
2210 * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
2211 */
2212#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
2213/*! @} */
2214
2215/* The count of DMA_CHANNEL_CTLSTAT */
2216#define DMA_CHANNEL_CTLSTAT_COUNT (30U)
2217
2218/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
2219/*! @{ */
2220#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
2221#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
2222/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor
2223 * is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
2224 * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
2225 * 0b1..Valid. The current channel descriptor is considered valid.
2226 */
2227#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
2228#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
2229#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
2230/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current
2231 * descriptor is exhausted. Reloading allows ping-pong and linked transfers.
2232 * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
2233 * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.
2234 */
2235#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
2236#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
2237#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
2238/*! SWTRIG - Software Trigger.
2239 * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by
2240 * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
2241 * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not
2242 * be used with level triggering when TRIGBURST = 0.
2243 */
2244#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
2245#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)
2246#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)
2247/*! CLRTRIG - Clear Trigger.
2248 * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
2249 * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted
2250 */
2251#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
2252#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)
2253#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)
2254/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between
2255 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
2256 * convention, interrupt A may be used when only one interrupt flag is needed.
2257 * 0b0..No effect.
2258 * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
2259 */
2260#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
2261#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)
2262#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)
2263/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between
2264 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
2265 * convention, interrupt A may be used when only one interrupt flag is needed.
2266 * 0b0..No effect.
2267 * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
2268 */
2269#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
2270#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)
2271#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)
2272/*! WIDTH - Transfer width used for this DMA channel.
2273 * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
2274 * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
2275 * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
2276 * 0b11..Reserved. Reserved setting, do not use.
2277 */
2278#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
2279#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)
2280#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)
2281/*! SRCINC - Determines whether the source address is incremented for each DMA transfer.
2282 * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
2283 * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is
2284 * the usual case when the source is memory.
2285 * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
2286 * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
2287 */
2288#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
2289#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)
2290#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)
2291/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer.
2292 * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when
2293 * the destination is a peripheral device.
2294 * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer.
2295 * This is the usual case when the destination is memory.
2296 * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
2297 * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
2298 */
2299#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
2300#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)
2301#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)
2302/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes
2303 * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller
2304 * uses this bit field during transfer to count down. Hence, it cannot be used by software to read
2305 * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1
2306 * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of
2307 * 1,024 transfers will be performed.
2308 */
2309#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
2310/*! @} */
2311
2312/* The count of DMA_CHANNEL_XFERCFG */
2313#define DMA_CHANNEL_XFERCFG_COUNT (30U)
2314
2315
2316/*!
2317 * @}
2318 */ /* end of group DMA_Register_Masks */
2319
2320
2321/* DMA - Peripheral instance base addresses */
2322/** Peripheral DMA0 base address */
2323#define DMA0_BASE (0x40082000u)
2324/** Peripheral DMA0 base pointer */
2325#define DMA0 ((DMA_Type *)DMA0_BASE)
2326/** Array initializer of DMA peripheral base addresses */
2327#define DMA_BASE_ADDRS { DMA0_BASE }
2328/** Array initializer of DMA peripheral base pointers */
2329#define DMA_BASE_PTRS { DMA0 }
2330/** Interrupt vectors for the DMA peripheral type */
2331#define DMA_IRQS { DMA0_IRQn }
2332
2333/*!
2334 * @}
2335 */ /* end of group DMA_Peripheral_Access_Layer */
2336
2337
2338/* ----------------------------------------------------------------------------
2339 -- DMIC Peripheral Access Layer
2340 ---------------------------------------------------------------------------- */
2341
2342/*!
2343 * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
2344 * @{
2345 */
2346
2347/** DMIC - Register Layout Typedef */
2348typedef struct {
2349 struct { /* offset: 0x0, array step: 0x100 */
2350 __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */
2351 __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */
2352 __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */
2353 __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */
2354 __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */
2355 uint8_t RESERVED_0[108];
2356 __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */
2357 __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */
2358 __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */
2359 __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */
2360 __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */
2361 uint8_t RESERVED_1[108];
2362 } CHANNEL[2];
2363 uint8_t RESERVED_0[3328];
2364 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */
2365 uint8_t RESERVED_1[8];
2366 __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */
2367 __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */
2368 uint8_t RESERVED_2[108];
2369 __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */
2370 __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */
2371 __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */
2372 __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */
2373 __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */
2374 __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */
2375 __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */
2376 uint8_t RESERVED_3[96];
2377 __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */
2378} DMIC_Type;
2379
2380/* ----------------------------------------------------------------------------
2381 -- DMIC Register Masks
2382 ---------------------------------------------------------------------------- */
2383
2384/*!
2385 * @addtogroup DMIC_Register_Masks DMIC Register Masks
2386 * @{
2387 */
2388
2389/*! @name CHANNEL_OSR - Oversample Rate register 0 */
2390/*! @{ */
2391#define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU)
2392#define DMIC_CHANNEL_OSR_OSR_SHIFT (0U)
2393/*! OSR - Selects the oversample rate for the related input channel.
2394 */
2395#define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
2396/*! @} */
2397
2398/* The count of DMIC_CHANNEL_OSR */
2399#define DMIC_CHANNEL_OSR_COUNT (2U)
2400
2401/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */
2402/*! @{ */
2403#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU)
2404#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U)
2405/*! PDMDIV - PDM clock divider value. 0 = divide by 1 1 = divide by 2 2 = divide by 3 3 = divide by
2406 * 4 4 = divide by 6 5 = divide by 8 6 = divide by 12 7 = divide by 16 8 = divide by 24 9 =
2407 * divide by 32 10 = divide by 48 11 = divide by 64 12 = divide by 96 13 = divide by 128 others =
2408 * reserved.
2409 */
2410#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
2411/*! @} */
2412
2413/* The count of DMIC_CHANNEL_DIVHFCLK */
2414#define DMIC_CHANNEL_DIVHFCLK_COUNT (2U)
2415
2416/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */
2417/*! @{ */
2418#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U)
2419#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U)
2420/*! COMP - Pre-emphasis filer coefficient for 2 FS mode. 0 = Compensation = 0 1 = Compensation = 16
2421 * 2 = Compensation = 15 3 = Compensation = 13
2422 */
2423#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
2424/*! @} */
2425
2426/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
2427#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U)
2428
2429/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */
2430/*! @{ */
2431#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U)
2432#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U)
2433/*! COMP - Pre-emphasis filer coefficient for 4 FS mode. 0 = Compensation = 0 1 = Compensation = 16
2434 * 2 = Compensation = 15 3 = Compensation = 13
2435 */
2436#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
2437/*! @} */
2438
2439/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
2440#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U)
2441
2442/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */
2443/*! @{ */
2444#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU)
2445#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U)
2446/*! GAIN - Gain control, as a positive or negative (two's complement) number of bits to shift.
2447 */
2448#define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
2449/*! @} */
2450
2451/* The count of DMIC_CHANNEL_GAINSHIFT */
2452#define DMIC_CHANNEL_GAINSHIFT_COUNT (2U)
2453
2454/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */
2455/*! @{ */
2456#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U)
2457#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U)
2458/*! ENABLE - FIFO enable.
2459 * 0b0..FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being
2460 * streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a
2461 * period when the data was not needed.
2462 * 0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
2463 */
2464#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
2465#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U)
2466#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U)
2467/*! RESETN - FIFO reset.
2468 * 0b0..Reset the FIFO.
2469 * 0b1..Normal operation
2470 */
2471#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
2472#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U)
2473#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U)
2474/*! INTEN - Interrupt enable.
2475 * 0b0..FIFO level interrupts are not enabled.
2476 * 0b1..FIFO level interrupts are enabled.
2477 */
2478#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
2479#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U)
2480#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U)
2481/*! DMAEN - DMA enable
2482 * 0b0..DMA requests are not enabled.
2483 * 0b1..DMA requests based on FIFO level are enabled.
2484 */
2485#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
2486#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U)
2487#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U)
2488/*! TRIGLVL - FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If
2489 * enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then
2490 * return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 =
2491 * trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has
2492 * received two entries. 15 = trigger when the FIFO has received 16 entries (has become full).
2493 */
2494#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
2495/*! @} */
2496
2497/* The count of DMIC_CHANNEL_FIFO_CTRL */
2498#define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U)
2499
2500/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */
2501/*! @{ */
2502#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U)
2503#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U)
2504/*! INT - Interrupt flag. Asserted when FIFO data reaches the level specified in the FIFOCTRL
2505 * register. Writing a one to this bit clears the flag. Remark: note that the bus clock to the DMIC
2506 * subsystem must be running in order for an interrupt to occur.
2507 */
2508#define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
2509#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U)
2510#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U)
2511/*! OVERRUN - Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one
2512 * to this bit clears the flag. This flag does not cause an interrupt.
2513 */
2514#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
2515#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U)
2516#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U)
2517/*! UNDERRUN - Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag.
2518 */
2519#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
2520/*! @} */
2521
2522/* The count of DMIC_CHANNEL_FIFO_STATUS */
2523#define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U)
2524
2525/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */
2526/*! @{ */
2527#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU)
2528#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U)
2529/*! DATA - Data from the top of the input filter FIFO.
2530 */
2531#define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
2532/*! @} */
2533
2534/* The count of DMIC_CHANNEL_FIFO_DATA */
2535#define DMIC_CHANNEL_FIFO_DATA_COUNT (2U)
2536
2537/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */
2538/*! @{ */
2539#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U)
2540#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U)
2541/*! PHY_FALL - Capture PDM_DATA
2542 * 0b0..Capture PDM_DATA on the rising edge of PDM_CLK.
2543 * 0b1..Capture PDM_DATA on the falling edge of PDM_CLK.
2544 */
2545#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
2546#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U)
2547#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U)
2548/*! PHY_HALF - Half rate sampling
2549 * 0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
2550 * 0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.
2551 */
2552#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
2553/*! @} */
2554
2555/* The count of DMIC_CHANNEL_PHY_CTRL */
2556#define DMIC_CHANNEL_PHY_CTRL_COUNT (2U)
2557
2558/*! @name CHANNEL_DC_CTRL - DC Control register 0 */
2559/*! @{ */
2560#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U)
2561#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U)
2562/*! DCPOLE - DC block filter
2563 * 0b00..Flat response, no filter.
2564 * 0b01..155 Hz.
2565 * 0b10..78 Hz.
2566 * 0b11..39 Hz
2567 */
2568#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
2569#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U)
2570#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U)
2571/*! DCGAIN - Fine gain adjustment in the form of a number of bits to downshift.
2572 */
2573#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
2574#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
2575#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
2576/*! SATURATEAT16BIT - Selects 16-bit saturation.
2577 * 0b0..Results roll over if out range and do not saturate.
2578 * 0b1..If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
2579 */
2580#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
2581/*! @} */
2582
2583/* The count of DMIC_CHANNEL_DC_CTRL */
2584#define DMIC_CHANNEL_DC_CTRL_COUNT (2U)
2585
2586/*! @name CHANEN - Channel Enable register */
2587/*! @{ */
2588#define DMIC_CHANEN_EN_CH0_MASK (0x1U)
2589#define DMIC_CHANEN_EN_CH0_SHIFT (0U)
2590/*! EN_CH0 - Enable channel 0. When 1, PDM channel 0 is enabled.
2591 */
2592#define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
2593#define DMIC_CHANEN_EN_CH1_MASK (0x2U)
2594#define DMIC_CHANEN_EN_CH1_SHIFT (1U)
2595/*! EN_CH1 - Enable channel 1. When 1, PDM channel 1 is enabled.
2596 */
2597#define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
2598/*! @} */
2599
2600/*! @name IOCFG - I/O Configuration register */
2601/*! @{ */
2602#define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U)
2603#define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U)
2604/*! CLK_BYPASS0 - Bypass CLK0. When 1, PDM_DATA1 becomes the clock for PDM channel 0. This provides
2605 * for the possibility of an external codec taking over the PDM bus.
2606 */
2607#define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)
2608#define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U)
2609#define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U)
2610/*! CLK_BYPASS1 - Bypass CLK1. When 1, PDM_DATA1 becomes the clock for PDM channel 1. This provides
2611 * for the possibility of an external codec taking over the PDM bus.
2612 */
2613#define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)
2614#define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U)
2615#define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U)
2616/*! STEREO_DATA0 - Stereo PDM select. When 1, PDM_DATA0 is routed to both PDM channels in a
2617 * configuration that supports a single stereo digital microphone.
2618 */
2619#define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)
2620/*! @} */
2621
2622/*! @name USE2FS - Use 2FS register */
2623/*! @{ */
2624#define DMIC_USE2FS_USE2FS_MASK (0x1U)
2625#define DMIC_USE2FS_USE2FS_SHIFT (0U)
2626/*! USE2FS - Use 2FS register
2627 * 0b0..Use 1FS output for PCM data.
2628 * 0b1..Use 2FS output for PCM data.
2629 */
2630#define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
2631/*! @} */
2632
2633/*! @name HWVADGAIN - HWVAD input gain register */
2634/*! @{ */
2635#define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU)
2636#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U)
2637/*! INPUTGAIN - Shift value for input bits 0x00 -10 bits 0x01 -8 bits 0x02 -6 bits 0x03 -4 bits 0x04
2638 * -2 bits 0x05 0 bits (default) 0x06 +2 bits 0x07 +4 bits 0x08 +6 bits 0x09 +8 bits 0x0A +10
2639 * bits 0x0B +12 bits 0x0C +14 bits 0x0D to 0x0F Reserved.
2640 */
2641#define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
2642/*! @} */
2643
2644/*! @name HWVADHPFS - HWVAD filter control register */
2645/*! @{ */
2646#define DMIC_HWVADHPFS_HPFS_MASK (0x3U)
2647#define DMIC_HWVADHPFS_HPFS_SHIFT (0U)
2648/*! HPFS - High pass filter
2649 * 0b00..First filter by-pass.
2650 * 0b01..High pass filter with -3dB cut-off at 1750Hz.
2651 * 0b10..High pass filter with -3dB cut-off at 215Hz.
2652 * 0b11..Reserved.
2653 */
2654#define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
2655/*! @} */
2656
2657/*! @name HWVADST10 - HWVAD control register */
2658/*! @{ */
2659#define DMIC_HWVADST10_ST10_MASK (0x1U)
2660#define DMIC_HWVADST10_ST10_SHIFT (0U)
2661/*! ST10 - Stage 0
2662 * 0b0..Normal operation, waiting for HWVAD trigger event (stage 0).
2663 * 0b1..Reset internal interrupt flag by writing a '1' pulse.
2664 */
2665#define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
2666/*! @} */
2667
2668/*! @name HWVADRSTT - HWVAD filter reset register */
2669/*! @{ */
2670#define DMIC_HWVADRSTT_RSTT_MASK (0x1U)
2671#define DMIC_HWVADRSTT_RSTT_SHIFT (0U)
2672/*! RSTT - Writing a 1 resets all filter values
2673 */
2674#define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)
2675/*! @} */
2676
2677/*! @name HWVADTHGN - HWVAD noise estimator gain register */
2678/*! @{ */
2679#define DMIC_HWVADTHGN_THGN_MASK (0xFU)
2680#define DMIC_HWVADTHGN_THGN_SHIFT (0U)
2681/*! THGN - Gain value for the noise estimator. Values 0 to 14. 0 corresponds to a gain of 1.
2682 */
2683#define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
2684/*! @} */
2685
2686/*! @name HWVADTHGS - HWVAD signal estimator gain register */
2687/*! @{ */
2688#define DMIC_HWVADTHGS_THGS_MASK (0xFU)
2689#define DMIC_HWVADTHGS_THGS_SHIFT (0U)
2690/*! THGS - Gain value for the signal estimator. Values 0 to 14. 0 corresponds to a gain of 1.
2691 */
2692#define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
2693/*! @} */
2694
2695/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */
2696/*! @{ */
2697#define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU)
2698#define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U)
2699/*! LOWZ - Noise envelope estimator value.
2700 */
2701#define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
2702/*! @} */
2703
2704/*! @name ID - Module Identification register */
2705/*! @{ */
2706#define DMIC_ID_ID_MASK (0xFFFFFFFFU)
2707#define DMIC_ID_ID_SHIFT (0U)
2708/*! ID - Indicates module ID and the number of channels in this DMIC interface.
2709 */
2710#define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)
2711/*! @} */
2712
2713
2714/*!
2715 * @}
2716 */ /* end of group DMIC_Register_Masks */
2717
2718
2719/* DMIC - Peripheral instance base addresses */
2720/** Peripheral DMIC0 base address */
2721#define DMIC0_BASE (0x40090000u)
2722/** Peripheral DMIC0 base pointer */
2723#define DMIC0 ((DMIC_Type *)DMIC0_BASE)
2724/** Array initializer of DMIC peripheral base addresses */
2725#define DMIC_BASE_ADDRS { DMIC0_BASE }
2726/** Array initializer of DMIC peripheral base pointers */
2727#define DMIC_BASE_PTRS { DMIC0 }
2728/** Interrupt vectors for the DMIC peripheral type */
2729#define DMIC_IRQS { DMIC0_IRQn }
2730#define DMIC_HWVAD_IRQS { HWVAD0_IRQn }
2731
2732/*!
2733 * @}
2734 */ /* end of group DMIC_Peripheral_Access_Layer */
2735
2736
2737/* ----------------------------------------------------------------------------
2738 -- EEPROM Peripheral Access Layer
2739 ---------------------------------------------------------------------------- */
2740
2741/*!
2742 * @addtogroup EEPROM_Peripheral_Access_Layer EEPROM Peripheral Access Layer
2743 * @{
2744 */
2745
2746/** EEPROM - Register Layout Typedef */
2747typedef struct {
2748 __IO uint32_t CMD; /**< EEPROM command register, offset: 0x0 */
2749 uint8_t RESERVED_0[4];
2750 __IO uint32_t RWSTATE; /**< EEPROM read wait state register, offset: 0x8 */
2751 __IO uint32_t AUTOPROG; /**< EEPROM auto programming register, offset: 0xC */
2752 __IO uint32_t WSTATE; /**< EEPROM wait state register, offset: 0x10 */
2753 __IO uint32_t CLKDIV; /**< EEPROM clock divider register, offset: 0x14 */
2754 __IO uint32_t PWRDWN; /**< EEPROM power-down register, offset: 0x18 */
2755 uint8_t RESERVED_1[4028];
2756 __O uint32_t INTENCLR; /**< EEPROM interrupt enable clear, offset: 0xFD8 */
2757 __O uint32_t INTENSET; /**< EEPROM interrupt enable set, offset: 0xFDC */
2758 __I uint32_t INTSTAT; /**< EEPROM interrupt status, offset: 0xFE0 */
2759 __I uint32_t INTEN; /**< EEPROM interrupt enable, offset: 0xFE4 */
2760 __O uint32_t INTSTATCLR; /**< EEPROM interrupt status clear, offset: 0xFE8 */
2761 __O uint32_t INTSTATSET; /**< EEPROM interrupt status set, offset: 0xFEC */
2762} EEPROM_Type;
2763
2764/* ----------------------------------------------------------------------------
2765 -- EEPROM Register Masks
2766 ---------------------------------------------------------------------------- */
2767
2768/*!
2769 * @addtogroup EEPROM_Register_Masks EEPROM Register Masks
2770 * @{
2771 */
2772
2773/*! @name CMD - EEPROM command register */
2774/*! @{ */
2775#define EEPROM_CMD_CMD_MASK (0x7U)
2776#define EEPROM_CMD_CMD_SHIFT (0U)
2777/*! CMD - Command.
2778 */
2779#define EEPROM_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_CMD_CMD_SHIFT)) & EEPROM_CMD_CMD_MASK)
2780/*! @} */
2781
2782/*! @name RWSTATE - EEPROM read wait state register */
2783/*! @{ */
2784#define EEPROM_RWSTATE_RPHASE2_MASK (0xFFU)
2785#define EEPROM_RWSTATE_RPHASE2_SHIFT (0U)
2786/*! RPHASE2 - Wait states 2 (minus 1 encoded).
2787 */
2788#define EEPROM_RWSTATE_RPHASE2(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE2_SHIFT)) & EEPROM_RWSTATE_RPHASE2_MASK)
2789#define EEPROM_RWSTATE_RPHASE1_MASK (0xFF00U)
2790#define EEPROM_RWSTATE_RPHASE1_SHIFT (8U)
2791/*! RPHASE1 - Wait states 1 (minus 1 encoded).
2792 */
2793#define EEPROM_RWSTATE_RPHASE1(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE1_SHIFT)) & EEPROM_RWSTATE_RPHASE1_MASK)
2794/*! @} */
2795
2796/*! @name AUTOPROG - EEPROM auto programming register */
2797/*! @{ */
2798#define EEPROM_AUTOPROG_AUTOPROG_MASK (0x3U)
2799#define EEPROM_AUTOPROG_AUTOPROG_SHIFT (0U)
2800/*! AUTOPROG - Auto programming mode: 00 = auto programming off 01 = erase/program cycle is
2801 * triggered after 1 word is written 10 = erase/program cycle is triggered after a write to AHB address
2802 * ending with .
2803 */
2804#define EEPROM_AUTOPROG_AUTOPROG(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_AUTOPROG_AUTOPROG_SHIFT)) & EEPROM_AUTOPROG_AUTOPROG_MASK)
2805/*! @} */
2806
2807/*! @name WSTATE - EEPROM wait state register */
2808/*! @{ */
2809#define EEPROM_WSTATE_PHASE3_MASK (0xFFU)
2810#define EEPROM_WSTATE_PHASE3_SHIFT (0U)
2811/*! PHASE3 - Wait states for phase 3 (minus 1 encoded).
2812 */
2813#define EEPROM_WSTATE_PHASE3(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE3_SHIFT)) & EEPROM_WSTATE_PHASE3_MASK)
2814#define EEPROM_WSTATE_PHASE2_MASK (0xFF00U)
2815#define EEPROM_WSTATE_PHASE2_SHIFT (8U)
2816/*! PHASE2 - Wait states for phase 2 (minus 1 encoded).
2817 */
2818#define EEPROM_WSTATE_PHASE2(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE2_SHIFT)) & EEPROM_WSTATE_PHASE2_MASK)
2819#define EEPROM_WSTATE_PHASE1_MASK (0xFF0000U)
2820#define EEPROM_WSTATE_PHASE1_SHIFT (16U)
2821/*! PHASE1 - Wait states for phase 1 (minus 1 encoded).
2822 */
2823#define EEPROM_WSTATE_PHASE1(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE1_SHIFT)) & EEPROM_WSTATE_PHASE1_MASK)
2824#define EEPROM_WSTATE_LCK_PARWEP_MASK (0x80000000U)
2825#define EEPROM_WSTATE_LCK_PARWEP_SHIFT (31U)
2826/*! LCK_PARWEP - Lock timing parameters for write, erase and program operation 0 = WSTATE and CLKDIV
2827 * registers have R/W access 1 = WSTATE and CLKDIV registers have R only access.
2828 */
2829#define EEPROM_WSTATE_LCK_PARWEP(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_LCK_PARWEP_SHIFT)) & EEPROM_WSTATE_LCK_PARWEP_MASK)
2830/*! @} */
2831
2832/*! @name CLKDIV - EEPROM clock divider register */
2833/*! @{ */
2834#define EEPROM_CLKDIV_CLKDIV_MASK (0xFFFFU)
2835#define EEPROM_CLKDIV_CLKDIV_SHIFT (0U)
2836/*! CLKDIV - Division factor (minus 1 encoded).
2837 */
2838#define EEPROM_CLKDIV_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_CLKDIV_CLKDIV_SHIFT)) & EEPROM_CLKDIV_CLKDIV_MASK)
2839/*! @} */
2840
2841/*! @name PWRDWN - EEPROM power-down register */
2842/*! @{ */
2843#define EEPROM_PWRDWN_PWRDWN_MASK (0x1U)
2844#define EEPROM_PWRDWN_PWRDWN_SHIFT (0U)
2845/*! PWRDWN - Power down mode bit.
2846 */
2847#define EEPROM_PWRDWN_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_PWRDWN_PWRDWN_SHIFT)) & EEPROM_PWRDWN_PWRDWN_MASK)
2848/*! @} */
2849
2850/*! @name INTENCLR - EEPROM interrupt enable clear */
2851/*! @{ */
2852#define EEPROM_INTENCLR_PROG_CLR_EN_MASK (0x4U)
2853#define EEPROM_INTENCLR_PROG_CLR_EN_SHIFT (2U)
2854/*! PROG_CLR_EN - Clear program operation finished interrupt enable bit for EEPROM.
2855 */
2856#define EEPROM_INTENCLR_PROG_CLR_EN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENCLR_PROG_CLR_EN_SHIFT)) & EEPROM_INTENCLR_PROG_CLR_EN_MASK)
2857/*! @} */
2858
2859/*! @name INTENSET - EEPROM interrupt enable set */
2860/*! @{ */
2861#define EEPROM_INTENSET_PROG_SET_EN_MASK (0x4U)
2862#define EEPROM_INTENSET_PROG_SET_EN_SHIFT (2U)
2863/*! PROG_SET_EN - Set program operation finished interrupt enable bit for EEPROM device 1.
2864 */
2865#define EEPROM_INTENSET_PROG_SET_EN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENSET_PROG_SET_EN_SHIFT)) & EEPROM_INTENSET_PROG_SET_EN_MASK)
2866/*! @} */
2867
2868/*! @name INTSTAT - EEPROM interrupt status */
2869/*! @{ */
2870#define EEPROM_INTSTAT_END_OF_PROG_MASK (0x4U)
2871#define EEPROM_INTSTAT_END_OF_PROG_SHIFT (2U)
2872/*! END_OF_PROG - EEPROM program operation finished interrupt status bit.
2873 */
2874#define EEPROM_INTSTAT_END_OF_PROG(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTAT_END_OF_PROG_SHIFT)) & EEPROM_INTSTAT_END_OF_PROG_MASK)
2875/*! @} */
2876
2877/*! @name INTEN - EEPROM interrupt enable */
2878/*! @{ */
2879#define EEPROM_INTEN_EE_PROG_DONE_MASK (0x4U)
2880#define EEPROM_INTEN_EE_PROG_DONE_SHIFT (2U)
2881/*! EE_PROG_DONE - EEPROM program operation finished interrupt enable bit.
2882 */
2883#define EEPROM_INTEN_EE_PROG_DONE(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTEN_EE_PROG_DONE_SHIFT)) & EEPROM_INTEN_EE_PROG_DONE_MASK)
2884/*! @} */
2885
2886/*! @name INTSTATCLR - EEPROM interrupt status clear */
2887/*! @{ */
2888#define EEPROM_INTSTATCLR_PROG_CLR_ST_MASK (0x4U)
2889#define EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT (2U)
2890/*! PROG_CLR_ST - Clear program operation finished interrupt status bit for EEPROM device.
2891 */
2892#define EEPROM_INTSTATCLR_PROG_CLR_ST(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT)) & EEPROM_INTSTATCLR_PROG_CLR_ST_MASK)
2893/*! @} */
2894
2895/*! @name INTSTATSET - EEPROM interrupt status set */
2896/*! @{ */
2897#define EEPROM_INTSTATSET_PROG_SET_ST_MASK (0x4U)
2898#define EEPROM_INTSTATSET_PROG_SET_ST_SHIFT (2U)
2899/*! PROG_SET_ST - Set program operation finished interrupt status bit for EEPROM device.
2900 */
2901#define EEPROM_INTSTATSET_PROG_SET_ST(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATSET_PROG_SET_ST_SHIFT)) & EEPROM_INTSTATSET_PROG_SET_ST_MASK)
2902/*! @} */
2903
2904
2905/*!
2906 * @}
2907 */ /* end of group EEPROM_Register_Masks */
2908
2909
2910/* EEPROM - Peripheral instance base addresses */
2911/** Peripheral EEPROM base address */
2912#define EEPROM_BASE (0x40014000u)
2913/** Peripheral EEPROM base pointer */
2914#define EEPROM ((EEPROM_Type *)EEPROM_BASE)
2915/** Array initializer of EEPROM peripheral base addresses */
2916#define EEPROM_BASE_ADDRS { EEPROM_BASE }
2917/** Array initializer of EEPROM peripheral base pointers */
2918#define EEPROM_BASE_PTRS { EEPROM }
2919/** Interrupt vectors for the EEPROM peripheral type */
2920#define EEPROM_IRQS { EEPROM_IRQn }
2921
2922/*!
2923 * @}
2924 */ /* end of group EEPROM_Peripheral_Access_Layer */
2925
2926
2927/* ----------------------------------------------------------------------------
2928 -- EMC Peripheral Access Layer
2929 ---------------------------------------------------------------------------- */
2930
2931/*!
2932 * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer
2933 * @{
2934 */
2935
2936/** EMC - Register Layout Typedef */
2937typedef struct {
2938 __IO uint32_t CONTROL; /**< Controls operation of the memory controller, offset: 0x0 */
2939 __I uint32_t STATUS; /**< Provides EMC status information, offset: 0x4 */
2940 __IO uint32_t CONFIG; /**< Configures operation of the memory controller, offset: 0x8 */
2941 uint8_t RESERVED_0[20];
2942 __IO uint32_t DYNAMICCONTROL; /**< Controls dynamic memory operation, offset: 0x20 */
2943 __IO uint32_t DYNAMICREFRESH; /**< Configures dynamic memory refresh, offset: 0x24 */
2944 __IO uint32_t DYNAMICREADCONFIG; /**< Configures dynamic memory read strategy, offset: 0x28 */
2945 uint8_t RESERVED_1[4];
2946 __IO uint32_t DYNAMICRP; /**< Precharge command period, offset: 0x30 */
2947 __IO uint32_t DYNAMICRAS; /**< Active to precharge command period, offset: 0x34 */
2948 __IO uint32_t DYNAMICSREX; /**< Self-refresh exit time, offset: 0x38 */
2949 __IO uint32_t DYNAMICAPR; /**< Last-data-out to active command time, offset: 0x3C */
2950 __IO uint32_t DYNAMICDAL; /**< Data-in to active command time, offset: 0x40 */
2951 __IO uint32_t DYNAMICWR; /**< Write recovery time, offset: 0x44 */
2952 __IO uint32_t DYNAMICRC; /**< Selects the active to active command period, offset: 0x48 */
2953 __IO uint32_t DYNAMICRFC; /**< Selects the auto-refresh period, offset: 0x4C */
2954 __IO uint32_t DYNAMICXSR; /**< Time for exit self-refresh to active command, offset: 0x50 */
2955 __IO uint32_t DYNAMICRRD; /**< Latency for active bank A to active bank B, offset: 0x54 */
2956 __IO uint32_t DYNAMICMRD; /**< Time for load mode register to active command, offset: 0x58 */
2957 uint8_t RESERVED_2[36];
2958 __IO uint32_t STATICEXTENDEDWAIT; /**< Time for long static memory read and write transfers, offset: 0x80 */
2959 uint8_t RESERVED_3[124];
2960 struct { /* offset: 0x100, array step: 0x20 */
2961 __IO uint32_t DYNAMICCONFIG; /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */
2962 __IO uint32_t DYNAMICRASCAS; /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */
2963 uint8_t RESERVED_0[24];
2964 } DYNAMIC[4];
2965 uint8_t RESERVED_4[128];
2966 struct { /* offset: 0x200, array step: 0x20 */
2967 __IO uint32_t STATICCONFIG; /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */
2968 __IO uint32_t STATICWAITWEN; /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */
2969 __IO uint32_t STATICWAITOEN; /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */
2970 __IO uint32_t STATICWAITRD; /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */
2971 __IO uint32_t STATICWAITPAGE; /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */
2972 __IO uint32_t STATICWAITWR; /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */
2973 __IO uint32_t STATICWAITTURN; /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */
2974 uint8_t RESERVED_0[4];
2975 } STATIC[4];
2976} EMC_Type;
2977
2978/* ----------------------------------------------------------------------------
2979 -- EMC Register Masks
2980 ---------------------------------------------------------------------------- */
2981
2982/*!
2983 * @addtogroup EMC_Register_Masks EMC Register Masks
2984 * @{
2985 */
2986
2987/*! @name CONTROL - Controls operation of the memory controller */
2988/*! @{ */
2989#define EMC_CONTROL_E_MASK (0x1U)
2990#define EMC_CONTROL_E_SHIFT (0U)
2991/*! E - EMC Enable.
2992 */
2993#define EMC_CONTROL_E(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK)
2994#define EMC_CONTROL_M_MASK (0x2U)
2995#define EMC_CONTROL_M_SHIFT (1U)
2996/*! M - Address mirror.
2997 */
2998#define EMC_CONTROL_M(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK)
2999#define EMC_CONTROL_L_MASK (0x4U)
3000#define EMC_CONTROL_L_SHIFT (2U)
3001/*! L - Low-power mode.
3002 */
3003#define EMC_CONTROL_L(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK)
3004/*! @} */
3005
3006/*! @name STATUS - Provides EMC status information */
3007/*! @{ */
3008#define EMC_STATUS_B_MASK (0x1U)
3009#define EMC_STATUS_B_SHIFT (0U)
3010/*! B - Busy.
3011 */
3012#define EMC_STATUS_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK)
3013#define EMC_STATUS_S_MASK (0x2U)
3014#define EMC_STATUS_S_SHIFT (1U)
3015/*! S - Write buffer status.
3016 */
3017#define EMC_STATUS_S(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK)
3018#define EMC_STATUS_SA_MASK (0x4U)
3019#define EMC_STATUS_SA_SHIFT (2U)
3020/*! SA - Self-refresh acknowledge.
3021 */
3022#define EMC_STATUS_SA(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK)
3023/*! @} */
3024
3025/*! @name CONFIG - Configures operation of the memory controller */
3026/*! @{ */
3027#define EMC_CONFIG_EM_MASK (0x1U)
3028#define EMC_CONFIG_EM_SHIFT (0U)
3029/*! EM - Endian mode.
3030 */
3031#define EMC_CONFIG_EM(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK)
3032#define EMC_CONFIG_CLKR_MASK (0x100U)
3033#define EMC_CONFIG_CLKR_SHIFT (8U)
3034/*! CLKR - This bit must contain 0 for proper operation of the EMC.
3035 */
3036#define EMC_CONFIG_CLKR(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK)
3037/*! @} */
3038
3039/*! @name DYNAMICCONTROL - Controls dynamic memory operation */
3040/*! @{ */
3041#define EMC_DYNAMICCONTROL_CE_MASK (0x1U)
3042#define EMC_DYNAMICCONTROL_CE_SHIFT (0U)
3043/*! CE - Dynamic memory clock enable.
3044 */
3045#define EMC_DYNAMICCONTROL_CE(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK)
3046#define EMC_DYNAMICCONTROL_CS_MASK (0x2U)
3047#define EMC_DYNAMICCONTROL_CS_SHIFT (1U)
3048/*! CS - Dynamic memory clock control.
3049 */
3050#define EMC_DYNAMICCONTROL_CS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK)
3051#define EMC_DYNAMICCONTROL_SR_MASK (0x4U)
3052#define EMC_DYNAMICCONTROL_SR_SHIFT (2U)
3053/*! SR - Self-refresh request, EMCSREFREQ.
3054 */
3055#define EMC_DYNAMICCONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK)
3056#define EMC_DYNAMICCONTROL_MMC_MASK (0x20U)
3057#define EMC_DYNAMICCONTROL_MMC_SHIFT (5U)
3058/*! MMC - Memory clock control.
3059 */
3060#define EMC_DYNAMICCONTROL_MMC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK)
3061#define EMC_DYNAMICCONTROL_I_MASK (0x180U)
3062#define EMC_DYNAMICCONTROL_I_SHIFT (7U)
3063/*! I - SDRAM initialization.
3064 */
3065#define EMC_DYNAMICCONTROL_I(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK)
3066/*! @} */
3067
3068/*! @name DYNAMICREFRESH - Configures dynamic memory refresh */
3069/*! @{ */
3070#define EMC_DYNAMICREFRESH_REFRESH_MASK (0x7FFU)
3071#define EMC_DYNAMICREFRESH_REFRESH_SHIFT (0U)
3072/*! REFRESH - Refresh timer.
3073 */
3074#define EMC_DYNAMICREFRESH_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK)
3075/*! @} */
3076
3077/*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */
3078/*! @{ */
3079#define EMC_DYNAMICREADCONFIG_RD_MASK (0x3U)
3080#define EMC_DYNAMICREADCONFIG_RD_SHIFT (0U)
3081/*! RD - Read data strategy.
3082 */
3083#define EMC_DYNAMICREADCONFIG_RD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK)
3084/*! @} */
3085
3086/*! @name DYNAMICRP - Precharge command period */
3087/*! @{ */
3088#define EMC_DYNAMICRP_TRP_MASK (0xFU)
3089#define EMC_DYNAMICRP_TRP_SHIFT (0U)
3090/*! TRP - Precharge command period.
3091 */
3092#define EMC_DYNAMICRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK)
3093/*! @} */
3094
3095/*! @name DYNAMICRAS - Active to precharge command period */
3096/*! @{ */
3097#define EMC_DYNAMICRAS_TRAS_MASK (0xFU)
3098#define EMC_DYNAMICRAS_TRAS_SHIFT (0U)
3099/*! TRAS - Active to precharge command period.
3100 */
3101#define EMC_DYNAMICRAS_TRAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK)
3102/*! @} */
3103
3104/*! @name DYNAMICSREX - Self-refresh exit time */
3105/*! @{ */
3106#define EMC_DYNAMICSREX_TSREX_MASK (0xFU)
3107#define EMC_DYNAMICSREX_TSREX_SHIFT (0U)
3108/*! TSREX - Self-refresh exit time.
3109 */
3110#define EMC_DYNAMICSREX_TSREX(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK)
3111/*! @} */
3112
3113/*! @name DYNAMICAPR - Last-data-out to active command time */
3114/*! @{ */
3115#define EMC_DYNAMICAPR_TAPR_MASK (0xFU)
3116#define EMC_DYNAMICAPR_TAPR_SHIFT (0U)
3117/*! TAPR - Last-data-out to active command time.
3118 */
3119#define EMC_DYNAMICAPR_TAPR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK)
3120/*! @} */
3121
3122/*! @name DYNAMICDAL - Data-in to active command time */
3123/*! @{ */
3124#define EMC_DYNAMICDAL_TDAL_MASK (0xFU)
3125#define EMC_DYNAMICDAL_TDAL_SHIFT (0U)
3126/*! TDAL - Data-in to active command.
3127 */
3128#define EMC_DYNAMICDAL_TDAL(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK)
3129/*! @} */
3130
3131/*! @name DYNAMICWR - Write recovery time */
3132/*! @{ */
3133#define EMC_DYNAMICWR_TWR_MASK (0xFU)
3134#define EMC_DYNAMICWR_TWR_SHIFT (0U)
3135/*! TWR - Write recovery time.
3136 */
3137#define EMC_DYNAMICWR_TWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK)
3138/*! @} */
3139
3140/*! @name DYNAMICRC - Selects the active to active command period */
3141/*! @{ */
3142#define EMC_DYNAMICRC_TRC_MASK (0x1FU)
3143#define EMC_DYNAMICRC_TRC_SHIFT (0U)
3144/*! TRC - Active to active command period.
3145 */
3146#define EMC_DYNAMICRC_TRC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK)
3147/*! @} */
3148
3149/*! @name DYNAMICRFC - Selects the auto-refresh period */
3150/*! @{ */
3151#define EMC_DYNAMICRFC_TRFC_MASK (0x1FU)
3152#define EMC_DYNAMICRFC_TRFC_SHIFT (0U)
3153/*! TRFC - Auto-refresh period and auto-refresh to active command period.
3154 */
3155#define EMC_DYNAMICRFC_TRFC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK)
3156/*! @} */
3157
3158/*! @name DYNAMICXSR - Time for exit self-refresh to active command */
3159/*! @{ */
3160#define EMC_DYNAMICXSR_TXSR_MASK (0x1FU)
3161#define EMC_DYNAMICXSR_TXSR_SHIFT (0U)
3162/*! TXSR - Exit self-refresh to active command time.
3163 */
3164#define EMC_DYNAMICXSR_TXSR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK)
3165/*! @} */
3166
3167/*! @name DYNAMICRRD - Latency for active bank A to active bank B */
3168/*! @{ */
3169#define EMC_DYNAMICRRD_TRRD_MASK (0xFU)
3170#define EMC_DYNAMICRRD_TRRD_SHIFT (0U)
3171/*! TRRD - Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles.
3172 */
3173#define EMC_DYNAMICRRD_TRRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK)
3174/*! @} */
3175
3176/*! @name DYNAMICMRD - Time for load mode register to active command */
3177/*! @{ */
3178#define EMC_DYNAMICMRD_TMRD_MASK (0xFU)
3179#define EMC_DYNAMICMRD_TMRD_SHIFT (0U)
3180/*! TMRD - Load mode register to active command time.
3181 */
3182#define EMC_DYNAMICMRD_TMRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK)
3183/*! @} */
3184
3185/*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */
3186/*! @{ */
3187#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU)
3188#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U)
3189/*! EXTENDEDWAIT - Extended wait time out.
3190 */
3191#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK)
3192/*! @} */
3193
3194/*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */
3195/*! @{ */
3196#define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK (0x18U)
3197#define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT (3U)
3198/*! MD - Memory device.
3199 */
3200#define EMC_DYNAMIC_DYNAMICCONFIG_MD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK)
3201#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK (0x1F80U)
3202#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT (7U)
3203/*! AM0 - See Table 933.
3204 */
3205#define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK)
3206#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK (0x4000U)
3207#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT (14U)
3208/*! AM1 - See Table 933.
3209 */
3210#define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
3211#define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK (0x80000U)
3212#define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT (19U)
3213/*! B - Buffer enable.
3214 */
3215#define EMC_DYNAMIC_DYNAMICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK)
3216#define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK (0x100000U)
3217#define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT (20U)
3218/*! P - Write protect.
3219 */
3220#define EMC_DYNAMIC_DYNAMICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK)
3221/*! @} */
3222
3223/* The count of EMC_DYNAMIC_DYNAMICCONFIG */
3224#define EMC_DYNAMIC_DYNAMICCONFIG_COUNT (4U)
3225
3226/*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */
3227/*! @{ */
3228#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK (0x3U)
3229#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT (0U)
3230/*! RAS - RAS latency (active to read/write delay).
3231 */
3232#define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK)
3233#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK (0x300U)
3234#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT (8U)
3235/*! CAS - CAS latency.
3236 */
3237#define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK)
3238/*! @} */
3239
3240/* The count of EMC_DYNAMIC_DYNAMICRASCAS */
3241#define EMC_DYNAMIC_DYNAMICRASCAS_COUNT (4U)
3242
3243/*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */
3244/*! @{ */
3245#define EMC_STATIC_STATICCONFIG_MW_MASK (0x3U)
3246#define EMC_STATIC_STATICCONFIG_MW_SHIFT (0U)
3247/*! MW - Memory width.
3248 */
3249#define EMC_STATIC_STATICCONFIG_MW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK)
3250#define EMC_STATIC_STATICCONFIG_PM_MASK (0x8U)
3251#define EMC_STATIC_STATICCONFIG_PM_SHIFT (3U)
3252/*! PM - Page mode.
3253 */
3254#define EMC_STATIC_STATICCONFIG_PM(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK)
3255#define EMC_STATIC_STATICCONFIG_PC_MASK (0x40U)
3256#define EMC_STATIC_STATICCONFIG_PC_SHIFT (6U)
3257/*! PC - Chip select polarity.
3258 */
3259#define EMC_STATIC_STATICCONFIG_PC(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK)
3260#define EMC_STATIC_STATICCONFIG_PB_MASK (0x80U)
3261#define EMC_STATIC_STATICCONFIG_PB_SHIFT (7U)
3262/*! PB - Byte lane state.
3263 */
3264#define EMC_STATIC_STATICCONFIG_PB(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK)
3265#define EMC_STATIC_STATICCONFIG_EW_MASK (0x100U)
3266#define EMC_STATIC_STATICCONFIG_EW_SHIFT (8U)
3267/*! EW - Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write
3268 * transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.
3269 */
3270#define EMC_STATIC_STATICCONFIG_EW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK)
3271#define EMC_STATIC_STATICCONFIG_B_MASK (0x80000U)
3272#define EMC_STATIC_STATICCONFIG_B_SHIFT (19U)
3273/*! B - Buffer enable [2].
3274 */
3275#define EMC_STATIC_STATICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK)
3276#define EMC_STATIC_STATICCONFIG_P_MASK (0x100000U)
3277#define EMC_STATIC_STATICCONFIG_P_SHIFT (20U)
3278/*! P - Write protect.
3279 */
3280#define EMC_STATIC_STATICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK)
3281/*! @} */
3282
3283/* The count of EMC_STATIC_STATICCONFIG */
3284#define EMC_STATIC_STATICCONFIG_COUNT (4U)
3285
3286/*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */
3287/*! @{ */
3288#define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK (0xFU)
3289#define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT (0U)
3290/*! WAITWEN - Wait write enable.
3291 */
3292#define EMC_STATIC_STATICWAITWEN_WAITWEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK)
3293/*! @} */
3294
3295/* The count of EMC_STATIC_STATICWAITWEN */
3296#define EMC_STATIC_STATICWAITWEN_COUNT (4U)
3297
3298/*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */
3299/*! @{ */
3300#define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK (0xFU)
3301#define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT (0U)
3302/*! WAITOEN - Wait output enable.
3303 */
3304#define EMC_STATIC_STATICWAITOEN_WAITOEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK)
3305/*! @} */
3306
3307/* The count of EMC_STATIC_STATICWAITOEN */
3308#define EMC_STATIC_STATICWAITOEN_COUNT (4U)
3309
3310/*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */
3311/*! @{ */
3312#define EMC_STATIC_STATICWAITRD_WAITRD_MASK (0x1FU)
3313#define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT (0U)
3314/*! WAITRD - .
3315 */
3316#define EMC_STATIC_STATICWAITRD_WAITRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK)
3317/*! @} */
3318
3319/* The count of EMC_STATIC_STATICWAITRD */
3320#define EMC_STATIC_STATICWAITRD_COUNT (4U)
3321
3322/*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */
3323/*! @{ */
3324#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK (0x1FU)
3325#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U)
3326/*! WAITPAGE - Asynchronous page mode read after the first read wait states.
3327 */
3328#define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK)
3329/*! @} */
3330
3331/* The count of EMC_STATIC_STATICWAITPAGE */
3332#define EMC_STATIC_STATICWAITPAGE_COUNT (4U)
3333
3334/*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */
3335/*! @{ */
3336#define EMC_STATIC_STATICWAITWR_WAITWR_MASK (0x1FU)
3337#define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT (0U)
3338/*! WAITWR - Write wait states.
3339 */
3340#define EMC_STATIC_STATICWAITWR_WAITWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK)
3341/*! @} */
3342
3343/* The count of EMC_STATIC_STATICWAITWR */
3344#define EMC_STATIC_STATICWAITWR_COUNT (4U)
3345
3346/*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */
3347/*! @{ */
3348#define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK (0xFU)
3349#define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U)
3350/*! WAITTURN - Bus turn-around cycles.
3351 */
3352#define EMC_STATIC_STATICWAITTURN_WAITTURN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK)
3353/*! @} */
3354
3355/* The count of EMC_STATIC_STATICWAITTURN */
3356#define EMC_STATIC_STATICWAITTURN_COUNT (4U)
3357
3358
3359/*!
3360 * @}
3361 */ /* end of group EMC_Register_Masks */
3362
3363
3364/* EMC - Peripheral instance base addresses */
3365/** Peripheral EMC base address */
3366#define EMC_BASE (0x40081000u)
3367/** Peripheral EMC base pointer */
3368#define EMC ((EMC_Type *)EMC_BASE)
3369/** Array initializer of EMC peripheral base addresses */
3370#define EMC_BASE_ADDRS { EMC_BASE }
3371/** Array initializer of EMC peripheral base pointers */
3372#define EMC_BASE_PTRS { EMC }
3373
3374/*!
3375 * @}
3376 */ /* end of group EMC_Peripheral_Access_Layer */
3377
3378
3379/* ----------------------------------------------------------------------------
3380 -- FLEXCOMM Peripheral Access Layer
3381 ---------------------------------------------------------------------------- */
3382
3383/*!
3384 * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
3385 * @{
3386 */
3387
3388/** FLEXCOMM - Register Layout Typedef */
3389typedef struct {
3390 uint8_t RESERVED_0[4088];
3391 __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
3392 __IO uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */
3393} FLEXCOMM_Type;
3394
3395/* ----------------------------------------------------------------------------
3396 -- FLEXCOMM Register Masks
3397 ---------------------------------------------------------------------------- */
3398
3399/*!
3400 * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
3401 * @{
3402 */
3403
3404/*! @name PSELID - Peripheral Select and Flexcomm ID register. */
3405/*! @{ */
3406#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U)
3407#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U)
3408/*! PERSEL - Peripheral Select. This field is writable by software.
3409 * 0b000..No peripheral selected.
3410 * 0b001..USART function selected.
3411 * 0b010..SPI function selected.
3412 * 0b011..I2C function selected.
3413 * 0b100..I2S transmit function selected.
3414 * 0b101..I2S receive function selected.
3415 * 0b110..Reserved
3416 * 0b111..Reserved
3417 */