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1/*
2** ###################################################################
3** Processors: LPC54607J256BD208
4** LPC54607J256ET180
5** LPC54607J512ET180
6**
7** Compilers: GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9** Keil ARM C/C++ Compiler
10** MCUXpresso Compiler
11**
12** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017
13** Version: rev. 1.2, 2017-06-08
14** Build: b201015
15**
16** Abstract:
17** Provides a system configuration function and a global variable that
18** contains the system frequency. It configures the device and initializes
19** the oscillator (PLL) that is part of the microcontroller device.
20**
21** Copyright 2016 Freescale Semiconductor, Inc.
22** Copyright 2016-2020 NXP
23** All rights reserved.
24**
25** SPDX-License-Identifier: BSD-3-Clause
26**
27** http: www.nxp.com
28** mail: [email protected]
29**
30** Revisions:
31** - rev. 1.0 (2016-08-12)
32** Initial version.
33** - rev. 1.1 (2016-11-25)
34** Update CANFD and Classic CAN register.
35** Add MAC TIMERSTAMP registers.
36** - rev. 1.2 (2017-06-08)
37** Remove RTC_CTRL_RTC_OSC_BYPASS.
38** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
39** Remove RESET and HALT from SYSCON_AHBCLKDIV.
40**
41** ###################################################################
42*/
43
44/*!
45 * @file LPC54607
46 * @version 1.2
47 * @date 2017-06-08
48 * @brief Device specific configuration file for LPC54607 (implementation file)
49 *
50 * Provides a system configuration function and a global variable that contains
51 * the system frequency. It configures the device and initializes the oscillator
52 * (PLL) that is part of the microcontroller device.
53 */
54
55#include <stdint.h>
56#include "fsl_device_registers.h"
57
58#define NVALMAX (0x100)
59#define PVALMAX (0x20U)
60#define MVALMAX (0x8000U)
61#define PLL_MDEC_VAL_P (0U) /* MDEC is in bits 16:0 */
62#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
63#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */
64#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
65#define PLL_PDEC_VAL_P (0U) /* PDEC is in bits 6:0 */
66#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
67
68static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
69 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
70/* Get WATCH DOG Clk */
71static uint32_t getWdtOscFreq(void)
72{
73 uint8_t freq_sel, div_sel;
74 if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) == SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
75 {
76 return 0U;
77 }
78 else
79 {
80 div_sel = (uint8_t)((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1UL) << 1UL;
81 freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
82 return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
83 }
84}
85/* Find decoded N value for raw NDEC value */
86static uint32_t pllDecodeN(uint32_t NDEC)
87{
88 uint32_t n, x, i;
89
90 /* Find NDec */
91 switch (NDEC)
92 {
93 case 0x3FFU:
94 n = 0UL;
95 break;
96 case 0x302U:
97 n = 1UL;
98 break;
99 case 0x202U:
100 n = 2UL;
101 break;
102 default:
103 x = 0x080UL;
104 n = 0xFFFFFFFFUL;
105 for (i = NVALMAX; i >= 3UL; i--)
106 {
107 x = (((x ^ (x >> 2UL) ^ (x >> 3UL) ^ (x >> 4UL)) & 1UL) << 7UL) | ((x >> 1UL) & 0x7FUL);
108 if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
109 {
110 /* Decoded value of NDEC */
111 n = i;
112 }
113 if (n != 0xFFFFFFFFUL)
114 {
115 break;
116 }
117 }
118 break;
119 }
120 return n;
121}
122
123/* Find decoded P value for raw PDEC value */
124static uint32_t pllDecodeP(uint32_t PDEC)
125{
126 uint32_t p, x, i;
127 /* Find PDec */
128 switch (PDEC)
129 {
130 case 0x7FU:
131 p = 0UL;
132 break;
133 case 0x62U:
134 p = 1UL;
135 break;
136 case 0x42U:
137 p = 2UL;
138 break;
139 default:
140 x = 0x10UL;
141 p = 0xFFFFFFFFUL;
142 for (i = PVALMAX; i >= 3UL; i--)
143 {
144 x = (((x ^ (x >> 2UL)) & 1UL) << 4UL) | ((x >> 1UL) & 0xFUL);
145 if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
146 {
147 /* Decoded value of PDEC */
148 p = i;
149 }
150 if (p != 0xFFFFFFFFUL)
151 {
152 break;
153 }
154 }
155 break;
156 }
157 return p;
158}
159
160/* Find decoded M value for raw MDEC value */
161static uint32_t pllDecodeM(uint32_t MDEC)
162{
163 uint32_t m, i, x;
164
165 /* Find MDec */
166 switch (MDEC)
167 {
168 case 0x1FFFFU:
169 m = 0UL;
170 break;
171 case 0x18003U:
172 m = 1UL;
173 break;
174 case 0x10003U:
175 m = 2UL;
176 break;
177 default:
178 x = 0x04000UL;
179 m = 0xFFFFFFFFUL;
180 for (i = MVALMAX; i >= 3UL; i--)
181 {
182 x = (((x ^ (x >> 1UL)) & 1UL) << 14UL) | ((x >> 1UL) & 0x3FFFUL);
183 if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
184 {
185 /* Decoded value of MDEC */
186 m = i;
187 }
188 if (m != 0xFFFFFFFFUL)
189 {
190 break;
191 }
192 }
193 break;
194 }
195 return m;
196}
197
198/* Get predivider (N) from PLL NDEC setting */
199static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
200{
201 uint32_t preDiv = 1U;
202
203 /* Direct input is not used? */
204 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0U)
205 {
206 /* Decode NDEC value to get (N) pre divider */
207 preDiv = pllDecodeN(nDecReg & 0x3FFU);
208 if (preDiv == 0U)
209 {
210 preDiv = 1U;
211 }
212 }
213 /* Adjusted by 1, directi is used to bypass */
214 return preDiv;
215}
216
217/* Get postdivider (P) from PLL PDEC setting */
218static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
219{
220 uint32_t postDiv = 1U;
221
222 /* Direct input is not used? */
223 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U)
224 {
225 /* Decode PDEC value to get (P) post divider */
226 postDiv = 2U * pllDecodeP(pDecReg & 0x7FU);
227 if (postDiv == 0U)
228 {
229 postDiv = 2U;
230 }
231 }
232 /* Adjusted by 1, directo is used to bypass */
233 return postDiv;
234}
235
236/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
237static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
238{
239 uint32_t mMult = 1U;
240
241 /* Decode MDEC value to get (M) multiplier */
242 mMult = pllDecodeM(mDecReg & 0x1FFFFU);
243 if (mMult == 0U)
244 {
245 mMult = 1U;
246 }
247 return mMult;
248}
249
250
251
252/* ----------------------------------------------------------------------------
253 -- Core clock
254 ---------------------------------------------------------------------------- */
255
256uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
257
258/* ----------------------------------------------------------------------------
259 -- SystemInit()
260 ---------------------------------------------------------------------------- */
261
262void SystemInit (void) {
263#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
264 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
265#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
266
267#if defined(__MCUXPRESSO)
268 extern void(*const g_pfnVectors[]) (void);
269 SCB->VTOR = (uint32_t) &g_pfnVectors;
270#else
271 extern void *__Vectors;
272 SCB->VTOR = (uint32_t) &__Vectors;
273#endif
274 SYSCON->ARMTRACECLKDIV = 0U;
275/* Optionally enable RAM banks that may be off by default at reset */
276#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
277 SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
278#endif
279 SystemInitHook();
280}
281
282/* ----------------------------------------------------------------------------
283 -- SystemCoreClockUpdate()
284 ---------------------------------------------------------------------------- */
285
286void SystemCoreClockUpdate (void) {
287uint32_t clkRate = 0U;
288 uint32_t prediv, postdiv;
289 uint64_t workRate;
290
291 switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
292 {
293 case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
294 switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
295 {
296 case 0x00U: /* FRO 12 MHz (fro_12m) */
297 clkRate = CLK_FRO_12MHZ;
298 break;
299 case 0x01U: /* CLKIN Source (clk_in) */
300 clkRate = CLK_CLK_IN;
301 break;
302 case 0x02U: /* Watchdog oscillator (wdt_clk) */
303 clkRate = getWdtOscFreq();
304 break;
305 default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
306 if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) == SYSCON_FROCTRL_SEL_MASK)
307 {
308 clkRate = CLK_FRO_96MHZ;
309 }
310 else
311 {
312 clkRate = CLK_FRO_48MHZ;
313 }
314 break;
315 }
316 break;
317 case 0x02U: /* System PLL clock (pll_clk)*/
318 switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
319 {
320 case 0x00U: /* FRO 12 MHz (fro_12m) */
321 clkRate = CLK_FRO_12MHZ;
322 break;
323 case 0x01U: /* CLKIN Source (clk_in) */
324 clkRate = CLK_CLK_IN;
325 break;
326 case 0x02U: /* Watchdog oscillator (wdt_clk) */
327 clkRate = getWdtOscFreq();
328 break;
329 case 0x03U: /* RTC oscillator 32 kHz output (32k_clk) */
330 clkRate = CLK_RTC_32K_CLK;
331 break;
332 default:
333 clkRate = 0U;
334 break;
335 }
336 if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0U)
337 {
338 /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
339 prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
340 postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
341 /* Adjust input clock */
342 clkRate = clkRate / prediv;
343
344 /* MDEC used for rate */
345 workRate = (uint64_t)(clkRate) * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
346 clkRate = (uint32_t)(workRate / ((uint64_t)postdiv));
347 clkRate = clkRate * 2UL; /* PLL CCO output is divided by 2 before to M-Divider */
348 }
349 break;
350 case 0x03U: /* RTC oscillator 32 kHz output (32k_clk) */
351 clkRate = CLK_RTC_32K_CLK;
352 break;
353 default:
354 clkRate = 0U;
355 break;
356 }
357 SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL);
358}
359
360/* ----------------------------------------------------------------------------
361 -- SystemInitHook()
362 ---------------------------------------------------------------------------- */
363
364__attribute__ ((weak)) void SystemInitHook (void) {
365 /* Void implementation of the weak function. */
366}
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