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1/*
2** ###################################################################
3** Processors: LPC54616J256ET180
4** LPC54616J512BD100
5** LPC54616J512BD208
6** LPC54616J512ET100
7**
8** Compilers: GNU C Compiler
9** IAR ANSI C/C++ Compiler for ARM
10** Keil ARM C/C++ Compiler
11** MCUXpresso Compiler
12**
13** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017
14** Version: rev. 1.2, 2017-06-08
15** Build: b200304
16**
17** Abstract:
18** CMSIS Peripheral Access Layer for LPC54616
19**
20** Copyright 1997-2016 Freescale Semiconductor, Inc.
21** Copyright 2016-2020 NXP
22** All rights reserved.
23**
24** SPDX-License-Identifier: BSD-3-Clause
25**
26** http: www.nxp.com
27** mail: [email protected]
28**
29** Revisions:
30** - rev. 1.0 (2016-08-12)
31** Initial version.
32** - rev. 1.1 (2016-11-25)
33** Update CANFD and Classic CAN register.
34** Add MAC TIMERSTAMP registers.
35** - rev. 1.2 (2017-06-08)
36** Remove RTC_CTRL_RTC_OSC_BYPASS.
37** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
38** Remove RESET and HALT from SYSCON_AHBCLKDIV.
39**
40** ###################################################################
41*/
42
43/*!
44 * @file LPC54616.h
45 * @version 1.2
46 * @date 2017-06-08
47 * @brief CMSIS Peripheral Access Layer for LPC54616
48 *
49 * CMSIS Peripheral Access Layer for LPC54616
50 */
51
52#ifndef _LPC54616_H_
53#define _LPC54616_H_ /**< Symbol preventing repeated inclusion */
54
55/** Memory map major version (memory maps with equal major version number are
56 * compatible) */
57#define MCU_MEM_MAP_VERSION 0x0100U
58/** Memory map minor version */
59#define MCU_MEM_MAP_VERSION_MINOR 0x0002U
60
61
62/* ----------------------------------------------------------------------------
63 -- Interrupt vector numbers
64 ---------------------------------------------------------------------------- */
65
66/*!
67 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
68 * @{
69 */
70
71/** Interrupt Number Definitions */
72#define NUMBER_OF_INT_VECTORS 73 /**< Number of interrupts in the Vector table */
73
74typedef enum IRQn {
75 /* Auxiliary constants */
76 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
77
78 /* Core interrupts */
79 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
80 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
81 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
82 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
83 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
84 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
85 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
86 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
87 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
88
89 /* Device specific interrupts */
90 WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */
91 DMA0_IRQn = 1, /**< DMA controller */
92 GINT0_IRQn = 2, /**< GPIO group 0 */
93 GINT1_IRQn = 3, /**< GPIO group 1 */
94 PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */
95 PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */
96 PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */
97 PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */
98 UTICK0_IRQn = 8, /**< Micro-tick Timer */
99 MRT0_IRQn = 9, /**< Multi-rate timer */
100 CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
101 CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
102 SCT0_IRQn = 12, /**< SCTimer/PWM */
103 CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
104 FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
105 FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
106 FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
107 FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
108 FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
109 FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
110 FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
111 FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
112 ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */
113 ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */
114 ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */
115 DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */
116 HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */
117 USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */
118 USB0_IRQn = 28, /**< USB device */
119 RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */
120 Reserved46_IRQn = 30, /**< Reserved interrupt */
121 Reserved47_IRQn = 31, /**< Reserved interrupt */
122 PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */
123 PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */
124 PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */
125 PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */
126 CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */
127 CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */
128 RIT_IRQn = 38, /**< Repetitive Interrupt Timer */
129 SPIFI0_IRQn = 39, /**< SPI flash interface */
130 FLEXCOMM8_IRQn = 40, /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
131 FLEXCOMM9_IRQn = 41, /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
132 SDIO_IRQn = 42, /**< SD/MMC */
133 CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */
134 CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */
135 CAN1_IRQ0_IRQn = 45, /**< CAN1 interrupt0 */
136 CAN1_IRQ1_IRQn = 46, /**< CAN1 interrupt1 */
137 USB1_IRQn = 47, /**< USB1 interrupt */
138 USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */
139 ETHERNET_IRQn = 49, /**< Ethernet */
140 ETHERNET_PMT_IRQn = 50, /**< Ethernet power management interrupt */
141 ETHERNET_MACLP_IRQn = 51, /**< Ethernet MAC interrupt */
142 EEPROM_IRQn = 52, /**< EEPROM interrupt */
143 LCD_IRQn = 53, /**< LCD interrupt */
144 SHA_IRQn = 54, /**< SHA interrupt */
145 SMARTCARD0_IRQn = 55, /**< Smart card 0 interrupt */
146 SMARTCARD1_IRQn = 56 /**< Smart card 1 interrupt */
147} IRQn_Type;
148
149/*!
150 * @}
151 */ /* end of group Interrupt_vector_numbers */
152
153
154/* ----------------------------------------------------------------------------
155 -- Cortex M4 Core Configuration
156 ---------------------------------------------------------------------------- */
157
158/*!
159 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
160 * @{
161 */
162
163#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
164#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
165#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
166#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
167
168#include "core_cm4.h" /* Core Peripheral Access Layer */
169#include "system_LPC54616.h" /* Device specific configuration file */
170
171/*!
172 * @}
173 */ /* end of group Cortex_Core_Configuration */
174
175
176/* ----------------------------------------------------------------------------
177 -- Mapping Information
178 ---------------------------------------------------------------------------- */
179
180/*!
181 * @addtogroup Mapping_Information Mapping Information
182 * @{
183 */
184
185/** Mapping Information */
186/*!
187 * @addtogroup dma_request
188 * @{
189 */
190
191/*******************************************************************************
192 * Definitions
193 ******************************************************************************/
194
195/*!
196 * @brief Structure for the DMA hardware request
197 *
198 * Defines the structure for the DMA hardware request collections. The user can configure the
199 * hardware request to trigger the DMA transfer accordingly. The index
200 * of the hardware request varies according to the to SoC.
201 */
202typedef enum _dma_request_source
203{
204 kDmaRequestFlexcomm0Rx = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */
205 kDmaRequestFlexcomm0Tx = 1U, /**< Flexcomm Interface 0 TX/I2C Master */
206 kDmaRequestFlexcomm1Rx = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */
207 kDmaRequestFlexcomm1Tx = 3U, /**< Flexcomm Interface 1 TX/I2C Master */
208 kDmaRequestFlexcomm2Rx = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */
209 kDmaRequestFlexcomm2Tx = 5U, /**< Flexcomm Interface 2 TX/I2C Master */
210 kDmaRequestFlexcomm3Rx = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */
211 kDmaRequestFlexcomm3Tx = 7U, /**< Flexcomm Interface 3 TX/I2C Master */
212 kDmaRequestFlexcomm4Rx = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */
213 kDmaRequestFlexcomm4Tx = 9U, /**< Flexcomm Interface 4 TX/I2C Master */
214 kDmaRequestFlexcomm5Rx = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */
215 kDmaRequestFlexcomm5Tx = 11U, /**< Flexcomm Interface 5 TX/I2C Master */
216 kDmaRequestFlexcomm6Rx = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */
217 kDmaRequestFlexcomm6Tx = 13U, /**< Flexcomm Interface 6 TX/I2C Master */
218 kDmaRequestFlexcomm7Rx = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */
219 kDmaRequestFlexcomm7Tx = 15U, /**< Flexcomm Interface 7 TX/I2C Master */
220 kDmaRequestDMIC0 = 16U, /**< Digital microphone interface 0 channel 0 */
221 kDmaRequestDMIC1 = 17U, /**< Digital microphone interface 0 channel 1 */
222 kDmaRequestSPIFI = 18U, /**< SPI Flash Interface */
223 kDmaRequestSHA = 19U, /**< Reserved */
224 kDmaRequestFlexcomm8Rx = 20U, /**< Flexcomm Interface 8 RX/I2C Slave */
225 kDmaRequestFlexcomm8Tx = 21U, /**< Flexcomm Interface 8 TX/I2C Slave */
226 kDmaRequestFlexcomm9Rx = 22U, /**< Flexcomm Interface 9 RX/I2C Slave */
227 kDmaRequestFlexcomm9Tx = 23U, /**< Flexcomm Interface 9 TX/I2C Slave */
228 kDmaRequestSMARTCARD0_RX = 24U, /**< SMARTCARD0 RX */
229 kDmaRequestSMARTCARD0_TX = 25U, /**< SMARTCARD0 TX */
230 kDmaRequestSMARTCARD1_RX = 26U, /**< SMARTCARD1 RX */
231 kDmaRequestSMARTCARD1_TX = 27U, /**< SMARTCARD1 TX */
232 kDmaRequestNoDMARequest28 = 28U, /**< No DMA request 28 */
233 kDmaRequestNoDMARequest29 = 29U, /**< No DMA request 29 */
234} dma_request_source_t;
235
236/* @} */
237
238
239/*!
240 * @}
241 */ /* end of group Mapping_Information */
242
243
244/* ----------------------------------------------------------------------------
245 -- Device Peripheral Access Layer
246 ---------------------------------------------------------------------------- */
247
248/*!
249 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
250 * @{
251 */
252
253
254/*
255** Start of section using anonymous unions
256*/
257
258#if defined(__ARMCC_VERSION)
259 #if (__ARMCC_VERSION >= 6010050)
260 #pragma clang diagnostic push
261 #else
262 #pragma push
263 #pragma anon_unions
264 #endif
265#elif defined(__GNUC__)
266 /* anonymous unions are enabled by default */
267#elif defined(__IAR_SYSTEMS_ICC__)
268 #pragma language=extended
269#else
270 #error Not supported compiler type
271#endif
272
273/* ----------------------------------------------------------------------------
274 -- ADC Peripheral Access Layer
275 ---------------------------------------------------------------------------- */
276
277/*!
278 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
279 * @{
280 */
281
282/** ADC - Register Layout Typedef */
283typedef struct {
284 __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
285 __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
286 __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
287 __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
288 uint8_t RESERVED_0[8];
289 __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
290 __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
291 __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
292 __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
293 __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
294 __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
295 __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
296 __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
297 __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */
298 __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */
299} ADC_Type;
300
301/* ----------------------------------------------------------------------------
302 -- ADC Register Masks
303 ---------------------------------------------------------------------------- */
304
305/*!
306 * @addtogroup ADC_Register_Masks ADC Register Masks
307 * @{
308 */
309
310/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
311/*! @{ */
312#define ADC_CTRL_CLKDIV_MASK (0xFFU)
313#define ADC_CTRL_CLKDIV_SHIFT (0U)
314/*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce
315 * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically,
316 * software should program the smallest value in this field that yields this maximum clock rate or
317 * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may
318 * be desirable. This field is ignored in the asynchronous operating mode.
319 */
320#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
321#define ADC_CTRL_ASYNMODE_MASK (0x100U)
322#define ADC_CTRL_ASYNMODE_SHIFT (8U)
323/*! ASYNMODE - Select clock mode.
324 * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in
325 * the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to
326 * eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger.
327 * In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC
328 * input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger
329 * pulse.
330 * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
331 */
332#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
333#define ADC_CTRL_RESOL_MASK (0x600U)
334#define ADC_CTRL_RESOL_SHIFT (9U)
335/*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher
336 * conversion rates. A single conversion (including one conversion in a burst or sequence) requires the
337 * selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when
338 * the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable
339 * results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate
340 * for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system
341 * clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution
342 * 0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field.
343 * 0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field.
344 * 0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field.
345 * 0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field.
346 */
347#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
348#define ADC_CTRL_BYPASSCAL_MASK (0x800U)
349#define ADC_CTRL_BYPASSCAL_SHIFT (11U)
350/*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset
351 * error is not a concern in the application.
352 * 0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for
353 * offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may
354 * be warranted periodically - especially if operating conditions have changed.
355 * 0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC -
356 * particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set.
357 */
358#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
359#define ADC_CTRL_TSAMP_MASK (0x7000U)
360#define ADC_CTRL_TSAMP_SHIFT (12U)
361/*! TSAMP - Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion
362 * is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions
363 * and the output impedance of the analog source, longer sampling times may be required. See
364 * Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to
365 * seven, by which the sample period will be extended. The total conversion time will increase by
366 * the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A
367 * complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will
368 * be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will
369 * require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock
370 * cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be
371 * extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require
372 * 22 ADC clocks.
373 */
374#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
375/*! @} */
376
377/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
378/*! @{ */
379#define ADC_INSEL_SEL_MASK (0x3U)
380#define ADC_INSEL_SEL_SHIFT (0U)
381/*! SEL - Selects the input source for channel 0. All other values are reserved.
382 * 0b00..ADC0_IN0 function.
383 * 0b11..Internal temperature sensor.
384 */
385#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
386/*! @} */
387
388/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
389/*! @{ */
390#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU)
391#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U)
392/*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this
393 * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be
394 * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1
395 * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via
396 * software command, ADC conversions will be performed on each enabled channel, in sequence,
397 * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31)
398 * is LOW. It is allowed to change this field and set bit 31 in the same write.
399 */
400#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
401#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U)
402#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U)
403/*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion
404 * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order
405 * to avoid generating a spurious trigger, it is recommended writing to this field only when
406 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
407 */
408#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
409#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U)
410#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U)
411/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In
412 * order to avoid generating a spurious trigger, it is recommended writing to this field only when
413 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
414 * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
415 * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
416 */
417#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
418#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U)
419#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U)
420/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization
421 * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a
422 * conversion. There are slightly different criteria for whether or not this bit can be set
423 * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0):
424 * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already
425 * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer).
426 * Whether this bit is set or not, a trigger pulse must be maintained for at least one system
427 * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be
428 * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse
429 * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and
430 * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be
431 * maintained for one system clock period.
432 * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled.
433 * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled.
434 */
435#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
436#define ADC_SEQ_CTRL_START_MASK (0x4000000U)
437#define ADC_SEQ_CTRL_START_SHIFT (26U)
438/*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The
439 * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this
440 * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a
441 * conversion sequence. It will consequently always read back as a zero.
442 */
443#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
444#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U)
445#define ADC_SEQ_CTRL_BURST_SHIFT (27U)
446/*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled
447 * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions
448 * can be halted by clearing this bit. The sequence currently in progress will be completed before
449 * conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
450 */
451#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
452#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U)
453#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U)
454/*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a
455 * single conversion on the next channel in the sequence instead of the default response of
456 * launching an entire sequence of conversions. Once all of the channels comprising a sequence have
457 * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled
458 * channel. Interrupt generation will still occur either after each individual conversion or at
459 * the end of the entire sequence, depending on the state of the MODE bit.
460 */
461#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
462#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U)
463#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U)
464/*! LOWPRIO - Set priority for sequence A.
465 * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
466 * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence
467 * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion
468 * currently in progress will be terminated. The A sequence that was interrupted will automatically resume
469 * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the
470 * conversion sequence will resume from that point.
471 */
472#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
473#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U)
474#define ADC_SEQ_CTRL_MODE_SHIFT (30U)
475/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence
476 * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each
477 * conversion, or the individual channel result registers at the end of the entire sequence. Impacts
478 * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which
479 * overrun conditions contribute to an overrun interrupt as described below.
480 * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC
481 * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The
482 * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger
483 * if enabled.
484 * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A
485 * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in
486 * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun
487 * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
488 */
489#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
490#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U)
491#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U)
492/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be
493 * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state
494 * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered
495 * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care
496 * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE
497 * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be
498 * triggered immediately upon being enabled.
499 * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence
500 * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is
501 * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
502 * 0b1..Enabled. Sequence n is enabled.
503 */
504#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
505/*! @} */
506
507/* The count of ADC_SEQ_CTRL */
508#define ADC_SEQ_CTRL_COUNT (2U)
509
510/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
511/*! @{ */
512#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U)
513#define ADC_SEQ_GDAT_RESULT_SHIFT (4U)
514/*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion
515 * performed under conversion sequence associated with this register. The result is a binary
516 * fraction representing the voltage on the currently-selected input channel as it falls within the
517 * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less
518 * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input
519 * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this
520 * result has not yet been read.
521 */
522#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
523#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U)
524#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U)
525/*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or
526 * within the range established by the designated threshold comparison registers (THRn_LOW and
527 * THRn_HIGH).
528 */
529#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
530#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U)
531#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U)
532/*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a
533 * crossing of the threshold level established by the designated LOW threshold comparison register
534 * (THRn_LOW) and, if so, in what direction the crossing occurred.
535 */
536#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
537#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U)
538#define ADC_SEQ_GDAT_CHN_SHIFT (26U)
539/*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000
540 * identifies channel 0, 0001 channel 1, etc.).
541 */
542#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
543#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U)
544#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U)
545/*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a
546 * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along
547 * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun
548 * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set
549 * to '0' (and if the overrun interrupt is enabled).
550 */
551#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
552#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U)
553#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U)
554/*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded
555 * into the RESULT field. It is cleared whenever this register is read. This bit will cause a
556 * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that
557 * sequence is set to 0 (and if the interrupt is enabled).
558 */
559#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
560/*! @} */
561
562/* The count of ADC_SEQ_GDAT */
563#define ADC_SEQ_GDAT_COUNT (2U)
564
565/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
566/*! @{ */
567#define ADC_DAT_RESULT_MASK (0xFFF0U)
568#define ADC_DAT_RESULT_SHIFT (4U)
569/*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed
570 * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin,
571 * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on
572 * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that
573 * the voltage on the input was close to, equal to, or greater than that on VREFP.
574 */
575#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
576#define ADC_DAT_THCMPRANGE_MASK (0x30000U)
577#define ADC_DAT_THCMPRANGE_SHIFT (16U)
578/*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion
579 * was greater than or equal to the value programmed into the designated LOW threshold register
580 * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold
581 * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value
582 * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last
583 * completed conversion was greater than the value programmed into the designated HIGH threshold
584 * register (THRn_HIGH). 0x3 = Reserved.
585 */
586#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
587#define ADC_DAT_THCMPCROSS_MASK (0xC0000U)
588#define ADC_DAT_THCMPCROSS_SHIFT (18U)
589/*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The
590 * most recent completed conversion on this channel had the same relationship (above or below) to
591 * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the
592 * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing
593 * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the
594 * previous sample on this channel was above the threshold value established by the designated LOW
595 * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward
596 * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred
597 * - i.e. the previous sample on this channel was below the threshold value established by the
598 * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
599 */
600#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
601#define ADC_DAT_CHANNEL_MASK (0x3C000000U)
602#define ADC_DAT_CHANNEL_SHIFT (26U)
603/*! CHANNEL - This field is hard-coded to contain the channel number that this particular register
604 * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1
605 * register, etc)
606 */
607#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
608#define ADC_DAT_OVERRUN_MASK (0x40000000U)
609#define ADC_DAT_OVERRUN_SHIFT (30U)
610/*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and
611 * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit
612 * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when
613 * the data related to this channel is read from either of the global SEQn_GDAT registers. This
614 * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if
615 * the overrun interrupt is enabled. While it is allowed to include the same channels in both
616 * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the
617 * data registers associated with any of the channels that are shared between the two sequences. Any
618 * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
619 */
620#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
621#define ADC_DAT_DATAVALID_MASK (0x80000000U)
622#define ADC_DAT_DATAVALID_SHIFT (31U)
623/*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is
624 * cleared whenever this register is read or when the data related to this channel is read from
625 * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in
626 * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in
627 * the data registers associated with any of the channels that are shared between the two
628 * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
629 */
630#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
631/*! @} */
632
633/* The count of ADC_DAT */
634#define ADC_DAT_COUNT (12U)
635
636/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
637/*! @{ */
638#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U)
639#define ADC_THR0_LOW_THRLOW_SHIFT (4U)
640/*! THRLOW - Low threshold value against which ADC results will be compared
641 */
642#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
643/*! @} */
644
645/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
646/*! @{ */
647#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U)
648#define ADC_THR1_LOW_THRLOW_SHIFT (4U)
649/*! THRLOW - Low threshold value against which ADC results will be compared
650 */
651#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
652/*! @} */
653
654/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
655/*! @{ */
656#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U)
657#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U)
658/*! THRHIGH - High threshold value against which ADC results will be compared
659 */
660#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
661/*! @} */
662
663/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
664/*! @{ */
665#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U)
666#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U)
667/*! THRHIGH - High threshold value against which ADC results will be compared
668 */
669#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
670/*! @} */
671
672/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
673/*! @{ */
674#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U)
675#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U)
676/*! CH0_THRSEL - Threshold select for channel 0.
677 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
678 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
679 */
680#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
681#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U)
682#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U)
683/*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0.
684 */
685#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
686#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U)
687#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U)
688/*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0.
689 */
690#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
691#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U)
692#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U)
693/*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0.
694 */
695#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
696#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U)
697#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U)
698/*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0.
699 */
700#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
701#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U)
702#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U)
703/*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0.
704 */
705#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
706#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U)
707#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U)
708/*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0.
709 */
710#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
711#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U)
712#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U)
713/*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0.
714 */
715#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
716#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U)
717#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U)
718/*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0.
719 */
720#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
721#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U)
722#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U)
723/*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0.
724 */
725#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
726#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U)
727#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U)
728/*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0.
729 */
730#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
731#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U)
732#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U)
733/*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0.
734 */
735#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
736/*! @} */
737
738/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
739/*! @{ */
740#define ADC_INTEN_SEQA_INTEN_MASK (0x1U)
741#define ADC_INTEN_SEQA_INTEN_SHIFT (0U)
742/*! SEQA_INTEN - Sequence A interrupt enable.
743 * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled.
744 * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of
745 * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of
746 * conversions, depending on the MODE bit in the SEQA_CTRL register.
747 */
748#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
749#define ADC_INTEN_SEQB_INTEN_MASK (0x2U)
750#define ADC_INTEN_SEQB_INTEN_SHIFT (1U)
751/*! SEQB_INTEN - Sequence B interrupt enable.
752 * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled.
753 * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of
754 * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of
755 * conversions, depending on the MODE bit in the SEQB_CTRL register.
756 */
757#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
758#define ADC_INTEN_OVR_INTEN_MASK (0x4U)
759#define ADC_INTEN_OVR_INTEN_SHIFT (2U)
760/*! OVR_INTEN - Overrun interrupt enable.
761 * 0b0..Disabled. The overrun interrupt is disabled.
762 * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel
763 * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular
764 * sequence is 0, then an overrun in the global data register for that sequence will also cause this
765 * interrupt/DMA trigger to be asserted.
766 */
767#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
768#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U)
769#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U)
770/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0.
771 * 0b00..Disabled.
772 * 0b01..Outside threshold.
773 * 0b10..Crossing threshold.
774 * 0b11..Reserved
775 */
776#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
777#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U)
778#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U)
779/*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0.
780 */
781#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
782#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U)
783#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U)
784/*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0.
785 */
786#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
787#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U)
788#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U)
789/*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0.
790 */
791#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
792#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U)
793#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U)
794/*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0.
795 */
796#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
797#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U)
798#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U)
799/*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0.
800 */
801#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
802#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U)
803#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U)
804/*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0.
805 */
806#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
807#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U)
808#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U)
809/*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0.
810 */
811#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
812#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U)
813#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U)
814/*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0.
815 */
816#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
817#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U)
818#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U)
819/*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0.
820 */
821#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
822#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U)
823#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U)
824/*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0.
825 */
826#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
827#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U)
828#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U)
829/*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0.
830 */
831#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
832/*! @} */
833
834/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
835/*! @{ */
836#define ADC_FLAGS_THCMP0_MASK (0x1U)
837#define ADC_FLAGS_THCMP0_SHIFT (0U)
838/*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or
839 * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by
840 * writing a 1.
841 */
842#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
843#define ADC_FLAGS_THCMP1_MASK (0x2U)
844#define ADC_FLAGS_THCMP1_SHIFT (1U)
845/*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0.
846 */
847#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
848#define ADC_FLAGS_THCMP2_MASK (0x4U)
849#define ADC_FLAGS_THCMP2_SHIFT (2U)
850/*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0.
851 */
852#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
853#define ADC_FLAGS_THCMP3_MASK (0x8U)
854#define ADC_FLAGS_THCMP3_SHIFT (3U)
855/*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0.
856 */
857#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
858#define ADC_FLAGS_THCMP4_MASK (0x10U)
859#define ADC_FLAGS_THCMP4_SHIFT (4U)
860/*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0.
861 */
862#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
863#define ADC_FLAGS_THCMP5_MASK (0x20U)
864#define ADC_FLAGS_THCMP5_SHIFT (5U)
865/*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0.
866 */
867#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
868#define ADC_FLAGS_THCMP6_MASK (0x40U)
869#define ADC_FLAGS_THCMP6_SHIFT (6U)
870/*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0.
871 */
872#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
873#define ADC_FLAGS_THCMP7_MASK (0x80U)
874#define ADC_FLAGS_THCMP7_SHIFT (7U)
875/*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0.
876 */
877#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
878#define ADC_FLAGS_THCMP8_MASK (0x100U)
879#define ADC_FLAGS_THCMP8_SHIFT (8U)
880/*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0.
881 */
882#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
883#define ADC_FLAGS_THCMP9_MASK (0x200U)
884#define ADC_FLAGS_THCMP9_SHIFT (9U)
885/*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0.
886 */
887#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
888#define ADC_FLAGS_THCMP10_MASK (0x400U)
889#define ADC_FLAGS_THCMP10_SHIFT (10U)
890/*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0.
891 */
892#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
893#define ADC_FLAGS_THCMP11_MASK (0x800U)
894#define ADC_FLAGS_THCMP11_SHIFT (11U)
895/*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0.
896 */
897#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
898#define ADC_FLAGS_OVERRUN0_MASK (0x1000U)
899#define ADC_FLAGS_OVERRUN0_SHIFT (12U)
900/*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0
901 */
902#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
903#define ADC_FLAGS_OVERRUN1_MASK (0x2000U)
904#define ADC_FLAGS_OVERRUN1_SHIFT (13U)
905/*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1
906 */
907#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
908#define ADC_FLAGS_OVERRUN2_MASK (0x4000U)
909#define ADC_FLAGS_OVERRUN2_SHIFT (14U)
910/*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2
911 */
912#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
913#define ADC_FLAGS_OVERRUN3_MASK (0x8000U)
914#define ADC_FLAGS_OVERRUN3_SHIFT (15U)
915/*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3
916 */
917#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
918#define ADC_FLAGS_OVERRUN4_MASK (0x10000U)
919#define ADC_FLAGS_OVERRUN4_SHIFT (16U)
920/*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4
921 */
922#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
923#define ADC_FLAGS_OVERRUN5_MASK (0x20000U)
924#define ADC_FLAGS_OVERRUN5_SHIFT (17U)
925/*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5
926 */
927#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
928#define ADC_FLAGS_OVERRUN6_MASK (0x40000U)
929#define ADC_FLAGS_OVERRUN6_SHIFT (18U)
930/*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6
931 */
932#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
933#define ADC_FLAGS_OVERRUN7_MASK (0x80000U)
934#define ADC_FLAGS_OVERRUN7_SHIFT (19U)
935/*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7
936 */
937#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
938#define ADC_FLAGS_OVERRUN8_MASK (0x100000U)
939#define ADC_FLAGS_OVERRUN8_SHIFT (20U)
940/*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8
941 */
942#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
943#define ADC_FLAGS_OVERRUN9_MASK (0x200000U)
944#define ADC_FLAGS_OVERRUN9_SHIFT (21U)
945/*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9
946 */
947#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
948#define ADC_FLAGS_OVERRUN10_MASK (0x400000U)
949#define ADC_FLAGS_OVERRUN10_SHIFT (22U)
950/*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10
951 */
952#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
953#define ADC_FLAGS_OVERRUN11_MASK (0x800000U)
954#define ADC_FLAGS_OVERRUN11_SHIFT (23U)
955/*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11
956 */
957#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
958#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U)
959#define ADC_FLAGS_SEQA_OVR_SHIFT (24U)
960/*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register
961 */
962#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
963#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U)
964#define ADC_FLAGS_SEQB_OVR_SHIFT (25U)
965/*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register
966 */
967#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
968#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U)
969#define ADC_FLAGS_SEQA_INT_SHIFT (28U)
970/*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0,
971 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which
972 * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared
973 * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register
974 * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be
975 * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN
976 * register.
977 */
978#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
979#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U)
980#define ADC_FLAGS_SEQB_INT_SHIFT (29U)
981/*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0,
982 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which
983 * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared
984 * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register
985 * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be
986 * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN
987 * register.
988 */
989#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
990#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U)
991#define ADC_FLAGS_THCMP_INT_SHIFT (30U)
992/*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in
993 * the lower bits of this register are set to 1 (due to an enabled out-of-range or
994 * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be
995 * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared
996 * when all of the individual threshold flags are cleared via writing 1s to those bits.
997 */
998#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
999#define ADC_FLAGS_OVR_INT_MASK (0x80000000U)
1000#define ADC_FLAGS_OVR_INT_SHIFT (31U)
1001/*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data
1002 * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers
1003 * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this
1004 * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all
1005 * of the individual overrun bits have been cleared via reading the corresponding data registers.
1006 */
1007#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
1008/*! @} */
1009
1010/*! @name STARTUP - ADC Startup register. */
1011/*! @{ */
1012#define ADC_STARTUP_ADC_ENA_MASK (0x1U)
1013#define ADC_STARTUP_ADC_ENA_SHIFT (0U)
1014/*! ADC_ENA - ADC Enable bit. This bit can only be set to a 1 by software. It is cleared
1015 * automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds
1016 * after the ADC is powered up (typically by altering a system-level ADC power control bit).
1017 */
1018#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
1019#define ADC_STARTUP_ADC_INIT_MASK (0x2U)
1020#define ADC_STARTUP_ADC_INIT_SHIFT (1U)
1021/*! ADC_INIT - ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine
1022 * will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not
1023 * calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is
1024 * required if a calibration is not performed. It will also reload the stored calibration value from
1025 * a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the
1026 * ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or
1027 * an ADC dummy conversion cycle is required. It should not be set during the same write that
1028 * sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically
1029 * when the 'dummy' conversion cycle completes.
1030 */
1031#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
1032/*! @} */
1033
1034/*! @name CALIB - ADC Calibration register. */
1035/*! @{ */
1036#define ADC_CALIB_CALIB_MASK (0x1U)
1037#define ADC_CALIB_CALIB_SHIFT (0U)
1038/*! CALIB - Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can
1039 * only be set to a '1' by software. It is cleared automatically when the calibration cycle
1040 * completes.
1041 */
1042#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
1043#define ADC_CALIB_CALREQD_MASK (0x2U)
1044#define ADC_CALIB_CALREQD_SHIFT (1U)
1045/*! CALREQD - Calibration required. This read-only bit indicates if calibration is required when
1046 * enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was
1047 * powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to
1048 * determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP
1049 * register) to launch the ADC initialization process which includes a 'dummy' conversion cycle.
1050 * Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks
1051 * required for calibration.
1052 */
1053#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
1054#define ADC_CALIB_CALVALUE_MASK (0x1FCU)
1055#define ADC_CALIB_CALVALUE_SHIFT (2U)
1056/*! CALVALUE - Calibration Value. This read-only field displays the calibration value established
1057 * during last calibration cycle. This value is not typically of any use to the user.
1058 */
1059#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
1060/*! @} */
1061
1062
1063/*!
1064 * @}
1065 */ /* end of group ADC_Register_Masks */
1066
1067
1068/* ADC - Peripheral instance base addresses */
1069/** Peripheral ADC0 base address */
1070#define ADC0_BASE (0x400A0000u)
1071/** Peripheral ADC0 base pointer */
1072#define ADC0 ((ADC_Type *)ADC0_BASE)
1073/** Array initializer of ADC peripheral base addresses */
1074#define ADC_BASE_ADDRS { ADC0_BASE }
1075/** Array initializer of ADC peripheral base pointers */
1076#define ADC_BASE_PTRS { ADC0 }
1077/** Interrupt vectors for the ADC peripheral type */
1078#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
1079#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn }
1080
1081/*!
1082 * @}
1083 */ /* end of group ADC_Peripheral_Access_Layer */
1084
1085
1086/* ----------------------------------------------------------------------------
1087 -- ASYNC_SYSCON Peripheral Access Layer
1088 ---------------------------------------------------------------------------- */
1089
1090/*!
1091 * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
1092 * @{
1093 */
1094
1095/** ASYNC_SYSCON - Register Layout Typedef */
1096typedef struct {
1097 __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */
1098 __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
1099 __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
1100 uint8_t RESERVED_0[4];
1101 __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */
1102 __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
1103 __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
1104 uint8_t RESERVED_1[4];
1105 __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */
1106} ASYNC_SYSCON_Type;
1107
1108/* ----------------------------------------------------------------------------
1109 -- ASYNC_SYSCON Register Masks
1110 ---------------------------------------------------------------------------- */
1111
1112/*!
1113 * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
1114 * @{
1115 */
1116
1117/*! @name ASYNCPRESETCTRL - Async peripheral reset control */
1118/*! @{ */
1119#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
1120#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
1121/*! CTIMER3 - Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
1122 */
1123#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
1124#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
1125#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
1126/*! CTIMER4 - Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
1127 */
1128#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
1129/*! @} */
1130
1131/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
1132/*! @{ */
1133#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
1134#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
1135/*! ARST_SET - Writing ones to this register sets the corresponding bit or bits in the
1136 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1137 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1138 */
1139#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
1140/*! @} */
1141
1142/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
1143/*! @{ */
1144#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
1145#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
1146/*! ARST_CLR - Writing ones to this register clears the corresponding bit or bits in the
1147 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1148 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1149 */
1150#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
1151/*! @} */
1152
1153/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
1154/*! @{ */
1155#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
1156#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
1157/*! CTIMER3 - Controls the clock for CTIMER3. 0 = Disable; 1 = Enable.
1158 */
1159#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
1160#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
1161#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
1162/*! CTIMER4 - Controls the clock for CTIMER4. 0 = Disable; 1 = Enable.
1163 */
1164#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
1165/*! @} */
1166
1167/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
1168/*! @{ */
1169#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
1170#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
1171/*! ACLK_SET - Writing ones to this register sets the corresponding bit or bits in the
1172 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1173 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1174 */
1175#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
1176/*! @} */
1177
1178/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
1179/*! @{ */
1180#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
1181#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
1182/*! ACLK_CLR - Writing ones to this register clears the corresponding bit or bits in the
1183 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1184 * ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them.
1185 */
1186#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
1187/*! @} */
1188
1189/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
1190/*! @{ */
1191#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U)
1192#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U)
1193/*! SEL - Clock source for asynchronous clock source selector A
1194 * 0b00..Main clock (main_clk)
1195 * 0b01..FRO 12 MHz (fro_12m)
1196 * 0b10..Audio PLL clock.(AUDPLL_BYPASS)
1197 * 0b11..fc6 fclk (fc6_fclk)
1198 */
1199#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
1200/*! @} */
1201
1202
1203/*!
1204 * @}
1205 */ /* end of group ASYNC_SYSCON_Register_Masks */
1206
1207
1208/* ASYNC_SYSCON - Peripheral instance base addresses */
1209/** Peripheral ASYNC_SYSCON base address */
1210#define ASYNC_SYSCON_BASE (0x40040000u)
1211/** Peripheral ASYNC_SYSCON base pointer */
1212#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
1213/** Array initializer of ASYNC_SYSCON peripheral base addresses */
1214#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE }
1215/** Array initializer of ASYNC_SYSCON peripheral base pointers */
1216#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON }
1217
1218/*!
1219 * @}
1220 */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
1221
1222
1223/* ----------------------------------------------------------------------------
1224 -- CAN Peripheral Access Layer
1225 ---------------------------------------------------------------------------- */
1226
1227/*!
1228 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
1229 * @{
1230 */
1231
1232/** CAN - Register Layout Typedef */
1233typedef struct {
1234 uint8_t RESERVED_0[12];
1235 __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */
1236 __IO uint32_t TEST; /**< Test Register, offset: 0x10 */
1237 uint8_t RESERVED_1[4];
1238 __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */
1239 __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */
1240 __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */
1241 __IO uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */
1242 __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */
1243 __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */
1244 uint8_t RESERVED_2[16];
1245 __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */
1246 __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */
1247 __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */
1248 uint8_t RESERVED_3[4];
1249 __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */
1250 __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */
1251 __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */
1252 __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */
1253 uint8_t RESERVED_4[32];
1254 __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */
1255 __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */
1256 __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */
1257 uint8_t RESERVED_5[4];
1258 __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */
1259 __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */
1260 __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */
1261 __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */
1262 __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */
1263 __IO uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */
1264 __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */
1265 __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */
1266 __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */
1267 __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */
1268 __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */
1269 __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */
1270 __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */
1271 __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */
1272 __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */
1273 __IO uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */
1274 __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */
1275 __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */
1276 __IO uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */
1277 __IO uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */
1278 __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */
1279 __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */
1280 uint8_t RESERVED_6[8];
1281 __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */
1282 __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */
1283 __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */
1284 uint8_t RESERVED_7[260];
1285 __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */
1286 uint8_t RESERVED_8[508];
1287 __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */
1288 uint8_t RESERVED_9[508];
1289 __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */
1290} CAN_Type;
1291
1292/* ----------------------------------------------------------------------------
1293 -- CAN Register Masks
1294 ---------------------------------------------------------------------------- */
1295
1296/*!
1297 * @addtogroup CAN_Register_Masks CAN Register Masks
1298 * @{
1299 */
1300
1301/*! @name DBTP - Data Bit Timing Prescaler Register */
1302/*! @{ */
1303#define CAN_DBTP_DSJW_MASK (0xFU)
1304#define CAN_DBTP_DSJW_SHIFT (0U)
1305/*! DSJW - Data (re)synchronization jump width.
1306 */
1307#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK)
1308#define CAN_DBTP_DTSEG2_MASK (0xF0U)
1309#define CAN_DBTP_DTSEG2_SHIFT (4U)
1310/*! DTSEG2 - Data time segment after sample point.
1311 */
1312#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK)
1313#define CAN_DBTP_DTSEG1_MASK (0x1F00U)
1314#define CAN_DBTP_DTSEG1_SHIFT (8U)
1315/*! DTSEG1 - Data time segment before sample point.
1316 */
1317#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK)
1318#define CAN_DBTP_DBRP_MASK (0x1F0000U)
1319#define CAN_DBTP_DBRP_SHIFT (16U)
1320/*! DBRP - Data bit rate prescaler.
1321 */
1322#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK)
1323#define CAN_DBTP_TDC_MASK (0x800000U)
1324#define CAN_DBTP_TDC_SHIFT (23U)
1325/*! TDC - Transmitter delay compensation.
1326 */
1327#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK)
1328/*! @} */
1329
1330/*! @name TEST - Test Register */
1331/*! @{ */
1332#define CAN_TEST_LBCK_MASK (0x10U)
1333#define CAN_TEST_LBCK_SHIFT (4U)
1334/*! LBCK - Loop back mode.
1335 */
1336#define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)
1337#define CAN_TEST_TX_MASK (0x60U)
1338#define CAN_TEST_TX_SHIFT (5U)
1339/*! TX - Control of transmit pin.
1340 */
1341#define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)
1342#define CAN_TEST_RX_MASK (0x80U)
1343#define CAN_TEST_RX_SHIFT (7U)
1344/*! RX - Monitors the actual value of the CAN_RXD.
1345 */
1346#define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)
1347/*! @} */
1348
1349/*! @name CCCR - CC Control Register */
1350/*! @{ */
1351#define CAN_CCCR_INIT_MASK (0x1U)
1352#define CAN_CCCR_INIT_SHIFT (0U)
1353/*! INIT - Initialization.
1354 */
1355#define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)
1356#define CAN_CCCR_CCE_MASK (0x2U)
1357#define CAN_CCCR_CCE_SHIFT (1U)
1358/*! CCE - Configuration change enable.
1359 */
1360#define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)
1361#define CAN_CCCR_ASM_MASK (0x4U)
1362#define CAN_CCCR_ASM_SHIFT (2U)
1363/*! ASM - Restricted operational mode.
1364 */
1365#define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)
1366#define CAN_CCCR_CSA_MASK (0x8U)
1367#define CAN_CCCR_CSA_SHIFT (3U)
1368/*! CSA - Clock Stop Acknowledge.
1369 */
1370#define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)
1371#define CAN_CCCR_CSR_MASK (0x10U)
1372#define CAN_CCCR_CSR_SHIFT (4U)
1373/*! CSR - Clock Stop Request.
1374 */
1375#define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)
1376#define CAN_CCCR_MON_MASK (0x20U)
1377#define CAN_CCCR_MON_SHIFT (5U)
1378/*! MON - Bus monitoring mode.
1379 */
1380#define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)
1381#define CAN_CCCR_DAR_MASK (0x40U)
1382#define CAN_CCCR_DAR_SHIFT (6U)
1383/*! DAR - Disable automatic retransmission.
1384 */
1385#define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)
1386#define CAN_CCCR_TEST_MASK (0x80U)
1387#define CAN_CCCR_TEST_SHIFT (7U)
1388/*! TEST - Test mode enable.
1389 */
1390#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
1391#define CAN_CCCR_FDOE_MASK (0x100U)
1392#define CAN_CCCR_FDOE_SHIFT (8U)
1393/*! FDOE - CAN FD operation enable.
1394 */
1395#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK)
1396#define CAN_CCCR_BRSE_MASK (0x200U)
1397#define CAN_CCCR_BRSE_SHIFT (9U)
1398/*! BRSE - When CAN FD operation is disabled, this bit is not evaluated.
1399 */
1400#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK)
1401#define CAN_CCCR_PXHD_MASK (0x1000U)
1402#define CAN_CCCR_PXHD_SHIFT (12U)
1403/*! PXHD - Protocol exception handling disable.
1404 */
1405#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
1406#define CAN_CCCR_EFBI_MASK (0x2000U)
1407#define CAN_CCCR_EFBI_SHIFT (13U)
1408/*! EFBI - Edge filtering during bus integration.
1409 */
1410#define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)
1411#define CAN_CCCR_TXP_MASK (0x4000U)
1412#define CAN_CCCR_TXP_SHIFT (14U)
1413/*! TXP - Transmit pause.
1414 */
1415#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
1416#define CAN_CCCR_NISO_MASK (0x8000U)
1417#define CAN_CCCR_NISO_SHIFT (15U)
1418/*! NISO - Non ISO operation.
1419 */
1420#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK)
1421/*! @} */
1422
1423/*! @name NBTP - Nominal Bit Timing and Prescaler Register */
1424/*! @{ */
1425#define CAN_NBTP_NTSEG2_MASK (0x7FU)
1426#define CAN_NBTP_NTSEG2_SHIFT (0U)
1427/*! NTSEG2 - Nominal time segment after sample point.
1428 */
1429#define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)
1430#define CAN_NBTP_NTSEG1_MASK (0xFF00U)
1431#define CAN_NBTP_NTSEG1_SHIFT (8U)
1432/*! NTSEG1 - Nominal time segment before sample point.
1433 */
1434#define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)
1435#define CAN_NBTP_NBRP_MASK (0x1FF0000U)
1436#define CAN_NBTP_NBRP_SHIFT (16U)
1437/*! NBRP - Nominal bit rate prescaler.
1438 */
1439#define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)
1440#define CAN_NBTP_NSJW_MASK (0xFE000000U)
1441#define CAN_NBTP_NSJW_SHIFT (25U)
1442/*! NSJW - Nominal (re)synchronization jump width.
1443 */
1444#define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)
1445/*! @} */
1446
1447/*! @name TSCC - Timestamp Counter Configuration */
1448/*! @{ */
1449#define CAN_TSCC_TSS_MASK (0x3U)
1450#define CAN_TSCC_TSS_SHIFT (0U)
1451/*! TSS - Timestamp select.
1452 */
1453#define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)
1454#define CAN_TSCC_TCP_MASK (0xF0000U)
1455#define CAN_TSCC_TCP_SHIFT (16U)
1456/*! TCP - Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times.
1457 */
1458#define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)
1459/*! @} */
1460
1461/*! @name TSCV - Timestamp Counter Value */
1462/*! @{ */
1463#define CAN_TSCV_TSC_MASK (0xFFFFU)
1464#define CAN_TSCV_TSC_SHIFT (0U)
1465/*! TSC - Timestamp counter.
1466 */
1467#define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)
1468/*! @} */
1469
1470/*! @name TOCC - Timeout Counter Configuration */
1471/*! @{ */
1472#define CAN_TOCC_ETOC_MASK (0x1U)
1473#define CAN_TOCC_ETOC_SHIFT (0U)
1474/*! ETOC - Enable timeout counter.
1475 */
1476#define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)
1477#define CAN_TOCC_TOS_MASK (0x6U)
1478#define CAN_TOCC_TOS_SHIFT (1U)
1479/*! TOS - Timeout select.
1480 */
1481#define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)
1482#define CAN_TOCC_TOP_MASK (0xFFFF0000U)
1483#define CAN_TOCC_TOP_SHIFT (16U)
1484/*! TOP - Timeout period.
1485 */
1486#define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)
1487/*! @} */
1488
1489/*! @name TOCV - Timeout Counter Value */
1490/*! @{ */
1491#define CAN_TOCV_TOC_MASK (0xFFFFU)
1492#define CAN_TOCV_TOC_SHIFT (0U)
1493/*! TOC - Timeout counter.
1494 */
1495#define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)
1496/*! @} */
1497
1498/*! @name ECR - Error Counter Register */
1499/*! @{ */
1500#define CAN_ECR_TEC_MASK (0xFFU)
1501#define CAN_ECR_TEC_SHIFT (0U)
1502/*! TEC - Transmit error counter.
1503 */
1504#define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)
1505#define CAN_ECR_REC_MASK (0x7F00U)
1506#define CAN_ECR_REC_SHIFT (8U)
1507/*! REC - Receive error counter.
1508 */
1509#define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)
1510#define CAN_ECR_RP_MASK (0x8000U)
1511#define CAN_ECR_RP_SHIFT (15U)
1512/*! RP - Receive error passive.
1513 */
1514#define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)
1515#define CAN_ECR_CEL_MASK (0xFF0000U)
1516#define CAN_ECR_CEL_SHIFT (16U)
1517/*! CEL - CAN error logging.
1518 */
1519#define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)
1520/*! @} */
1521
1522/*! @name PSR - Protocol Status Register */
1523/*! @{ */
1524#define CAN_PSR_LEC_MASK (0x7U)
1525#define CAN_PSR_LEC_SHIFT (0U)
1526/*! LEC - Last error code.
1527 */
1528#define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)
1529#define CAN_PSR_ACT_MASK (0x18U)
1530#define CAN_PSR_ACT_SHIFT (3U)
1531/*! ACT - Activity.
1532 */
1533#define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)
1534#define CAN_PSR_EP_MASK (0x20U)
1535#define CAN_PSR_EP_SHIFT (5U)
1536/*! EP - Error Passive.
1537 */
1538#define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)
1539#define CAN_PSR_EW_MASK (0x40U)
1540#define CAN_PSR_EW_SHIFT (6U)
1541/*! EW - Warning status.
1542 */
1543#define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)
1544#define CAN_PSR_BO_MASK (0x80U)
1545#define CAN_PSR_BO_SHIFT (7U)
1546/*! BO - Bus Off Status.
1547 */
1548#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
1549#define CAN_PSR_DLEC_MASK (0x700U)
1550#define CAN_PSR_DLEC_SHIFT (8U)
1551/*! DLEC - Data phase last error code.
1552 */
1553#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK)
1554#define CAN_PSR_RESI_MASK (0x800U)
1555#define CAN_PSR_RESI_SHIFT (11U)
1556/*! RESI - ESI flag of the last received CAN FD message.
1557 */
1558#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK)
1559#define CAN_PSR_RBRS_MASK (0x1000U)
1560#define CAN_PSR_RBRS_SHIFT (12U)
1561/*! RBRS - BRS flag of last received CAN FD message.
1562 */
1563#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK)
1564#define CAN_PSR_RFDF_MASK (0x2000U)
1565#define CAN_PSR_RFDF_SHIFT (13U)
1566/*! RFDF - Received a CAN FD message.
1567 */
1568#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK)
1569#define CAN_PSR_PXE_MASK (0x4000U)
1570#define CAN_PSR_PXE_SHIFT (14U)
1571/*! PXE - Protocol exception event.
1572 */
1573#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
1574#define CAN_PSR_TDCV_MASK (0x7F0000U)
1575#define CAN_PSR_TDCV_SHIFT (16U)
1576/*! TDCV - Transmitter delay compensation value.
1577 */
1578#define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)
1579/*! @} */
1580
1581/*! @name TDCR - Transmitter Delay Compensator Register */
1582/*! @{ */
1583#define CAN_TDCR_TDCF_MASK (0x7FU)
1584#define CAN_TDCR_TDCF_SHIFT (0U)
1585/*! TDCF - Transmitter delay compensation filter window length.
1586 */
1587#define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)
1588#define CAN_TDCR_TDCO_MASK (0x7F00U)
1589#define CAN_TDCR_TDCO_SHIFT (8U)
1590/*! TDCO - Transmitter delay compensation offset.
1591 */
1592#define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)
1593/*! @} */
1594
1595/*! @name IR - Interrupt Register */
1596/*! @{ */
1597#define CAN_IR_RF0N_MASK (0x1U)
1598#define CAN_IR_RF0N_SHIFT (0U)
1599/*! RF0N - Rx FIFO 0 new message.
1600 */
1601#define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)
1602#define CAN_IR_RF0W_MASK (0x2U)
1603#define CAN_IR_RF0W_SHIFT (1U)
1604/*! RF0W - Rx FIFO 0 watermark reached.
1605 */
1606#define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)
1607#define CAN_IR_RF0F_MASK (0x4U)
1608#define CAN_IR_RF0F_SHIFT (2U)
1609/*! RF0F - Rx FIFO 0 full.
1610 */
1611#define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)
1612#define CAN_IR_RF0L_MASK (0x8U)
1613#define CAN_IR_RF0L_SHIFT (3U)
1614/*! RF0L - Rx FIFO 0 message lost.
1615 */
1616#define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)
1617#define CAN_IR_RF1N_MASK (0x10U)
1618#define CAN_IR_RF1N_SHIFT (4U)
1619/*! RF1N - Rx FIFO 1 new message.
1620 */
1621#define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)
1622#define CAN_IR_RF1W_MASK (0x20U)
1623#define CAN_IR_RF1W_SHIFT (5U)
1624/*! RF1W - Rx FIFO 1 watermark reached.
1625 */
1626#define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)
1627#define CAN_IR_RF1F_MASK (0x40U)
1628#define CAN_IR_RF1F_SHIFT (6U)
1629/*! RF1F - Rx FIFO 1 full.
1630 */
1631#define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)
1632#define CAN_IR_RF1L_MASK (0x80U)
1633#define CAN_IR_RF1L_SHIFT (7U)
1634/*! RF1L - Rx FIFO 1 message lost.
1635 */
1636#define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)
1637#define CAN_IR_HPM_MASK (0x100U)
1638#define CAN_IR_HPM_SHIFT (8U)
1639/*! HPM - High priority message.
1640 */
1641#define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)
1642#define CAN_IR_TC_MASK (0x200U)
1643#define CAN_IR_TC_SHIFT (9U)
1644/*! TC - Transmission completed.
1645 */
1646#define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)
1647#define CAN_IR_TCF_MASK (0x400U)
1648#define CAN_IR_TCF_SHIFT (10U)
1649/*! TCF - Transmission cancellation finished.
1650 */
1651#define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)
1652#define CAN_IR_TFE_MASK (0x800U)
1653#define CAN_IR_TFE_SHIFT (11U)
1654/*! TFE - Tx FIFO empty.
1655 */
1656#define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)
1657#define CAN_IR_TEFN_MASK (0x1000U)
1658#define CAN_IR_TEFN_SHIFT (12U)
1659/*! TEFN - Tx event FIFO new entry.
1660 */
1661#define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)
1662#define CAN_IR_TEFW_MASK (0x2000U)
1663#define CAN_IR_TEFW_SHIFT (13U)
1664/*! TEFW - Tx event FIFO watermark reached.
1665 */
1666#define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)
1667#define CAN_IR_TEFF_MASK (0x4000U)
1668#define CAN_IR_TEFF_SHIFT (14U)
1669/*! TEFF - Tx event FIFO full.
1670 */
1671#define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)
1672#define CAN_IR_TEFL_MASK (0x8000U)
1673#define CAN_IR_TEFL_SHIFT (15U)
1674/*! TEFL - Tx event FIFO element lost.
1675 */
1676#define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)
1677#define CAN_IR_TSW_MASK (0x10000U)
1678#define CAN_IR_TSW_SHIFT (16U)
1679/*! TSW - Timestamp wraparound.
1680 */
1681#define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)
1682#define CAN_IR_MRAF_MASK (0x20000U)
1683#define CAN_IR_MRAF_SHIFT (17U)
1684/*! MRAF - Message RAM access failure.
1685 */
1686#define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)
1687#define CAN_IR_TOO_MASK (0x40000U)
1688#define CAN_IR_TOO_SHIFT (18U)
1689/*! TOO - Timeout occurred.
1690 */
1691#define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)
1692#define CAN_IR_DRX_MASK (0x80000U)
1693#define CAN_IR_DRX_SHIFT (19U)
1694/*! DRX - Message stored in dedicated Rx buffer.
1695 */
1696#define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)
1697#define CAN_IR_BEC_MASK (0x100000U)
1698#define CAN_IR_BEC_SHIFT (20U)
1699/*! BEC - Bit error corrected.
1700 */
1701#define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)
1702#define CAN_IR_BEU_MASK (0x200000U)
1703#define CAN_IR_BEU_SHIFT (21U)
1704/*! BEU - Bit error uncorrected.
1705 */
1706#define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)
1707#define CAN_IR_ELO_MASK (0x400000U)
1708#define CAN_IR_ELO_SHIFT (22U)
1709/*! ELO - Error logging overflow.
1710 */
1711#define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK)
1712#define CAN_IR_EP_MASK (0x800000U)
1713#define CAN_IR_EP_SHIFT (23U)
1714/*! EP - Error passive.
1715 */
1716#define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK)
1717#define CAN_IR_EW_MASK (0x1000000U)
1718#define CAN_IR_EW_SHIFT (24U)
1719/*! EW - Warning status.
1720 */
1721#define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK)
1722#define CAN_IR_BO_MASK (0x2000000U)
1723#define CAN_IR_BO_SHIFT (25U)
1724/*! BO - Bus_Off Status.
1725 */
1726#define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK)
1727#define CAN_IR_WDI_MASK (0x4000000U)
1728#define CAN_IR_WDI_SHIFT (26U)
1729/*! WDI - Watchdog interrupt.
1730 */
1731#define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK)
1732#define CAN_IR_PEA_MASK (0x8000000U)
1733#define CAN_IR_PEA_SHIFT (27U)
1734/*! PEA - Protocol error in arbitration phase.
1735 */
1736#define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK)
1737#define CAN_IR_PED_MASK (0x10000000U)
1738#define CAN_IR_PED_SHIFT (28U)
1739/*! PED - Protocol error in data phase.
1740 */
1741#define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK)
1742#define CAN_IR_ARA_MASK (0x20000000U)
1743#define CAN_IR_ARA_SHIFT (29U)
1744/*! ARA - Access to reserved address.
1745 */
1746#define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK)
1747/*! @} */
1748
1749/*! @name IE - Interrupt Enable */
1750/*! @{ */
1751#define CAN_IE_RF0NE_MASK (0x1U)
1752#define CAN_IE_RF0NE_SHIFT (0U)
1753/*! RF0NE - Rx FIFO 0 new message interrupt enable.
1754 */
1755#define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK)
1756#define CAN_IE_RF0WE_MASK (0x2U)
1757#define CAN_IE_RF0WE_SHIFT (1U)
1758/*! RF0WE - Rx FIFO 0 watermark reached interrupt enable.
1759 */
1760#define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK)
1761#define CAN_IE_RF0FE_MASK (0x4U)
1762#define CAN_IE_RF0FE_SHIFT (2U)
1763/*! RF0FE - Rx FIFO 0 full interrupt enable.
1764 */
1765#define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK)
1766#define CAN_IE_RF0LE_MASK (0x8U)
1767#define CAN_IE_RF0LE_SHIFT (3U)
1768/*! RF0LE - Rx FIFO 0 message lost interrupt enable.
1769 */
1770#define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK)
1771#define CAN_IE_RF1NE_MASK (0x10U)
1772#define CAN_IE_RF1NE_SHIFT (4U)
1773/*! RF1NE - Rx FIFO 1 new message interrupt enable.
1774 */
1775#define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK)
1776#define CAN_IE_RF1WE_MASK (0x20U)
1777#define CAN_IE_RF1WE_SHIFT (5U)
1778/*! RF1WE - Rx FIFO 1 watermark reached interrupt enable.
1779 */
1780#define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK)
1781#define CAN_IE_RF1FE_MASK (0x40U)
1782#define CAN_IE_RF1FE_SHIFT (6U)
1783/*! RF1FE - Rx FIFO 1 full interrupt enable.
1784 */
1785#define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK)
1786#define CAN_IE_RF1LE_MASK (0x80U)
1787#define CAN_IE_RF1LE_SHIFT (7U)
1788/*! RF1LE - Rx FIFO 1 message lost interrupt enable.
1789 */
1790#define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK)
1791#define CAN_IE_HPME_MASK (0x100U)
1792#define CAN_IE_HPME_SHIFT (8U)
1793/*! HPME - High priority message interrupt enable.
1794 */
1795#define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK)
1796#define CAN_IE_TCE_MASK (0x200U)
1797#define CAN_IE_TCE_SHIFT (9U)
1798/*! TCE - Transmission completed interrupt enable.
1799 */
1800#define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK)
1801#define CAN_IE_TCFE_MASK (0x400U)
1802#define CAN_IE_TCFE_SHIFT (10U)
1803/*! TCFE - Transmission cancellation finished interrupt enable.
1804 */
1805#define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK)
1806#define CAN_IE_TFEE_MASK (0x800U)
1807#define CAN_IE_TFEE_SHIFT (11U)
1808/*! TFEE - Tx FIFO empty interrupt enable.
1809 */
1810#define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK)
1811#define CAN_IE_TEFNE_MASK (0x1000U)
1812#define CAN_IE_TEFNE_SHIFT (12U)
1813/*! TEFNE - Tx event FIFO new entry interrupt enable.
1814 */
1815#define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK)
1816#define CAN_IE_TEFWE_MASK (0x2000U)
1817#define CAN_IE_TEFWE_SHIFT (13U)
1818/*! TEFWE - Tx event FIFO watermark reached interrupt enable.
1819 */
1820#define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK)
1821#define CAN_IE_TEFFE_MASK (0x4000U)
1822#define CAN_IE_TEFFE_SHIFT (14U)
1823/*! TEFFE - Tx event FIFO full interrupt enable.
1824 */
1825#define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK)
1826#define CAN_IE_TEFLE_MASK (0x8000U)
1827#define CAN_IE_TEFLE_SHIFT (15U)
1828/*! TEFLE - Tx event FIFO element lost interrupt enable.
1829 */
1830#define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK)
1831#define CAN_IE_TSWE_MASK (0x10000U)
1832#define CAN_IE_TSWE_SHIFT (16U)
1833/*! TSWE - Timestamp wraparound interrupt enable.
1834 */
1835#define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK)
1836#define CAN_IE_MRAFE_MASK (0x20000U)
1837#define CAN_IE_MRAFE_SHIFT (17U)
1838/*! MRAFE - Message RAM access failure interrupt enable.
1839 */
1840#define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK)
1841#define CAN_IE_TOOE_MASK (0x40000U)
1842#define CAN_IE_TOOE_SHIFT (18U)
1843/*! TOOE - Timeout occurred interrupt enable.
1844 */
1845#define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK)
1846#define CAN_IE_DRXE_MASK (0x80000U)
1847#define CAN_IE_DRXE_SHIFT (19U)
1848/*! DRXE - Message stored in dedicated Rx buffer interrupt enable.
1849 */
1850#define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK)
1851#define CAN_IE_BECE_MASK (0x100000U)
1852#define CAN_IE_BECE_SHIFT (20U)
1853/*! BECE - Bit error corrected interrupt enable.
1854 */
1855#define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK)
1856#define CAN_IE_BEUE_MASK (0x200000U)
1857#define CAN_IE_BEUE_SHIFT (21U)
1858/*! BEUE - Bit error uncorrected interrupt enable.
1859 */
1860#define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK)
1861#define CAN_IE_ELOE_MASK (0x400000U)
1862#define CAN_IE_ELOE_SHIFT (22U)
1863/*! ELOE - Error logging overflow interrupt enable.
1864 */
1865#define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK)
1866#define CAN_IE_EPE_MASK (0x800000U)
1867#define CAN_IE_EPE_SHIFT (23U)
1868/*! EPE - Error passive interrupt enable.
1869 */
1870#define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK)
1871#define CAN_IE_EWE_MASK (0x1000000U)
1872#define CAN_IE_EWE_SHIFT (24U)
1873/*! EWE - Warning status interrupt enable.
1874 */
1875#define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK)
1876#define CAN_IE_BOE_MASK (0x2000000U)
1877#define CAN_IE_BOE_SHIFT (25U)
1878/*! BOE - Bus_Off Status interrupt enable.
1879 */
1880#define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK)
1881#define CAN_IE_WDIE_MASK (0x4000000U)
1882#define CAN_IE_WDIE_SHIFT (26U)
1883/*! WDIE - Watchdog interrupt enable.
1884 */
1885#define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK)
1886#define CAN_IE_PEAE_MASK (0x8000000U)
1887#define CAN_IE_PEAE_SHIFT (27U)
1888/*! PEAE - Protocol error in arbitration phase interrupt enable.
1889 */
1890#define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK)
1891#define CAN_IE_PEDE_MASK (0x10000000U)
1892#define CAN_IE_PEDE_SHIFT (28U)
1893/*! PEDE - Protocol error in data phase interrupt enable.
1894 */
1895#define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK)
1896#define CAN_IE_ARAE_MASK (0x20000000U)
1897#define CAN_IE_ARAE_SHIFT (29U)
1898/*! ARAE - Access to reserved address interrupt enable.
1899 */
1900#define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK)
1901/*! @} */
1902
1903/*! @name ILS - Interrupt Line Select */
1904/*! @{ */
1905#define CAN_ILS_RF0NL_MASK (0x1U)
1906#define CAN_ILS_RF0NL_SHIFT (0U)
1907/*! RF0NL - Rx FIFO 0 new message interrupt line.
1908 */
1909#define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK)
1910#define CAN_ILS_RF0WL_MASK (0x2U)
1911#define CAN_ILS_RF0WL_SHIFT (1U)
1912/*! RF0WL - Rx FIFO 0 watermark reached interrupt line.
1913 */
1914#define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK)
1915#define CAN_ILS_RF0FL_MASK (0x4U)
1916#define CAN_ILS_RF0FL_SHIFT (2U)
1917/*! RF0FL - Rx FIFO 0 full interrupt line.
1918 */
1919#define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK)
1920#define CAN_ILS_RF0LL_MASK (0x8U)
1921#define CAN_ILS_RF0LL_SHIFT (3U)
1922/*! RF0LL - Rx FIFO 0 message lost interrupt line.
1923 */
1924#define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK)
1925#define CAN_ILS_RF1NL_MASK (0x10U)
1926#define CAN_ILS_RF1NL_SHIFT (4U)
1927/*! RF1NL - Rx FIFO 1 new message interrupt line.
1928 */
1929#define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK)
1930#define CAN_ILS_RF1WL_MASK (0x20U)
1931#define CAN_ILS_RF1WL_SHIFT (5U)
1932/*! RF1WL - Rx FIFO 1 watermark reached interrupt line.
1933 */
1934#define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK)
1935#define CAN_ILS_RF1FL_MASK (0x40U)
1936#define CAN_ILS_RF1FL_SHIFT (6U)
1937/*! RF1FL - Rx FIFO 1 full interrupt line.
1938 */
1939#define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK)
1940#define CAN_ILS_RF1LL_MASK (0x80U)
1941#define CAN_ILS_RF1LL_SHIFT (7U)
1942/*! RF1LL - Rx FIFO 1 message lost interrupt line.
1943 */
1944#define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK)
1945#define CAN_ILS_HPML_MASK (0x100U)
1946#define CAN_ILS_HPML_SHIFT (8U)
1947/*! HPML - High priority message interrupt line.
1948 */
1949#define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK)
1950#define CAN_ILS_TCL_MASK (0x200U)
1951#define CAN_ILS_TCL_SHIFT (9U)
1952/*! TCL - Transmission completed interrupt line.
1953 */
1954#define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK)
1955#define CAN_ILS_TCFL_MASK (0x400U)
1956#define CAN_ILS_TCFL_SHIFT (10U)
1957/*! TCFL - Transmission cancellation finished interrupt line.
1958 */
1959#define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK)
1960#define CAN_ILS_TFEL_MASK (0x800U)
1961#define CAN_ILS_TFEL_SHIFT (11U)
1962/*! TFEL - Tx FIFO empty interrupt line.
1963 */
1964#define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK)
1965#define CAN_ILS_TEFNL_MASK (0x1000U)
1966#define CAN_ILS_TEFNL_SHIFT (12U)
1967/*! TEFNL - Tx event FIFO new entry interrupt line.
1968 */
1969#define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK)
1970#define CAN_ILS_TEFWL_MASK (0x2000U)
1971#define CAN_ILS_TEFWL_SHIFT (13U)
1972/*! TEFWL - Tx event FIFO watermark reached interrupt line.
1973 */
1974#define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK)
1975#define CAN_ILS_TEFFL_MASK (0x4000U)
1976#define CAN_ILS_TEFFL_SHIFT (14U)
1977/*! TEFFL - Tx event FIFO full interrupt line.
1978 */
1979#define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK)
1980#define CAN_ILS_TEFLL_MASK (0x8000U)
1981#define CAN_ILS_TEFLL_SHIFT (15U)
1982/*! TEFLL - Tx event FIFO element lost interrupt line.
1983 */
1984#define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK)
1985#define CAN_ILS_TSWL_MASK (0x10000U)
1986#define CAN_ILS_TSWL_SHIFT (16U)
1987/*! TSWL - Timestamp wraparound interrupt line.
1988 */
1989#define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK)
1990#define CAN_ILS_MRAFL_MASK (0x20000U)
1991#define CAN_ILS_MRAFL_SHIFT (17U)
1992/*! MRAFL - Message RAM access failure interrupt line.
1993 */
1994#define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK)
1995#define CAN_ILS_TOOL_MASK (0x40000U)
1996#define CAN_ILS_TOOL_SHIFT (18U)
1997/*! TOOL - Timeout occurred interrupt line.
1998 */
1999#define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK)
2000#define CAN_ILS_DRXL_MASK (0x80000U)
2001#define CAN_ILS_DRXL_SHIFT (19U)
2002/*! DRXL - Message stored in dedicated Rx buffer interrupt line.
2003 */
2004#define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK)
2005#define CAN_ILS_BECL_MASK (0x100000U)
2006#define CAN_ILS_BECL_SHIFT (20U)
2007/*! BECL - Bit error corrected interrupt line.
2008 */
2009#define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK)
2010#define CAN_ILS_BEUL_MASK (0x200000U)
2011#define CAN_ILS_BEUL_SHIFT (21U)
2012/*! BEUL - Bit error uncorrected interrupt line.
2013 */
2014#define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK)
2015#define CAN_ILS_ELOL_MASK (0x400000U)
2016#define CAN_ILS_ELOL_SHIFT (22U)
2017/*! ELOL - Error logging overflow interrupt line.
2018 */
2019#define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK)
2020#define CAN_ILS_EPL_MASK (0x800000U)
2021#define CAN_ILS_EPL_SHIFT (23U)
2022/*! EPL - Error passive interrupt line.
2023 */
2024#define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK)
2025#define CAN_ILS_EWL_MASK (0x1000000U)
2026#define CAN_ILS_EWL_SHIFT (24U)
2027/*! EWL - Warning status interrupt line.
2028 */
2029#define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK)
2030#define CAN_ILS_BOL_MASK (0x2000000U)
2031#define CAN_ILS_BOL_SHIFT (25U)
2032/*! BOL - Bus_Off Status interrupt line.
2033 */
2034#define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK)
2035#define CAN_ILS_WDIL_MASK (0x4000000U)
2036#define CAN_ILS_WDIL_SHIFT (26U)
2037/*! WDIL - Watchdog interrupt line.
2038 */
2039#define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK)
2040#define CAN_ILS_PEAL_MASK (0x8000000U)
2041#define CAN_ILS_PEAL_SHIFT (27U)
2042/*! PEAL - Protocol error in arbitration phase interrupt line.
2043 */
2044#define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK)
2045#define CAN_ILS_PEDL_MASK (0x10000000U)
2046#define CAN_ILS_PEDL_SHIFT (28U)
2047/*! PEDL - Protocol error in data phase interrupt line.
2048 */
2049#define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK)
2050#define CAN_ILS_ARAL_MASK (0x20000000U)
2051#define CAN_ILS_ARAL_SHIFT (29U)
2052/*! ARAL - Access to reserved address interrupt line.
2053 */
2054#define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK)
2055/*! @} */
2056
2057/*! @name ILE - Interrupt Line Enable */
2058/*! @{ */
2059#define CAN_ILE_EINT0_MASK (0x1U)
2060#define CAN_ILE_EINT0_SHIFT (0U)
2061/*! EINT0 - Enable interrupt line 0.
2062 */
2063#define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK)
2064#define CAN_ILE_EINT1_MASK (0x2U)
2065#define CAN_ILE_EINT1_SHIFT (1U)
2066/*! EINT1 - Enable interrupt line 1.
2067 */
2068#define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK)
2069/*! @} */
2070
2071/*! @name GFC - Global Filter Configuration */
2072/*! @{ */
2073#define CAN_GFC_RRFE_MASK (0x1U)
2074#define CAN_GFC_RRFE_SHIFT (0U)
2075/*! RRFE - Reject remote frames extended.
2076 */
2077#define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK)
2078#define CAN_GFC_RRFS_MASK (0x2U)
2079#define CAN_GFC_RRFS_SHIFT (1U)
2080/*! RRFS - Reject remote frames standard.
2081 */
2082#define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK)
2083#define CAN_GFC_ANFE_MASK (0xCU)
2084#define CAN_GFC_ANFE_SHIFT (2U)
2085/*! ANFE - Accept non-matching frames extended.
2086 */
2087#define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK)
2088#define CAN_GFC_ANFS_MASK (0x30U)
2089#define CAN_GFC_ANFS_SHIFT (4U)
2090/*! ANFS - Accept non-matching frames standard.
2091 */
2092#define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK)
2093/*! @} */
2094
2095/*! @name SIDFC - Standard ID Filter Configuration */
2096/*! @{ */
2097#define CAN_SIDFC_FLSSA_MASK (0xFFFCU)
2098#define CAN_SIDFC_FLSSA_SHIFT (2U)
2099/*! FLSSA - Filter list standard start address.
2100 */
2101#define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK)
2102#define CAN_SIDFC_LSS_MASK (0xFF0000U)
2103#define CAN_SIDFC_LSS_SHIFT (16U)
2104/*! LSS - List size standard 0 = No standard message ID filter.
2105 */
2106#define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK)
2107/*! @} */
2108
2109/*! @name XIDFC - Extended ID Filter Configuration */
2110/*! @{ */
2111#define CAN_XIDFC_FLESA_MASK (0xFFFCU)
2112#define CAN_XIDFC_FLESA_SHIFT (2U)
2113/*! FLESA - Filter list extended start address.
2114 */
2115#define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK)
2116#define CAN_XIDFC_LSE_MASK (0xFF0000U)
2117#define CAN_XIDFC_LSE_SHIFT (16U)
2118/*! LSE - List size extended 0 = No extended message ID filter.
2119 */
2120#define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK)
2121/*! @} */
2122
2123/*! @name XIDAM - Extended ID AND Mask */
2124/*! @{ */
2125#define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU)
2126#define CAN_XIDAM_EIDM_SHIFT (0U)
2127/*! EIDM - Extended ID mask.
2128 */
2129#define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK)
2130/*! @} */
2131
2132/*! @name HPMS - High Priority Message Status */
2133/*! @{ */
2134#define CAN_HPMS_BIDX_MASK (0x3FU)
2135#define CAN_HPMS_BIDX_SHIFT (0U)
2136/*! BIDX - Buffer index.
2137 */
2138#define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK)
2139#define CAN_HPMS_MSI_MASK (0xC0U)
2140#define CAN_HPMS_MSI_SHIFT (6U)
2141/*! MSI - Message storage indicator.
2142 */
2143#define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK)
2144#define CAN_HPMS_FIDX_MASK (0x7F00U)
2145#define CAN_HPMS_FIDX_SHIFT (8U)
2146/*! FIDX - Filter index.
2147 */
2148#define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK)
2149#define CAN_HPMS_FLST_MASK (0x8000U)
2150#define CAN_HPMS_FLST_SHIFT (15U)
2151/*! FLST - Filter list.
2152 */
2153#define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK)
2154/*! @} */
2155
2156/*! @name NDAT1 - New Data 1 */
2157/*! @{ */
2158#define CAN_NDAT1_ND_MASK (0xFFFFFFFFU)
2159#define CAN_NDAT1_ND_SHIFT (0U)
2160/*! ND - New Data.
2161 */
2162#define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK)
2163/*! @} */
2164
2165/*! @name NDAT2 - New Data 2 */
2166/*! @{ */
2167#define CAN_NDAT2_ND_MASK (0xFFFFFFFFU)
2168#define CAN_NDAT2_ND_SHIFT (0U)
2169/*! ND - New Data.
2170 */
2171#define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK)
2172/*! @} */
2173
2174/*! @name RXF0C - Rx FIFO 0 Configuration */
2175/*! @{ */
2176#define CAN_RXF0C_F0SA_MASK (0xFFFCU)
2177#define CAN_RXF0C_F0SA_SHIFT (2U)
2178/*! F0SA - Rx FIFO 0 start address.
2179 */
2180#define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK)
2181#define CAN_RXF0C_F0S_MASK (0x7F0000U)
2182#define CAN_RXF0C_F0S_SHIFT (16U)
2183/*! F0S - Rx FIFO 0 size.
2184 */
2185#define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK)
2186#define CAN_RXF0C_F0WM_MASK (0x7F000000U)
2187#define CAN_RXF0C_F0WM_SHIFT (24U)
2188/*! F0WM - Rx FIFO 0 watermark 0 = Watermark interrupt disabled.
2189 */
2190#define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK)
2191#define CAN_RXF0C_F0OM_MASK (0x80000000U)
2192#define CAN_RXF0C_F0OM_SHIFT (31U)
2193/*! F0OM - FIFO 0 operation mode.
2194 */
2195#define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK)
2196/*! @} */
2197
2198/*! @name RXF0S - Rx FIFO 0 Status */
2199/*! @{ */
2200#define CAN_RXF0S_F0FL_MASK (0x7FU)
2201#define CAN_RXF0S_F0FL_SHIFT (0U)
2202/*! F0FL - Rx FIFO 0 fill level.
2203 */
2204#define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK)
2205#define CAN_RXF0S_F0GI_MASK (0x3F00U)
2206#define CAN_RXF0S_F0GI_SHIFT (8U)
2207/*! F0GI - Rx FIFO 0 get index.
2208 */
2209#define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK)
2210#define CAN_RXF0S_F0PI_MASK (0x3F0000U)
2211#define CAN_RXF0S_F0PI_SHIFT (16U)
2212/*! F0PI - Rx FIFO 0 put index.
2213 */
2214#define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK)
2215#define CAN_RXF0S_F0F_MASK (0x1000000U)
2216#define CAN_RXF0S_F0F_SHIFT (24U)
2217/*! F0F - Rx FIFO 0 full.
2218 */
2219#define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK)
2220#define CAN_RXF0S_RF0L_MASK (0x2000000U)
2221#define CAN_RXF0S_RF0L_SHIFT (25U)
2222/*! RF0L - Rx FIFO 0 message lost.
2223 */
2224#define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK)
2225/*! @} */
2226
2227/*! @name RXF0A - Rx FIFO 0 Acknowledge */
2228/*! @{ */
2229#define CAN_RXF0A_F0AI_MASK (0x3FU)
2230#define CAN_RXF0A_F0AI_SHIFT (0U)
2231/*! F0AI - Rx FIFO 0 acknowledge index.
2232 */
2233#define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK)
2234/*! @} */
2235
2236/*! @name RXBC - Rx Buffer Configuration */
2237/*! @{ */
2238#define CAN_RXBC_RBSA_MASK (0xFFFCU)
2239#define CAN_RXBC_RBSA_SHIFT (2U)
2240/*! RBSA - Rx buffer start address.
2241 */
2242#define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK)
2243/*! @} */
2244
2245/*! @name RXF1C - Rx FIFO 1 Configuration */
2246/*! @{ */
2247#define CAN_RXF1C_F1SA_MASK (0xFFFCU)
2248#define CAN_RXF1C_F1SA_SHIFT (2U)
2249/*! F1SA - Rx FIFO 1 start address.
2250 */
2251#define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK)
2252#define CAN_RXF1C_F1S_MASK (0x7F0000U)
2253#define CAN_RXF1C_F1S_SHIFT (16U)
2254/*! F1S - Rx FIFO 1 size 0 = No Rx FIFO 1.
2255 */
2256#define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK)
2257#define CAN_RXF1C_F1WM_MASK (0x7F000000U)
2258#define CAN_RXF1C_F1WM_SHIFT (24U)
2259/*! F1WM - Rx FIFO 1 watermark 0 = Watermark interrupt disabled.
2260 */
2261#define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK)
2262#define CAN_RXF1C_F1OM_MASK (0x80000000U)
2263#define CAN_RXF1C_F1OM_SHIFT (31U)
2264/*! F1OM - FIFO 1 operation mode.
2265 */
2266#define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK)
2267/*! @} */
2268
2269/*! @name RXF1S - Rx FIFO 1 Status */
2270/*! @{ */
2271#define CAN_RXF1S_F1FL_MASK (0x7FU)
2272#define CAN_RXF1S_F1FL_SHIFT (0U)
2273/*! F1FL - Rx FIFO 1 fill level.
2274 */
2275#define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK)
2276#define CAN_RXF1S_F1GI_MASK (0x3F00U)
2277#define CAN_RXF1S_F1GI_SHIFT (8U)
2278/*! F1GI - Rx FIFO 1 get index.
2279 */
2280#define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK)
2281#define CAN_RXF1S_F1PI_MASK (0x3F0000U)
2282#define CAN_RXF1S_F1PI_SHIFT (16U)
2283/*! F1PI - Rx FIFO 1 put index.
2284 */
2285#define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK)
2286#define CAN_RXF1S_F1F_MASK (0x1000000U)
2287#define CAN_RXF1S_F1F_SHIFT (24U)
2288/*! F1F - Rx FIFO 1 full.
2289 */
2290#define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK)
2291#define CAN_RXF1S_RF1L_MASK (0x2000000U)
2292#define CAN_RXF1S_RF1L_SHIFT (25U)
2293/*! RF1L - Rx FIFO 1 message lost.
2294 */
2295#define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK)
2296/*! @} */
2297
2298/*! @name RXF1A - Rx FIFO 1 Acknowledge */
2299/*! @{ */
2300#define CAN_RXF1A_F1AI_MASK (0x3FU)
2301#define CAN_RXF1A_F1AI_SHIFT (0U)
2302/*! F1AI - Rx FIFO 1 acknowledge index.
2303 */
2304#define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK)
2305/*! @} */
2306
2307/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */
2308/*! @{ */
2309#define CAN_RXESC_F0DS_MASK (0x7U)
2310#define CAN_RXESC_F0DS_SHIFT (0U)
2311/*! F0DS - Rx FIFO 0 data field size.
2312 */
2313#define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK)
2314#define CAN_RXESC_F1DS_MASK (0x70U)
2315#define CAN_RXESC_F1DS_SHIFT (4U)
2316/*! F1DS - Rx FIFO 1 data field size.
2317 */
2318#define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK)
2319#define CAN_RXESC_RBDS_MASK (0x700U)
2320#define CAN_RXESC_RBDS_SHIFT (8U)
2321/*! RBDS - .
2322 */
2323#define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK)
2324/*! @} */
2325
2326/*! @name TXBC - Tx Buffer Configuration */
2327/*! @{ */
2328#define CAN_TXBC_TBSA_MASK (0xFFFCU)
2329#define CAN_TXBC_TBSA_SHIFT (2U)
2330/*! TBSA - Tx buffers start address.
2331 */
2332#define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK)
2333#define CAN_TXBC_NDTB_MASK (0x3F0000U)
2334#define CAN_TXBC_NDTB_SHIFT (16U)
2335/*! NDTB - Number of dedicated transmit buffers 0 = No dedicated Tx buffers.
2336 */
2337#define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK)
2338#define CAN_TXBC_TFQS_MASK (0x3F000000U)
2339#define CAN_TXBC_TFQS_SHIFT (24U)
2340/*! TFQS - Transmit FIFO/queue size 0 = No tx FIFO/Queue.
2341 */
2342#define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK)
2343#define CAN_TXBC_TFQM_MASK (0x40000000U)
2344#define CAN_TXBC_TFQM_SHIFT (30U)
2345/*! TFQM - Tx FIFO/queue mode.
2346 */
2347#define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK)
2348/*! @} */
2349
2350/*! @name TXFQS - Tx FIFO/Queue Status */
2351/*! @{ */
2352#define CAN_TXFQS_TFGI_MASK (0x1F00U)
2353#define CAN_TXFQS_TFGI_SHIFT (8U)
2354/*! TFGI - Tx FIFO get index.
2355 */
2356#define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK)
2357#define CAN_TXFQS_TFQPI_MASK (0x1F0000U)
2358#define CAN_TXFQS_TFQPI_SHIFT (16U)
2359/*! TFQPI - Tx FIFO/queue put index.
2360 */
2361#define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK)
2362#define CAN_TXFQS_TFQF_MASK (0x200000U)
2363#define CAN_TXFQS_TFQF_SHIFT (21U)
2364/*! TFQF - Tx FIFO/queue full.
2365 */
2366#define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK)
2367/*! @} */
2368
2369/*! @name TXESC - Tx Buffer Element Size Configuration */
2370/*! @{ */
2371#define CAN_TXESC_TBDS_MASK (0x7U)
2372#define CAN_TXESC_TBDS_SHIFT (0U)
2373/*! TBDS - Tx buffer data field size.
2374 */
2375#define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK)
2376/*! @} */
2377
2378/*! @name TXBRP - Tx Buffer Request Pending */
2379/*! @{ */
2380#define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU)
2381#define CAN_TXBRP_TRP_SHIFT (0U)
2382/*! TRP - Transmission request pending.
2383 */
2384#define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK)
2385/*! @} */
2386
2387/*! @name TXBAR - Tx Buffer Add Request */
2388/*! @{ */
2389#define CAN_TXBAR_AR_MASK (0xFFFFFFFFU)
2390#define CAN_TXBAR_AR_SHIFT (0U)
2391/*! AR - Add request.
2392 */
2393#define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK)
2394/*! @} */
2395
2396/*! @name TXBCR - Tx Buffer Cancellation Request */
2397/*! @{ */
2398#define CAN_TXBCR_CR_MASK (0xFFFFFFFFU)
2399#define CAN_TXBCR_CR_SHIFT (0U)
2400/*! CR - Cancellation request.
2401 */
2402#define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK)
2403/*! @} */
2404
2405/*! @name TXBTO - Tx Buffer Transmission Occurred */
2406/*! @{ */
2407#define CAN_TXBTO_TO_MASK (0xFFFFFFFFU)
2408#define CAN_TXBTO_TO_SHIFT (0U)
2409/*! TO - Transmission occurred.
2410 */
2411#define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK)
2412/*! @} */
2413
2414/*! @name TXBCF - Tx Buffer Cancellation Finished */
2415/*! @{ */
2416#define CAN_TXBCF_TO_MASK (0xFFFFFFFFU)
2417#define CAN_TXBCF_TO_SHIFT (0U)
2418/*! TO - Cancellation finished.
2419 */
2420#define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK)
2421/*! @} */
2422
2423/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */
2424/*! @{ */
2425#define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU)
2426#define CAN_TXBTIE_TIE_SHIFT (0U)
2427/*! TIE - Transmission interrupt enable.
2428 */
2429#define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK)
2430/*! @} */
2431
2432/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */
2433/*! @{ */
2434#define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU)
2435#define CAN_TXBCIE_CFIE_SHIFT (0U)
2436/*! CFIE - Cancellation finished interrupt enable.
2437 */
2438#define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK)
2439/*! @} */
2440
2441/*! @name TXEFC - Tx Event FIFO Configuration */
2442/*! @{ */
2443#define CAN_TXEFC_EFSA_MASK (0xFFFCU)
2444#define CAN_TXEFC_EFSA_SHIFT (2U)
2445/*! EFSA - Event FIFO start address.
2446 */
2447#define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK)
2448#define CAN_TXEFC_EFS_MASK (0x3F0000U)
2449#define CAN_TXEFC_EFS_SHIFT (16U)
2450/*! EFS - Event FIFO size 0 = Tx event FIFO disabled.
2451 */
2452#define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK)
2453#define CAN_TXEFC_EFWM_MASK (0x3F000000U)
2454#define CAN_TXEFC_EFWM_SHIFT (24U)
2455/*! EFWM - Event FIFO watermark 0 = Watermark interrupt disabled.
2456 */
2457#define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK)
2458/*! @} */
2459
2460/*! @name TXEFS - Tx Event FIFO Status */
2461/*! @{ */
2462#define CAN_TXEFS_EFFL_MASK (0x3FU)
2463#define CAN_TXEFS_EFFL_SHIFT (0U)
2464/*! EFFL - Event FIFO fill level.
2465 */
2466#define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK)
2467#define CAN_TXEFS_EFGI_MASK (0x1F00U)
2468#define CAN_TXEFS_EFGI_SHIFT (8U)
2469/*! EFGI - Event FIFO get index.
2470 */
2471#define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK)
2472#define CAN_TXEFS_EFPI_MASK (0x3F0000U)
2473#define CAN_TXEFS_EFPI_SHIFT (16U)
2474/*! EFPI - Event FIFO put index.
2475 */
2476#define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK)
2477#define CAN_TXEFS_EFF_MASK (0x1000000U)
2478#define CAN_TXEFS_EFF_SHIFT (24U)
2479/*! EFF - Event FIFO full.
2480 */
2481#define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK)
2482#define CAN_TXEFS_TEFL_MASK (0x2000000U)
2483#define CAN_TXEFS_TEFL_SHIFT (25U)
2484/*! TEFL - Tx event FIFO element lost.
2485 */
2486#define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK)
2487/*! @} */
2488
2489/*! @name TXEFA - Tx Event FIFO Acknowledge */
2490/*! @{ */
2491#define CAN_TXEFA_EFAI_MASK (0x1FU)
2492#define CAN_TXEFA_EFAI_SHIFT (0U)
2493/*! EFAI - Event FIFO acknowledge index.
2494 */
2495#define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK)
2496/*! @} */
2497
2498/*! @name MRBA - CAN Message RAM Base Address */
2499/*! @{ */
2500#define CAN_MRBA_BA_MASK (0xFFFF0000U)
2501#define CAN_MRBA_BA_SHIFT (16U)
2502/*! BA - Base address for the message RAM in the chip memory map.
2503 */
2504#define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK)
2505/*! @} */
2506
2507/*! @name ETSCC - External Timestamp Counter Configuration */
2508/*! @{ */
2509#define CAN_ETSCC_ETCP_MASK (0x7FFU)
2510#define CAN_ETSCC_ETCP_SHIFT (0U)
2511/*! ETCP - External timestamp prescaler value.
2512 */
2513#define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK)
2514#define CAN_ETSCC_ETCE_MASK (0x80000000U)
2515#define CAN_ETSCC_ETCE_SHIFT (31U)
2516/*! ETCE - External timestamp counter enable.
2517 */
2518#define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK)
2519/*! @} */
2520
2521/*! @name ETSCV - External Timestamp Counter Value */
2522/*! @{ */
2523#define CAN_ETSCV_ETSC_MASK (0xFFFFU)
2524#define CAN_ETSCV_ETSC_SHIFT (0U)
2525/*! ETSC - External timestamp counter.
2526 */
2527#define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK)
2528/*! @} */
2529
2530
2531/*!
2532 * @}
2533 */ /* end of group CAN_Register_Masks */
2534
2535
2536/* CAN - Peripheral instance base addresses */
2537/** Peripheral CAN0 base address */
2538#define CAN0_BASE (0x4009D000u)
2539/** Peripheral CAN0 base pointer */
2540#define CAN0 ((CAN_Type *)CAN0_BASE)
2541/** Peripheral CAN1 base address */
2542#define CAN1_BASE (0x4009E000u)
2543/** Peripheral CAN1 base pointer */
2544#define CAN1 ((CAN_Type *)CAN1_BASE)
2545/** Array initializer of CAN peripheral base addresses */
2546#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
2547/** Array initializer of CAN peripheral base pointers */
2548#define CAN_BASE_PTRS { CAN0, CAN1 }
2549/** Interrupt vectors for the CAN peripheral type */
2550#define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } }
2551
2552/*!
2553 * @}
2554 */ /* end of group CAN_Peripheral_Access_Layer */
2555
2556
2557/* ----------------------------------------------------------------------------
2558 -- CRC Peripheral Access Layer
2559 ---------------------------------------------------------------------------- */
2560
2561/*!
2562 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
2563 * @{
2564 */
2565
2566/** CRC - Register Layout Typedef */
2567typedef struct {
2568 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
2569 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
2570 union { /* offset: 0x8 */
2571 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
2572 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
2573 };
2574} CRC_Type;
2575
2576/* ----------------------------------------------------------------------------
2577 -- CRC Register Masks
2578 ---------------------------------------------------------------------------- */
2579
2580/*!
2581 * @addtogroup CRC_Register_Masks CRC Register Masks
2582 * @{
2583 */
2584
2585/*! @name MODE - CRC mode register */
2586/*! @{ */
2587#define CRC_MODE_CRC_POLY_MASK (0x3U)
2588#define CRC_MODE_CRC_POLY_SHIFT (0U)
2589/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
2590 */
2591#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
2592#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
2593#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
2594/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
2595 */
2596#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
2597#define CRC_MODE_CMPL_WR_MASK (0x8U)
2598#define CRC_MODE_CMPL_WR_SHIFT (3U)
2599/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
2600 */
2601#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
2602#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
2603#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
2604/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
2605 */
2606#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
2607#define CRC_MODE_CMPL_SUM_MASK (0x20U)
2608#define CRC_MODE_CMPL_SUM_SHIFT (5U)
2609/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
2610 */
2611#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
2612/*! @} */
2613
2614/*! @name SEED - CRC seed register */
2615/*! @{ */
2616#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
2617#define CRC_SEED_CRC_SEED_SHIFT (0U)
2618/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
2619 * selected bit order and 1's complement pre-processes. A write access to this register will
2620 * overrule the CRC calculation in progresses.
2621 */
2622#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
2623/*! @} */
2624
2625/*! @name SUM - CRC checksum register */
2626/*! @{ */
2627#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
2628#define CRC_SUM_CRC_SUM_SHIFT (0U)
2629/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
2630 */
2631#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
2632/*! @} */
2633
2634/*! @name WR_DATA - CRC data register */
2635/*! @{ */
2636#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
2637#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
2638/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
2639 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
2640 * accept back-to-back transactions.
2641 */
2642#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
2643/*! @} */
2644
2645
2646/*!
2647 * @}
2648 */ /* end of group CRC_Register_Masks */
2649
2650
2651/* CRC - Peripheral instance base addresses */
2652/** Peripheral CRC_ENGINE base address */
2653#define CRC_ENGINE_BASE (0x40095000u)
2654/** Peripheral CRC_ENGINE base pointer */
2655#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
2656/** Array initializer of CRC peripheral base addresses */
2657#define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
2658/** Array initializer of CRC peripheral base pointers */
2659#define CRC_BASE_PTRS { CRC_ENGINE }
2660
2661/*!
2662 * @}
2663 */ /* end of group CRC_Peripheral_Access_Layer */
2664
2665
2666/* ----------------------------------------------------------------------------
2667 -- CTIMER Peripheral Access Layer
2668 ---------------------------------------------------------------------------- */
2669
2670/*!
2671 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
2672 * @{
2673 */
2674
2675/** CTIMER - Register Layout Typedef */
2676typedef struct {
2677 __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
2678 __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
2679 __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */
2680 __IO uint32_t PR; /**< Prescale Register, offset: 0xC */
2681 __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */
2682 __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */
2683 __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
2684 __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
2685 __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
2686 __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
2687 uint8_t RESERVED_0[48];
2688 __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
2689 __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
2690 __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
2691} CTIMER_Type;
2692
2693/* ----------------------------------------------------------------------------
2694 -- CTIMER Register Masks
2695 ---------------------------------------------------------------------------- */
2696
2697/*!
2698 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
2699 * @{
2700 */
2701
2702/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
2703/*! @{ */
2704#define CTIMER_IR_MR0INT_MASK (0x1U)
2705#define CTIMER_IR_MR0INT_SHIFT (0U)
2706/*! MR0INT - Interrupt flag for match channel 0.
2707 */
2708#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
2709#define CTIMER_IR_MR1INT_MASK (0x2U)
2710#define CTIMER_IR_MR1INT_SHIFT (1U)
2711/*! MR1INT - Interrupt flag for match channel 1.
2712 */
2713#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
2714#define CTIMER_IR_MR2INT_MASK (0x4U)
2715#define CTIMER_IR_MR2INT_SHIFT (2U)
2716/*! MR2INT - Interrupt flag for match channel 2.
2717 */
2718#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
2719#define CTIMER_IR_MR3INT_MASK (0x8U)
2720#define CTIMER_IR_MR3INT_SHIFT (3U)
2721/*! MR3INT - Interrupt flag for match channel 3.
2722 */
2723#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
2724#define CTIMER_IR_CR0INT_MASK (0x10U)
2725#define CTIMER_IR_CR0INT_SHIFT (4U)
2726/*! CR0INT - Interrupt flag for capture channel 0 event.
2727 */
2728#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
2729#define CTIMER_IR_CR1INT_MASK (0x20U)
2730#define CTIMER_IR_CR1INT_SHIFT (5U)
2731/*! CR1INT - Interrupt flag for capture channel 1 event.
2732 */
2733#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
2734#define CTIMER_IR_CR2INT_MASK (0x40U)
2735#define CTIMER_IR_CR2INT_SHIFT (6U)
2736/*! CR2INT - Interrupt flag for capture channel 2 event.
2737 */
2738#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
2739#define CTIMER_IR_CR3INT_MASK (0x80U)
2740#define CTIMER_IR_CR3INT_SHIFT (7U)
2741/*! CR3INT - Interrupt flag for capture channel 3 event.
2742 */
2743#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
2744/*! @} */
2745
2746/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
2747/*! @{ */
2748#define CTIMER_TCR_CEN_MASK (0x1U)
2749#define CTIMER_TCR_CEN_SHIFT (0U)
2750/*! CEN - Counter enable.
2751 * 0b0..Disabled.The counters are disabled.
2752 * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
2753 */
2754#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
2755#define CTIMER_TCR_CRST_MASK (0x2U)
2756#define CTIMER_TCR_CRST_SHIFT (1U)
2757/*! CRST - Counter reset.
2758 * 0b0..Disabled. Do nothing.
2759 * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
2760 * the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
2761 */
2762#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
2763/*! @} */
2764
2765/*! @name TC - Timer Counter */
2766/*! @{ */
2767#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
2768#define CTIMER_TC_TCVAL_SHIFT (0U)
2769/*! TCVAL - Timer counter value.
2770 */
2771#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
2772/*! @} */
2773
2774/*! @name PR - Prescale Register */
2775/*! @{ */
2776#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
2777#define CTIMER_PR_PRVAL_SHIFT (0U)
2778/*! PRVAL - Prescale counter value.
2779 */
2780#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
2781/*! @} */
2782
2783/*! @name PC - Prescale Counter */
2784/*! @{ */
2785#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
2786#define CTIMER_PC_PCVAL_SHIFT (0U)
2787/*! PCVAL - Prescale counter value.
2788 */
2789#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
2790/*! @} */
2791
2792/*! @name MCR - Match Control Register */
2793/*! @{ */
2794#define CTIMER_MCR_MR0I_MASK (0x1U)
2795#define CTIMER_MCR_MR0I_SHIFT (0U)
2796/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
2797 */
2798#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
2799#define CTIMER_MCR_MR0R_MASK (0x2U)
2800#define CTIMER_MCR_MR0R_SHIFT (1U)
2801/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it.
2802 */
2803#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
2804#define CTIMER_MCR_MR0S_MASK (0x4U)
2805#define CTIMER_MCR_MR0S_SHIFT (2U)
2806/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
2807 */
2808#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
2809#define CTIMER_MCR_MR1I_MASK (0x8U)
2810#define CTIMER_MCR_MR1I_SHIFT (3U)
2811/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
2812 */
2813#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
2814#define CTIMER_MCR_MR1R_MASK (0x10U)
2815#define CTIMER_MCR_MR1R_SHIFT (4U)
2816/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it.
2817 */
2818#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
2819#define CTIMER_MCR_MR1S_MASK (0x20U)
2820#define CTIMER_MCR_MR1S_SHIFT (5U)
2821/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
2822 */
2823#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
2824#define CTIMER_MCR_MR2I_MASK (0x40U)
2825#define CTIMER_MCR_MR2I_SHIFT (6U)
2826/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
2827 */
2828#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
2829#define CTIMER_MCR_MR2R_MASK (0x80U)
2830#define CTIMER_MCR_MR2R_SHIFT (7U)
2831/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it.
2832 */
2833#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
2834#define CTIMER_MCR_MR2S_MASK (0x100U)
2835#define CTIMER_MCR_MR2S_SHIFT (8U)
2836/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
2837 */
2838#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
2839#define CTIMER_MCR_MR3I_MASK (0x200U)
2840#define CTIMER_MCR_MR3I_SHIFT (9U)
2841/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
2842 */
2843#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
2844#define CTIMER_MCR_MR3R_MASK (0x400U)
2845#define CTIMER_MCR_MR3R_SHIFT (10U)
2846/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it.
2847 */
2848#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
2849#define CTIMER_MCR_MR3S_MASK (0x800U)
2850#define CTIMER_MCR_MR3S_SHIFT (11U)
2851/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
2852 */
2853#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
2854#define CTIMER_MCR_MR0RL_MASK (0x1000000U)
2855#define CTIMER_MCR_MR0RL_SHIFT (24U)
2856/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
2857 * (either via a match event or a write to bit 1 of the TCR).
2858 */
2859#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
2860#define CTIMER_MCR_MR1RL_MASK (0x2000000U)
2861#define CTIMER_MCR_MR1RL_SHIFT (25U)
2862/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
2863 * (either via a match event or a write to bit 1 of the TCR).
2864 */
2865#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
2866#define CTIMER_MCR_MR2RL_MASK (0x4000000U)
2867#define CTIMER_MCR_MR2RL_SHIFT (26U)
2868/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
2869 * (either via a match event or a write to bit 1 of the TCR).
2870 */
2871#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
2872#define CTIMER_MCR_MR3RL_MASK (0x8000000U)
2873#define CTIMER_MCR_MR3RL_SHIFT (27U)
2874/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
2875 * (either via a match event or a write to bit 1 of the TCR).
2876 */
2877#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
2878/*! @} */
2879
2880/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
2881/*! @{ */
2882#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
2883#define CTIMER_MR_MATCH_SHIFT (0U)
2884/*! MATCH - Timer counter match value.
2885 */
2886#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
2887/*! @} */
2888
2889/* The count of CTIMER_MR */
2890#define CTIMER_MR_COUNT (4U)
2891
2892/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
2893/*! @{ */
2894#define CTIMER_CCR_CAP0RE_MASK (0x1U)
2895#define CTIMER_CCR_CAP0RE_SHIFT (0U)
2896/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
2897 * the contents of TC. 0 = disabled. 1 = enabled.
2898 */
2899#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
2900#define CTIMER_CCR_CAP0FE_MASK (0x2U)
2901#define CTIMER_CCR_CAP0FE_SHIFT (1U)
2902/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
2903 * the contents of TC. 0 = disabled. 1 = enabled.
2904 */
2905#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
2906#define CTIMER_CCR_CAP0I_MASK (0x4U)
2907#define CTIMER_CCR_CAP0I_SHIFT (2U)
2908/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
2909 */
2910#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
2911#define CTIMER_CCR_CAP1RE_MASK (0x8U)
2912#define CTIMER_CCR_CAP1RE_SHIFT (3U)
2913/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
2914 * the contents of TC. 0 = disabled. 1 = enabled.
2915 */
2916#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
2917#define CTIMER_CCR_CAP1FE_MASK (0x10U)
2918#define CTIMER_CCR_CAP1FE_SHIFT (4U)
2919/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
2920 * the contents of TC. 0 = disabled. 1 = enabled.
2921 */
2922#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
2923#define CTIMER_CCR_CAP1I_MASK (0x20U)
2924#define CTIMER_CCR_CAP1I_SHIFT (5U)
2925/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
2926 */
2927#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
2928#define CTIMER_CCR_CAP2RE_MASK (0x40U)
2929#define CTIMER_CCR_CAP2RE_SHIFT (6U)
2930/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
2931 * the contents of TC. 0 = disabled. 1 = enabled.
2932 */
2933#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
2934#define CTIMER_CCR_CAP2FE_MASK (0x80U)
2935#define CTIMER_CCR_CAP2FE_SHIFT (7U)
2936/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
2937 * the contents of TC. 0 = disabled. 1 = enabled.
2938 */
2939#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
2940#define CTIMER_CCR_CAP2I_MASK (0x100U)
2941#define CTIMER_CCR_CAP2I_SHIFT (8U)
2942/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
2943 */
2944#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
2945#define CTIMER_CCR_CAP3RE_MASK (0x200U)
2946#define CTIMER_CCR_CAP3RE_SHIFT (9U)
2947/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with
2948 * the contents of TC. 0 = disabled. 1 = enabled.
2949 */
2950#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
2951#define CTIMER_CCR_CAP3FE_MASK (0x400U)
2952#define CTIMER_CCR_CAP3FE_SHIFT (10U)
2953/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with
2954 * the contents of TC. 0 = disabled. 1 = enabled.
2955 */
2956#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
2957#define CTIMER_CCR_CAP3I_MASK (0x800U)
2958#define CTIMER_CCR_CAP3I_SHIFT (11U)
2959/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
2960 */
2961#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
2962/*! @} */
2963
2964/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
2965/*! @{ */
2966#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
2967#define CTIMER_CR_CAP_SHIFT (0U)
2968/*! CAP - Timer counter capture value.
2969 */
2970#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
2971/*! @} */
2972
2973/* The count of CTIMER_CR */
2974#define CTIMER_CR_COUNT (4U)
2975
2976/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
2977/*! @{ */
2978#define CTIMER_EMR_EM0_MASK (0x1U)
2979#define CTIMER_EMR_EM0_SHIFT (0U)
2980/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
2981 * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
2982 * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
2983 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2984 */
2985#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
2986#define CTIMER_EMR_EM1_MASK (0x2U)
2987#define CTIMER_EMR_EM1_SHIFT (1U)
2988/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
2989 * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
2990 * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
2991 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2992 */
2993#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
2994#define CTIMER_EMR_EM2_MASK (0x4U)
2995#define CTIMER_EMR_EM2_SHIFT (2U)
2996/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
2997 * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
2998 * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
2999 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
3000 */
3001#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
3002#define CTIMER_EMR_EM3_MASK (0x8U)
3003#define CTIMER_EMR_EM3_SHIFT (3U)
3004/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
3005 * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
3006 * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
3007 * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
3008 */
3009#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
3010#define CTIMER_EMR_EMC0_MASK (0x30U)
3011#define CTIMER_EMR_EMC0_SHIFT (4U)
3012/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
3013 * 0b00..Do Nothing.
3014 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
3015 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
3016 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3017 */
3018#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
3019#define CTIMER_EMR_EMC1_MASK (0xC0U)
3020#define CTIMER_EMR_EMC1_SHIFT (6U)
3021/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
3022 * 0b00..Do Nothing.
3023 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
3024 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
3025 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3026 */
3027#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
3028#define CTIMER_EMR_EMC2_MASK (0x300U)
3029#define CTIMER_EMR_EMC2_SHIFT (8U)
3030/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
3031 * 0b00..Do Nothing.
3032 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
3033 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
3034 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3035 */
3036#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
3037#define CTIMER_EMR_EMC3_MASK (0xC00U)
3038#define CTIMER_EMR_EMC3_SHIFT (10U)
3039/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
3040 * 0b00..Do Nothing.
3041 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
3042 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
3043 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3044 */
3045#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
3046/*! @} */
3047
3048/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
3049/*! @{ */
3050#define CTIMER_CTCR_CTMODE_MASK (0x3U)
3051#define CTIMER_CTCR_CTMODE_SHIFT (0U)
3052/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
3053 * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
3054 * is incremented when the Prescale Counter matches the Prescale Register.
3055 * 0b00..Timer Mode. Incremented every rising APB bus clock edge.
3056 * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
3057 * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
3058 * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
3059 */
3060#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
3061#define CTIMER_CTCR_CINSEL_MASK (0xCU)
3062#define CTIMER_CTCR_CINSEL_SHIFT (2U)
3063/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
3064 * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
3065 * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
3066 * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
3067 * same timer.
3068 * 0b00..Channel 0. CAPn.0 for CTIMERn
3069 * 0b01..Channel 1. CAPn.1 for CTIMERn
3070 * 0b10..Channel 2. CAPn.2 for CTIMERn
3071 * 0b11..Channel 3. CAPn.3 for CTIMERn
3072 */
3073#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
3074#define CTIMER_CTCR_ENCC_MASK (0x10U)
3075#define CTIMER_CTCR_ENCC_SHIFT (4U)
3076/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
3077 * capture-edge event specified in bits 7:5 occurs.
3078 */
3079#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
3080#define CTIMER_CTCR_SELCC_MASK (0xE0U)
3081#define CTIMER_CTCR_SELCC_SHIFT (5U)
3082/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
3083 * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
3084 * 0x3 and 0x6 to 0x7 are reserved.
3085 * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
3086 * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
3087 * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
3088 * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
3089 * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
3090 * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
3091 */
3092#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
3093/*! @} */
3094
3095/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
3096/*! @{ */
3097#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
3098#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
3099/*! PWMEN0 - PWM mode enable for channel0.
3100 * 0b0..Match. CTIMERn_MAT0 is controlled by EM0.
3101 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
3102 */
3103#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
3104#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
3105#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
3106/*! PWMEN1 - PWM mode enable for channel1.
3107 * 0b0..Match. CTIMERn_MAT01 is controlled by EM1.
3108 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
3109 */
3110#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
3111#define CTIMER_PWMC_PWMEN2_MASK (0x4U)
3112#define CTIMER_PWMC_PWMEN2_SHIFT (2U)
3113/*! PWMEN2 - PWM mode enable for channel2.
3114 * 0b0..Match. CTIMERn_MAT2 is controlled by EM2.
3115 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
3116 */
3117#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
3118#define CTIMER_PWMC_PWMEN3_MASK (0x8U)
3119#define CTIMER_PWMC_PWMEN3_SHIFT (3U)
3120/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
3121 * 0b0..Match. CTIMERn_MAT3 is controlled by EM3.
3122 * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
3123 */
3124#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
3125/*! @} */
3126
3127/*! @name MSR - Match Shadow Register */
3128/*! @{ */
3129#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU)
3130#define CTIMER_MSR_SHADOWW_SHIFT (0U)
3131/*! SHADOWW - Timer counter match shadow value.
3132 */
3133#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)
3134/*! @} */
3135
3136/* The count of CTIMER_MSR */
3137#define CTIMER_MSR_COUNT (4U)
3138
3139
3140/*!
3141 * @}
3142 */ /* end of group CTIMER_Register_Masks */
3143
3144
3145/* CTIMER - Peripheral instance base addresses */
3146/** Peripheral CTIMER0 base address */
3147#define CTIMER0_BASE (0x40008000u)
3148/** Peripheral CTIMER0 base pointer */
3149#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
3150/** Peripheral CTIMER1 base address */
3151#define CTIMER1_BASE (0x40009000u)
3152/** Peripheral CTIMER1 base pointer */
3153#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
3154/** Peripheral CTIMER2 base address */
3155#define CTIMER2_BASE (0x40028000u)
3156/** Peripheral CTIMER2 base pointer */
3157#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
3158/** Peripheral CTIMER3 base address */
3159#define CTIMER3_BASE (0x40048000u)
3160/** Peripheral CTIMER3 base pointer */
3161#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
3162/** Peripheral CTIMER4 base address */
3163#define CTIMER4_BASE (0x40049000u)
3164/** Peripheral CTIMER4 base pointer */
3165#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
3166/** Array initializer of CTIMER peripheral base addresses */
3167#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
3168/** Array initializer of CTIMER peripheral base pointers */
3169#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
3170/** Interrupt vectors for the CTIMER peripheral type */
3171#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
3172
3173/*!
3174 * @}
3175 */ /* end of group CTIMER_Peripheral_Access_Layer */
3176
3177
3178/* ----------------------------------------------------------------------------
3179 -- DMA Peripheral Access Layer
3180 ---------------------------------------------------------------------------- */
3181
3182/*!
3183 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
3184 * @{
3185 */
3186
3187/** DMA - Register Layout Typedef */
3188typedef struct {
3189 __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
3190 __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
3191 __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
3192 uint8_t RESERVED_0[20];
3193 struct { /* offset: 0x20, array step: 0x5C */
3194 __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
3195 uint8_t RESERVED_0[4];
3196 __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
3197 uint8_t RESERVED_1[4];
3198 __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
3199 uint8_t RESERVED_2[4];
3200 __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
3201 uint8_t RESERVED_3[4];
3202 __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
3203 uint8_t RESERVED_4[4];
3204 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
3205 uint8_t RESERVED_5[4];
3206 __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
3207 uint8_t RESERVED_6[4];
3208 __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
3209 uint8_t RESERVED_7[4];
3210 __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
3211 uint8_t RESERVED_8[4];
3212 __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
3213 uint8_t RESERVED_9[4];
3214 __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
3215 uint8_t RESERVED_10[4];
3216 __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
3217 } COMMON[1];
3218 uint8_t RESERVED_1[900];
3219 struct { /* offset: 0x400, array step: 0x10 */
3220 __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
3221 __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
3222 __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
3223 uint8_t RESERVED_0[4];
3224 } CHANNEL[30];
3225} DMA_Type;
3226
3227/* ----------------------------------------------------------------------------
3228 -- DMA Register Masks
3229 ---------------------------------------------------------------------------- */
3230
3231/*!
3232 * @addtogroup DMA_Register_Masks DMA Register Masks
3233 * @{
3234 */
3235
3236/*! @name CTRL - DMA control. */
3237/*! @{ */
3238#define DMA_CTRL_ENABLE_MASK (0x1U)
3239#define DMA_CTRL_ENABLE_SHIFT (0U)
3240/*! ENABLE - DMA controller master enable.
3241 * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
3242 * disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
3243 * 0b1..Enabled. The DMA controller is enabled.
3244 */
3245#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
3246/*! @} */
3247
3248/*! @name INTSTAT - Interrupt status. */
3249/*! @{ */
3250#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
3251#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
3252/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
3253 * 0b0..Not pending. No enabled interrupts are pending.
3254 * 0b1..Pending. At least one enabled interrupt is pending.
3255 */
3256#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
3257#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
3258#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
3259/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
3260 * 0b0..Not pending. No error interrupts are pending.
3261 * 0b1..Pending. At least one error interrupt is pending.
3262 */
3263#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
3264/*! @} */
3265
3266/*! @name SRAMBASE - SRAM address of the channel configuration table. */
3267/*! @{ */
3268#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
3269#define DMA_SRAMBASE_OFFSET_SHIFT (9U)
3270/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
3271 * table must begin on a 512 byte boundary.
3272 */
3273#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
3274/*! @} */
3275
3276/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
3277/*! @{ */
3278#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)
3279#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
3280/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
3281 * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
3282 */
3283#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
3284/*! @} */
3285
3286/* The count of DMA_COMMON_ENABLESET */
3287#define DMA_COMMON_ENABLESET_COUNT (1U)
3288
3289/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
3290/*! @{ */
3291#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)
3292#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
3293/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
3294 * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
3295 * are reserved.
3296 */
3297#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
3298/*! @} */
3299
3300/* The count of DMA_COMMON_ENABLECLR */
3301#define DMA_COMMON_ENABLECLR_COUNT (1U)
3302
3303/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
3304/*! @{ */
3305#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)
3306#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
3307/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
3308 * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
3309 */
3310#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
3311/*! @} */
3312
3313/* The count of DMA_COMMON_ACTIVE */
3314#define DMA_COMMON_ACTIVE_COUNT (1U)
3315
3316/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
3317/*! @{ */
3318#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)
3319#define DMA_COMMON_BUSY_BSY_SHIFT (0U)
3320/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
3321 * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
3322 */
3323#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
3324/*! @} */
3325
3326/* The count of DMA_COMMON_BUSY */
3327#define DMA_COMMON_BUSY_COUNT (1U)
3328
3329/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
3330/*! @{ */
3331#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)
3332#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
3333/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
3334 * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
3335 * not active. 1 = error interrupt is active.
3336 */
3337#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
3338/*! @} */
3339
3340/* The count of DMA_COMMON_ERRINT */
3341#define DMA_COMMON_ERRINT_COUNT (1U)
3342
3343/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
3344/*! @{ */
3345#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)
3346#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
3347/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
3348 * number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
3349 * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
3350 */
3351#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
3352/*! @} */
3353
3354/* The count of DMA_COMMON_INTENSET */
3355#define DMA_COMMON_INTENSET_COUNT (1U)
3356
3357/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
3358/*! @{ */
3359#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)
3360#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
3361/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
3362 * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
3363 * reserved.
3364 */
3365#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
3366/*! @} */
3367
3368/* The count of DMA_COMMON_INTENCLR */
3369#define DMA_COMMON_INTENCLR_COUNT (1U)
3370
3371/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
3372/*! @{ */
3373#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)
3374#define DMA_COMMON_INTA_IA_SHIFT (0U)
3375/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
3376 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
3377 * interrupt A is not active. 1 = the DMA channel interrupt A is active.
3378 */
3379#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
3380/*! @} */
3381
3382/* The count of DMA_COMMON_INTA */
3383#define DMA_COMMON_INTA_COUNT (1U)
3384
3385/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
3386/*! @{ */
3387#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)
3388#define DMA_COMMON_INTB_IB_SHIFT (0U)
3389/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
3390 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
3391 * interrupt B is not active. 1 = the DMA channel interrupt B is active.
3392 */
3393#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
3394/*! @} */
3395
3396/* The count of DMA_COMMON_INTB */
3397#define DMA_COMMON_INTB_COUNT (1U)
3398
3399/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
3400/*! @{ */
3401#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)
3402#define DMA_COMMON_SETVALID_SV_SHIFT (0U)
3403/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
3404 * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
3405 * VALIDPENDING control bit for DMA channel n
3406 */
3407#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
3408/*! @} */
3409
3410/* The count of DMA_COMMON_SETVALID */
3411#define DMA_COMMON_SETVALID_COUNT (1U)
3412
3413/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
3414/*! @{ */
3415#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)
3416#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
3417/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
3418 * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
3419 * sets the TRIG bit for DMA channel n.
3420 */
3421#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
3422/*! @} */
3423
3424/* The count of DMA_COMMON_SETTRIG */
3425#define DMA_COMMON_SETTRIG_COUNT (1U)
3426
3427/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
3428/*! @{ */
3429#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)
3430#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
3431/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
3432 * 1 = aborts DMA operations on channel n.
3433 */
3434#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
3435/*! @} */
3436
3437/* The count of DMA_COMMON_ABORT */
3438#define DMA_COMMON_ABORT_COUNT (1U)
3439
3440/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
3441/*! @{ */
3442#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
3443#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
3444/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
3445 * move, any peripheral DMA request associated with that channel can be disabled to prevent any
3446 * interaction between the peripheral and the DMA controller.
3447 * 0b0..Disabled. Peripheral DMA requests are disabled.
3448 * 0b1..Enabled. Peripheral DMA requests are enabled.
3449 */
3450#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
3451#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
3452#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
3453/*! HWTRIGEN - Hardware Triggering Enable for this channel.
3454 * 0b0..Disabled. Hardware triggering is not used.
3455 * 0b1..Enabled. Use hardware triggering.
3456 */
3457#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
3458#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
3459#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
3460/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
3461 * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
3462 * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
3463 */
3464#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
3465#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
3466#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
3467/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
3468 * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
3469 * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
3470 * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
3471 * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
3472 * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
3473 * current BURSTPOWER length are completed.
3474 */
3475#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
3476#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
3477#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
3478/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
3479 * 0b0..Single transfer. Hardware trigger causes a single transfer.
3480 * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
3481 * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a
3482 * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
3483 * complete.
3484 */
3485#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
3486#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
3487#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
3488/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
3489 * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
3490 * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
3491 * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that
3492 * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:
3493 * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =
3494 * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The
3495 * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
3496 * multiple of the burst size.
3497 */
3498#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
3499#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
3500#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
3501/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
3502 * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this
3503 * could be used to read several sequential registers from a peripheral for each DMA burst,
3504 * reading the same registers again for each burst.
3505 * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
3506 * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
3507 */
3508#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
3509#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
3510#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
3511/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
3512 * 'wrapped', meaning that the destination address range for each burst will be the same. As an
3513 * example, this could be used to write several sequential registers to a peripheral for each DMA
3514 * burst, writing the same registers again for each burst.
3515 * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
3516 * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
3517 */
3518#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
3519#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
3520#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
3521/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority
3522 * levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
3523 */
3524#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
3525/*! @} */
3526
3527/* The count of DMA_CHANNEL_CFG */
3528#define DMA_CHANNEL_CFG_COUNT (30U)
3529
3530/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
3531/*! @{ */
3532#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
3533#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
3534/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the
3535 * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
3536 * 0b0..No effect. No effect on DMA operation.
3537 * 0b1..Valid pending.
3538 */
3539#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
3540#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
3541#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
3542/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is
3543 * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
3544 * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
3545 * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
3546 */
3547#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
3548/*! @} */
3549
3550/* The count of DMA_CHANNEL_CTLSTAT */
3551#define DMA_CHANNEL_CTLSTAT_COUNT (30U)
3552
3553/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
3554/*! @{ */
3555#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
3556#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
3557/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor
3558 * is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
3559 * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
3560 * 0b1..Valid. The current channel descriptor is considered valid.
3561 */
3562#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
3563#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
3564#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
3565/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current
3566 * descriptor is exhausted. Reloading allows ping-pong and linked transfers.
3567 * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
3568 * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.
3569 */
3570#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
3571#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
3572#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
3573/*! SWTRIG - Software Trigger.