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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54616/system_LPC54616.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54616/system_LPC54616.c
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1/*
2** ###################################################################
3** Processors: LPC54616J256ET180
4** LPC54616J512BD100
5** LPC54616J512BD208
6** LPC54616J512ET100
7**
8** Compilers: GNU C Compiler
9** IAR ANSI C/C++ Compiler for ARM
10** Keil ARM C/C++ Compiler
11** MCUXpresso Compiler
12**
13** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017
14** Version: rev. 1.2, 2017-06-08
15** Build: b201015
16**
17** Abstract:
18** Provides a system configuration function and a global variable that
19** contains the system frequency. It configures the device and initializes
20** the oscillator (PLL) that is part of the microcontroller device.
21**
22** Copyright 2016 Freescale Semiconductor, Inc.
23** Copyright 2016-2020 NXP
24** All rights reserved.
25**
26** SPDX-License-Identifier: BSD-3-Clause
27**
28** http: www.nxp.com
29** mail: [email protected]
30**
31** Revisions:
32** - rev. 1.0 (2016-08-12)
33** Initial version.
34** - rev. 1.1 (2016-11-25)
35** Update CANFD and Classic CAN register.
36** Add MAC TIMERSTAMP registers.
37** - rev. 1.2 (2017-06-08)
38** Remove RTC_CTRL_RTC_OSC_BYPASS.
39** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
40** Remove RESET and HALT from SYSCON_AHBCLKDIV.
41**
42** ###################################################################
43*/
44
45/*!
46 * @file LPC54616
47 * @version 1.2
48 * @date 2017-06-08
49 * @brief Device specific configuration file for LPC54616 (implementation file)
50 *
51 * Provides a system configuration function and a global variable that contains
52 * the system frequency. It configures the device and initializes the oscillator
53 * (PLL) that is part of the microcontroller device.
54 */
55
56#include <stdint.h>
57#include "fsl_device_registers.h"
58
59#define NVALMAX (0x100)
60#define PVALMAX (0x20U)
61#define MVALMAX (0x8000U)
62#define PLL_MDEC_VAL_P (0U) /* MDEC is in bits 16:0 */
63#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
64#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */
65#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
66#define PLL_PDEC_VAL_P (0U) /* PDEC is in bits 6:0 */
67#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
68
69static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
70 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
71/* Get WATCH DOG Clk */
72static uint32_t getWdtOscFreq(void)
73{
74 uint8_t freq_sel, div_sel;
75 if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) == SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
76 {
77 return 0U;
78 }
79 else
80 {
81 div_sel = (uint8_t)((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1UL) << 1UL;
82 freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
83 return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
84 }
85}
86/* Find decoded N value for raw NDEC value */
87static uint32_t pllDecodeN(uint32_t NDEC)
88{
89 uint32_t n, x, i;
90
91 /* Find NDec */
92 switch (NDEC)
93 {
94 case 0x3FFU:
95 n = 0UL;
96 break;
97 case 0x302U:
98 n = 1UL;
99 break;
100 case 0x202U:
101 n = 2UL;
102 break;
103 default:
104 x = 0x080UL;
105 n = 0xFFFFFFFFUL;
106 for (i = NVALMAX; i >= 3UL; i--)
107 {
108 x = (((x ^ (x >> 2UL) ^ (x >> 3UL) ^ (x >> 4UL)) & 1UL) << 7UL) | ((x >> 1UL) & 0x7FUL);
109 if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
110 {
111 /* Decoded value of NDEC */
112 n = i;
113 }
114 if (n != 0xFFFFFFFFUL)
115 {
116 break;
117 }
118 }
119 break;
120 }
121 return n;
122}
123
124/* Find decoded P value for raw PDEC value */
125static uint32_t pllDecodeP(uint32_t PDEC)
126{
127 uint32_t p, x, i;
128 /* Find PDec */
129 switch (PDEC)
130 {
131 case 0x7FU:
132 p = 0UL;
133 break;
134 case 0x62U:
135 p = 1UL;
136 break;
137 case 0x42U:
138 p = 2UL;
139 break;
140 default:
141 x = 0x10UL;
142 p = 0xFFFFFFFFUL;
143 for (i = PVALMAX; i >= 3UL; i--)
144 {
145 x = (((x ^ (x >> 2UL)) & 1UL) << 4UL) | ((x >> 1UL) & 0xFUL);
146 if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
147 {
148 /* Decoded value of PDEC */
149 p = i;
150 }
151 if (p != 0xFFFFFFFFUL)
152 {
153 break;
154 }
155 }
156 break;
157 }
158 return p;
159}
160
161/* Find decoded M value for raw MDEC value */
162static uint32_t pllDecodeM(uint32_t MDEC)
163{
164 uint32_t m, i, x;
165
166 /* Find MDec */
167 switch (MDEC)
168 {
169 case 0x1FFFFU:
170 m = 0UL;
171 break;
172 case 0x18003U:
173 m = 1UL;
174 break;
175 case 0x10003U:
176 m = 2UL;
177 break;
178 default:
179 x = 0x04000UL;
180 m = 0xFFFFFFFFUL;
181 for (i = MVALMAX; i >= 3UL; i--)
182 {
183 x = (((x ^ (x >> 1UL)) & 1UL) << 14UL) | ((x >> 1UL) & 0x3FFFUL);
184 if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
185 {
186 /* Decoded value of MDEC */
187 m = i;
188 }
189 if (m != 0xFFFFFFFFUL)
190 {
191 break;
192 }
193 }
194 break;
195 }
196 return m;
197}
198
199/* Get predivider (N) from PLL NDEC setting */
200static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
201{
202 uint32_t preDiv = 1U;
203
204 /* Direct input is not used? */
205 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0U)
206 {
207 /* Decode NDEC value to get (N) pre divider */
208 preDiv = pllDecodeN(nDecReg & 0x3FFU);
209 if (preDiv == 0U)
210 {
211 preDiv = 1U;
212 }
213 }
214 /* Adjusted by 1, directi is used to bypass */
215 return preDiv;
216}
217
218/* Get postdivider (P) from PLL PDEC setting */
219static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
220{
221 uint32_t postDiv = 1U;
222
223 /* Direct input is not used? */
224 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U)
225 {
226 /* Decode PDEC value to get (P) post divider */
227 postDiv = 2U * pllDecodeP(pDecReg & 0x7FU);
228 if (postDiv == 0U)
229 {
230 postDiv = 2U;
231 }
232 }
233 /* Adjusted by 1, directo is used to bypass */
234 return postDiv;
235}
236
237/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
238static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
239{
240 uint32_t mMult = 1U;
241
242 /* Decode MDEC value to get (M) multiplier */
243 mMult = pllDecodeM(mDecReg & 0x1FFFFU);
244 if (mMult == 0U)
245 {
246 mMult = 1U;
247 }
248 return mMult;
249}
250
251
252
253/* ----------------------------------------------------------------------------
254 -- Core clock
255 ---------------------------------------------------------------------------- */
256
257uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
258
259/* ----------------------------------------------------------------------------
260 -- SystemInit()
261 ---------------------------------------------------------------------------- */
262
263void SystemInit (void) {
264#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
265 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
266#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
267
268#if defined(__MCUXPRESSO)
269 extern void(*const g_pfnVectors[]) (void);
270 SCB->VTOR = (uint32_t) &g_pfnVectors;
271#else
272 extern void *__Vectors;
273 SCB->VTOR = (uint32_t) &__Vectors;
274#endif
275 SYSCON->ARMTRACECLKDIV = 0U;
276/* Optionally enable RAM banks that may be off by default at reset */
277#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
278 SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
279#endif
280 SystemInitHook();
281}
282
283/* ----------------------------------------------------------------------------
284 -- SystemCoreClockUpdate()
285 ---------------------------------------------------------------------------- */
286
287void SystemCoreClockUpdate (void) {
288uint32_t clkRate = 0U;
289 uint32_t prediv, postdiv;
290 uint64_t workRate;
291
292 switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
293 {
294 case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
295 switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
296 {
297 case 0x00U: /* FRO 12 MHz (fro_12m) */
298 clkRate = CLK_FRO_12MHZ;
299 break;
300 case 0x01U: /* CLKIN Source (clk_in) */
301 clkRate = CLK_CLK_IN;
302 break;
303 case 0x02U: /* Watchdog oscillator (wdt_clk) */
304 clkRate = getWdtOscFreq();
305 break;
306 default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
307 if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) == SYSCON_FROCTRL_SEL_MASK)
308 {
309 clkRate = CLK_FRO_96MHZ;
310 }
311 else
312 {
313 clkRate = CLK_FRO_48MHZ;
314 }
315 break;
316 }
317 break;
318 case 0x02U: /* System PLL clock (pll_clk)*/
319 switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
320 {
321 case 0x00U: /* FRO 12 MHz (fro_12m) */
322 clkRate = CLK_FRO_12MHZ;
323 break;
324 case 0x01U: /* CLKIN Source (clk_in) */
325 clkRate = CLK_CLK_IN;
326 break;
327 case 0x02U: /* Watchdog oscillator (wdt_clk) */
328 clkRate = getWdtOscFreq();
329 break;
330 case 0x03U: /* RTC oscillator 32 kHz output (32k_clk) */
331 clkRate = CLK_RTC_32K_CLK;
332 break;
333 default:
334 clkRate = 0U;
335 break;
336 }
337 if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0U)
338 {
339 /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
340 prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
341 postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
342 /* Adjust input clock */
343 clkRate = clkRate / prediv;
344
345 /* MDEC used for rate */
346 workRate = (uint64_t)(clkRate) * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
347 clkRate = (uint32_t)(workRate / ((uint64_t)postdiv));
348 clkRate = clkRate * 2UL; /* PLL CCO output is divided by 2 before to M-Divider */
349 }
350 break;
351 case 0x03U: /* RTC oscillator 32 kHz output (32k_clk) */
352 clkRate = CLK_RTC_32K_CLK;
353 break;
354 default:
355 clkRate = 0U;
356 break;
357 }
358 SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL);
359}
360
361/* ----------------------------------------------------------------------------
362 -- SystemInitHook()
363 ---------------------------------------------------------------------------- */
364
365__attribute__ ((weak)) void SystemInitHook (void) {
366 /* Void implementation of the weak function. */
367}
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