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1/*
2** ###################################################################
3** Processor: LPC54628J512ET180
4** Compilers: GNU C Compiler
5** IAR ANSI C/C++ Compiler for ARM
6** Keil ARM C/C++ Compiler
7** MCUXpresso Compiler
8**
9** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017
10** Version: rev. 1.2, 2017-06-08
11** Build: b201015
12**
13** Abstract:
14** Provides a system configuration function and a global variable that
15** contains the system frequency. It configures the device and initializes
16** the oscillator (PLL) that is part of the microcontroller device.
17**
18** Copyright 2016 Freescale Semiconductor, Inc.
19** Copyright 2016-2020 NXP
20** All rights reserved.
21**
22** SPDX-License-Identifier: BSD-3-Clause
23**
24** http: www.nxp.com
25** mail: [email protected]
26**
27** Revisions:
28** - rev. 1.0 (2016-08-12)
29** Initial version.
30** - rev. 1.1 (2016-11-25)
31** Update CANFD and Classic CAN register.
32** Add MAC TIMERSTAMP registers.
33** - rev. 1.2 (2017-06-08)
34** Remove RTC_CTRL_RTC_OSC_BYPASS.
35** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
36** Remove RESET and HALT from SYSCON_AHBCLKDIV.
37**
38** ###################################################################
39*/
40
41/*!
42 * @file LPC54628
43 * @version 1.2
44 * @date 2017-06-08
45 * @brief Device specific configuration file for LPC54628 (implementation file)
46 *
47 * Provides a system configuration function and a global variable that contains
48 * the system frequency. It configures the device and initializes the oscillator
49 * (PLL) that is part of the microcontroller device.
50 */
51
52#include <stdint.h>
53#include "fsl_device_registers.h"
54
55#define NVALMAX (0x100)
56#define PVALMAX (0x20U)
57#define MVALMAX (0x8000U)
58#define PLL_MDEC_VAL_P (0U) /* MDEC is in bits 16:0 */
59#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
60#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */
61#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
62#define PLL_PDEC_VAL_P (0U) /* PDEC is in bits 6:0 */
63#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
64
65static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
66 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
67/* Get WATCH DOG Clk */
68static uint32_t getWdtOscFreq(void)
69{
70 uint8_t freq_sel, div_sel;
71 if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) == SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
72 {
73 return 0U;
74 }
75 else
76 {
77 div_sel = (uint8_t)((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1UL) << 1UL;
78 freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
79 return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
80 }
81}
82/* Find decoded N value for raw NDEC value */
83static uint32_t pllDecodeN(uint32_t NDEC)
84{
85 uint32_t n, x, i;
86
87 /* Find NDec */
88 switch (NDEC)
89 {
90 case 0x3FFU:
91 n = 0UL;
92 break;
93 case 0x302U:
94 n = 1UL;
95 break;
96 case 0x202U:
97 n = 2UL;
98 break;
99 default:
100 x = 0x080UL;
101 n = 0xFFFFFFFFUL;
102 for (i = NVALMAX; i >= 3UL; i--)
103 {
104 x = (((x ^ (x >> 2UL) ^ (x >> 3UL) ^ (x >> 4UL)) & 1UL) << 7UL) | ((x >> 1UL) & 0x7FUL);
105 if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
106 {
107 /* Decoded value of NDEC */
108 n = i;
109 }
110 if (n != 0xFFFFFFFFUL)
111 {
112 break;
113 }
114 }
115 break;
116 }
117 return n;
118}
119
120/* Find decoded P value for raw PDEC value */
121static uint32_t pllDecodeP(uint32_t PDEC)
122{
123 uint32_t p, x, i;
124 /* Find PDec */
125 switch (PDEC)
126 {
127 case 0x7FU:
128 p = 0UL;
129 break;
130 case 0x62U:
131 p = 1UL;
132 break;
133 case 0x42U:
134 p = 2UL;
135 break;
136 default:
137 x = 0x10UL;
138 p = 0xFFFFFFFFUL;
139 for (i = PVALMAX; i >= 3UL; i--)
140 {
141 x = (((x ^ (x >> 2UL)) & 1UL) << 4UL) | ((x >> 1UL) & 0xFUL);
142 if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
143 {
144 /* Decoded value of PDEC */
145 p = i;
146 }
147 if (p != 0xFFFFFFFFUL)
148 {
149 break;
150 }
151 }
152 break;
153 }
154 return p;
155}
156
157/* Find decoded M value for raw MDEC value */
158static uint32_t pllDecodeM(uint32_t MDEC)
159{
160 uint32_t m, i, x;
161
162 /* Find MDec */
163 switch (MDEC)
164 {
165 case 0x1FFFFU:
166 m = 0UL;
167 break;
168 case 0x18003U:
169 m = 1UL;
170 break;
171 case 0x10003U:
172 m = 2UL;
173 break;
174 default:
175 x = 0x04000UL;
176 m = 0xFFFFFFFFUL;
177 for (i = MVALMAX; i >= 3UL; i--)
178 {
179 x = (((x ^ (x >> 1UL)) & 1UL) << 14UL) | ((x >> 1UL) & 0x3FFFUL);
180 if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
181 {
182 /* Decoded value of MDEC */
183 m = i;
184 }
185 if (m != 0xFFFFFFFFUL)
186 {
187 break;
188 }
189 }
190 break;
191 }
192 return m;
193}
194
195/* Get predivider (N) from PLL NDEC setting */
196static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
197{
198 uint32_t preDiv = 1U;
199
200 /* Direct input is not used? */
201 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0U)
202 {
203 /* Decode NDEC value to get (N) pre divider */
204 preDiv = pllDecodeN(nDecReg & 0x3FFU);
205 if (preDiv == 0U)
206 {
207 preDiv = 1U;
208 }
209 }
210 /* Adjusted by 1, directi is used to bypass */
211 return preDiv;
212}
213
214/* Get postdivider (P) from PLL PDEC setting */
215static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
216{
217 uint32_t postDiv = 1U;
218
219 /* Direct input is not used? */
220 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U)
221 {
222 /* Decode PDEC value to get (P) post divider */
223 postDiv = 2U * pllDecodeP(pDecReg & 0x7FU);
224 if (postDiv == 0U)
225 {
226 postDiv = 2U;
227 }
228 }
229 /* Adjusted by 1, directo is used to bypass */
230 return postDiv;
231}
232
233/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
234static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
235{
236 uint32_t mMult = 1U;
237
238 /* Decode MDEC value to get (M) multiplier */
239 mMult = pllDecodeM(mDecReg & 0x1FFFFU);
240 if (mMult == 0U)
241 {
242 mMult = 1U;
243 }
244 return mMult;
245}
246
247
248
249/* ----------------------------------------------------------------------------
250 -- Core clock
251 ---------------------------------------------------------------------------- */
252
253uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
254
255/* ----------------------------------------------------------------------------
256 -- SystemInit()
257 ---------------------------------------------------------------------------- */
258
259void SystemInit (void) {
260#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
261 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
262#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
263
264#if defined(__MCUXPRESSO)
265 extern void(*const g_pfnVectors[]) (void);
266 SCB->VTOR = (uint32_t) &g_pfnVectors;
267#else
268 extern void *__Vectors;
269 SCB->VTOR = (uint32_t) &__Vectors;
270#endif
271 SYSCON->ARMTRACECLKDIV = 0U;
272/* Optionally enable RAM banks that may be off by default at reset */
273#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
274 SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
275#endif
276 SystemInitHook();
277}
278
279/* ----------------------------------------------------------------------------
280 -- SystemCoreClockUpdate()
281 ---------------------------------------------------------------------------- */
282
283void SystemCoreClockUpdate (void) {
284uint32_t clkRate = 0U;
285 uint32_t prediv, postdiv;
286 uint64_t workRate;
287
288 switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
289 {
290 case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
291 switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
292 {
293 case 0x00U: /* FRO 12 MHz (fro_12m) */
294 clkRate = CLK_FRO_12MHZ;
295 break;
296 case 0x01U: /* CLKIN Source (clk_in) */
297 clkRate = CLK_CLK_IN;
298 break;
299 case 0x02U: /* Watchdog oscillator (wdt_clk) */
300 clkRate = getWdtOscFreq();
301 break;
302 default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
303 if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) == SYSCON_FROCTRL_SEL_MASK)
304 {
305 clkRate = CLK_FRO_96MHZ;
306 }
307 else
308 {
309 clkRate = CLK_FRO_48MHZ;
310 }
311 break;
312 }
313 break;
314 case 0x02U: /* System PLL clock (pll_clk)*/
315 switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
316 {
317 case 0x00U: /* FRO 12 MHz (fro_12m) */
318 clkRate = CLK_FRO_12MHZ;
319 break;
320 case 0x01U: /* CLKIN Source (clk_in) */
321 clkRate = CLK_CLK_IN;
322 break;
323 case 0x02U: /* Watchdog oscillator (wdt_clk) */
324 clkRate = getWdtOscFreq();
325 break;
326 case 0x03U: /* RTC oscillator 32 kHz output (32k_clk) */
327 clkRate = CLK_RTC_32K_CLK;
328 break;
329 default:
330 clkRate = 0U;
331 break;
332 }
333 if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0U)
334 {
335 /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
336 prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
337 postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
338 /* Adjust input clock */
339 clkRate = clkRate / prediv;
340
341 /* MDEC used for rate */
342 workRate = (uint64_t)(clkRate) * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
343 clkRate = (uint32_t)(workRate / ((uint64_t)postdiv));
344 clkRate = clkRate * 2UL; /* PLL CCO output is divided by 2 before to M-Divider */
345 }
346 break;
347 case 0x03U: /* RTC oscillator 32 kHz output (32k_clk) */
348 clkRate = CLK_RTC_32K_CLK;
349 break;
350 default:
351 clkRate = 0U;
352 break;
353 }
354 SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL);
355}
356
357/* ----------------------------------------------------------------------------
358 -- SystemInitHook()
359 ---------------------------------------------------------------------------- */
360
361__attribute__ ((weak)) void SystemInitHook (void) {
362 /* Void implementation of the weak function. */
363}
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