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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54S005/LPC54S005.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54S005/LPC54S005.h
new file mode 100644
index 000000000..256f64532
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54S005/LPC54S005.h
@@ -0,0 +1,17823 @@
+/*
+** ###################################################################
+**     Processors:          LPC54S005JBD100
+**                          LPC54S005JET100
+**
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
+**     Version:             rev. 1.0, 2018-04-20
+**     Build:               b200304
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for LPC54S005
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2020 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2018-04-20)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54S005.h
+ * @version 1.0
+ * @date 2018-04-20
+ * @brief CMSIS Peripheral Access Layer for LPC54S005
+ *
+ * CMSIS Peripheral Access Layer for LPC54S005
+ */
+
+#ifndef _LPC54S005_H_
+#define _LPC54S005_H_                            /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 75                 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  WDT_BOD_IRQn                 = 0,                /**< Windowed watchdog timer, Brownout detect */
+  DMA0_IRQn                    = 1,                /**< DMA controller */
+  GINT0_IRQn                   = 2,                /**< GPIO group 0 */
+  GINT1_IRQn                   = 3,                /**< GPIO group 1 */
+  PIN_INT0_IRQn                = 4,                /**< Pin interrupt 0 or pattern match engine slice 0 */
+  PIN_INT1_IRQn                = 5,                /**< Pin interrupt 1or pattern match engine slice 1 */
+  PIN_INT2_IRQn                = 6,                /**< Pin interrupt 2 or pattern match engine slice 2 */
+  PIN_INT3_IRQn                = 7,                /**< Pin interrupt 3 or pattern match engine slice 3 */
+  UTICK0_IRQn                  = 8,                /**< Micro-tick Timer */
+  MRT0_IRQn                    = 9,                /**< Multi-rate timer */
+  CTIMER0_IRQn                 = 10,               /**< Standard counter/timer CTIMER0 */
+  CTIMER1_IRQn                 = 11,               /**< Standard counter/timer CTIMER1 */
+  SCT0_IRQn                    = 12,               /**< SCTimer/PWM */
+  CTIMER3_IRQn                 = 13,               /**< Standard counter/timer CTIMER3 */
+  FLEXCOMM0_IRQn               = 14,               /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM1_IRQn               = 15,               /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM2_IRQn               = 16,               /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM3_IRQn               = 17,               /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM4_IRQn               = 18,               /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM5_IRQn               = 19,               /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
+  FLEXCOMM6_IRQn               = 20,               /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+  FLEXCOMM7_IRQn               = 21,               /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+  ADC0_SEQA_IRQn               = 22,               /**< ADC0 sequence A completion. */
+  ADC0_SEQB_IRQn               = 23,               /**< ADC0 sequence B completion. */
+  ADC0_THCMP_IRQn              = 24,               /**< ADC0 threshold compare and error. */
+  DMIC0_IRQn                   = 25,               /**< Digital microphone and DMIC subsystem */
+  HWVAD0_IRQn                  = 26,               /**< Hardware Voice Activity Detector */
+  USB0_NEEDCLK_IRQn            = 27,               /**< USB Activity Wake-up Interrupt */
+  USB0_IRQn                    = 28,               /**< USB device */
+  RTC_IRQn                     = 29,               /**< RTC alarm and wake-up interrupts */
+  FLEXCOMM10_IRQn              = 30,               /**< Flexcomm Interface 10 (SPI, FLEXCOMM) */
+  Reserved47_IRQn              = 31,               /**< Reserved interrupt */
+  PIN_INT4_IRQn                = 32,               /**< Pin interrupt 4 or pattern match engine slice 4 int */
+  PIN_INT5_IRQn                = 33,               /**< Pin interrupt 5 or pattern match engine slice 5 int */
+  PIN_INT6_IRQn                = 34,               /**< Pin interrupt 6 or pattern match engine slice 6 int */
+  PIN_INT7_IRQn                = 35,               /**< Pin interrupt 7 or pattern match engine slice 7 int */
+  CTIMER2_IRQn                 = 36,               /**< Standard counter/timer CTIMER2 */
+  CTIMER4_IRQn                 = 37,               /**< Standard counter/timer CTIMER4 */
+  RIT_IRQn                     = 38,               /**< Repetitive Interrupt Timer */
+  SPIFI0_IRQn                  = 39,               /**< SPI flash interface */
+  FLEXCOMM8_IRQn               = 40,               /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM9_IRQn               = 41,               /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
+  SDIO_IRQn                    = 42,               /**< SD/MMC  */
+  CAN0_IRQ0_IRQn               = 43,               /**< CAN0 interrupt0 */
+  CAN0_IRQ1_IRQn               = 44,               /**< CAN0 interrupt1 */
+  CAN1_IRQ0_IRQn               = 45,               /**< CAN1 interrupt0 */
+  CAN1_IRQ1_IRQn               = 46,               /**< CAN1 interrupt1 */
+  USB1_IRQn                    = 47,               /**< USB1 interrupt */
+  USB1_NEEDCLK_IRQn            = 48,               /**< USB1 activity */
+  ETHERNET_IRQn                = 49,               /**< Ethernet */
+  ETHERNET_PMT_IRQn            = 50,               /**< Ethernet power management interrupt */
+  ETHERNET_MACLP_IRQn          = 51,               /**< Ethernet MAC interrupt */
+  Reserved68_IRQn              = 52,               /**< Reserved interrupt */
+  LCD_IRQn                     = 53,               /**< LCD interrupt */
+  SHA_IRQn                     = 54,               /**< SHA interrupt */
+  SMARTCARD0_IRQn              = 55,               /**< Smart card 0 interrupt */
+  SMARTCARD1_IRQn              = 56,               /**< Smart card 1 interrupt */
+  Reserved73_IRQn              = 57,               /**< Reserved interrupt */
+  PUF_IRQn                     = 58                /**< PUF interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               3         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_LPC54S005.h"          /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup dma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according  to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+    kDmaRequestFlexcomm0Rx          = 0U,          /**< Flexcomm Interface 0 RX/I2C Slave */
+    kDmaRequestFlexcomm0Tx          = 1U,          /**< Flexcomm Interface 0 TX/I2C Master */
+    kDmaRequestFlexcomm1Rx          = 2U,          /**< Flexcomm Interface 1 RX/I2C Slave */
+    kDmaRequestFlexcomm1Tx          = 3U,          /**< Flexcomm Interface 1 TX/I2C Master */
+    kDmaRequestFlexcomm2Rx          = 4U,          /**< Flexcomm Interface 2 RX/I2C Slave */
+    kDmaRequestFlexcomm2Tx          = 5U,          /**< Flexcomm Interface 2 TX/I2C Master */
+    kDmaRequestFlexcomm3Rx          = 6U,          /**< Flexcomm Interface 3 RX/I2C Slave */
+    kDmaRequestFlexcomm3Tx          = 7U,          /**< Flexcomm Interface 3 TX/I2C Master */
+    kDmaRequestFlexcomm4Rx          = 8U,          /**< Flexcomm Interface 4 RX/I2C Slave */
+    kDmaRequestFlexcomm4Tx          = 9U,          /**< Flexcomm Interface 4 TX/I2C Master */
+    kDmaRequestFlexcomm5Rx          = 10U,         /**< Flexcomm Interface 5 RX/I2C Slave */
+    kDmaRequestFlexcomm5Tx          = 11U,         /**< Flexcomm Interface 5 TX/I2C Master */
+    kDmaRequestFlexcomm6Rx          = 12U,         /**< Flexcomm Interface 6 RX/I2C Slave */
+    kDmaRequestFlexcomm6Tx          = 13U,         /**< Flexcomm Interface 6 TX/I2C Master */
+    kDmaRequestFlexcomm7Rx          = 14U,         /**< Flexcomm Interface 7 RX/I2C Slave */
+    kDmaRequestFlexcomm7Tx          = 15U,         /**< Flexcomm Interface 7 TX/I2C Master */
+    kDmaRequestDMIC0                = 16U,         /**< Digital microphone interface 0 channel 0 */
+    kDmaRequestDMIC1                = 17U,         /**< Digital microphone interface 0 channel 1 */
+    kDmaRequestSPIFI                = 18U,         /**< SPI Flash Interface */
+    kDmaRequestSHA                  = 19U,         /**< Secure Hash Algorithm */
+    kDmaRequestFlexcomm8Rx          = 20U,         /**< Flexcomm Interface 8 RX/I2C Slave */
+    kDmaRequestFlexcomm8Tx          = 21U,         /**< Flexcomm Interface 8 TX/I2C Slave */
+    kDmaRequestFlexcomm9Rx          = 22U,         /**< Flexcomm Interface 9 RX/I2C Slave */
+    kDmaRequestFlexcomm9Tx          = 23U,         /**< Flexcomm Interface 9 TX/I2C Slave */
+    kDmaRequestSMARTCARD0_RX        = 24U,         /**< SMARTCARD0 RX */
+    kDmaRequestSMARTCARD0_TX        = 25U,         /**< SMARTCARD0 TX */
+    kDmaRequestSMARTCARD1_RX        = 26U,         /**< SMARTCARD1 RX */
+    kDmaRequestSMARTCARD1_TX        = 27U,         /**< SMARTCARD1 TX */
+    kDmaRequestFlexcomm10Rx         = 28U,         /**< Flexcomm Interface 10 RX */
+    kDmaRequestFlexcomm10Tx         = 29U,         /**< Flexcomm Interface 10 TX */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
+  __IO uint32_t INSEL;                             /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
+  __IO uint32_t SEQ_CTRL[2];                       /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
+  __I  uint32_t SEQ_GDAT[2];                       /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
+       uint8_t RESERVED_0[8];
+  __I  uint32_t DAT[12];                           /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
+  __IO uint32_t THR0_LOW;                          /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
+  __IO uint32_t THR1_LOW;                          /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
+  __IO uint32_t THR0_HIGH;                         /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
+  __IO uint32_t THR1_HIGH;                         /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
+  __IO uint32_t CHAN_THRSEL;                       /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
+  __IO uint32_t INTEN;                             /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
+  __IO uint32_t FLAGS;                             /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
+  __IO uint32_t STARTUP;                           /**< ADC Startup register., offset: 0x6C */
+  __IO uint32_t CALIB;                             /**< ADC Calibration register., offset: 0x70 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
+/*! @{ */
+#define ADC_CTRL_CLKDIV_MASK                     (0xFFU)
+#define ADC_CTRL_CLKDIV_SHIFT                    (0U)
+/*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce
+ *    the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically,
+ *    software should program the smallest value in this field that yields this maximum clock rate or
+ *    slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may
+ *    be desirable. This field is ignored in the asynchronous operating mode.
+ */
+#define ADC_CTRL_CLKDIV(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
+#define ADC_CTRL_ASYNMODE_MASK                   (0x100U)
+#define ADC_CTRL_ASYNMODE_SHIFT                  (8U)
+/*! ASYNMODE - Select clock mode.
+ *  0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in
+ *       the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to
+ *       eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger.
+ *       In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC
+ *       input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger
+ *       pulse.
+ *  0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
+ */
+#define ADC_CTRL_ASYNMODE(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
+#define ADC_CTRL_RESOL_MASK                      (0x600U)
+#define ADC_CTRL_RESOL_SHIFT                     (9U)
+/*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher
+ *    conversion rates. A single conversion (including one conversion in a burst or sequence) requires the
+ *    selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when
+ *    the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable
+ *    results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate
+ *    for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system
+ *    clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution
+ *  0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field.
+ *  0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field.
+ *  0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field.
+ *  0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field.
+ */
+#define ADC_CTRL_RESOL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
+#define ADC_CTRL_BYPASSCAL_MASK                  (0x800U)
+#define ADC_CTRL_BYPASSCAL_SHIFT                 (11U)
+/*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset
+ *    error is not a concern in the application.
+ *  0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for
+ *       offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may
+ *       be warranted periodically - especially if operating conditions have changed.
+ *  0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC -
+ *       particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set.
+ */
+#define ADC_CTRL_BYPASSCAL(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
+#define ADC_CTRL_TSAMP_MASK                      (0x7000U)
+#define ADC_CTRL_TSAMP_SHIFT                     (12U)
+/*! TSAMP - Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion
+ *    is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions
+ *    and the output impedance of the analog source, longer sampling times may be required. See
+ *    Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to
+ *    seven, by which the sample period will be extended. The total conversion time will increase by
+ *    the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A
+ *    complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will
+ *    be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will
+ *    require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock
+ *    cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be
+ *    extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require
+ *    22 ADC clocks.
+ */
+#define ADC_CTRL_TSAMP(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
+/*! @} */
+
+/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
+/*! @{ */
+#define ADC_INSEL_SEL_MASK                       (0x3U)
+#define ADC_INSEL_SEL_SHIFT                      (0U)
+/*! SEL - Selects the input source for channel 0. All other values are reserved.
+ *  0b00..ADC0_IN0 function.
+ *  0b11..Internal temperature sensor.
+ */
+#define ADC_INSEL_SEL(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
+/*! @{ */
+#define ADC_SEQ_CTRL_CHANNELS_MASK               (0xFFFU)
+#define ADC_SEQ_CTRL_CHANNELS_SHIFT              (0U)
+/*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this
+ *    sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be
+ *    included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1
+ *    and so forth. When this conversion sequence is triggered, either by a hardware trigger or via
+ *    software command, ADC conversions will be performed on each enabled channel, in sequence,
+ *    beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31)
+ *    is LOW. It is allowed to change this field and set bit 31 in the same write.
+ */
+#define ADC_SEQ_CTRL_CHANNELS(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
+#define ADC_SEQ_CTRL_TRIGGER_MASK                (0x3F000U)
+#define ADC_SEQ_CTRL_TRIGGER_SHIFT               (12U)
+/*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion
+ *    sequence to be initiated. Program the trigger input number in this field. See Table 476. In order
+ *    to avoid generating a spurious trigger, it is recommended writing to this field only when
+ *    SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
+ */
+#define ADC_SEQ_CTRL_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
+#define ADC_SEQ_CTRL_TRIGPOL_MASK                (0x40000U)
+#define ADC_SEQ_CTRL_TRIGPOL_SHIFT               (18U)
+/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In
+ *    order to avoid generating a spurious trigger, it is recommended writing to this field only when
+ *    SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
+ *  0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
+ *  0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
+ */
+#define ADC_SEQ_CTRL_TRIGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
+#define ADC_SEQ_CTRL_SYNCBYPASS_MASK             (0x80000U)
+#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT            (19U)
+/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization
+ *    flip-flop stages and therefore shorten the time between the trigger input signal and the start of a
+ *    conversion. There are slightly different criteria for whether or not this bit can be set
+ *    depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0):
+ *    Synchronization may be bypassed (this bit may be set) if the selected trigger source is already
+ *    synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer).
+ *    Whether this bit is set or not, a trigger pulse must be maintained for at least one system
+ *    clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be
+ *    bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse
+ *    will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and
+ *    on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be
+ *    maintained for one system clock period.
+ *  0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled.
+ *  0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled.
+ */
+#define ADC_SEQ_CTRL_SYNCBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
+#define ADC_SEQ_CTRL_START_MASK                  (0x4000000U)
+#define ADC_SEQ_CTRL_START_SHIFT                 (26U)
+/*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The
+ *    behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this
+ *    bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a
+ *    conversion sequence. It will consequently always read back as a zero.
+ */
+#define ADC_SEQ_CTRL_START(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
+#define ADC_SEQ_CTRL_BURST_MASK                  (0x8000000U)
+#define ADC_SEQ_CTRL_BURST_SHIFT                 (27U)
+/*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled
+ *    through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions
+ *    can be halted by clearing this bit. The sequence currently in progress will be completed before
+ *    conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
+ */
+#define ADC_SEQ_CTRL_BURST(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
+#define ADC_SEQ_CTRL_SINGLESTEP_MASK             (0x10000000U)
+#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT            (28U)
+/*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a
+ *    single conversion on the next channel in the sequence instead of the default response of
+ *    launching an entire sequence of conversions. Once all of the channels comprising a sequence have
+ *    been converted, a subsequent trigger will repeat the sequence beginning with the first enabled
+ *    channel. Interrupt generation will still occur either after each individual conversion or at
+ *    the end of the entire sequence, depending on the state of the MODE bit.
+ */
+#define ADC_SEQ_CTRL_SINGLESTEP(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
+#define ADC_SEQ_CTRL_LOWPRIO_MASK                (0x20000000U)
+#define ADC_SEQ_CTRL_LOWPRIO_SHIFT               (29U)
+/*! LOWPRIO - Set priority for sequence A.
+ *  0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
+ *  0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence
+ *       software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion
+ *       currently in progress will be terminated. The A sequence that was interrupted will automatically resume
+ *       after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the
+ *       conversion sequence will resume from that point.
+ */
+#define ADC_SEQ_CTRL_LOWPRIO(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
+#define ADC_SEQ_CTRL_MODE_MASK                   (0x40000000U)
+#define ADC_SEQ_CTRL_MODE_SHIFT                  (30U)
+/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence
+ *    will be accomplished via reading the global data register (SEQA_GDAT) at the end of each
+ *    conversion, or the individual channel result registers at the end of the entire sequence. Impacts
+ *    when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which
+ *    overrun conditions contribute to an overrun interrupt as described below.
+ *  0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC
+ *       conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The
+ *       OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger
+ *       if enabled.
+ *  0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A
+ *       conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in
+ *       this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun
+ *       interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
+ */
+#define ADC_SEQ_CTRL_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
+#define ADC_SEQ_CTRL_SEQ_ENA_MASK                (0x80000000U)
+#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT               (31U)
+/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be
+ *    taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state
+ *    (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered
+ *    immediately upon being enabled. In order to avoid spuriously triggering the sequence, care
+ *    should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE
+ *    state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be
+ *    triggered immediately upon being enabled.
+ *  0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence
+ *       n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is
+ *       re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
+ *  0b1..Enabled. Sequence n is enabled.
+ */
+#define ADC_SEQ_CTRL_SEQ_ENA(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
+/*! @} */
+
+/* The count of ADC_SEQ_CTRL */
+#define ADC_SEQ_CTRL_COUNT                       (2U)
+
+/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
+/*! @{ */
+#define ADC_SEQ_GDAT_RESULT_MASK                 (0xFFF0U)
+#define ADC_SEQ_GDAT_RESULT_SHIFT                (4U)
+/*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion
+ *    performed under conversion sequence associated with this register. The result is a binary
+ *    fraction representing the voltage on the currently-selected input channel as it falls within the
+ *    range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less
+ *    than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input
+ *    was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this
+ *    result has not yet been read.
+ */
+#define ADC_SEQ_GDAT_RESULT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
+#define ADC_SEQ_GDAT_THCMPRANGE_MASK             (0x30000U)
+#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT            (16U)
+/*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or
+ *    within the range established by the designated threshold comparison registers (THRn_LOW and
+ *    THRn_HIGH).
+ */
+#define ADC_SEQ_GDAT_THCMPRANGE(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
+#define ADC_SEQ_GDAT_THCMPCROSS_MASK             (0xC0000U)
+#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT            (18U)
+/*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a
+ *    crossing of the threshold level established by the designated LOW threshold comparison register
+ *    (THRn_LOW) and, if so, in what direction the crossing occurred.
+ */
+#define ADC_SEQ_GDAT_THCMPCROSS(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
+#define ADC_SEQ_GDAT_CHN_MASK                    (0x3C000000U)
+#define ADC_SEQ_GDAT_CHN_SHIFT                   (26U)
+/*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000
+ *    identifies channel 0, 0001 channel 1, etc.).
+ */
+#define ADC_SEQ_GDAT_CHN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
+#define ADC_SEQ_GDAT_OVERRUN_MASK                (0x40000000U)
+#define ADC_SEQ_GDAT_OVERRUN_SHIFT               (30U)
+/*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a
+ *    previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along
+ *    with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun
+ *    interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set
+ *    to '0' (and if the overrun interrupt is enabled).
+ */
+#define ADC_SEQ_GDAT_OVERRUN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
+#define ADC_SEQ_GDAT_DATAVALID_MASK              (0x80000000U)
+#define ADC_SEQ_GDAT_DATAVALID_SHIFT             (31U)
+/*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded
+ *    into the RESULT field. It is cleared whenever this register is read. This bit will cause a
+ *    conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that
+ *    sequence is set to 0 (and if the interrupt is enabled).
+ */
+#define ADC_SEQ_GDAT_DATAVALID(x)                (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
+/*! @} */
+
+/* The count of ADC_SEQ_GDAT */
+#define ADC_SEQ_GDAT_COUNT                       (2U)
+
+/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
+/*! @{ */
+#define ADC_DAT_RESULT_MASK                      (0xFFF0U)
+#define ADC_DAT_RESULT_SHIFT                     (4U)
+/*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed
+ *    on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin,
+ *    as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on
+ *    the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that
+ *    the voltage on the input was close to, equal to, or greater than that on VREFP.
+ */
+#define ADC_DAT_RESULT(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
+#define ADC_DAT_THCMPRANGE_MASK                  (0x30000U)
+#define ADC_DAT_THCMPRANGE_SHIFT                 (16U)
+/*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion
+ *    was greater than or equal to the value programmed into the designated LOW threshold register
+ *    (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold
+ *    register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value
+ *    programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last
+ *    completed conversion was greater than the value programmed into the designated HIGH threshold
+ *    register (THRn_HIGH). 0x3 = Reserved.
+ */
+#define ADC_DAT_THCMPRANGE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
+#define ADC_DAT_THCMPCROSS_MASK                  (0xC0000U)
+#define ADC_DAT_THCMPCROSS_SHIFT                 (18U)
+/*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The
+ *    most recent completed conversion on this channel had the same relationship (above or below) to
+ *    the threshold value established by the designated LOW threshold register (THRn_LOW) as did the
+ *    previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing
+ *    Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the
+ *    previous sample on this channel was above the threshold value established by the designated LOW
+ *    threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward
+ *    Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred
+ *    - i.e. the previous sample on this channel was below the threshold value established by the
+ *    designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
+ */
+#define ADC_DAT_THCMPCROSS(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
+#define ADC_DAT_CHANNEL_MASK                     (0x3C000000U)
+#define ADC_DAT_CHANNEL_SHIFT                    (26U)
+/*! CHANNEL - This field is hard-coded to contain the channel number that this particular register
+ *    relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1
+ *    register, etc)
+ */
+#define ADC_DAT_CHANNEL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
+#define ADC_DAT_OVERRUN_MASK                     (0x40000000U)
+#define ADC_DAT_OVERRUN_SHIFT                    (30U)
+/*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and
+ *    overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit
+ *    is set. This bit is cleared, along with the DONE bit, whenever this register is read or when
+ *    the data related to this channel is read from either of the global SEQn_GDAT registers. This
+ *    bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if
+ *    the overrun interrupt is enabled. While it is allowed to include the same channels in both
+ *    conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the
+ *    data registers associated with any of the channels that are shared between the two sequences. Any
+ *    erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
+ */
+#define ADC_DAT_OVERRUN(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
+#define ADC_DAT_DATAVALID_MASK                   (0x80000000U)
+#define ADC_DAT_DATAVALID_SHIFT                  (31U)
+/*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is
+ *    cleared whenever this register is read or when the data related to this channel is read from
+ *    either of the global SEQn_GDAT registers. While it is allowed to include the same channels in
+ *    both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in
+ *    the data registers associated with any of the channels that are shared between the two
+ *    sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
+ */
+#define ADC_DAT_DATAVALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
+/*! @} */
+
+/* The count of ADC_DAT */
+#define ADC_DAT_COUNT                            (12U)
+
+/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
+/*! @{ */
+#define ADC_THR0_LOW_THRLOW_MASK                 (0xFFF0U)
+#define ADC_THR0_LOW_THRLOW_SHIFT                (4U)
+/*! THRLOW - Low threshold value against which ADC results will be compared
+ */
+#define ADC_THR0_LOW_THRLOW(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
+/*! @} */
+
+/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
+/*! @{ */
+#define ADC_THR1_LOW_THRLOW_MASK                 (0xFFF0U)
+#define ADC_THR1_LOW_THRLOW_SHIFT                (4U)
+/*! THRLOW - Low threshold value against which ADC results will be compared
+ */
+#define ADC_THR1_LOW_THRLOW(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
+/*! @} */
+
+/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
+/*! @{ */
+#define ADC_THR0_HIGH_THRHIGH_MASK               (0xFFF0U)
+#define ADC_THR0_HIGH_THRHIGH_SHIFT              (4U)
+/*! THRHIGH - High threshold value against which ADC results will be compared
+ */
+#define ADC_THR0_HIGH_THRHIGH(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
+/*! @} */
+
+/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
+/*! @{ */
+#define ADC_THR1_HIGH_THRHIGH_MASK               (0xFFF0U)
+#define ADC_THR1_HIGH_THRHIGH_SHIFT              (4U)
+/*! THRHIGH - High threshold value against which ADC results will be compared
+ */
+#define ADC_THR1_HIGH_THRHIGH(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
+/*! @} */
+
+/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
+/*! @{ */
+#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK          (0x1U)
+#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT         (0U)
+/*! CH0_THRSEL - Threshold select for channel 0.
+ *  0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
+ *  0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
+ */
+#define ADC_CHAN_THRSEL_CH0_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK          (0x2U)
+#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT         (1U)
+/*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH1_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK          (0x4U)
+#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT         (2U)
+/*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH2_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK          (0x8U)
+#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT         (3U)
+/*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH3_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK          (0x10U)
+#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT         (4U)
+/*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH4_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK          (0x20U)
+#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT         (5U)
+/*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH5_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK          (0x40U)
+#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT         (6U)
+/*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH6_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK          (0x80U)
+#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT         (7U)
+/*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH7_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK          (0x100U)
+#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT         (8U)
+/*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH8_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK          (0x200U)
+#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT         (9U)
+/*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH9_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK         (0x400U)
+#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT        (10U)
+/*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH10_THRSEL(x)           (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK         (0x800U)
+#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT        (11U)
+/*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH11_THRSEL(x)           (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
+/*! @} */
+
+/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
+/*! @{ */
+#define ADC_INTEN_SEQA_INTEN_MASK                (0x1U)
+#define ADC_INTEN_SEQA_INTEN_SHIFT               (0U)
+/*! SEQA_INTEN - Sequence A interrupt enable.
+ *  0b0..Disabled. The sequence A interrupt/DMA trigger is disabled.
+ *  0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of
+ *       each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of
+ *       conversions, depending on the MODE bit in the SEQA_CTRL register.
+ */
+#define ADC_INTEN_SEQA_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
+#define ADC_INTEN_SEQB_INTEN_MASK                (0x2U)
+#define ADC_INTEN_SEQB_INTEN_SHIFT               (1U)
+/*! SEQB_INTEN - Sequence B interrupt enable.
+ *  0b0..Disabled. The sequence B interrupt/DMA trigger is disabled.
+ *  0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of
+ *       each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of
+ *       conversions, depending on the MODE bit in the SEQB_CTRL register.
+ */
+#define ADC_INTEN_SEQB_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
+#define ADC_INTEN_OVR_INTEN_MASK                 (0x4U)
+#define ADC_INTEN_OVR_INTEN_SHIFT                (2U)
+/*! OVR_INTEN - Overrun interrupt enable.
+ *  0b0..Disabled. The overrun interrupt is disabled.
+ *  0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel
+ *       data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular
+ *       sequence is 0, then an overrun in the global data register for that sequence will also cause this
+ *       interrupt/DMA trigger to be asserted.
+ */
+#define ADC_INTEN_OVR_INTEN(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
+#define ADC_INTEN_ADCMPINTEN0_MASK               (0x18U)
+#define ADC_INTEN_ADCMPINTEN0_SHIFT              (3U)
+/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0.
+ *  0b00..Disabled.
+ *  0b01..Outside threshold.
+ *  0b10..Crossing threshold.
+ *  0b11..Reserved
+ */
+#define ADC_INTEN_ADCMPINTEN0(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
+#define ADC_INTEN_ADCMPINTEN1_MASK               (0x60U)
+#define ADC_INTEN_ADCMPINTEN1_SHIFT              (5U)
+/*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN1(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
+#define ADC_INTEN_ADCMPINTEN2_MASK               (0x180U)
+#define ADC_INTEN_ADCMPINTEN2_SHIFT              (7U)
+/*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN2(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
+#define ADC_INTEN_ADCMPINTEN3_MASK               (0x600U)
+#define ADC_INTEN_ADCMPINTEN3_SHIFT              (9U)
+/*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN3(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
+#define ADC_INTEN_ADCMPINTEN4_MASK               (0x1800U)
+#define ADC_INTEN_ADCMPINTEN4_SHIFT              (11U)
+/*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN4(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
+#define ADC_INTEN_ADCMPINTEN5_MASK               (0x6000U)
+#define ADC_INTEN_ADCMPINTEN5_SHIFT              (13U)
+/*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN5(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
+#define ADC_INTEN_ADCMPINTEN6_MASK               (0x18000U)
+#define ADC_INTEN_ADCMPINTEN6_SHIFT              (15U)
+/*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN6(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
+#define ADC_INTEN_ADCMPINTEN7_MASK               (0x60000U)
+#define ADC_INTEN_ADCMPINTEN7_SHIFT              (17U)
+/*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN7(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
+#define ADC_INTEN_ADCMPINTEN8_MASK               (0x180000U)
+#define ADC_INTEN_ADCMPINTEN8_SHIFT              (19U)
+/*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN8(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
+#define ADC_INTEN_ADCMPINTEN9_MASK               (0x600000U)
+#define ADC_INTEN_ADCMPINTEN9_SHIFT              (21U)
+/*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN9(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
+#define ADC_INTEN_ADCMPINTEN10_MASK              (0x1800000U)
+#define ADC_INTEN_ADCMPINTEN10_SHIFT             (23U)
+/*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN10(x)                (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
+#define ADC_INTEN_ADCMPINTEN11_MASK              (0x6000000U)
+#define ADC_INTEN_ADCMPINTEN11_SHIFT             (25U)
+/*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN11(x)                (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
+/*! @} */
+
+/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
+/*! @{ */
+#define ADC_FLAGS_THCMP0_MASK                    (0x1U)
+#define ADC_FLAGS_THCMP0_SHIFT                   (0U)
+/*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or
+ *    a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by
+ *    writing a 1.
+ */
+#define ADC_FLAGS_THCMP0(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
+#define ADC_FLAGS_THCMP1_MASK                    (0x2U)
+#define ADC_FLAGS_THCMP1_SHIFT                   (1U)
+/*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP1(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
+#define ADC_FLAGS_THCMP2_MASK                    (0x4U)
+#define ADC_FLAGS_THCMP2_SHIFT                   (2U)
+/*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP2(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
+#define ADC_FLAGS_THCMP3_MASK                    (0x8U)
+#define ADC_FLAGS_THCMP3_SHIFT                   (3U)
+/*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP3(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
+#define ADC_FLAGS_THCMP4_MASK                    (0x10U)
+#define ADC_FLAGS_THCMP4_SHIFT                   (4U)
+/*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP4(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
+#define ADC_FLAGS_THCMP5_MASK                    (0x20U)
+#define ADC_FLAGS_THCMP5_SHIFT                   (5U)
+/*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP5(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
+#define ADC_FLAGS_THCMP6_MASK                    (0x40U)
+#define ADC_FLAGS_THCMP6_SHIFT                   (6U)
+/*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP6(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
+#define ADC_FLAGS_THCMP7_MASK                    (0x80U)
+#define ADC_FLAGS_THCMP7_SHIFT                   (7U)
+/*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP7(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
+#define ADC_FLAGS_THCMP8_MASK                    (0x100U)
+#define ADC_FLAGS_THCMP8_SHIFT                   (8U)
+/*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP8(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
+#define ADC_FLAGS_THCMP9_MASK                    (0x200U)
+#define ADC_FLAGS_THCMP9_SHIFT                   (9U)
+/*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP9(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
+#define ADC_FLAGS_THCMP10_MASK                   (0x400U)
+#define ADC_FLAGS_THCMP10_SHIFT                  (10U)
+/*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP10(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
+#define ADC_FLAGS_THCMP11_MASK                   (0x800U)
+#define ADC_FLAGS_THCMP11_SHIFT                  (11U)
+/*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP11(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
+#define ADC_FLAGS_OVERRUN0_MASK                  (0x1000U)
+#define ADC_FLAGS_OVERRUN0_SHIFT                 (12U)
+/*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0
+ */
+#define ADC_FLAGS_OVERRUN0(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
+#define ADC_FLAGS_OVERRUN1_MASK                  (0x2000U)
+#define ADC_FLAGS_OVERRUN1_SHIFT                 (13U)
+/*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1
+ */
+#define ADC_FLAGS_OVERRUN1(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
+#define ADC_FLAGS_OVERRUN2_MASK                  (0x4000U)
+#define ADC_FLAGS_OVERRUN2_SHIFT                 (14U)
+/*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2
+ */
+#define ADC_FLAGS_OVERRUN2(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
+#define ADC_FLAGS_OVERRUN3_MASK                  (0x8000U)
+#define ADC_FLAGS_OVERRUN3_SHIFT                 (15U)
+/*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3
+ */
+#define ADC_FLAGS_OVERRUN3(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
+#define ADC_FLAGS_OVERRUN4_MASK                  (0x10000U)
+#define ADC_FLAGS_OVERRUN4_SHIFT                 (16U)
+/*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4
+ */
+#define ADC_FLAGS_OVERRUN4(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
+#define ADC_FLAGS_OVERRUN5_MASK                  (0x20000U)
+#define ADC_FLAGS_OVERRUN5_SHIFT                 (17U)
+/*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5
+ */
+#define ADC_FLAGS_OVERRUN5(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
+#define ADC_FLAGS_OVERRUN6_MASK                  (0x40000U)
+#define ADC_FLAGS_OVERRUN6_SHIFT                 (18U)
+/*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6
+ */
+#define ADC_FLAGS_OVERRUN6(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
+#define ADC_FLAGS_OVERRUN7_MASK                  (0x80000U)
+#define ADC_FLAGS_OVERRUN7_SHIFT                 (19U)
+/*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7
+ */
+#define ADC_FLAGS_OVERRUN7(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
+#define ADC_FLAGS_OVERRUN8_MASK                  (0x100000U)
+#define ADC_FLAGS_OVERRUN8_SHIFT                 (20U)
+/*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8
+ */
+#define ADC_FLAGS_OVERRUN8(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
+#define ADC_FLAGS_OVERRUN9_MASK                  (0x200000U)
+#define ADC_FLAGS_OVERRUN9_SHIFT                 (21U)
+/*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9
+ */
+#define ADC_FLAGS_OVERRUN9(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
+#define ADC_FLAGS_OVERRUN10_MASK                 (0x400000U)
+#define ADC_FLAGS_OVERRUN10_SHIFT                (22U)
+/*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10
+ */
+#define ADC_FLAGS_OVERRUN10(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
+#define ADC_FLAGS_OVERRUN11_MASK                 (0x800000U)
+#define ADC_FLAGS_OVERRUN11_SHIFT                (23U)
+/*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11
+ */
+#define ADC_FLAGS_OVERRUN11(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
+#define ADC_FLAGS_SEQA_OVR_MASK                  (0x1000000U)
+#define ADC_FLAGS_SEQA_OVR_SHIFT                 (24U)
+/*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register
+ */
+#define ADC_FLAGS_SEQA_OVR(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
+#define ADC_FLAGS_SEQB_OVR_MASK                  (0x2000000U)
+#define ADC_FLAGS_SEQB_OVR_SHIFT                 (25U)
+/*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register
+ */
+#define ADC_FLAGS_SEQB_OVR(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
+#define ADC_FLAGS_SEQA_INT_MASK                  (0x10000000U)
+#define ADC_FLAGS_SEQA_INT_SHIFT                 (28U)
+/*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0,
+ *    this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which
+ *    is set at the end of every ADC conversion performed as part of sequence A. It will be cleared
+ *    automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register
+ *    is 1, this flag will be set upon completion of an entire A sequence. In this case it must be
+ *    cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN
+ *    register.
+ */
+#define ADC_FLAGS_SEQA_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
+#define ADC_FLAGS_SEQB_INT_MASK                  (0x20000000U)
+#define ADC_FLAGS_SEQB_INT_SHIFT                 (29U)
+/*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0,
+ *    this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which
+ *    is set at the end of every ADC conversion performed as part of sequence B. It will be cleared
+ *    automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register
+ *    is 1, this flag will be set upon completion of an entire B sequence. In this case it must be
+ *    cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN
+ *    register.
+ */
+#define ADC_FLAGS_SEQB_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
+#define ADC_FLAGS_THCMP_INT_MASK                 (0x40000000U)
+#define ADC_FLAGS_THCMP_INT_SHIFT                (30U)
+/*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in
+ *    the lower bits of this register are set to 1 (due to an enabled out-of-range or
+ *    threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be
+ *    individually enabled in the INTEN register to cause this interrupt. This bit will be cleared
+ *    when all of the individual threshold flags are cleared via writing 1s to those bits.
+ */
+#define ADC_FLAGS_THCMP_INT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
+#define ADC_FLAGS_OVR_INT_MASK                   (0x80000000U)
+#define ADC_FLAGS_OVR_INT_SHIFT                  (31U)
+/*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data
+ *    registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers
+ *    is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this
+ *    interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all
+ *    of the individual overrun bits have been cleared via reading the corresponding data registers.
+ */
+#define ADC_FLAGS_OVR_INT(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
+/*! @} */
+
+/*! @name STARTUP - ADC Startup register. */
+/*! @{ */
+#define ADC_STARTUP_ADC_ENA_MASK                 (0x1U)
+#define ADC_STARTUP_ADC_ENA_SHIFT                (0U)
+/*! ADC_ENA - ADC Enable bit. This bit can only be set to a 1 by software. It is cleared
+ *    automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds
+ *    after the ADC is powered up (typically by altering a system-level ADC power control bit).
+ */
+#define ADC_STARTUP_ADC_ENA(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
+#define ADC_STARTUP_ADC_INIT_MASK                (0x2U)
+#define ADC_STARTUP_ADC_INIT_SHIFT               (1U)
+/*! ADC_INIT - ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine
+ *    will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not
+ *    calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is
+ *    required if a calibration is not performed. It will also reload the stored calibration value from
+ *    a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the
+ *    ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or
+ *    an ADC dummy conversion cycle is required. It should not be set during the same write that
+ *    sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically
+ *    when the 'dummy' conversion cycle completes.
+ */
+#define ADC_STARTUP_ADC_INIT(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
+/*! @} */
+
+/*! @name CALIB - ADC Calibration register. */
+/*! @{ */
+#define ADC_CALIB_CALIB_MASK                     (0x1U)
+#define ADC_CALIB_CALIB_SHIFT                    (0U)
+/*! CALIB - Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can
+ *    only be set to a '1' by software. It is cleared automatically when the calibration cycle
+ *    completes.
+ */
+#define ADC_CALIB_CALIB(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
+#define ADC_CALIB_CALREQD_MASK                   (0x2U)
+#define ADC_CALIB_CALREQD_SHIFT                  (1U)
+/*! CALREQD - Calibration required. This read-only bit indicates if calibration is required when
+ *    enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was
+ *    powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to
+ *    determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP
+ *    register) to launch the ADC initialization process which includes a 'dummy' conversion cycle.
+ *    Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks
+ *    required for calibration.
+ */
+#define ADC_CALIB_CALREQD(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
+#define ADC_CALIB_CALVALUE_MASK                  (0x1FCU)
+#define ADC_CALIB_CALVALUE_SHIFT                 (2U)
+/*! CALVALUE - Calibration Value. This read-only field displays the calibration value established
+ *    during last calibration cycle. This value is not typically of any use to the user.
+ */
+#define ADC_CALIB_CALVALUE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x400A0000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_SEQ_IRQS                             { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
+#define ADC_THCMP_IRQS                           { ADC0_THCMP_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AES Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AES_Peripheral_Access_Layer AES Peripheral Access Layer
+ * @{
+ */
+
+/** AES - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    __IO uint32_t CFG;                               /**< AES Configuration register, offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      union {                                          /* offset: 0x0 */
+        __IO uint16_t CFG0_15;                           /**< AES Configuration register 0:15, offset: 0x0 */
+        struct {                                         /* offset: 0x0 */
+          __IO uint8_t CFG0_7;                             /**< AES Configuration register 0:7, offset: 0x0 */
+          __IO uint8_t CFG8_15;                            /**< AES Configuration register 8:15, offset: 0x1 */
+        } CFGL;
+      };
+      __IO uint16_t CFG16_31;                          /**< AES Configuration register 16:31, offset: 0x2 */
+    } CFG0_32;
+  };
+  __IO uint32_t CMD;                               /**< AES Command register, offset: 0x4 */
+  __IO uint32_t STAT;                              /**< AES Status register, offset: 0x8 */
+  __IO uint32_t CTR_INCR;                          /**< Counter Increment, offset: 0xC */
+       uint8_t RESERVED_0[16];
+  __O  uint32_t KEY[8];                            /**< Bits of the AES key, array offset: 0x20, array step: 0x4 */
+  __O  uint32_t INTEXT[4];                         /**< Input text bits, array offset: 0x40, array step: 0x4 */
+  __O  uint32_t HOLDING[4];                        /**< Holding register bits, array offset: 0x50, array step: 0x4 */
+  __I  uint32_t OUTTEXT[4];                        /**< Output text bits, array offset: 0x60, array step: 0x4 */
+  __O  uint32_t GF128_Y[4];                        /**< Y bits input of GF128 hash, array offset: 0x70, array step: 0x4 */
+  __I  uint32_t GF128_Z[4];                        /**< Result bits of GF128 hash, array offset: 0x80, array step: 0x4 */
+  __I  uint32_t GCM_TAG[4];                        /**< GCM Tag bits, array offset: 0x90, array step: 0x4 */
+} AES_Type;
+
+/* ----------------------------------------------------------------------------
+   -- AES Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AES_Register_Masks AES Register Masks
+ * @{
+ */
+
+/*! @name CFG - AES Configuration register */
+/*! @{ */
+#define AES_CFG_PROC_EN_MASK                     (0x3U)
+#define AES_CFG_PROC_EN_SHIFT                    (0U)
+/*! PROC_EN - Process type enable.
+ */
+#define AES_CFG_PROC_EN(x)                       (((uint32_t)(((uint32_t)(x)) << AES_CFG_PROC_EN_SHIFT)) & AES_CFG_PROC_EN_MASK)
+#define AES_CFG_GF128_SEL_MASK                   (0x4U)
+#define AES_CFG_GF128_SEL_SHIFT                  (2U)
+/*! GF128_SEL - GF128 hash selection.
+ */
+#define AES_CFG_GF128_SEL(x)                     (((uint32_t)(((uint32_t)(x)) << AES_CFG_GF128_SEL_SHIFT)) & AES_CFG_GF128_SEL_MASK)
+#define AES_CFG_INTEXT_BSWAP_MASK                (0x10U)
+#define AES_CFG_INTEXT_BSWAP_SHIFT               (4U)
+/*! INTEXT_BSWAP - Byte swap input text.
+ */
+#define AES_CFG_INTEXT_BSWAP(x)                  (((uint32_t)(((uint32_t)(x)) << AES_CFG_INTEXT_BSWAP_SHIFT)) & AES_CFG_INTEXT_BSWAP_MASK)
+#define AES_CFG_INTEXT_WSWAP_MASK                (0x20U)
+#define AES_CFG_INTEXT_WSWAP_SHIFT               (5U)
+/*! INTEXT_WSWAP - Word swap input text.
+ */
+#define AES_CFG_INTEXT_WSWAP(x)                  (((uint32_t)(((uint32_t)(x)) << AES_CFG_INTEXT_WSWAP_SHIFT)) & AES_CFG_INTEXT_WSWAP_MASK)
+#define AES_CFG_OUTTEXT_BSWAP_MASK               (0x40U)
+#define AES_CFG_OUTTEXT_BSWAP_SHIFT              (6U)
+/*! OUTTEXT_BSWAP - Byte swap output text.
+ */
+#define AES_CFG_OUTTEXT_BSWAP(x)                 (((uint32_t)(((uint32_t)(x)) << AES_CFG_OUTTEXT_BSWAP_SHIFT)) & AES_CFG_OUTTEXT_BSWAP_MASK)
+#define AES_CFG_OUTTEXT_WSWAP_MASK               (0x80U)
+#define AES_CFG_OUTTEXT_WSWAP_SHIFT              (7U)
+/*! OUTTEXT_WSWAP - Word swap output text.
+ */
+#define AES_CFG_OUTTEXT_WSWAP(x)                 (((uint32_t)(((uint32_t)(x)) << AES_CFG_OUTTEXT_WSWAP_SHIFT)) & AES_CFG_OUTTEXT_WSWAP_MASK)
+#define AES_CFG_KEY_CFG_MASK                     (0x300U)
+#define AES_CFG_KEY_CFG_SHIFT                    (8U)
+/*! KEY_CFG - Key Configuration.
+ */
+#define AES_CFG_KEY_CFG(x)                       (((uint32_t)(((uint32_t)(x)) << AES_CFG_KEY_CFG_SHIFT)) & AES_CFG_KEY_CFG_MASK)
+#define AES_CFG_INBLK_SEL_MASK                   (0x30000U)
+#define AES_CFG_INBLK_SEL_SHIFT                  (16U)
+/*! INBLK_SEL - Input block select.
+ */
+#define AES_CFG_INBLK_SEL(x)                     (((uint32_t)(((uint32_t)(x)) << AES_CFG_INBLK_SEL_SHIFT)) & AES_CFG_INBLK_SEL_MASK)
+#define AES_CFG_HOLD_SEL_MASK                    (0x300000U)
+#define AES_CFG_HOLD_SEL_SHIFT                   (20U)
+/*! HOLD_SEL - Holding register source select.
+ */
+#define AES_CFG_HOLD_SEL(x)                      (((uint32_t)(((uint32_t)(x)) << AES_CFG_HOLD_SEL_SHIFT)) & AES_CFG_HOLD_SEL_MASK)
+#define AES_CFG_OUTTEXT_SEL_MASK                 (0x3000000U)
+#define AES_CFG_OUTTEXT_SEL_SHIFT                (24U)
+/*! OUTTEXT_SEL - Output text source select.
+ */
+#define AES_CFG_OUTTEXT_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << AES_CFG_OUTTEXT_SEL_SHIFT)) & AES_CFG_OUTTEXT_SEL_MASK)
+/*! @} */
+
+/*! @name CFG0_15 - AES Configuration register 0:15 */
+/*! @{ */
+#define AES_CFG0_15_PROC_EN_MASK                 (0x3U)
+#define AES_CFG0_15_PROC_EN_SHIFT                (0U)
+/*! PROC_EN - Process type enable.
+ */
+#define AES_CFG0_15_PROC_EN(x)                   (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_PROC_EN_SHIFT)) & AES_CFG0_15_PROC_EN_MASK)
+#define AES_CFG0_15_GF128_SEL_MASK               (0x4U)
+#define AES_CFG0_15_GF128_SEL_SHIFT              (2U)
+/*! GF128_SEL - GF128 hash selection.
+ */
+#define AES_CFG0_15_GF128_SEL(x)                 (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_GF128_SEL_SHIFT)) & AES_CFG0_15_GF128_SEL_MASK)
+#define AES_CFG0_15_INTEXT_BSWAP_MASK            (0x10U)
+#define AES_CFG0_15_INTEXT_BSWAP_SHIFT           (4U)
+/*! INTEXT_BSWAP - Byte swap input text.
+ */
+#define AES_CFG0_15_INTEXT_BSWAP(x)              (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_INTEXT_BSWAP_SHIFT)) & AES_CFG0_15_INTEXT_BSWAP_MASK)
+#define AES_CFG0_15_INTEXT_WSWAP_MASK            (0x20U)
+#define AES_CFG0_15_INTEXT_WSWAP_SHIFT           (5U)
+/*! INTEXT_WSWAP - Word swap input text.
+ */
+#define AES_CFG0_15_INTEXT_WSWAP(x)              (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_INTEXT_WSWAP_SHIFT)) & AES_CFG0_15_INTEXT_WSWAP_MASK)
+#define AES_CFG0_15_OUTTEXT_BSWAP_MASK           (0x40U)
+#define AES_CFG0_15_OUTTEXT_BSWAP_SHIFT          (6U)
+/*! OUTTEXT_BSWAP - Byte swap output text.
+ */
+#define AES_CFG0_15_OUTTEXT_BSWAP(x)             (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_OUTTEXT_BSWAP_SHIFT)) & AES_CFG0_15_OUTTEXT_BSWAP_MASK)
+#define AES_CFG0_15_OUTTEXT_WSWAP_MASK           (0x80U)
+#define AES_CFG0_15_OUTTEXT_WSWAP_SHIFT          (7U)
+/*! OUTTEXT_WSWAP - Word swap output text.
+ */
+#define AES_CFG0_15_OUTTEXT_WSWAP(x)             (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_OUTTEXT_WSWAP_SHIFT)) & AES_CFG0_15_OUTTEXT_WSWAP_MASK)
+#define AES_CFG0_15_KEY_CFG_MASK                 (0x300U)
+#define AES_CFG0_15_KEY_CFG_SHIFT                (8U)
+/*! KEY_CFG - Key Configuration.
+ */
+#define AES_CFG0_15_KEY_CFG(x)                   (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_KEY_CFG_SHIFT)) & AES_CFG0_15_KEY_CFG_MASK)
+/*! @} */
+
+/*! @name CFG0_7 - AES Configuration register 0:7 */
+/*! @{ */
+#define AES_CFG0_7_PROC_EN_MASK                  (0x3U)
+#define AES_CFG0_7_PROC_EN_SHIFT                 (0U)
+/*! PROC_EN - Process type enable.
+ */
+#define AES_CFG0_7_PROC_EN(x)                    (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_PROC_EN_SHIFT)) & AES_CFG0_7_PROC_EN_MASK)
+#define AES_CFG0_7_GF128_SEL_MASK                (0x4U)
+#define AES_CFG0_7_GF128_SEL_SHIFT               (2U)
+/*! GF128_SEL - GF128 hash selection.
+ */
+#define AES_CFG0_7_GF128_SEL(x)                  (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_GF128_SEL_SHIFT)) & AES_CFG0_7_GF128_SEL_MASK)
+#define AES_CFG0_7_INTEXT_BSWAP_MASK             (0x10U)
+#define AES_CFG0_7_INTEXT_BSWAP_SHIFT            (4U)
+/*! INTEXT_BSWAP - Byte swap input text.
+ */
+#define AES_CFG0_7_INTEXT_BSWAP(x)               (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_INTEXT_BSWAP_SHIFT)) & AES_CFG0_7_INTEXT_BSWAP_MASK)
+#define AES_CFG0_7_INTEXT_WSWAP_MASK             (0x20U)
+#define AES_CFG0_7_INTEXT_WSWAP_SHIFT            (5U)
+/*! INTEXT_WSWAP - Word swap input text.
+ */
+#define AES_CFG0_7_INTEXT_WSWAP(x)               (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_INTEXT_WSWAP_SHIFT)) & AES_CFG0_7_INTEXT_WSWAP_MASK)
+#define AES_CFG0_7_OUTTEXT_BSWAP_MASK            (0x40U)
+#define AES_CFG0_7_OUTTEXT_BSWAP_SHIFT           (6U)
+/*! OUTTEXT_BSWAP - Byte swap output text.
+ */
+#define AES_CFG0_7_OUTTEXT_BSWAP(x)              (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_OUTTEXT_BSWAP_SHIFT)) & AES_CFG0_7_OUTTEXT_BSWAP_MASK)
+#define AES_CFG0_7_OUTTEXT_WSWAP_MASK            (0x80U)
+#define AES_CFG0_7_OUTTEXT_WSWAP_SHIFT           (7U)
+/*! OUTTEXT_WSWAP - Word swap output text.
+ */
+#define AES_CFG0_7_OUTTEXT_WSWAP(x)              (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_OUTTEXT_WSWAP_SHIFT)) & AES_CFG0_7_OUTTEXT_WSWAP_MASK)
+/*! @} */
+
+/*! @name CFG8_15 - AES Configuration register 8:15 */
+/*! @{ */
+#define AES_CFG8_15_KEY_CFG_MASK                 (0x3U)
+#define AES_CFG8_15_KEY_CFG_SHIFT                (0U)
+/*! KEY_CFG - Key Configuration.
+ */
+#define AES_CFG8_15_KEY_CFG(x)                   (((uint8_t)(((uint8_t)(x)) << AES_CFG8_15_KEY_CFG_SHIFT)) & AES_CFG8_15_KEY_CFG_MASK)
+/*! @} */
+
+/*! @name CFG16_31 - AES Configuration register 16:31 */
+/*! @{ */
+#define AES_CFG16_31_INBLK_SEL_MASK              (0x3U)
+#define AES_CFG16_31_INBLK_SEL_SHIFT             (0U)
+/*! INBLK_SEL - Input block select.
+ */
+#define AES_CFG16_31_INBLK_SEL(x)                (((uint16_t)(((uint16_t)(x)) << AES_CFG16_31_INBLK_SEL_SHIFT)) & AES_CFG16_31_INBLK_SEL_MASK)
+#define AES_CFG16_31_HOLD_SEL_MASK               (0x30U)
+#define AES_CFG16_31_HOLD_SEL_SHIFT              (4U)
+/*! HOLD_SEL - Holding register source select.
+ */
+#define AES_CFG16_31_HOLD_SEL(x)                 (((uint16_t)(((uint16_t)(x)) << AES_CFG16_31_HOLD_SEL_SHIFT)) & AES_CFG16_31_HOLD_SEL_MASK)
+#define AES_CFG16_31_OUTTEXT_SEL_MASK            (0x300U)
+#define AES_CFG16_31_OUTTEXT_SEL_SHIFT           (8U)
+/*! OUTTEXT_SEL - Output text source select.
+ */
+#define AES_CFG16_31_OUTTEXT_SEL(x)              (((uint16_t)(((uint16_t)(x)) << AES_CFG16_31_OUTTEXT_SEL_SHIFT)) & AES_CFG16_31_OUTTEXT_SEL_MASK)
+/*! @} */
+
+/*! @name CMD - AES Command register */
+/*! @{ */
+#define AES_CMD_COPY_TO_Y_MASK                   (0x2U)
+#define AES_CMD_COPY_TO_Y_SHIFT                  (1U)
+/*! COPY_TO_Y - Copy output text to GF128Y.
+ */
+#define AES_CMD_COPY_TO_Y(x)                     (((uint32_t)(((uint32_t)(x)) << AES_CMD_COPY_TO_Y_SHIFT)) & AES_CMD_COPY_TO_Y_MASK)
+#define AES_CMD_SWITCH_MODE_MASK                 (0x10U)
+#define AES_CMD_SWITCH_MODE_SHIFT                (4U)
+/*! SWITCH_MODE - When this bit is set the mode switches from forward mode (encryption) to reverse
+ *    mode (decryption) or reverse mode to forward mode.
+ */
+#define AES_CMD_SWITCH_MODE(x)                   (((uint32_t)(((uint32_t)(x)) << AES_CMD_SWITCH_MODE_SHIFT)) & AES_CMD_SWITCH_MODE_MASK)
+#define AES_CMD_ABORT_MASK                       (0x100U)
+#define AES_CMD_ABORT_SHIFT                      (8U)
+/*! ABORT - Aborts Encrypt/Decrypt and GF128 Hash operation.
+ */
+#define AES_CMD_ABORT(x)                         (((uint32_t)(((uint32_t)(x)) << AES_CMD_ABORT_SHIFT)) & AES_CMD_ABORT_MASK)
+#define AES_CMD_WIPE_MASK                        (0x200U)
+#define AES_CMD_WIPE_SHIFT                       (9U)
+/*! WIPE - When set this bit performs abort, clears KEY and GF128_Y registers and disables cipher.
+ */
+#define AES_CMD_WIPE(x)                          (((uint32_t)(((uint32_t)(x)) << AES_CMD_WIPE_SHIFT)) & AES_CMD_WIPE_MASK)
+/*! @} */
+
+/*! @name STAT - AES Status register */
+/*! @{ */
+#define AES_STAT_IDLE_MASK                       (0x1U)
+#define AES_STAT_IDLE_SHIFT                      (0U)
+/*! IDLE - AES engine Idle.
+ */
+#define AES_STAT_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << AES_STAT_IDLE_SHIFT)) & AES_STAT_IDLE_MASK)
+#define AES_STAT_IN_READY_MASK                   (0x2U)
+#define AES_STAT_IN_READY_SHIFT                  (1U)
+/*! IN_READY - Input text ready.
+ */
+#define AES_STAT_IN_READY(x)                     (((uint32_t)(((uint32_t)(x)) << AES_STAT_IN_READY_SHIFT)) & AES_STAT_IN_READY_MASK)
+#define AES_STAT_OUT_READY_MASK                  (0x4U)
+#define AES_STAT_OUT_READY_SHIFT                 (2U)
+/*! OUT_READY - Output text ready.
+ */
+#define AES_STAT_OUT_READY(x)                    (((uint32_t)(((uint32_t)(x)) << AES_STAT_OUT_READY_SHIFT)) & AES_STAT_OUT_READY_MASK)
+#define AES_STAT_REVERSE_MASK                    (0x10U)
+#define AES_STAT_REVERSE_SHIFT                   (4U)
+/*! REVERSE - Reverse mode.
+ */
+#define AES_STAT_REVERSE(x)                      (((uint32_t)(((uint32_t)(x)) << AES_STAT_REVERSE_SHIFT)) & AES_STAT_REVERSE_MASK)
+#define AES_STAT_KEY_VALID_MASK                  (0x20U)
+#define AES_STAT_KEY_VALID_SHIFT                 (5U)
+/*! KEY_VALID - Key valid.
+ */
+#define AES_STAT_KEY_VALID(x)                    (((uint32_t)(((uint32_t)(x)) << AES_STAT_KEY_VALID_SHIFT)) & AES_STAT_KEY_VALID_MASK)
+/*! @} */
+
+/*! @name CTR_INCR - Counter Increment */
+/*! @{ */
+#define AES_CTR_INCR_CTR_INCR_MASK               (0xFFFFFFFFU)
+#define AES_CTR_INCR_CTR_INCR_SHIFT              (0U)
+/*! CTR_INCR - Increment value for HOLDING register when in counter modes.
+ */
+#define AES_CTR_INCR_CTR_INCR(x)                 (((uint32_t)(((uint32_t)(x)) << AES_CTR_INCR_CTR_INCR_SHIFT)) & AES_CTR_INCR_CTR_INCR_MASK)
+/*! @} */
+
+/*! @name KEY - Bits of the AES key */
+/*! @{ */
+#define AES_KEY_KEY_MASK                         (0xFFFFFFFFU)
+#define AES_KEY_KEY_SHIFT                        (0U)
+/*! KEY - Contains the bits of the AES key.
+ */
+#define AES_KEY_KEY(x)                           (((uint32_t)(((uint32_t)(x)) << AES_KEY_KEY_SHIFT)) & AES_KEY_KEY_MASK)
+/*! @} */
+
+/* The count of AES_KEY */
+#define AES_KEY_COUNT                            (8U)
+
+/*! @name INTEXT - Input text bits */
+/*! @{ */
+#define AES_INTEXT_INTEXT_MASK                   (0xFFFFFFFFU)
+#define AES_INTEXT_INTEXT_SHIFT                  (0U)
+/*! INTEXT - Contains bits of the AES key.
+ */
+#define AES_INTEXT_INTEXT(x)                     (((uint32_t)(((uint32_t)(x)) << AES_INTEXT_INTEXT_SHIFT)) & AES_INTEXT_INTEXT_MASK)
+/*! @} */
+
+/* The count of AES_INTEXT */
+#define AES_INTEXT_COUNT                         (4U)
+
+/*! @name HOLDING - Holding register bits */
+/*! @{ */
+#define AES_HOLDING_HOLDING_MASK                 (0xFFFFFFFFU)
+#define AES_HOLDING_HOLDING_SHIFT                (0U)
+/*! HOLDING - Contains the first word (bits 31:0) of the 128 bit Holding value.
+ */
+#define AES_HOLDING_HOLDING(x)                   (((uint32_t)(((uint32_t)(x)) << AES_HOLDING_HOLDING_SHIFT)) & AES_HOLDING_HOLDING_MASK)
+/*! @} */
+
+/* The count of AES_HOLDING */
+#define AES_HOLDING_COUNT                        (4U)
+
+/*! @name OUTTEXT - Output text bits */
+/*! @{ */
+#define AES_OUTTEXT_OUTTEXT_MASK                 (0xFFFFFFFFU)
+#define AES_OUTTEXT_OUTTEXT_SHIFT                (0U)
+/*! OUTTEXT - Contains the bits of the 128 bit Output text data.
+ */
+#define AES_OUTTEXT_OUTTEXT(x)                   (((uint32_t)(((uint32_t)(x)) << AES_OUTTEXT_OUTTEXT_SHIFT)) & AES_OUTTEXT_OUTTEXT_MASK)
+/*! @} */
+
+/* The count of AES_OUTTEXT */
+#define AES_OUTTEXT_COUNT                        (4U)
+
+/*! @name GF128_Y - Y bits input of GF128 hash */
+/*! @{ */
+#define AES_GF128_Y_GF128_Y_MASK                 (0xFFFFFFFFU)
+#define AES_GF128_Y_GF128_Y_SHIFT                (0U)
+/*! GF128_Y - Contains the bits of the Y input of GF128 hash.
+ */
+#define AES_GF128_Y_GF128_Y(x)                   (((uint32_t)(((uint32_t)(x)) << AES_GF128_Y_GF128_Y_SHIFT)) & AES_GF128_Y_GF128_Y_MASK)
+/*! @} */
+
+/* The count of AES_GF128_Y */
+#define AES_GF128_Y_COUNT                        (4U)
+
+/*! @name GF128_Z - Result bits of GF128 hash */
+/*! @{ */
+#define AES_GF128_Z_GF128_Z_MASK                 (0xFFFFFFFFU)
+#define AES_GF128_Z_GF128_Z_SHIFT                (0U)
+/*! GF128_Z - Contains bits of the result of GF128 hash.
+ */
+#define AES_GF128_Z_GF128_Z(x)                   (((uint32_t)(((uint32_t)(x)) << AES_GF128_Z_GF128_Z_SHIFT)) & AES_GF128_Z_GF128_Z_MASK)
+/*! @} */
+
+/* The count of AES_GF128_Z */
+#define AES_GF128_Z_COUNT                        (4U)
+
+/*! @name GCM_TAG - GCM Tag bits */
+/*! @{ */
+#define AES_GCM_TAG_GCM_TAG_MASK                 (0xFFFFFFFFU)
+#define AES_GCM_TAG_GCM_TAG_SHIFT                (0U)
+/*! GCM_TAG - Contains bits of the 128 bit GCM tag.
+ */
+#define AES_GCM_TAG_GCM_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << AES_GCM_TAG_GCM_TAG_SHIFT)) & AES_GCM_TAG_GCM_TAG_MASK)
+/*! @} */
+
+/* The count of AES_GCM_TAG */
+#define AES_GCM_TAG_COUNT                        (4U)
+
+
+/*!
+ * @}
+ */ /* end of group AES_Register_Masks */
+
+
+/* AES - Peripheral instance base addresses */
+/** Peripheral AES0 base address */
+#define AES0_BASE                                (0x400A1000u)
+/** Peripheral AES0 base pointer */
+#define AES0                                     ((AES_Type *)AES0_BASE)
+/** Array initializer of AES peripheral base addresses */
+#define AES_BASE_ADDRS                           { AES0_BASE }
+/** Array initializer of AES peripheral base pointers */
+#define AES_BASE_PTRS                            { AES0 }
+
+/*!
+ * @}
+ */ /* end of group AES_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ASYNC_SYSCON Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
+ * @{
+ */
+
+/** ASYNC_SYSCON - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t ASYNCPRESETCTRL;                   /**< Async peripheral reset control, offset: 0x0 */
+  __O  uint32_t ASYNCPRESETCTRLSET;                /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
+  __O  uint32_t ASYNCPRESETCTRLCLR;                /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ASYNCAPBCLKCTRL;                   /**< Async peripheral clock control, offset: 0x10 */
+  __O  uint32_t ASYNCAPBCLKCTRLSET;                /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
+  __O  uint32_t ASYNCAPBCLKCTRLCLR;                /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t ASYNCAPBCLKSELA;                   /**< Async APB clock source select A, offset: 0x20 */
+} ASYNC_SYSCON_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ASYNC_SYSCON Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
+ * @{
+ */
+
+/*! @name ASYNCPRESETCTRL - Async peripheral reset control */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
+/*! CTIMER3 - Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
+/*! CTIMER4 - Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
+/*! @} */
+
+/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
+/*! ARST_SET - Writing ones to this register sets the corresponding bit or bits in the
+ *    ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ *    ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
+/*! @} */
+
+/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
+/*! ARST_CLR - Writing ones to this register clears the corresponding bit or bits in the
+ *    ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ *    ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
+/*! CTIMER3 - Controls the clock for CTIMER3. 0 = Disable; 1 = Enable.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
+/*! CTIMER4 - Controls the clock for CTIMER4. 0 = Disable; 1 = Enable.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
+/*! ACLK_SET - Writing ones to this register sets the corresponding bit or bits in the
+ *    ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ *    ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
+/*! ACLK_CLR - Writing ones to this register clears the corresponding bit or bits in the
+ *    ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ *    ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK    (0x3U)
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT   (0U)
+/*! SEL - Clock source for asynchronous clock source selector A
+ *  0b00..Main clock (main_clk)
+ *  0b01..FRO 12 MHz (fro_12m)
+ *  0b10..Audio PLL clock.(AUDPLL_BYPASS)
+ *  0b11..fc6 fclk (fc6_fclk)
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x)      (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ASYNC_SYSCON_Register_Masks */
+
+
+/* ASYNC_SYSCON - Peripheral instance base addresses */
+/** Peripheral ASYNC_SYSCON base address */
+#define ASYNC_SYSCON_BASE                        (0x40040000u)
+/** Peripheral ASYNC_SYSCON base pointer */
+#define ASYNC_SYSCON                             ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
+/** Array initializer of ASYNC_SYSCON peripheral base addresses */
+#define ASYNC_SYSCON_BASE_ADDRS                  { ASYNC_SYSCON_BASE }
+/** Array initializer of ASYNC_SYSCON peripheral base pointers */
+#define ASYNC_SYSCON_BASE_PTRS                   { ASYNC_SYSCON }
+
+/*!
+ * @}
+ */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MODE;                              /**< CRC mode register, offset: 0x0 */
+  __IO uint32_t SEED;                              /**< CRC seed register, offset: 0x4 */
+  union {                                          /* offset: 0x8 */
+    __I  uint32_t SUM;                               /**< CRC checksum register, offset: 0x8 */
+    __O  uint32_t WR_DATA;                           /**< CRC data register, offset: 0x8 */
+  };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name MODE - CRC mode register */
+/*! @{ */
+#define CRC_MODE_CRC_POLY_MASK                   (0x3U)
+#define CRC_MODE_CRC_POLY_SHIFT                  (0U)
+/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
+ */
+#define CRC_MODE_CRC_POLY(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
+#define CRC_MODE_BIT_RVS_WR_MASK                 (0x4U)
+#define CRC_MODE_BIT_RVS_WR_SHIFT                (2U)
+/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
+ */
+#define CRC_MODE_BIT_RVS_WR(x)                   (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
+#define CRC_MODE_CMPL_WR_MASK                    (0x8U)
+#define CRC_MODE_CMPL_WR_SHIFT                   (3U)
+/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
+ */
+#define CRC_MODE_CMPL_WR(x)                      (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
+#define CRC_MODE_BIT_RVS_SUM_MASK                (0x10U)
+#define CRC_MODE_BIT_RVS_SUM_SHIFT               (4U)
+/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
+ */
+#define CRC_MODE_BIT_RVS_SUM(x)                  (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
+#define CRC_MODE_CMPL_SUM_MASK                   (0x20U)
+#define CRC_MODE_CMPL_SUM_SHIFT                  (5U)
+/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
+ */
+#define CRC_MODE_CMPL_SUM(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
+/*! @} */
+
+/*! @name SEED - CRC seed register */
+/*! @{ */
+#define CRC_SEED_CRC_SEED_MASK                   (0xFFFFFFFFU)
+#define CRC_SEED_CRC_SEED_SHIFT                  (0U)
+/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
+ *    selected bit order and 1's complement pre-processes. A write access to this register will
+ *    overrule the CRC calculation in progresses.
+ */
+#define CRC_SEED_CRC_SEED(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
+/*! @} */
+
+/*! @name SUM - CRC checksum register */
+/*! @{ */
+#define CRC_SUM_CRC_SUM_MASK                     (0xFFFFFFFFU)
+#define CRC_SUM_CRC_SUM_SHIFT                    (0U)
+/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
+ */
+#define CRC_SUM_CRC_SUM(x)                       (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
+/*! @} */
+
+/*! @name WR_DATA - CRC data register */
+/*! @{ */
+#define CRC_WR_DATA_CRC_WR_DATA_MASK             (0xFFFFFFFFU)
+#define CRC_WR_DATA_CRC_WR_DATA_SHIFT            (0U)
+/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
+ *    selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
+ *    accept back-to-back transactions.
+ */
+#define CRC_WR_DATA_CRC_WR_DATA(x)               (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC_ENGINE base address */
+#define CRC_ENGINE_BASE                          (0x40095000u)
+/** Peripheral CRC_ENGINE base pointer */
+#define CRC_ENGINE                               ((CRC_Type *)CRC_ENGINE_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC_ENGINE_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC_ENGINE }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CTIMER Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
+ * @{
+ */
+
+/** CTIMER - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t IR;                                /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
+  __IO uint32_t TCR;                               /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
+  __IO uint32_t TC;                                /**< Timer Counter, offset: 0x8 */
+  __IO uint32_t PR;                                /**< Prescale Register, offset: 0xC */
+  __IO uint32_t PC;                                /**< Prescale Counter, offset: 0x10 */
+  __IO uint32_t MCR;                               /**< Match Control Register, offset: 0x14 */
+  __IO uint32_t MR[4];                             /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
+  __IO uint32_t CCR;                               /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
+  __I  uint32_t CR[4];                             /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
+  __IO uint32_t EMR;                               /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
+       uint8_t RESERVED_0[48];
+  __IO uint32_t CTCR;                              /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
+  __IO uint32_t PWMC;                              /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
+  __IO uint32_t MSR[4];                            /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
+} CTIMER_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CTIMER Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
+ * @{
+ */
+
+/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+/*! @{ */
+#define CTIMER_IR_MR0INT_MASK                    (0x1U)
+#define CTIMER_IR_MR0INT_SHIFT                   (0U)
+/*! MR0INT - Interrupt flag for match channel 0.
+ */
+#define CTIMER_IR_MR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
+#define CTIMER_IR_MR1INT_MASK                    (0x2U)
+#define CTIMER_IR_MR1INT_SHIFT                   (1U)
+/*! MR1INT - Interrupt flag for match channel 1.
+ */
+#define CTIMER_IR_MR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
+#define CTIMER_IR_MR2INT_MASK                    (0x4U)
+#define CTIMER_IR_MR2INT_SHIFT                   (2U)
+/*! MR2INT - Interrupt flag for match channel 2.
+ */
+#define CTIMER_IR_MR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
+#define CTIMER_IR_MR3INT_MASK                    (0x8U)
+#define CTIMER_IR_MR3INT_SHIFT                   (3U)
+/*! MR3INT - Interrupt flag for match channel 3.
+ */
+#define CTIMER_IR_MR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
+#define CTIMER_IR_CR0INT_MASK                    (0x10U)
+#define CTIMER_IR_CR0INT_SHIFT                   (4U)
+/*! CR0INT - Interrupt flag for capture channel 0 event.
+ */
+#define CTIMER_IR_CR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
+#define CTIMER_IR_CR1INT_MASK                    (0x20U)
+#define CTIMER_IR_CR1INT_SHIFT                   (5U)
+/*! CR1INT - Interrupt flag for capture channel 1 event.
+ */
+#define CTIMER_IR_CR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
+#define CTIMER_IR_CR2INT_MASK                    (0x40U)
+#define CTIMER_IR_CR2INT_SHIFT                   (6U)
+/*! CR2INT - Interrupt flag for capture channel 2 event.
+ */
+#define CTIMER_IR_CR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
+#define CTIMER_IR_CR3INT_MASK                    (0x80U)
+#define CTIMER_IR_CR3INT_SHIFT                   (7U)
+/*! CR3INT - Interrupt flag for capture channel 3 event.
+ */
+#define CTIMER_IR_CR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
+/*! @} */
+
+/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+/*! @{ */
+#define CTIMER_TCR_CEN_MASK                      (0x1U)
+#define CTIMER_TCR_CEN_SHIFT                     (0U)
+/*! CEN - Counter enable.
+ *  0b0..Disabled.The counters are disabled.
+ *  0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
+ */
+#define CTIMER_TCR_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
+#define CTIMER_TCR_CRST_MASK                     (0x2U)
+#define CTIMER_TCR_CRST_SHIFT                    (1U)
+/*! CRST - Counter reset.
+ *  0b0..Disabled. Do nothing.
+ *  0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
+ *       the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
+ */
+#define CTIMER_TCR_CRST(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
+/*! @} */
+
+/*! @name TC - Timer Counter */
+/*! @{ */
+#define CTIMER_TC_TCVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_TC_TCVAL_SHIFT                    (0U)
+/*! TCVAL - Timer counter value.
+ */
+#define CTIMER_TC_TCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
+/*! @} */
+
+/*! @name PR - Prescale Register */
+/*! @{ */
+#define CTIMER_PR_PRVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_PR_PRVAL_SHIFT                    (0U)
+/*! PRVAL - Prescale counter value.
+ */
+#define CTIMER_PR_PRVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
+/*! @} */
+
+/*! @name PC - Prescale Counter */
+/*! @{ */
+#define CTIMER_PC_PCVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_PC_PCVAL_SHIFT                    (0U)
+/*! PCVAL - Prescale counter value.
+ */
+#define CTIMER_PC_PCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
+/*! @} */
+
+/*! @name MCR - Match Control Register */
+/*! @{ */
+#define CTIMER_MCR_MR0I_MASK                     (0x1U)
+#define CTIMER_MCR_MR0I_SHIFT                    (0U)
+/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR0I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
+#define CTIMER_MCR_MR0R_MASK                     (0x2U)
+#define CTIMER_MCR_MR0R_SHIFT                    (1U)
+/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it.
+ */
+#define CTIMER_MCR_MR0R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
+#define CTIMER_MCR_MR0S_MASK                     (0x4U)
+#define CTIMER_MCR_MR0S_SHIFT                    (2U)
+/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
+ */
+#define CTIMER_MCR_MR0S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
+#define CTIMER_MCR_MR1I_MASK                     (0x8U)
+#define CTIMER_MCR_MR1I_SHIFT                    (3U)
+/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR1I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
+#define CTIMER_MCR_MR1R_MASK                     (0x10U)
+#define CTIMER_MCR_MR1R_SHIFT                    (4U)
+/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it.
+ */
+#define CTIMER_MCR_MR1R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
+#define CTIMER_MCR_MR1S_MASK                     (0x20U)
+#define CTIMER_MCR_MR1S_SHIFT                    (5U)
+/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
+ */
+#define CTIMER_MCR_MR1S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
+#define CTIMER_MCR_MR2I_MASK                     (0x40U)
+#define CTIMER_MCR_MR2I_SHIFT                    (6U)
+/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR2I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
+#define CTIMER_MCR_MR2R_MASK                     (0x80U)
+#define CTIMER_MCR_MR2R_SHIFT                    (7U)
+/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it.
+ */
+#define CTIMER_MCR_MR2R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
+#define CTIMER_MCR_MR2S_MASK                     (0x100U)
+#define CTIMER_MCR_MR2S_SHIFT                    (8U)
+/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
+ */
+#define CTIMER_MCR_MR2S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
+#define CTIMER_MCR_MR3I_MASK                     (0x200U)
+#define CTIMER_MCR_MR3I_SHIFT                    (9U)
+/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR3I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
+#define CTIMER_MCR_MR3R_MASK                     (0x400U)
+#define CTIMER_MCR_MR3R_SHIFT                    (10U)
+/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it.
+ */
+#define CTIMER_MCR_MR3R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
+#define CTIMER_MCR_MR3S_MASK                     (0x800U)
+#define CTIMER_MCR_MR3S_SHIFT                    (11U)
+/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
+ */
+#define CTIMER_MCR_MR3S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
+#define CTIMER_MCR_MR0RL_MASK                    (0x1000000U)
+#define CTIMER_MCR_MR0RL_SHIFT                   (24U)
+/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
+ *    (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR0RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
+#define CTIMER_MCR_MR1RL_MASK                    (0x2000000U)
+#define CTIMER_MCR_MR1RL_SHIFT                   (25U)
+/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
+ *    (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR1RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
+#define CTIMER_MCR_MR2RL_MASK                    (0x4000000U)
+#define CTIMER_MCR_MR2RL_SHIFT                   (26U)
+/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
+ *    (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR2RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
+#define CTIMER_MCR_MR3RL_MASK                    (0x8000000U)
+#define CTIMER_MCR_MR3RL_SHIFT                   (27U)
+/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
+ *    (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR3RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
+/*! @} */
+
+/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+/*! @{ */
+#define CTIMER_MR_MATCH_MASK                     (0xFFFFFFFFU)
+#define CTIMER_MR_MATCH_SHIFT                    (0U)
+/*! MATCH - Timer counter match value.
+ */
+#define CTIMER_MR_MATCH(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
+/*! @} */
+
+/* The count of CTIMER_MR */
+#define CTIMER_MR_COUNT                          (4U)
+
+/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+/*! @{ */
+#define CTIMER_CCR_CAP0RE_MASK                   (0x1U)
+#define CTIMER_CCR_CAP0RE_SHIFT                  (0U)
+/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP0RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
+#define CTIMER_CCR_CAP0FE_MASK                   (0x2U)
+#define CTIMER_CCR_CAP0FE_SHIFT                  (1U)
+/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP0FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
+#define CTIMER_CCR_CAP0I_MASK                    (0x4U)
+#define CTIMER_CCR_CAP0I_SHIFT                   (2U)
+/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP0I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
+#define CTIMER_CCR_CAP1RE_MASK                   (0x8U)
+#define CTIMER_CCR_CAP1RE_SHIFT                  (3U)
+/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP1RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
+#define CTIMER_CCR_CAP1FE_MASK                   (0x10U)
+#define CTIMER_CCR_CAP1FE_SHIFT                  (4U)
+/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP1FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
+#define CTIMER_CCR_CAP1I_MASK                    (0x20U)
+#define CTIMER_CCR_CAP1I_SHIFT                   (5U)
+/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP1I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
+#define CTIMER_CCR_CAP2RE_MASK                   (0x40U)
+#define CTIMER_CCR_CAP2RE_SHIFT                  (6U)
+/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP2RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
+#define CTIMER_CCR_CAP2FE_MASK                   (0x80U)
+#define CTIMER_CCR_CAP2FE_SHIFT                  (7U)
+/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP2FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
+#define CTIMER_CCR_CAP2I_MASK                    (0x100U)
+#define CTIMER_CCR_CAP2I_SHIFT                   (8U)
+/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP2I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
+#define CTIMER_CCR_CAP3RE_MASK                   (0x200U)
+#define CTIMER_CCR_CAP3RE_SHIFT                  (9U)
+/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP3RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
+#define CTIMER_CCR_CAP3FE_MASK                   (0x400U)
+#define CTIMER_CCR_CAP3FE_SHIFT                  (10U)
+/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP3FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
+#define CTIMER_CCR_CAP3I_MASK                    (0x800U)
+#define CTIMER_CCR_CAP3I_SHIFT                   (11U)
+/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP3I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
+/*! @} */
+
+/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
+/*! @{ */
+#define CTIMER_CR_CAP_MASK                       (0xFFFFFFFFU)
+#define CTIMER_CR_CAP_SHIFT                      (0U)
+/*! CAP - Timer counter capture value.
+ */
+#define CTIMER_CR_CAP(x)                         (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
+/*! @} */
+
+/* The count of CTIMER_CR */
+#define CTIMER_CR_COUNT                          (4U)
+
+/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
+/*! @{ */
+#define CTIMER_EMR_EM0_MASK                      (0x1U)
+#define CTIMER_EMR_EM0_SHIFT                     (0U)
+/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
+ *    is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
+ *    go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
+ *    the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM0(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
+#define CTIMER_EMR_EM1_MASK                      (0x2U)
+#define CTIMER_EMR_EM1_SHIFT                     (1U)
+/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
+ *    is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
+ *    go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
+ *    the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM1(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
+#define CTIMER_EMR_EM2_MASK                      (0x4U)
+#define CTIMER_EMR_EM2_SHIFT                     (2U)
+/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
+ *    is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
+ *    go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
+ *    the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM2(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
+#define CTIMER_EMR_EM3_MASK                      (0x8U)
+#define CTIMER_EMR_EM3_SHIFT                     (3U)
+/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
+ *    is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
+ *    go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
+ *    if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM3(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
+#define CTIMER_EMR_EMC0_MASK                     (0x30U)
+#define CTIMER_EMR_EMC0_SHIFT                    (4U)
+/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC0(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
+#define CTIMER_EMR_EMC1_MASK                     (0xC0U)
+#define CTIMER_EMR_EMC1_SHIFT                    (6U)
+/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC1(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
+#define CTIMER_EMR_EMC2_MASK                     (0x300U)
+#define CTIMER_EMR_EMC2_SHIFT                    (8U)
+/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC2(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
+#define CTIMER_EMR_EMC3_MASK                     (0xC00U)
+#define CTIMER_EMR_EMC3_SHIFT                    (10U)
+/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC3(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
+/*! @} */
+
+/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+/*! @{ */
+#define CTIMER_CTCR_CTMODE_MASK                  (0x3U)
+#define CTIMER_CTCR_CTMODE_SHIFT                 (0U)
+/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
+ *    Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
+ *    is incremented when the Prescale Counter matches the Prescale Register.
+ *  0b00..Timer Mode. Incremented every rising APB bus clock edge.
+ *  0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
+ *  0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
+ *  0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
+ */
+#define CTIMER_CTCR_CTMODE(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
+#define CTIMER_CTCR_CINSEL_MASK                  (0xCU)
+#define CTIMER_CTCR_CINSEL_SHIFT                 (2U)
+/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
+ *    CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
+ *    in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
+ *    programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
+ *    same timer.
+ *  0b00..Channel 0. CAPn.0 for CTIMERn
+ *  0b01..Channel 1. CAPn.1 for CTIMERn
+ *  0b10..Channel 2. CAPn.2 for CTIMERn
+ *  0b11..Channel 3. CAPn.3 for CTIMERn
+ */
+#define CTIMER_CTCR_CINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
+#define CTIMER_CTCR_ENCC_MASK                    (0x10U)
+#define CTIMER_CTCR_ENCC_SHIFT                   (4U)
+/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
+ *    capture-edge event specified in bits 7:5 occurs.
+ */
+#define CTIMER_CTCR_ENCC(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
+#define CTIMER_CTCR_SELCC_MASK                   (0xE0U)
+#define CTIMER_CTCR_SELCC_SHIFT                  (5U)
+/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
+ *    timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
+ *    0x3 and 0x6 to 0x7 are reserved.
+ *  0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
+ *  0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
+ *  0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
+ *  0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
+ *  0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
+ *  0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
+ */
+#define CTIMER_CTCR_SELCC(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
+/*! @} */
+
+/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
+/*! @{ */
+#define CTIMER_PWMC_PWMEN0_MASK                  (0x1U)
+#define CTIMER_PWMC_PWMEN0_SHIFT                 (0U)
+/*! PWMEN0 - PWM mode enable for channel0.
+ *  0b0..Match. CTIMERn_MAT0 is controlled by EM0.
+ *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
+ */
+#define CTIMER_PWMC_PWMEN0(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
+#define CTIMER_PWMC_PWMEN1_MASK                  (0x2U)
+#define CTIMER_PWMC_PWMEN1_SHIFT                 (1U)
+/*! PWMEN1 - PWM mode enable for channel1.
+ *  0b0..Match. CTIMERn_MAT01 is controlled by EM1.
+ *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
+ */
+#define CTIMER_PWMC_PWMEN1(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
+#define CTIMER_PWMC_PWMEN2_MASK                  (0x4U)
+#define CTIMER_PWMC_PWMEN2_SHIFT                 (2U)
+/*! PWMEN2 - PWM mode enable for channel2.
+ *  0b0..Match. CTIMERn_MAT2 is controlled by EM2.
+ *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
+ */
+#define CTIMER_PWMC_PWMEN2(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
+#define CTIMER_PWMC_PWMEN3_MASK                  (0x8U)
+#define CTIMER_PWMC_PWMEN3_SHIFT                 (3U)
+/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
+ *  0b0..Match. CTIMERn_MAT3 is controlled by EM3.
+ *  0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
+ */
+#define CTIMER_PWMC_PWMEN3(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
+/*! @} */
+
+/*! @name MSR - Match Shadow Register */
+/*! @{ */
+#define CTIMER_MSR_SHADOWW_MASK                  (0xFFFFFFFFU)
+#define CTIMER_MSR_SHADOWW_SHIFT                 (0U)
+/*! SHADOWW - Timer counter match shadow value.
+ */
+#define CTIMER_MSR_SHADOWW(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)
+/*! @} */
+
+/* The count of CTIMER_MSR */
+#define CTIMER_MSR_COUNT                         (4U)
+
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Register_Masks */
+
+
+/* CTIMER - Peripheral instance base addresses */
+/** Peripheral CTIMER0 base address */
+#define CTIMER0_BASE                             (0x40008000u)
+/** Peripheral CTIMER0 base pointer */
+#define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
+/** Peripheral CTIMER1 base address */
+#define CTIMER1_BASE                             (0x40009000u)
+/** Peripheral CTIMER1 base pointer */
+#define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
+/** Peripheral CTIMER2 base address */
+#define CTIMER2_BASE                             (0x40028000u)
+/** Peripheral CTIMER2 base pointer */
+#define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
+/** Peripheral CTIMER3 base address */
+#define CTIMER3_BASE                             (0x40048000u)
+/** Peripheral CTIMER3 base pointer */
+#define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
+/** Peripheral CTIMER4 base address */
+#define CTIMER4_BASE                             (0x40049000u)
+/** Peripheral CTIMER4 base pointer */
+#define CTIMER4                                  ((CTIMER_Type *)CTIMER4_BASE)
+/** Array initializer of CTIMER peripheral base addresses */
+#define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
+/** Array initializer of CTIMER peripheral base pointers */
+#define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
+/** Interrupt vectors for the CTIMER peripheral type */
+#define CTIMER_IRQS                              { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< DMA control., offset: 0x0 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt status., offset: 0x4 */
+  __IO uint32_t SRAMBASE;                          /**< SRAM address of the channel configuration table., offset: 0x8 */
+       uint8_t RESERVED_0[20];
+  struct {                                         /* offset: 0x20, array step: 0x5C */
+    __IO uint32_t ENABLESET;                         /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
+         uint8_t RESERVED_0[4];
+    __O  uint32_t ENABLECLR;                         /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
+         uint8_t RESERVED_1[4];
+    __I  uint32_t ACTIVE;                            /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
+         uint8_t RESERVED_2[4];
+    __I  uint32_t BUSY;                              /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
+         uint8_t RESERVED_3[4];
+    __IO uint32_t ERRINT;                            /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
+         uint8_t RESERVED_4[4];
+    __IO uint32_t INTENSET;                          /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
+         uint8_t RESERVED_5[4];
+    __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
+         uint8_t RESERVED_6[4];
+    __IO uint32_t INTA;                              /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
+         uint8_t RESERVED_7[4];
+    __IO uint32_t INTB;                              /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
+         uint8_t RESERVED_8[4];
+    __O  uint32_t SETVALID;                          /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
+         uint8_t RESERVED_9[4];
+    __O  uint32_t SETTRIG;                           /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
+         uint8_t RESERVED_10[4];
+    __O  uint32_t ABORT;                             /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
+  } COMMON[1];
+       uint8_t RESERVED_1[900];
+  struct {                                         /* offset: 0x400, array step: 0x10 */
+    __IO uint32_t CFG;                               /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
+    __I  uint32_t CTLSTAT;                           /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
+    __IO uint32_t XFERCFG;                           /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
+         uint8_t RESERVED_0[4];
+  } CHANNEL[32];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name CTRL - DMA control. */
+/*! @{ */
+#define DMA_CTRL_ENABLE_MASK                     (0x1U)
+#define DMA_CTRL_ENABLE_SHIFT                    (0U)
+/*! ENABLE - DMA controller master enable.
+ *  0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
+ *       disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
+ *  0b1..Enabled. The DMA controller is enabled.
+ */
+#define DMA_CTRL_ENABLE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt status. */
+/*! @{ */
+#define DMA_INTSTAT_ACTIVEINT_MASK               (0x2U)
+#define DMA_INTSTAT_ACTIVEINT_SHIFT              (1U)
+/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
+ *  0b0..Not pending. No enabled interrupts are pending.
+ *  0b1..Pending. At least one enabled interrupt is pending.
+ */
+#define DMA_INTSTAT_ACTIVEINT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
+#define DMA_INTSTAT_ACTIVEERRINT_MASK            (0x4U)
+#define DMA_INTSTAT_ACTIVEERRINT_SHIFT           (2U)
+/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
+ *  0b0..Not pending. No error interrupts are pending.
+ *  0b1..Pending. At least one error interrupt is pending.
+ */
+#define DMA_INTSTAT_ACTIVEERRINT(x)              (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
+/*! @} */
+
+/*! @name SRAMBASE - SRAM address of the channel configuration table. */
+/*! @{ */
+#define DMA_SRAMBASE_OFFSET_MASK                 (0xFFFFFE00U)
+#define DMA_SRAMBASE_OFFSET_SHIFT                (9U)
+/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
+ *    table must begin on a 512 byte boundary.
+ */
+#define DMA_SRAMBASE_OFFSET(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
+/*! @} */
+
+/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ENABLESET_ENA_MASK            (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLESET_ENA_SHIFT           (0U)
+/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
+ *    number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENA(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ENABLESET */
+#define DMA_COMMON_ENABLESET_COUNT               (1U)
+
+/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ENABLECLR_CLR_MASK            (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLECLR_CLR_SHIFT           (0U)
+/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
+ *    the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
+ *    are reserved.
+ */
+#define DMA_COMMON_ENABLECLR_CLR(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ENABLECLR */
+#define DMA_COMMON_ENABLECLR_COUNT               (1U)
+
+/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ACTIVE_ACT_MASK               (0xFFFFFFFFU)
+#define DMA_COMMON_ACTIVE_ACT_SHIFT              (0U)
+/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
+ *    number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
+ */
+#define DMA_COMMON_ACTIVE_ACT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ACTIVE */
+#define DMA_COMMON_ACTIVE_COUNT                  (1U)
+
+/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_BUSY_BSY_MASK                 (0xFFFFFFFFU)
+#define DMA_COMMON_BUSY_BSY_SHIFT                (0U)
+/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
+ *    number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
+ */
+#define DMA_COMMON_BUSY_BSY(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_BUSY */
+#define DMA_COMMON_BUSY_COUNT                    (1U)
+
+/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ERRINT_ERR_MASK               (0xFFFFFFFFU)
+#define DMA_COMMON_ERRINT_ERR_SHIFT              (0U)
+/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
+ *    bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
+ *    not active. 1 = error interrupt is active.
+ */
+#define DMA_COMMON_ERRINT_ERR(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ERRINT */
+#define DMA_COMMON_ERRINT_COUNT                  (1U)
+
+/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTENSET_INTEN_MASK           (0xFFFFFFFFU)
+#define DMA_COMMON_INTENSET_INTEN_SHIFT          (0U)
+/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
+ *    number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
+ *    interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTENSET */
+#define DMA_COMMON_INTENSET_COUNT                (1U)
+
+/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTENCLR_CLR_MASK             (0xFFFFFFFFU)
+#define DMA_COMMON_INTENCLR_CLR_SHIFT            (0U)
+/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
+ *    corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
+ *    reserved.
+ */
+#define DMA_COMMON_INTENCLR_CLR(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTENCLR */
+#define DMA_COMMON_INTENCLR_COUNT                (1U)
+
+/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTA_IA_MASK                  (0xFFFFFFFFU)
+#define DMA_COMMON_INTA_IA_SHIFT                 (0U)
+/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
+ *    bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
+ *    interrupt A is not active. 1 = the DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_IA(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTA */
+#define DMA_COMMON_INTA_COUNT                    (1U)
+
+/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTB_IB_MASK                  (0xFFFFFFFFU)
+#define DMA_COMMON_INTB_IB_SHIFT                 (0U)
+/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
+ *    bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
+ *    interrupt B is not active. 1 = the DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_IB(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTB */
+#define DMA_COMMON_INTB_COUNT                    (1U)
+
+/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_SETVALID_SV_MASK              (0xFFFFFFFFU)
+#define DMA_COMMON_SETVALID_SV_SHIFT             (0U)
+/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
+ *    = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
+ *    VALIDPENDING control bit for DMA channel n
+ */
+#define DMA_COMMON_SETVALID_SV(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_SETVALID */
+#define DMA_COMMON_SETVALID_COUNT                (1U)
+
+/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_SETTRIG_TRIG_MASK             (0xFFFFFFFFU)
+#define DMA_COMMON_SETTRIG_TRIG_SHIFT            (0U)
+/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
+ *    of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
+ *    sets the TRIG bit for DMA channel n.
+ */
+#define DMA_COMMON_SETTRIG_TRIG(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_SETTRIG */
+#define DMA_COMMON_SETTRIG_COUNT                 (1U)
+
+/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ABORT_ABORTCTRL_MASK          (0xFFFFFFFFU)
+#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT         (0U)
+/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
+ *    1 = aborts DMA operations on channel n.
+ */
+#define DMA_COMMON_ABORT_ABORTCTRL(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ABORT */
+#define DMA_COMMON_ABORT_COUNT                   (1U)
+
+/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
+/*! @{ */
+#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK         (0x1U)
+#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT        (0U)
+/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
+ *    move, any peripheral DMA request associated with that channel can be disabled to prevent any
+ *    interaction between the peripheral and the DMA controller.
+ *  0b0..Disabled. Peripheral DMA requests are disabled.
+ *  0b1..Enabled. Peripheral DMA requests are enabled.
+ */
+#define DMA_CHANNEL_CFG_PERIPHREQEN(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
+#define DMA_CHANNEL_CFG_HWTRIGEN_MASK            (0x2U)
+#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT           (1U)
+/*! HWTRIGEN - Hardware Triggering Enable for this channel.
+ *  0b0..Disabled. Hardware triggering is not used.
+ *  0b1..Enabled. Use hardware triggering.
+ */
+#define DMA_CHANNEL_CFG_HWTRIGEN(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
+#define DMA_CHANNEL_CFG_TRIGPOL_MASK             (0x10U)
+#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT            (4U)
+/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
+ *  0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
+ *  0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
+ */
+#define DMA_CHANNEL_CFG_TRIGPOL(x)               (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
+#define DMA_CHANNEL_CFG_TRIGTYPE_MASK            (0x20U)
+#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT           (5U)
+/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
+ *  0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
+ *  0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
+ *       0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
+ *       trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
+ *       is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
+ *       current BURSTPOWER length are completed.
+ */
+#define DMA_CHANNEL_CFG_TRIGTYPE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
+#define DMA_CHANNEL_CFG_TRIGBURST_MASK           (0x40U)
+#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT          (6U)
+/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
+ *  0b0..Single transfer. Hardware trigger causes a single transfer.
+ *  0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
+ *       burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a
+ *       hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
+ *       complete.
+ */
+#define DMA_CHANNEL_CFG_TRIGBURST(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
+#define DMA_CHANNEL_CFG_BURSTPOWER_MASK          (0xF00U)
+#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT         (8U)
+/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
+ *    SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
+ *    When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
+ *    transfers are performed for each DMA trigger. This can be used, for example, with peripherals that
+ *    contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:
+ *    Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =
+ *    1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The
+ *    total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
+ *    multiple of the burst size.
+ */
+#define DMA_CHANNEL_CFG_BURSTPOWER(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK        (0x4000U)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT       (14U)
+/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
+ *    'wrapped', meaning that the source address range for each burst will be the same. As an example, this
+ *    could be used to read several sequential registers from a peripheral for each DMA burst,
+ *    reading the same registers again for each burst.
+ *  0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
+ *  0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
+ */
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK        (0x8000U)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT       (15U)
+/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
+ *    'wrapped', meaning that the destination address range for each burst will be the same. As an
+ *    example, this could be used to write several sequential registers to a peripheral for each DMA
+ *    burst, writing the same registers again for each burst.
+ *  0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
+ *  0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
+ */
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_CHPRIORITY_MASK          (0x70000U)
+#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT         (16U)
+/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority
+ *    levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
+ */
+#define DMA_CHANNEL_CFG_CHPRIORITY(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
+/*! @} */
+
+/* The count of DMA_CHANNEL_CFG */
+#define DMA_CHANNEL_CFG_COUNT                    (32U)
+
+/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
+/*! @{ */
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK    (0x1U)
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT   (0U)
+/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the
+ *    corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
+ *  0b0..No effect. No effect on DMA operation.
+ *  0b1..Valid pending.
+ */
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x)      (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
+#define DMA_CHANNEL_CTLSTAT_TRIG_MASK            (0x4U)
+#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT           (2U)
+/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is
+ *    cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
+ *  0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
+ *  0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
+ */
+#define DMA_CHANNEL_CTLSTAT_TRIG(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
+/*! @} */
+
+/* The count of DMA_CHANNEL_CTLSTAT */
+#define DMA_CHANNEL_CTLSTAT_COUNT                (32U)
+
+/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
+/*! @{ */
+#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK        (0x1U)
+#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT       (0U)
+/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor
+ *    is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
+ *  0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
+ *  0b1..Valid. The current channel descriptor is considered valid.
+ */
+#define DMA_CHANNEL_XFERCFG_CFGVALID(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
+#define DMA_CHANNEL_XFERCFG_RELOAD_MASK          (0x2U)
+#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT         (1U)
+/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current
+ *    descriptor is exhausted. Reloading allows ping-pong and linked transfers.
+ *  0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
+ *  0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.
+ */
+#define DMA_CHANNEL_XFERCFG_RELOAD(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK          (0x4U)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT         (2U)
+/*! SWTRIG - Software Trigger.
+ *  0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by
+ *       the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
+ *  0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not
+ *       be used with level triggering when TRIGBURST = 0.
+ */
+#define DMA_CHANNEL_XFERCFG_SWTRIG(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK         (0x8U)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT        (3U)
+/*! CLRTRIG - Clear Trigger.
+ *  0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
+ *  0b1..Cleared. The trigger is cleared when this descriptor is exhausted
+ */
+#define DMA_CHANNEL_XFERCFG_CLRTRIG(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
+#define DMA_CHANNEL_XFERCFG_SETINTA_MASK         (0x10U)
+#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT        (4U)
+/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between
+ *    interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
+ *    convention, interrupt A may be used when only one interrupt flag is needed.
+ *  0b0..No effect.
+ *  0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
+ */
+#define DMA_CHANNEL_XFERCFG_SETINTA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
+#define DMA_CHANNEL_XFERCFG_SETINTB_MASK         (0x20U)
+#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT        (5U)
+/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between
+ *    interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
+ *    convention, interrupt A may be used when only one interrupt flag is needed.
+ *  0b0..No effect.
+ *  0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
+ */
+#define DMA_CHANNEL_XFERCFG_SETINTB(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
+#define DMA_CHANNEL_XFERCFG_WIDTH_MASK           (0x300U)
+#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT          (8U)
+/*! WIDTH - Transfer width used for this DMA channel.
+ *  0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
+ *  0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
+ *  0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
+ *  0b11..Reserved. Reserved setting, do not use.
+ */
+#define DMA_CHANNEL_XFERCFG_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
+#define DMA_CHANNEL_XFERCFG_SRCINC_MASK          (0x3000U)
+#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT         (12U)
+/*! SRCINC - Determines whether the source address is incremented for each DMA transfer.
+ *  0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
+ *  0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is
+ *        the usual case when the source is memory.
+ *  0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
+ *  0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
+ */
+#define DMA_CHANNEL_XFERCFG_SRCINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
+#define DMA_CHANNEL_XFERCFG_DSTINC_MASK          (0xC000U)
+#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT         (14U)
+/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer.
+ *  0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when
+ *        the destination is a peripheral device.
+ *  0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer.
+ *        This is the usual case when the destination is memory.
+ *  0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
+ *  0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
+ */
+#define DMA_CHANNEL_XFERCFG_DSTINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK       (0x3FF0000U)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT      (16U)
+/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes
+ *    transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller
+ *    uses this bit field during transfer to count down. Hence, it cannot be used by software to read
+ *    back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1
+ *    transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of
+ *    1,024 transfers will be performed.
+ */
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
+/*! @} */
+
+/* The count of DMA_CHANNEL_XFERCFG */
+#define DMA_CHANNEL_XFERCFG_COUNT                (32U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA0 base address */
+#define DMA0_BASE                                (0x40082000u)
+/** Peripheral DMA0 base pointer */
+#define DMA0                                     ((DMA_Type *)DMA0_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA0_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_IRQS                                 { DMA0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMIC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
+ * @{
+ */
+
+/** DMIC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x100 */
+    __IO uint32_t OSR;                               /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */
+    __IO uint32_t DIVHFCLK;                          /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */
+    __IO uint32_t PREAC2FSCOEF;                      /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */
+    __IO uint32_t PREAC4FSCOEF;                      /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */
+    __IO uint32_t GAINSHIFT;                         /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */
+         uint8_t RESERVED_0[108];
+    __IO uint32_t FIFO_CTRL;                         /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */
+    __IO uint32_t FIFO_STATUS;                       /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */
+    __IO uint32_t FIFO_DATA;                         /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */
+    __IO uint32_t PHY_CTRL;                          /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */
+    __IO uint32_t DC_CTRL;                           /**< DC Control register 0, array offset: 0x90, array step: 0x100 */
+         uint8_t RESERVED_1[108];
+  } CHANNEL[2];
+       uint8_t RESERVED_0[3328];
+  __IO uint32_t CHANEN;                            /**< Channel Enable register, offset: 0xF00 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t IOCFG;                             /**< I/O Configuration register, offset: 0xF0C */
+  __IO uint32_t USE2FS;                            /**< Use 2FS register, offset: 0xF10 */
+       uint8_t RESERVED_2[108];
+  __IO uint32_t HWVADGAIN;                         /**< HWVAD input gain register, offset: 0xF80 */
+  __IO uint32_t HWVADHPFS;                         /**< HWVAD filter control register, offset: 0xF84 */
+  __IO uint32_t HWVADST10;                         /**< HWVAD control register, offset: 0xF88 */
+  __IO uint32_t HWVADRSTT;                         /**< HWVAD filter reset register, offset: 0xF8C */
+  __IO uint32_t HWVADTHGN;                         /**< HWVAD noise estimator gain register, offset: 0xF90 */
+  __IO uint32_t HWVADTHGS;                         /**< HWVAD signal estimator gain register, offset: 0xF94 */
+  __I  uint32_t HWVADLOWZ;                         /**< HWVAD noise envelope estimator register, offset: 0xF98 */
+       uint8_t RESERVED_3[96];
+  __I  uint32_t ID;                                /**< Module Identification register, offset: 0xFFC */
+} DMIC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMIC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Register_Masks DMIC Register Masks
+ * @{
+ */
+
+/*! @name CHANNEL_OSR - Oversample Rate register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_OSR_OSR_MASK                (0xFFU)
+#define DMIC_CHANNEL_OSR_OSR_SHIFT               (0U)
+/*! OSR - Selects the oversample rate for the related input channel.
+ */
+#define DMIC_CHANNEL_OSR_OSR(x)                  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_OSR */
+#define DMIC_CHANNEL_OSR_COUNT                   (2U)
+
+/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK        (0xFU)
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT       (0U)
+/*! PDMDIV - PDM clock divider value. 0 = divide by 1 1 = divide by 2 2 = divide by 3 3 = divide by
+ *    4 4 = divide by 6 5 = divide by 8 6 = divide by 12 7 = divide by 16 8 = divide by 24 9 =
+ *    divide by 32 10 = divide by 48 11 = divide by 64 12 = divide by 96 13 = divide by 128 others =
+ *    reserved.
+ */
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_DIVHFCLK */
+#define DMIC_CHANNEL_DIVHFCLK_COUNT              (2U)
+
+/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */
+/*! @{ */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK      (0x3U)
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT     (0U)
+/*! COMP - Pre-emphasis filer coefficient for 2 FS mode. 0 = Compensation = 0 1 = Compensation = 16
+ *    2 = Compensation = 15 3 = Compensation = 13
+ */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT          (2U)
+
+/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */
+/*! @{ */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK      (0x3U)
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT     (0U)
+/*! COMP - Pre-emphasis filer coefficient for 4 FS mode. 0 = Compensation = 0 1 = Compensation = 16
+ *    2 = Compensation = 15 3 = Compensation = 13
+ */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT          (2U)
+
+/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */
+/*! @{ */
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK         (0x3FU)
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT        (0U)
+/*! GAIN - Gain control, as a positive or negative (two's complement) number of bits to shift.
+ */
+#define DMIC_CHANNEL_GAINSHIFT_GAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_GAINSHIFT */
+#define DMIC_CHANNEL_GAINSHIFT_COUNT             (2U)
+
+/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK       (0x1U)
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT      (0U)
+/*! ENABLE - FIFO enable.
+ *  0b0..FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being
+ *       streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a
+ *       period when the data was not needed.
+ *  0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK       (0x2U)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT      (1U)
+/*! RESETN - FIFO reset.
+ *  0b0..Reset the FIFO.
+ *  0b1..Normal operation
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK        (0x4U)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT       (2U)
+/*! INTEN - Interrupt enable.
+ *  0b0..FIFO level interrupts are not enabled.
+ *  0b1..FIFO level interrupts are enabled.
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK        (0x8U)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT       (3U)
+/*! DMAEN - DMA enable
+ *  0b0..DMA requests are not enabled.
+ *  0b1..DMA requests based on FIFO level are enabled.
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK      (0x1F0000U)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT     (16U)
+/*! TRIGLVL - FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If
+ *    enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then
+ *    return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 =
+ *    trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has
+ *    received two entries. 15 = trigger when the FIFO has received 16 entries (has become full).
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_FIFO_CTRL */
+#define DMIC_CHANNEL_FIFO_CTRL_COUNT             (2U)
+
+/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK        (0x1U)
+#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT       (0U)
+/*! INT - Interrupt flag. Asserted when FIFO data reaches the level specified in the FIFOCTRL
+ *    register. Writing a one to this bit clears the flag. Remark: note that the bus clock to the DMIC
+ *    subsystem must be running in order for an interrupt to occur.
+ */
+#define DMIC_CHANNEL_FIFO_STATUS_INT(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK    (0x2U)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT   (1U)
+/*! OVERRUN - Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one
+ *    to this bit clears the flag. This flag does not cause an interrupt.
+ */
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x)      (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK   (0x4U)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT  (2U)
+/*! UNDERRUN - Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag.
+ */
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x)     (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_FIFO_STATUS */
+#define DMIC_CHANNEL_FIFO_STATUS_COUNT           (2U)
+
+/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK         (0xFFFFFFU)
+#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT        (0U)
+/*! DATA - Data from the top of the input filter FIFO.
+ */
+#define DMIC_CHANNEL_FIFO_DATA_DATA(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_FIFO_DATA */
+#define DMIC_CHANNEL_FIFO_DATA_COUNT             (2U)
+
+/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK      (0x1U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT     (0U)
+/*! PHY_FALL - Capture PDM_DATA
+ *  0b0..Capture PDM_DATA on the rising edge of PDM_CLK.
+ *  0b1..Capture PDM_DATA on the falling edge of PDM_CLK.
+ */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK      (0x2U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT     (1U)
+/*! PHY_HALF - Half rate sampling
+ *  0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
+ *  0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.
+ */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_PHY_CTRL */
+#define DMIC_CHANNEL_PHY_CTRL_COUNT              (2U)
+
+/*! @name CHANNEL_DC_CTRL - DC Control register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK         (0x3U)
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT        (0U)
+/*! DCPOLE - DC block filter
+ *  0b00..Flat response, no filter.
+ *  0b01..155 Hz.
+ *  0b10..78 Hz.
+ *  0b11..39 Hz
+ */
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK         (0xF0U)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT        (4U)
+/*! DCGAIN - Fine gain adjustment in the form of a number of bits to downshift.
+ */
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
+/*! SATURATEAT16BIT - Selects 16-bit saturation.
+ *  0b0..Results roll over if out range and do not saturate.
+ *  0b1..If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
+ */
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x)  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_DC_CTRL */
+#define DMIC_CHANNEL_DC_CTRL_COUNT               (2U)
+
+/*! @name CHANEN - Channel Enable register */
+/*! @{ */
+#define DMIC_CHANEN_EN_CH0_MASK                  (0x1U)
+#define DMIC_CHANEN_EN_CH0_SHIFT                 (0U)
+/*! EN_CH0 - Enable channel 0. When 1, PDM channel 0 is enabled.
+ */
+#define DMIC_CHANEN_EN_CH0(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
+#define DMIC_CHANEN_EN_CH1_MASK                  (0x2U)
+#define DMIC_CHANEN_EN_CH1_SHIFT                 (1U)
+/*! EN_CH1 - Enable channel 1. When 1, PDM channel 1 is enabled.
+ */
+#define DMIC_CHANEN_EN_CH1(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
+/*! @} */
+
+/*! @name IOCFG - I/O Configuration register */
+/*! @{ */
+#define DMIC_IOCFG_CLK_BYPASS0_MASK              (0x1U)
+#define DMIC_IOCFG_CLK_BYPASS0_SHIFT             (0U)
+/*! CLK_BYPASS0 - Bypass CLK0. When 1, PDM_DATA1 becomes the clock for PDM channel 0. This provides
+ *    for the possibility of an external codec taking over the PDM bus.
+ */
+#define DMIC_IOCFG_CLK_BYPASS0(x)                (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)
+#define DMIC_IOCFG_CLK_BYPASS1_MASK              (0x2U)
+#define DMIC_IOCFG_CLK_BYPASS1_SHIFT             (1U)
+/*! CLK_BYPASS1 - Bypass CLK1. When 1, PDM_DATA1 becomes the clock for PDM channel 1. This provides
+ *    for the possibility of an external codec taking over the PDM bus.
+ */
+#define DMIC_IOCFG_CLK_BYPASS1(x)                (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)
+#define DMIC_IOCFG_STEREO_DATA0_MASK             (0x4U)
+#define DMIC_IOCFG_STEREO_DATA0_SHIFT            (2U)
+/*! STEREO_DATA0 - Stereo PDM select. When 1, PDM_DATA0 is routed to both PDM channels in a
+ *    configuration that supports a single stereo digital microphone.
+ */
+#define DMIC_IOCFG_STEREO_DATA0(x)               (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)
+/*! @} */
+
+/*! @name USE2FS - Use 2FS register */
+/*! @{ */
+#define DMIC_USE2FS_USE2FS_MASK                  (0x1U)
+#define DMIC_USE2FS_USE2FS_SHIFT                 (0U)
+/*! USE2FS - Use 2FS register
+ *  0b0..Use 1FS output for PCM data.
+ *  0b1..Use 2FS output for PCM data.
+ */
+#define DMIC_USE2FS_USE2FS(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
+/*! @} */
+
+/*! @name HWVADGAIN - HWVAD input gain register */
+/*! @{ */
+#define DMIC_HWVADGAIN_INPUTGAIN_MASK            (0xFU)
+#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT           (0U)
+/*! INPUTGAIN - Shift value for input bits 0x00 -10 bits 0x01 -8 bits 0x02 -6 bits 0x03 -4 bits 0x04
+ *    -2 bits 0x05 0 bits (default) 0x06 +2 bits 0x07 +4 bits 0x08 +6 bits 0x09 +8 bits 0x0A +10
+ *    bits 0x0B +12 bits 0x0C +14 bits 0x0D to 0x0F Reserved.
+ */
+#define DMIC_HWVADGAIN_INPUTGAIN(x)              (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
+/*! @} */
+
+/*! @name HWVADHPFS - HWVAD filter control register */
+/*! @{ */
+#define DMIC_HWVADHPFS_HPFS_MASK                 (0x3U)
+#define DMIC_HWVADHPFS_HPFS_SHIFT                (0U)
+/*! HPFS - High pass filter
+ *  0b00..First filter by-pass.
+ *  0b01..High pass filter with -3dB cut-off at 1750Hz.
+ *  0b10..High pass filter with -3dB cut-off at 215Hz.
+ *  0b11..Reserved.
+ */
+#define DMIC_HWVADHPFS_HPFS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
+/*! @} */
+
+/*! @name HWVADST10 - HWVAD control register */
+/*! @{ */
+#define DMIC_HWVADST10_ST10_MASK                 (0x1U)
+#define DMIC_HWVADST10_ST10_SHIFT                (0U)
+/*! ST10 - Stage 0
+ *  0b0..Normal operation, waiting for HWVAD trigger event (stage 0).
+ *  0b1..Reset internal interrupt flag by writing a '1' pulse.
+ */
+#define DMIC_HWVADST10_ST10(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
+/*! @} */
+
+/*! @name HWVADRSTT - HWVAD filter reset register */
+/*! @{ */
+#define DMIC_HWVADRSTT_RSTT_MASK                 (0x1U)
+#define DMIC_HWVADRSTT_RSTT_SHIFT                (0U)
+/*! RSTT - Writing a 1 resets all filter values
+ */
+#define DMIC_HWVADRSTT_RSTT(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)
+/*! @} */
+
+/*! @name HWVADTHGN - HWVAD noise estimator gain register */
+/*! @{ */
+#define DMIC_HWVADTHGN_THGN_MASK                 (0xFU)
+#define DMIC_HWVADTHGN_THGN_SHIFT                (0U)
+/*! THGN - Gain value for the noise estimator. Values 0 to 14. 0 corresponds to a gain of 1.
+ */
+#define DMIC_HWVADTHGN_THGN(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
+/*! @} */
+
+/*! @name HWVADTHGS - HWVAD signal estimator gain register */
+/*! @{ */
+#define DMIC_HWVADTHGS_THGS_MASK                 (0xFU)
+#define DMIC_HWVADTHGS_THGS_SHIFT                (0U)
+/*! THGS - Gain value for the signal estimator. Values 0 to 14. 0 corresponds to a gain of 1.
+ */
+#define DMIC_HWVADTHGS_THGS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
+/*! @} */
+
+/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */
+/*! @{ */
+#define DMIC_HWVADLOWZ_LOWZ_MASK                 (0xFFFFU)
+#define DMIC_HWVADLOWZ_LOWZ_SHIFT                (0U)
+/*! LOWZ - Noise envelope estimator value.
+ */
+#define DMIC_HWVADLOWZ_LOWZ(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
+/*! @} */
+
+/*! @name ID - Module Identification register */
+/*! @{ */
+#define DMIC_ID_ID_MASK                          (0xFFFFFFFFU)
+#define DMIC_ID_ID_SHIFT                         (0U)
+/*! ID - Indicates module ID and the number of channels in this DMIC interface.
+ */
+#define DMIC_ID_ID(x)                            (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group DMIC_Register_Masks */
+
+
+/* DMIC - Peripheral instance base addresses */
+/** Peripheral DMIC0 base address */
+#define DMIC0_BASE                               (0x40090000u)
+/** Peripheral DMIC0 base pointer */
+#define DMIC0                                    ((DMIC_Type *)DMIC0_BASE)
+/** Array initializer of DMIC peripheral base addresses */
+#define DMIC_BASE_ADDRS                          { DMIC0_BASE }
+/** Array initializer of DMIC peripheral base pointers */
+#define DMIC_BASE_PTRS                           { DMIC0 }
+/** Interrupt vectors for the DMIC peripheral type */
+#define DMIC_IRQS                                { DMIC0_IRQn }
+#define DMIC_HWVAD_IRQS                          { HWVAD0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMIC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer
+ * @{
+ */
+
+/** EMC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Controls operation of the memory controller, offset: 0x0 */
+  __I  uint32_t STATUS;                            /**< Provides EMC status information, offset: 0x4 */
+  __IO uint32_t CONFIG;                            /**< Configures operation of the memory controller, offset: 0x8 */
+       uint8_t RESERVED_0[20];
+  __IO uint32_t DYNAMICCONTROL;                    /**< Controls dynamic memory operation, offset: 0x20 */
+  __IO uint32_t DYNAMICREFRESH;                    /**< Configures dynamic memory refresh, offset: 0x24 */
+  __IO uint32_t DYNAMICREADCONFIG;                 /**< Configures dynamic memory read strategy, offset: 0x28 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t DYNAMICRP;                         /**< Precharge command period, offset: 0x30 */
+  __IO uint32_t DYNAMICRAS;                        /**< Active to precharge command period, offset: 0x34 */
+  __IO uint32_t DYNAMICSREX;                       /**< Self-refresh exit time, offset: 0x38 */
+  __IO uint32_t DYNAMICAPR;                        /**< Last-data-out to active command time, offset: 0x3C */
+  __IO uint32_t DYNAMICDAL;                        /**< Data-in to active command time, offset: 0x40 */
+  __IO uint32_t DYNAMICWR;                         /**< Write recovery time, offset: 0x44 */
+  __IO uint32_t DYNAMICRC;                         /**< Selects the active to active command period, offset: 0x48 */
+  __IO uint32_t DYNAMICRFC;                        /**< Selects the auto-refresh period, offset: 0x4C */
+  __IO uint32_t DYNAMICXSR;                        /**< Time for exit self-refresh to active command, offset: 0x50 */
+  __IO uint32_t DYNAMICRRD;                        /**< Latency for active bank A to active bank B, offset: 0x54 */
+  __IO uint32_t DYNAMICMRD;                        /**< Time for load mode register to active command, offset: 0x58 */
+       uint8_t RESERVED_2[36];
+  __IO uint32_t STATICEXTENDEDWAIT;                /**< Time for long static memory read and write transfers, offset: 0x80 */
+       uint8_t RESERVED_3[124];
+  struct {                                         /* offset: 0x100, array step: 0x20 */
+    __IO uint32_t DYNAMICCONFIG;                     /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */
+    __IO uint32_t DYNAMICRASCAS;                     /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */
+         uint8_t RESERVED_0[24];
+  } DYNAMIC[4];
+       uint8_t RESERVED_4[128];
+  struct {                                         /* offset: 0x200, array step: 0x20 */
+    __IO uint32_t STATICCONFIG;                      /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */
+    __IO uint32_t STATICWAITWEN;                     /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */
+    __IO uint32_t STATICWAITOEN;                     /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */
+    __IO uint32_t STATICWAITRD;                      /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */
+    __IO uint32_t STATICWAITPAGE;                    /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */
+    __IO uint32_t STATICWAITWR;                      /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */
+    __IO uint32_t STATICWAITTURN;                    /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */
+         uint8_t RESERVED_0[4];
+  } STATIC[4];
+} EMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMC_Register_Masks EMC Register Masks
+ * @{
+ */
+
+/*! @name CONTROL - Controls operation of the memory controller */
+/*! @{ */
+#define EMC_CONTROL_E_MASK                       (0x1U)
+#define EMC_CONTROL_E_SHIFT                      (0U)
+/*! E - EMC Enable.
+ */
+#define EMC_CONTROL_E(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK)
+#define EMC_CONTROL_M_MASK                       (0x2U)
+#define EMC_CONTROL_M_SHIFT                      (1U)
+/*! M - Address mirror.
+ */
+#define EMC_CONTROL_M(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK)
+#define EMC_CONTROL_L_MASK                       (0x4U)
+#define EMC_CONTROL_L_SHIFT                      (2U)
+/*! L - Low-power mode.
+ */
+#define EMC_CONTROL_L(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK)
+/*! @} */
+
+/*! @name STATUS - Provides EMC status information */
+/*! @{ */
+#define EMC_STATUS_B_MASK                        (0x1U)
+#define EMC_STATUS_B_SHIFT                       (0U)
+/*! B - Busy.
+ */
+#define EMC_STATUS_B(x)                          (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK)
+#define EMC_STATUS_S_MASK                        (0x2U)
+#define EMC_STATUS_S_SHIFT                       (1U)
+/*! S - Write buffer status.
+ */
+#define EMC_STATUS_S(x)                          (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK)
+#define EMC_STATUS_SA_MASK                       (0x4U)
+#define EMC_STATUS_SA_SHIFT                      (2U)
+/*! SA - Self-refresh acknowledge.
+ */
+#define EMC_STATUS_SA(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK)
+/*! @} */
+
+/*! @name CONFIG - Configures operation of the memory controller */
+/*! @{ */
+#define EMC_CONFIG_EM_MASK                       (0x1U)
+#define EMC_CONFIG_EM_SHIFT                      (0U)
+/*! EM - Endian mode.
+ */
+#define EMC_CONFIG_EM(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK)
+#define EMC_CONFIG_CLKR_MASK                     (0x100U)
+#define EMC_CONFIG_CLKR_SHIFT                    (8U)
+/*! CLKR - This bit must contain 0 for proper operation of the EMC.
+ */
+#define EMC_CONFIG_CLKR(x)                       (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK)
+/*! @} */
+
+/*! @name DYNAMICCONTROL - Controls dynamic memory operation */
+/*! @{ */
+#define EMC_DYNAMICCONTROL_CE_MASK               (0x1U)
+#define EMC_DYNAMICCONTROL_CE_SHIFT              (0U)
+/*! CE - Dynamic memory clock enable.
+ */
+#define EMC_DYNAMICCONTROL_CE(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK)
+#define EMC_DYNAMICCONTROL_CS_MASK               (0x2U)
+#define EMC_DYNAMICCONTROL_CS_SHIFT              (1U)
+/*! CS - Dynamic memory clock control.
+ */
+#define EMC_DYNAMICCONTROL_CS(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK)
+#define EMC_DYNAMICCONTROL_SR_MASK               (0x4U)
+#define EMC_DYNAMICCONTROL_SR_SHIFT              (2U)
+/*! SR - Self-refresh request, EMCSREFREQ.
+ */
+#define EMC_DYNAMICCONTROL_SR(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK)
+#define EMC_DYNAMICCONTROL_MMC_MASK              (0x20U)
+#define EMC_DYNAMICCONTROL_MMC_SHIFT             (5U)
+/*! MMC - Memory clock control.
+ */
+#define EMC_DYNAMICCONTROL_MMC(x)                (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK)
+#define EMC_DYNAMICCONTROL_I_MASK                (0x180U)
+#define EMC_DYNAMICCONTROL_I_SHIFT               (7U)
+/*! I - SDRAM initialization.
+ */
+#define EMC_DYNAMICCONTROL_I(x)                  (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK)
+/*! @} */
+
+/*! @name DYNAMICREFRESH - Configures dynamic memory refresh */
+/*! @{ */
+#define EMC_DYNAMICREFRESH_REFRESH_MASK          (0x7FFU)
+#define EMC_DYNAMICREFRESH_REFRESH_SHIFT         (0U)
+/*! REFRESH - Refresh timer.
+ */
+#define EMC_DYNAMICREFRESH_REFRESH(x)            (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK)
+/*! @} */
+
+/*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */
+/*! @{ */
+#define EMC_DYNAMICREADCONFIG_RD_MASK            (0x3U)
+#define EMC_DYNAMICREADCONFIG_RD_SHIFT           (0U)
+/*! RD - Read data strategy.
+ */
+#define EMC_DYNAMICREADCONFIG_RD(x)              (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK)
+/*! @} */
+
+/*! @name DYNAMICRP - Precharge command period */
+/*! @{ */
+#define EMC_DYNAMICRP_TRP_MASK                   (0xFU)
+#define EMC_DYNAMICRP_TRP_SHIFT                  (0U)
+/*! TRP - Precharge command period.
+ */
+#define EMC_DYNAMICRP_TRP(x)                     (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK)
+/*! @} */
+
+/*! @name DYNAMICRAS - Active to precharge command period */
+/*! @{ */
+#define EMC_DYNAMICRAS_TRAS_MASK                 (0xFU)
+#define EMC_DYNAMICRAS_TRAS_SHIFT                (0U)
+/*! TRAS - Active to precharge command period.
+ */
+#define EMC_DYNAMICRAS_TRAS(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK)
+/*! @} */
+
+/*! @name DYNAMICSREX - Self-refresh exit time */
+/*! @{ */
+#define EMC_DYNAMICSREX_TSREX_MASK               (0xFU)
+#define EMC_DYNAMICSREX_TSREX_SHIFT              (0U)
+/*! TSREX - Self-refresh exit time.
+ */
+#define EMC_DYNAMICSREX_TSREX(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK)
+/*! @} */
+
+/*! @name DYNAMICAPR - Last-data-out to active command time */
+/*! @{ */
+#define EMC_DYNAMICAPR_TAPR_MASK                 (0xFU)
+#define EMC_DYNAMICAPR_TAPR_SHIFT                (0U)
+/*! TAPR - Last-data-out to active command time.
+ */
+#define EMC_DYNAMICAPR_TAPR(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK)
+/*! @} */
+
+/*! @name DYNAMICDAL - Data-in to active command time */
+/*! @{ */
+#define EMC_DYNAMICDAL_TDAL_MASK                 (0xFU)
+#define EMC_DYNAMICDAL_TDAL_SHIFT                (0U)
+/*! TDAL - Data-in to active command.
+ */
+#define EMC_DYNAMICDAL_TDAL(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK)
+/*! @} */
+
+/*! @name DYNAMICWR - Write recovery time */
+/*! @{ */
+#define EMC_DYNAMICWR_TWR_MASK                   (0xFU)
+#define EMC_DYNAMICWR_TWR_SHIFT                  (0U)
+/*! TWR - Write recovery time.
+ */
+#define EMC_DYNAMICWR_TWR(x)                     (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK)
+/*! @} */
+
+/*! @name DYNAMICRC - Selects the active to active command period */
+/*! @{ */
+#define EMC_DYNAMICRC_TRC_MASK                   (0x1FU)
+#define EMC_DYNAMICRC_TRC_SHIFT                  (0U)
+/*! TRC - Active to active command period.
+ */
+#define EMC_DYNAMICRC_TRC(x)                     (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK)
+/*! @} */
+
+/*! @name DYNAMICRFC - Selects the auto-refresh period */
+/*! @{ */
+#define EMC_DYNAMICRFC_TRFC_MASK                 (0x1FU)
+#define EMC_DYNAMICRFC_TRFC_SHIFT                (0U)
+/*! TRFC - Auto-refresh period and auto-refresh to active command period.
+ */
+#define EMC_DYNAMICRFC_TRFC(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK)
+/*! @} */
+
+/*! @name DYNAMICXSR - Time for exit self-refresh to active command */
+/*! @{ */
+#define EMC_DYNAMICXSR_TXSR_MASK                 (0x1FU)
+#define EMC_DYNAMICXSR_TXSR_SHIFT                (0U)
+/*! TXSR - Exit self-refresh to active command time.
+ */
+#define EMC_DYNAMICXSR_TXSR(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK)
+/*! @} */
+
+/*! @name DYNAMICRRD - Latency for active bank A to active bank B */
+/*! @{ */
+#define EMC_DYNAMICRRD_TRRD_MASK                 (0xFU)
+#define EMC_DYNAMICRRD_TRRD_SHIFT                (0U)
+/*! TRRD - Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles.
+ */
+#define EMC_DYNAMICRRD_TRRD(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK)
+/*! @} */
+
+/*! @name DYNAMICMRD - Time for load mode register to active command */
+/*! @{ */
+#define EMC_DYNAMICMRD_TMRD_MASK                 (0xFU)
+#define EMC_DYNAMICMRD_TMRD_SHIFT                (0U)
+/*! TMRD - Load mode register to active command time.
+ */
+#define EMC_DYNAMICMRD_TMRD(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK)
+/*! @} */
+
+/*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */
+/*! @{ */
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU)
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U)
+/*! EXTENDEDWAIT - Extended wait time out.
+ */
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x)   (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK)
+/*! @} */
+
+/*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */
+/*! @{ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK        (0x18U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT       (3U)
+/*! MD - Memory device.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD(x)          (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK       (0x1F80U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT      (7U)
+/*! AM0 - See Table 933.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK       (0x4000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT      (14U)
+/*! AM1 - See Table 933.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK         (0x80000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT        (19U)
+/*! B - Buffer enable.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_B(x)           (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK         (0x100000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT        (20U)
+/*! P - Write protect.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_P(x)           (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK)
+/*! @} */
+
+/* The count of EMC_DYNAMIC_DYNAMICCONFIG */
+#define EMC_DYNAMIC_DYNAMICCONFIG_COUNT          (4U)
+
+/*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */
+/*! @{ */
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK       (0x3U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT      (0U)
+/*! RAS - RAS latency (active to read/write delay).
+ */
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK)
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK       (0x300U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT      (8U)
+/*! CAS - CAS latency.
+ */
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK)
+/*! @} */
+
+/* The count of EMC_DYNAMIC_DYNAMICRASCAS */
+#define EMC_DYNAMIC_DYNAMICRASCAS_COUNT          (4U)
+
+/*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */
+/*! @{ */
+#define EMC_STATIC_STATICCONFIG_MW_MASK          (0x3U)
+#define EMC_STATIC_STATICCONFIG_MW_SHIFT         (0U)
+/*! MW - Memory width.
+ */
+#define EMC_STATIC_STATICCONFIG_MW(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK)
+#define EMC_STATIC_STATICCONFIG_PM_MASK          (0x8U)
+#define EMC_STATIC_STATICCONFIG_PM_SHIFT         (3U)
+/*! PM - Page mode.
+ */
+#define EMC_STATIC_STATICCONFIG_PM(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK)
+#define EMC_STATIC_STATICCONFIG_PC_MASK          (0x40U)
+#define EMC_STATIC_STATICCONFIG_PC_SHIFT         (6U)
+/*! PC - Chip select polarity.
+ */
+#define EMC_STATIC_STATICCONFIG_PC(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK)
+#define EMC_STATIC_STATICCONFIG_PB_MASK          (0x80U)
+#define EMC_STATIC_STATICCONFIG_PB_SHIFT         (7U)
+/*! PB - Byte lane state.
+ */
+#define EMC_STATIC_STATICCONFIG_PB(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK)
+#define EMC_STATIC_STATICCONFIG_EW_MASK          (0x100U)
+#define EMC_STATIC_STATICCONFIG_EW_SHIFT         (8U)
+/*! EW - Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write
+ *    transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.
+ */
+#define EMC_STATIC_STATICCONFIG_EW(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK)
+#define EMC_STATIC_STATICCONFIG_B_MASK           (0x80000U)
+#define EMC_STATIC_STATICCONFIG_B_SHIFT          (19U)
+/*! B - Buffer enable [2].
+ */
+#define EMC_STATIC_STATICCONFIG_B(x)             (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK)
+#define EMC_STATIC_STATICCONFIG_P_MASK           (0x100000U)
+#define EMC_STATIC_STATICCONFIG_P_SHIFT          (20U)
+/*! P - Write protect.
+ */
+#define EMC_STATIC_STATICCONFIG_P(x)             (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICCONFIG */
+#define EMC_STATIC_STATICCONFIG_COUNT            (4U)
+
+/*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */
+/*! @{ */
+#define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK    (0xFU)
+#define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT   (0U)
+/*! WAITWEN - Wait write enable.
+ */
+#define EMC_STATIC_STATICWAITWEN_WAITWEN(x)      (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITWEN */
+#define EMC_STATIC_STATICWAITWEN_COUNT           (4U)
+
+/*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */
+/*! @{ */
+#define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK    (0xFU)
+#define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT   (0U)
+/*! WAITOEN - Wait output enable.
+ */
+#define EMC_STATIC_STATICWAITOEN_WAITOEN(x)      (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITOEN */
+#define EMC_STATIC_STATICWAITOEN_COUNT           (4U)
+
+/*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */
+/*! @{ */
+#define EMC_STATIC_STATICWAITRD_WAITRD_MASK      (0x1FU)
+#define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT     (0U)
+/*! WAITRD - .
+ */
+#define EMC_STATIC_STATICWAITRD_WAITRD(x)        (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITRD */
+#define EMC_STATIC_STATICWAITRD_COUNT            (4U)
+
+/*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */
+/*! @{ */
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK  (0x1FU)
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U)
+/*! WAITPAGE - Asynchronous page mode read after the first read wait states.
+ */
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x)    (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITPAGE */
+#define EMC_STATIC_STATICWAITPAGE_COUNT          (4U)
+
+/*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */
+/*! @{ */
+#define EMC_STATIC_STATICWAITWR_WAITWR_MASK      (0x1FU)
+#define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT     (0U)
+/*! WAITWR - Write wait states.
+ */
+#define EMC_STATIC_STATICWAITWR_WAITWR(x)        (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITWR */
+#define EMC_STATIC_STATICWAITWR_COUNT            (4U)
+
+/*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */
+/*! @{ */
+#define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK  (0xFU)
+#define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U)
+/*! WAITTURN - Bus turn-around cycles.
+ */
+#define EMC_STATIC_STATICWAITTURN_WAITTURN(x)    (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITTURN */
+#define EMC_STATIC_STATICWAITTURN_COUNT          (4U)
+
+
+/*!
+ * @}
+ */ /* end of group EMC_Register_Masks */
+
+
+/* EMC - Peripheral instance base addresses */
+/** Peripheral EMC base address */
+#define EMC_BASE                                 (0x40081000u)
+/** Peripheral EMC base pointer */
+#define EMC                                      ((EMC_Type *)EMC_BASE)
+/** Array initializer of EMC peripheral base addresses */
+#define EMC_BASE_ADDRS                           { EMC_BASE }
+/** Array initializer of EMC peripheral base pointers */
+#define EMC_BASE_PTRS                            { EMC }
+
+/*!
+ * @}
+ */ /* end of group EMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FLEXCOMM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXCOMM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[4088];
+  __IO uint32_t PSELID;                            /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
+  __I  uint32_t PID;                               /**< Peripheral identification register., offset: 0xFFC */
+} FLEXCOMM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FLEXCOMM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
+ * @{
+ */
+
+/*! @name PSELID - Peripheral Select and Flexcomm ID register. */
+/*! @{ */
+#define FLEXCOMM_PSELID_PERSEL_MASK              (0x7U)
+#define FLEXCOMM_PSELID_PERSEL_SHIFT             (0U)
+/*! PERSEL - Peripheral Select. This field is writable by software.
+ *  0b000..No peripheral selected.
+ *  0b001..USART function selected.
+ *  0b010..SPI function selected.
+ *  0b011..I2C function selected.
+ *  0b100..I2S transmit function selected.
+ *  0b101..I2S receive function selected.
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define FLEXCOMM_PSELID_PERSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
+#define FLEXCOMM_PSELID_LOCK_MASK                (0x8U)
+#define FLEXCOMM_PSELID_LOCK_SHIFT               (3U)
+/*! LOCK - Lock the peripheral select. This field is writable by software.
+ *  0b0..Peripheral select can be changed by software.
+ *  0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset.
+ */
+#define FLEXCOMM_PSELID_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
+#define FLEXCOMM_PSELID_USARTPRESENT_MASK        (0x10U)
+#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT       (4U)
+/*! USARTPRESENT - USART present indicator. This field is Read-only.
+ *  0b0..This Flexcomm does not include the USART function.
+ *  0b1..This Flexcomm includes the USART function.
+ */
+#define FLEXCOMM_PSELID_USARTPRESENT(x)          (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
+#define FLEXCOMM_PSELID_SPIPRESENT_MASK          (0x20U)
+#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT         (5U)
+/*! SPIPRESENT - SPI present indicator. This field is Read-only.
+ *  0b0..This Flexcomm does not include the SPI function.
+ *  0b1..This Flexcomm includes the SPI function.
+ */
+#define FLEXCOMM_PSELID_SPIPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
+#define FLEXCOMM_PSELID_I2CPRESENT_MASK          (0x40U)
+#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT         (6U)
+/*! I2CPRESENT - I2C present indicator. This field is Read-only.
+ *  0b0..This Flexcomm does not include the I2C function.
+ *  0b1..This Flexcomm includes the I2C function.
+ */
+#define FLEXCOMM_PSELID_I2CPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
+#define FLEXCOMM_PSELID_I2SPRESENT_MASK          (0x80U)
+#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT         (7U)
+/*! I2SPRESENT - I 2S present indicator. This field is Read-only.
+ *  0b0..This Flexcomm does not include the I2S function.
+ *  0b1..This Flexcomm includes the I2S function.
+ */
+#define FLEXCOMM_PSELID_I2SPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
+#define FLEXCOMM_PSELID_ID_MASK                  (0xFFFFF000U)
+#define FLEXCOMM_PSELID_ID_SHIFT                 (12U)
+/*! ID - Flexcomm ID.
+ */
+#define FLEXCOMM_PSELID_ID(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
+/*! @} */
+
+/*! @name PID - Peripheral identification register. */
+/*! @{ */
+#define FLEXCOMM_PID_Minor_Rev_MASK              (0xF00U)
+#define FLEXCOMM_PID_Minor_Rev_SHIFT             (8U)
+/*! Minor_Rev - Minor revision of module implementation.
+ */
+#define FLEXCOMM_PID_Minor_Rev(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)
+#define FLEXCOMM_PID_Major_Rev_MASK              (0xF000U)
+#define FLEXCOMM_PID_Major_Rev_SHIFT             (12U)
+/*! Major_Rev - Major revision of module implementation.
+ */
+#define FLEXCOMM_PID_Major_Rev(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)
+#define FLEXCOMM_PID_ID_MASK                     (0xFFFF0000U)
+#define FLEXCOMM_PID_ID_SHIFT                    (16U)
+/*! ID - Module identifier for the selected function.
+ */
+#define FLEXCOMM_PID_ID(x)                       (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FLEXCOMM_Register_Masks */
+
+
+/* FLEXCOMM - Peripheral instance base addresses */
+/** Peripheral FLEXCOMM0 base address */
+#define FLEXCOMM0_BASE                           (0x40086000u)
+/** Peripheral FLEXCOMM0 base pointer */
+#define FLEXCOMM0                                ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
+/** Peripheral FLEXCOMM1 base address */
+#define FLEXCOMM1_BASE                           (0x40087000u)
+/** Peripheral FLEXCOMM1 base pointer */
+#define FLEXCOMM1                                ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
+/** Peripheral FLEXCOMM2 base address */
+#define FLEXCOMM2_BASE                           (0x40088000u)
+/** Peripheral FLEXCOMM2 base pointer */
+#define FLEXCOMM2                                ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
+/** Peripheral FLEXCOMM3 base address */
+#define FLEXCOMM3_BASE                           (0x40089000u)
+/** Peripheral FLEXCOMM3 base pointer */
+#define FLEXCOMM3                                ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
+/** Peripheral FLEXCOMM4 base address */
+#define FLEXCOMM4_BASE                           (0x4008A000u)
+/** Peripheral FLEXCOMM4 base pointer */
+#define FLEXCOMM4                                ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
+/** Peripheral FLEXCOMM5 base address */
+#define FLEXCOMM5_BASE                           (0x40096000u)
+/** Peripheral FLEXCOMM5 base pointer */
+#define FLEXCOMM5                                ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
+/** Peripheral FLEXCOMM6 base address */
+#define FLEXCOMM6_BASE                           (0x40097000u)
+/** Peripheral FLEXCOMM6 base pointer */
+#define FLEXCOMM6                                ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
+/** Peripheral FLEXCOMM7 base address */
+#define FLEXCOMM7_BASE                           (0x40098000u)
+/** Peripheral FLEXCOMM7 base pointer */
+#define FLEXCOMM7                                ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
+/** Peripheral FLEXCOMM8 base address */
+#define FLEXCOMM8_BASE                           (0x40099000u)
+/** Peripheral FLEXCOMM8 base pointer */
+#define FLEXCOMM8                                ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
+/** Peripheral FLEXCOMM9 base address */
+#define FLEXCOMM9_BASE                           (0x4009A000u)
+/** Peripheral FLEXCOMM9 base pointer */
+#define FLEXCOMM9                                ((FLEXCOMM_Type *)FLEXCOMM9_BASE)
+/** Peripheral FLEXCOMM10 base address */
+#define FLEXCOMM10_BASE                          (0x4009F000u)
+/** Peripheral FLEXCOMM10 base pointer */
+#define FLEXCOMM10                               ((FLEXCOMM_Type *)FLEXCOMM10_BASE)
+/** Array initializer of FLEXCOMM peripheral base addresses */
+#define FLEXCOMM_BASE_ADDRS                      { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE, FLEXCOMM10_BASE }
+/** Array initializer of FLEXCOMM peripheral base pointers */
+#define FLEXCOMM_BASE_PTRS                       { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9, FLEXCOMM10 }
+/** Interrupt vectors for the FLEXCOMM peripheral type */
+#define FLEXCOMM_IRQS                            { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn, FLEXCOMM10_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FLEXCOMM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GINT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer
+ * @{
+ */
+
+/** GINT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< GPIO grouped interrupt control register, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  __IO uint32_t PORT_POL[2];                       /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_1[24];
+  __IO uint32_t PORT_ENA[2];                       /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */
+} GINT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GINT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GINT_Register_Masks GINT Register Masks
+ * @{
+ */
+
+/*! @name CTRL - GPIO grouped interrupt control register */
+/*! @{ */
+#define GINT_CTRL_INT_MASK                       (0x1U)
+#define GINT_CTRL_INT_SHIFT                      (0U)
+/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.
+ *  0b0..No request. No interrupt request is pending.
+ *  0b1..Request active. Interrupt request is active.
+ */
+#define GINT_CTRL_INT(x)                         (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)
+#define GINT_CTRL_COMB_MASK                      (0x2U)
+#define GINT_CTRL_COMB_SHIFT                     (1U)
+/*! COMB - Combine enabled inputs for group interrupt
+ *  0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).
+ *  0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).
+ */
+#define GINT_CTRL_COMB(x)                        (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)
+#define GINT_CTRL_TRIG_MASK                      (0x4U)
+#define GINT_CTRL_TRIG_SHIFT                     (2U)
+/*! TRIG - Group interrupt trigger
+ *  0b0..Edge-triggered.
+ *  0b1..Level-triggered.
+ */
+#define GINT_CTRL_TRIG(x)                        (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)
+/*! @} */
+
+/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */
+/*! @{ */
+#define GINT_PORT_POL_POL_MASK                   (0xFFFFFFFFU)
+#define GINT_PORT_POL_POL_SHIFT                  (0U)
+/*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n
+ *    of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to
+ *    the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin
+ *    contributes to the group interrupt.
+ */
+#define GINT_PORT_POL_POL(x)                     (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)
+/*! @} */
+
+/* The count of GINT_PORT_POL */
+#define GINT_PORT_POL_COUNT                      (2U)
+
+/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */
+/*! @{ */
+#define GINT_PORT_ENA_ENA_MASK                   (0xFFFFFFFFU)
+#define GINT_PORT_ENA_ENA_SHIFT                  (0U)
+/*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the
+ *    port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is
+ *    enabled and contributes to the grouped interrupt.
+ */
+#define GINT_PORT_ENA_ENA(x)                     (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)
+/*! @} */
+
+/* The count of GINT_PORT_ENA */
+#define GINT_PORT_ENA_COUNT                      (2U)
+
+
+/*!
+ * @}
+ */ /* end of group GINT_Register_Masks */
+
+
+/* GINT - Peripheral instance base addresses */
+/** Peripheral GINT0 base address */
+#define GINT0_BASE                               (0x40002000u)
+/** Peripheral GINT0 base pointer */
+#define GINT0                                    ((GINT_Type *)GINT0_BASE)
+/** Peripheral GINT1 base address */
+#define GINT1_BASE                               (0x40003000u)
+/** Peripheral GINT1 base pointer */
+#define GINT1                                    ((GINT_Type *)GINT1_BASE)
+/** Array initializer of GINT peripheral base addresses */
+#define GINT_BASE_ADDRS                          { GINT0_BASE, GINT1_BASE }
+/** Array initializer of GINT peripheral base pointers */
+#define GINT_BASE_PTRS                           { GINT0, GINT1 }
+/** Interrupt vectors for the GINT peripheral type */
+#define GINT_IRQS                                { GINT0_IRQn, GINT1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group GINT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t B[6][32];                           /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
+       uint8_t RESERVED_0[3904];
+  __IO uint32_t W[6][32];                          /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
+       uint8_t RESERVED_1[3328];
+  __IO uint32_t DIR[6];                            /**< Direction registers, array offset: 0x2000, array step: 0x4 */
+       uint8_t RESERVED_2[104];
+  __IO uint32_t MASK[6];                           /**< Mask register, array offset: 0x2080, array step: 0x4 */
+       uint8_t RESERVED_3[104];
+  __IO uint32_t PIN[6];                            /**< Port pin register, array offset: 0x2100, array step: 0x4 */
+       uint8_t RESERVED_4[104];
+  __IO uint32_t MPIN[6];                           /**< Masked port register, array offset: 0x2180, array step: 0x4 */
+       uint8_t RESERVED_5[104];
+  __IO uint32_t SET[6];                            /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
+       uint8_t RESERVED_6[104];
+  __O  uint32_t CLR[6];                            /**< Clear port, array offset: 0x2280, array step: 0x4 */
+       uint8_t RESERVED_7[104];
+  __O  uint32_t NOT[6];                            /**< Toggle port, array offset: 0x2300, array step: 0x4 */
+       uint8_t RESERVED_8[104];
+  __O  uint32_t DIRSET[6];                         /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
+       uint8_t RESERVED_9[104];
+  __O  uint32_t DIRCLR[6];                         /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
+       uint8_t RESERVED_10[104];
+  __O  uint32_t DIRNOT[6];                         /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
+/*! @{ */
+#define GPIO_B_PBYTE_MASK                        (0x1U)
+#define GPIO_B_PBYTE_SHIFT                       (0U)
+/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function,
+ *    except that pins configured as analog I/O always read as 0. One register for each port pin.
+ *    Supported pins depends on the specific device and package. Write: loads the pin's output bit.
+ *    One register for each port pin. Supported pins depends on the specific device and package.
+ */
+#define GPIO_B_PBYTE(x)                          (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
+/*! @} */
+
+/* The count of GPIO_B */
+#define GPIO_B_COUNT                             (6U)
+
+/* The count of GPIO_B */
+#define GPIO_B_COUNT2                            (32U)
+
+/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
+/*! @{ */
+#define GPIO_W_PWORD_MASK                        (0xFFFFFFFFU)
+#define GPIO_W_PWORD_SHIFT                       (0U)
+/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is
+ *    HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be
+ *    read. Writing any value other than 0 will set the output bit. One register for each port pin.
+ *    Supported pins depends on the specific device and package.
+ */
+#define GPIO_W_PWORD(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
+/*! @} */
+
+/* The count of GPIO_W */
+#define GPIO_W_COUNT                             (6U)
+
+/* The count of GPIO_W */
+#define GPIO_W_COUNT2                            (32U)
+
+/*! @name DIR - Direction registers */
+/*! @{ */
+#define GPIO_DIR_DIRP_MASK                       (0xFFFFFFFFU)
+#define GPIO_DIR_DIRP_SHIFT                      (0U)
+/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
+ *    pins depends on the specific device and package. 0 = input. 1 = output.
+ */
+#define GPIO_DIR_DIRP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
+/*! @} */
+
+/* The count of GPIO_DIR */
+#define GPIO_DIR_COUNT                           (6U)
+
+/*! @name MASK - Mask register */
+/*! @{ */
+#define GPIO_MASK_MASKP_MASK                     (0xFFFFFFFFU)
+#define GPIO_MASK_MASKP_SHIFT                    (0U)
+/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 =
+ *    PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 =
+ *    Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit
+ *    not affected.
+ */
+#define GPIO_MASK_MASKP(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
+/*! @} */
+
+/* The count of GPIO_MASK */
+#define GPIO_MASK_COUNT                          (6U)
+
+/*! @name PIN - Port pin register */
+/*! @{ */
+#define GPIO_PIN_PORT_MASK                       (0xFFFFFFFFU)
+#define GPIO_PIN_PORT_SHIFT                      (0U)
+/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
+ *    pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit.
+ *    1 = Read: pin is high; write: set output bit.
+ */
+#define GPIO_PIN_PORT(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
+/*! @} */
+
+/* The count of GPIO_PIN */
+#define GPIO_PIN_COUNT                           (6U)
+
+/*! @name MPIN - Masked port register */
+/*! @{ */
+#define GPIO_MPIN_MPORTP_MASK                    (0xFFFFFFFFU)
+#define GPIO_MPIN_MPORTP_SHIFT                   (0U)
+/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
+ *    the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK
+ *    register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1
+ *    = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit
+ *    if the corresponding bit in the MASK register is 0.
+ */
+#define GPIO_MPIN_MPORTP(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
+/*! @} */
+
+/* The count of GPIO_MPIN */
+#define GPIO_MPIN_COUNT                          (6U)
+
+/*! @name SET - Write: Set register for port Read: output bits for port */
+/*! @{ */
+#define GPIO_SET_SETP_MASK                       (0xFFFFFFFFU)
+#define GPIO_SET_SETP_SHIFT                      (0U)
+/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
+ *    the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output
+ *    bit; write: set output bit.
+ */
+#define GPIO_SET_SETP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
+/*! @} */
+
+/* The count of GPIO_SET */
+#define GPIO_SET_COUNT                           (6U)
+
+/*! @name CLR - Clear port */
+/*! @{ */
+#define GPIO_CLR_CLRP_MASK                       (0xFFFFFFFFU)
+#define GPIO_CLR_CLRP_SHIFT                      (0U)
+/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
+ *    specific device and package. 0 = No operation. 1 = Clear output bit.
+ */
+#define GPIO_CLR_CLRP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
+/*! @} */
+
+/* The count of GPIO_CLR */
+#define GPIO_CLR_COUNT                           (6U)
+
+/*! @name NOT - Toggle port */
+/*! @{ */
+#define GPIO_NOT_NOTP_MASK                       (0xFFFFFFFFU)
+#define GPIO_NOT_NOTP_SHIFT                      (0U)
+/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
+ *    specific device and package. 0 = no operation. 1 = Toggle output bit.
+ */
+#define GPIO_NOT_NOTP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
+/*! @} */
+
+/* The count of GPIO_NOT */
+#define GPIO_NOT_COUNT                           (6U)
+
+/*! @name DIRSET - Set pin direction bits for port */
+/*! @{ */
+#define GPIO_DIRSET_DIRSETP_MASK                 (0x1FFFFFFFU)
+#define GPIO_DIRSET_DIRSETP_SHIFT                (0U)
+/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
+ *    the specific device and package. 0 = No operation. 1 = Set direction bit.
+ */
+#define GPIO_DIRSET_DIRSETP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
+/*! @} */
+
+/* The count of GPIO_DIRSET */
+#define GPIO_DIRSET_COUNT                        (6U)
+
+/*! @name DIRCLR - Clear pin direction bits for port */
+/*! @{ */
+#define GPIO_DIRCLR_DIRCLRP_MASK                 (0x1FFFFFFFU)
+#define GPIO_DIRCLR_DIRCLRP_SHIFT                (0U)
+/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
+ *    the specific device and package. 0 = No operation. 1 = Clear direction bit.
+ */
+#define GPIO_DIRCLR_DIRCLRP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
+/*! @} */
+
+/* The count of GPIO_DIRCLR */
+#define GPIO_DIRCLR_COUNT                        (6U)
+
+/*! @name DIRNOT - Toggle pin direction bits for port */
+/*! @{ */
+#define GPIO_DIRNOT_DIRNOTP_MASK                 (0x1FFFFFFFU)
+#define GPIO_DIRNOT_DIRNOTP_SHIFT                (0U)
+/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends
+ *    on the specific device and package. 0 = no operation. 1 = Toggle direction bit.
+ */
+#define GPIO_DIRNOT_DIRNOTP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
+/*! @} */
+
+/* The count of GPIO_DIRNOT */
+#define GPIO_DIRNOT_COUNT                        (6U)
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIO base address */
+#define GPIO_BASE                                (0x4008C000u)
+/** Peripheral GPIO base pointer */
+#define GPIO                                     ((GPIO_Type *)GPIO_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { GPIO_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { GPIO }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[2048];
+  __IO uint32_t CFG;                               /**< Configuration for shared functions., offset: 0x800 */
+  __IO uint32_t STAT;                              /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */
+  __IO uint32_t INTENSET;                          /**< Interrupt Enable Set and read register., offset: 0x808 */
+  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear register., offset: 0x80C */
+  __IO uint32_t TIMEOUT;                           /**< Time-out value register., offset: 0x810 */
+  __IO uint32_t CLKDIV;                            /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t MSTCTL;                            /**< Master control register., offset: 0x820 */
+  __IO uint32_t MSTTIME;                           /**< Master timing configuration., offset: 0x824 */
+  __IO uint32_t MSTDAT;                            /**< Combined Master receiver and transmitter data register., offset: 0x828 */
+       uint8_t RESERVED_2[20];
+  __IO uint32_t SLVCTL;                            /**< Slave control register., offset: 0x840 */
+  __IO uint32_t SLVDAT;                            /**< Combined Slave receiver and transmitter data register., offset: 0x844 */
+  __IO uint32_t SLVADR[4];                         /**< Slave address register., array offset: 0x848, array step: 0x4 */
+  __IO uint32_t SLVQUAL0;                          /**< Slave Qualification for address 0., offset: 0x858 */
+       uint8_t RESERVED_3[36];
+  __I  uint32_t MONRXDAT;                          /**< Monitor receiver data register., offset: 0x880 */
+       uint8_t RESERVED_4[1912];
+  __I  uint32_t ID;                                /**< Peripheral identification register., offset: 0xFFC */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/*! @name CFG - Configuration for shared functions. */
+/*! @{ */
+#define I2C_CFG_MSTEN_MASK                       (0x1U)
+#define I2C_CFG_MSTEN_SHIFT                      (0U)
+/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not
+ *    changed, but the Master function is internally reset.
+ *  0b0..Disabled. The I2C Master function is disabled.
+ *  0b1..Enabled. The I2C Master function is enabled.
+ */
+#define I2C_CFG_MSTEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
+#define I2C_CFG_SLVEN_MASK                       (0x2U)
+#define I2C_CFG_SLVEN_SHIFT                      (1U)
+/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not
+ *    changed, but the Slave function is internally reset.
+ *  0b0..Disabled. The I2C slave function is disabled.
+ *  0b1..Enabled. The I2C slave function is enabled.
+ */
+#define I2C_CFG_SLVEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
+#define I2C_CFG_MONEN_MASK                       (0x4U)
+#define I2C_CFG_MONEN_SHIFT                      (2U)
+/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not
+ *    changed, but the Monitor function is internally reset.
+ *  0b0..Disabled. The I2C Monitor function is disabled.
+ *  0b1..Enabled. The I2C Monitor function is enabled.
+ */
+#define I2C_CFG_MONEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
+#define I2C_CFG_TIMEOUTEN_MASK                   (0x8U)
+#define I2C_CFG_TIMEOUTEN_SHIFT                  (3U)
+/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
+ *  0b0..Disabled. Time-out function is disabled.
+ *  0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause
+ *       interrupts if they are enabled. Typically, only one time-out will be used in a system.
+ */
+#define I2C_CFG_TIMEOUTEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
+#define I2C_CFG_MONCLKSTR_MASK                   (0x10U)
+#define I2C_CFG_MONCLKSTR_SHIFT                  (4U)
+/*! MONCLKSTR - Monitor function Clock Stretching.
+ *  0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able
+ *       to read data provided by the Monitor function before it is overwritten. This mode may be used when
+ *       non-invasive monitoring is critical.
+ *  0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can
+ *       read all incoming data supplied by the Monitor function.
+ */
+#define I2C_CFG_MONCLKSTR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
+#define I2C_CFG_HSCAPABLE_MASK                   (0x20U)
+#define I2C_CFG_HSCAPABLE_SHIFT                  (5U)
+/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive
+ *    and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies
+ *    to all functions: Master, Slave, and Monitor.
+ *  0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the
+ *       extent that the pin electronics support these modes. Any changes that need to be made to the pin controls,
+ *       such as changing the drive strength or filtering, must be made by software via the IOCON register associated
+ *       with each I2C pin,
+ *  0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support
+ *       High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more
+ *       information.
+ */
+#define I2C_CFG_HSCAPABLE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
+/*! @} */
+
+/*! @name STAT - Status register for Master, Slave, and Monitor functions. */
+/*! @{ */
+#define I2C_STAT_MSTPENDING_MASK                 (0x1U)
+#define I2C_STAT_MSTPENDING_SHIFT                (0U)
+/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on
+ *    the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what
+ *    type of software service if any the master expects. This flag will cause an interrupt when set
+ *    if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling
+ *    an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle
+ *    state, and no communication is needed, mask this interrupt.
+ *  0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
+ *  0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the
+ *       idle state, it is waiting to receive or transmit data or the NACK bit.
+ */
+#define I2C_STAT_MSTPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
+#define I2C_STAT_MSTSTATE_MASK                   (0xEU)
+#define I2C_STAT_MSTSTATE_SHIFT                  (1U)
+/*! MSTSTATE - Master State code. The master state code reflects the master state when the
+ *    MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field
+ *    indicates a specific required service for the Master function. All other values are reserved. See
+ *    Table 400 for details of state values and appropriate responses.
+ *  0b000..Idle. The Master function is available to be used for a new transaction.
+ *  0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
+ *  0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
+ *  0b011..NACK Address. Slave NACKed address.
+ *  0b100..NACK Data. Slave NACKed transmitted data.
+ */
+#define I2C_STAT_MSTSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
+#define I2C_STAT_MSTARBLOSS_MASK                 (0x10U)
+#define I2C_STAT_MSTARBLOSS_SHIFT                (4U)
+/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to
+ *    this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
+ *  0b0..No Arbitration Loss has occurred.
+ *  0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master
+ *       function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing,
+ *       or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
+ */
+#define I2C_STAT_MSTARBLOSS(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
+#define I2C_STAT_MSTSTSTPERR_MASK                (0x40U)
+#define I2C_STAT_MSTSTSTPERR_SHIFT               (6U)
+/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to
+ *    this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
+ *  0b0..No Start/Stop Error has occurred.
+ *  0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is
+ *       not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an
+ *       idle state, no action is required. A request for a Start could be made, or software could attempt to insure
+ *       that the bus has not stalled.
+ */
+#define I2C_STAT_MSTSTSTPERR(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
+#define I2C_STAT_SLVPENDING_MASK                 (0x100U)
+#define I2C_STAT_SLVPENDING_SHIFT                (8U)
+/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue
+ *    communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if
+ *    enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the
+ *    SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is
+ *    automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time
+ *    when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section
+ *    25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are
+ *    detected automatically. Due to the requirements of the HS I2C specification, slave addresses must
+ *    also be detected automatically, since the address must be acknowledged before the clock can be
+ *    stretched.
+ *  0b0..In progress. The Slave function does not currently need service.
+ *  0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
+ */
+#define I2C_STAT_SLVPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
+#define I2C_STAT_SLVSTATE_MASK                   (0x600U)
+#define I2C_STAT_SLVSTATE_SHIFT                  (9U)
+/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for
+ *    the Slave function. All other values are reserved. See Table 401 for state values and actions.
+ *    note that the occurrence of some states and how they are handled are affected by DMA mode and
+ *    Automatic Operation modes.
+ *  0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
+ *  0b01..Slave receive. Received data is available (Slave Receiver mode).
+ *  0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode).
+ */
+#define I2C_STAT_SLVSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
+#define I2C_STAT_SLVNOTSTR_MASK                  (0x800U)
+#define I2C_STAT_SLVNOTSTR_SHIFT                 (11U)
+/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock.
+ *    This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave
+ *    operation. This read-only flag reflects the slave function status in real time.
+ *  0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
+ *  0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or
+ *       Power-down mode could be entered at this time.
+ */
+#define I2C_STAT_SLVNOTSTR(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
+#define I2C_STAT_SLVIDX_MASK                     (0x3000U)
+#define I2C_STAT_SLVIDX_SHIFT                    (12U)
+/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been
+ *    selected by receiving an address that matches one of the slave addresses defined by any enabled
+ *    slave address registers, and provides an identification of the address that was matched. It is
+ *    possible that more than one address could be matched, but only one match can be reported here.
+ *  0b00..Address 0. Slave address 0 was matched.
+ *  0b01..Address 1. Slave address 1 was matched.
+ *  0b10..Address 2. Slave address 2 was matched.
+ *  0b11..Address 3. Slave address 3 was matched.
+ */
+#define I2C_STAT_SLVIDX(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
+#define I2C_STAT_SLVSEL_MASK                     (0x4000U)
+#define I2C_STAT_SLVSEL_SHIFT                    (14U)
+/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave
+ *    function to acknowledge the address, or when the address has been automatically acknowledged.
+ *    It is cleared when another address cycle presents an address that does not match an enabled
+ *    address on the Slave function, when slave software decides to NACK a matched address, when
+ *    there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of
+ *    Automatic Operation. SLVSEL is not cleared if software NACKs data.
+ *  0b0..Not selected. The Slave function is not currently selected.
+ *  0b1..Selected. The Slave function is currently selected.
+ */
+#define I2C_STAT_SLVSEL(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
+#define I2C_STAT_SLVDESEL_MASK                   (0x8000U)
+#define I2C_STAT_SLVDESEL_SHIFT                  (15U)
+/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via
+ *    INTENSET. This flag can be cleared by writing a 1 to this bit.
+ *  0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently
+ *       selected. That information can be found in the SLVSEL flag.
+ *  0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag
+ *       changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
+ */
+#define I2C_STAT_SLVDESEL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
+#define I2C_STAT_MONRDY_MASK                     (0x10000U)
+#define I2C_STAT_MONRDY_SHIFT                    (16U)
+/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read.
+ *  0b0..No data. The Monitor function does not currently have data available.
+ *  0b1..Data waiting. The Monitor function has data waiting to be read.
+ */
+#define I2C_STAT_MONRDY(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
+#define I2C_STAT_MONOV_MASK                      (0x20000U)
+#define I2C_STAT_MONOV_SHIFT                     (17U)
+/*! MONOV - Monitor Overflow flag.
+ *  0b0..No overrun. Monitor data has not overrun.
+ *  0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not
+ *       enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
+ */
+#define I2C_STAT_MONOV(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
+#define I2C_STAT_MONACTIVE_MASK                  (0x40000U)
+#define I2C_STAT_MONACTIVE_SHIFT                 (18U)
+/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to
+ *    be active. Active is defined here as when some Master is on the bus: a bus Start has occurred
+ *    more recently than a bus Stop.
+ *  0b0..Inactive. The Monitor function considers the I2C bus to be inactive.
+ *  0b1..Active. The Monitor function considers the I2C bus to be active.
+ */
+#define I2C_STAT_MONACTIVE(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
+#define I2C_STAT_MONIDLE_MASK                    (0x80000U)
+#define I2C_STAT_MONIDLE_SHIFT                   (19U)
+/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change
+ *    from active to inactive. This can be used by software to decide when to process data
+ *    accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the
+ *    INTENSET register. The flag can be cleared by writing a 1 to this bit.
+ *  0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software.
+ *  0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
+ */
+#define I2C_STAT_MONIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
+#define I2C_STAT_EVENTTIMEOUT_MASK               (0x1000000U)
+#define I2C_STAT_EVENTTIMEOUT_SHIFT              (24U)
+/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been
+ *    longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock
+ *    edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus
+ *    is idle.
+ *  0b0..No time-out. I2C bus events have not caused a time-out.
+ *  0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
+ */
+#define I2C_STAT_EVENTTIMEOUT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
+#define I2C_STAT_SCLTIMEOUT_MASK                 (0x2000000U)
+#define I2C_STAT_SCLTIMEOUT_SHIFT                (25U)
+/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the
+ *    time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
+ *  0b0..No time-out. SCL low time has not caused a time-out.
+ *  0b1..Time-out. SCL low time has caused a time-out.
+ */
+#define I2C_STAT_SCLTIMEOUT(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
+/*! @} */
+
+/*! @name INTENSET - Interrupt Enable Set and read register. */
+/*! @{ */
+#define I2C_INTENSET_MSTPENDINGEN_MASK           (0x1U)
+#define I2C_INTENSET_MSTPENDINGEN_SHIFT          (0U)
+/*! MSTPENDINGEN - Master Pending interrupt Enable.
+ *  0b0..Disabled. The MstPending interrupt is disabled.
+ *  0b1..Enabled. The MstPending interrupt is enabled.
+ */
+#define I2C_INTENSET_MSTPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
+#define I2C_INTENSET_MSTARBLOSSEN_MASK           (0x10U)
+#define I2C_INTENSET_MSTARBLOSSEN_SHIFT          (4U)
+/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable.
+ *  0b0..Disabled. The MstArbLoss interrupt is disabled.
+ *  0b1..Enabled. The MstArbLoss interrupt is enabled.
+ */
+#define I2C_INTENSET_MSTARBLOSSEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
+#define I2C_INTENSET_MSTSTSTPERREN_MASK          (0x40U)
+#define I2C_INTENSET_MSTSTSTPERREN_SHIFT         (6U)
+/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable.
+ *  0b0..Disabled. The MstStStpErr interrupt is disabled.
+ *  0b1..Enabled. The MstStStpErr interrupt is enabled.
+ */
+#define I2C_INTENSET_MSTSTSTPERREN(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
+#define I2C_INTENSET_SLVPENDINGEN_MASK           (0x100U)
+#define I2C_INTENSET_SLVPENDINGEN_SHIFT          (8U)
+/*! SLVPENDINGEN - Slave Pending interrupt Enable.
+ *  0b0..Disabled. The SlvPending interrupt is disabled.
+ *  0b1..Enabled. The SlvPending interrupt is enabled.
+ */
+#define I2C_INTENSET_SLVPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
+#define I2C_INTENSET_SLVNOTSTREN_MASK            (0x800U)
+#define I2C_INTENSET_SLVNOTSTREN_SHIFT           (11U)
+/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable.
+ *  0b0..Disabled. The SlvNotStr interrupt is disabled.
+ *  0b1..Enabled. The SlvNotStr interrupt is enabled.
+ */
+#define I2C_INTENSET_SLVNOTSTREN(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
+#define I2C_INTENSET_SLVDESELEN_MASK             (0x8000U)
+#define I2C_INTENSET_SLVDESELEN_SHIFT            (15U)
+/*! SLVDESELEN - Slave Deselect interrupt Enable.
+ *  0b0..Disabled. The SlvDeSel interrupt is disabled.
+ *  0b1..Enabled. The SlvDeSel interrupt is enabled.
+ */
+#define I2C_INTENSET_SLVDESELEN(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
+#define I2C_INTENSET_MONRDYEN_MASK               (0x10000U)
+#define I2C_INTENSET_MONRDYEN_SHIFT              (16U)
+/*! MONRDYEN - Monitor data Ready interrupt Enable.
+ *  0b0..Disabled. The MonRdy interrupt is disabled.
+ *  0b1..Enabled. The MonRdy interrupt is enabled.
+ */
+#define I2C_INTENSET_MONRDYEN(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
+#define I2C_INTENSET_MONOVEN_MASK                (0x20000U)
+#define I2C_INTENSET_MONOVEN_SHIFT               (17U)
+/*! MONOVEN - Monitor Overrun interrupt Enable.
+ *  0b0..Disabled. The MonOv interrupt is disabled.
+ *  0b1..Enabled. The MonOv interrupt is enabled.
+ */
+#define I2C_INTENSET_MONOVEN(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
+#define I2C_INTENSET_MONIDLEEN_MASK              (0x80000U)
+#define I2C_INTENSET_MONIDLEEN_SHIFT             (19U)
+/*! MONIDLEEN - Monitor Idle interrupt Enable.
+ *  0b0..Disabled. The MonIdle interrupt is disabled.
+ *  0b1..Enabled. The MonIdle interrupt is enabled.
+ */
+#define I2C_INTENSET_MONIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
+#define I2C_INTENSET_EVENTTIMEOUTEN_MASK         (0x1000000U)
+#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT        (24U)
+/*! EVENTTIMEOUTEN - Event time-out interrupt Enable.
+ *  0b0..Disabled. The Event time-out interrupt is disabled.
+ *  0b1..Enabled. The Event time-out interrupt is enabled.
+ */
+#define I2C_INTENSET_EVENTTIMEOUTEN(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
+#define I2C_INTENSET_SCLTIMEOUTEN_MASK           (0x2000000U)
+#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT          (25U)
+/*! SCLTIMEOUTEN - SCL time-out interrupt Enable.
+ *  0b0..Disabled. The SCL time-out interrupt is disabled.
+ *  0b1..Enabled. The SCL time-out interrupt is enabled.
+ */
+#define I2C_INTENSET_SCLTIMEOUTEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
+/*! @} */
+
+/*! @name INTENCLR - Interrupt Enable Clear register. */
+/*! @{ */
+#define I2C_INTENCLR_MSTPENDINGCLR_MASK          (0x1U)
+#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT         (0U)
+/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding
+ *    bit in the INTENSET register if implemented.
+ */
+#define I2C_INTENCLR_MSTPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
+#define I2C_INTENCLR_MSTARBLOSSCLR_MASK          (0x10U)
+#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT         (4U)
+/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear.
+ */
+#define I2C_INTENCLR_MSTARBLOSSCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
+#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK         (0x40U)
+#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT        (6U)
+/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear.
+ */
+#define I2C_INTENCLR_MSTSTSTPERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
+#define I2C_INTENCLR_SLVPENDINGCLR_MASK          (0x100U)
+#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT         (8U)
+/*! SLVPENDINGCLR - Slave Pending interrupt clear.
+ */
+#define I2C_INTENCLR_SLVPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
+#define I2C_INTENCLR_SLVNOTSTRCLR_MASK           (0x800U)
+#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT          (11U)
+/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear.
+ */
+#define I2C_INTENCLR_SLVNOTSTRCLR(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
+#define I2C_INTENCLR_SLVDESELCLR_MASK            (0x8000U)
+#define I2C_INTENCLR_SLVDESELCLR_SHIFT           (15U)
+/*! SLVDESELCLR - Slave Deselect interrupt clear.
+ */
+#define I2C_INTENCLR_SLVDESELCLR(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
+#define I2C_INTENCLR_MONRDYCLR_MASK              (0x10000U)
+#define I2C_INTENCLR_MONRDYCLR_SHIFT             (16U)
+/*! MONRDYCLR - Monitor data Ready interrupt clear.
+ */
+#define I2C_INTENCLR_MONRDYCLR(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
+#define I2C_INTENCLR_MONOVCLR_MASK               (0x20000U)
+#define I2C_INTENCLR_MONOVCLR_SHIFT              (17U)
+/*! MONOVCLR - Monitor Overrun interrupt clear.
+ */
+#define I2C_INTENCLR_MONOVCLR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
+#define I2C_INTENCLR_MONIDLECLR_MASK             (0x80000U)
+#define I2C_INTENCLR_MONIDLECLR_SHIFT            (19U)
+/*! MONIDLECLR - Monitor Idle interrupt clear.
+ */
+#define I2C_INTENCLR_MONIDLECLR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK        (0x1000000U)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT       (24U)
+/*! EVENTTIMEOUTCLR - Event time-out interrupt clear.
+ */
+#define I2C_INTENCLR_EVENTTIMEOUTCLR(x)          (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
+#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK          (0x2000000U)
+#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT         (25U)
+/*! SCLTIMEOUTCLR - SCL time-out interrupt clear.
+ */
+#define I2C_INTENCLR_SCLTIMEOUTCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
+/*! @} */
+
+/*! @name TIMEOUT - Time-out value register. */
+/*! @{ */
+#define I2C_TIMEOUT_TOMIN_MASK                   (0xFU)
+#define I2C_TIMEOUT_TOMIN_SHIFT                  (0U)
+/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum
+ *    time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
+ */
+#define I2C_TIMEOUT_TOMIN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
+#define I2C_TIMEOUT_TO_MASK                      (0xFFF0U)
+#define I2C_TIMEOUT_TO_SHIFT                     (4U)
+/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C
+ *    function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation,
+ *    disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A
+ *    time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after
+ *    32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the
+ *    I2C function clock.
+ */
+#define I2C_TIMEOUT_TO(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
+/*! @} */
+
+/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */
+/*! @{ */
+#define I2C_CLKDIV_DIVVAL_MASK                   (0xFFFFU)
+#define I2C_CLKDIV_DIVVAL_SHIFT                  (0U)
+/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that
+ *    need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 =
+ *    FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is
+ *    divided by 65,536 before use.
+ */
+#define I2C_CLKDIV_DIVVAL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
+/*! @{ */
+#define I2C_INTSTAT_MSTPENDING_MASK              (0x1U)
+#define I2C_INTSTAT_MSTPENDING_SHIFT             (0U)
+/*! MSTPENDING - Master Pending.
+ */
+#define I2C_INTSTAT_MSTPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
+#define I2C_INTSTAT_MSTARBLOSS_MASK              (0x10U)
+#define I2C_INTSTAT_MSTARBLOSS_SHIFT             (4U)
+/*! MSTARBLOSS - Master Arbitration Loss flag.
+ */
+#define I2C_INTSTAT_MSTARBLOSS(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
+#define I2C_INTSTAT_MSTSTSTPERR_MASK             (0x40U)
+#define I2C_INTSTAT_MSTSTSTPERR_SHIFT            (6U)
+/*! MSTSTSTPERR - Master Start/Stop Error flag.
+ */
+#define I2C_INTSTAT_MSTSTSTPERR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
+#define I2C_INTSTAT_SLVPENDING_MASK              (0x100U)
+#define I2C_INTSTAT_SLVPENDING_SHIFT             (8U)
+/*! SLVPENDING - Slave Pending.
+ */
+#define I2C_INTSTAT_SLVPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
+#define I2C_INTSTAT_SLVNOTSTR_MASK               (0x800U)
+#define I2C_INTSTAT_SLVNOTSTR_SHIFT              (11U)
+/*! SLVNOTSTR - Slave Not Stretching status.
+ */
+#define I2C_INTSTAT_SLVNOTSTR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
+#define I2C_INTSTAT_SLVDESEL_MASK                (0x8000U)
+#define I2C_INTSTAT_SLVDESEL_SHIFT               (15U)
+/*! SLVDESEL - Slave Deselected flag.
+ */
+#define I2C_INTSTAT_SLVDESEL(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
+#define I2C_INTSTAT_MONRDY_MASK                  (0x10000U)
+#define I2C_INTSTAT_MONRDY_SHIFT                 (16U)
+/*! MONRDY - Monitor Ready.
+ */
+#define I2C_INTSTAT_MONRDY(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
+#define I2C_INTSTAT_MONOV_MASK                   (0x20000U)
+#define I2C_INTSTAT_MONOV_SHIFT                  (17U)
+/*! MONOV - Monitor Overflow flag.
+ */
+#define I2C_INTSTAT_MONOV(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
+#define I2C_INTSTAT_MONIDLE_MASK                 (0x80000U)
+#define I2C_INTSTAT_MONIDLE_SHIFT                (19U)
+/*! MONIDLE - Monitor Idle flag.
+ */
+#define I2C_INTSTAT_MONIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
+#define I2C_INTSTAT_EVENTTIMEOUT_MASK            (0x1000000U)
+#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT           (24U)
+/*! EVENTTIMEOUT - Event time-out Interrupt flag.
+ */
+#define I2C_INTSTAT_EVENTTIMEOUT(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
+#define I2C_INTSTAT_SCLTIMEOUT_MASK              (0x2000000U)
+#define I2C_INTSTAT_SCLTIMEOUT_SHIFT             (25U)
+/*! SCLTIMEOUT - SCL time-out Interrupt flag.
+ */
+#define I2C_INTSTAT_SCLTIMEOUT(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
+/*! @} */
+
+/*! @name MSTCTL - Master control register. */
+/*! @{ */
+#define I2C_MSTCTL_MSTCONTINUE_MASK              (0x1U)
+#define I2C_MSTCTL_MSTCONTINUE_SHIFT             (0U)
+/*! MSTCONTINUE - Master Continue. This bit is write-only.
+ *  0b0..No effect.
+ *  0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing
+ *       transmit data, reading received data, or any other housekeeping related to the next bus operation.
+ */
+#define I2C_MSTCTL_MSTCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
+#define I2C_MSTCTL_MSTSTART_MASK                 (0x2U)
+#define I2C_MSTCTL_MSTSTART_SHIFT                (1U)
+/*! MSTSTART - Master Start control. This bit is write-only.
+ *  0b0..No effect.
+ *  0b1..Start. A Start will be generated on the I2C bus at the next allowed time.
+ */
+#define I2C_MSTCTL_MSTSTART(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
+#define I2C_MSTCTL_MSTSTOP_MASK                  (0x4U)
+#define I2C_MSTCTL_MSTSTOP_SHIFT                 (2U)
+/*! MSTSTOP - Master Stop control. This bit is write-only.
+ *  0b0..No effect.
+ *  0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave
+ *       if the master is receiving data from the slave (Master Receiver mode).
+ */
+#define I2C_MSTCTL_MSTSTOP(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
+#define I2C_MSTCTL_MSTDMA_MASK                   (0x8U)
+#define I2C_MSTCTL_MSTDMA_SHIFT                  (3U)
+/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type
+ *    operations such as Start, address, Stop, and address match must always be done with software,
+ *    typically via an interrupt. Address acknowledgement must also be done by software except when
+ *    the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by
+ *    hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA
+ *    must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is
+ *    read/write.
+ *  0b0..Disable. No DMA requests are generated for master operation.
+ *  0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating
+ *       Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
+ */
+#define I2C_MSTCTL_MSTDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
+/*! @} */
+
+/*! @name MSTTIME - Master timing configuration. */
+/*! @{ */
+#define I2C_MSTTIME_MSTSCLLOW_MASK               (0x7U)
+#define I2C_MSTTIME_MSTSCLLOW_SHIFT              (0U)
+/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this
+ *    master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This
+ *    corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters
+ *    tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.
+ *  0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
+ *  0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
+ *  0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
+ *  0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
+ *  0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
+ *  0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
+ *  0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
+ *  0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
+ */
+#define I2C_MSTTIME_MSTSCLLOW(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
+#define I2C_MSTTIME_MSTSCLHIGH_MASK              (0x70U)
+#define I2C_MSTTIME_MSTSCLHIGH_SHIFT             (4U)
+/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this
+ *    master on SCL. Other masters in a multi-master system could shorten this time. This
+ *    corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters
+ *    tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.
+ *  0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
+ *  0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
+ *  0b0