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1/*
2** ###################################################################
3** Processors: LPC54S016JBD100
4** LPC54S016JBD208
5** LPC54S016JET180
6**
7** Compilers: GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9** Keil ARM C/C++ Compiler
10** MCUXpresso Compiler
11**
12** Reference manual: LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
13** Version: rev. 1.0, 2018-04-20
14** Build: b200304
15**
16** Abstract:
17** CMSIS Peripheral Access Layer for LPC54S016
18**
19** Copyright 1997-2016 Freescale Semiconductor, Inc.
20** Copyright 2016-2020 NXP
21** All rights reserved.
22**
23** SPDX-License-Identifier: BSD-3-Clause
24**
25** http: www.nxp.com
26** mail: [email protected]
27**
28** Revisions:
29** - rev. 1.0 (2018-04-20)
30** Initial version.
31**
32** ###################################################################
33*/
34
35/*!
36 * @file LPC54S016.h
37 * @version 1.0
38 * @date 2018-04-20
39 * @brief CMSIS Peripheral Access Layer for LPC54S016
40 *
41 * CMSIS Peripheral Access Layer for LPC54S016
42 */
43
44#ifndef _LPC54S016_H_
45#define _LPC54S016_H_ /**< Symbol preventing repeated inclusion */
46
47/** Memory map major version (memory maps with equal major version number are
48 * compatible) */
49#define MCU_MEM_MAP_VERSION 0x0100U
50/** Memory map minor version */
51#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
52
53
54/* ----------------------------------------------------------------------------
55 -- Interrupt vector numbers
56 ---------------------------------------------------------------------------- */
57
58/*!
59 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
60 * @{
61 */
62
63/** Interrupt Number Definitions */
64#define NUMBER_OF_INT_VECTORS 75 /**< Number of interrupts in the Vector table */
65
66typedef enum IRQn {
67 /* Auxiliary constants */
68 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
69
70 /* Core interrupts */
71 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
72 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
73 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
74 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
75 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
76 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
77 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
78 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
79 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
80
81 /* Device specific interrupts */
82 WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */
83 DMA0_IRQn = 1, /**< DMA controller */
84 GINT0_IRQn = 2, /**< GPIO group 0 */
85 GINT1_IRQn = 3, /**< GPIO group 1 */
86 PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */
87 PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */
88 PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */
89 PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */
90 UTICK0_IRQn = 8, /**< Micro-tick Timer */
91 MRT0_IRQn = 9, /**< Multi-rate timer */
92 CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
93 CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
94 SCT0_IRQn = 12, /**< SCTimer/PWM */
95 CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
96 FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
97 FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
98 FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
99 FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
100 FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
101 FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
102 FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
103 FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
104 ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */
105 ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */
106 ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */
107 DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */
108 HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */
109 USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */
110 USB0_IRQn = 28, /**< USB device */
111 RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */
112 FLEXCOMM10_IRQn = 30, /**< Flexcomm Interface 10 (SPI, FLEXCOMM) */
113 Reserved47_IRQn = 31, /**< Reserved interrupt */
114 PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */
115 PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */
116 PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */
117 PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */
118 CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */
119 CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */
120 RIT_IRQn = 38, /**< Repetitive Interrupt Timer */
121 SPIFI0_IRQn = 39, /**< SPI flash interface */
122 FLEXCOMM8_IRQn = 40, /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
123 FLEXCOMM9_IRQn = 41, /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
124 SDIO_IRQn = 42, /**< SD/MMC */
125 CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */
126 CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */
127 CAN1_IRQ0_IRQn = 45, /**< CAN1 interrupt0 */
128 CAN1_IRQ1_IRQn = 46, /**< CAN1 interrupt1 */
129 USB1_IRQn = 47, /**< USB1 interrupt */
130 USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */
131 ETHERNET_IRQn = 49, /**< Ethernet */
132 ETHERNET_PMT_IRQn = 50, /**< Ethernet power management interrupt */
133 ETHERNET_MACLP_IRQn = 51, /**< Ethernet MAC interrupt */
134 Reserved68_IRQn = 52, /**< Reserved interrupt */
135 LCD_IRQn = 53, /**< LCD interrupt */
136 SHA_IRQn = 54, /**< SHA interrupt */
137 SMARTCARD0_IRQn = 55, /**< Smart card 0 interrupt */
138 SMARTCARD1_IRQn = 56, /**< Smart card 1 interrupt */
139 Reserved73_IRQn = 57, /**< Reserved interrupt */
140 PUF_IRQn = 58 /**< PUF interrupt */
141} IRQn_Type;
142
143/*!
144 * @}
145 */ /* end of group Interrupt_vector_numbers */
146
147
148/* ----------------------------------------------------------------------------
149 -- Cortex M4 Core Configuration
150 ---------------------------------------------------------------------------- */
151
152/*!
153 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
154 * @{
155 */
156
157#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
158#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
159#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
160#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
161
162#include "core_cm4.h" /* Core Peripheral Access Layer */
163#include "system_LPC54S016.h" /* Device specific configuration file */
164
165/*!
166 * @}
167 */ /* end of group Cortex_Core_Configuration */
168
169
170/* ----------------------------------------------------------------------------
171 -- Mapping Information
172 ---------------------------------------------------------------------------- */
173
174/*!
175 * @addtogroup Mapping_Information Mapping Information
176 * @{
177 */
178
179/** Mapping Information */
180/*!
181 * @addtogroup dma_request
182 * @{
183 */
184
185/*******************************************************************************
186 * Definitions
187 ******************************************************************************/
188
189/*!
190 * @brief Structure for the DMA hardware request
191 *
192 * Defines the structure for the DMA hardware request collections. The user can configure the
193 * hardware request to trigger the DMA transfer accordingly. The index
194 * of the hardware request varies according to the to SoC.
195 */
196typedef enum _dma_request_source
197{
198 kDmaRequestFlexcomm0Rx = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */
199 kDmaRequestFlexcomm0Tx = 1U, /**< Flexcomm Interface 0 TX/I2C Master */
200 kDmaRequestFlexcomm1Rx = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */
201 kDmaRequestFlexcomm1Tx = 3U, /**< Flexcomm Interface 1 TX/I2C Master */
202 kDmaRequestFlexcomm2Rx = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */
203 kDmaRequestFlexcomm2Tx = 5U, /**< Flexcomm Interface 2 TX/I2C Master */
204 kDmaRequestFlexcomm3Rx = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */
205 kDmaRequestFlexcomm3Tx = 7U, /**< Flexcomm Interface 3 TX/I2C Master */
206 kDmaRequestFlexcomm4Rx = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */
207 kDmaRequestFlexcomm4Tx = 9U, /**< Flexcomm Interface 4 TX/I2C Master */
208 kDmaRequestFlexcomm5Rx = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */
209 kDmaRequestFlexcomm5Tx = 11U, /**< Flexcomm Interface 5 TX/I2C Master */
210 kDmaRequestFlexcomm6Rx = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */
211 kDmaRequestFlexcomm6Tx = 13U, /**< Flexcomm Interface 6 TX/I2C Master */
212 kDmaRequestFlexcomm7Rx = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */
213 kDmaRequestFlexcomm7Tx = 15U, /**< Flexcomm Interface 7 TX/I2C Master */
214 kDmaRequestDMIC0 = 16U, /**< Digital microphone interface 0 channel 0 */
215 kDmaRequestDMIC1 = 17U, /**< Digital microphone interface 0 channel 1 */
216 kDmaRequestSPIFI = 18U, /**< SPI Flash Interface */
217 kDmaRequestSHA = 19U, /**< Secure Hash Algorithm */
218 kDmaRequestFlexcomm8Rx = 20U, /**< Flexcomm Interface 8 RX/I2C Slave */
219 kDmaRequestFlexcomm8Tx = 21U, /**< Flexcomm Interface 8 TX/I2C Slave */
220 kDmaRequestFlexcomm9Rx = 22U, /**< Flexcomm Interface 9 RX/I2C Slave */
221 kDmaRequestFlexcomm9Tx = 23U, /**< Flexcomm Interface 9 TX/I2C Slave */
222 kDmaRequestSMARTCARD0_RX = 24U, /**< SMARTCARD0 RX */
223 kDmaRequestSMARTCARD0_TX = 25U, /**< SMARTCARD0 TX */
224 kDmaRequestSMARTCARD1_RX = 26U, /**< SMARTCARD1 RX */
225 kDmaRequestSMARTCARD1_TX = 27U, /**< SMARTCARD1 TX */
226 kDmaRequestFlexcomm10Rx = 28U, /**< Flexcomm Interface 10 RX */
227 kDmaRequestFlexcomm10Tx = 29U, /**< Flexcomm Interface 10 TX */
228} dma_request_source_t;
229
230/* @} */
231
232
233/*!
234 * @}
235 */ /* end of group Mapping_Information */
236
237
238/* ----------------------------------------------------------------------------
239 -- Device Peripheral Access Layer
240 ---------------------------------------------------------------------------- */
241
242/*!
243 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
244 * @{
245 */
246
247
248/*
249** Start of section using anonymous unions
250*/
251
252#if defined(__ARMCC_VERSION)
253 #if (__ARMCC_VERSION >= 6010050)
254 #pragma clang diagnostic push
255 #else
256 #pragma push
257 #pragma anon_unions
258 #endif
259#elif defined(__GNUC__)
260 /* anonymous unions are enabled by default */
261#elif defined(__IAR_SYSTEMS_ICC__)
262 #pragma language=extended
263#else
264 #error Not supported compiler type
265#endif
266
267/* ----------------------------------------------------------------------------
268 -- ADC Peripheral Access Layer
269 ---------------------------------------------------------------------------- */
270
271/*!
272 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
273 * @{
274 */
275
276/** ADC - Register Layout Typedef */
277typedef struct {
278 __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
279 __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
280 __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
281 __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
282 uint8_t RESERVED_0[8];
283 __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
284 __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
285 __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
286 __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
287 __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
288 __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
289 __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
290 __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
291 __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */
292 __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */
293} ADC_Type;
294
295/* ----------------------------------------------------------------------------
296 -- ADC Register Masks
297 ---------------------------------------------------------------------------- */
298
299/*!
300 * @addtogroup ADC_Register_Masks ADC Register Masks
301 * @{
302 */
303
304/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
305/*! @{ */
306#define ADC_CTRL_CLKDIV_MASK (0xFFU)
307#define ADC_CTRL_CLKDIV_SHIFT (0U)
308/*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce
309 * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically,
310 * software should program the smallest value in this field that yields this maximum clock rate or
311 * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may
312 * be desirable. This field is ignored in the asynchronous operating mode.
313 */
314#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
315#define ADC_CTRL_ASYNMODE_MASK (0x100U)
316#define ADC_CTRL_ASYNMODE_SHIFT (8U)
317/*! ASYNMODE - Select clock mode.
318 * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in
319 * the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to
320 * eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger.
321 * In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC
322 * input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger
323 * pulse.
324 * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
325 */
326#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
327#define ADC_CTRL_RESOL_MASK (0x600U)
328#define ADC_CTRL_RESOL_SHIFT (9U)
329/*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher
330 * conversion rates. A single conversion (including one conversion in a burst or sequence) requires the
331 * selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when
332 * the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable
333 * results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate
334 * for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system
335 * clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution
336 * 0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field.
337 * 0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field.
338 * 0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field.
339 * 0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field.
340 */
341#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
342#define ADC_CTRL_BYPASSCAL_MASK (0x800U)
343#define ADC_CTRL_BYPASSCAL_SHIFT (11U)
344/*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset
345 * error is not a concern in the application.
346 * 0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for
347 * offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may
348 * be warranted periodically - especially if operating conditions have changed.
349 * 0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC -
350 * particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set.
351 */
352#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
353#define ADC_CTRL_TSAMP_MASK (0x7000U)
354#define ADC_CTRL_TSAMP_SHIFT (12U)
355/*! TSAMP - Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion
356 * is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions
357 * and the output impedance of the analog source, longer sampling times may be required. See
358 * Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to
359 * seven, by which the sample period will be extended. The total conversion time will increase by
360 * the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A
361 * complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will
362 * be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will
363 * require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock
364 * cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be
365 * extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require
366 * 22 ADC clocks.
367 */
368#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
369/*! @} */
370
371/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
372/*! @{ */
373#define ADC_INSEL_SEL_MASK (0x3U)
374#define ADC_INSEL_SEL_SHIFT (0U)
375/*! SEL - Selects the input source for channel 0. All other values are reserved.
376 * 0b00..ADC0_IN0 function.
377 * 0b11..Internal temperature sensor.
378 */
379#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
380/*! @} */
381
382/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
383/*! @{ */
384#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU)
385#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U)
386/*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this
387 * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be
388 * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1
389 * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via
390 * software command, ADC conversions will be performed on each enabled channel, in sequence,
391 * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31)
392 * is LOW. It is allowed to change this field and set bit 31 in the same write.
393 */
394#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
395#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U)
396#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U)
397/*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion
398 * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order
399 * to avoid generating a spurious trigger, it is recommended writing to this field only when
400 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
401 */
402#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
403#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U)
404#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U)
405/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In
406 * order to avoid generating a spurious trigger, it is recommended writing to this field only when
407 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
408 * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
409 * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
410 */
411#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
412#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U)
413#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U)
414/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization
415 * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a
416 * conversion. There are slightly different criteria for whether or not this bit can be set
417 * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0):
418 * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already
419 * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer).
420 * Whether this bit is set or not, a trigger pulse must be maintained for at least one system
421 * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be
422 * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse
423 * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and
424 * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be
425 * maintained for one system clock period.
426 * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled.
427 * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled.
428 */
429#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
430#define ADC_SEQ_CTRL_START_MASK (0x4000000U)
431#define ADC_SEQ_CTRL_START_SHIFT (26U)
432/*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The
433 * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this
434 * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a
435 * conversion sequence. It will consequently always read back as a zero.
436 */
437#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
438#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U)
439#define ADC_SEQ_CTRL_BURST_SHIFT (27U)
440/*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled
441 * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions
442 * can be halted by clearing this bit. The sequence currently in progress will be completed before
443 * conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
444 */
445#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
446#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U)
447#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U)
448/*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a
449 * single conversion on the next channel in the sequence instead of the default response of
450 * launching an entire sequence of conversions. Once all of the channels comprising a sequence have
451 * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled
452 * channel. Interrupt generation will still occur either after each individual conversion or at
453 * the end of the entire sequence, depending on the state of the MODE bit.
454 */
455#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
456#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U)
457#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U)
458/*! LOWPRIO - Set priority for sequence A.
459 * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
460 * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence
461 * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion
462 * currently in progress will be terminated. The A sequence that was interrupted will automatically resume
463 * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the
464 * conversion sequence will resume from that point.
465 */
466#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
467#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U)
468#define ADC_SEQ_CTRL_MODE_SHIFT (30U)
469/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence
470 * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each
471 * conversion, or the individual channel result registers at the end of the entire sequence. Impacts
472 * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which
473 * overrun conditions contribute to an overrun interrupt as described below.
474 * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC
475 * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The
476 * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger
477 * if enabled.
478 * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A
479 * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in
480 * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun
481 * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
482 */
483#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
484#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U)
485#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U)
486/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be
487 * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state
488 * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered
489 * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care
490 * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE
491 * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be
492 * triggered immediately upon being enabled.
493 * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence
494 * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is
495 * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
496 * 0b1..Enabled. Sequence n is enabled.
497 */
498#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
499/*! @} */
500
501/* The count of ADC_SEQ_CTRL */
502#define ADC_SEQ_CTRL_COUNT (2U)
503
504/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
505/*! @{ */
506#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U)
507#define ADC_SEQ_GDAT_RESULT_SHIFT (4U)
508/*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion
509 * performed under conversion sequence associated with this register. The result is a binary
510 * fraction representing the voltage on the currently-selected input channel as it falls within the
511 * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less
512 * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input
513 * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this
514 * result has not yet been read.
515 */
516#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
517#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U)
518#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U)
519/*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or
520 * within the range established by the designated threshold comparison registers (THRn_LOW and
521 * THRn_HIGH).
522 */
523#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
524#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U)
525#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U)
526/*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a
527 * crossing of the threshold level established by the designated LOW threshold comparison register
528 * (THRn_LOW) and, if so, in what direction the crossing occurred.
529 */
530#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
531#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U)
532#define ADC_SEQ_GDAT_CHN_SHIFT (26U)
533/*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000
534 * identifies channel 0, 0001 channel 1, etc.).
535 */
536#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
537#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U)
538#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U)
539/*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a
540 * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along
541 * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun
542 * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set
543 * to '0' (and if the overrun interrupt is enabled).
544 */
545#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
546#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U)
547#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U)
548/*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded
549 * into the RESULT field. It is cleared whenever this register is read. This bit will cause a
550 * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that
551 * sequence is set to 0 (and if the interrupt is enabled).
552 */
553#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
554/*! @} */
555
556/* The count of ADC_SEQ_GDAT */
557#define ADC_SEQ_GDAT_COUNT (2U)
558
559/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
560/*! @{ */
561#define ADC_DAT_RESULT_MASK (0xFFF0U)
562#define ADC_DAT_RESULT_SHIFT (4U)
563/*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed
564 * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin,
565 * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on
566 * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that
567 * the voltage on the input was close to, equal to, or greater than that on VREFP.
568 */
569#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
570#define ADC_DAT_THCMPRANGE_MASK (0x30000U)
571#define ADC_DAT_THCMPRANGE_SHIFT (16U)
572/*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion
573 * was greater than or equal to the value programmed into the designated LOW threshold register
574 * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold
575 * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value
576 * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last
577 * completed conversion was greater than the value programmed into the designated HIGH threshold
578 * register (THRn_HIGH). 0x3 = Reserved.
579 */
580#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
581#define ADC_DAT_THCMPCROSS_MASK (0xC0000U)
582#define ADC_DAT_THCMPCROSS_SHIFT (18U)
583/*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The
584 * most recent completed conversion on this channel had the same relationship (above or below) to
585 * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the
586 * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing
587 * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the
588 * previous sample on this channel was above the threshold value established by the designated LOW
589 * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward
590 * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred
591 * - i.e. the previous sample on this channel was below the threshold value established by the
592 * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
593 */
594#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
595#define ADC_DAT_CHANNEL_MASK (0x3C000000U)
596#define ADC_DAT_CHANNEL_SHIFT (26U)
597/*! CHANNEL - This field is hard-coded to contain the channel number that this particular register
598 * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1
599 * register, etc)
600 */
601#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
602#define ADC_DAT_OVERRUN_MASK (0x40000000U)
603#define ADC_DAT_OVERRUN_SHIFT (30U)
604/*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and
605 * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit
606 * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when
607 * the data related to this channel is read from either of the global SEQn_GDAT registers. This
608 * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if
609 * the overrun interrupt is enabled. While it is allowed to include the same channels in both
610 * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the
611 * data registers associated with any of the channels that are shared between the two sequences. Any
612 * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
613 */
614#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
615#define ADC_DAT_DATAVALID_MASK (0x80000000U)
616#define ADC_DAT_DATAVALID_SHIFT (31U)
617/*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is
618 * cleared whenever this register is read or when the data related to this channel is read from
619 * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in
620 * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in
621 * the data registers associated with any of the channels that are shared between the two
622 * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
623 */
624#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
625/*! @} */
626
627/* The count of ADC_DAT */
628#define ADC_DAT_COUNT (12U)
629
630/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
631/*! @{ */
632#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U)
633#define ADC_THR0_LOW_THRLOW_SHIFT (4U)
634/*! THRLOW - Low threshold value against which ADC results will be compared
635 */
636#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
637/*! @} */
638
639/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
640/*! @{ */
641#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U)
642#define ADC_THR1_LOW_THRLOW_SHIFT (4U)
643/*! THRLOW - Low threshold value against which ADC results will be compared
644 */
645#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
646/*! @} */
647
648/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
649/*! @{ */
650#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U)
651#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U)
652/*! THRHIGH - High threshold value against which ADC results will be compared
653 */
654#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
655/*! @} */
656
657/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
658/*! @{ */
659#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U)
660#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U)
661/*! THRHIGH - High threshold value against which ADC results will be compared
662 */
663#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
664/*! @} */
665
666/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
667/*! @{ */
668#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U)
669#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U)
670/*! CH0_THRSEL - Threshold select for channel 0.
671 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
672 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
673 */
674#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
675#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U)
676#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U)
677/*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0.
678 */
679#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
680#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U)
681#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U)
682/*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0.
683 */
684#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
685#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U)
686#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U)
687/*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0.
688 */
689#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
690#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U)
691#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U)
692/*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0.
693 */
694#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
695#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U)
696#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U)
697/*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0.
698 */
699#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
700#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U)
701#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U)
702/*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0.
703 */
704#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
705#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U)
706#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U)
707/*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0.
708 */
709#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
710#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U)
711#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U)
712/*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0.
713 */
714#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
715#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U)
716#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U)
717/*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0.
718 */
719#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
720#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U)
721#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U)
722/*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0.
723 */
724#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
725#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U)
726#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U)
727/*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0.
728 */
729#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
730/*! @} */
731
732/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
733/*! @{ */
734#define ADC_INTEN_SEQA_INTEN_MASK (0x1U)
735#define ADC_INTEN_SEQA_INTEN_SHIFT (0U)
736/*! SEQA_INTEN - Sequence A interrupt enable.
737 * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled.
738 * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of
739 * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of
740 * conversions, depending on the MODE bit in the SEQA_CTRL register.
741 */
742#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
743#define ADC_INTEN_SEQB_INTEN_MASK (0x2U)
744#define ADC_INTEN_SEQB_INTEN_SHIFT (1U)
745/*! SEQB_INTEN - Sequence B interrupt enable.
746 * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled.
747 * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of
748 * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of
749 * conversions, depending on the MODE bit in the SEQB_CTRL register.
750 */
751#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
752#define ADC_INTEN_OVR_INTEN_MASK (0x4U)
753#define ADC_INTEN_OVR_INTEN_SHIFT (2U)
754/*! OVR_INTEN - Overrun interrupt enable.
755 * 0b0..Disabled. The overrun interrupt is disabled.
756 * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel
757 * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular
758 * sequence is 0, then an overrun in the global data register for that sequence will also cause this
759 * interrupt/DMA trigger to be asserted.
760 */
761#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
762#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U)
763#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U)
764/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0.
765 * 0b00..Disabled.
766 * 0b01..Outside threshold.
767 * 0b10..Crossing threshold.
768 * 0b11..Reserved
769 */
770#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
771#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U)
772#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U)
773/*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0.
774 */
775#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
776#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U)
777#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U)
778/*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0.
779 */
780#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
781#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U)
782#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U)
783/*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0.
784 */
785#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
786#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U)
787#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U)
788/*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0.
789 */
790#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
791#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U)
792#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U)
793/*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0.
794 */
795#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
796#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U)
797#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U)
798/*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0.
799 */
800#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
801#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U)
802#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U)
803/*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0.
804 */
805#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
806#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U)
807#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U)
808/*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0.
809 */
810#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
811#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U)
812#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U)
813/*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0.
814 */
815#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
816#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U)
817#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U)
818/*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0.
819 */
820#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
821#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U)
822#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U)
823/*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0.
824 */
825#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
826/*! @} */
827
828/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
829/*! @{ */
830#define ADC_FLAGS_THCMP0_MASK (0x1U)
831#define ADC_FLAGS_THCMP0_SHIFT (0U)
832/*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or
833 * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by
834 * writing a 1.
835 */
836#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
837#define ADC_FLAGS_THCMP1_MASK (0x2U)
838#define ADC_FLAGS_THCMP1_SHIFT (1U)
839/*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0.
840 */
841#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
842#define ADC_FLAGS_THCMP2_MASK (0x4U)
843#define ADC_FLAGS_THCMP2_SHIFT (2U)
844/*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0.
845 */
846#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
847#define ADC_FLAGS_THCMP3_MASK (0x8U)
848#define ADC_FLAGS_THCMP3_SHIFT (3U)
849/*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0.
850 */
851#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
852#define ADC_FLAGS_THCMP4_MASK (0x10U)
853#define ADC_FLAGS_THCMP4_SHIFT (4U)
854/*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0.
855 */
856#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
857#define ADC_FLAGS_THCMP5_MASK (0x20U)
858#define ADC_FLAGS_THCMP5_SHIFT (5U)
859/*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0.
860 */
861#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
862#define ADC_FLAGS_THCMP6_MASK (0x40U)
863#define ADC_FLAGS_THCMP6_SHIFT (6U)
864/*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0.
865 */
866#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
867#define ADC_FLAGS_THCMP7_MASK (0x80U)
868#define ADC_FLAGS_THCMP7_SHIFT (7U)
869/*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0.
870 */
871#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
872#define ADC_FLAGS_THCMP8_MASK (0x100U)
873#define ADC_FLAGS_THCMP8_SHIFT (8U)
874/*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0.
875 */
876#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
877#define ADC_FLAGS_THCMP9_MASK (0x200U)
878#define ADC_FLAGS_THCMP9_SHIFT (9U)
879/*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0.
880 */
881#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
882#define ADC_FLAGS_THCMP10_MASK (0x400U)
883#define ADC_FLAGS_THCMP10_SHIFT (10U)
884/*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0.
885 */
886#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
887#define ADC_FLAGS_THCMP11_MASK (0x800U)
888#define ADC_FLAGS_THCMP11_SHIFT (11U)
889/*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0.
890 */
891#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
892#define ADC_FLAGS_OVERRUN0_MASK (0x1000U)
893#define ADC_FLAGS_OVERRUN0_SHIFT (12U)
894/*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0
895 */
896#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
897#define ADC_FLAGS_OVERRUN1_MASK (0x2000U)
898#define ADC_FLAGS_OVERRUN1_SHIFT (13U)
899/*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1
900 */
901#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
902#define ADC_FLAGS_OVERRUN2_MASK (0x4000U)
903#define ADC_FLAGS_OVERRUN2_SHIFT (14U)
904/*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2
905 */
906#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
907#define ADC_FLAGS_OVERRUN3_MASK (0x8000U)
908#define ADC_FLAGS_OVERRUN3_SHIFT (15U)
909/*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3
910 */
911#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
912#define ADC_FLAGS_OVERRUN4_MASK (0x10000U)
913#define ADC_FLAGS_OVERRUN4_SHIFT (16U)
914/*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4
915 */
916#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
917#define ADC_FLAGS_OVERRUN5_MASK (0x20000U)
918#define ADC_FLAGS_OVERRUN5_SHIFT (17U)
919/*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5
920 */
921#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
922#define ADC_FLAGS_OVERRUN6_MASK (0x40000U)
923#define ADC_FLAGS_OVERRUN6_SHIFT (18U)
924/*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6
925 */
926#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
927#define ADC_FLAGS_OVERRUN7_MASK (0x80000U)
928#define ADC_FLAGS_OVERRUN7_SHIFT (19U)
929/*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7
930 */
931#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
932#define ADC_FLAGS_OVERRUN8_MASK (0x100000U)
933#define ADC_FLAGS_OVERRUN8_SHIFT (20U)
934/*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8
935 */
936#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
937#define ADC_FLAGS_OVERRUN9_MASK (0x200000U)
938#define ADC_FLAGS_OVERRUN9_SHIFT (21U)
939/*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9
940 */
941#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
942#define ADC_FLAGS_OVERRUN10_MASK (0x400000U)
943#define ADC_FLAGS_OVERRUN10_SHIFT (22U)
944/*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10
945 */
946#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
947#define ADC_FLAGS_OVERRUN11_MASK (0x800000U)
948#define ADC_FLAGS_OVERRUN11_SHIFT (23U)
949/*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11
950 */
951#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
952#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U)
953#define ADC_FLAGS_SEQA_OVR_SHIFT (24U)
954/*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register
955 */
956#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
957#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U)
958#define ADC_FLAGS_SEQB_OVR_SHIFT (25U)
959/*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register
960 */
961#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
962#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U)
963#define ADC_FLAGS_SEQA_INT_SHIFT (28U)
964/*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0,
965 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which
966 * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared
967 * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register
968 * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be
969 * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN
970 * register.
971 */
972#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
973#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U)
974#define ADC_FLAGS_SEQB_INT_SHIFT (29U)
975/*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0,
976 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which
977 * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared
978 * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register
979 * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be
980 * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN
981 * register.
982 */
983#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
984#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U)
985#define ADC_FLAGS_THCMP_INT_SHIFT (30U)
986/*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in
987 * the lower bits of this register are set to 1 (due to an enabled out-of-range or
988 * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be
989 * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared
990 * when all of the individual threshold flags are cleared via writing 1s to those bits.
991 */
992#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
993#define ADC_FLAGS_OVR_INT_MASK (0x80000000U)
994#define ADC_FLAGS_OVR_INT_SHIFT (31U)
995/*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data
996 * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers
997 * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this
998 * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all
999 * of the individual overrun bits have been cleared via reading the corresponding data registers.
1000 */
1001#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
1002/*! @} */
1003
1004/*! @name STARTUP - ADC Startup register. */
1005/*! @{ */
1006#define ADC_STARTUP_ADC_ENA_MASK (0x1U)
1007#define ADC_STARTUP_ADC_ENA_SHIFT (0U)
1008/*! ADC_ENA - ADC Enable bit. This bit can only be set to a 1 by software. It is cleared
1009 * automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds
1010 * after the ADC is powered up (typically by altering a system-level ADC power control bit).
1011 */
1012#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
1013#define ADC_STARTUP_ADC_INIT_MASK (0x2U)
1014#define ADC_STARTUP_ADC_INIT_SHIFT (1U)
1015/*! ADC_INIT - ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine
1016 * will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not
1017 * calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is
1018 * required if a calibration is not performed. It will also reload the stored calibration value from
1019 * a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the
1020 * ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or
1021 * an ADC dummy conversion cycle is required. It should not be set during the same write that
1022 * sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically
1023 * when the 'dummy' conversion cycle completes.
1024 */
1025#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
1026/*! @} */
1027
1028/*! @name CALIB - ADC Calibration register. */
1029/*! @{ */
1030#define ADC_CALIB_CALIB_MASK (0x1U)
1031#define ADC_CALIB_CALIB_SHIFT (0U)
1032/*! CALIB - Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can
1033 * only be set to a '1' by software. It is cleared automatically when the calibration cycle
1034 * completes.
1035 */
1036#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
1037#define ADC_CALIB_CALREQD_MASK (0x2U)
1038#define ADC_CALIB_CALREQD_SHIFT (1U)
1039/*! CALREQD - Calibration required. This read-only bit indicates if calibration is required when
1040 * enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was
1041 * powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to
1042 * determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP
1043 * register) to launch the ADC initialization process which includes a 'dummy' conversion cycle.
1044 * Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks
1045 * required for calibration.
1046 */
1047#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
1048#define ADC_CALIB_CALVALUE_MASK (0x1FCU)
1049#define ADC_CALIB_CALVALUE_SHIFT (2U)
1050/*! CALVALUE - Calibration Value. This read-only field displays the calibration value established
1051 * during last calibration cycle. This value is not typically of any use to the user.
1052 */
1053#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
1054/*! @} */
1055
1056
1057/*!
1058 * @}
1059 */ /* end of group ADC_Register_Masks */
1060
1061
1062/* ADC - Peripheral instance base addresses */
1063/** Peripheral ADC0 base address */
1064#define ADC0_BASE (0x400A0000u)
1065/** Peripheral ADC0 base pointer */
1066#define ADC0 ((ADC_Type *)ADC0_BASE)
1067/** Array initializer of ADC peripheral base addresses */
1068#define ADC_BASE_ADDRS { ADC0_BASE }
1069/** Array initializer of ADC peripheral base pointers */
1070#define ADC_BASE_PTRS { ADC0 }
1071/** Interrupt vectors for the ADC peripheral type */
1072#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
1073#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn }
1074
1075/*!
1076 * @}
1077 */ /* end of group ADC_Peripheral_Access_Layer */
1078
1079
1080/* ----------------------------------------------------------------------------
1081 -- AES Peripheral Access Layer
1082 ---------------------------------------------------------------------------- */
1083
1084/*!
1085 * @addtogroup AES_Peripheral_Access_Layer AES Peripheral Access Layer
1086 * @{
1087 */
1088
1089/** AES - Register Layout Typedef */
1090typedef struct {
1091 union { /* offset: 0x0 */
1092 __IO uint32_t CFG; /**< AES Configuration register, offset: 0x0 */
1093 struct { /* offset: 0x0 */
1094 union { /* offset: 0x0 */
1095 __IO uint16_t CFG0_15; /**< AES Configuration register 0:15, offset: 0x0 */
1096 struct { /* offset: 0x0 */
1097 __IO uint8_t CFG0_7; /**< AES Configuration register 0:7, offset: 0x0 */
1098 __IO uint8_t CFG8_15; /**< AES Configuration register 8:15, offset: 0x1 */
1099 } CFGL;
1100 };
1101 __IO uint16_t CFG16_31; /**< AES Configuration register 16:31, offset: 0x2 */
1102 } CFG0_32;
1103 };
1104 __IO uint32_t CMD; /**< AES Command register, offset: 0x4 */
1105 __IO uint32_t STAT; /**< AES Status register, offset: 0x8 */
1106 __IO uint32_t CTR_INCR; /**< Counter Increment, offset: 0xC */
1107 uint8_t RESERVED_0[16];
1108 __O uint32_t KEY[8]; /**< Bits of the AES key, array offset: 0x20, array step: 0x4 */
1109 __O uint32_t INTEXT[4]; /**< Input text bits, array offset: 0x40, array step: 0x4 */
1110 __O uint32_t HOLDING[4]; /**< Holding register bits, array offset: 0x50, array step: 0x4 */
1111 __I uint32_t OUTTEXT[4]; /**< Output text bits, array offset: 0x60, array step: 0x4 */
1112 __O uint32_t GF128_Y[4]; /**< Y bits input of GF128 hash, array offset: 0x70, array step: 0x4 */
1113 __I uint32_t GF128_Z[4]; /**< Result bits of GF128 hash, array offset: 0x80, array step: 0x4 */
1114 __I uint32_t GCM_TAG[4]; /**< GCM Tag bits, array offset: 0x90, array step: 0x4 */
1115} AES_Type;
1116
1117/* ----------------------------------------------------------------------------
1118 -- AES Register Masks
1119 ---------------------------------------------------------------------------- */
1120
1121/*!
1122 * @addtogroup AES_Register_Masks AES Register Masks
1123 * @{
1124 */
1125
1126/*! @name CFG - AES Configuration register */
1127/*! @{ */
1128#define AES_CFG_PROC_EN_MASK (0x3U)
1129#define AES_CFG_PROC_EN_SHIFT (0U)
1130/*! PROC_EN - Process type enable.
1131 */
1132#define AES_CFG_PROC_EN(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_PROC_EN_SHIFT)) & AES_CFG_PROC_EN_MASK)
1133#define AES_CFG_GF128_SEL_MASK (0x4U)
1134#define AES_CFG_GF128_SEL_SHIFT (2U)
1135/*! GF128_SEL - GF128 hash selection.
1136 */
1137#define AES_CFG_GF128_SEL(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_GF128_SEL_SHIFT)) & AES_CFG_GF128_SEL_MASK)
1138#define AES_CFG_INTEXT_BSWAP_MASK (0x10U)
1139#define AES_CFG_INTEXT_BSWAP_SHIFT (4U)
1140/*! INTEXT_BSWAP - Byte swap input text.
1141 */
1142#define AES_CFG_INTEXT_BSWAP(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_INTEXT_BSWAP_SHIFT)) & AES_CFG_INTEXT_BSWAP_MASK)
1143#define AES_CFG_INTEXT_WSWAP_MASK (0x20U)
1144#define AES_CFG_INTEXT_WSWAP_SHIFT (5U)
1145/*! INTEXT_WSWAP - Word swap input text.
1146 */
1147#define AES_CFG_INTEXT_WSWAP(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_INTEXT_WSWAP_SHIFT)) & AES_CFG_INTEXT_WSWAP_MASK)
1148#define AES_CFG_OUTTEXT_BSWAP_MASK (0x40U)
1149#define AES_CFG_OUTTEXT_BSWAP_SHIFT (6U)
1150/*! OUTTEXT_BSWAP - Byte swap output text.
1151 */
1152#define AES_CFG_OUTTEXT_BSWAP(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_OUTTEXT_BSWAP_SHIFT)) & AES_CFG_OUTTEXT_BSWAP_MASK)
1153#define AES_CFG_OUTTEXT_WSWAP_MASK (0x80U)
1154#define AES_CFG_OUTTEXT_WSWAP_SHIFT (7U)
1155/*! OUTTEXT_WSWAP - Word swap output text.
1156 */
1157#define AES_CFG_OUTTEXT_WSWAP(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_OUTTEXT_WSWAP_SHIFT)) & AES_CFG_OUTTEXT_WSWAP_MASK)
1158#define AES_CFG_KEY_CFG_MASK (0x300U)
1159#define AES_CFG_KEY_CFG_SHIFT (8U)
1160/*! KEY_CFG - Key Configuration.
1161 */
1162#define AES_CFG_KEY_CFG(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_KEY_CFG_SHIFT)) & AES_CFG_KEY_CFG_MASK)
1163#define AES_CFG_INBLK_SEL_MASK (0x30000U)
1164#define AES_CFG_INBLK_SEL_SHIFT (16U)
1165/*! INBLK_SEL - Input block select.
1166 */
1167#define AES_CFG_INBLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_INBLK_SEL_SHIFT)) & AES_CFG_INBLK_SEL_MASK)
1168#define AES_CFG_HOLD_SEL_MASK (0x300000U)
1169#define AES_CFG_HOLD_SEL_SHIFT (20U)
1170/*! HOLD_SEL - Holding register source select.
1171 */
1172#define AES_CFG_HOLD_SEL(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_HOLD_SEL_SHIFT)) & AES_CFG_HOLD_SEL_MASK)
1173#define AES_CFG_OUTTEXT_SEL_MASK (0x3000000U)
1174#define AES_CFG_OUTTEXT_SEL_SHIFT (24U)
1175/*! OUTTEXT_SEL - Output text source select.
1176 */
1177#define AES_CFG_OUTTEXT_SEL(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_OUTTEXT_SEL_SHIFT)) & AES_CFG_OUTTEXT_SEL_MASK)
1178/*! @} */
1179
1180/*! @name CFG0_15 - AES Configuration register 0:15 */
1181/*! @{ */
1182#define AES_CFG0_15_PROC_EN_MASK (0x3U)
1183#define AES_CFG0_15_PROC_EN_SHIFT (0U)
1184/*! PROC_EN - Process type enable.
1185 */
1186#define AES_CFG0_15_PROC_EN(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_PROC_EN_SHIFT)) & AES_CFG0_15_PROC_EN_MASK)
1187#define AES_CFG0_15_GF128_SEL_MASK (0x4U)
1188#define AES_CFG0_15_GF128_SEL_SHIFT (2U)
1189/*! GF128_SEL - GF128 hash selection.
1190 */
1191#define AES_CFG0_15_GF128_SEL(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_GF128_SEL_SHIFT)) & AES_CFG0_15_GF128_SEL_MASK)
1192#define AES_CFG0_15_INTEXT_BSWAP_MASK (0x10U)
1193#define AES_CFG0_15_INTEXT_BSWAP_SHIFT (4U)
1194/*! INTEXT_BSWAP - Byte swap input text.
1195 */
1196#define AES_CFG0_15_INTEXT_BSWAP(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_INTEXT_BSWAP_SHIFT)) & AES_CFG0_15_INTEXT_BSWAP_MASK)
1197#define AES_CFG0_15_INTEXT_WSWAP_MASK (0x20U)
1198#define AES_CFG0_15_INTEXT_WSWAP_SHIFT (5U)
1199/*! INTEXT_WSWAP - Word swap input text.
1200 */
1201#define AES_CFG0_15_INTEXT_WSWAP(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_INTEXT_WSWAP_SHIFT)) & AES_CFG0_15_INTEXT_WSWAP_MASK)
1202#define AES_CFG0_15_OUTTEXT_BSWAP_MASK (0x40U)
1203#define AES_CFG0_15_OUTTEXT_BSWAP_SHIFT (6U)
1204/*! OUTTEXT_BSWAP - Byte swap output text.
1205 */
1206#define AES_CFG0_15_OUTTEXT_BSWAP(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_OUTTEXT_BSWAP_SHIFT)) & AES_CFG0_15_OUTTEXT_BSWAP_MASK)
1207#define AES_CFG0_15_OUTTEXT_WSWAP_MASK (0x80U)
1208#define AES_CFG0_15_OUTTEXT_WSWAP_SHIFT (7U)
1209/*! OUTTEXT_WSWAP - Word swap output text.
1210 */
1211#define AES_CFG0_15_OUTTEXT_WSWAP(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_OUTTEXT_WSWAP_SHIFT)) & AES_CFG0_15_OUTTEXT_WSWAP_MASK)
1212#define AES_CFG0_15_KEY_CFG_MASK (0x300U)
1213#define AES_CFG0_15_KEY_CFG_SHIFT (8U)
1214/*! KEY_CFG - Key Configuration.
1215 */
1216#define AES_CFG0_15_KEY_CFG(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_KEY_CFG_SHIFT)) & AES_CFG0_15_KEY_CFG_MASK)
1217/*! @} */
1218
1219/*! @name CFG0_7 - AES Configuration register 0:7 */
1220/*! @{ */
1221#define AES_CFG0_7_PROC_EN_MASK (0x3U)
1222#define AES_CFG0_7_PROC_EN_SHIFT (0U)
1223/*! PROC_EN - Process type enable.
1224 */
1225#define AES_CFG0_7_PROC_EN(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_PROC_EN_SHIFT)) & AES_CFG0_7_PROC_EN_MASK)
1226#define AES_CFG0_7_GF128_SEL_MASK (0x4U)
1227#define AES_CFG0_7_GF128_SEL_SHIFT (2U)
1228/*! GF128_SEL - GF128 hash selection.
1229 */
1230#define AES_CFG0_7_GF128_SEL(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_GF128_SEL_SHIFT)) & AES_CFG0_7_GF128_SEL_MASK)
1231#define AES_CFG0_7_INTEXT_BSWAP_MASK (0x10U)
1232#define AES_CFG0_7_INTEXT_BSWAP_SHIFT (4U)
1233/*! INTEXT_BSWAP - Byte swap input text.
1234 */
1235#define AES_CFG0_7_INTEXT_BSWAP(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_INTEXT_BSWAP_SHIFT)) & AES_CFG0_7_INTEXT_BSWAP_MASK)
1236#define AES_CFG0_7_INTEXT_WSWAP_MASK (0x20U)
1237#define AES_CFG0_7_INTEXT_WSWAP_SHIFT (5U)
1238/*! INTEXT_WSWAP - Word swap input text.
1239 */
1240#define AES_CFG0_7_INTEXT_WSWAP(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_INTEXT_WSWAP_SHIFT)) & AES_CFG0_7_INTEXT_WSWAP_MASK)
1241#define AES_CFG0_7_OUTTEXT_BSWAP_MASK (0x40U)
1242#define AES_CFG0_7_OUTTEXT_BSWAP_SHIFT (6U)
1243/*! OUTTEXT_BSWAP - Byte swap output text.
1244 */
1245#define AES_CFG0_7_OUTTEXT_BSWAP(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_OUTTEXT_BSWAP_SHIFT)) & AES_CFG0_7_OUTTEXT_BSWAP_MASK)
1246#define AES_CFG0_7_OUTTEXT_WSWAP_MASK (0x80U)
1247#define AES_CFG0_7_OUTTEXT_WSWAP_SHIFT (7U)
1248/*! OUTTEXT_WSWAP - Word swap output text.
1249 */
1250#define AES_CFG0_7_OUTTEXT_WSWAP(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_OUTTEXT_WSWAP_SHIFT)) & AES_CFG0_7_OUTTEXT_WSWAP_MASK)
1251/*! @} */
1252
1253/*! @name CFG8_15 - AES Configuration register 8:15 */
1254/*! @{ */
1255#define AES_CFG8_15_KEY_CFG_MASK (0x3U)
1256#define AES_CFG8_15_KEY_CFG_SHIFT (0U)
1257/*! KEY_CFG - Key Configuration.
1258 */
1259#define AES_CFG8_15_KEY_CFG(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG8_15_KEY_CFG_SHIFT)) & AES_CFG8_15_KEY_CFG_MASK)
1260/*! @} */
1261
1262/*! @name CFG16_31 - AES Configuration register 16:31 */
1263/*! @{ */
1264#define AES_CFG16_31_INBLK_SEL_MASK (0x3U)
1265#define AES_CFG16_31_INBLK_SEL_SHIFT (0U)
1266/*! INBLK_SEL - Input block select.
1267 */
1268#define AES_CFG16_31_INBLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG16_31_INBLK_SEL_SHIFT)) & AES_CFG16_31_INBLK_SEL_MASK)
1269#define AES_CFG16_31_HOLD_SEL_MASK (0x30U)
1270#define AES_CFG16_31_HOLD_SEL_SHIFT (4U)
1271/*! HOLD_SEL - Holding register source select.
1272 */
1273#define AES_CFG16_31_HOLD_SEL(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG16_31_HOLD_SEL_SHIFT)) & AES_CFG16_31_HOLD_SEL_MASK)
1274#define AES_CFG16_31_OUTTEXT_SEL_MASK (0x300U)
1275#define AES_CFG16_31_OUTTEXT_SEL_SHIFT (8U)
1276/*! OUTTEXT_SEL - Output text source select.
1277 */
1278#define AES_CFG16_31_OUTTEXT_SEL(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG16_31_OUTTEXT_SEL_SHIFT)) & AES_CFG16_31_OUTTEXT_SEL_MASK)
1279/*! @} */
1280
1281/*! @name CMD - AES Command register */
1282/*! @{ */
1283#define AES_CMD_COPY_TO_Y_MASK (0x2U)
1284#define AES_CMD_COPY_TO_Y_SHIFT (1U)
1285/*! COPY_TO_Y - Copy output text to GF128Y.
1286 */
1287#define AES_CMD_COPY_TO_Y(x) (((uint32_t)(((uint32_t)(x)) << AES_CMD_COPY_TO_Y_SHIFT)) & AES_CMD_COPY_TO_Y_MASK)
1288#define AES_CMD_SWITCH_MODE_MASK (0x10U)
1289#define AES_CMD_SWITCH_MODE_SHIFT (4U)
1290/*! SWITCH_MODE - When this bit is set the mode switches from forward mode (encryption) to reverse
1291 * mode (decryption) or reverse mode to forward mode.
1292 */
1293#define AES_CMD_SWITCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << AES_CMD_SWITCH_MODE_SHIFT)) & AES_CMD_SWITCH_MODE_MASK)
1294#define AES_CMD_ABORT_MASK (0x100U)
1295#define AES_CMD_ABORT_SHIFT (8U)
1296/*! ABORT - Aborts Encrypt/Decrypt and GF128 Hash operation.
1297 */
1298#define AES_CMD_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AES_CMD_ABORT_SHIFT)) & AES_CMD_ABORT_MASK)
1299#define AES_CMD_WIPE_MASK (0x200U)
1300#define AES_CMD_WIPE_SHIFT (9U)
1301/*! WIPE - When set this bit performs abort, clears KEY and GF128_Y registers and disables cipher.
1302 */
1303#define AES_CMD_WIPE(x) (((uint32_t)(((uint32_t)(x)) << AES_CMD_WIPE_SHIFT)) & AES_CMD_WIPE_MASK)
1304/*! @} */
1305
1306/*! @name STAT - AES Status register */
1307/*! @{ */
1308#define AES_STAT_IDLE_MASK (0x1U)
1309#define AES_STAT_IDLE_SHIFT (0U)
1310/*! IDLE - AES engine Idle.
1311 */
1312#define AES_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << AES_STAT_IDLE_SHIFT)) & AES_STAT_IDLE_MASK)
1313#define AES_STAT_IN_READY_MASK (0x2U)
1314#define AES_STAT_IN_READY_SHIFT (1U)
1315/*! IN_READY - Input text ready.
1316 */
1317#define AES_STAT_IN_READY(x) (((uint32_t)(((uint32_t)(x)) << AES_STAT_IN_READY_SHIFT)) & AES_STAT_IN_READY_MASK)
1318#define AES_STAT_OUT_READY_MASK (0x4U)
1319#define AES_STAT_OUT_READY_SHIFT (2U)
1320/*! OUT_READY - Output text ready.
1321 */
1322#define AES_STAT_OUT_READY(x) (((uint32_t)(((uint32_t)(x)) << AES_STAT_OUT_READY_SHIFT)) & AES_STAT_OUT_READY_MASK)
1323#define AES_STAT_REVERSE_MASK (0x10U)
1324#define AES_STAT_REVERSE_SHIFT (4U)
1325/*! REVERSE - Reverse mode.
1326 */
1327#define AES_STAT_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << AES_STAT_REVERSE_SHIFT)) & AES_STAT_REVERSE_MASK)
1328#define AES_STAT_KEY_VALID_MASK (0x20U)
1329#define AES_STAT_KEY_VALID_SHIFT (5U)
1330/*! KEY_VALID - Key valid.
1331 */
1332#define AES_STAT_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << AES_STAT_KEY_VALID_SHIFT)) & AES_STAT_KEY_VALID_MASK)
1333/*! @} */
1334
1335/*! @name CTR_INCR - Counter Increment */
1336/*! @{ */
1337#define AES_CTR_INCR_CTR_INCR_MASK (0xFFFFFFFFU)
1338#define AES_CTR_INCR_CTR_INCR_SHIFT (0U)
1339/*! CTR_INCR - Increment value for HOLDING register when in counter modes.
1340 */
1341#define AES_CTR_INCR_CTR_INCR(x) (((uint32_t)(((uint32_t)(x)) << AES_CTR_INCR_CTR_INCR_SHIFT)) & AES_CTR_INCR_CTR_INCR_MASK)
1342/*! @} */
1343
1344/*! @name KEY - Bits of the AES key */
1345/*! @{ */
1346#define AES_KEY_KEY_MASK (0xFFFFFFFFU)
1347#define AES_KEY_KEY_SHIFT (0U)
1348/*! KEY - Contains the bits of the AES key.
1349 */
1350#define AES_KEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << AES_KEY_KEY_SHIFT)) & AES_KEY_KEY_MASK)
1351/*! @} */
1352
1353/* The count of AES_KEY */
1354#define AES_KEY_COUNT (8U)
1355
1356/*! @name INTEXT - Input text bits */
1357/*! @{ */
1358#define AES_INTEXT_INTEXT_MASK (0xFFFFFFFFU)
1359#define AES_INTEXT_INTEXT_SHIFT (0U)
1360/*! INTEXT - Contains bits of the AES key.
1361 */
1362#define AES_INTEXT_INTEXT(x) (((uint32_t)(((uint32_t)(x)) << AES_INTEXT_INTEXT_SHIFT)) & AES_INTEXT_INTEXT_MASK)
1363/*! @} */
1364
1365/* The count of AES_INTEXT */
1366#define AES_INTEXT_COUNT (4U)
1367
1368/*! @name HOLDING - Holding register bits */
1369/*! @{ */
1370#define AES_HOLDING_HOLDING_MASK (0xFFFFFFFFU)
1371#define AES_HOLDING_HOLDING_SHIFT (0U)
1372/*! HOLDING - Contains the first word (bits 31:0) of the 128 bit Holding value.
1373 */
1374#define AES_HOLDING_HOLDING(x) (((uint32_t)(((uint32_t)(x)) << AES_HOLDING_HOLDING_SHIFT)) & AES_HOLDING_HOLDING_MASK)
1375/*! @} */
1376
1377/* The count of AES_HOLDING */
1378#define AES_HOLDING_COUNT (4U)
1379
1380/*! @name OUTTEXT - Output text bits */
1381/*! @{ */
1382#define AES_OUTTEXT_OUTTEXT_MASK (0xFFFFFFFFU)
1383#define AES_OUTTEXT_OUTTEXT_SHIFT (0U)
1384/*! OUTTEXT - Contains the bits of the 128 bit Output text data.
1385 */
1386#define AES_OUTTEXT_OUTTEXT(x) (((uint32_t)(((uint32_t)(x)) << AES_OUTTEXT_OUTTEXT_SHIFT)) & AES_OUTTEXT_OUTTEXT_MASK)
1387/*! @} */
1388
1389/* The count of AES_OUTTEXT */
1390#define AES_OUTTEXT_COUNT (4U)
1391
1392/*! @name GF128_Y - Y bits input of GF128 hash */
1393/*! @{ */
1394#define AES_GF128_Y_GF128_Y_MASK (0xFFFFFFFFU)
1395#define AES_GF128_Y_GF128_Y_SHIFT (0U)
1396/*! GF128_Y - Contains the bits of the Y input of GF128 hash.
1397 */
1398#define AES_GF128_Y_GF128_Y(x) (((uint32_t)(((uint32_t)(x)) << AES_GF128_Y_GF128_Y_SHIFT)) & AES_GF128_Y_GF128_Y_MASK)
1399/*! @} */
1400
1401/* The count of AES_GF128_Y */
1402#define AES_GF128_Y_COUNT (4U)
1403
1404/*! @name GF128_Z - Result bits of GF128 hash */
1405/*! @{ */
1406#define AES_GF128_Z_GF128_Z_MASK (0xFFFFFFFFU)
1407#define AES_GF128_Z_GF128_Z_SHIFT (0U)
1408/*! GF128_Z - Contains bits of the result of GF128 hash.
1409 */
1410#define AES_GF128_Z_GF128_Z(x) (((uint32_t)(((uint32_t)(x)) << AES_GF128_Z_GF128_Z_SHIFT)) & AES_GF128_Z_GF128_Z_MASK)
1411/*! @} */
1412
1413/* The count of AES_GF128_Z */
1414#define AES_GF128_Z_COUNT (4U)
1415
1416/*! @name GCM_TAG - GCM Tag bits */
1417/*! @{ */
1418#define AES_GCM_TAG_GCM_TAG_MASK (0xFFFFFFFFU)
1419#define AES_GCM_TAG_GCM_TAG_SHIFT (0U)
1420/*! GCM_TAG - Contains bits of the 128 bit GCM tag.
1421 */
1422#define AES_GCM_TAG_GCM_TAG(x) (((uint32_t)(((uint32_t)(x)) << AES_GCM_TAG_GCM_TAG_SHIFT)) & AES_GCM_TAG_GCM_TAG_MASK)
1423/*! @} */
1424
1425/* The count of AES_GCM_TAG */
1426#define AES_GCM_TAG_COUNT (4U)
1427
1428
1429/*!
1430 * @}
1431 */ /* end of group AES_Register_Masks */
1432
1433
1434/* AES - Peripheral instance base addresses */
1435/** Peripheral AES0 base address */
1436#define AES0_BASE (0x400A1000u)
1437/** Peripheral AES0 base pointer */
1438#define AES0 ((AES_Type *)AES0_BASE)
1439/** Array initializer of AES peripheral base addresses */
1440#define AES_BASE_ADDRS { AES0_BASE }
1441/** Array initializer of AES peripheral base pointers */
1442#define AES_BASE_PTRS { AES0 }
1443
1444/*!
1445 * @}
1446 */ /* end of group AES_Peripheral_Access_Layer */
1447
1448
1449/* ----------------------------------------------------------------------------
1450 -- ASYNC_SYSCON Peripheral Access Layer
1451 ---------------------------------------------------------------------------- */
1452
1453/*!
1454 * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
1455 * @{
1456 */
1457
1458/** ASYNC_SYSCON - Register Layout Typedef */
1459typedef struct {
1460 __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */
1461 __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
1462 __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
1463 uint8_t RESERVED_0[4];
1464 __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */
1465 __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
1466 __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
1467 uint8_t RESERVED_1[4];
1468 __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */
1469} ASYNC_SYSCON_Type;
1470
1471/* ----------------------------------------------------------------------------
1472 -- ASYNC_SYSCON Register Masks
1473 ---------------------------------------------------------------------------- */
1474
1475/*!
1476 * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
1477 * @{
1478 */
1479
1480/*! @name ASYNCPRESETCTRL - Async peripheral reset control */
1481/*! @{ */
1482#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
1483#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
1484/*! CTIMER3 - Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
1485 */
1486#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
1487#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
1488#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
1489/*! CTIMER4 - Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
1490 */
1491#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
1492/*! @} */
1493
1494/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
1495/*! @{ */
1496#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
1497#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
1498/*! ARST_SET - Writing ones to this register sets the corresponding bit or bits in the
1499 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1500 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1501 */
1502#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
1503/*! @} */
1504
1505/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
1506/*! @{ */
1507#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
1508#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
1509/*! ARST_CLR - Writing ones to this register clears the corresponding bit or bits in the
1510 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1511 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1512 */
1513#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
1514/*! @} */
1515
1516/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
1517/*! @{ */
1518#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
1519#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
1520/*! CTIMER3 - Controls the clock for CTIMER3. 0 = Disable; 1 = Enable.
1521 */
1522#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
1523#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
1524#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
1525/*! CTIMER4 - Controls the clock for CTIMER4. 0 = Disable; 1 = Enable.
1526 */
1527#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
1528/*! @} */
1529
1530/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
1531/*! @{ */
1532#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
1533#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
1534/*! ACLK_SET - Writing ones to this register sets the corresponding bit or bits in the
1535 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1536 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1537 */
1538#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
1539/*! @} */
1540
1541/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
1542/*! @{ */
1543#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
1544#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
1545/*! ACLK_CLR - Writing ones to this register clears the corresponding bit or bits in the
1546 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1547 * ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them.
1548 */
1549#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
1550/*! @} */
1551
1552/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
1553/*! @{ */
1554#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U)
1555#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U)
1556/*! SEL - Clock source for asynchronous clock source selector A
1557 * 0b00..Main clock (main_clk)
1558 * 0b01..FRO 12 MHz (fro_12m)
1559 * 0b10..Audio PLL clock.(AUDPLL_BYPASS)
1560 * 0b11..fc6 fclk (fc6_fclk)
1561 */
1562#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
1563/*! @} */
1564
1565
1566/*!
1567 * @}
1568 */ /* end of group ASYNC_SYSCON_Register_Masks */
1569
1570
1571/* ASYNC_SYSCON - Peripheral instance base addresses */
1572/** Peripheral ASYNC_SYSCON base address */
1573#define ASYNC_SYSCON_BASE (0x40040000u)
1574/** Peripheral ASYNC_SYSCON base pointer */
1575#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
1576/** Array initializer of ASYNC_SYSCON peripheral base addresses */
1577#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE }
1578/** Array initializer of ASYNC_SYSCON peripheral base pointers */
1579#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON }
1580
1581/*!
1582 * @}
1583 */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
1584
1585
1586/* ----------------------------------------------------------------------------
1587 -- CAN Peripheral Access Layer
1588 ---------------------------------------------------------------------------- */
1589
1590/*!
1591 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
1592 * @{
1593 */
1594
1595/** CAN - Register Layout Typedef */
1596typedef struct {
1597 uint8_t RESERVED_0[12];
1598 __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */
1599 __IO uint32_t TEST; /**< Test Register, offset: 0x10 */
1600 uint8_t RESERVED_1[4];
1601 __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */
1602 __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */
1603 __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */
1604 __I uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */
1605 __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */
1606 __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */
1607 uint8_t RESERVED_2[16];
1608 __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */
1609 __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */
1610 __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */
1611 uint8_t RESERVED_3[4];
1612 __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */
1613 __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */
1614 __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */
1615 __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */
1616 uint8_t RESERVED_4[32];
1617 __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */
1618 __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */
1619 __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */
1620 uint8_t RESERVED_5[4];
1621 __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */
1622 __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */
1623 __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */
1624 __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */
1625 __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */
1626 __I uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */
1627 __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */
1628 __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */
1629 __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */
1630 __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */
1631 __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */
1632 __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */
1633 __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */
1634 __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */
1635 __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */
1636 __I uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */
1637 __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */
1638 __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */
1639 __I uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */
1640 __I uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */
1641 __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */
1642 __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */
1643 uint8_t RESERVED_6[8];
1644 __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */
1645 __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */
1646 __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */
1647 uint8_t RESERVED_7[260];
1648 __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */
1649 uint8_t RESERVED_8[508];
1650 __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */
1651 uint8_t RESERVED_9[508];
1652 __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */
1653} CAN_Type;
1654
1655/* ----------------------------------------------------------------------------
1656 -- CAN Register Masks
1657 ---------------------------------------------------------------------------- */
1658
1659/*!
1660 * @addtogroup CAN_Register_Masks CAN Register Masks
1661 * @{
1662 */
1663
1664/*! @name DBTP - Data Bit Timing Prescaler Register */
1665/*! @{ */
1666#define CAN_DBTP_DSJW_MASK (0xFU)
1667#define CAN_DBTP_DSJW_SHIFT (0U)
1668/*! DSJW - Data (re)synchronization jump width.
1669 */
1670#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK)
1671#define CAN_DBTP_DTSEG2_MASK (0xF0U)
1672#define CAN_DBTP_DTSEG2_SHIFT (4U)
1673/*! DTSEG2 - Data time segment after sample point.
1674 */
1675#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK)
1676#define CAN_DBTP_DTSEG1_MASK (0x1F00U)
1677#define CAN_DBTP_DTSEG1_SHIFT (8U)
1678/*! DTSEG1 - Data time segment before sample point.
1679 */
1680#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK)
1681#define CAN_DBTP_DBRP_MASK (0x1F0000U)
1682#define CAN_DBTP_DBRP_SHIFT (16U)
1683/*! DBRP - Data bit rate prescaler.
1684 */
1685#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK)
1686#define CAN_DBTP_TDC_MASK (0x800000U)
1687#define CAN_DBTP_TDC_SHIFT (23U)
1688/*! TDC - Transmitter delay compensation.
1689 */
1690#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK)
1691/*! @} */
1692
1693/*! @name TEST - Test Register */
1694/*! @{ */
1695#define CAN_TEST_LBCK_MASK (0x10U)
1696#define CAN_TEST_LBCK_SHIFT (4U)
1697/*! LBCK - Loop back mode.
1698 */
1699#define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)
1700#define CAN_TEST_TX_MASK (0x60U)
1701#define CAN_TEST_TX_SHIFT (5U)
1702/*! TX - Control of transmit pin.
1703 */
1704#define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)
1705#define CAN_TEST_RX_MASK (0x80U)
1706#define CAN_TEST_RX_SHIFT (7U)
1707/*! RX - Monitors the actual value of the CAN_RXD.
1708 */
1709#define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)
1710/*! @} */
1711
1712/*! @name CCCR - CC Control Register */
1713/*! @{ */
1714#define CAN_CCCR_INIT_MASK (0x1U)
1715#define CAN_CCCR_INIT_SHIFT (0U)
1716/*! INIT - Initialization.
1717 */
1718#define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)
1719#define CAN_CCCR_CCE_MASK (0x2U)
1720#define CAN_CCCR_CCE_SHIFT (1U)
1721/*! CCE - Configuration change enable.
1722 */
1723#define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)
1724#define CAN_CCCR_ASM_MASK (0x4U)
1725#define CAN_CCCR_ASM_SHIFT (2U)
1726/*! ASM - Restricted operational mode.
1727 */
1728#define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)
1729#define CAN_CCCR_CSA_MASK (0x8U)
1730#define CAN_CCCR_CSA_SHIFT (3U)
1731/*! CSA - Clock Stop Acknowledge.
1732 */
1733#define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)
1734#define CAN_CCCR_CSR_MASK (0x10U)
1735#define CAN_CCCR_CSR_SHIFT (4U)
1736/*! CSR - Clock Stop Request.
1737 */
1738#define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)
1739#define CAN_CCCR_MON_MASK (0x20U)
1740#define CAN_CCCR_MON_SHIFT (5U)
1741/*! MON - Bus monitoring mode.
1742 */
1743#define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)
1744#define CAN_CCCR_DAR_MASK (0x40U)
1745#define CAN_CCCR_DAR_SHIFT (6U)
1746/*! DAR - Disable automatic retransmission.
1747 */
1748#define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)
1749#define CAN_CCCR_TEST_MASK (0x80U)
1750#define CAN_CCCR_TEST_SHIFT (7U)
1751/*! TEST - Test mode enable.
1752 */
1753#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
1754#define CAN_CCCR_FDOE_MASK (0x100U)
1755#define CAN_CCCR_FDOE_SHIFT (8U)
1756/*! FDOE - CAN FD operation enable.
1757 */
1758#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK)
1759#define CAN_CCCR_BRSE_MASK (0x200U)
1760#define CAN_CCCR_BRSE_SHIFT (9U)
1761/*! BRSE - When CAN FD operation is disabled, this bit is not evaluated.
1762 */
1763#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK)
1764#define CAN_CCCR_PXHD_MASK (0x1000U)
1765#define CAN_CCCR_PXHD_SHIFT (12U)
1766/*! PXHD - Protocol exception handling disable.
1767 */
1768#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
1769#define CAN_CCCR_EFBI_MASK (0x2000U)
1770#define CAN_CCCR_EFBI_SHIFT (13U)
1771/*! EFBI - Edge filtering during bus integration.
1772 */
1773#define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)
1774#define CAN_CCCR_TXP_MASK (0x4000U)
1775#define CAN_CCCR_TXP_SHIFT (14U)
1776/*! TXP - Transmit pause.
1777 */
1778#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
1779#define CAN_CCCR_NISO_MASK (0x8000U)
1780#define CAN_CCCR_NISO_SHIFT (15U)
1781/*! NISO - Non ISO operation.
1782 */
1783#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK)
1784/*! @} */
1785
1786/*! @name NBTP - Nominal Bit Timing and Prescaler Register */
1787/*! @{ */
1788#define CAN_NBTP_NTSEG2_MASK (0x7FU)
1789#define CAN_NBTP_NTSEG2_SHIFT (0U)
1790/*! NTSEG2 - Nominal time segment after sample point.
1791 */
1792#define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)
1793#define CAN_NBTP_NTSEG1_MASK (0xFF00U)
1794#define CAN_NBTP_NTSEG1_SHIFT (8U)
1795/*! NTSEG1 - Nominal time segment before sample point.
1796 */
1797#define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)
1798#define CAN_NBTP_NBRP_MASK (0x1FF0000U)
1799#define CAN_NBTP_NBRP_SHIFT (16U)
1800/*! NBRP - Nominal bit rate prescaler.
1801 */
1802#define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)
1803#define CAN_NBTP_NSJW_MASK (0xFE000000U)
1804#define CAN_NBTP_NSJW_SHIFT (25U)
1805/*! NSJW - Nominal (re)synchronization jump width.
1806 */
1807#define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)
1808/*! @} */
1809
1810/*! @name TSCC - Timestamp Counter Configuration */
1811/*! @{ */
1812#define CAN_TSCC_TSS_MASK (0x3U)
1813#define CAN_TSCC_TSS_SHIFT (0U)
1814/*! TSS - Timestamp select.
1815 */
1816#define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)
1817#define CAN_TSCC_TCP_MASK (0xF0000U)
1818#define CAN_TSCC_TCP_SHIFT (16U)
1819/*! TCP - Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times.
1820 */
1821#define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)
1822/*! @} */
1823
1824/*! @name TSCV - Timestamp Counter Value */
1825/*! @{ */
1826#define CAN_TSCV_TSC_MASK (0xFFFFU)
1827#define CAN_TSCV_TSC_SHIFT (0U)
1828/*! TSC - Timestamp counter.
1829 */
1830#define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)
1831/*! @} */
1832
1833/*! @name TOCC - Timeout Counter Configuration */
1834/*! @{ */
1835#define CAN_TOCC_ETOC_MASK (0x1U)
1836#define CAN_TOCC_ETOC_SHIFT (0U)
1837/*! ETOC - Enable timeout counter.
1838 */
1839#define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)
1840#define CAN_TOCC_TOS_MASK (0x6U)
1841#define CAN_TOCC_TOS_SHIFT (1U)
1842/*! TOS - Timeout select.
1843 */
1844#define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)
1845#define CAN_TOCC_TOP_MASK (0xFFFF0000U)
1846#define CAN_TOCC_TOP_SHIFT (16U)
1847/*! TOP - Timeout period.
1848 */
1849#define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)
1850/*! @} */
1851
1852/*! @name TOCV - Timeout Counter Value */
1853/*! @{ */
1854#define CAN_TOCV_TOC_MASK (0xFFFFU)
1855#define CAN_TOCV_TOC_SHIFT (0U)
1856/*! TOC - Timeout counter.
1857 */
1858#define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)
1859/*! @} */
1860
1861/*! @name ECR - Error Counter Register */
1862/*! @{ */
1863#define CAN_ECR_TEC_MASK (0xFFU)
1864#define CAN_ECR_TEC_SHIFT (0U)
1865/*! TEC - Transmit error counter.
1866 */
1867#define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)
1868#define CAN_ECR_REC_MASK (0x7F00U)
1869#define CAN_ECR_REC_SHIFT (8U)
1870/*! REC - Receive error counter.
1871 */
1872#define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)
1873#define CAN_ECR_RP_MASK (0x8000U)
1874#define CAN_ECR_RP_SHIFT (15U)
1875/*! RP - Receive error passive.
1876 */
1877#define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)
1878#define CAN_ECR_CEL_MASK (0xFF0000U)
1879#define CAN_ECR_CEL_SHIFT (16U)
1880/*! CEL - CAN error logging.
1881 */
1882#define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)
1883/*! @} */
1884
1885/*! @name PSR - Protocol Status Register */
1886/*! @{ */
1887#define CAN_PSR_LEC_MASK (0x7U)
1888#define CAN_PSR_LEC_SHIFT (0U)
1889/*! LEC - Last error code.
1890 */
1891#define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)
1892#define CAN_PSR_ACT_MASK (0x18U)
1893#define CAN_PSR_ACT_SHIFT (3U)
1894/*! ACT - Activity.
1895 */
1896#define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)
1897#define CAN_PSR_EP_MASK (0x20U)
1898#define CAN_PSR_EP_SHIFT (5U)
1899/*! EP - Error Passive.
1900 */
1901#define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)
1902#define CAN_PSR_EW_MASK (0x40U)
1903#define CAN_PSR_EW_SHIFT (6U)
1904/*! EW - Warning status.
1905 */
1906#define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)
1907#define CAN_PSR_BO_MASK (0x80U)
1908#define CAN_PSR_BO_SHIFT (7U)
1909/*! BO - Bus Off Status.
1910 */
1911#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
1912#define CAN_PSR_DLEC_MASK (0x700U)
1913#define CAN_PSR_DLEC_SHIFT (8U)
1914/*! DLEC - Data phase last error code.
1915 */
1916#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK)
1917#define CAN_PSR_RESI_MASK (0x800U)
1918#define CAN_PSR_RESI_SHIFT (11U)
1919/*! RESI - ESI flag of the last received CAN FD message.
1920 */
1921#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK)
1922#define CAN_PSR_RBRS_MASK (0x1000U)
1923#define CAN_PSR_RBRS_SHIFT (12U)
1924/*! RBRS - BRS flag of last received CAN FD message.
1925 */
1926#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK)
1927#define CAN_PSR_RFDF_MASK (0x2000U)
1928#define CAN_PSR_RFDF_SHIFT (13U)
1929/*! RFDF - Received a CAN FD message.
1930 */
1931#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK)
1932#define CAN_PSR_PXE_MASK (0x4000U)
1933#define CAN_PSR_PXE_SHIFT (14U)
1934/*! PXE - Protocol exception event.
1935 */
1936#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
1937#define CAN_PSR_TDCV_MASK (0x7F0000U)
1938#define CAN_PSR_TDCV_SHIFT (16U)
1939/*! TDCV - Transmitter delay compensation value.
1940 */
1941#define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)
1942/*! @} */
1943
1944/*! @name TDCR - Transmitter Delay Compensator Register */
1945/*! @{ */
1946#define CAN_TDCR_TDCF_MASK (0x7FU)
1947#define CAN_TDCR_TDCF_SHIFT (0U)
1948/*! TDCF - Transmitter delay compensation filter window length.
1949 */
1950#define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)
1951#define CAN_TDCR_TDCO_MASK (0x7F00U)
1952#define CAN_TDCR_TDCO_SHIFT (8U)
1953/*! TDCO - Transmitter delay compensation offset.
1954 */
1955#define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)
1956/*! @} */
1957
1958/*! @name IR - Interrupt Register */
1959/*! @{ */
1960#define CAN_IR_RF0N_MASK (0x1U)
1961#define CAN_IR_RF0N_SHIFT (0U)
1962/*! RF0N - Rx FIFO 0 new message.
1963 */
1964#define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)
1965#define CAN_IR_RF0W_MASK (0x2U)
1966#define CAN_IR_RF0W_SHIFT (1U)
1967/*! RF0W - Rx FIFO 0 watermark reached.
1968 */
1969#define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)
1970#define CAN_IR_RF0F_MASK (0x4U)
1971#define CAN_IR_RF0F_SHIFT (2U)
1972/*! RF0F - Rx FIFO 0 full.
1973 */
1974#define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)
1975#define CAN_IR_RF0L_MASK (0x8U)
1976#define CAN_IR_RF0L_SHIFT (3U)
1977/*! RF0L - Rx FIFO 0 message lost.
1978 */
1979#define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)
1980#define CAN_IR_RF1N_MASK (0x10U)
1981#define CAN_IR_RF1N_SHIFT (4U)
1982/*! RF1N - Rx FIFO 1 new message.
1983 */
1984#define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)
1985#define CAN_IR_RF1W_MASK (0x20U)
1986#define CAN_IR_RF1W_SHIFT (5U)
1987/*! RF1W - Rx FIFO 1 watermark reached.
1988 */
1989#define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)
1990#define CAN_IR_RF1F_MASK (0x40U)
1991#define CAN_IR_RF1F_SHIFT (6U)
1992/*! RF1F - Rx FIFO 1 full.
1993 */
1994#define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)
1995#define CAN_IR_RF1L_MASK (0x80U)
1996#define CAN_IR_RF1L_SHIFT (7U)
1997/*! RF1L - Rx FIFO 1 message lost.
1998 */
1999#define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)
2000#define CAN_IR_HPM_MASK (0x100U)
2001#define CAN_IR_HPM_SHIFT (8U)
2002/*! HPM - High priority message.
2003 */
2004#define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)
2005#define CAN_IR_TC_MASK (0x200U)
2006#define CAN_IR_TC_SHIFT (9U)
2007/*! TC - Transmission completed.
2008 */
2009#define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)
2010#define CAN_IR_TCF_MASK (0x400U)
2011#define CAN_IR_TCF_SHIFT (10U)
2012/*! TCF - Transmission cancellation finished.
2013 */
2014#define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)
2015#define CAN_IR_TFE_MASK (0x800U)
2016#define CAN_IR_TFE_SHIFT (11U)
2017/*! TFE - Tx FIFO empty.
2018 */
2019#define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)
2020#define CAN_IR_TEFN_MASK (0x1000U)
2021#define CAN_IR_TEFN_SHIFT (12U)
2022/*! TEFN - Tx event FIFO new entry.
2023 */
2024#define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)
2025#define CAN_IR_TEFW_MASK (0x2000U)
2026#define CAN_IR_TEFW_SHIFT (13U)
2027/*! TEFW - Tx event FIFO watermark reached.
2028 */
2029#define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)
2030#define CAN_IR_TEFF_MASK (0x4000U)
2031#define CAN_IR_TEFF_SHIFT (14U)
2032/*! TEFF - Tx event FIFO full.
2033 */
2034#define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)
2035#define CAN_IR_TEFL_MASK (0x8000U)
2036#define CAN_IR_TEFL_SHIFT (15U)
2037/*! TEFL - Tx event FIFO element lost.
2038 */
2039#define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)
2040#define CAN_IR_TSW_MASK (0x10000U)
2041#define CAN_IR_TSW_SHIFT (16U)
2042/*! TSW - Timestamp wraparound.
2043 */
2044#define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)
2045#define CAN_IR_MRAF_MASK (0x20000U)
2046#define CAN_IR_MRAF_SHIFT (17U)
2047/*! MRAF - Message RAM access failure.
2048 */
2049#define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)
2050#define CAN_IR_TOO_MASK (0x40000U)
2051#define CAN_IR_TOO_SHIFT (18U)
2052/*! TOO - Timeout occurred.
2053 */
2054#define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)
2055#define CAN_IR_DRX_MASK (0x80000U)
2056#define CAN_IR_DRX_SHIFT (19U)
2057/*! DRX - Message stored in dedicated Rx buffer.
2058 */
2059#define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)
2060#define CAN_IR_BEC_MASK (0x100000U)
2061#define CAN_IR_BEC_SHIFT (20U)
2062/*! BEC - Bit error corrected.
2063 */
2064#define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)
2065#define CAN_IR_BEU_MASK (0x200000U)
2066#define CAN_IR_BEU_SHIFT (21U)
2067/*! BEU - Bit error uncorrected.
2068 */
2069#define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)
2070#define CAN_IR_ELO_MASK (0x400000U)
2071#define CAN_IR_ELO_SHIFT (22U)
2072/*! ELO - Error logging overflow.
2073 */
2074#define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK)
2075#define CAN_IR_EP_MASK (0x800000U)
2076#define CAN_IR_EP_SHIFT (23U)
2077/*! EP - Error passive.
2078 */
2079#define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK)
2080#define CAN_IR_EW_MASK (0x1000000U)
2081#define CAN_IR_EW_SHIFT (24U)
2082/*! EW - Warning status.
2083 */
2084#define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK)
2085#define CAN_IR_BO_MASK (0x2000000U)
2086#define CAN_IR_BO_SHIFT (25U)
2087/*! BO - Bus_Off Status.
2088 */
2089#define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK)
2090#define CAN_IR_WDI_MASK (0x4000000U)
2091#define CAN_IR_WDI_SHIFT (26U)
2092/*! WDI - Watchdog interrupt.
2093 */
2094#define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK)
2095#define CAN_IR_PEA_MASK (0x8000000U)
2096#define CAN_IR_PEA_SHIFT (27U)
2097/*! PEA - Protocol error in arbitration phase.
2098 */
2099#define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK)
2100#define CAN_IR_PED_MASK (0x10000000U)
2101#define CAN_IR_PED_SHIFT (28U)
2102/*! PED - Protocol error in data phase.
2103 */
2104#define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK)
2105#define CAN_IR_ARA_MASK (0x20000000U)
2106#define CAN_IR_ARA_SHIFT (29U)
2107/*! ARA - Access to reserved address.
2108 */
2109#define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK)
2110/*! @} */
2111
2112/*! @name IE - Interrupt Enable */
2113/*! @{ */
2114#define CAN_IE_RF0NE_MASK (0x1U)
2115#define CAN_IE_RF0NE_SHIFT (0U)
2116/*! RF0NE - Rx FIFO 0 new message interrupt enable.
2117 */
2118#define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK)
2119#define CAN_IE_RF0WE_MASK (0x2U)
2120#define CAN_IE_RF0WE_SHIFT (1U)
2121/*! RF0WE - Rx FIFO 0 watermark reached interrupt enable.
2122 */
2123#define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK)
2124#define CAN_IE_RF0FE_MASK (0x4U)
2125#define CAN_IE_RF0FE_SHIFT (2U)
2126/*! RF0FE - Rx FIFO 0 full interrupt enable.
2127 */
2128#define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK)
2129#define CAN_IE_RF0LE_MASK (0x8U)
2130#define CAN_IE_RF0LE_SHIFT (3U)
2131/*! RF0LE - Rx FIFO 0 message lost interrupt enable.
2132 */
2133#define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK)
2134#define CAN_IE_RF1NE_MASK (0x10U)
2135#define CAN_IE_RF1NE_SHIFT (4U)
2136/*! RF1NE - Rx FIFO 1 new message interrupt enable.
2137 */
2138#define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK)
2139#define CAN_IE_RF1WE_MASK (0x20U)
2140#define CAN_IE_RF1WE_SHIFT (5U)
2141/*! RF1WE - Rx FIFO 1 watermark reached interrupt enable.
2142 */
2143#define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK)
2144#define CAN_IE_RF1FE_MASK (0x40U)
2145#define CAN_IE_RF1FE_SHIFT (6U)
2146/*! RF1FE - Rx FIFO 1 full interrupt enable.
2147 */
2148#define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK)
2149#define CAN_IE_RF1LE_MASK (0x80U)
2150#define CAN_IE_RF1LE_SHIFT (7U)
2151/*! RF1LE - Rx FIFO 1 message lost interrupt enable.
2152 */
2153#define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK)
2154#define CAN_IE_HPME_MASK (0x100U)
2155#define CAN_IE_HPME_SHIFT (8U)
2156/*! HPME - High priority message interrupt enable.
2157 */
2158#define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK)
2159#define CAN_IE_TCE_MASK (0x200U)
2160#define CAN_IE_TCE_SHIFT (9U)
2161/*! TCE - Transmission completed interrupt enable.
2162 */
2163#define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK)
2164#define CAN_IE_TCFE_MASK (0x400U)
2165#define CAN_IE_TCFE_SHIFT (10U)
2166/*! TCFE - Transmission cancellation finished interrupt enable.
2167 */
2168#define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK)
2169#define CAN_IE_TFEE_MASK (0x800U)
2170#define CAN_IE_TFEE_SHIFT (11U)
2171/*! TFEE - Tx FIFO empty interrupt enable.
2172 */
2173#define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK)
2174#define CAN_IE_TEFNE_MASK (0x1000U)
2175#define CAN_IE_TEFNE_SHIFT (12U)
2176/*! TEFNE - Tx event FIFO new entry interrupt enable.
2177 */
2178#define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK)
2179#define CAN_IE_TEFWE_MASK (0x2000U)
2180#define CAN_IE_TEFWE_SHIFT (13U)
2181/*! TEFWE - Tx event FIFO watermark reached interrupt enable.
2182 */
2183#define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK)
2184#define CAN_IE_TEFFE_MASK (0x4000U)
2185#define CAN_IE_TEFFE_SHIFT (14U)
2186/*! TEFFE - Tx event FIFO full interrupt enable.
2187 */
2188#define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK)
2189#define CAN_IE_TEFLE_MASK (0x8000U)
2190#define CAN_IE_TEFLE_SHIFT (15U)
2191/*! TEFLE - Tx event FIFO element lost interrupt enable.
2192 */
2193#define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK)
2194#define CAN_IE_TSWE_MASK (0x10000U)
2195#define CAN_IE_TSWE_SHIFT (16U)
2196/*! TSWE - Timestamp wraparound interrupt enable.
2197 */
2198#define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK)
2199#define CAN_IE_MRAFE_MASK (0x20000U)
2200#define CAN_IE_MRAFE_SHIFT (17U)
2201/*! MRAFE - Message RAM access failure interrupt enable.
2202 */
2203#define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK)
2204#define CAN_IE_TOOE_MASK (0x40000U)
2205#define CAN_IE_TOOE_SHIFT (18U)
2206/*! TOOE - Timeout occurred interrupt enable.
2207 */
2208#define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK)
2209#define CAN_IE_DRXE_MASK (0x80000U)
2210#define CAN_IE_DRXE_SHIFT (19U)
2211/*! DRXE - Message stored in dedicated Rx buffer interrupt enable.
2212 */
2213#define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK)
2214#define CAN_IE_BECE_MASK (0x100000U)
2215#define CAN_IE_BECE_SHIFT (20U)
2216/*! BECE - Bit error corrected interrupt enable.
2217 */
2218#define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK)
2219#define CAN_IE_BEUE_MASK (0x200000U)
2220#define CAN_IE_BEUE_SHIFT (21U)
2221/*! BEUE - Bit error uncorrected interrupt enable.
2222 */
2223#define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK)
2224#define CAN_IE_ELOE_MASK (0x400000U)
2225#define CAN_IE_ELOE_SHIFT (22U)
2226/*! ELOE - Error logging overflow interrupt enable.
2227 */
2228#define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK)
2229#define CAN_IE_EPE_MASK (0x800000U)
2230#define CAN_IE_EPE_SHIFT (23U)
2231/*! EPE - Error passive interrupt enable.
2232 */
2233#define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK)
2234#define CAN_IE_EWE_MASK (0x1000000U)
2235#define CAN_IE_EWE_SHIFT (24U)
2236/*! EWE - Warning status interrupt enable.
2237 */
2238#define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK)
2239#define CAN_IE_BOE_MASK (0x2000000U)
2240#define CAN_IE_BOE_SHIFT (25U)
2241/*! BOE - Bus_Off Status interrupt enable.
2242 */
2243#define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK)
2244#define CAN_IE_WDIE_MASK (0x4000000U)
2245#define CAN_IE_WDIE_SHIFT (26U)
2246/*! WDIE - Watchdog interrupt enable.
2247 */
2248#define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK)
2249#define CAN_IE_PEAE_MASK (0x8000000U)
2250#define CAN_IE_PEAE_SHIFT (27U)
2251/*! PEAE - Protocol error in arbitration phase interrupt enable.
2252 */
2253#define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK)
2254#define CAN_IE_PEDE_MASK (0x10000000U)
2255#define CAN_IE_PEDE_SHIFT (28U)
2256/*! PEDE - Protocol error in data phase interrupt enable.
2257 */
2258#define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK)
2259#define CAN_IE_ARAE_MASK (0x20000000U)
2260#define CAN_IE_ARAE_SHIFT (29U)
2261/*! ARAE - Access to reserved address interrupt enable.
2262 */
2263#define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK)
2264/*! @} */
2265
2266/*! @name ILS - Interrupt Line Select */
2267/*! @{ */
2268#define CAN_ILS_RF0NL_MASK (0x1U)
2269#define CAN_ILS_RF0NL_SHIFT (0U)
2270/*! RF0NL - Rx FIFO 0 new message interrupt line.
2271 */
2272#define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK)
2273#define CAN_ILS_RF0WL_MASK (0x2U)
2274#define CAN_ILS_RF0WL_SHIFT (1U)
2275/*! RF0WL - Rx FIFO 0 watermark reached interrupt line.
2276 */
2277#define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK)
2278#define CAN_ILS_RF0FL_MASK (0x4U)
2279#define CAN_ILS_RF0FL_SHIFT (2U)
2280/*! RF0FL - Rx FIFO 0 full interrupt line.
2281 */
2282#define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK)
2283#define CAN_ILS_RF0LL_MASK (0x8U)
2284#define CAN_ILS_RF0LL_SHIFT (3U)
2285/*! RF0LL - Rx FIFO 0 message lost interrupt line.
2286 */
2287#define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK)
2288#define CAN_ILS_RF1NL_MASK (0x10U)
2289#define CAN_ILS_RF1NL_SHIFT (4U)
2290/*! RF1NL - Rx FIFO 1 new message interrupt line.
2291 */
2292#define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK)
2293#define CAN_ILS_RF1WL_MASK (0x20U)
2294#define CAN_ILS_RF1WL_SHIFT (5U)
2295/*! RF1WL - Rx FIFO 1 watermark reached interrupt line.
2296 */
2297#define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK)
2298#define CAN_ILS_RF1FL_MASK (0x40U)
2299#define CAN_ILS_RF1FL_SHIFT (6U)
2300/*! RF1FL - Rx FIFO 1 full interrupt line.
2301 */
2302#define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK)
2303#define CAN_ILS_RF1LL_MASK (0x80U)
2304#define CAN_ILS_RF1LL_SHIFT (7U)
2305/*! RF1LL - Rx FIFO 1 message lost interrupt line.
2306 */
2307#define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK)
2308#define CAN_ILS_HPML_MASK (0x100U)
2309#define CAN_ILS_HPML_SHIFT (8U)
2310/*! HPML - High priority message interrupt line.
2311 */
2312#define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK)
2313#define CAN_ILS_TCL_MASK (0x200U)
2314#define CAN_ILS_TCL_SHIFT (9U)
2315/*! TCL - Transmission completed interrupt line.
2316 */
2317#define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK)
2318#define CAN_ILS_TCFL_MASK (0x400U)
2319#define CAN_ILS_TCFL_SHIFT (10U)
2320/*! TCFL - Transmission cancellation finished interrupt line.
2321 */
2322#define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK)
2323#define CAN_ILS_TFEL_MASK (0x800U)
2324#define CAN_ILS_TFEL_SHIFT (11U)
2325/*! TFEL - Tx FIFO empty interrupt line.
2326 */
2327#define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK)
2328#define CAN_ILS_TEFNL_MASK (0x1000U)
2329#define CAN_ILS_TEFNL_SHIFT (12U)
2330/*! TEFNL - Tx event FIFO new entry interrupt line.
2331 */
2332#define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK)
2333#define CAN_ILS_TEFWL_MASK (0x2000U)
2334#define CAN_ILS_TEFWL_SHIFT (13U)
2335/*! TEFWL - Tx event FIFO watermark reached interrupt line.
2336 */
2337#define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK)
2338#define CAN_ILS_TEFFL_MASK (0x4000U)
2339#define CAN_ILS_TEFFL_SHIFT (14U)
2340/*! TEFFL - Tx event FIFO full interrupt line.
2341 */
2342#define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK)
2343#define CAN_ILS_TEFLL_MASK (0x8000U)
2344#define CAN_ILS_TEFLL_SHIFT (15U)
2345/*! TEFLL - Tx event FIFO element lost interrupt line.
2346 */
2347#define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK)
2348#define CAN_ILS_TSWL_MASK (0x10000U)
2349#define CAN_ILS_TSWL_SHIFT (16U)
2350/*! TSWL - Timestamp wraparound interrupt line.
2351 */
2352#define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK)
2353#define CAN_ILS_MRAFL_MASK (0x20000U)
2354#define CAN_ILS_MRAFL_SHIFT (17U)
2355/*! MRAFL - Message RAM access failure interrupt line.
2356 */
2357#define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK)
2358#define CAN_ILS_TOOL_MASK (0x40000U)
2359#define CAN_ILS_TOOL_SHIFT (18U)
2360/*! TOOL - Timeout occurred interrupt line.
2361 */
2362#define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK)
2363#define CAN_ILS_DRXL_MASK (0x80000U)
2364#define CAN_ILS_DRXL_SHIFT (19U)
2365/*! DRXL - Message stored in dedicated Rx buffer interrupt line.
2366 */
2367#define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK)
2368#define CAN_ILS_BECL_MASK (0x100000U)
2369#define CAN_ILS_BECL_SHIFT (20U)
2370/*! BECL - Bit error corrected interrupt line.
2371 */
2372#define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK)
2373#define CAN_ILS_BEUL_MASK (0x200000U)
2374#define CAN_ILS_BEUL_SHIFT (21U)
2375/*! BEUL - Bit error uncorrected interrupt line.
2376 */
2377#define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK)
2378#define CAN_ILS_ELOL_MASK (0x400000U)
2379#define CAN_ILS_ELOL_SHIFT (22U)
2380/*! ELOL - Error logging overflow interrupt line.
2381 */
2382#define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK)
2383#define CAN_ILS_EPL_MASK (0x800000U)
2384#define CAN_ILS_EPL_SHIFT (23U)
2385/*! EPL - Error passive interrupt line.
2386 */
2387#define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK)
2388#define CAN_ILS_EWL_MASK (0x1000000U)
2389#define CAN_ILS_EWL_SHIFT (24U)
2390/*! EWL - Warning status interrupt line.
2391 */
2392#define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK)
2393#define CAN_ILS_BOL_MASK (0x2000000U)
2394#define CAN_ILS_BOL_SHIFT (25U)
2395/*! BOL - Bus_Off Status interrupt line.
2396 */
2397#define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK)
2398#define CAN_ILS_WDIL_MASK (0x4000000U)
2399#define CAN_ILS_WDIL_SHIFT (26U)
2400/*! WDIL - Watchdog interrupt line.
2401 */
2402#define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK)
2403#define CAN_ILS_PEAL_MASK (0x8000000U)
2404#define CAN_ILS_PEAL_SHIFT (27U)
2405/*! PEAL - Protocol error in arbitration phase interrupt line.
2406 */
2407#define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK)
2408#define CAN_ILS_PEDL_MASK (0x10000000U)
2409#define CAN_ILS_PEDL_SHIFT (28U)
2410/*! PEDL - Protocol error in data phase interrupt line.
2411 */
2412#define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK)
2413#define CAN_ILS_ARAL_MASK (0x20000000U)
2414#define CAN_ILS_ARAL_SHIFT (29U)
2415/*! ARAL - Access to reserved address interrupt line.
2416 */
2417#define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK)
2418/*! @} */
2419
2420/*! @name ILE - Interrupt Line Enable */
2421/*! @{ */
2422#define CAN_ILE_EINT0_MASK (0x1U)
2423#define CAN_ILE_EINT0_SHIFT (0U)
2424/*! EINT0 - Enable interrupt line 0.
2425 */
2426#define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK)
2427#define CAN_ILE_EINT1_MASK (0x2U)
2428#define CAN_ILE_EINT1_SHIFT (1U)
2429/*! EINT1 - Enable interrupt line 1.
2430 */
2431#define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK)
2432/*! @} */
2433
2434/*! @name GFC - Global Filter Configuration */
2435/*! @{ */
2436#define CAN_GFC_RRFE_MASK (0x1U)
2437#define CAN_GFC_RRFE_SHIFT (0U)
2438/*! RRFE - Reject remote frames extended.
2439 */
2440#define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK)
2441#define CAN_GFC_RRFS_MASK (0x2U)
2442#define CAN_GFC_RRFS_SHIFT (1U)
2443/*! RRFS - Reject remote frames standard.
2444 */
2445#define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK)
2446#define CAN_GFC_ANFE_MASK (0xCU)
2447#define CAN_GFC_ANFE_SHIFT (2U)
2448/*! ANFE - Accept non-matching frames extended.
2449 */
2450#define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK)
2451#define CAN_GFC_ANFS_MASK (0x30U)
2452#define CAN_GFC_ANFS_SHIFT (4U)
2453/*! ANFS - Accept non-matching frames standard.
2454 */
2455#define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK)
2456/*! @} */
2457
2458/*! @name SIDFC - Standard ID Filter Configuration */
2459/*! @{ */
2460#define CAN_SIDFC_FLSSA_MASK (0xFFFCU)
2461#define CAN_SIDFC_FLSSA_SHIFT (2U)
2462/*! FLSSA - Filter list standard start address.
2463 */
2464#define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK)
2465#define CAN_SIDFC_LSS_MASK (0xFF0000U)
2466#define CAN_SIDFC_LSS_SHIFT (16U)
2467/*! LSS - List size standard 0 = No standard message ID filter.
2468 */
2469#define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK)
2470/*! @} */
2471
2472/*! @name XIDFC - Extended ID Filter Configuration */
2473/*! @{ */
2474#define CAN_XIDFC_FLESA_MASK (0xFFFCU)
2475#define CAN_XIDFC_FLESA_SHIFT (2U)
2476/*! FLESA - Filter list extended start address.
2477 */
2478#define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK)
2479#define CAN_XIDFC_LSE_MASK (0xFF0000U)
2480#define CAN_XIDFC_LSE_SHIFT (16U)
2481/*! LSE - List size extended 0 = No extended message ID filter.
2482 */
2483#define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK)
2484/*! @} */
2485
2486/*! @name XIDAM - Extended ID AND Mask */
2487/*! @{ */
2488#define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU)
2489#define CAN_XIDAM_EIDM_SHIFT (0U)
2490/*! EIDM - Extended ID mask.
2491 */
2492#define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK)
2493/*! @} */
2494
2495/*! @name HPMS - High Priority Message Status */
2496/*! @{ */
2497#define CAN_HPMS_BIDX_MASK (0x3FU)
2498#define CAN_HPMS_BIDX_SHIFT (0U)
2499/*! BIDX - Buffer index.
2500 */
2501#define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK)
2502#define CAN_HPMS_MSI_MASK (0xC0U)
2503#define CAN_HPMS_MSI_SHIFT (6U)
2504/*! MSI - Message storage indicator.
2505 */
2506#define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK)
2507#define CAN_HPMS_FIDX_MASK (0x7F00U)
2508#define CAN_HPMS_FIDX_SHIFT (8U)
2509/*! FIDX - Filter index.
2510 */
2511#define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK)
2512#define CAN_HPMS_FLST_MASK (0x8000U)
2513#define CAN_HPMS_FLST_SHIFT (15U)
2514/*! FLST - Filter list.
2515 */
2516#define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK)
2517/*! @} */
2518
2519/*! @name NDAT1 - New Data 1 */
2520/*! @{ */
2521#define CAN_NDAT1_ND_MASK (0xFFFFFFFFU)
2522#define CAN_NDAT1_ND_SHIFT (0U)
2523/*! ND - New Data.
2524 */
2525#define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK)
2526/*! @} */
2527
2528/*! @name NDAT2 - New Data 2 */
2529/*! @{ */
2530#define CAN_NDAT2_ND_MASK (0xFFFFFFFFU)
2531#define CAN_NDAT2_ND_SHIFT (0U)
2532/*! ND - New Data.
2533 */
2534#define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK)
2535/*! @} */
2536
2537/*! @name RXF0C - Rx FIFO 0 Configuration */
2538/*! @{ */
2539#define CAN_RXF0C_F0SA_MASK (0xFFFCU)
2540#define CAN_RXF0C_F0SA_SHIFT (2U)
2541/*! F0SA - Rx FIFO 0 start address.
2542 */
2543#define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK)
2544#define CAN_RXF0C_F0S_MASK (0x7F0000U)
2545#define CAN_RXF0C_F0S_SHIFT (16U)
2546/*! F0S - Rx FIFO 0 size.
2547 */
2548#define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK)
2549#define CAN_RXF0C_F0WM_MASK (0x7F000000U)
2550#define CAN_RXF0C_F0WM_SHIFT (24U)
2551/*! F0WM - Rx FIFO 0 watermark 0 = Watermark interrupt disabled.
2552 */
2553#define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK)
2554#define CAN_RXF0C_F0OM_MASK (0x80000000U)
2555#define CAN_RXF0C_F0OM_SHIFT (31U)
2556/*! F0OM - FIFO 0 operation mode.
2557 */
2558#define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK)
2559/*! @} */
2560
2561/*! @name RXF0S - Rx FIFO 0 Status */
2562/*! @{ */
2563#define CAN_RXF0S_F0FL_MASK (0x7FU)
2564#define CAN_RXF0S_F0FL_SHIFT (0U)
2565/*! F0FL - Rx FIFO 0 fill level.
2566 */
2567#define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK)
2568#define CAN_RXF0S_F0GI_MASK (0x3F00U)
2569#define CAN_RXF0S_F0GI_SHIFT (8U)
2570/*! F0GI - Rx FIFO 0 get index.
2571 */
2572#define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK)
2573#define CAN_RXF0S_F0PI_MASK (0x3F0000U)
2574#define CAN_RXF0S_F0PI_SHIFT (16U)
2575/*! F0PI - Rx FIFO 0 put index.
2576 */
2577#define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK)
2578#define CAN_RXF0S_F0F_MASK (0x1000000U)
2579#define CAN_RXF0S_F0F_SHIFT (24U)
2580/*! F0F - Rx FIFO 0 full.
2581 */
2582#define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK)
2583#define CAN_RXF0S_RF0L_MASK (0x2000000U)
2584#define CAN_RXF0S_RF0L_SHIFT (25U)
2585/*! RF0L - Rx FIFO 0 message lost.
2586 */
2587#define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK)
2588/*! @} */
2589
2590/*! @name RXF0A - Rx FIFO 0 Acknowledge */
2591/*! @{ */
2592#define CAN_RXF0A_F0AI_MASK (0x3FU)
2593#define CAN_RXF0A_F0AI_SHIFT (0U)
2594/*! F0AI - Rx FIFO 0 acknowledge index.
2595 */
2596#define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK)
2597/*! @} */
2598
2599/*! @name RXBC - Rx Buffer Configuration */
2600/*! @{ */
2601#define CAN_RXBC_RBSA_MASK (0xFFFCU)
2602#define CAN_RXBC_RBSA_SHIFT (2U)
2603/*! RBSA - Rx buffer start address.
2604 */
2605#define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK)
2606/*! @} */
2607
2608/*! @name RXF1C - Rx FIFO 1 Configuration */
2609/*! @{ */
2610#define CAN_RXF1C_F1SA_MASK (0xFFFCU)
2611#define CAN_RXF1C_F1SA_SHIFT (2U)
2612/*! F1SA - Rx FIFO 1 start address.
2613 */
2614#define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK)
2615#define CAN_RXF1C_F1S_MASK (0x7F0000U)
2616#define CAN_RXF1C_F1S_SHIFT (16U)
2617/*! F1S - Rx FIFO 1 size 0 = No Rx FIFO 1.
2618 */
2619#define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK)
2620#define CAN_RXF1C_F1WM_MASK (0x7F000000U)
2621#define CAN_RXF1C_F1WM_SHIFT (24U)
2622/*! F1WM - Rx FIFO 1 watermark 0 = Watermark interrupt disabled.
2623 */
2624#define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK)
2625#define CAN_RXF1C_F1OM_MASK (0x80000000U)
2626#define CAN_RXF1C_F1OM_SHIFT (31U)
2627/*! F1OM - FIFO 1 operation mode.
2628 */
2629#define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK)
2630/*! @} */
2631
2632/*! @name RXF1S - Rx FIFO 1 Status */
2633/*! @{ */
2634#define CAN_RXF1S_F1FL_MASK (0x7FU)
2635#define CAN_RXF1S_F1FL_SHIFT (0U)
2636/*! F1FL - Rx FIFO 1 fill level.
2637 */
2638#define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK)
2639#define CAN_RXF1S_F1GI_MASK (0x3F00U)
2640#define CAN_RXF1S_F1GI_SHIFT (8U)
2641/*! F1GI - Rx FIFO 1 get index.
2642 */
2643#define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK)
2644#define CAN_RXF1S_F1PI_MASK (0x3F0000U)
2645#define CAN_RXF1S_F1PI_SHIFT (16U)
2646/*! F1PI - Rx FIFO 1 put index.
2647 */
2648#define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK)
2649#define CAN_RXF1S_F1F_MASK (0x1000000U)
2650#define CAN_RXF1S_F1F_SHIFT (24U)
2651/*! F1F - Rx FIFO 1 full.
2652 */
2653#define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK)
2654#define CAN_RXF1S_RF1L_MASK (0x2000000U)
2655#define CAN_RXF1S_RF1L_SHIFT (25U)
2656/*! RF1L - Rx FIFO 1 message lost.
2657 */
2658#define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK)
2659/*! @} */
2660
2661/*! @name RXF1A - Rx FIFO 1 Acknowledge */
2662/*! @{ */
2663#define CAN_RXF1A_F1AI_MASK (0x3FU)
2664#define CAN_RXF1A_F1AI_SHIFT (0U)
2665/*! F1AI - Rx FIFO 1 acknowledge index.
2666 */
2667#define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK)
2668/*! @} */
2669
2670/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */
2671/*! @{ */
2672#define CAN_RXESC_F0DS_MASK (0x7U)
2673#define CAN_RXESC_F0DS_SHIFT (0U)
2674/*! F0DS - Rx FIFO 0 data field size.
2675 */
2676#define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK)
2677#define CAN_RXESC_F1DS_MASK (0x70U)
2678#define CAN_RXESC_F1DS_SHIFT (4U)
2679/*! F1DS - Rx FIFO 1 data field size.
2680 */
2681#define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK)
2682#define CAN_RXESC_RBDS_MASK (0x700U)
2683#define CAN_RXESC_RBDS_SHIFT (8U)
2684/*! RBDS - .
2685 */
2686#define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK)
2687/*! @} */
2688
2689/*! @name TXBC - Tx Buffer Configuration */
2690/*! @{ */
2691#define CAN_TXBC_TBSA_MASK (0xFFFCU)
2692#define CAN_TXBC_TBSA_SHIFT (2U)
2693/*! TBSA - Tx buffers start address.
2694 */
2695#define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK)
2696#define CAN_TXBC_NDTB_MASK (0x3F0000U)
2697#define CAN_TXBC_NDTB_SHIFT (16U)
2698/*! NDTB - Number of dedicated transmit buffers 0 = No dedicated Tx buffers.
2699 */
2700#define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK)
2701#define CAN_TXBC_TFQS_MASK (0x3F000000U)
2702#define CAN_TXBC_TFQS_SHIFT (24U)
2703/*! TFQS - Transmit FIFO/queue size 0 = No tx FIFO/Queue.
2704 */
2705#define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK)
2706#define CAN_TXBC_TFQM_MASK (0x40000000U)
2707#define CAN_TXBC_TFQM_SHIFT (30U)
2708/*! TFQM - Tx FIFO/queue mode.
2709 */
2710#define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK)
2711/*! @} */
2712
2713/*! @name TXFQS - Tx FIFO/Queue Status */
2714/*! @{ */
2715#define CAN_TXFQS_TFGI_MASK (0x1F00U)
2716#define CAN_TXFQS_TFGI_SHIFT (8U)
2717/*! TFGI - Tx FIFO get index.
2718 */
2719#define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK)
2720#define CAN_TXFQS_TFQPI_MASK (0x1F0000U)
2721#define CAN_TXFQS_TFQPI_SHIFT (16U)
2722/*! TFQPI - Tx FIFO/queue put index.
2723 */
2724#define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK)
2725#define CAN_TXFQS_TFQF_MASK (0x200000U)
2726#define CAN_TXFQS_TFQF_SHIFT (21U)
2727/*! TFQF - Tx FIFO/queue full.
2728 */
2729#define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK)
2730/*! @} */
2731
2732/*! @name TXESC - Tx Buffer Element Size Configuration */
2733/*! @{ */
2734#define CAN_TXESC_TBDS_MASK (0x7U)
2735#define CAN_TXESC_TBDS_SHIFT (0U)
2736/*! TBDS - Tx buffer data field size.
2737 */
2738#define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK)
2739/*! @} */
2740
2741/*! @name TXBRP - Tx Buffer Request Pending */
2742/*! @{ */
2743#define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU)
2744#define CAN_TXBRP_TRP_SHIFT (0U)
2745/*! TRP - Transmission request pending.
2746 */
2747#define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK)
2748/*! @} */
2749
2750/*! @name TXBAR - Tx Buffer Add Request */
2751/*! @{ */
2752#define CAN_TXBAR_AR_MASK (0xFFFFFFFFU)
2753#define CAN_TXBAR_AR_SHIFT (0U)
2754/*! AR - Add request.
2755 */
2756#define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK)
2757/*! @} */
2758
2759/*! @name TXBCR - Tx Buffer Cancellation Request */
2760/*! @{ */
2761#define CAN_TXBCR_CR_MASK (0xFFFFFFFFU)
2762#define CAN_TXBCR_CR_SHIFT (0U)
2763/*! CR - Cancellation request.
2764 */
2765#define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK)
2766/*! @} */
2767
2768/*! @name TXBTO - Tx Buffer Transmission Occurred */
2769/*! @{ */
2770#define CAN_TXBTO_TO_MASK (0xFFFFFFFFU)
2771#define CAN_TXBTO_TO_SHIFT (0U)
2772/*! TO - Transmission occurred.
2773 */
2774#define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK)
2775/*! @} */
2776
2777/*! @name TXBCF - Tx Buffer Cancellation Finished */
2778/*! @{ */
2779#define CAN_TXBCF_TO_MASK (0xFFFFFFFFU)
2780#define CAN_TXBCF_TO_SHIFT (0U)
2781/*! TO - Cancellation finished.
2782 */
2783#define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK)
2784/*! @} */
2785
2786/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */
2787/*! @{ */
2788#define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU)
2789#define CAN_TXBTIE_TIE_SHIFT (0U)
2790/*! TIE - Transmission interrupt enable.
2791 */
2792#define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK)
2793/*! @} */
2794
2795/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */
2796/*! @{ */
2797#define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU)
2798#define CAN_TXBCIE_CFIE_SHIFT (0U)
2799/*! CFIE - Cancellation finished interrupt enable.
2800 */
2801#define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK)
2802/*! @} */
2803
2804/*! @name TXEFC - Tx Event FIFO Configuration */
2805/*! @{ */
2806#define CAN_TXEFC_EFSA_MASK (0xFFFCU)
2807#define CAN_TXEFC_EFSA_SHIFT (2U)
2808/*! EFSA - Event FIFO start address.
2809 */
2810#define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK)
2811#define CAN_TXEFC_EFS_MASK (0x3F0000U)
2812#define CAN_TXEFC_EFS_SHIFT (16U)
2813/*! EFS - Event FIFO size 0 = Tx event FIFO disabled.
2814 */
2815#define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK)
2816#define CAN_TXEFC_EFWM_MASK (0x3F000000U)
2817#define CAN_TXEFC_EFWM_SHIFT (24U)
2818/*! EFWM - Event FIFO watermark 0 = Watermark interrupt disabled.
2819 */
2820#define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK)
2821/*! @} */
2822
2823/*! @name TXEFS - Tx Event FIFO Status */
2824/*! @{ */
2825#define CAN_TXEFS_EFFL_MASK (0x3FU)
2826#define CAN_TXEFS_EFFL_SHIFT (0U)
2827/*! EFFL - Event FIFO fill level.
2828 */
2829#define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK)
2830#define CAN_TXEFS_EFGI_MASK (0x1F00U)
2831#define CAN_TXEFS_EFGI_SHIFT (8U)
2832/*! EFGI - Event FIFO get index.
2833 */
2834#define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK)
2835#define CAN_TXEFS_EFPI_MASK (0x3F0000U)
2836#define CAN_TXEFS_EFPI_SHIFT (16U)
2837/*! EFPI - Event FIFO put index.
2838 */
2839#define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK)
2840#define CAN_TXEFS_EFF_MASK (0x1000000U)
2841#define CAN_TXEFS_EFF_SHIFT (24U)
2842/*! EFF - Event FIFO full.
2843 */
2844#define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK)
2845#define CAN_TXEFS_TEFL_MASK (0x2000000U)
2846#define CAN_TXEFS_TEFL_SHIFT (25U)
2847/*! TEFL - Tx event FIFO element lost.
2848 */
2849#define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK)
2850/*! @} */
2851
2852/*! @name TXEFA - Tx Event FIFO Acknowledge */
2853/*! @{ */
2854#define CAN_TXEFA_EFAI_MASK (0x1FU)
2855#define CAN_TXEFA_EFAI_SHIFT (0U)
2856/*! EFAI - Event FIFO acknowledge index.
2857 */
2858#define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK)
2859/*! @} */
2860
2861/*! @name MRBA - CAN Message RAM Base Address */
2862/*! @{ */
2863#define CAN_MRBA_BA_MASK (0xFFFF0000U)
2864#define CAN_MRBA_BA_SHIFT (16U)
2865/*! BA - Base address for the message RAM in the chip memory map.
2866 */
2867#define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK)
2868/*! @} */
2869
2870/*! @name ETSCC - External Timestamp Counter Configuration */
2871/*! @{ */
2872#define CAN_ETSCC_ETCP_MASK (0x7FFU)
2873#define CAN_ETSCC_ETCP_SHIFT (0U)
2874/*! ETCP - External timestamp prescaler value.
2875 */
2876#define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK)
2877#define CAN_ETSCC_ETCE_MASK (0x80000000U)
2878#define CAN_ETSCC_ETCE_SHIFT (31U)
2879/*! ETCE - External timestamp counter enable.
2880 */
2881#define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK)
2882/*! @} */
2883
2884/*! @name ETSCV - External Timestamp Counter Value */
2885/*! @{ */
2886#define CAN_ETSCV_ETSC_MASK (0xFFFFU)
2887#define CAN_ETSCV_ETSC_SHIFT (0U)
2888/*! ETSC - External timestamp counter.
2889 */
2890#define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK)
2891/*! @} */
2892
2893
2894/*!
2895 * @}
2896 */ /* end of group CAN_Register_Masks */
2897
2898
2899/* CAN - Peripheral instance base addresses */
2900/** Peripheral CAN0 base address */
2901#define CAN0_BASE (0x4009D000u)
2902/** Peripheral CAN0 base pointer */
2903#define CAN0 ((CAN_Type *)CAN0_BASE)
2904/** Peripheral CAN1 base address */
2905#define CAN1_BASE (0x4009E000u)
2906/** Peripheral CAN1 base pointer */
2907#define CAN1 ((CAN_Type *)CAN1_BASE)
2908/** Array initializer of CAN peripheral base addresses */
2909#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
2910/** Array initializer of CAN peripheral base pointers */
2911#define CAN_BASE_PTRS { CAN0, CAN1 }
2912/** Interrupt vectors for the CAN peripheral type */
2913#define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } }
2914
2915/*!
2916 * @}
2917 */ /* end of group CAN_Peripheral_Access_Layer */
2918
2919
2920/* ----------------------------------------------------------------------------
2921 -- CRC Peripheral Access Layer
2922 ---------------------------------------------------------------------------- */
2923
2924/*!
2925 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
2926 * @{
2927 */
2928
2929/** CRC - Register Layout Typedef */
2930typedef struct {
2931 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
2932 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
2933 union { /* offset: 0x8 */
2934 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
2935 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
2936 };
2937} CRC_Type;
2938
2939/* ----------------------------------------------------------------------------
2940 -- CRC Register Masks
2941 ---------------------------------------------------------------------------- */
2942
2943/*!
2944 * @addtogroup CRC_Register_Masks CRC Register Masks
2945 * @{
2946 */
2947
2948/*! @name MODE - CRC mode register */
2949/*! @{ */
2950#define CRC_MODE_CRC_POLY_MASK (0x3U)
2951#define CRC_MODE_CRC_POLY_SHIFT (0U)
2952/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
2953 */
2954#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
2955#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
2956#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
2957/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
2958 */
2959#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
2960#define CRC_MODE_CMPL_WR_MASK (0x8U)
2961#define CRC_MODE_CMPL_WR_SHIFT (3U)
2962/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
2963 */
2964#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
2965#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
2966#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
2967/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
2968 */
2969#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
2970#define CRC_MODE_CMPL_SUM_MASK (0x20U)
2971#define CRC_MODE_CMPL_SUM_SHIFT (5U)
2972/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
2973 */
2974#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
2975/*! @} */
2976
2977/*! @name SEED - CRC seed register */
2978/*! @{ */
2979#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
2980#define CRC_SEED_CRC_SEED_SHIFT (0U)
2981/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
2982 * selected bit order and 1's complement pre-processes. A write access to this register will
2983 * overrule the CRC calculation in progresses.
2984 */
2985#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
2986/*! @} */
2987
2988/*! @name SUM - CRC checksum register */
2989/*! @{ */
2990#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
2991#define CRC_SUM_CRC_SUM_SHIFT (0U)
2992/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
2993 */
2994#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
2995/*! @} */
2996
2997/*! @name WR_DATA - CRC data register */
2998/*! @{ */
2999#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
3000#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
3001/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
3002 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
3003 * accept back-to-back transactions.
3004 */
3005#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
3006/*! @} */
3007
3008
3009/*!
3010 * @}
3011 */ /* end of group CRC_Register_Masks */
3012
3013
3014/* CRC - Peripheral instance base addresses */
3015/** Peripheral CRC_ENGINE base address */
3016#define CRC_ENGINE_BASE (0x40095000u)
3017/** Peripheral CRC_ENGINE base pointer */
3018#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
3019/** Array initializer of CRC peripheral base addresses */
3020#define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
3021/** Array initializer of CRC peripheral base pointers */
3022#define CRC_BASE_PTRS { CRC_ENGINE }
3023
3024/*!
3025 * @}
3026 */ /* end of group CRC_Peripheral_Access_Layer */
3027
3028
3029/* ----------------------------------------------------------------------------
3030 -- CTIMER Peripheral Access Layer
3031 ---------------------------------------------------------------------------- */
3032
3033/*!
3034 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
3035 * @{
3036 */
3037
3038/** CTIMER - Register Layout Typedef */
3039typedef struct {
3040 __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
3041 __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
3042 __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */
3043 __IO uint32_t PR; /**< Prescale Register, offset: 0xC */
3044 __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */
3045 __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */
3046 __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
3047 __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
3048 __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
3049 __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
3050 uint8_t RESERVED_0[48];
3051 __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
3052 __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
3053 __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
3054} CTIMER_Type;
3055
3056/* ----------------------------------------------------------------------------
3057 -- CTIMER Register Masks
3058 ---------------------------------------------------------------------------- */
3059
3060/*!
3061 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
3062 * @{
3063 */
3064
3065/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
3066/*! @{ */
3067#define CTIMER_IR_MR0INT_MASK (0x1U)
3068#define CTIMER_IR_MR0INT_SHIFT (0U)
3069/*! MR0INT - Interrupt flag for match channel 0.
3070 */
3071#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
3072#define CTIMER_IR_MR1INT_MASK (0x2U)
3073#define CTIMER_IR_MR1INT_SHIFT (1U)
3074/*! MR1INT - Interrupt flag for match channel 1.
3075 */
3076#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
3077#define CTIMER_IR_MR2INT_MASK (0x4U)
3078#define CTIMER_IR_MR2INT_SHIFT (2U)
3079/*! MR2INT - Interrupt flag for match channel 2.
3080 */
3081#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
3082#define CTIMER_IR_MR3INT_MASK (0x8U)
3083#define CTIMER_IR_MR3INT_SHIFT (3U)
3084/*! MR3INT - Interrupt flag for match channel 3.
3085 */
3086#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
3087#define CTIMER_IR_CR0INT_MASK (0x10U)
3088#define CTIMER_IR_CR0INT_SHIFT (4U)
3089/*! CR0INT - Interrupt flag for capture channel 0 event.
3090 */
3091#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
3092#define CTIMER_IR_CR1INT_MASK (0x20U)
3093#define CTIMER_IR_CR1INT_SHIFT (5U)
3094/*! CR1INT - Interrupt flag for capture channel 1 event.
3095 */
3096#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
3097#define CTIMER_IR_CR2INT_MASK (0x40U)
3098#define CTIMER_IR_CR2INT_SHIFT (6U)
3099/*! CR2INT - Interrupt flag for capture channel 2 event.
3100 */
3101#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
3102#define CTIMER_IR_CR3INT_MASK (0x80U)
3103#define CTIMER_IR_CR3INT_SHIFT (7U)
3104/*! CR3INT - Interrupt flag for capture channel 3 event.
3105 */
3106#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
3107/*! @} */
3108
3109/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
3110/*! @{ */
3111#define CTIMER_TCR_CEN_MASK (0x1U)
3112#define CTIMER_TCR_CEN_SHIFT (0U)
3113/*! CEN - Counter enable.
3114 * 0b0..Disabled.The counters are disabled.
3115 * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
3116 */
3117#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
3118#define CTIMER_TCR_CRST_MASK (0x2U)
3119#define CTIMER_TCR_CRST_SHIFT (1U)
3120/*! CRST - Counter reset.
3121 * 0b0..Disabled. Do nothing.
3122 * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
3123 * the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
3124 */
3125#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
3126/*! @} */
3127
3128/*! @name TC - Timer Counter */
3129/*! @{ */
3130#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
3131#define CTIMER_TC_TCVAL_SHIFT (0U)
3132/*! TCVAL - Timer counter value.
3133 */
3134#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
3135/*! @} */
3136
3137/*! @name PR - Prescale Register */
3138/*! @{ */
3139#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
3140#define CTIMER_PR_PRVAL_SHIFT (0U)
3141/*! PRVAL - Prescale counter value.
3142 */
3143#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
3144/*! @} */
3145
3146/*! @name PC - Prescale Counter */
3147/*! @{ */
3148#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
3149#define CTIMER_PC_PCVAL_SHIFT (0U)
3150/*! PCVAL - Prescale counter value.
3151 */
3152#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
3153/*! @} */
3154
3155/*! @name MCR - Match Control Register */
3156/*! @{ */
3157#define CTIMER_MCR_MR0I_MASK (0x1U)
3158#define CTIMER_MCR_MR0I_SHIFT (0U)
3159/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
3160 */
3161#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
3162#define CTIMER_MCR_MR0R_MASK (0x2U)
3163#define CTIMER_MCR_MR0R_SHIFT (1U)
3164/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it.
3165 */
3166#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
3167#define CTIMER_MCR_MR0S_MASK (0x4U)
3168#define CTIMER_MCR_MR0S_SHIFT (2U)
3169/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
3170 */
3171#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
3172#define CTIMER_MCR_MR1I_MASK (0x8U)
3173#define CTIMER_MCR_MR1I_SHIFT (3U)
3174/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
3175 */
3176#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
3177#define CTIMER_MCR_MR1R_MASK (0x10U)
3178#define CTIMER_MCR_MR1R_SHIFT (4U)
3179/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it.
3180 */
3181#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
3182#define CTIMER_MCR_MR1S_MASK (0x20U)
3183#define CTIMER_MCR_MR1S_SHIFT (5U)
3184/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
3185 */
3186#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
3187#define CTIMER_MCR_MR2I_MASK (0x40U)
3188#define CTIMER_MCR_MR2I_SHIFT (6U)
3189/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
3190 */
3191#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
3192#define CTIMER_MCR_MR2R_MASK (0x80U)
3193#define CTIMER_MCR_MR2R_SHIFT (7U)
3194/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it.
3195 */
3196#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
3197#define CTIMER_MCR_MR2S_MASK (0x100U)
3198#define CTIMER_MCR_MR2S_SHIFT (8U)
3199/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
3200 */
3201#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
3202#define CTIMER_MCR_MR3I_MASK (0x200U)
3203#define CTIMER_MCR_MR3I_SHIFT (9U)
3204/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
3205 */
3206#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
3207#define CTIMER_MCR_MR3R_MASK (0x400U)
3208#define CTIMER_MCR_MR3R_SHIFT (10U)
3209/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it.
3210 */
3211#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
3212#define CTIMER_MCR_MR3S_MASK (0x800U)
3213#define CTIMER_MCR_MR3S_SHIFT (11U)
3214/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
3215 */
3216#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
3217#define CTIMER_MCR_MR0RL_MASK (0x1000000U)
3218#define CTIMER_MCR_MR0RL_SHIFT (24U)
3219/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
3220 * (either via a match event or a write to bit 1 of the TCR).
3221 */
3222#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
3223#define CTIMER_MCR_MR1RL_MASK (0x2000000U)
3224#define CTIMER_MCR_MR1RL_SHIFT (25U)
3225/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
3226 * (either via a match event or a write to bit 1 of the TCR).
3227 */
3228#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
3229#define CTIMER_MCR_MR2RL_MASK (0x4000000U)
3230#define CTIMER_MCR_MR2RL_SHIFT (26U)
3231/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
3232 * (either via a match event or a write to bit 1 of the TCR).
3233 */
3234#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
3235#define CTIMER_MCR_MR3RL_MASK (0x8000000U)
3236#define CTIMER_MCR_MR3RL_SHIFT (27U)
3237/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
3238 * (either via a match event or a write to bit 1 of the TCR).
3239 */
3240#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
3241/*! @} */
3242
3243/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
3244/*! @{ */
3245#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
3246#define CTIMER_MR_MATCH_SHIFT (0U)
3247/*! MATCH - Timer counter match value.
3248 */
3249#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
3250/*! @} */
3251
3252/* The count of CTIMER_MR */
3253#define CTIMER_MR_COUNT (4U)
3254
3255/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
3256/*! @{ */
3257#define CTIMER_CCR_CAP0RE_MASK (0x1U)
3258#define CTIMER_CCR_CAP0RE_SHIFT (0U)
3259/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
3260 * the contents of TC. 0 = disabled. 1 = enabled.
3261 */
3262#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
3263#define CTIMER_CCR_CAP0FE_MASK (0x2U)
3264#define CTIMER_CCR_CAP0FE_SHIFT (1U)
3265/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
3266 * the contents of TC. 0 = disabled. 1 = enabled.
3267 */
3268#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
3269#define CTIMER_CCR_CAP0I_MASK (0x4U)
3270#define CTIMER_CCR_CAP0I_SHIFT (2U)
3271/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
3272 */
3273#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
3274#define CTIMER_CCR_CAP1RE_MASK (0x8U)
3275#define CTIMER_CCR_CAP1RE_SHIFT (3U)
3276/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
3277 * the contents of TC. 0 = disabled. 1 = enabled.
3278 */
3279#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
3280#define CTIMER_CCR_CAP1FE_MASK (0x10U)
3281#define CTIMER_CCR_CAP1FE_SHIFT (4U)
3282/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
3283 * the contents of TC. 0 = disabled. 1 = enabled.
3284 */
3285#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
3286#define CTIMER_CCR_CAP1I_MASK (0x20U)
3287#define CTIMER_CCR_CAP1I_SHIFT (5U)
3288/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
3289 */
3290#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
3291#define CTIMER_CCR_CAP2RE_MASK (0x40U)
3292#define CTIMER_CCR_CAP2RE_SHIFT (6U)
3293/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
3294 * the contents of TC. 0 = disabled. 1 = enabled.
3295 */
3296#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
3297#define CTIMER_CCR_CAP2FE_MASK (0x80U)
3298#define CTIMER_CCR_CAP2FE_SHIFT (7U)
3299/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
3300 * the contents of TC. 0 = disabled. 1 = enabled.
3301 */
3302#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
3303#define CTIMER_CCR_CAP2I_MASK (0x100U)
3304#define CTIMER_CCR_CAP2I_SHIFT (8U)
3305/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
3306 */
3307#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
3308#define CTIMER_CCR_CAP3RE_MASK (0x200U)
3309#define CTIMER_CCR_CAP3RE_SHIFT (9U)
3310/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with
3311 * the contents of TC. 0 = disabled. 1 = enabled.
3312 */
3313#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
3314#define CTIMER_CCR_CAP3FE_MASK (0x400U)
3315#define CTIMER_CCR_CAP3FE_SHIFT (10U)
3316/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with
3317 * the contents of TC. 0 = disabled. 1 = enabled.
3318 */
3319#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
3320#define CTIMER_CCR_CAP3I_MASK (0x800U)
3321#define CTIMER_CCR_CAP3I_SHIFT (11U)
3322/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
3323 */
3324#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
3325/*! @} */
3326
3327/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
3328/*! @{ */
3329#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
3330#define CTIMER_CR_CAP_SHIFT (0U)
3331/*! CAP - Timer counter capture value.
3332 */
3333#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
3334/*! @} */
3335
3336/* The count of CTIMER_CR */
3337#define CTIMER_CR_COUNT (4U)
3338
3339/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
3340/*! @{ */
3341#define CTIMER_EMR_EM0_MASK (0x1U)
3342#define CTIMER_EMR_EM0_SHIFT (0U)
3343/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
3344 * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
3345 * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
3346 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
3347 */
3348#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
3349#define CTIMER_EMR_EM1_MASK (0x2U)
3350#define CTIMER_EMR_EM1_SHIFT (1U)
3351/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
3352 * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
3353 * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
3354 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
3355 */
3356#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
3357#define CTIMER_EMR_EM2_MASK (0x4U)
3358#define CTIMER_EMR_EM2_SHIFT (2U)
3359/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
3360 * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
3361 * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
3362 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
3363 */
3364#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
3365#define CTIMER_EMR_EM3_MASK (0x8U)
3366#define CTIMER_EMR_EM3_SHIFT (3U)
3367/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
3368 * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
3369 * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
3370 * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
3371 */
3372#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
3373#define CTIMER_EMR_EMC0_MASK (0x30U)
3374#define CTIMER_EMR_EMC0_SHIFT (4U)
3375/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
3376 * 0b00..Do Nothing.
3377 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
3378 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
3379 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3380 */
3381#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
3382#define CTIMER_EMR_EMC1_MASK (0xC0U)
3383#define CTIMER_EMR_EMC1_SHIFT (6U)
3384/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
3385 * 0b00..Do Nothing.
3386 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
3387 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
3388 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3389 */
3390#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
3391#define CTIMER_EMR_EMC2_MASK (0x300U)
3392#define CTIMER_EMR_EMC2_SHIFT (8U)
3393/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
3394 * 0b00..Do Nothing.
3395 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
3396 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
3397 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3398 */
3399#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
3400#define CTIMER_EMR_EMC3_MASK (0xC00U)
3401#define CTIMER_EMR_EMC3_SHIFT (10U)
3402/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
3403 * 0b00..Do Nothing.
3404 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
3405 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
3406 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3407 */
3408#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
3409/*! @} */
3410
3411/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
3412/*! @{ */
3413#define CTIMER_CTCR_CTMODE_MASK (0x3U)
3414#define CTIMER_CTCR_CTMODE_SHIFT (0U)
3415/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
3416 * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
3417 * is incremented when the Prescale Counter matches the Prescale Register.
3418 * 0b00..Timer Mode. Incremented every rising APB bus clock edge.
3419 * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
3420 * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
3421 * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
3422 */
3423#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
3424#define CTIMER_CTCR_CINSEL_MASK (0xCU)
3425#define CTIMER_CTCR_CINSEL_SHIFT (2U)
3426/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
3427 * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
3428 * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
3429 * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
3430 * same timer.
3431 * 0b00..Channel 0. CAPn.0 for CTIMERn
3432 * 0b01..Channel 1. CAPn.1 for CTIMERn
3433 * 0b10..Channel 2. CAPn.2 for CTIMERn
3434 * 0b11..Channel 3. CAPn.3 for CTIMERn
3435 */
3436#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
3437#define CTIMER_CTCR_ENCC_MASK (0x10U)
3438#define CTIMER_CTCR_ENCC_SHIFT (4U)
3439/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
3440 * capture-edge event specified in bits 7:5 occurs.
3441 */
3442#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
3443#define CTIMER_CTCR_SELCC_MASK (0xE0U)
3444#define CTIMER_CTCR_SELCC_SHIFT (5U)
3445/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
3446 * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
3447 * 0x3 and 0x6 to 0x7 are reserved.
3448 * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
3449 * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
3450 * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
3451 * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
3452 * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
3453 * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
3454 */
3455#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
3456/*! @} */
3457
3458/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
3459/*! @{ */
3460#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
3461#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
3462/*! PWMEN0 - PWM mode enable for channel0.
3463 * 0b0..Match. CTIMERn_MAT0 is controlled by EM0.
3464 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
3465 */
3466#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
3467#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
3468#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
3469/*! PWMEN1 - PWM mode enable for channel1.
3470 * 0b0..Match. CTIMERn_MAT01 is controlled by EM1.
3471 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
3472 */
3473#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
3474#define CTIMER_PWMC_PWMEN2_MASK (0x4U)
3475#define CTIMER_PWMC_PWMEN2_SHIFT (2U)
3476/*! PWMEN2 - PWM mode enable for channel2.
3477 * 0b0..Match. CTIMERn_MAT2 is controlled by EM2.
3478 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
3479 */
3480#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
3481#define CTIMER_PWMC_PWMEN3_MASK (0x8U)
3482#define CTIMER_PWMC_PWMEN3_SHIFT (3U)
3483/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
3484 * 0b0..Match. CTIMERn_MAT3 is controlled by EM3.
3485 * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
3486 */
3487#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
3488/*! @} */
3489
3490/*! @name MSR - Match Shadow Register */
3491/*! @{ */
3492#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU)
3493#define CTIMER_MSR_SHADOWW_SHIFT (0U)
3494/*! SHADOWW - Timer counter match shadow value.
3495 */
3496#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)
3497/*! @} */
3498
3499/* The count of CTIMER_MSR */
3500#define CTIMER_MSR_COUNT (4U)
3501
3502
3503/*!
3504 * @}
3505 */ /* end of group CTIMER_Register_Masks */
3506
3507
3508/* CTIMER - Peripheral instance base addresses */
3509/** Peripheral CTIMER0 base address */
3510#define CTIMER0_BASE (0x40008000u)
3511/** Peripheral CTIMER0 base pointer */
3512#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
3513/** Peripheral CTIMER1 base address */
3514#define CTIMER1_BASE (0x40009000u)
3515/** Peripheral CTIMER1 base pointer */
3516#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
3517/** Peripheral CTIMER2 base address */
3518#define CTIMER2_BASE (0x40028000u)
3519/** Peripheral CTIMER2 base pointer */
3520#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
3521/** Peripheral CTIMER3 base address */
3522#define CTIMER3_BASE (0x40048000u)
3523/** Peripheral CTIMER3 base pointer */
3524#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
3525/** Peripheral CTIMER4 base address */
3526#define CTIMER4_BASE (0x40049000u)
3527/** Peripheral CTIMER4 base pointer */
3528#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
3529/** Array initializer of CTIMER peripheral base addresses */
3530#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
3531/** Array initializer of CTIMER peripheral base pointers */
3532#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
3533/** Interrupt vectors for the CTIMER peripheral type */
3534#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
3535
3536/*!
3537 * @}
3538 */ /* end of group CTIMER_Peripheral_Access_Layer */
3539
3540
3541/* ----------------------------------------------------------------------------
3542 -- DMA Peripheral Access Layer
3543 ---------------------------------------------------------------------------- */
3544
3545/*!
3546 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
3547 * @{
3548 */
3549
3550/** DMA - Register Layout Typedef */
3551typedef struct {
3552 __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
3553 __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
3554 __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
3555 uint8_t RESERVED_0[20];
3556 struct { /* offset: 0x20, array step: 0x5C */
3557 __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
3558 uint8_t RESERVED_0[4];
3559 __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
3560 uint8_t RESERVED_1[4];
3561 __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
3562 uint8_t RESERVED_2[4];
3563 __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
3564 uint8_t RESERVED_3[4];
3565 __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
3566 uint8_t RESERVED_4[4];
3567 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
3568 uint8_t RESERVED_5[4];
3569 __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
3570 uint8_t RESERVED_6[4];
3571 __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
3572 uint8_t RESERVED_7[4];
3573 __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
3574 uint8_t RESERVED_8[4];
3575 __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
3576 uint8_t RESERVED_9[4];
3577 __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
3578 uint8_t RESERVED_10[4];
3579 __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
3580 } COMMON[1];
3581 uint8_t RESERVED_1[900];
3582 struct { /* offset: 0x400, array step: 0x10 */
3583 __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
3584 __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
3585 __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
3586 uint8_t RESERVED_0[4];
3587 } CHANNEL[32];
3588} DMA_Type;
3589
3590/* ----------------------------------------------------------------------------
3591 -- DMA Register Masks
3592 ---------------------------------------------------------------------------- */
3593
3594/*!
3595 * @addtogroup DMA_Register_Masks DMA Register Masks
3596 * @{
3597 */
3598
3599/*! @name CTRL - DMA control. */
3600/*! @{ */
3601#define DMA_CTRL_ENABLE_MASK (0x1U)
3602#define DMA_CTRL_ENABLE_SHIFT (0U)
3603/*! ENABLE - DMA controller master enable.
3604 * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
3605 * disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
3606 * 0b1..Enabled. The DMA controller is enabled.
3607 */
3608#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
3609/*! @} */
3610
3611/*! @name INTSTAT - Interrupt status. */
3612/*! @{ */
3613#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
3614#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
3615/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
3616 * 0b0..Not pending. No enabled interrupts are pending.
3617 * 0b1..Pending. At least one enabled interrupt is pending.
3618 */
3619#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
3620#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
3621#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
3622/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
3623 * 0b0..Not pending. No error interrupts are pending.
3624 * 0b1..Pending. At least one error interrupt is pending.
3625 */
3626#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
3627/*! @} */
3628
3629/*! @name SRAMBASE - SRAM address of the channel configuration table. */
3630/*! @{ */
3631#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
3632#define DMA_SRAMBASE_OFFSET_SHIFT (9U)
3633/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
3634 * table must begin on a 512 byte boundary.
3635 */
3636#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
3637/*! @} */
3638
3639/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
3640/*! @{ */
3641#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)
3642#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
3643/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
3644 * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
3645 */
3646#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
3647/*! @} */
3648
3649/* The count of DMA_COMMON_ENABLESET */
3650#define DMA_COMMON_ENABLESET_COUNT (1U)
3651
3652/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
3653/*! @{ */
3654#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)
3655#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
3656/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
3657 * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
3658 * are reserved.
3659 */
3660#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
3661/*! @} */
3662
3663/* The count of DMA_COMMON_ENABLECLR */
3664#define DMA_COMMON_ENABLECLR_COUNT (1U)
3665
3666/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
3667/*! @{ */
3668#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)
3669#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
3670/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
3671 * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
3672 */
3673#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
3674/*! @} */
3675
3676/* The count of DMA_COMMON_ACTIVE */
3677#define DMA_COMMON_ACTIVE_COUNT (1U)
3678
3679/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
3680/*! @{ */
3681#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)
3682#define DMA_COMMON_BUSY_BSY_SHIFT (0U)
3683/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
3684 * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
3685 */
3686#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
3687/*! @} */
3688
3689/* The count of DMA_COMMON_BUSY */
3690#define DMA_COMMON_BUSY_COUNT (1U)
3691
3692/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
3693/*! @{ */
3694#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)
3695#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
3696/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
3697 * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
3698 * not active. 1 = error interrupt is active.
3699 */
3700#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
3701/*! @} */
3702
3703/* The count of DMA_COMMON_ERRINT */
3704#define DMA_COMMON_ERRINT_COUNT (1U)
3705
3706/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
3707/*! @{ */
3708#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)
3709#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
3710/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
3711 * number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
3712 * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
3713 */
3714#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
3715/*! @} */
3716
3717/* The count of DMA_COMMON_INTENSET */
3718#define DMA_COMMON_INTENSET_COUNT (1U)
3719
3720/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
3721/*! @{ */
3722#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)
3723#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
3724/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
3725 * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
3726 * reserved.
3727 */
3728#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
3729/*! @} */
3730
3731/* The count of DMA_COMMON_INTENCLR */
3732#define DMA_COMMON_INTENCLR_COUNT (1U)
3733
3734/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
3735/*! @{ */
3736#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)
3737#define DMA_COMMON_INTA_IA_SHIFT (0U)
3738/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
3739 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
3740 * interrupt A is not active. 1 = the DMA channel interrupt A is active.
3741 */
3742#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
3743/*! @} */
3744
3745/* The count of DMA_COMMON_INTA */
3746#define DMA_COMMON_INTA_COUNT (1U)
3747
3748/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
3749/*! @{ */
3750#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)
3751#define DMA_COMMON_INTB_IB_SHIFT (0U)
3752/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
3753 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
3754 * interrupt B is not active. 1 = the DMA channel interrupt B is active.
3755 */
3756#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
3757/*! @} */
3758
3759/* The count of DMA_COMMON_INTB */
3760#define DMA_COMMON_INTB_COUNT (1U)
3761
3762/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
3763/*! @{ */
3764#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)
3765#define DMA_COMMON_SETVALID_SV_SHIFT (0U)
3766/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
3767 * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
3768 * VALIDPENDING control bit for DMA channel n
3769 */
3770#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
3771/*! @} */
3772
3773/* The count of DMA_COMMON_SETVALID */
3774#define DMA_COMMON_SETVALID_COUNT (1U)
3775
3776/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
3777/*! @{ */
3778#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)
3779#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
3780/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
3781 * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
3782 * sets the TRIG bit for DMA channel n.
3783 */
3784#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
3785/*! @} */
3786
3787/* The count of DMA_COMMON_SETTRIG */
3788#define DMA_COMMON_SETTRIG_COUNT (1U)
3789
3790/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
3791/*! @{ */
3792#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)
3793#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
3794/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
3795 * 1 = aborts DMA operations on channel n.
3796 */
3797#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
3798/*! @} */
3799
3800/* The count of DMA_COMMON_ABORT */
3801#define DMA_COMMON_ABORT_COUNT (1U)
3802
3803/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
3804/*! @{ */
3805#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
3806#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
3807/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
3808 * move, any peripheral DMA request associated with that channel can be disabled to prevent any
3809 * interaction between the peripheral and the DMA controller.
3810 * 0b0..Disabled. Peripheral DMA requests are disabled.
3811 * 0b1..Enabled. Peripheral DMA requests are enabled.
3812 */
3813#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
3814#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
3815#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
3816/*! HWTRIGEN - Hardware Triggering Enable for this channel.
3817 * 0b0..Disabled. Hardware triggering is not used.
3818 * 0b1..Enabled. Use hardware triggering.
3819 */
3820#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
3821#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
3822#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
3823/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
3824 * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
3825 * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
3826 */
3827#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
3828#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
3829#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
3830/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
3831 * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
3832 * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
3833 * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
3834 * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
3835 * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
3836 * current BURSTPOWER length are completed.
3837 */
3838#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
3839#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
3840#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
3841/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
3842 * 0b0..Single transfer. Hardware trigger causes a single transfer.
3843 * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
3844 * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a
3845 * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
3846 * complete.
3847 */
3848#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
3849#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
3850#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
3851/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
3852 * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
3853 * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
3854 * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that
3855 * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:
3856 * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =
3857 * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The
3858 * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
3859 * multiple of the burst size.
3860 */
3861#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
3862#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
3863#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
3864/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
3865 * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this
3866 * could be used to read several sequential registers from a peripheral for each DMA burst,
3867 * reading the same registers again for each burst.
3868 * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
3869 * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
3870 */
3871#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
3872#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
3873#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
3874/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
3875 * 'wrapped', meaning that the destination address range for each burst will be the same. As an
3876 * example, this could be used to write several sequential registers to a peripheral for each DMA
3877 * burst, writing the same registers again for each burst.
3878 * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
3879 * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
3880 */
3881#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
3882#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
3883#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
3884/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority
3885 * levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
3886 */
3887#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
3888/*! @} */
3889
3890/* The count of DMA_CHANNEL_CFG */
3891#define DMA_CHANNEL_CFG_COUNT (32U)
3892
3893/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
3894/*! @{ */
3895#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
3896#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
3897/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the
3898 * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
3899 * 0b0..No effect. No effect on DMA operation.
3900 * 0b1..Valid pending.
3901 */
3902#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
3903#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
3904#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
3905/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is
3906 * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
3907 * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
3908 * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
3909 */
3910#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
3911/*! @} */
3912
3913/* The count of DMA_CHANNEL_CTLSTAT */
3914#define DMA_CHANNEL_CTLSTAT_COUNT (32U)
3915
3916/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
3917/*! @{ */
3918#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
3919#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
3920/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor
3921 * is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
3922 * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
3923 * 0b1..Valid. The current channel descriptor is considered valid.
3924 */
3925#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
3926#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
3927#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
3928/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current
3929 * descriptor is exhausted. Reloading allows ping-pong and linked transfers.
3930 * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
3931 * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.
3932 */
3933#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
3934#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
3935#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
3936/*! SWTRIG - Software Trigger.
3937 * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by
3938 * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
3939 * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not
3940 * be used with level triggering when TRIGBURST = 0.
3941 */
3942#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
3943#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)
3944#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)
3945/*! CLRTRIG - Clear Trigger.
3946 * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
3947 * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted
3948 */
3949#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
3950#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)
3951#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)
3952/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between
3953 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
3954 * convention, interrupt A may be used when only one interrupt flag is needed.
3955 * 0b0..No effect.
3956 * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
3957 */
3958#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
3959#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)
3960#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)
3961/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between
3962 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
3963 * convention, interrupt A may be used when only one interrupt flag is needed.
3964 * 0b0..No effect.
3965 * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
3966 */
3967#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
3968#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)
3969#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)
3970/*! WIDTH - Transfer width used for this DMA channel.
3971 * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
3972 * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
3973 * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
3974 * 0b11..Reserved. Reserved setting, do not use.
3975 */
3976#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
3977#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)
3978#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)
3979/*! SRCINC - Determines whether the source address is incremented for each DMA transfer.
3980 * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
3981 * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is
3982 * the usual case when the source is memory.
3983 * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
3984 * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
3985 */
3986#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
3987#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)
3988#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)
3989/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer.
3990 * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when
3991 * the destination is a peripheral device.
3992 * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer.
3993 * This is the usual case when the destination is memory.
3994 * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
3995 * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
3996 */
3997#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
3998#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)
3999#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)
4000/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes
4001 * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller
4002 * uses this bit field during transfer to count down. Hence, it cannot be used by software to read
4003 * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1
4004 * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of
4005 * 1,024 transfers will be performed.
4006 */
4007#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
4008/*! @} */
4009
4010/* The count of DMA_CHANNEL_XFERCFG */
4011#define DMA_CHANNEL_XFERCFG_COUNT (32U)
4012
4013
4014/*!
4015 * @}
4016 */ /* end of group DMA_Register_Masks */
4017
4018
4019/* DMA - Peripheral instance base addresses */
4020/** Peripheral DMA0 base address */
4021#define DMA0_BASE (0x40082000u)
4022/** Peripheral DMA0 base pointer */
4023#define DMA0 ((DMA_Type *)DMA0_BASE)
4024/** Array initializer of DMA peripheral base addresses */
4025#define DMA_BASE_ADDRS { DMA0_BASE }
4026/** Array initializer of DMA peripheral base pointers */
4027#define DMA_BASE_PTRS { DMA0 }
4028/** Interrupt vectors for the DMA peripheral type */
4029#define DMA_IRQS { DMA0_IRQn }
4030
4031/*!
4032 * @}
4033 */ /* end of group DMA_Peripheral_Access_Layer */
4034
4035
4036/* ----------------------------------------------------------------------------
4037 -- DMIC Peripheral Access Layer
4038 ---------------------------------------------------------------------------- */
4039
4040/*!
4041 * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
4042 * @{
4043 */
4044
4045/** DMIC - Register Layout Typedef */
4046typedef struct {
4047 struct { /* offset: 0x0, array step: 0x100 */
4048 __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */
4049 __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */
4050 __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */
4051 __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */
4052 __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */
4053 uint8_t RESERVED_0[108];
4054 __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */
4055 __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */
4056 __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */
4057 __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */
4058 __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */
4059 uint8_t RESERVED_1[108];
4060 } CHANNEL[2];
4061 uint8_t RESERVED_0[3328];
4062 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */
4063 uint8_t RESERVED_1[8];
4064 __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */
4065 __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */
4066 uint8_t RESERVED_2[108];
4067 __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */
4068 __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */
4069 __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */
4070 __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */
4071 __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */
4072 __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */
4073 __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */
4074 uint8_t RESERVED_3[96];
4075 __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */
4076} DMIC_Type;
4077
4078/* ----------------------------------------------------------------------------
4079 -- DMIC Register Masks
4080 ---------------------------------------------------------------------------- */
4081
4082/*!
4083 * @addtogroup DMIC_Register_Masks DMIC Register Masks
4084 * @{
4085 */
4086
4087/*! @name CHANNEL_OSR - Oversample Rate register 0 */
4088/*! @{ */
4089#define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU)
4090#define DMIC_CHANNEL_OSR_OSR_SHIFT (0U)
4091/*! OSR - Selects the oversample rate for the related input channel.
4092 */
4093#define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
4094/*! @} */
4095
4096/* The count of DMIC_CHANNEL_OSR */
4097#define DMIC_CHANNEL_OSR_COUNT (2U)
4098
4099/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */
4100/*! @{ */
4101#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU)
4102#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U)
4103/*! PDMDIV - PDM clock divider value. 0 = divide by 1 1 = divide by 2 2 = divide by 3 3 = divide by
4104 * 4 4 = divide by 6 5 = divide by 8 6 = divide by 12 7 = divide by 16 8 = divide by 24 9 =
4105 * divide by 32 10 = divide by 48 11 = divide by 64 12 = divide by 96 13 = divide by 128 others =
4106 * reserved.
4107 */
4108#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
4109/*! @} */
4110
4111/* The count of DMIC_CHANNEL_DIVHFCLK */
4112#define DMIC_CHANNEL_DIVHFCLK_COUNT (2U)
4113
4114/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */
4115/*! @{ */
4116#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U)
4117#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U)
4118/*! COMP - Pre-emphasis filer coefficient for 2 FS mode. 0 = Compensation = 0 1 = Compensation = 16
4119 * 2 = Compensation = 15 3 = Compensation = 13
4120 */
4121#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
4122/*! @} */
4123
4124/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
4125#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U)
4126
4127/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */
4128/*! @{ */
4129#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U)
4130#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U)
4131/*! COMP - Pre-emphasis filer coefficient for 4 FS mode. 0 = Compensation = 0 1 = Compensation = 16
4132 * 2 = Compensation = 15 3 = Compensation = 13
4133 */
4134#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
4135/*! @} */
4136
4137/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
4138#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U)
4139
4140/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */
4141/*! @{ */
4142#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU)
4143#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U)
4144/*! GAIN - Gain control, as a positive or negative (two's complement) number of bits to shift.
4145 */
4146#define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
4147/*! @} */
4148
4149/* The count of DMIC_CHANNEL_GAINSHIFT */
4150#define DMIC_CHANNEL_GAINSHIFT_COUNT (2U)
4151
4152/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */
4153/*! @{ */
4154#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U)
4155#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U)
4156/*! ENABLE - FIFO enable.
4157 * 0b0..FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being
4158 * streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a
4159 * period when the data was not needed.
4160 * 0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
4161 */
4162#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
4163#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U)
4164#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U)
4165/*! RESETN - FIFO reset.
4166 * 0b0..Reset the FIFO.
4167 * 0b1..Normal operation
4168 */
4169#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
4170#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U)
4171#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U)
4172/*! INTEN - Interrupt enable.
4173 * 0b0..FIFO level interrupts are not enabled.
4174 * 0b1..FIFO level interrupts are enabled.
4175 */
4176#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
4177#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U)
4178#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U)
4179/*! DMAEN - DMA enable
4180 * 0b0..DMA requests are not enabled.
4181 * 0b1..DMA requests based on FIFO level are enabled.
4182 */
4183#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
4184#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U)
4185#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U)
4186/*! TRIGLVL - FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If
4187 * enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then
4188 * return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 =
4189 * trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has
4190 * received two entries. 15 = trigger when the FIFO has received 16 entries (has become full).
4191 */
4192#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
4193/*! @} */
4194
4195/* The count of DMIC_CHANNEL_FIFO_CTRL */
4196#define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U)
4197
4198/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */
4199/*! @{ */
4200#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U)
4201#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U)
4202/*! INT - Interrupt flag. Asserted when FIFO data reaches the level specified in the FIFOCTRL
4203 * register. Writing a one to this bit clears the flag. Remark: note that the bus clock to the DMIC
4204 * subsystem must be running in order for an interrupt to occur.
4205 */
4206#define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
4207#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U)
4208#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U)
4209/*! OVERRUN - Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one
4210 * to this bit clears the flag. This flag does not cause an interrupt.
4211 */
4212#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
4213#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U)
4214#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U)
4215/*! UNDERRUN - Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag.
4216 */
4217#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
4218/*! @} */
4219
4220/* The count of DMIC_CHANNEL_FIFO_STATUS */
4221#define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U)
4222
4223/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */
4224/*! @{ */
4225#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU)
4226#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U)
4227/*! DATA - Data from the top of the input filter FIFO.
4228 */
4229#define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
4230/*! @} */
4231
4232/* The count of DMIC_CHANNEL_FIFO_DATA */
4233#define DMIC_CHANNEL_FIFO_DATA_COUNT (2U)
4234
4235/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */
4236/*! @{ */
4237#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U)
4238#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U)
4239/*! PHY_FALL - Capture PDM_DATA
4240 * 0b0..Capture PDM_DATA on the rising edge of PDM_CLK.
4241 * 0b1..Capture PDM_DATA on the falling edge of PDM_CLK.
4242 */
4243#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
4244#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U)
4245#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U)
4246/*! PHY_HALF - Half rate sampling
4247 * 0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
4248 * 0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.
4249 */
4250#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
4251/*! @} */
4252
4253/* The count of DMIC_CHANNEL_PHY_CTRL */
4254#define DMIC_CHANNEL_PHY_CTRL_COUNT (2U)
4255
4256/*! @name CHANNEL_DC_CTRL - DC Control register 0 */
4257/*! @{ */
4258#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U)
4259#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U)
4260/*! DCPOLE - DC block filter
4261 * 0b00..Flat response, no filter.
4262 * 0b01..155 Hz.
4263 * 0b10..78 Hz.
4264 * 0b11..39 Hz
4265 */
4266#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
4267#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U)
4268#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U)
4269/*! DCGAIN - Fine gain adjustment in the form of a number of bits to downshift.
4270 */
4271#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
4272#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
4273#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
4274/*! SATURATEAT16BIT - Selects 16-bit saturation.
4275 * 0b0..Results roll over if out range and do not saturate.
4276 * 0b1..If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
4277 */
4278#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
4279/*! @} */
4280
4281/* The count of DMIC_CHANNEL_DC_CTRL */
4282#define DMIC_CHANNEL_DC_CTRL_COUNT (2U)
4283
4284/*! @name CHANEN - Channel Enable register */
4285/*! @{ */
4286#define DMIC_CHANEN_EN_CH0_MASK (0x1U)
4287#define DMIC_CHANEN_EN_CH0_SHIFT (0U)
4288/*! EN_CH0 - Enable channel 0. When 1, PDM channel 0 is enabled.
4289 */
4290#define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
4291#define DMIC_CHANEN_EN_CH1_MASK (0x2U)
4292#define DMIC_CHANEN_EN_CH1_SHIFT (1U)
4293/*! EN_CH1 - Enable channel 1. When 1, PDM channel 1 is enabled.
4294 */
4295#define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
4296/*! @} */
4297
4298/*! @name IOCFG - I/O Configuration register */
4299/*! @{ */
4300#define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U)
4301#define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U)
4302/*! CLK_BYPASS0 - Bypass CLK0. When 1, PDM_DATA1 becomes the clock for PDM channel 0. This provides
4303 * for the possibility of an external codec taking over the PDM bus.
4304 */
4305#define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)
4306#define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U)
4307#define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U)
4308/*! CLK_BYPASS1 - Bypass CLK1. When 1, PDM_DATA1 becomes the clock for PDM channel 1. This provides
4309 * for the possibility of an external codec taking over the PDM bus.
4310 */
4311#define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)
4312#define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U)
4313#define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U)
4314/*! STEREO_DATA0 - Stereo PDM select. When 1, PDM_DATA0 is routed to both PDM channels in a
4315 * configuration that supports a single stereo digital microphone.
4316 */
4317#define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)
4318/*! @} */
4319
4320/*! @name USE2FS - Use 2FS register */
4321/*! @{ */
4322#define DMIC_USE2FS_USE2FS_MASK (0x1U)
4323#define DMIC_USE2FS_USE2FS_SHIFT (0U)
4324/*! USE2FS - Use 2FS register
4325 * 0b0..Use 1FS output for PCM data.
4326 * 0b1..Use 2FS output for PCM data.
4327 */
4328#define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
4329/*! @} */
4330
4331/*! @name HWVADGAIN - HWVAD input gain register */
4332/*! @{ */
4333#define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU)
4334#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U)
4335/*! INPUTGAIN - Shift value for input bits 0x00 -10 bits 0x01 -8 bits 0x02 -6 bits 0x03 -4 bits 0x04
4336 * -2 bits 0x05 0 bits (default) 0x06 +2 bits 0x07 +4 bits 0x08 +6 bits 0x09 +8 bits 0x0A +10
4337 * bits 0x0B +12 bits 0x0C +14 bits 0x0D to 0x0F Reserved.
4338 */
4339#define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
4340/*! @} */
4341
4342/*! @name HWVADHPFS - HWVAD filter control register */
4343/*! @{ */
4344#define DMIC_HWVADHPFS_HPFS_MASK (0x3U)
4345#define DMIC_HWVADHPFS_HPFS_SHIFT (0U)
4346/*! HPFS - High pass filter
4347 * 0b00..First filter by-pass.
4348 * 0b01..High pass filter with -3dB cut-off at 1750Hz.
4349 * 0b10..High pass filter with -3dB cut-off at 215Hz.
4350 * 0b11..Reserved.
4351 */
4352#define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
4353/*! @} */
4354
4355/*! @name HWVADST10 - HWVAD control register */
4356/*! @{ */
4357#define DMIC_HWVADST10_ST10_MASK (0x1U)
4358#define DMIC_HWVADST10_ST10_SHIFT (0U)
4359/*! ST10 - Stage 0
4360 * 0b0..Normal operation, waiting for HWVAD trigger event (stage 0).
4361 * 0b1..Reset internal interrupt flag by writing a '1' pulse.
4362 */
4363#define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
4364/*! @} */
4365
4366/*! @name HWVADRSTT - HWVAD filter reset register */
4367/*! @{ */
4368#define DMIC_HWVADRSTT_RSTT_MASK (0x1U)
4369#define DMIC_HWVADRSTT_RSTT_SHIFT (0U)
4370/*! RSTT - Writing a 1 resets all filter values
4371 */
4372#define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)
4373/*! @} */
4374
4375/*! @name HWVADTHGN - HWVAD noise estimator gain register */
4376/*! @{ */
4377#define DMIC_HWVADTHGN_THGN_MASK (0xFU)
4378#define DMIC_HWVADTHGN_THGN_SHIFT (0U)
4379/*! THGN - Gain value for the noise estimator. Values 0 to 14. 0 corresponds to a gain of 1.
4380 */
4381#define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
4382/*! @} */
4383
4384/*! @name HWVADTHGS - HWVAD signal estimator gain register */
4385/*! @{ */
4386#define DMIC_HWVADTHGS_THGS_MASK (0xFU)
4387#define DMIC_HWVADTHGS_THGS_SHIFT (0U)
4388/*! THGS - Gain value for the signal estimator. Values 0 to 14. 0 corresponds to a gain of 1.
4389 */
4390#define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
4391/*! @} */
4392
4393/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */
4394/*! @{ */
4395#define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU)
4396#define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U)
4397/*! LOWZ - Noise envelope estimator value.
4398 */
4399#define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
4400/*! @} */
4401
4402/*! @name ID - Module Identification register */
4403/*! @{ */
4404#define DMIC_ID_ID_MASK (0xFFFFFFFFU)
4405#define DMIC_ID_ID_SHIFT (0U)
4406/*! ID - Indicates module ID and the number of channels in this DMIC interface.
4407 */
4408#define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)
4409/*! @} */
4410
4411
4412/*!
4413 * @}
4414 */ /* end of group DMIC_Register_Masks */
4415
4416
4417/* DMIC - Peripheral instance base addresses */
4418/** Peripheral DMIC0 base address */
4419#define DMIC0_BASE (0x40090000u)
4420/** Peripheral DMIC0 base pointer */
4421#define DMIC0 ((DMIC_Type *)DMIC0_BASE)
4422/** Array initializer of DMIC peripheral base addresses */
4423#define DMIC_BASE_ADDRS { DMIC0_BASE }
4424/** Array initializer of DMIC peripheral base pointers */
4425#define DMIC_BASE_PTRS { DMIC0 }
4426/** Interrupt vectors for the DMIC peripheral type */
4427#define DMIC_IRQS { DMIC0_IRQn }
4428#define DMIC_HWVAD_IRQS { HWVAD0_IRQn }
4429
4430/*!
4431 * @}
4432 */ /* end of group DMIC_Peripheral_Access_Layer */
4433
4434
4435/* ----------------------------------------------------------------------------
4436 -- EMC Peripheral Access Layer
4437 ---------------------------------------------------------------------------- */
4438
4439/*!
4440 * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer
4441 * @{
4442 */
4443
4444/** EMC - Register Layout Typedef */
4445typedef struct {
4446 __IO uint32_t CONTROL; /**< Controls operation of the memory controller, offset: 0x0 */
4447 __I uint32_t STATUS; /**< Provides EMC status information, offset: 0x4 */
4448 __IO uint32_t CONFIG; /**< Configures operation of the memory controller, offset: 0x8 */
4449 uint8_t RESERVED_0[20];
4450 __IO uint32_t DYNAMICCONTROL; /**< Controls dynamic memory operation, offset: 0x20 */
4451 __IO uint32_t DYNAMICREFRESH; /**< Configures dynamic memory refresh, offset: 0x24 */
4452 __IO uint32_t DYNAMICREADCONFIG; /**< Configures dynamic memory read strategy, offset: 0x28 */
4453 uint8_t RESERVED_1[4];
4454 __IO uint32_t DYNAMICRP; /**< Precharge command period, offset: 0x30 */
4455 __IO uint32_t DYNAMICRAS; /**< Active to precharge command period, offset: 0x34 */
4456 __IO uint32_t DYNAMICSREX; /**< Self-refresh exit time, offset: 0x38 */
4457 __IO uint32_t DYNAMICAPR; /**< Last-data-out to active command time, offset: 0x3C */
4458 __IO uint32_t DYNAMICDAL; /**< Data-in to active command time, offset: 0x40 */
4459 __IO uint32_t DYNAMICWR; /**< Write recovery time, offset: 0x44 */
4460 __IO uint32_t DYNAMICRC; /**< Selects the active to active command period, offset: 0x48 */
4461 __IO uint32_t DYNAMICRFC; /**< Selects the auto-refresh period, offset: 0x4C */
4462 __IO uint32_t DYNAMICXSR; /**< Time for exit self-refresh to active command, offset: 0x50 */
4463 __IO uint32_t DYNAMICRRD; /**< Latency for active bank A to active bank B, offset: 0x54 */
4464 __IO uint32_t DYNAMICMRD; /**< Time for load mode register to active command, offset: 0x58 */
4465 uint8_t RESERVED_2[36];
4466 __IO uint32_t STATICEXTENDEDWAIT; /**< Time for long static memory read and write transfers, offset: 0x80 */
4467 uint8_t RESERVED_3[124];
4468 struct { /* offset: 0x100, array step: 0x20 */
4469 __IO uint32_t DYNAMICCONFIG; /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */
4470 __IO uint32_t DYNAMICRASCAS; /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */
4471 uint8_t RESERVED_0[24];
4472 } DYNAMIC[4];
4473 uint8_t RESERVED_4[128];
4474 struct { /* offset: 0x200, array step: 0x20 */
4475 __IO uint32_t STATICCONFIG; /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */
4476 __IO uint32_t STATICWAITWEN; /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */
4477 __IO uint32_t STATICWAITOEN; /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */
4478 __IO uint32_t STATICWAITRD; /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */
4479 __IO uint32_t STATICWAITPAGE; /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */
4480 __IO uint32_t STATICWAITWR; /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */
4481 __IO uint32_t STATICWAITTURN; /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */
4482 uint8_t RESERVED_0[4];
4483 } STATIC[4];
4484} EMC_Type;
4485
4486/* ----------------------------------------------------------------------------
4487 -- EMC Register Masks
4488 ---------------------------------------------------------------------------- */
4489
4490/*!
4491 * @addtogroup EMC_Register_Masks EMC Register Masks
4492 * @{
4493 */
4494
4495/*! @name CONTROL - Controls operation of the memory controller */
4496/*! @{ */
4497#define EMC_CONTROL_E_MASK (0x1U)
4498#define EMC_CONTROL_E_SHIFT (0U)
4499/*! E - EMC Enable.
4500 */
4501#define EMC_CONTROL_E(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK)
4502#define EMC_CONTROL_M_MASK (0x2U)
4503#define EMC_CONTROL_M_SHIFT (1U)
4504/*! M - Address mirror.
4505 */
4506#define EMC_CONTROL_M(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK)
4507#define EMC_CONTROL_L_MASK (0x4U)
4508#define EMC_CONTROL_L_SHIFT (2U)
4509/*! L - Low-power mode.
4510 */
4511#define EMC_CONTROL_L(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK)
4512/*! @} */
4513
4514/*! @name STATUS - Provides EMC status information */
4515/*! @{ */
4516#define EMC_STATUS_B_MASK (0x1U)
4517#define EMC_STATUS_B_SHIFT (0U)
4518/*! B - Busy.
4519 */
4520#define EMC_STATUS_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK)
4521#define EMC_STATUS_S_MASK (0x2U)
4522#define EMC_STATUS_S_SHIFT (1U)
4523/*! S - Write buffer status.
4524 */
4525#define EMC_STATUS_S(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK)
4526#define EMC_STATUS_SA_MASK (0x4U)
4527#define EMC_STATUS_SA_SHIFT (2U)
4528/*! SA - Self-refresh acknowledge.
4529 */
4530#define EMC_STATUS_SA(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK)
4531/*! @} */
4532
4533/*! @name CONFIG - Configures operation of the memory controller */
4534/*! @{ */
4535#define EMC_CONFIG_EM_MASK (0x1U)
4536#define EMC_CONFIG_EM_SHIFT (0U)
4537/*! EM - Endian mode.
4538 */
4539#define EMC_CONFIG_EM(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK)
4540#define EMC_CONFIG_CLKR_MASK (0x100U)
4541#define EMC_CONFIG_CLKR_SHIFT (8U)
4542/*! CLKR - This bit must contain 0 for proper operation of the EMC.
4543 */
4544#define EMC_CONFIG_CLKR(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK)
4545/*! @} */
4546
4547/*! @name DYNAMICCONTROL - Controls dynamic memory operation */
4548/*! @{ */
4549#define EMC_DYNAMICCONTROL_CE_MASK (0x1U)
4550#define EMC_DYNAMICCONTROL_CE_SHIFT (0U)
4551/*! CE - Dynamic memory clock enable.
4552 */
4553#define EMC_DYNAMICCONTROL_CE(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK)
4554#define EMC_DYNAMICCONTROL_CS_MASK (0x2U)
4555#define EMC_DYNAMICCONTROL_CS_SHIFT (1U)
4556/*! CS - Dynamic memory clock control.
4557 */
4558#define EMC_DYNAMICCONTROL_CS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK)
4559#define EMC_DYNAMICCONTROL_SR_MASK (0x4U)
4560#define EMC_DYNAMICCONTROL_SR_SHIFT (2U)
4561/*! SR - Self-refresh request, EMCSREFREQ.
4562 */
4563#define EMC_DYNAMICCONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK)
4564#define EMC_DYNAMICCONTROL_MMC_MASK (0x20U)
4565#define EMC_DYNAMICCONTROL_MMC_SHIFT (5U)
4566/*! MMC - Memory clock control.
4567 */
4568#define EMC_DYNAMICCONTROL_MMC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK)
4569#define EMC_DYNAMICCONTROL_I_MASK (0x180U)
4570#define EMC_DYNAMICCONTROL_I_SHIFT (7U)
4571/*! I - SDRAM initialization.
4572 */
4573#define EMC_DYNAMICCONTROL_I(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK)
4574/*! @} */
4575
4576/*! @name DYNAMICREFRESH - Configures dynamic memory refresh */
4577/*! @{ */
4578#define EMC_DYNAMICREFRESH_REFRESH_MASK (0x7FFU)
4579#define EMC_DYNAMICREFRESH_REFRESH_SHIFT (0U)
4580/*! REFRESH - Refresh timer.
4581 */
4582#define EMC_DYNAMICREFRESH_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK)
4583/*! @} */
4584
4585/*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */
4586/*! @{ */
4587#define EMC_DYNAMICREADCONFIG_RD_MASK (0x3U)
4588#define EMC_DYNAMICREADCONFIG_RD_SHIFT (0U)
4589/*! RD - Read data strategy.
4590 */
4591#define EMC_DYNAMICREADCONFIG_RD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK)
4592/*! @} */
4593
4594/*! @name DYNAMICRP - Precharge command period */
4595/*! @{ */
4596#define EMC_DYNAMICRP_TRP_MASK (0xFU)
4597#define EMC_DYNAMICRP_TRP_SHIFT (0U)
4598/*! TRP - Precharge command period.
4599 */
4600#define EMC_DYNAMICRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK)
4601/*! @} */
4602
4603/*! @name DYNAMICRAS - Active to precharge command period */
4604/*! @{ */
4605#define EMC_DYNAMICRAS_TRAS_MASK (0xFU)
4606#define EMC_DYNAMICRAS_TRAS_SHIFT (0U)
4607/*! TRAS - Active to precharge command period.
4608 */
4609#define EMC_DYNAMICRAS_TRAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK)
4610/*! @} */
4611
4612/*! @name DYNAMICSREX - Self-refresh exit time */
4613/*! @{ */
4614#define EMC_DYNAMICSREX_TSREX_MASK (0xFU)
4615#define EMC_DYNAMICSREX_TSREX_SHIFT (0U)
4616/*! TSREX - Self-refresh exit time.
4617 */
4618#define EMC_DYNAMICSREX_TSREX(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK)
4619/*! @} */
4620
4621/*! @name DYNAMICAPR - Last-data-out to active command time */
4622/*! @{ */
4623#define EMC_DYNAMICAPR_TAPR_MASK (0xFU)
4624#define EMC_DYNAMICAPR_TAPR_SHIFT (0U)
4625/*! TAPR - Last-data-out to active command time.
4626 */
4627#define EMC_DYNAMICAPR_TAPR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK)
4628/*! @} */
4629
4630/*! @name DYNAMICDAL - Data-in to active command time */
4631/*! @{ */
4632#define EMC_DYNAMICDAL_TDAL_MASK (0xFU)
4633#define EMC_DYNAMICDAL_TDAL_SHIFT (0U)
4634/*! TDAL - Data-in to active command.
4635 */
4636#define EMC_DYNAMICDAL_TDAL(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK)
4637/*! @} */
4638
4639/*! @name DYNAMICWR - Write recovery time */
4640/*! @{ */
4641#define EMC_DYNAMICWR_TWR_MASK (0xFU)
4642#define EMC_DYNAMICWR_TWR_SHIFT (0U)
4643/*! TWR - Write recovery time.
4644 */
4645#define EMC_DYNAMICWR_TWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK)
4646/*! @} */
4647
4648/*! @name DYNAMICRC - Selects the active to active command period */
4649/*! @{ */
4650#define EMC_DYNAMICRC_TRC_MASK (0x1FU)
4651#define EMC_DYNAMICRC_TRC_SHIFT (0U)
4652/*! TRC - Active to active command period.
4653 */
4654#define EMC_DYNAMICRC_TRC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK)
4655/*! @} */
4656
4657/*! @name DYNAMICRFC - Selects the auto-refresh period */
4658/*! @{ */
4659#define EMC_DYNAMICRFC_TRFC_MASK (0x1FU)
4660#define EMC_DYNAMICRFC_TRFC_SHIFT (0U)
4661/*! TRFC - Auto-refresh period and auto-refresh to active command period.
4662 */
4663#define EMC_DYNAMICRFC_TRFC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK)
4664/*! @} */
4665
4666/*! @name DYNAMICXSR - Time for exit self-refresh to active command */
4667/*! @{ */
4668#define EMC_DYNAMICXSR_TXSR_MASK (0x1FU)
4669#define EMC_DYNAMICXSR_TXSR_SHIFT (0U)
4670/*! TXSR - Exit self-refresh to active command time.
4671 */
4672#define EMC_DYNAMICXSR_TXSR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK)
4673/*! @} */
4674
4675/*! @name DYNAMICRRD - Latency for active bank A to active bank B */
4676/*! @{ */
4677#define EMC_DYNAMICRRD_TRRD_MASK (0xFU)
4678#define EMC_DYNAMICRRD_TRRD_SHIFT (0U)
4679/*! TRRD - Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles.
4680 */
4681#define EMC_DYNAMICRRD_TRRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK)
4682/*! @} */
4683
4684/*! @name DYNAMICMRD - Time for load mode register to active command */
4685/*! @{ */
4686#define EMC_DYNAMICMRD_TMRD_MASK (0xFU)
4687#define EMC_DYNAMICMRD_TMRD_SHIFT (0U)
4688/*! TMRD - Load mode register to active command time.
4689 */
4690#define EMC_DYNAMICMRD_TMRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK)
4691/*! @} */
4692
4693/*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */
4694/*! @{ */
4695#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU)
4696#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U)
4697/*! EXTENDEDWAIT - Extended wait time out.
4698 */
4699#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK)
4700/*! @} */
4701
4702/*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */
4703/*! @{ */
4704#define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK (0x18U)
4705#define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT (3U)
4706/*! MD - Memory device.
4707 */
4708#define EMC_DYNAMIC_DYNAMICCONFIG_MD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK)
4709#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK (0x1F80U)
4710#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT (7U)
4711/*! AM0 - See Table 933.
4712 */
4713#define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK)
4714#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK (0x4000U)
4715#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT (14U)
4716/*! AM1 - See Table 933.
4717 */
4718#define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
4719#define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK (0x80000U)
4720#define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT (19U)
4721/*! B - Buffer enable.
4722 */
4723#define EMC_DYNAMIC_DYNAMICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK)
4724#define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK (0x100000U)
4725#define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT (20U)
4726/*! P - Write protect.
4727 */
4728#define EMC_DYNAMIC_DYNAMICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK)
4729/*! @} */
4730
4731/* The count of EMC_DYNAMIC_DYNAMICCONFIG */
4732#define EMC_DYNAMIC_DYNAMICCONFIG_COUNT (4U)
4733
4734/*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */
4735/*! @{ */
4736#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK (0x3U)
4737#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT (0U)
4738/*! RAS - RAS latency (active to read/write delay).
4739 */
4740#define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK)
4741#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK (0x300U)
4742#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT (8U)
4743/*! CAS - CAS latency.
4744 */
4745#define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK)
4746/*! @} */
4747
4748/* The count of EMC_DYNAMIC_DYNAMICRASCAS */
4749#define EMC_DYNAMIC_DYNAMICRASCAS_COUNT (4U)
4750
4751/*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */
4752/*! @{ */
4753#define EMC_STATIC_STATICCONFIG_MW_MASK (0x3U)
4754#define EMC_STATIC_STATICCONFIG_MW_SHIFT (0U)
4755/*! MW - Memory width.
4756 */
4757#define EMC_STATIC_STATICCONFIG_MW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK)
4758#define EMC_STATIC_STATICCONFIG_PM_MASK (0x8U)
4759#define EMC_STATIC_STATICCONFIG_PM_SHIFT (3U)
4760/*! PM - Page mode.
4761 */
4762#define EMC_STATIC_STATICCONFIG_PM(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK)
4763#define EMC_STATIC_STATICCONFIG_PC_MASK (0x40U)
4764#define EMC_STATIC_STATICCONFIG_PC_SHIFT (6U)
4765/*! PC - Chip select polarity.
4766 */
4767#define EMC_STATIC_STATICCONFIG_PC(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK)
4768#define EMC_STATIC_STATICCONFIG_PB_MASK (0x80U)
4769#define EMC_STATIC_STATICCONFIG_PB_SHIFT (7U)
4770/*! PB - Byte lane state.
4771 */
4772#define EMC_STATIC_STATICCONFIG_PB(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK)
4773#define EMC_STATIC_STATICCONFIG_EW_MASK (0x100U)
4774#define EMC_STATIC_STATICCONFIG_EW_SHIFT (8U)
4775/*! EW - Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write
4776 * transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.
4777 */
4778#define EMC_STATIC_STATICCONFIG_EW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK)
4779#define EMC_STATIC_STATICCONFIG_B_MASK (0x80000U)
4780#define EMC_STATIC_STATICCONFIG_B_SHIFT (19U)
4781/*! B - Buffer enable [2].
4782 */
4783#define EMC_STATIC_STATICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK)
4784#define EMC_STATIC_STATICCONFIG_P_MASK (0x100000U)
4785#define EMC_STATIC_STATICCONFIG_P_SHIFT (20U)
4786/*! P - Write protect.
4787 */
4788#define EMC_STATIC_STATICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK)
4789/*! @} */
4790
4791/* The count of EMC_STATIC_STATICCONFIG */
4792#define EMC_STATIC_STATICCONFIG_COUNT (4U)
4793
4794/*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */
4795/*! @{ */
4796#define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK (0xFU)
4797#define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT (0U)
4798/*! WAITWEN - Wait write enable.
4799 */
4800#define EMC_STATIC_STATICWAITWEN_WAITWEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK)
4801/*! @} */
4802
4803/* The count of EMC_STATIC_STATICWAITWEN */
4804#define EMC_STATIC_STATICWAITWEN_COUNT (4U)
4805
4806/*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */
4807/*! @{ */
4808#define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK (0xFU)
4809#define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT (0U)
4810/*! WAITOEN - Wait output enable.
4811 */
4812#define EMC_STATIC_STATICWAITOEN_WAITOEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK)
4813/*! @} */
4814
4815/* The count of EMC_STATIC_STATICWAITOEN */
4816#define EMC_STATIC_STATICWAITOEN_COUNT (4U)
4817
4818/*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */
4819/*! @{ */
4820#define EMC_STATIC_STATICWAITRD_WAITRD_MASK (0x1FU)
4821#define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT (0U)
4822/*! WAITRD - .
4823 */
4824#define EMC_STATIC_STATICWAITRD_WAITRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK)
4825/*! @} */
4826
4827/* The count of EMC_STATIC_STATICWAITRD */
4828#define EMC_STATIC_STATICWAITRD_COUNT (4U)
4829
4830/*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */
4831/*! @{ */
4832#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK (0x1FU)
4833#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U)
4834/*! WAITPAGE - Asynchronous page mode read after the first read wait states.
4835 */
4836#define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK)
4837/*! @} */
4838
4839/* The count of EMC_STATIC_STATICWAITPAGE */
4840#define EMC_STATIC_STATICWAITPAGE_COUNT (4U)
4841
4842/*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */
4843/*! @{ */
4844#define EMC_STATIC_STATICWAITWR_WAITWR_MASK (0x1FU)
4845#define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT (0U)
4846/*! WAITWR - Write wait states.
4847 */
4848#define EMC_STATIC_STATICWAITWR_WAITWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK)
4849/*! @} */
4850
4851/* The count of EMC_STATIC_STATICWAITWR */
4852#define EMC_STATIC_STATICWAITWR_COUNT (4U)
4853
4854/*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */
4855/*! @{ */
4856#define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK (0xFU)
4857#define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U)
4858/*! WAITTURN - Bus turn-around cycles.
4859 */
4860#define EMC_STATIC_STATICWAITTURN_WAITTURN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK)
4861/*! @} */
4862
4863/* The count of EMC_STATIC_STATICWAITTURN */
4864#define EMC_STATIC_STATICWAITTURN_COUNT (4U)
4865
4866
4867/*!
4868 * @}
4869 */ /* end of group EMC_Register_Masks */
4870
4871
4872/* EMC - Peripheral instance base addresses */
4873/** Peripheral EMC base address */
4874#define EMC_BASE (0x40081000u)
4875/** Peripheral EMC base pointer */
4876#define EMC ((EMC_Type *)EMC_BASE)
4877/** Array initializer of EMC peripheral base addresses */
4878#define EMC_BASE_ADDRS { EMC_BASE }
4879/** Array initializer of EMC peripheral base pointers */
4880#define EMC_BASE_PTRS { EMC }
4881
4882/*!
4883 * @}
4884 */ /* end of group EMC_Peripheral_Access_Layer */
4885
4886
4887/* ----------------------------------------------------------------------------
4888 -- ENET Peripheral Access Layer
4889 ---------------------------------------------------------------------------- */
4890
4891/*!
4892 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
4893 * @{
4894 */
4895
4896/** ENET - Register Layout Typedef */
4897typedef struct {
4898 __IO uint32_t MAC_CONFIG; /**< MAC configuration register, offset: 0x0 */
4899 __IO uint32_t MAC_EXT_CONFIG; /**< , offset: 0x4 */
4900 __IO uint32_t MAC_FRAME_FILTER; /**< MAC frame filter register, offset: 0x8 */
4901 __IO uint32_t MAC_WD_TIMEROUT; /**< MAC watchdog Timeout register, offset: 0xC */
4902 uint8_t RESERVED_0[64];
4903 __IO uint32_t MAC_VLAN_TAG; /**< MAC vlan tag register, offset: 0x50 */
4904 uint8_t RESERVED_1[28];
4905 __IO uint32_t MAC_TX_FLOW_CTRL_Q[2]; /**< Transmit flow control register, array offset: 0x70, array step: 0x4 */
4906 uint8_t RESERVED_2[24];
4907 __IO uint32_t MAC_RX_FLOW_CTRL; /**< Receive flow control register, offset: 0x90 */
4908 uint8_t RESERVED_3[4];
4909 __IO uint32_t MAC_TXQ_PRIO_MAP; /**< , offset: 0x98 */
4910 uint8_t RESERVED_4[4];
4911 __IO uint32_t MAC_RXQ_CTRL[3]; /**< Receive Queue Control 0 register 0x0000, array offset: 0xA0, array step: 0x4 */
4912 uint8_t RESERVED_5[4];
4913 __I uint32_t MAC_INTR_STAT; /**< Interrupt status register 0x0000, offset: 0xB0 */
4914 __IO uint32_t MAC_INTR_EN; /**< Interrupt enable register 0x0000, offset: 0xB4 */
4915 __I uint32_t MAC_RXTX_STAT; /**< Receive Transmit Status register, offset: 0xB8 */
4916 uint8_t RESERVED_6[4];
4917 __IO uint32_t MAC_PMT_CRTL_STAT; /**< , offset: 0xC0 */
4918 __IO uint32_t MAC_RWAKE_FRFLT; /**< Remote wake-up frame filter, offset: 0xC4 */
4919 uint8_t RESERVED_7[8];
4920 __IO uint32_t MAC_LPI_CTRL_STAT; /**< LPI Control and Status Register, offset: 0xD0 */
4921 __IO uint32_t MAC_LPI_TIMER_CTRL; /**< LPI Timers Control register, offset: 0xD4 */
4922 __IO uint32_t MAC_LPI_ENTR_TIMR; /**< LPI entry Timer register, offset: 0xD8 */
4923 __IO uint32_t MAC_1US_TIC_COUNTR; /**< , offset: 0xDC */
4924 uint8_t RESERVED_8[48];
4925 __I uint32_t MAC_VERSION; /**< MAC version register, offset: 0x110 */
4926 __I uint32_t MAC_DBG; /**< MAC debug register, offset: 0x114 */
4927 uint8_t RESERVED_9[4];
4928 __I uint32_t MAC_HW_FEAT[3]; /**< MAC hardware feature register 0x0201, array offset: 0x11C, array step: 0x4 */
4929 uint8_t RESERVED_10[216];
4930 __IO uint32_t MAC_MDIO_ADDR; /**< MIDO address Register, offset: 0x200 */
4931 __IO uint32_t MAC_MDIO_DATA; /**< MDIO Data register, offset: 0x204 */
4932 uint8_t RESERVED_11[248];
4933 __IO uint32_t MAC_ADDR_HIGH; /**< MAC address0 high register, offset: 0x300 */
4934 __IO uint32_t MAC_ADDR_LOW; /**< MAC address0 low register, offset: 0x304 */
4935 uint8_t RESERVED_12[2040];
4936 __IO uint32_t MAC_TIMESTAMP_CTRL; /**< Time stamp control register, offset: 0xB00 */
4937 __IO uint32_t MAC_SUB_SCND_INCR; /**< Sub-second increment register, offset: 0xB04 */
4938 __I uint32_t MAC_SYS_TIME_SCND; /**< System time seconds register, offset: 0xB08 */
4939 __I uint32_t MAC_SYS_TIME_NSCND; /**< System time nanoseconds register, offset: 0xB0C */
4940 __IO uint32_t MAC_SYS_TIME_SCND_UPD; /**< , offset: 0xB10 */
4941 __IO uint32_t MAC_SYS_TIME_NSCND_UPD; /**< , offset: 0xB14 */
4942 __IO uint32_t MAC_SYS_TIMESTMP_ADDEND; /**< Time stamp addend register, offset: 0xB18 */
4943 __IO uint32_t MAC_SYS_TIME_HWORD_SCND; /**< , offset: 0xB1C */
4944 __I uint32_t MAC_SYS_TIMESTMP_STAT; /**< Time stamp status register, offset: 0xB20 */
4945 uint8_t RESERVED_13[12];
4946 __I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Tx timestamp status nanoseconds, offset: 0xB30 */
4947 __I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< Tx timestamp status seconds, offset: 0xB34 */
4948 uint8_t RESERVED_14[32];
4949 __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp ingress correction, offset: 0xB58 */
4950 __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp egress correction, offset: 0xB5C */
4951 uint8_t RESERVED_15[160];
4952 __IO uint32_t MTL_OP_MODE; /**< MTL Operation Mode Register, offset: 0xC00 */
4953 uint8_t RESERVED_16[28];
4954 __I uint32_t MTL_INTR_STAT; /**< MTL Interrupt Status register, offset: 0xC20 */
4955 uint8_t RESERVED_17[12];
4956 __IO uint32_t MTL_RXQ_DMA_MAP; /**< MTL Receive Queue and DMA Channel Mapping register, offset: 0xC30 */
4957 uint8_t RESERVED_18[204];
4958 struct { /* offset: 0xD00, array step: 0x40 */
4959 __IO uint32_t MTL_TXQX_OP_MODE; /**< MTL TxQx Operation Mode register, array offset: 0xD00, array step: 0x40 */
4960 __I uint32_t MTL_TXQX_UNDRFLW; /**< MTL TxQx Underflow register, array offset: 0xD04, array step: 0x40 */
4961 __I uint32_t MTL_TXQX_DBG; /**< MTL TxQx Debug register, array offset: 0xD08, array step: 0x40 */
4962 uint8_t RESERVED_0[4];
4963 __IO uint32_t MTL_TXQX_ETS_CTRL; /**< MTL TxQx ETS control register, only TxQ1 support, array offset: 0xD10, array step: 0x40 */
4964 __I uint32_t MTL_TXQX_ETS_STAT; /**< MTL TxQx ETS Status register, array offset: 0xD14, array step: 0x40 */
4965 __IO uint32_t MTL_TXQX_QNTM_WGHT; /**< , array offset: 0xD18, array step: 0x40 */
4966 __IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< MTL TxQx SendSlopCredit register, only TxQ1 support, array offset: 0xD1C, array step: 0x40 */
4967 __IO uint32_t MTL_TXQX_HI_CRDT; /**< MTL TxQx hiCredit register, only TxQ1 support, array offset: 0xD20, array step: 0x40 */
4968 __IO uint32_t MTL_TXQX_LO_CRDT; /**< MTL TxQx loCredit register, only TxQ1 support, array offset: 0xD24, array step: 0x40 */
4969 uint8_t RESERVED_1[4];
4970 __IO uint32_t MTL_TXQX_INTCTRL_STAT; /**< , array offset: 0xD2C, array step: 0x40 */
4971 __IO uint32_t MTL_RXQX_OP_MODE; /**< MTL RxQx Operation Mode register, array offset: 0xD30, array step: 0x40 */
4972 __I uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< MTL RxQx Missed Packet Overflow Counter register, array offset: 0xD34, array step: 0x40 */
4973 __I uint32_t MTL_RXQX_DBG; /**< MTL RxQx Debug register, array offset: 0xD38, array step: 0x40 */
4974 __IO uint32_t MTL_RXQX_CTRL; /**< MTL RxQx Control register, array offset: 0xD3C, array step: 0x40 */
4975 } MTL_QUEUE[2];
4976 uint8_t RESERVED_19[640];
4977 __IO uint32_t DMA_MODE; /**< DMA mode register, offset: 0x1000 */
4978 __IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus mode, offset: 0x1004 */
4979 __IO uint32_t DMA_INTR_STAT; /**< DMA Interrupt status, offset: 0x1008 */
4980 __I uint32_t DMA_DBG_STAT; /**< DMA Debug Status, offset: 0x100C */
4981 uint8_t RESERVED_20[240];
4982 struct { /* offset: 0x1100, array step: 0x80 */
4983 __IO uint32_t DMA_CHX_CTRL; /**< DMA Channelx Control, array offset: 0x1100, array step: 0x80 */
4984 __IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channelx Transmit Control, array offset: 0x1104, array step: 0x80 */
4985 __IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channelx Receive Control, array offset: 0x1108, array step: 0x80 */
4986 uint8_t RESERVED_0[8];
4987 __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< , array offset: 0x1114, array step: 0x80 */
4988 uint8_t RESERVED_1[4];
4989 __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< , array offset: 0x111C, array step: 0x80 */
4990 __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< , array offset: 0x1120, array step: 0x80 */
4991 uint8_t RESERVED_2[4];
4992 __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< , array offset: 0x1128, array step: 0x80 */
4993 __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< , array offset: 0x112C, array step: 0x80 */
4994 __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH; /**< Channelx Rx descriptor Ring Length, array offset: 0x1130, array step: 0x80 */
4995 __IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1134, array step: 0x80 */
4996 __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
4997 __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
4998 uint8_t RESERVED_3[4];
4999 __I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< Channelx Current Host Transmit descriptor, array offset: 0x1144, array step: 0x80 */
5000 uint8_t RESERVED_4[4];
5001 __I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< , array offset: 0x114C, array step: 0x80 */
5002 uint8_t RESERVED_5[4];
5003 __I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< , array offset: 0x1154, array step: 0x80 */
5004 uint8_t RESERVED_6[4];
5005 __I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< Channelx Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
5006 __IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: 0x1160, array step: 0x80 */
5007 uint8_t RESERVED_7[8];
5008 __IO uint32_t DMA_CHX_MISS_FRAME_CNT; /**< Channelx missed frame count., array offset: 0x116C, array step: 0x80 */
5009 uint8_t RESERVED_8[16];
5010 } DMA_CH[2];
5011} ENET_Type;
5012
5013/* ----------------------------------------------------------------------------
5014 -- ENET Register Masks
5015 ---------------------------------------------------------------------------- */
5016
5017/*!
5018 * @addtogroup ENET_Register_Masks ENET Register Masks
5019 * @{
5020 */
5021
5022/*! @name MAC_CONFIG - MAC configuration register */
5023/*! @{ */
5024#define ENET_MAC_CONFIG_RE_MASK (0x1U)
5025#define ENET_MAC_CONFIG_RE_SHIFT (0U)
5026/*! RE - Receiver Enable When this bit is set, the receiver state machine of the MAC is enabled for
5027 * receiving frames from the MII.
5028 */
5029#define ENET_MAC_CONFIG_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_RE_SHIFT)) & ENET_MAC_CONFIG_RE_MASK)
5030#define ENET_MAC_CONFIG_TE_MASK (0x2U)
5031#define ENET_MAC_CONFIG_TE_SHIFT (1U)
5032/*! TE - Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII.
5033 */
5034#define ENET_MAC_CONFIG_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_TE_SHIFT)) & ENET_MAC_CONFIG_TE_MASK)
5035#define ENET_MAC_CONFIG_PRELEN_MASK (0xCU)
5036#define ENET_MAC_CONFIG_PRELEN_SHIFT (2U)
5037/*! PRELEN - Preamble Length for Transmit packets These bits control the number of preamble bytes
5038 * that are added to the beginning of every Tx packet.
5039 */
5040#define ENET_MAC_CONFIG_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PRELEN_SHIFT)) & ENET_MAC_CONFIG_PRELEN_MASK)
5041#define ENET_MAC_CONFIG_DC_MASK (0x10U)
5042#define ENET_MAC_CONFIG_DC_SHIFT (4U)
5043/*! DC - Deferral Check When this bit is set, the deferral check function is enabled in the MAC.
5044 */
5045#define ENET_MAC_CONFIG_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DC_SHIFT)) & ENET_MAC_CONFIG_DC_MASK)
5046#define ENET_MAC_CONFIG_BL_MASK (0x60U)
5047#define ENET_MAC_CONFIG_BL_SHIFT (5U)
5048/*! BL - Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time
5049 * delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before
5050 * rescheduling a transmission attempt during retries after a collision.
5051 */
5052#define ENET_MAC_CONFIG_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BL_SHIFT)) & ENET_MAC_CONFIG_BL_MASK)
5053#define ENET_MAC_CONFIG_DR_MASK (0x100U)
5054#define ENET_MAC_CONFIG_DR_SHIFT (8U)
5055/*! DR - Disable Retry When this bit is set, the MAC will attempt only one transmission.
5056 */
5057#define ENET_MAC_CONFIG_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DR_SHIFT)) & ENET_MAC_CONFIG_DR_MASK)
5058#define ENET_MAC_CONFIG_DCRS_MASK (0x200U)
5059#define ENET_MAC_CONFIG_DCRS_SHIFT (9U)
5060/*! DCRS - Disable Carrier Sense During Transmission When this bit is set, the MAC transmitter
5061 * ignores the MII CRS signal during packet transmission in the half-duplex mode.
5062 */
5063#define ENET_MAC_CONFIG_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DCRS_SHIFT)) & ENET_MAC_CONFIG_DCRS_MASK)
5064#define ENET_MAC_CONFIG_DO_MASK (0x400U)
5065#define ENET_MAC_CONFIG_DO_SHIFT (10U)
5066/*! DO - Disable Receive Own When this bit is set, the MAC disables the reception of frames when the
5067 * gmii_txen_o is asserted in Half-Duplex mode.
5068 */
5069#define ENET_MAC_CONFIG_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DO_SHIFT)) & ENET_MAC_CONFIG_DO_MASK)
5070#define ENET_MAC_CONFIG_ECRSFD_MASK (0x800U)
5071#define ENET_MAC_CONFIG_ECRSFD_SHIFT (11U)
5072/*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set, the
5073 * MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode.
5074 */
5075#define ENET_MAC_CONFIG_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ECRSFD_SHIFT)) & ENET_MAC_CONFIG_ECRSFD_MASK)
5076#define ENET_MAC_CONFIG_LM_MASK (0x1000U)
5077#define ENET_MAC_CONFIG_LM_SHIFT (12U)
5078/*! LM - Loopback Mode When this bit is set, the MAC operates in loopback mode at MII.
5079 */
5080#define ENET_MAC_CONFIG_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_LM_SHIFT)) & ENET_MAC_CONFIG_LM_MASK)
5081#define ENET_MAC_CONFIG_DM_MASK (0x2000U)
5082#define ENET_MAC_CONFIG_DM_SHIFT (13U)
5083/*! DM - Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can
5084 * transmit and receive simultaneously.
5085 */
5086#define ENET_MAC_CONFIG_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DM_SHIFT)) & ENET_MAC_CONFIG_DM_MASK)
5087#define ENET_MAC_CONFIG_FES_MASK (0x4000U)
5088#define ENET_MAC_CONFIG_FES_SHIFT (14U)
5089/*! FES - Speed Indicates the speed in Fast Ethernet (MII) mode: This bit is reserved (RO) by
5090 * default and is enabled only when RMII/SMII is enabled during configuration.
5091 */
5092#define ENET_MAC_CONFIG_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_FES_SHIFT)) & ENET_MAC_CONFIG_FES_MASK)
5093#define ENET_MAC_CONFIG_PS_MASK (0x8000U)
5094#define ENET_MAC_CONFIG_PS_SHIFT (15U)
5095/*! PS - Portselect.
5096 */
5097#define ENET_MAC_CONFIG_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PS_SHIFT)) & ENET_MAC_CONFIG_PS_MASK)
5098#define ENET_MAC_CONFIG_JE_MASK (0x10000U)
5099#define ENET_MAC_CONFIG_JE_SHIFT (16U)
5100/*! JE - Jumbo Frame Enable When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022
5101 * bytes for tagged frames) without reporting a giant frame error in the receive frame status.
5102 */
5103#define ENET_MAC_CONFIG_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JE_SHIFT)) & ENET_MAC_CONFIG_JE_MASK)
5104#define ENET_MAC_CONFIG_JD_MASK (0x20000U)
5105#define ENET_MAC_CONFIG_JD_SHIFT (17U)
5106/*! JD - Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter,
5107 * and can transfer frames of up to 16,384 bytes.
5108 */
5109#define ENET_MAC_CONFIG_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JD_SHIFT)) & ENET_MAC_CONFIG_JD_MASK)
5110#define ENET_MAC_CONFIG_BE_MASK (0x40000U)
5111#define ENET_MAC_CONFIG_BE_SHIFT (18U)
5112/*! BE - Packet Burst Enable When this bit is set, the MAC allows packet bursting during
5113 * transmission in the MII half-duplex mode.
5114 */
5115#define ENET_MAC_CONFIG_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BE_SHIFT)) & ENET_MAC_CONFIG_BE_MASK)
5116#define ENET_MAC_CONFIG_WD_MASK (0x80000U)
5117#define ENET_MAC_CONFIG_WD_SHIFT (19U)
5118/*! WD - Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver,
5119 * and can receive frames of up to 16,384 bytes.
5120 */
5121#define ENET_MAC_CONFIG_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_WD_SHIFT)) & ENET_MAC_CONFIG_WD_MASK)
5122#define ENET_MAC_CONFIG_ACS_MASK (0x100000U)
5123#define ENET_MAC_CONFIG_ACS_SHIFT (20U)
5124/*! ACS - Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field
5125 * on the incoming packets only if the value of the length field is less than 1,536 bytes.
5126 */
5127#define ENET_MAC_CONFIG_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ACS_SHIFT)) & ENET_MAC_CONFIG_ACS_MASK)
5128#define ENET_MAC_CONFIG_CST_MASK (0x200000U)
5129#define ENET_MAC_CONFIG_CST_SHIFT (21U)
5130/*! CST - CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all
5131 * packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding
5132 * the packet to the application.
5133 */
5134#define ENET_MAC_CONFIG_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_CST_SHIFT)) & ENET_MAC_CONFIG_CST_MASK)
5135#define ENET_MAC_CONFIG_S2KP_MASK (0x400000U)
5136#define ENET_MAC_CONFIG_S2KP_SHIFT (22U)
5137/*! S2KP - IEEE 802.
5138 */
5139#define ENET_MAC_CONFIG_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_S2KP_SHIFT)) & ENET_MAC_CONFIG_S2KP_MASK)
5140#define ENET_MAC_CONFIG_GPSLCE_MASK (0x800000U)
5141#define ENET_MAC_CONFIG_GPSLCE_SHIFT (23U)
5142/*! GPSLCE - Giant Packet Size Limit Control Enable When this bit is set, the MAC considers the
5143 * value in GPSL field in MAC Ext Configuration register to declare a received packet as Giant packet.
5144 */
5145#define ENET_MAC_CONFIG_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_GPSLCE_SHIFT)) & ENET_MAC_CONFIG_GPSLCE_MASK)
5146#define ENET_MAC_CONFIG_IPG_MASK (0x7000000U)
5147#define ENET_MAC_CONFIG_IPG_SHIFT (24U)
5148/*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission.
5149 */
5150#define ENET_MAC_CONFIG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPG_SHIFT)) & ENET_MAC_CONFIG_IPG_MASK)
5151#define ENET_MAC_CONFIG_IPC_MASK (0x8000000U)
5152#define ENET_MAC_CONFIG_IPC_SHIFT (27U)
5153/*! IPC - Checksum Offload When set, this bit enables the IPv4 header checksum checking and IPv4 or
5154 * IPv6 TCP, UDP, or ICMP payload checksum checking.
5155 */
5156#define ENET_MAC_CONFIG_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPC_SHIFT)) & ENET_MAC_CONFIG_IPC_MASK)
5157/*! @} */
5158
5159/*! @name MAC_EXT_CONFIG - */
5160/*! @{ */
5161#define ENET_MAC_EXT_CONFIG_GPSL_MASK (0x3FFFU)
5162#define ENET_MAC_EXT_CONFIG_GPSL_SHIFT (0U)
5163/*! GPSL - Giant Packet Size Limit If the received packet size is greater than the value programmed
5164 * in this field in units of bytes, the MAC declares the received packet as Giant packet.
5165 */
5166#define ENET_MAC_EXT_CONFIG_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIG_GPSL_MASK)
5167#define ENET_MAC_EXT_CONFIG_DCRCC_MASK (0x10000U)
5168#define ENET_MAC_EXT_CONFIG_DCRCC_SHIFT (16U)
5169/*! DCRCC - Disable CRC Checking for Received Packets When this bit is set, the MAC receiver does
5170 * not check the CRC field in the received packets.
5171 */
5172#define ENET_MAC_EXT_CONFIG_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIG_DCRCC_MASK)
5173#define ENET_MAC_EXT_CONFIG_SPEN_MASK (0x20000U)
5174#define ENET_MAC_EXT_CONFIG_SPEN_SHIFT (17U)
5175/*! SPEN - Slow Protocol Detection Enable When this bit is set, MAC processes the Slow Protocol
5176 * packets (Ether Type 0x8809) and provides the Rx status.
5177 */
5178#define ENET_MAC_EXT_CONFIG_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIG_SPEN_MASK)
5179#define ENET_MAC_EXT_CONFIG_USP_MASK (0x40000U)
5180#define ENET_MAC_EXT_CONFIG_USP_SHIFT (18U)
5181/*! USP - Unicast Slow Protocol Packet Detect When this bit is set, the MAC detects the Slow
5182 * Protocol packets with unicast address of the station specified in the MAC Address High Table 747 and
5183 * MAC Address Low Table 748 registers.
5184 */
5185#define ENET_MAC_EXT_CONFIG_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_USP_SHIFT)) & ENET_MAC_EXT_CONFIG_USP_MASK)
5186/*! @} */
5187
5188/*! @name MAC_FRAME_FILTER - MAC frame filter register */
5189/*! @{ */
5190#define ENET_MAC_FRAME_FILTER_PR_MASK (0x1U)
5191#define ENET_MAC_FRAME_FILTER_PR_SHIFT (0U)
5192/*! PR - Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frames
5193 * regardless of its destination or source address.
5194 */
5195#define ENET_MAC_FRAME_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PR_SHIFT)) & ENET_MAC_FRAME_FILTER_PR_MASK)
5196#define ENET_MAC_FRAME_FILTER_DAIF_MASK (0x8U)
5197#define ENET_MAC_FRAME_FILTER_DAIF_SHIFT (3U)
5198/*! DAIF - DA Inverse Filtering When this bit is set, the Address Check block operates in inverse
5199 * filtering mode for the DA address comparison for both unicast and multicast frames.
5200 */
5201#define ENET_MAC_FRAME_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_DAIF_MASK)
5202#define ENET_MAC_FRAME_FILTER_PM_MASK (0x10U)
5203#define ENET_MAC_FRAME_FILTER_PM_SHIFT (4U)
5204/*! PM - Pass All Multicast When set, this bit indicates that all received frames with a multicast
5205 * destination address (first bit in the destination address field is '1') are passed.
5206 */
5207#define ENET_MAC_FRAME_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PM_SHIFT)) & ENET_MAC_FRAME_FILTER_PM_MASK)
5208#define ENET_MAC_FRAME_FILTER_DBF_MASK (0x20U)
5209#define ENET_MAC_FRAME_FILTER_DBF_SHIFT (5U)
5210/*! DBF - Disable Broadcast Frames When this bit is set, the AFM module filters all incoming broadcast frames.
5211 */
5212#define ENET_MAC_FRAME_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DBF_SHIFT)) & ENET_MAC_FRAME_FILTER_DBF_MASK)
5213#define ENET_MAC_FRAME_FILTER_PCF_MASK (0xC0U)
5214#define ENET_MAC_FRAME_FILTER_PCF_SHIFT (6U)
5215/*! PCF - Pass Control Frames These bits control the forwarding of all control frames (including
5216 * unicast and multicast PAUSE frames).
5217 */
5218#define ENET_MAC_FRAME_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PCF_SHIFT)) & ENET_MAC_FRAME_FILTER_PCF_MASK)
5219#define ENET_MAC_FRAME_FILTER_SAIF_MASK (0x100U)
5220#define ENET_MAC_FRAME_FILTER_SAIF_SHIFT (8U)
5221/*! SAIF - SA Inverse Filtering When this bit is set, the Address Check block operates in the
5222 * inverse filtering mode for SA address comparison.
5223 */
5224#define ENET_MAC_FRAME_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAIF_MASK)
5225#define ENET_MAC_FRAME_FILTER_SAF_MASK (0x200U)
5226#define ENET_MAC_FRAME_FILTER_SAF_SHIFT (9U)
5227/*! SAF - Source Address Filter Enable When this bit is set, the MAC compares the SA field of the
5228 * received packets with the values programmed in the enabled SA registers.
5229 */
5230#define ENET_MAC_FRAME_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAF_MASK)
5231#define ENET_MAC_FRAME_FILTER_RA_MASK (0x80000000U)
5232#define ENET_MAC_FRAME_FILTER_RA_SHIFT (31U)
5233/*! RA - Receive all When this bit is set, the MAC Receiver module passes to the Application all
5234 * frames received irrespective of whether they pass the address filter.
5235 */
5236#define ENET_MAC_FRAME_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_RA_SHIFT)) & ENET_MAC_FRAME_FILTER_RA_MASK)
5237/*! @} */
5238
5239/*! @name MAC_WD_TIMEROUT - MAC watchdog Timeout register */
5240/*! @{ */
5241#define ENET_MAC_WD_TIMEROUT_WTO_MASK (0xFU)
5242#define ENET_MAC_WD_TIMEROUT_WTO_SHIFT (0U)
5243/*! WTO - Watchdog Timeout When the PWE bit is set and the WD bit of the MAC Configuration register
5244 * Table 722 is reset, this field is used as watchdog timeout for a received packet.
5245 */
5246#define ENET_MAC_WD_TIMEROUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_WTO_SHIFT)) & ENET_MAC_WD_TIMEROUT_WTO_MASK)
5247#define ENET_MAC_WD_TIMEROUT_PWE_MASK (0x100U)
5248#define ENET_MAC_WD_TIMEROUT_PWE_SHIFT (8U)
5249/*! PWE - Programmable Watchdog Enable When this bit is set and the WD bit of the MAC Configuration
5250 * register Table 722 is reset, the WTO field is used as watchdog timeout for a received packet.
5251 */
5252#define ENET_MAC_WD_TIMEROUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_PWE_SHIFT)) & ENET_MAC_WD_TIMEROUT_PWE_MASK)
5253/*! @} */
5254
5255/*! @name MAC_VLAN_TAG - MAC vlan tag register */
5256/*! @{ */
5257#define ENET_MAC_VLAN_TAG_VL_MASK (0xFFFFU)
5258#define ENET_MAC_VLAN_TAG_VL_SHIFT (0U)
5259/*! VL - VLAN Tag Identifier for Receive Packets.
5260 */
5261#define ENET_MAC_VLAN_TAG_VL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VL_SHIFT)) & ENET_MAC_VLAN_TAG_VL_MASK)
5262#define ENET_MAC_VLAN_TAG_ETV_MASK (0x10000U)
5263#define ENET_MAC_VLAN_TAG_ETV_SHIFT (16U)
5264/*! ETV - Enable 12-Bit VLAN Tag Comparison.
5265 */
5266#define ENET_MAC_VLAN_TAG_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_ETV_MASK)
5267#define ENET_MAC_VLAN_TAG_VTIM_MASK (0x20000U)
5268#define ENET_MAC_VLAN_TAG_VTIM_SHIFT (17U)
5269/*! VTIM - VLAN Tag Inverse Match Enable.
5270 */
5271#define ENET_MAC_VLAN_TAG_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_VTIM_MASK)
5272#define ENET_MAC_VLAN_TAG_ESVL_MASK (0x40000U)
5273#define ENET_MAC_VLAN_TAG_ESVL_SHIFT (18U)
5274/*! ESVL - Enable S-VLAN.
5275 */
5276#define ENET_MAC_VLAN_TAG_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_ESVL_MASK)
5277#define ENET_MAC_VLAN_TAG_ERSVLM_MASK (0x80000U)
5278#define ENET_MAC_VLAN_TAG_ERSVLM_SHIFT (19U)
5279/*! ERSVLM - Enable Receive S-VLAN Match.
5280 */
5281#define ENET_MAC_VLAN_TAG_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_ERSVLM_MASK)
5282#define ENET_MAC_VLAN_TAG_DOVLTC_MASK (0x100000U)
5283#define ENET_MAC_VLAN_TAG_DOVLTC_SHIFT (20U)
5284/*! DOVLTC - Disable VLAN Type Check.
5285 */
5286#define ENET_MAC_VLAN_TAG_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_DOVLTC_MASK)
5287#define ENET_MAC_VLAN_TAG_EVLS_MASK (0x600000U)
5288#define ENET_MAC_VLAN_TAG_EVLS_SHIFT (21U)
5289/*! EVLS - Enable VLAN Tag Stripping on Receive.
5290 */
5291#define ENET_MAC_VLAN_TAG_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLS_MASK)
5292#define ENET_MAC_VLAN_TAG_EVLRXS_MASK (0x1000000U)
5293#define ENET_MAC_VLAN_TAG_EVLRXS_SHIFT (24U)
5294/*! EVLRXS - Enable VLAN Tag in Rx status.
5295 */
5296#define ENET_MAC_VLAN_TAG_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLRXS_MASK)
5297#define ENET_MAC_VLAN_TAG_VTHM_MASK (0x2000000U)
5298#define ENET_MAC_VLAN_TAG_VTHM_SHIFT (25U)
5299/*! VTHM - Disable VLAN Type Check.
5300 */
5301#define ENET_MAC_VLAN_TAG_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTHM_SHIFT)) & ENET_MAC_VLAN_TAG_VTHM_MASK)
5302#define ENET_MAC_VLAN_TAG_EDVLP_MASK (0x4000000U)
5303#define ENET_MAC_VLAN_TAG_EDVLP_SHIFT (26U)
5304/*! EDVLP - Enable Double VLAN Processing.
5305 */
5306#define ENET_MAC_VLAN_TAG_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_EDVLP_MASK)
5307#define ENET_MAC_VLAN_TAG_ERIVLT_MASK (0x8000000U)
5308#define ENET_MAC_VLAN_TAG_ERIVLT_SHIFT (27U)
5309/*! ERIVLT - Enable Inner VLAN Tag.
5310 */
5311#define ENET_MAC_VLAN_TAG_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_ERIVLT_MASK)
5312#define ENET_MAC_VLAN_TAG_EIVLS_MASK (0x30000000U)
5313#define ENET_MAC_VLAN_TAG_EIVLS_SHIFT (28U)
5314/*! EIVLS - Enable Inner VLAN Tag Stripping on Receive.
5315 */
5316#define ENET_MAC_VLAN_TAG_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLS_MASK)
5317#define ENET_MAC_VLAN_TAG_EIVLRXS_MASK (0x80000000U)
5318#define ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT (31U)
5319/*! EIVLRXS - Enable Inner VLAN Tag in Rx Status.
5320 */
5321#define ENET_MAC_VLAN_TAG_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLRXS_MASK)
5322/*! @} */
5323
5324/*! @name MAC_TX_FLOW_CTRL_Q - Transmit flow control register */
5325/*! @{ */
5326#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK (0x1U)
5327#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT (0U)
5328/*! FCB - Flow Control Busy/Backpressure Activate This register field can be read by the application
5329 * (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is
5330 * cleared to 0 by the core (Self Clear).
5331 */
5332#define ENET_MAC_TX_FLOW_CTRL_Q_FCB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK)
5333#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U)
5334#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U)
5335/*! TFE - Transmit Flow Control Enable In Full-Duplex mode, when this bit is set, the MAC enables
5336 * the flow control operation to transmit Pause frames.
5337 */
5338#define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
5339#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U)
5340#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U)
5341/*! PLT - Pause Low Threshold This field configures the threshold of the PAUSE timer at which the
5342 * input flow control signal is checked for automatic retransmission of PAUSE Frame.
5343 */
5344#define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
5345#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U)
5346#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U)
5347/*! DZPQ - Disable Zero-Quanta Pause When set, this bit disables the automatic generation of
5348 * Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer.
5349 */
5350#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
5351#define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U)
5352#define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U)
5353/*! PT - Pause time This field holds the value to be used in the Pause Time field in the transmit control frame.
5354 */
5355#define ENET_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK)
5356/*! @} */
5357
5358/* The count of ENET_MAC_TX_FLOW_CTRL_Q */
5359#define ENET_MAC_TX_FLOW_CTRL_Q_COUNT (2U)
5360
5361/*! @name MAC_RX_FLOW_CTRL - Receive flow control register */
5362/*! @{ */
5363#define ENET_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U)
5364#define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U)
5365/*! RFE - Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex
5366 * mode, the MAC decodes the received Pause packet and disables its transmitter for a specified
5367 * (Pause) time.
5368 */
5369#define ENET_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK)
5370#define ENET_MAC_RX_FLOW_CTRL_UP_MASK (0x2U)
5371#define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT (1U)
5372/*! UP - Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast
5373 * address specified in the IEEE 802.
5374 */
5375#define ENET_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK)
5376/*! @} */
5377
5378/*! @name MAC_TXQ_PRIO_MAP - */
5379/*! @{ */
5380#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK (0xFFU)
5381#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT (0U)
5382/*! PSTQ0 - Priorities Selected in Transmit Queue 0 This field holds the priorities assigned to Tx Queue 0 by the software.
5383 */
5384#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK)
5385#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK (0xFF00U)
5386#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT (8U)
5387/*! PSTQ1 - Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit.
5388 */
5389#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK)
5390/*! @} */
5391
5392/*! @name MAC_RXQ_CTRL - Receive Queue Control 0 register 0x0000 */
5393/*! @{ */
5394#define ENET_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U)
5395#define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U)
5396/*! AVCPQ - AV Untagged Control Packets Queue.
5397 */
5398#define ENET_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK)
5399#define ENET_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU)
5400#define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U)
5401/*! PSRQ0 - Priorities Selected in the Receive Queue 0.
5402 */
5403#define ENET_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK)
5404#define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U)
5405#define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U)
5406/*! RXQ0EN - Receive Queue 0 Enable.
5407 */
5408#define ENET_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK)
5409#define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU)
5410#define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U)
5411/*! RXQ1EN - Receive Queue 1 Enable.
5412 */
5413#define ENET_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK)
5414#define ENET_MAC_RXQ_CTRL_AVPTPQ_MASK (0x70U)
5415#define ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT (4U)
5416/*! AVPTPQ - AV PTP Packets Queue.
5417 */
5418#define ENET_MAC_RXQ_CTRL_AVPTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVPTPQ_MASK)
5419#define ENET_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U)
5420#define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U)
5421/*! PSRQ1 - Priorities Selected in the Receive Queue 1.
5422 */
5423#define ENET_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK)
5424#define ENET_MAC_RXQ_CTRL_UPQ_MASK (0x7000U)
5425#define ENET_MAC_RXQ_CTRL_UPQ_SHIFT (12U)
5426/*! UPQ - Untagged Packet Queue.
5427 */
5428#define ENET_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK)
5429#define ENET_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U)
5430#define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U)
5431/*! MCBCQ - Multicast and Broadcast Queue.
5432 */
5433#define ENET_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK)
5434#define ENET_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U)
5435#define ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U)
5436/*! PSRQ2 - Priorities Selected in the Receive Queue 2.
5437 */
5438#define ENET_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ2_MASK)
5439#define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U)
5440#define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U)
5441/*! MCBCQEN - Multicast and Broadcast Queue Enable.
5442 */
5443#define ENET_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK)
5444#define ENET_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U)
5445#define ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U)
5446/*! PSRQ3 - Priorities Selected in the Receive Queue 3.
5447 */
5448#define ENET_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ3_MASK)
5449/*! @} */
5450
5451/* The count of ENET_MAC_RXQ_CTRL */
5452#define ENET_MAC_RXQ_CTRL_COUNT (3U)
5453
5454/*! @name MAC_INTR_STAT - Interrupt status register 0x0000 */
5455/*! @{ */
5456#define ENET_MAC_INTR_STAT_PHYIS_MASK (0x8U)
5457#define ENET_MAC_INTR_STAT_PHYIS_SHIFT (3U)
5458/*! PHYIS - PHY Interrupt.
5459 */
5460#define ENET_MAC_INTR_STAT_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PHYIS_SHIFT)) & ENET_MAC_INTR_STAT_PHYIS_MASK)
5461#define ENET_MAC_INTR_STAT_PMTIS_MASK (0x10U)
5462#define ENET_MAC_INTR_STAT_PMTIS_SHIFT (4U)
5463/*! PMTIS - PMT Interrupt Status.
5464 */
5465#define ENET_MAC_INTR_STAT_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PMTIS_SHIFT)) & ENET_MAC_INTR_STAT_PMTIS_MASK)
5466#define ENET_MAC_INTR_STAT_LPIIS_MASK (0x20U)
5467#define ENET_MAC_INTR_STAT_LPIIS_SHIFT (5U)
5468/*! LPIIS - LPI Interrupt Status.
5469 */
5470#define ENET_MAC_INTR_STAT_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_LPIIS_SHIFT)) & ENET_MAC_INTR_STAT_LPIIS_MASK)
5471#define ENET_MAC_INTR_STAT_TSIS_MASK (0x1000U)
5472#define ENET_MAC_INTR_STAT_TSIS_SHIFT (12U)
5473/*! TSIS - Timestamp interrupt status.
5474 */
5475#define ENET_MAC_INTR_STAT_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TSIS_SHIFT)) & ENET_MAC_INTR_STAT_TSIS_MASK)
5476#define ENET_MAC_INTR_STAT_TXSTSIS_MASK (0x2000U)
5477#define ENET_MAC_INTR_STAT_TXSTSIS_SHIFT (13U)
5478/*! TXSTSIS - Transmit Status Interrupt.
5479 */
5480#define ENET_MAC_INTR_STAT_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_TXSTSIS_MASK)
5481#define ENET_MAC_INTR_STAT_RXSTSIS_MASK (0x4000U)
5482#define ENET_MAC_INTR_STAT_RXSTSIS_SHIFT (14U)
5483/*! RXSTSIS - Receive Status Interrupt.
5484 */
5485#define ENET_MAC_INTR_STAT_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_RXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_RXSTSIS_MASK)
5486/*! @} */
5487
5488/*! @name MAC_INTR_EN - Interrupt enable register 0x0000 */
5489/*! @{ */
5490#define ENET_MAC_INTR_EN_PHYIE_MASK (0x8U)
5491#define ENET_MAC_INTR_EN_PHYIE_SHIFT (3U)
5492/*! PHYIE - PHY Interrupt Enable.
5493 */
5494#define ENET_MAC_INTR_EN_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PHYIE_SHIFT)) & ENET_MAC_INTR_EN_PHYIE_MASK)
5495#define ENET_MAC_INTR_EN_PMTIE_MASK (0x10U)
5496#define ENET_MAC_INTR_EN_PMTIE_SHIFT (4U)
5497/*! PMTIE - PMT Interrupt Enable.
5498 */
5499#define ENET_MAC_INTR_EN_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PMTIE_SHIFT)) & ENET_MAC_INTR_EN_PMTIE_MASK)
5500#define ENET_MAC_INTR_EN_LPIIE_MASK (0x20U)
5501#define ENET_MAC_INTR_EN_LPIIE_SHIFT (5U)
5502/*! LPIIE - LPI Interrupt Enable.
5503 */
5504#define ENET_MAC_INTR_EN_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_LPIIE_SHIFT)) & ENET_MAC_INTR_EN_LPIIE_MASK)
5505#define ENET_MAC_INTR_EN_TSIE_MASK (0x1000U)
5506#define ENET_MAC_INTR_EN_TSIE_SHIFT (12U)
5507/*! TSIE - Timestamp Interrupt Enable.
5508 */
5509#define ENET_MAC_INTR_EN_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TSIE_SHIFT)) & ENET_MAC_INTR_EN_TSIE_MASK)
5510#define ENET_MAC_INTR_EN_TXSTSIE_MASK (0x2000U)
5511#define ENET_MAC_INTR_EN_TXSTSIE_SHIFT (13U)
5512/*! TXSTSIE - Transmit Status Interrupt Enable.
5513 */
5514#define ENET_MAC_INTR_EN_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TXSTSIE_SHIFT)) & ENET_MAC_INTR_EN_TXSTSIE_MASK)
5515#define ENET_MAC_INTR_EN_RXSTSIS_MASK (0x4000U)
5516#define ENET_MAC_INTR_EN_RXSTSIS_SHIFT (14U)
5517/*! RXSTSIS - Receive Status Interrupt Enable.
5518 */
5519#define ENET_MAC_INTR_EN_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_RXSTSIS_SHIFT)) & ENET_MAC_INTR_EN_RXSTSIS_MASK)
5520/*! @} */
5521
5522/*! @name MAC_RXTX_STAT - Receive Transmit Status register */
5523/*! @{ */
5524#define ENET_MAC_RXTX_STAT_TJT_MASK (0x1U)
5525#define ENET_MAC_RXTX_STAT_TJT_SHIFT (0U)
5526/*! TJT - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt
5527 * signal because of the setting of PHYIS bit in MAC Interrupt Status register Table 731.
5528 */
5529#define ENET_MAC_RXTX_STAT_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_TJT_SHIFT)) & ENET_MAC_RXTX_STAT_TJT_MASK)
5530#define ENET_MAC_RXTX_STAT_NCARR_MASK (0x2U)
5531#define ENET_MAC_RXTX_STAT_NCARR_SHIFT (1U)
5532/*! NCARR - No Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758, this
5533 * bit indicates that the carrier signal from the PHY is not present at the end of preamble
5534 * transmission.
5535 */
5536#define ENET_MAC_RXTX_STAT_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_NCARR_SHIFT)) & ENET_MAC_RXTX_STAT_NCARR_MASK)
5537#define ENET_MAC_RXTX_STAT_LCARR_MASK (0x4U)
5538#define ENET_MAC_RXTX_STAT_LCARR_SHIFT (2U)
5539/*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758,
5540 * this bit indicates that the loss of carrier occurred during packet transmission, that is, the
5541 * PHY Carrier signal was inactive for one or more transmission clock periods during packet
5542 * transmission.
5543 */
5544#define ENET_MAC_RXTX_STAT_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCARR_SHIFT)) & ENET_MAC_RXTX_STAT_LCARR_MASK)
5545#define ENET_MAC_RXTX_STAT_EXDEF_MASK (0x8U)
5546#define ENET_MAC_RXTX_STAT_EXDEF_SHIFT (3U)
5547/*! EXDEF - Excessive Deferral When the DTXSTS bit is set in the MTL Operation Mode register Table
5548 * 758 and the DC bit is set in the MAC Configuration register Table 758, this bit indicates that
5549 * the transmission ended because of excessive deferral of over 24,288 bit times (155,680 when
5550 * Jumbo packet is enabled).
5551 */
5552#define ENET_MAC_RXTX_STAT_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXDEF_SHIFT)) & ENET_MAC_RXTX_STAT_EXDEF_MASK)
5553#define ENET_MAC_RXTX_STAT_LCOL_MASK (0x10U)
5554#define ENET_MAC_RXTX_STAT_LCOL_SHIFT (4U)
5555/*! LCOL - Late Collision When the DTXSTS bit is set in the MTL Operation Mode register Table 758,
5556 * this bit indicates that the packet transmission aborted because a collision occurred after the
5557 * collision window (64 bytes including Preamble in MII mode).
5558 */
5559#define ENET_MAC_RXTX_STAT_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCOL_SHIFT)) & ENET_MAC_RXTX_STAT_LCOL_MASK)
5560#define ENET_MAC_RXTX_STAT_EXCOL_MASK (0x20U)
5561#define ENET_MAC_RXTX_STAT_EXCOL_SHIFT (5U)
5562/*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MTL Operation Mode register Table
5563 * 758, this bit indicates that the transmission aborted after 16 successive collisions while
5564 * attempting to transmit the current packet.
5565 */
5566#define ENET_MAC_RXTX_STAT_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXCOL_SHIFT)) & ENET_MAC_RXTX_STAT_EXCOL_MASK)
5567#define ENET_MAC_RXTX_STAT_RWT_MASK (0x100U)
5568#define ENET_MAC_RXTX_STAT_RWT_SHIFT (8U)
5569/*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048
5570 * bytes is received (10,240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the
5571 * MAC Configuration register Table 722.
5572 */
5573#define ENET_MAC_RXTX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_RWT_SHIFT)) & ENET_MAC_RXTX_STAT_RWT_MASK)
5574/*! @} */
5575
5576/*! @name MAC_PMT_CRTL_STAT - */
5577/*! @{ */
5578#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK (0x1U)
5579#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT (0U)
5580/*! PWRDWN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
5581 * entered the LPI state because of the setting of the LPIEN bit.
5582 */
5583#define ENET_MAC_PMT_CRTL_STAT_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK)
5584#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK (0x2U)
5585#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT (1U)
5586/*! MGKPKTEN - Magic Packet Enable.
5587 */
5588#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK)
5589#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK (0x4U)
5590#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT (2U)
5591/*! RWKPKTEN - Remote Wake-Up Packet Enable When this bit is set, a power management event is
5592 * generated when the MAC receives a remote wake-up packet.
5593 */
5594#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK)
5595#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK (0x20U)
5596#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT (5U)
5597/*! MGKPRCVD - Magic Packet Received.
5598 */
5599#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK)
5600#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK (0x40U)
5601#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT (6U)
5602/*! RWKPRCVD - Remote Wake-Up Packet Received.
5603 */
5604#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK)
5605#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK (0x200U)
5606#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT (9U)
5607/*! GLBLUCAST - Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF)
5608 * address recognition is detected as a remote wake-up packet.
5609 */
5610#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK)
5611#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK (0x400U)
5612#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT (10U)
5613/*! RWKPFE - Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the
5614 * MAC receiver drops all received frames until it receives the expected wake-up frame.
5615 */
5616#define ENET_MAC_PMT_CRTL_STAT_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK)
5617#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK (0x1F000000U)
5618#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT (24U)
5619/*! RWKPTR - Remote Wake-up FIFO Pointer This field gives the current value (0 to 7) of the Remote
5620 * Wake-up Packet Filter register pointer.
5621 */
5622#define ENET_MAC_PMT_CRTL_STAT_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK)
5623#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK (0x80000000U)
5624#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT (31U)
5625/*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the
5626 * remote wake-up packet filter register pointer is reset to 3'b000.
5627 */
5628#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK)
5629/*! @} */
5630
5631/*! @name MAC_RWAKE_FRFLT - Remote wake-up frame filter */
5632/*! @{ */
5633#define ENET_MAC_RWAKE_FRFLT_ADDR_MASK (0xFFFFFFFFU)
5634#define ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT (0U)
5635/*! ADDR - WKUPFMFILTER address.
5636 */
5637#define ENET_MAC_RWAKE_FRFLT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT)) & ENET_MAC_RWAKE_FRFLT_ADDR_MASK)
5638/*! @} */
5639
5640/*! @name MAC_LPI_CTRL_STAT - LPI Control and Status Register */
5641/*! @{ */
5642#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK (0x1U)
5643#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT (0U)
5644/*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
5645 * entered the LPI state because of the setting of the LPIEN bit.
5646 */
5647#define ENET_MAC_LPI_CTRL_STAT_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK)
5648#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK (0x2U)
5649#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT (1U)
5650/*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited
5651 * the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired.
5652 */
5653#define ENET_MAC_LPI_CTRL_STAT_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK)
5654#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK (0x4U)
5655#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT (2U)
5656/*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received
5657 * an LPI pattern and entered the LPI state.
5658 */
5659#define ENET_MAC_LPI_CTRL_STAT_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK)
5660#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK (0x8U)
5661#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT (3U)
5662/*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped
5663 * receiving the LPI pattern on the MII interface, exited the LPI state, and resumed the normal
5664 * reception.
5665 */
5666#define ENET_MAC_LPI_CTRL_STAT_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK)
5667#define ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK (0x100U)
5668#define ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT (8U)
5669/*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the LPI pattern on the MII interface.
5670 */
5671#define ENET_MAC_LPI_CTRL_STAT_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK)
5672#define ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK (0x200U)
5673#define ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT (9U)
5674/*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI pattern on the MII interface.
5675 */
5676#define ENET_MAC_LPI_CTRL_STAT_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK)
5677#define ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK (0x10000U)
5678#define ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT (16U)
5679/*! LPIEN - LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state.
5680 */
5681#define ENET_MAC_LPI_CTRL_STAT_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK)
5682#define ENET_MAC_LPI_CTRL_STAT_PLS_MASK (0x20000U)
5683#define ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT (17U)
5684/*! PLS - PHY Link Status This bit indicates the link status of the PHY.
5685 */
5686#define ENET_MAC_LPI_CTRL_STAT_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_PLS_MASK)
5687#define ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK (0x80000U)
5688#define ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT (19U)
5689/*! LPITXA - LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming
5690 * out of the LPI mode on the Transmit side.
5691 */
5692#define ENET_MAC_LPI_CTRL_STAT_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK)
5693#define ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK (0x100000U)
5694#define ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT (20U)
5695/*! LPIATE - LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state.
5696 */
5697#define ENET_MAC_LPI_CTRL_STAT_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK)
5698#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK (0x200000U)
5699#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT (21U)
5700/*! LPITCSE - LPI Tx Clock Stop Enable When this bit is set, the MAC asserts LPI Tx Clock Gating
5701 * Control signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be
5702 * stopped.
5703 */
5704#define ENET_MAC_LPI_CTRL_STAT_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK)
5705/*! @} */
5706
5707/*! @name MAC_LPI_TIMER_CTRL - LPI Timers Control register */
5708/*! @{ */
5709#define ENET_MAC_LPI_TIMER_CTRL_TWT_MASK (0xFFFFU)
5710#define ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT (0U)
5711/*! TWT - LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC
5712 * waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal
5713 * transmission.
5714 */
5715#define ENET_MAC_LPI_TIMER_CTRL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_TWT_MASK)
5716#define ENET_MAC_LPI_TIMER_CTRL_LST_MASK (0x3FF0000U)
5717#define ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT (16U)
5718/*! LST - LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link
5719 * status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY.
5720 */
5721#define ENET_MAC_LPI_TIMER_CTRL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_LST_MASK)
5722/*! @} */
5723
5724/*! @name MAC_LPI_ENTR_TIMR - LPI entry Timer register */
5725/*! @{ */
5726#define ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK (0xFFFF8U)
5727#define ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT (3U)
5728/*! LPIET - LPI Entry Timer This field specifies the time in microseconds the MAC will wait to enter
5729 * LPI mode, after it has transmitted all the frames.
5730 */
5731#define ENET_MAC_LPI_ENTR_TIMR_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT)) & ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK)
5732/*! @} */
5733
5734/*! @name MAC_1US_TIC_COUNTR - */
5735/*! @{ */
5736#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK (0xFFFU)
5737#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT (0U)
5738/*! TIC_1US_CNTR - 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us.
5739 */
5740#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT)) & ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK)
5741/*! @} */
5742
5743/*! @name MAC_VERSION - MAC version register */
5744/*! @{ */
5745#define ENET_MAC_VERSION_SNPVER_MASK (0xFFU)
5746#define ENET_MAC_VERSION_SNPVER_SHIFT (0U)
5747/*! SNPVER - NXP defined version.
5748 */
5749#define ENET_MAC_VERSION_SNPVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPVER_SHIFT)) & ENET_MAC_VERSION_SNPVER_MASK)
5750#define ENET_MAC_VERSION_USERVER_MASK (0xFF00U)
5751#define ENET_MAC_VERSION_USERVER_SHIFT (8U)
5752/*! USERVER - User defined version.
5753 */
5754#define ENET_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK)
5755/*! @} */
5756
5757/*! @name MAC_DBG - MAC debug register */
5758/*! @{ */
5759#define ENET_MAC_DBG_REPESTS_MASK (0x1U)
5760#define ENET_MAC_DBG_REPESTS_SHIFT (0U)
5761/*! REPESTS - MAC MII Receive Protocol Engine Status When this bit is set, it indicates that the MAC
5762 * MII receive protocol engine is actively receiving data, and it is not in the Idle state.
5763 */
5764#define ENET_MAC_DBG_REPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_REPESTS_SHIFT)) & ENET_MAC_DBG_REPESTS_MASK)
5765#define ENET_MAC_DBG_RFCFCSTS_MASK (0x6U)
5766#define ENET_MAC_DBG_RFCFCSTS_SHIFT (1U)
5767/*! RFCFCSTS - MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates
5768 * the active state of the small FIFO Read and Write controllers of the MAC Receive Packet
5769 * Controller module.
5770 */
5771#define ENET_MAC_DBG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_RFCFCSTS_SHIFT)) & ENET_MAC_DBG_RFCFCSTS_MASK)
5772#define ENET_MAC_DBG_TPESTS_MASK (0x10000U)
5773#define ENET_MAC_DBG_TPESTS_SHIFT (16U)
5774/*! TPESTS - MAC MII Transmit Protocol Engine Status When this bit is set, it indicates that the MAC
5775 * or MII transmit protocol engine is actively transmitting data, and it is not in the Idle
5776 * state.
5777 */
5778#define ENET_MAC_DBG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TPESTS_SHIFT)) & ENET_MAC_DBG_TPESTS_MASK)
5779#define ENET_MAC_DBG_TFCSTS_MASK (0x60000U)
5780#define ENET_MAC_DBG_TFCSTS_SHIFT (17U)
5781/*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module.
5782 */
5783#define ENET_MAC_DBG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TFCSTS_SHIFT)) & ENET_MAC_DBG_TFCSTS_MASK)
5784/*! @} */
5785
5786/*! @name MAC_HW_FEAT - MAC hardware feature register 0x0201 */
5787/*! @{ */
5788#define ENET_MAC_HW_FEAT_MIISEL_MASK (0x1U)
5789#define ENET_MAC_HW_FEAT_MIISEL_SHIFT (0U)
5790/*! MIISEL - 10 or 100 Mbps Support.
5791 */
5792#define ENET_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK)
5793#define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU)
5794#define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U)
5795/*! RXFIFOSIZE - MTL Receive FIFO Size.
5796 */
5797#define ENET_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK)
5798#define ENET_MAC_HW_FEAT_RXQCNT_MASK (0xFU)
5799#define ENET_MAC_HW_FEAT_RXQCNT_SHIFT (0U)
5800/*! RXQCNT - Number of MTL Receive Queues.
5801 */
5802#define ENET_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK)
5803#define ENET_MAC_HW_FEAT_HDSEL_MASK (0x4U)
5804#define ENET_MAC_HW_FEAT_HDSEL_SHIFT (2U)
5805/*! HDSEL - Half-duplex Support.
5806 */
5807#define ENET_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK)
5808#define ENET_MAC_HW_FEAT_VLHASH_MASK (0x10U)
5809#define ENET_MAC_HW_FEAT_VLHASH_SHIFT (4U)
5810/*! VLHASH - Hash Table Based Filtering option.
5811 */
5812#define ENET_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK)
5813#define ENET_MAC_HW_FEAT_SMASEL_MASK (0x20U)
5814#define ENET_MAC_HW_FEAT_SMASEL_SHIFT (5U)
5815/*! SMASEL - SMA (MDIO) Interface.
5816 */
5817#define ENET_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK)
5818#define ENET_MAC_HW_FEAT_RWKSEL_MASK (0x40U)
5819#define ENET_MAC_HW_FEAT_RWKSEL_SHIFT (6U)
5820/*! RWKSEL - PMT Remote Wake-up Packet Detection.
5821 */
5822#define ENET_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK)
5823#define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U)
5824#define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U)
5825/*! TXFIFOSIZE - MTL Transmit FIFO Size.
5826 */
5827#define ENET_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK)
5828#define ENET_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U)
5829#define ENET_MAC_HW_FEAT_TXQCNT_SHIFT (6U)
5830/*! TXQCNT - Number of MTL Transmit Queues.
5831 */
5832#define ENET_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK)
5833#define ENET_MAC_HW_FEAT_MGKSEL_MASK (0x80U)
5834#define ENET_MAC_HW_FEAT_MGKSEL_SHIFT (7U)
5835/*! MGKSEL - PMT magic packet detection.
5836 */
5837#define ENET_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK)
5838#define ENET_MAC_HW_FEAT_MMCSEL_MASK (0x100U)
5839#define ENET_MAC_HW_FEAT_MMCSEL_SHIFT (8U)
5840/*! MMCSEL - RMON Module Enable.
5841 */
5842#define ENET_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK)
5843#define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U)
5844#define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U)
5845/*! ARPOFFSEL - ARP Offload Enabled.
5846 */
5847#define ENET_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK)
5848#define ENET_MAC_HW_FEAT_OSTEN_MASK (0x800U)
5849#define ENET_MAC_HW_FEAT_OSTEN_SHIFT (11U)
5850/*! OSTEN - One-Step Timestamping Feature.
5851 */
5852#define ENET_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK)
5853#define ENET_MAC_HW_FEAT_PTOEN_MASK (0x1000U)
5854#define ENET_MAC_HW_FEAT_PTOEN_SHIFT (12U)
5855/*! PTOEN - PTP OffLoad Feature.
5856 */
5857#define ENET_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK)
5858#define ENET_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U)
5859#define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT (12U)
5860/*! RXCHCNT - Number of DMA Receive Channels.
5861 */
5862#define ENET_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK)
5863#define ENET_MAC_HW_FEAT_TSSEL_MASK (0x1000U)
5864#define ENET_MAC_HW_FEAT_TSSEL_SHIFT (12U)
5865/*! TSSEL - IEEE 1588-2008 Timestamp support .
5866 */
5867#define ENET_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK)
5868#define ENET_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U)
5869#define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U)
5870/*! ADVTHWORD - IEEE 1588 High Word Register Feature.
5871 */
5872#define ENET_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK)
5873#define ENET_MAC_HW_FEAT_EEESEL_MASK (0x2000U)
5874#define ENET_MAC_HW_FEAT_EEESEL_SHIFT (13U)
5875/*! EEESEL - Energy Efficient Ethernet Support .
5876 */
5877#define ENET_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK)
5878#define ENET_MAC_HW_FEAT_ADDR64_MASK (0xC000U)
5879#define ENET_MAC_HW_FEAT_ADDR64_SHIFT (14U)
5880/*! ADDR64 - Address width.
5881 */
5882#define ENET_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK)
5883#define ENET_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U)
5884#define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT (14U)
5885/*! TXCOESEL - Transmit Checksum Offload Support.
5886 */
5887#define ENET_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK)
5888#define ENET_MAC_HW_FEAT_DCBEN_MASK (0x10000U)
5889#define ENET_MAC_HW_FEAT_DCBEN_SHIFT (16U)
5890/*! DCBEN - Data Center Bridging feature.
5891 */
5892#define ENET_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK)
5893#define ENET_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U)
5894#define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT (16U)
5895/*! RXCOESEL - Receive Checksum Offload Support.
5896 */
5897#define ENET_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK)
5898#define ENET_MAC_HW_FEAT_SPEN_MASK (0x20000U)
5899#define ENET_MAC_HW_FEAT_SPEN_SHIFT (17U)
5900/*! SPEN - Split Header Structure feature.
5901 */
5902#define ENET_MAC_HW_FEAT_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPEN_SHIFT)) & ENET_MAC_HW_FEAT_SPEN_MASK)
5903#define ENET_MAC_HW_FEAT_TSOEN_MASK (0x40000U)
5904#define ENET_MAC_HW_FEAT_TSOEN_SHIFT (18U)
5905/*! TSOEN - TCP Segment Offload Feature.
5906 */
5907#define ENET_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK)
5908#define ENET_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U)
5909#define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT (18U)
5910/*! TXCHCNT - Number of DMA Transmit Channels.
5911 */
5912#define ENET_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK)
5913#define ENET_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U)
5914#define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT (19U)
5915/*! DBGMEMA - DMA Debug Register Feature.
5916 */
5917#define ENET_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK)
5918#define ENET_MAC_HW_FEAT_AVSEL_MASK (0x100000U)
5919#define ENET_MAC_HW_FEAT_AVSEL_SHIFT (20U)
5920/*! AVSEL - Audio Video Bridging Feature.
5921 */
5922#define ENET_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK)
5923#define ENET_MAC_HW_FEAT_LPMODEEN_MASK (0x800000U)
5924#define ENET_MAC_HW_FEAT_LPMODEEN_SHIFT (23U)
5925/*! LPMODEEN - Low Power Mode Feature Support .
5926 */
5927#define ENET_MAC_HW_FEAT_LPMODEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_LPMODEEN_SHIFT)) & ENET_MAC_HW_FEAT_LPMODEEN_MASK)
5928#define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U)
5929#define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U)
5930/*! HASHTBLSZ - Hash Table Size.
5931 */
5932#define ENET_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK)
5933#define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U)
5934#define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U)
5935/*! PPSOUTNUM - Number of PPS Outputs.
5936 */
5937#define ENET_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK)
5938#define ENET_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U)
5939#define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U)
5940/*! TSSTSSEL - Timestamp System Time Source.
5941 */
5942#define ENET_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK)
5943#define ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK (0x78000000U)
5944#define ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT (27U)
5945/*! L3_L4_FILTER - Total Number of L3 and L4 Filters .
5946 */
5947#define ENET_MAC_HW_FEAT_L3_L4_FILTER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT)) & ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK)
5948#define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U)
5949#define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U)
5950/*! ACTPHYSEL - Active PHY Selected.
5951 */
5952#define ENET_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK)
5953#define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U)
5954#define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U)
5955/*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs.
5956 */
5957#define ENET_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK)
5958/*! @} */
5959
5960/* The count of ENET_MAC_HW_FEAT */
5961#define ENET_MAC_HW_FEAT_COUNT (3U)
5962
5963/*! @name MAC_MDIO_ADDR - MIDO address Register */
5964/*! @{ */
5965#define ENET_MAC_MDIO_ADDR_MB_MASK (0x1U)
5966#define ENET_MAC_MDIO_ADDR_MB_SHIFT (0U)
5967/*! MB - MII busy.
5968 */
5969#define ENET_MAC_MDIO_ADDR_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MB_SHIFT)) & ENET_MAC_MDIO_ADDR_MB_MASK)
5970#define ENET_MAC_MDIO_ADDR_MOC_MASK (0xCU)
5971#define ENET_MAC_MDIO_ADDR_MOC_SHIFT (2U)
5972/*! MOC - MII Operation Command.
5973 */
5974#define ENET_MAC_MDIO_ADDR_MOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MOC_SHIFT)) & ENET_MAC_MDIO_ADDR_MOC_MASK)
5975#define ENET_MAC_MDIO_ADDR_CR_MASK (0xF00U)
5976#define ENET_MAC_MDIO_ADDR_CR_SHIFT (8U)
5977/*! CR - CSR Clock Range.
5978 */
5979#define ENET_MAC_MDIO_ADDR_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_CR_SHIFT)) & ENET_MAC_MDIO_ADDR_CR_MASK)
5980#define ENET_MAC_MDIO_ADDR_NTC_MASK (0x7000U)
5981#define ENET_MAC_MDIO_ADDR_NTC_SHIFT (12U)
5982/*! NTC - Number of Training Clocks This field controls the number of trailing clock cycles
5983 * generated on MDC after the end of transmission of MDIO frame.
5984 */
5985#define ENET_MAC_MDIO_ADDR_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_NTC_SHIFT)) & ENET_MAC_MDIO_ADDR_NTC_MASK)
5986#define ENET_MAC_MDIO_ADDR_RDA_MASK (0x1F0000U)
5987#define ENET_MAC_MDIO_ADDR_RDA_SHIFT (16U)
5988/*! RDA - Register/Device Address These bits select the PHY register in selected PHY device.
5989 */
5990#define ENET_MAC_MDIO_ADDR_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_RDA_SHIFT)) & ENET_MAC_MDIO_ADDR_RDA_MASK)
5991#define ENET_MAC_MDIO_ADDR_PA_MASK (0x3E00000U)
5992#define ENET_MAC_MDIO_ADDR_PA_SHIFT (21U)
5993/*! PA - Physical Layer Address This field indicates which PHY devices (out of 32 devices) the MAC is accessing.
5994 */
5995#define ENET_MAC_MDIO_ADDR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PA_SHIFT)) & ENET_MAC_MDIO_ADDR_PA_MASK)
5996#define ENET_MAC_MDIO_ADDR_BTB_MASK (0x4000000U)
5997#define ENET_MAC_MDIO_ADDR_BTB_SHIFT (26U)
5998/*! BTB - Back to Back transactions When this bit is set and the NTC has value greater than 0, then
5999 * the MAC will inform the completion of a read or write command at the end of frame transfer
6000 * (before the trailing clocks are transmitted).
6001 */
6002#define ENET_MAC_MDIO_ADDR_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_BTB_SHIFT)) & ENET_MAC_MDIO_ADDR_BTB_MASK)
6003#define ENET_MAC_MDIO_ADDR_PSE_MASK (0x8000000U)
6004#define ENET_MAC_MDIO_ADDR_PSE_SHIFT (27U)
6005/*! PSE - Preamble Suppression Enable When this bit is set, the SMA will suppress the 32-bit
6006 * preamble and transmit MDIO frames with only 1 preamble bit.
6007 */
6008#define ENET_MAC_MDIO_ADDR_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PSE_SHIFT)) & ENET_MAC_MDIO_ADDR_PSE_MASK)
6009/*! @} */
6010
6011/*! @name MAC_MDIO_DATA - MDIO Data register */
6012/*! @{ */
6013#define ENET_MAC_MDIO_DATA_MD_MASK (0xFFFFU)
6014#define ENET_MAC_MDIO_DATA_MD_SHIFT (0U)
6015/*! MD - MII Data This field contains the 16-bit data value read from the PHY after a Management
6016 * Read operation or the 16-bit data value to be written to the PHY before a Management Write
6017 * operation.
6018 */
6019#define ENET_MAC_MDIO_DATA_MD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_MD_SHIFT)) & ENET_MAC_MDIO_DATA_MD_MASK)
6020/*! @} */
6021
6022/*! @name MAC_ADDR_HIGH - MAC address0 high register */
6023/*! @{ */
6024#define ENET_MAC_ADDR_HIGH_A47_32_MASK (0xFFFFU)
6025#define ENET_MAC_ADDR_HIGH_A47_32_SHIFT (0U)
6026/*! A47_32 - MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the 6-byte first MAC address.
6027 */
6028#define ENET_MAC_ADDR_HIGH_A47_32(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_A47_32_SHIFT)) & ENET_MAC_ADDR_HIGH_A47_32_MASK)
6029#define ENET_MAC_ADDR_HIGH_DCS_MASK (0x10000U)
6030#define ENET_MAC_ADDR_HIGH_DCS_SHIFT (16U)
6031/*! DCS - DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose
6032 * DA matches the MAC Address content is routed.
6033 */
6034#define ENET_MAC_ADDR_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_DCS_SHIFT)) & ENET_MAC_ADDR_HIGH_DCS_MASK)
6035#define ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000U)
6036#define ENET_MAC_ADDR_HIGH_AE_SHIFT (31U)
6037/*! AE - Address Enable.
6038 */
6039#define ENET_MAC_ADDR_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_AE_SHIFT)) & ENET_MAC_ADDR_HIGH_AE_MASK)
6040/*! @} */
6041
6042/*! @name MAC_ADDR_LOW - MAC address0 low register */
6043/*! @{ */
6044#define ENET_MAC_ADDR_LOW_A31_0_MASK (0xFFFFFFFFU)
6045#define ENET_MAC_ADDR_LOW_A31_0_SHIFT (0U)
6046/*! A31_0 - MAC Address0 [31:0] This field contains the lower 32 bits of the 6-byte first MAC address.
6047 */
6048#define ENET_MAC_ADDR_LOW_A31_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_LOW_A31_0_SHIFT)) & ENET_MAC_ADDR_LOW_A31_0_MASK)
6049/*! @} */
6050
6051/*! @name MAC_TIMESTAMP_CTRL - Time stamp control register */
6052/*! @{ */
6053#define ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK (0x1U)
6054#define ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT (0U)
6055/*! TSENA - Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets.
6056 */
6057#define ENET_MAC_TIMESTAMP_CTRL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK)
6058#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK (0x2U)
6059#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT (1U)
6060/*! TSCFUPDT - Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp.
6061 */
6062#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK)
6063#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK (0x4U)
6064#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT (2U)
6065/*! TSINIT - Initialize Timestamp When this bit is set, the system time is initialized (overwritten)
6066 * with the value specified in the MAC Register 80 (System Time Seconds Update.
6067 */
6068#define ENET_MAC_TIMESTAMP_CTRL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK)
6069#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK (0x8U)
6070#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT (3U)
6071/*! TSUPDT - Update Timestamp When this bit is set, the system time is updated (added or subtracted)
6072 * with the value specified in MAC System Time Seconds Update Table 753 and MAC System Time
6073 * Nanoseconds Update Table 754.
6074 */
6075#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK)
6076#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK (0x10U)
6077#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT (4U)
6078/*! TSTRIG - Enable Timestamp Interrupt Trigger When this bit is set, the timestamp interrupt is
6079 * generated when the System Time becomes greater than the value written in the Target Time register.
6080 */
6081#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK)
6082#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK (0x20U)
6083#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT (5U)
6084/*! TADDREG - Update Addend Register When this bit is set, the content of the Timestamp Addend
6085 * register is updated in the PTP block for fine correction.
6086 */
6087#define ENET_MAC_TIMESTAMP_CTRL_TADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK)
6088#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK (0x100U)
6089#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT (8U)
6090/*! TSENALL - Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is
6091 * enabled for all packets received by the MAC.
6092 */
6093#define ENET_MAC_TIMESTAMP_CTRL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK)
6094#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK (0x200U)
6095#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT (9U)
6096/*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low
6097 * register rolls over after 0x3B9AC9FF value (that is, 1 nanosecond accuracy) and increments
6098 * the timestamp (High) seconds.
6099 */
6100#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)
6101#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK (0x400U)
6102#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT (10U)
6103/*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE
6104 * 1588 version 2 format is used to process the PTP packets.
6105 */
6106#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK)
6107#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK (0x800U)
6108#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT (11U)
6109/*! TSIPENA - Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver
6110 * processes the PTP packets encapsulated directly in the Ethernet packets.
6111 */
6112#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK)
6113#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK (0x1000U)
6114#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT (12U)
6115/*! TSIPV6ENA - Enable Processing of PTP Packets Sent over 1Pv6-UDP When this bit is set, the MAC
6116 * receiver processes the PTP packets encapsulated in IPv6-UDP packets.
6117 */
6118#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK)
6119#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK (0x2000U)
6120#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT (13U)
6121/*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC
6122 * receiver processes the PTP packets encapsulated in IPv4-UDP packets.
6123 */
6124#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK)
6125#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK (0x4000U)
6126#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT (14U)
6127/*! TSEVTENA - Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp
6128 * snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp).
6129 */
6130#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK)
6131#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK (0x8000U)
6132#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT (15U)
6133/*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot
6134 * is taken only for the messages that are relevant to the master node.
6135 */
6136#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK)
6137#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK (0x30000U)
6138#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT (16U)
6139/*! SNAPTYPSEL - Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14,
6140 * decide the set of PTP packet types for which snapshot needs to be taken.
6141 */
6142#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK)
6143#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK (0x40000U)
6144#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT (18U)
6145/*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC
6146 * address (that matches any MAC Address register) is used to filter the PTP packets when PTP is
6147 * directly sent over Ethernet.
6148 */
6149#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK)
6150#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK (0x1000000U)
6151#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT (24U)
6152/*! TXTTSSTSM - Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier
6153 * transmit timestamp status even if it is not read by the software.
6154 */
6155#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK)
6156#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK (0x10000000U)
6157#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT (28U)
6158/*! AV8021ASMEN - AV 802.
6159 */
6160#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK)
6161/*! @} */
6162
6163/*! @name MAC_SUB_SCND_INCR - Sub-second increment register */
6164/*! @{ */
6165#define ENET_MAC_SUB_SCND_INCR_SSINC_MASK (0xFF0000U)
6166#define ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT (16U)
6167/*! SSINC - Sub-second increment value.
6168 */
6169#define ENET_MAC_SUB_SCND_INCR_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT)) & ENET_MAC_SUB_SCND_INCR_SSINC_MASK)
6170/*! @} */
6171
6172/*! @name MAC_SYS_TIME_SCND - System time seconds register */
6173/*! @{ */
6174#define ENET_MAC_SYS_TIME_SCND_TSS_MASK (0xFFFFFFFFU)
6175#define ENET_MAC_SYS_TIME_SCND_TSS_SHIFT (0U)
6176/*! TSS - Time stamp second The value in this field indicates the current value in seconds of the
6177 * System Time maintained by the MAC.
6178 */
6179#define ENET_MAC_SYS_TIME_SCND_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_TSS_MASK)
6180/*! @} */
6181
6182/*! @name MAC_SYS_TIME_NSCND - System time nanoseconds register */
6183/*! @{ */
6184#define ENET_MAC_SYS_TIME_NSCND_TSSS_MASK (0x7FFFFFFFU)
6185#define ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT (0U)
6186/*! TSSS - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.
6187 */
6188#define ENET_MAC_SYS_TIME_NSCND_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK)
6189/*! @} */
6190
6191/*! @name MAC_SYS_TIME_SCND_UPD - */
6192/*! @{ */
6193#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK (0xFFFFFFFFU)
6194#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT (0U)
6195/*! TSS - Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time.
6196 */
6197#define ENET_MAC_SYS_TIME_SCND_UPD_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK)
6198/*! @} */
6199
6200/*! @name MAC_SYS_TIME_NSCND_UPD - */
6201/*! @{ */
6202#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK (0x7FFFFFFFU)
6203#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT (0U)
6204/*! TSSS - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.
6205 */
6206#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK)
6207#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK (0x80000000U)
6208#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT (31U)
6209/*! ADDSUB - Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register.
6210 */
6211#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK)
6212/*! @} */
6213
6214/*! @name MAC_SYS_TIMESTMP_ADDEND - Time stamp addend register */
6215/*! @{ */
6216#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK (0xFFFFFFFFU)
6217#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT (0U)
6218/*! TSAR - Time stamp addend This register indicates the 32-bit time value to be added to the
6219 * Accumulator register to achieve time synchronization.
6220 */
6221#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK)
6222/*! @} */
6223
6224/*! @name MAC_SYS_TIME_HWORD_SCND - */
6225/*! @{ */
6226#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK (0xFFFFU)
6227#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT (0U)
6228/*! TSHWR - Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value.
6229 */
6230#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT)) & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK)
6231/*! @} */
6232
6233/*! @name MAC_SYS_TIMESTMP_STAT - Time stamp status register */
6234/*! @{ */
6235#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK (0x1U)
6236#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT (0U)
6237/*! TSSOVF - Time stamp seconds overflow When set, indicates that the seconds value of the Time
6238 * stamp has overflowed beyond 0xFFFF_FFFF.
6239 */
6240#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT)) & ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK)
6241/*! @} */
6242
6243/*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Tx timestamp status nanoseconds */
6244/*! @{ */
6245#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK (0x7FFFFFFFU)
6246#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT (0U)
6247/*! TXTSSTSLO - Transmit timestamp status low.
6248 */
6249#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK)
6250#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK (0x80000000U)
6251#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT (31U)
6252/*! TXTSSTSMIS - Transmit timestamp status missed.
6253 */
6254#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK)
6255/*! @} */
6256
6257/*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Tx timestamp status seconds */
6258/*! @{ */
6259#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK (0xFFFFFFFFU)
6260#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT (0U)
6261/*! TXTSSTSHI - Transmit timestamp status high.
6262 */
6263#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK)
6264/*! @} */
6265
6266/*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp ingress correction */
6267/*! @{ */
6268#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
6269#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
6270/*! TSIC - Transmit ingress correction.
6271 */
6272#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
6273/*! @} */
6274
6275/*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp egress correction */
6276/*! @{ */
6277#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
6278#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
6279/*! TSEC - Transmit egress correction.
6280 */
6281#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
6282/*! @} */
6283
6284/*! @name MTL_OP_MODE - MTL Operation Mode Register */
6285/*! @{ */
6286#define ENET_MTL_OP_MODE_DTXSTS_MASK (0x2U)
6287#define ENET_MTL_OP_MODE_DTXSTS_SHIFT (1U)
6288/*! DTXSTS - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL.
6289 */
6290#define ENET_MTL_OP_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_DTXSTS_SHIFT)) & ENET_MTL_OP_MODE_DTXSTS_MASK)
6291#define ENET_MTL_OP_MODE_RAA_MASK (0x4U)
6292#define ENET_MTL_OP_MODE_RAA_SHIFT (2U)
6293/*! RAA - Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side.
6294 */
6295#define ENET_MTL_OP_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_RAA_SHIFT)) & ENET_MTL_OP_MODE_RAA_MASK)
6296#define ENET_MTL_OP_MODE_SCHALG_MASK (0x60U)
6297#define ENET_MTL_OP_MODE_SCHALG_SHIFT (5U)
6298/*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: 0x00: WRR
6299 * algorithm 0x1: Reserved 0x2: Reserved 0x3: Strict priority algorithm.
6300 */
6301#define ENET_MTL_OP_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_SCHALG_SHIFT)) & ENET_MTL_OP_MODE_SCHALG_MASK)
6302#define ENET_MTL_OP_MODE_CNTPRST_MASK (0x100U)
6303#define ENET_MTL_OP_MODE_CNTPRST_SHIFT (8U)
6304/*! CNTPRST - Counters Preset When this bit is set, MTL TxQ0 Underflow register (Table 762) and
6305 * MTL_TxQ1_Underflow (Table 762) registers are initialized/preset to 0x7F0.
6306 */
6307#define ENET_MTL_OP_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTPRST_SHIFT)) & ENET_MTL_OP_MODE_CNTPRST_MASK)
6308#define ENET_MTL_OP_MODE_CNTCLR_MASK (0x200U)
6309#define ENET_MTL_OP_MODE_CNTCLR_SHIFT (9U)
6310/*! CNTCLR - Counters Reset When this bit is set, all counters are reset.
6311 */
6312#define ENET_MTL_OP_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTCLR_SHIFT)) & ENET_MTL_OP_MODE_CNTCLR_MASK)
6313/*! @} */
6314
6315/*! @name MTL_INTR_STAT - MTL Interrupt Status register */
6316/*! @{ */
6317#define ENET_MTL_INTR_STAT_Q0IS_MASK (0x1U)
6318#define ENET_MTL_INTR_STAT_Q0IS_SHIFT (0U)
6319/*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0.
6320 */
6321#define ENET_MTL_INTR_STAT_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q0IS_SHIFT)) & ENET_MTL_INTR_STAT_Q0IS_MASK)
6322#define ENET_MTL_INTR_STAT_Q1IS_MASK (0x2U)
6323#define ENET_MTL_INTR_STAT_Q1IS_SHIFT (1U)
6324/*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1.
6325 */
6326#define ENET_MTL_INTR_STAT_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q1IS_SHIFT)) & ENET_MTL_INTR_STAT_Q1IS_MASK)
6327/*! @} */
6328
6329/*! @name MTL_RXQ_DMA_MAP - MTL Receive Queue and DMA Channel Mapping register */
6330/*! @{ */
6331#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK (0x1U)
6332#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT (0U)
6333/*! Q0MDMACH - Queue 0 Mapped to DMA Channel This field controls the routing of the packet received
6334 * in Queue 0 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the
6335 * Q0DDMACH field is reset.
6336 */
6337#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK)
6338#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK (0x10U)
6339#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT (4U)
6340/*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
6341 * the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC
6342 * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
6343 * Ethernet DA address.
6344 */
6345#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK)
6346#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK (0x100U)
6347#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT (8U)
6348/*! Q1MDMACH - Queue 1 Mapped to DMA Channel This field controls the routing of the received packet
6349 * in Queue 1 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the
6350 * Q1DDMACH field is reset.
6351 */
6352#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK)
6353#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK (0x1000U)
6354#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT (12U)
6355/*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
6356 * the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC
6357 * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
6358 * Ethernet DA address.
6359 */
6360#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK)
6361/*! @} */
6362
6363/*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - MTL TxQx Operation Mode register */
6364/*! @{ */
6365#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U)
6366#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U)
6367/*! FTQ - Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values.
6368 */
6369#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK)
6370#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U)
6371#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U)
6372/*! TSF - Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue.
6373 */
6374#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK)
6375#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU)
6376#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U)
6377/*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0.
6378 */
6379#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK)
6380#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U)
6381#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U)
6382/*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue.
6383 */
6384#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK)
6385#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U)
6386#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U)
6387/*! TQS - Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes.
6388 */
6389#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK)
6390/*! @} */
6391
6392/* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */
6393#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT (2U)
6394
6395/*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - MTL TxQx Underflow register */
6396/*! @{ */
6397#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU)
6398#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
6399/*! UFFRMCNT - Underflow Packet Counter This field indicates the number of packets aborted by the
6400 * controller because of Tx Queue Underflow.
6401 */
6402#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
6403#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U)
6404#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
6405/*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue
6406 * Underflow Packet Counter field overflows, that is, it has crossed the maximum count.
6407 */
6408#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
6409/*! @} */
6410
6411/* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */
6412#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT (2U)
6413
6414/*! @name MTL_QUEUE_MTL_TXQX_DBG - MTL TxQx Debug register */
6415/*! @{ */
6416#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U)
6417#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U)
6418/*! TXQPAUSED - Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it
6419 * indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because
6420 * of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue
6421 * when PFC is enabled - Reception of 802.
6422 */
6423#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK)
6424#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK (0x6U)
6425#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U)
6426/*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read
6427 * Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10:
6428 * Waiting for pending Tx Status from the MAC transmitter 11: Flushing the Tx queue because of the
6429 * Packet Abort request from the MAC.
6430 */
6431#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK)
6432#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK (0x8U)
6433#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U)
6434/*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx
6435 * Queue Write Controller is active, and it is transferring the data to the Tx Queue.
6436 */
6437#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK)
6438#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK (0x10U)
6439#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U)
6440/*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue
6441 * is not empty and some data is left for transmission.
6442 */
6443#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK)
6444#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U)
6445#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U)
6446/*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full.
6447 */
6448#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK)
6449#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK (0x70000U)
6450#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT (16U)
6451/*! PTXQ - Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue.
6452 */
6453#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK)
6454#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK (0x700000U)
6455#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT (20U)
6456/*! STSXSTSF - Number of Status Words in Tx Status FIFO of Queue This field indicates the current
6457 * number of status in the Tx Status FIFO of this queue.
6458 */
6459#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK)
6460/*! @} */
6461
6462/* The count of ENET_MTL_QUEUE_MTL_TXQX_DBG */
6463#define ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT (2U)
6464
6465/*! @name MTL_QUEUE_MTL_TXQX_ETS_CTRL - MTL TxQx ETS control register, only TxQ1 support */
6466/*! @{ */
6467#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U)
6468#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U)
6469/*! AVALG - AV Algorithm.
6470 */
6471#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK)
6472#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U)
6473#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U)
6474/*! CC - Credit Control.
6475 */
6476#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK)
6477#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U)
6478#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U)
6479/*! SLC - Credit Control.
6480 */
6481#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK)
6482/*! @} */
6483
6484/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL */
6485#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT (2U)
6486
6487/*! @name MTL_QUEUE_MTL_TXQX_ETS_STAT - MTL TxQx ETS Status register */
6488/*! @{ */
6489#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU)
6490#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U)
6491/*! ABS - Average Bits per Slot.
6492 */
6493#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK)
6494/*! @} */
6495
6496/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT */
6497#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT (2U)
6498
6499/*! @name MTL_QUEUE_MTL_TXQX_QNTM_WGHT - */
6500/*! @{ */
6501#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU)
6502#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U)
6503/*! ISCQW - Average Bits per Slot.
6504 */
6505#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)
6506/*! @} */
6507
6508/* The count of ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT */
6509#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT (2U)
6510
6511/*! @name MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT - MTL TxQx SendSlopCredit register, only TxQ1 support */
6512/*! @{ */
6513#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU)
6514#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U)
6515/*! SSC - sendSlopeCredit.
6516 */
6517#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)
6518/*! @} */
6519
6520/* The count of ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT */
6521#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U)
6522
6523/*! @name MTL_QUEUE_MTL_TXQX_HI_CRDT - MTL TxQx hiCredit register, only TxQ1 support */
6524/*! @{ */
6525#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU)
6526#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U)
6527/*! HC - hiCredit.
6528 */
6529#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK)
6530/*! @} */
6531
6532/* The count of ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT */
6533#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT (2U)
6534
6535/*! @name MTL_QUEUE_MTL_TXQX_LO_CRDT - MTL TxQx loCredit register, only TxQ1 support */
6536/*! @{ */
6537#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU)
6538#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U)
6539/*! LC - loCredit.
6540 */
6541#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK)
6542/*! @} */
6543
6544/* The count of ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT */
6545#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT (2U)
6546
6547/*! @name MTL_QUEUE_MTL_TXQX_INTCTRL_STAT - */
6548/*! @{ */
6549#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)
6550#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)
6551/*! TXUNFIS - Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue
6552 * had an underflow while transmitting the packet.
6553 */
6554#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)
6555#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)
6556#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)
6557/*! ABPSIS - Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value.
6558 */
6559#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)
6560#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)
6561#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)
6562/*! TXUIE - Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled.
6563 */
6564#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)
6565#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)
6566#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)
6567/*! ABPSIE - Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the
6568 * interrupt when the average bits per slot status is updated.
6569 */
6570#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)
6571#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)
6572#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)
6573/*! RXOVFIS - Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had
6574 * an overflow while receiving the packet.
6575 */
6576#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)
6577#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)
6578#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)
6579/*! RXOIE - Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled.
6580 */
6581#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)
6582/*! @} */
6583
6584/* The count of ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT */
6585#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_COUNT (2U)
6586
6587/*! @name MTL_QUEUE_MTL_RXQX_OP_MODE - MTL RxQx Operation Mode register */
6588/*! @{ */
6589#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U)
6590#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U)
6591/*! RTC - Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue
6592 * (in bytes): 00: 64 01: 32 10: 96 11: 128 The packet received is transferred to the
6593 * application or DMA when the packet size within the MTL Rx queue is larger than the threshold.
6594 */
6595#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK)
6596#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U)
6597#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U)
6598/*! FUP - Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized
6599 * good packets (packets with no error and length less than 64 bytes), including pad-bytes and
6600 * CRC.
6601 */
6602#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK)
6603#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U)
6604#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U)
6605/*! FEP - Forward Error Packets When this bit is reset, the Rx queue drops packets with error status
6606 * (CRC error, Mll_ER, watchdog timeout, or overflow).
6607 */
6608#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK)
6609#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U)
6610#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U)
6611/*! RSF - Receive Queue Store and Forward When this bit is set, the ethernet block on this chip
6612 * reads a packet from the Rx queue only after the complete packet has been written to it, ignoring
6613 * the RTC field of this register.
6614 */
6615#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK)
6616#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)
6617#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)
6618/*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC
6619 * does not drop the packets which only have the errors detected by the Receive Checksum Offload
6620 * engine.
6621 */
6622#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)
6623#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U)
6624#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U)
6625/*! RQS - This field indicates the size of the allocated Receive queues in blocks of 256 bytes.
6626 */
6627#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK)
6628/*! @} */
6629
6630/* The count of ENET_MTL_QUEUE_MTL_RXQX_OP_MODE */
6631#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT (2U)
6632
6633/*! @name MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT - MTL RxQx Missed Packet Overflow Counter register */
6634/*! @{ */
6635#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)
6636#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)
6637/*! OVFPKTCNT - Overflow Packet Counter This field indicates the number of packets discarded by the
6638 * Ethernet block because of Receive queue overflow.
6639 */
6640#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)
6641#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)
6642#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)
6643/*! OVFCNTOVF - Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue
6644 * Overflow Packet Counter field crossed the maximum limit.
6645 */
6646#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)
6647/*! @} */
6648
6649/* The count of ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT */
6650#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U)
6651
6652/*! @name MTL_QUEUE_MTL_RXQX_DBG - MTL RxQx Debug register */
6653/*! @{ */
6654#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK (0x1U)
6655#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U)
6656/*! RWCSTS - MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL
6657 * Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue.
6658 */
6659#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK)
6660#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK (0x6U)
6661#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U)
6662/*! RRCSTS - MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read
6663 * controller: 00: Idle state 01: Reading packet data 10: Reading packet status (or timestamp) 11:
6664 * Flushing the packet data and status.
6665 */
6666#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK)
6667#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK (0x30U)
6668#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U)
6669/*! RXQSTS - MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx
6670 * Queue: 0x0: Rx Queue empty 0x1: Rx Queue fill-level below flow-control deactivate threshold
6671 * 0x2: Rx Queue fill-level above flow-control activate threshold 0x3: Rx Queue full.
6672 */
6673#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK)
6674#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U)
6675#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT (16U)
6676/*! PRXQ - Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue.
6677 */
6678#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK)
6679/*! @} */
6680
6681/* The count of ENET_MTL_QUEUE_MTL_RXQX_DBG */
6682#define ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT (2U)
6683
6684/*! @name MTL_QUEUE_MTL_RXQX_CTRL - MTL RxQx Control register */
6685/*! @{ */
6686#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U)
6687#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U)
6688/*! RXQ_WEGT - Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0.
6689 */
6690#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK)
6691#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)
6692#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)
6693/*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration When this bit is set, the The ethernet block
6694 * drives the packet data to the ARI interface such that the entire packet data of
6695 * currently-selected queue is transmitted before switching to other queue.
6696 */
6697#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)
6698/*! @} */
6699
6700/* The count of ENET_MTL_QUEUE_MTL_RXQX_CTRL */
6701#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT (2U)
6702
6703/*! @name DMA_MODE - DMA mode register */
6704/*! @{ */
6705#define ENET_DMA_MODE_SWR_MASK (0x1U)
6706#define ENET_DMA_MODE_SWR_SHIFT (0U)
6707/*! SWR - Software Reset When this bit is set, the MAC and the OMA controller reset the logic and
6708 * all internal registers of the OMA, MTL, and MAC.
6709 */
6710#define ENET_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK)
6711#define ENET_DMA_MODE_DA_MASK (0x2U)
6712#define ENET_DMA_MODE_DA_SHIFT (1U)
6713/*! DA - DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the
6714 * Transmit and Receive paths of all channels: The Tx path has priority over the Rx path when the TXPR
6715 * bit is set.
6716 */
6717#define ENET_DMA_MODE_DA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK)
6718#define ENET_DMA_MODE_TAA_MASK (0x1CU)
6719#define ENET_DMA_MODE_TAA_SHIFT (2U)
6720/*! TAA - Transmit Arbitration Algorithm This field is used to select the arbitration algorithm for
6721 * the Transmit side when multiple Tx DMAs are selected.
6722 */
6723#define ENET_DMA_MODE_TAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK)
6724#define ENET_DMA_MODE_TXPR_MASK (0x800U)
6725#define ENET_DMA_MODE_TXPR_SHIFT (11U)
6726/*! TXPR - Transmit Priority When set, this bit indicates that the Tx DMA has higher priority than
6727 * the Rx DMA during arbitration for the system-side bus.
6728 */
6729#define ENET_DMA_MODE_TXPR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK)
6730#define ENET_DMA_MODE_PR_MASK (0x7000U)
6731#define ENET_DMA_MODE_PR_SHIFT (12U)
6732/*! PR - Priority Ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA.
6733 */
6734#define ENET_DMA_MODE_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK)
6735/*! @} */
6736
6737/*! @name DMA_SYSBUS_MODE - DMA System Bus mode */
6738/*! @{ */
6739#define ENET_DMA_SYSBUS_MODE_FB_MASK (0x1U)
6740#define ENET_DMA_SYSBUS_MODE_FB_SHIFT (0U)
6741/*! FB - Fixed Burst Length When this bit is set to 1, the AHB master will initiate burst transfers
6742 * of specified length (INCRx or SINGLE).
6743 */
6744#define ENET_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK)
6745#define ENET_DMA_SYSBUS_MODE_AAL_MASK (0x1000U)
6746#define ENET_DMA_SYSBUS_MODE_AAL_SHIFT (12U)
6747/*! AAL - Address-Aligned Beats When this bit is set to 1, the AHB master performs address-aligned
6748 * burst transfers on Read and Write channels.
6749 */
6750#define ENET_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK)
6751#define ENET_DMA_SYSBUS_MODE_MB_MASK (0x4000U)
6752#define ENET_DMA_SYSBUS_MODE_MB_SHIFT (14U)
6753/*! MB - Mixed Burst When this bit is set high and the FB bit is low, the AHB master performs
6754 * undefined bursts transfers (INCR) for burst length of 16 or more.
6755 */
6756#define ENET_DMA_SYSBUS_MODE_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK)
6757#define ENET_DMA_SYSBUS_MODE_RB_MASK (0x8000U)
6758#define ENET_DMA_SYSBUS_MODE_RB_SHIFT (15U)
6759/*! RB - Rebuild INCRx Burst When this bit is set high and the AHB master gets SPLIT, RETRY, or
6760 * EarlyBurst Termination (EBT) response, the AHB master interface rebuilds the pending beats of any
6761 * initiated burst transfer with INCRx and SINGLEtransfers.
6762 */
6763#define ENET_DMA_SYSBUS_MODE_RB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK)
6764/*! @} */
6765
6766/*! @name DMA_INTR_STAT - DMA Interrupt status */
6767/*! @{ */
6768#define ENET_DMA_INTR_STAT_DC0IS_MASK (0x1U)
6769#define ENET_DMA_INTR_STAT_DC0IS_SHIFT (0U)
6770/*! DC0IS - DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0.
6771 */
6772#define ENET_DMA_INTR_STAT_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC0IS_SHIFT)) & ENET_DMA_INTR_STAT_DC0IS_MASK)
6773#define ENET_DMA_INTR_STAT_DC1IS_MASK (0x2U)
6774#define ENET_DMA_INTR_STAT_DC1IS_SHIFT (1U)
6775/*! DC1IS - DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1.
6776 */
6777#define ENET_DMA_INTR_STAT_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC1IS_SHIFT)) & ENET_DMA_INTR_STAT_DC1IS_MASK)
6778#define ENET_DMA_INTR_STAT_MTLIS_MASK (0x10000U)
6779#define ENET_DMA_INTR_STAT_MTLIS_SHIFT (16U)
6780/*! MTLIS - MTL Interrupt Status This bit indicates an interrupt event in the MTL.
6781 */
6782#define ENET_DMA_INTR_STAT_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MTLIS_SHIFT)) & ENET_DMA_INTR_STAT_MTLIS_MASK)
6783#define ENET_DMA_INTR_STAT_MACIS_MASK (0x20000U)
6784#define ENET_DMA_INTR_STAT_MACIS_SHIFT (17U)
6785/*! MACIS - MAC Interrupt Status This bit indicates an interrupt event in the MAC.
6786 */
6787#define ENET_DMA_INTR_STAT_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MACIS_SHIFT)) & ENET_DMA_INTR_STAT_MACIS_MASK)
6788/*! @} */
6789
6790/*! @name DMA_DBG_STAT - DMA Debug Status */
6791/*! @{ */
6792#define ENET_DMA_DBG_STAT_AHSTS_MASK (0x1U)
6793#define ENET_DMA_DBG_STAT_AHSTS_SHIFT (0U)
6794/*! AHSTS - AHB Master Status When high, this bit indicates that the AHB master FSMs are in the non-idle state.
6795 */
6796#define ENET_DMA_DBG_STAT_AHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_AHSTS_SHIFT)) & ENET_DMA_DBG_STAT_AHSTS_MASK)
6797#define ENET_DMA_DBG_STAT_RPS0_MASK (0xF00U)
6798#define ENET_DMA_DBG_STAT_RPS0_SHIFT (8U)
6799/*! RPS0 - DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel
6800 * 0: 0x0: Stopped (Reset or Stop Receive Command issued) 0x1: Running (Fetching Rx Transfer )
6801 * 0x2: Reserved 0x3: Running (Waiting for Rx packet) 0x4: Suspended (Rx Unavailable) 0x5: Running
6802 * (Closing the Rx) 0x6: Timestamp write state 0x7: Running (Transferring the received packet
6803 * data from the Rx buffer to the system memory) This field does not generate an interrupt.
6804 */
6805#define ENET_DMA_DBG_STAT_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS0_SHIFT)) & ENET_DMA_DBG_STAT_RPS0_MASK)
6806#define ENET_DMA_DBG_STAT_TPS0_MASK (0xF000U)
6807#define ENET_DMA_DBG_STAT_TPS0_SHIFT (12U)
6808/*! TPS0 - DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for
6809 * Channel 0: 000: Stopped (Reset or Stop Transmit Command issued) 0x1: Running (Fetching Tx Transfer)
6810 * 0x2: Running (Waiting for status) 0x3: Running (Reading Data from system memory buffer and
6811 * queuing it to the Tx buffer (Tx FIFO)) 0x4: Timestamp write state 0x5: Reserved for future use
6812 * 0x6: Suspended (Tx Unavailable or Tx Buffer Underflow) 0x7: Running (Closing Tx ) This field
6813 * does not generate an interrupt.
6814 */
6815#define ENET_DMA_DBG_STAT_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS0_SHIFT)) & ENET_DMA_DBG_STAT_TPS0_MASK)
6816#define ENET_DMA_DBG_STAT_RPS1_MASK (0xF0000U)
6817#define ENET_DMA_DBG_STAT_RPS1_SHIFT (16U)
6818/*! RPS1 - DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1.
6819 */
6820#define ENET_DMA_DBG_STAT_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS1_SHIFT)) & ENET_DMA_DBG_STAT_RPS1_MASK)
6821#define ENET_DMA_DBG_STAT_TPS1_MASK (0xF00000U)
6822#define ENET_DMA_DBG_STAT_TPS1_SHIFT (20U)
6823/*! TPS1 - DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1.
6824 */
6825#define ENET_DMA_DBG_STAT_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS1_SHIFT)) & ENET_DMA_DBG_STAT_TPS1_MASK)
6826/*! @} */
6827
6828/*! @name DMA_CH_DMA_CHX_CTRL - DMA Channelx Control */
6829/*! @{ */
6830#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK (0x10000U)
6831#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT (16U)
6832/*! PBLx8 - 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in DMA Channel
6833 * Transmit Control Table 780 is multiplied eight times.
6834 */
6835#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK)
6836#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK (0x1C0000U)
6837#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT (18U)
6838/*! DSL - Skip Length This bit specifies the Word, Dword, or Lword number (depending on the 32- bit,
6839 * 64-bit, or 128-bit bus) to skip between two unchained s.
6840 */
6841#define ENET_DMA_CH_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK)
6842/*! @} */
6843
6844/* The count of ENET_DMA_CH_DMA_CHX_CTRL */
6845#define ENET_DMA_CH_DMA_CHX_CTRL_COUNT (2U)
6846
6847/*! @name DMA_CH_DMA_CHX_TX_CTRL - DMA Channelx Transmit Control */
6848/*! @{ */
6849#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK (0x1U)
6850#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT (0U)
6851/*! ST - Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state.
6852 */
6853#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK)
6854#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK (0xEU)
6855#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT (1U)
6856/*! TCW - Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel.
6857 */
6858#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK)
6859#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK (0x10U)
6860#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT (4U)
6861/*! OSF - Operate on Second Frame When this bit is set, it instructs the DMA to process the second
6862 * packet of the Transmit data even before the status for the first packet is obtained.
6863 */
6864#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK)
6865#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U)
6866#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U)
6867/*! TxPBL - Transmit Programmable Burst Length These bits indicate the maximum number of beats to be
6868 * transferred in one DMA data transfer.
6869 */
6870#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK)
6871/*! @} */
6872
6873/* The count of ENET_DMA_CH_DMA_CHX_TX_CTRL */
6874#define ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT (2U)
6875
6876/*! @name DMA_CH_DMA_CHX_RX_CTRL - DMA Channelx Receive Control */
6877/*! @{ */
6878#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK (0x1U)
6879#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT (0U)
6880/*! SR - Start or Stop Receive When this bit is set, the DMA tries to acquire the from the receive
6881 * list and processes the incoming packets.
6882 */
6883#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK)
6884#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK (0x7FF8U)
6885#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT (3U)
6886/*! RBSZ - Receive Buffer size This field indicates the size of the Rx buffers specified in bytes.
6887 */
6888#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK)
6889#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U)
6890#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U)
6891/*! RxPBL - Receive Programmable Burst Length These bits indicate the maximum number of beats to be
6892 * transferred in one DMA data transfer.
6893 */
6894#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK)
6895#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U)
6896#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT (31U)
6897/*! RPF - DMA Rx Channel 0 Packet Flush When this bit is set to 1, the DMA will automatically flush
6898 * the packet from the Rx Queues destined to DMA Rx Channel 0 when the DMA Rx Channel 0 is
6899 * stopped after a system bus error has occurred.
6900 */
6901#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK)
6902/*! @} */
6903
6904/* The count of ENET_DMA_CH_DMA_CHX_RX_CTRL */
6905#define ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT (2U)
6906
6907/*! @name DMA_CH_DMA_CHX_TXDESC_LIST_ADDR - */
6908/*! @{ */
6909#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK (0xFFFFFFFCU)
6910#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT (2U)
6911/*! STL - Start of transmit list This field contains the base address of the first in the Transmit list.
6912 */
6913#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK)
6914/*! @} */
6915
6916/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR */
6917#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U)
6918
6919/*! @name DMA_CH_DMA_CHX_RXDESC_LIST_ADDR - */
6920/*! @{ */
6921#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK (0xFFFFFFFCU)
6922#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT (2U)
6923/*! SRL - Start of receive list This field contains the base address of the First in the Receive list.
6924 */
6925#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK)
6926/*! @} */
6927
6928/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR */
6929#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U)
6930
6931/*! @name DMA_CH_DMA_CHX_TXDESC_TAIL_PTR - */
6932/*! @{ */
6933#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU)
6934#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U)
6935/*! TDTP - Transmit Tail Pointer This field contains the tail pointer for the Tx ring.
6936 */
6937#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)
6938/*! @} */
6939
6940/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR */
6941#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U)
6942
6943/*! @name DMA_CH_DMA_CHX_RXDESC_TAIL_PTR - */
6944/*! @{ */
6945#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU)
6946#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U)
6947/*! RDTP - Receive Tail Pointer This field contains the tail pointer for the Rx ring.
6948 */
6949#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)
6950/*! @} */
6951
6952/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR */
6953#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U)
6954
6955/*! @name DMA_CH_DMA_CHX_TXDESC_RING_LENGTH - */
6956/*! @{ */
6957#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)
6958#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
6959/*! TDRL - Transmit Ring Length This field sets the maximum number of Tx descriptors in the circular ring.
6960 */
6961#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)
6962/*! @} */
6963
6964/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH */
6965#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U)
6966
6967/*! @name DMA_CH_DMA_CHX_RXDESC_RING_LENGTH - Channelx Rx descriptor Ring Length */
6968/*! @{ */
6969#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)
6970#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)
6971/*! RDRL - Receive Ring Length This register sets the maximum number of Rx descriptors in the circular ring.
6972 */
6973#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)
6974/*! @} */
6975
6976/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH */
6977#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_COUNT (2U)
6978
6979/*! @name DMA_CH_DMA_CHX_INT_EN - Channelx Interrupt Enable */
6980/*! @{ */
6981#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK (0x1U)
6982#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT (0U)
6983/*! TIE - Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit
6984 * 16 in this register), Transmit Interrupt is enabled.
6985 */
6986#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK)
6987#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK (0x2U)
6988#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT (1U)
6989/*! TSE - Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit
6990 * 15 in this register), Transmission Stopped Interrupt is enabled.
6991 */
6992#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK)
6993#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK (0x4U)
6994#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT (2U)
6995/*! TBUE - Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary
6996 * Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled.
6997 */
6998#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK)
6999#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK (0x40U)
7000#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT (6U)
7001/*! RIE - Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16
7002 * in this register), Receive Interrupt is enabled.
7003 */
7004#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK)
7005#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK (0x80U)
7006#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT (7U)
7007/*! RBUE - Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary
7008 * Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled.
7009 */
7010#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK)
7011#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK (0x100U)
7012#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT (8U)
7013/*! RSE - Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit
7014 * 15 in this register), Receive Stopped Interrupt is enabled.
7015 */
7016#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK)
7017#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK (0x200U)
7018#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT (9U)
7019/*! RWTE - Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary
7020 * Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled.
7021 */
7022#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK)
7023#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK (0x400U)
7024#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT (10U)
7025/*! ETIE - Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary
7026 * Enable (bit 15 in this register), Early Transmit Interrupt is enabled.
7027 */
7028#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK)
7029#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK (0x800U)
7030#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT (11U)
7031/*! ERIE - Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable
7032 * (bit 16 in this register), Early Receive Interrupt is enabled.
7033 */
7034#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK)
7035#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK (0x1000U)
7036#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT (12U)
7037/*! FBEE - Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit
7038 * 15 in this register), the Fatal Bus Error Interrupt is enabled.
7039 */
7040#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK)
7041#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK (0x4000U)
7042#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT (14U)
7043/*! AIE - Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt summary is enabled.
7044 */
7045#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK)
7046#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK (0x8000U)
7047#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT (15U)
7048/*! NIE - Normal interrupt summary enable When this bit is set, a normal interrupt is enabled.
7049 */
7050#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK)
7051/*! @} */
7052
7053/* The count of ENET_DMA_CH_DMA_CHX_INT_EN */
7054#define ENET_DMA_CH_DMA_CHX_INT_EN_COUNT (2U)
7055
7056/*! @name DMA_CH_DMA_CHX_RX_INT_WDTIMER - Receive Interrupt Watchdog Timer */
7057/*! @{ */
7058#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK (0xFFU)
7059#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT (0U)
7060/*! RIWT - Receive Interrupt Watchdog Timer Count Indicates the number of system clock cycles
7061 * multiplied by 256 for which the watchdog timer is set.
7062 */
7063#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK)
7064/*! @} */
7065
7066/* The count of ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER */
7067#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_COUNT (2U)
7068
7069/*! @name DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT - Slot Function Control and Status */
7070/*! @{ */
7071#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)
7072#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)
7073/*! ESC - Enable Slot Comparison When set, this bit enables the checking of the slot numbers
7074 * programmed in the Tx descriptor with the current reference given in the RSN field.
7075 */
7076#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)
7077#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)
7078#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)
7079/*! ASC - Advance Slot Check When set, this bit enables the D MA to fetch the data from the buffer
7080 * when the slot number (SLOTNUM) programmed in the Tx descriptor is equal to the reference slot
7081 * number given in the RSN field or, ahead of the reference slot number by up to two slots This
7082 * bit is applicable only when the ESC bit is set.
7083 */
7084#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)
7085#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)
7086#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)
7087/*! RSN - Reference Slot Number This field gives the current value of the reference slot number in the DMA.
7088 */
7089#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)
7090/*! @} */
7091
7092/* The count of ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT */
7093#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U)
7094
7095/*! @name DMA_CH_DMA_CHX_CUR_HST_TXDESC - Channelx Current Host Transmit descriptor */
7096/*! @{ */
7097#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK (0xFFFFFFFFU)
7098#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT (0U)
7099/*! HTD - Host Transmit descriptor Address Pointer Cleared on Reset.
7100 */
7101#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK)
7102/*! @} */
7103
7104/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC */
7105#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_COUNT (2U)
7106
7107/*! @name DMA_CH_DMA_CHX_CUR_HST_RXDESC - */
7108/*! @{ */
7109#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK (0xFFFFFFFFU)
7110#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT (0U)
7111/*! HRD - Host Receive descriptor Address Pointer Cleared on Reset.
7112 */
7113#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK)
7114/*! @} */
7115
7116/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC */
7117#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_COUNT (2U)
7118
7119/*! @name DMA_CH_DMA_CHX_CUR_HST_TXBUF - */
7120/*! @{ */
7121#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK (0xFFFFFFFFU)
7122#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT (0U)
7123/*! HTB - Host Transmit Buffer Address Pointer Cleared on Reset.
7124 */
7125#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK)
7126/*! @} */
7127
7128/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF */
7129#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_COUNT (2U)
7130
7131/*! @name DMA_CH_DMA_CHX_CUR_HST_RXBUF - Channelx Current Application Receive Buffer Address */
7132/*! @{ */
7133#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK (0xFFFFFFFFU)
7134#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT (0U)
7135/*! HRB - Host Receive Buffer Address Pointer Cleared on Reset.
7136 */
7137#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK)
7138/*! @} */
7139
7140/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF */
7141#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_COUNT (2U)
7142
7143/*! @name DMA_CH_DMA_CHX_STAT - Channelx DMA status register */
7144/*! @{ */
7145#define ENET_DMA_CH_DMA_CHX_STAT_TI_MASK (0x1U)
7146#define ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT (0U)
7147/*! TI - Transmit Interrupt This bit indicates that the packet transmission is complete.
7148 */
7149#define ENET_DMA_CH_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK)
7150#define ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK (0x2U)
7151#define ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT (1U)
7152/*! TPS - Transmit Process Stopped This bit is set when the transmission is stopped.
7153 */
7154#define ENET_DMA_CH_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK)
7155#define ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK (0x4U)
7156#define ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT (2U)
7157/*! TBU - Transmit Buffer Unavailable This bit indicates that the application owns the next
7158 * descriptor in the transmit list, and the DMA cannot acquire it.
7159 */
7160#define ENET_DMA_CH_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK)
7161#define ENET_DMA_CH_DMA_CHX_STAT_RI_MASK (0x40U)
7162#define ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT (6U)
7163/*! RI - Receive Interrupt This bit indicates that the packet reception is complete.
7164 */
7165#define ENET_DMA_CH_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK)
7166#define ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK (0x80U)
7167#define ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT (7U)
7168/*! RBU - Receive Buffer Unavailable This bit indicates that the application owns the next in the
7169 * receive list, and the DMA cannot acquire it.
7170 */
7171#define ENET_DMA_CH_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK)
7172#define ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK (0x100U)
7173#define ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT (8U)
7174/*! RPS - Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state.
7175 */
7176#define ENET_DMA_CH_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK)
7177#define ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK (0x200U)
7178#define ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT (9U)
7179/*! RWT - Receive Watchdog time out This bit is asserted when a packet with length greater than
7180 * 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received.
7181 */
7182#define ENET_DMA_CH_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK)
7183#define ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK (0x400U)
7184#define ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT (10U)
7185/*! ETI - Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO.
7186 */
7187#define ENET_DMA_CH_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK)
7188#define ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK (0x800U)
7189#define ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT (11U)
7190/*! ERI - Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet.
7191 */
7192#define ENET_DMA_CH_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK)
7193#define ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK (0x1000U)
7194#define ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT (12U)
7195/*! FBE - Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field).
7196 */
7197#define ENET_DMA_CH_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK)
7198#define ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK (0x4000U)
7199#define ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT (14U)
7200/*! AIS - Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the
7201 * following when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable
7202 * register Table 778: Bit 1: Transmit Process Stopped Bit 7: Receive Buffer Unavailable Bit 8:
7203 * Receive Process Stopped Bit 10: Ear1y Transmit Interrupt Bit 12: Fatal Bus Error Only unmasked
7204 * bits affect the Abnormal Interrupt Summary bit.
7205 */
7206#define ENET_DMA_CH_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK)
7207#define ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK (0x8000U)
7208#define ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT (15U)
7209/*! NIS - Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the
7210 * following bits when the corresponding interrupt bits are enabled in the DMA Channel Interrupt
7211 * Enable register Table 778: Bit 0: Transmit Interrupt Bit 2: Transmit Buffer Unavailable Bit 6:
7212 * Receive Interrupt Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which
7213 * interrupt enable is set in DMA Channel Interrupt Enable register Table 778) affect the Normal
7214 * Interrupt Summary bit.
7215 */
7216#define ENET_DMA_CH_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK)
7217#define ENET_DMA_CH_DMA_CHX_STAT_EB_MASK (0x70000U)
7218#define ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT (16U)
7219/*! EB - DMA Error Bits This field indicates the type of error that caused a Bus Error.
7220 */
7221#define ENET_DMA_CH_DMA_CHX_STAT_EB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_EB_MASK)
7222/*! @} */
7223
7224/* The count of ENET_DMA_CH_DMA_CHX_STAT */
7225#define ENET_DMA_CH_DMA_CHX_STAT_COUNT (2U)
7226
7227/*! @name DMA_CH_DMA_CHX_MISS_FRAME_CNT - Channelx missed frame count. */
7228/*! @{ */
7229#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_MASK (0x7FFU)
7230#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT (0U)
7231/*! MFC - Dropped packet counters.
7232 */
7233#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT)) & ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_MASK)
7234#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U)
7235#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U)
7236/*! MFCO - Overflow status of the MFC counter.
7237 */
7238#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT)) & ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK)
7239/*! @} */
7240
7241/* The count of ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT */
7242#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_COUNT (2U)
7243
7244
7245/*!
7246 * @}
7247 */ /* end of group ENET_Register_Masks */
7248
7249
7250/* ENET - Peripheral instance base addresses */
7251/** Peripheral ENET base address */
7252#define ENET_BASE (0x40092000u)
7253/** Peripheral ENET base pointer */
7254#define ENET ((ENET_Type *)ENET_BASE)
7255/** Array initializer of ENET peripheral base addresses */
7256#define ENET_BASE_ADDRS { ENET_BASE }
7257/** Array initializer of ENET peripheral base pointers */
7258#define ENET_BASE_PTRS { ENET }
7259/** Interrupt vectors for the ENET peripheral type */
7260#define ENET_IRQS { ETHERNET_IRQn }
7261#define ENET_PMT_IRQS { ETHERNET_PMT_IRQn }
7262#define ENET_MACLP_IRQS { ETHERNET_MACLP_IRQn }
7263
7264/*!
7265 * @}
7266 */ /* end of group ENET_Peripheral_Access_Layer */
7267
7268
7269/* ----------------------------------------------------------------------------
7270 -- FLEXCOMM Peripheral Access Layer
7271 ---------------------------------------------------------------------------- */
7272
7273/*!
7274 * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
7275 * @{
7276 */
7277
7278/** FLEXCOMM - Register Layout Typedef */
7279typedef struct {
7280 uint8_t RESERVED_0[4088];
7281 __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
7282 __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */
7283} FLEXCOMM_Type;
7284
7285/* ----------------------------------------------------------------------------
7286 -- FLEXCOMM Register Masks
7287 ---------------------------------------------------------------------------- */
7288
7289/*!
7290 * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
7291 * @{
7292 */
7293
7294/*! @name PSELID - Peripheral Select and Flexcomm ID register. */
7295/*! @{ */
7296#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U)
7297#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U)
7298/*! PERSEL - Peripheral Select. This field is writable by software.
7299 * 0b000..No peripheral selected.
7300 * 0b001..USART function selected.
7301 * 0b010..SPI function selected.
7302 * 0b011..I2C function selected.
7303 * 0b100..I2S transmit function selected.
7304 * 0b101..I2S receive function selected.
7305 * 0b110..Reserved
7306 * 0b111..Reserved
7307 */
7308#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
7309#define FLEXCOMM_PSELID_LOCK_MASK (0x8U)
7310#define FLEXCOMM_PSELID_LOCK_SHIFT (3U)
7311/*! LOCK - Lock the peripheral select. This field is writable by software.
7312 * 0b0..Peripheral select can be changed by software.
7313 * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset.
7314 */
7315#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
7316#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U)
7317#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U)
7318/*! USARTPRESENT - USART present indicator. This field is Read-only.
7319 * 0b0..This Flexcomm does not include the USART function.
7320 * 0b1..This Flexcomm includes the USART function.
7321 */
7322#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
7323#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U)
7324#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U)
7325/*! SPIPRESENT - SPI present indicator. This field is Read-only.
7326 * 0b0..This Flexcomm does not include the SPI function.
7327 * 0b1..This Flexcomm includes the SPI function.
7328 */
7329#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
7330#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U)
7331#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U)
7332/*! I2CPRESENT - I2C present indicator. This field is Read-only.
7333 * 0b0..This Flexcomm does not include the I2C function.
7334 * 0b1..This Flexcomm includes the I2C function.
7335 */
7336#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
7337#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U)
7338#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U)
7339/*! I2SPRESENT - I 2S present indicator. This field is Read-only.
7340 * 0b0..This Flexcomm does not include the I2S function.
7341 * 0b1..This Flexcomm includes the I2S function.
7342 */
7343#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
7344#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U)
7345#define FLEXCOMM_PSELID_ID_SHIFT (12U)
7346/*! ID - Flexcomm ID.
7347 */
7348#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
7349/*! @} */
7350
7351/*! @name PID - Peripheral identification register. */
7352/*! @{ */
7353#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U)
7354#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U)
7355/*! Minor_Rev - Minor revision of module implementation.
7356 */
7357#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)
7358#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U)
7359#define FLEXCOMM_PID_Major_Rev_SHIFT (12U)
7360/*! Major_Rev - Major revision of module implementation.
7361 */
7362#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)
7363#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U)
7364#define FLEXCOMM_PID_ID_SHIFT (16U)
7365/*! ID - Module identifier for the selected function.
7366 */
7367#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
7368/*! @} */
7369
7370
7371/*!
7372 * @}
7373 */ /* end of group FLEXCOMM_Register_Masks */
7374
7375
7376/* FLEXCOMM - Peripheral instance base addresses */
7377/** Peripheral FLEXCOMM0 base address */
7378#define FLEXCOMM0_BASE (0x40086000u)
7379/** Peripheral FLEXCOMM0 base pointer */
7380#define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
7381/** Peripheral FLEXCOMM1 base address */
7382#define FLEXCOMM1_BASE (0x40087000u)
7383/** Peripheral FLEXCOMM1 base pointer */
7384#define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
7385/** Peripheral FLEXCOMM2 base address */
7386#define FLEXCOMM2_BASE (0x40088000u)
7387/** Peripheral FLEXCOMM2 base pointer */
7388#define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
7389/** Peripheral FLEXCOMM3 base address */
7390#define FLEXCOMM3_BASE (0x40089000u)
7391/** Peripheral FLEXCOMM3 base pointer */
7392#define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
7393/** Peripheral FLEXCOMM4 base address */
7394#define FLEXCOMM4_BASE (0x4008A000u)
7395/** Peripheral FLEXCOMM4 base pointer */
7396#define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
7397/** Peripheral FLEXCOMM5 base address */
7398#define FLEXCOMM5_BASE (0x40096000u)
7399/** Peripheral FLEXCOMM5 base pointer */
7400#define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
7401/** Peripheral FLEXCOMM6 base address */
7402#define FLEXCOMM6_BASE (0x40097000u)
7403/** Peripheral FLEXCOMM6 base pointer */
7404#define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
7405/** Peripheral FLEXCOMM7 base address */
7406#define FLEXCOMM7_BASE (0x40098000u)
7407/** Peripheral FLEXCOMM7 base pointer */
7408#define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
7409/** Peripheral FLEXCOMM8 base address */
7410#define FLEXCOMM8_BASE (0x40099000u)
7411/** Peripheral FLEXCOMM8 base pointer */
7412#define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
7413/** Peripheral FLEXCOMM9 base address */
7414#define FLEXCOMM9_BASE (0x4009A000u)
7415/** Peripheral FLEXCOMM9 base pointer */
7416#define FLEXCOMM9 ((FLEXCOMM_Type *)FLEXCOMM9_BASE)
7417/** Peripheral FLEXCOMM10 base address */
7418#define FLEXCOMM10_BASE (0x4009F000u)
7419/** Peripheral FLEXCOMM10 base pointer */
7420#define FLEXCOMM10 ((FLEXCOMM_Type *)FLEXCOMM10_BASE)
7421/** Array initializer of FLEXCOMM peripheral base addresses */
7422#define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE, FLEXCOMM10_BASE }
7423/** Array initializer of FLEXCOMM peripheral base pointers */
7424#define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9, FLEXCOMM10 }
7425/** Interrupt vectors for the FLEXCOMM peripheral type */
7426#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn, FLEXCOMM10_IRQn }
7427
7428/*!
7429 * @}
7430 */ /* end of group FLEXCOMM_Peripheral_Access_Layer */
7431
7432
7433/* ----------------------------------------------------------------------------
7434 -- GINT Peripheral Access Layer
7435 ---------------------------------------------------------------------------- */
7436
7437/*!
7438 * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer
7439 * @{
7440 */
7441
7442/** GINT - Register Layout Typedef */
7443typedef struct {
7444 __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */
7445 uint8_t RESERVED_0[28];
7446 __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */
7447 uint8_t RESERVED_1[24];
7448 __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */
7449} GINT_Type;
7450
7451/* ----------------------------------------------------------------------------
7452 -- GINT Register Masks
7453 ---------------------------------------------------------------------------- */
7454
7455/*!
7456 * @addtogroup GINT_Register_Masks GINT Register Masks
7457 * @{
7458 */
7459
7460/*! @name CTRL - GPIO grouped interrupt control register */
7461/*! @{ */
7462#define GINT_CTRL_INT_MASK (0x1U)
7463#define GINT_CTRL_INT_SHIFT (0U)
7464/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.
7465 * 0b0..No request. No interrupt request is pending.
7466 * 0b1..Request active. Interrupt request is active.
7467 */
7468#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)
7469#define GINT_CTRL_COMB_MASK (0x2U)
7470#define GINT_CTRL_COMB_SHIFT (1U)
7471/*! COMB - Combine enabled inputs for group interrupt
7472 * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).
7473 * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).
7474 */
7475#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)
7476#define GINT_CTRL_TRIG_MASK (0x4U)
7477#define GINT_CTRL_TRIG_SHIFT (2U)
7478/*! TRIG - Group interrupt trigger