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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/driver_reset.cmake14
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_clock.c2051
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_clock.h1249
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_inputmux_connections.h481
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_power.c19
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_power.h603
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_reset.c99
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_reset.h255
8 files changed, 4771 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/driver_reset.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/driver_reset.cmake
new file mode 100644
index 000000000..989530f6f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/driver_reset.cmake
@@ -0,0 +1,14 @@
1if(NOT DRIVER_RESET_INCLUDED)
2
3 set(DRIVER_RESET_INCLUDED true CACHE BOOL "driver_reset component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 )
7
8 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
9 ${CMAKE_CURRENT_LIST_DIR}/.
10 )
11
12
13
14endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_clock.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_clock.c
new file mode 100644
index 000000000..51da68c6f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_clock.c
@@ -0,0 +1,2051 @@
1/*
2 * Copyright 2017 - 2020 , NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_clock.h"
9#include "fsl_power.h"
10/*******************************************************************************
11 * Definitions
12 ******************************************************************************/
13/* Component ID definition, used by tools. */
14#ifndef FSL_COMPONENT_ID
15#define FSL_COMPONENT_ID "platform.drivers.clock"
16#endif
17#define NVALMAX (0x100U)
18#define PVALMAX (0x20U)
19#define MVALMAX (0x10000U)
20
21#define PLL_MAX_N_DIV 0x100U
22
23/*--------------------------------------------------------------------------
24!!! If required these #defines can be moved to chip library file
25----------------------------------------------------------------------------*/
26
27#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 25 downto 10 */
28#define PLL_SSCG1_MDEC_VAL_M (0xFFFFULL << PLL_SSCG1_MDEC_VAL_P)
29#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */
30#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P)
31#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */
32#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P)
33
34#define PLL_MIN_CCO_FREQ_MHZ (275000000U)
35#define PLL_MAX_CCO_FREQ_MHZ (550000000U)
36#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */
37#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */
38#define PLL_MIN_IN_SSMODE (3000000U)
39#define PLL_MAX_IN_SSMODE \
40 (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */
41
42/* PLL NDEC reg */
43#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M)
44/* PLL PDEC reg */
45#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M)
46/* SSCG control1 */
47#define PLL_SSCG1_MDEC_VAL_SET(value) (((uint64_t)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M)
48
49/* PLL0 SSCG control1 */
50#define PLL0_SSCG_MD_FRACT_P 0U
51#define PLL0_SSCG_MD_INT_P 25U
52#define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P)
53#define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P)
54
55#define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_FRACT_M)
56#define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M)
57
58/* Saved value of PLL output rate, computed whenever needed to save run-time
59 computation on each call to retrive the PLL rate. */
60static uint32_t s_Pll0_Freq;
61static uint32_t s_Pll1_Freq;
62
63/** External clock rate on the CLKIN pin in Hz. If not used,
64 set this to 0. Otherwise, set it to the exact rate in Hz this pin is
65 being driven at. */
66static uint32_t s_Ext_Clk_Freq = 16000000U;
67static uint32_t s_I2S_Mclk_Freq = 0U;
68static uint32_t s_PLU_ClkIn_Freq = 0U;
69
70/*******************************************************************************
71 * Variables
72 ******************************************************************************/
73
74/*******************************************************************************
75 * Prototypes
76 ******************************************************************************/
77/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */
78static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR);
79/* Get predivider (N) from PLL0 NDEC setting */
80static uint32_t findPll0PreDiv(void);
81/* Get predivider (N) from PLL1 NDEC setting */
82static uint32_t findPll1PreDiv(void);
83/* Get postdivider (P) from PLL0 PDEC setting */
84static uint32_t findPll0PostDiv(void);
85/* Get postdivider (P) from PLL1 PDEC setting. */
86static uint32_t findPll1PostDiv(void);
87/* Get multiplier (M) from PLL0 MDEC and SSCG settings */
88static float findPll0MMult(void);
89/* Get multiplier (M) from PLL1 MDEC. */
90static uint32_t findPll1MMult(void);
91/* Get the greatest common divisor */
92static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n);
93/* Set PLL output based on desired output rate */
94static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS);
95/* Update local PLL rate variable */
96static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup);
97/* Update local PLL1 rate variable */
98static void CLOCK_GetPLL1OutFromSetupUpdate(pll_setup_t *pSetup);
99
100/*******************************************************************************
101 * Code
102 ******************************************************************************/
103
104/* Clock Selection for IP */
105/**
106 * brief Configure the clock selection muxes.
107 * param connection : Clock to be configured.
108 * return Nothing
109 */
110void CLOCK_AttachClk(clock_attach_id_t connection)
111{
112 uint8_t mux;
113 uint8_t sel;
114 uint16_t item;
115 uint32_t tmp32 = (uint32_t)connection;
116 uint32_t i;
117 volatile uint32_t *pClkSel;
118
119 pClkSel = &(SYSCON->SYSTICKCLKSELX[0]);
120
121 if (kNONE_to_NONE != connection)
122 {
123 for (i = 0U; i < 2U; i++)
124 {
125 if (tmp32 == 0U)
126 {
127 break;
128 }
129 item = (uint16_t)GET_ID_ITEM(tmp32);
130 if (item != 0U)
131 {
132 mux = (uint8_t)GET_ID_ITEM_MUX(item);
133 sel = (uint8_t)GET_ID_ITEM_SEL(item);
134 if (mux == CM_RTCOSC32KCLKSEL)
135 {
136 PMC->RTCOSC32K = (PMC->RTCOSC32K & ~PMC_RTCOSC32K_SEL_MASK) | PMC_RTCOSC32K_SEL(sel);
137 }
138 else if (mux == CM_OSTIMERCLKSEL)
139 {
140 PMC->OSTIMERr = (PMC->OSTIMERr & ~PMC_OSTIMER_OSTIMERCLKSEL_MASK) | PMC_OSTIMER_OSTIMERCLKSEL(sel);
141 }
142 else
143 {
144 pClkSel[mux] = sel;
145 }
146 }
147 tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */
148 }
149 }
150}
151
152/* Return the actual clock attach id */
153/**
154 * brief Get the actual clock attach id.
155 * This fuction uses the offset in input attach id, then it reads the actual source value in
156 * the register and combine the offset to obtain an actual attach id.
157 * param attachId : Clock attach id to get.
158 * return Clock source value.
159 */
160clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId)
161{
162 uint8_t mux;
163 uint32_t actualSel;
164 uint32_t tmp32 = (uint32_t)attachId;
165 uint32_t i;
166 uint32_t actualAttachId = 0U;
167 uint32_t selector = GET_ID_SELECTOR(tmp32);
168 volatile uint32_t *pClkSel;
169
170 pClkSel = &(SYSCON->SYSTICKCLKSELX[0]);
171
172 if (kNONE_to_NONE == attachId)
173 {
174 return kNONE_to_NONE;
175 }
176
177 for (i = 0U; i < 2U; i++)
178 {
179 mux = (uint8_t)GET_ID_ITEM_MUX(tmp32);
180 if (tmp32 != 0UL)
181 {
182 if (mux == CM_RTCOSC32KCLKSEL)
183 {
184 actualSel = ((PMC->RTCOSC32K) & PMC_RTCOSC32K_SEL_MASK) >> PMC_RTCOSC32K_SEL_SHIFT;
185 }
186 else if (mux == CM_OSTIMERCLKSEL)
187 {
188 actualSel = ((PMC->OSTIMERr) & PMC_OSTIMER_OSTIMERCLKSEL_MASK) >> PMC_OSTIMER_OSTIMERCLKSEL_SHIFT;
189 }
190 else
191 {
192 actualSel = pClkSel[mux];
193 }
194
195 /* Consider the combination of two registers */
196 actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i);
197 }
198 tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */
199 }
200
201 actualAttachId |= selector;
202
203 return (clock_attach_id_t)actualAttachId;
204}
205
206/* Set IP Clock Divider */
207/**
208 * brief Setup peripheral clock dividers.
209 * param div_name : Clock divider name
210 * param divided_by_value: Value to be divided
211 * param reset : Whether to reset the divider counter.
212 * return Nothing
213 */
214void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset)
215{
216 volatile uint32_t *pClkDiv;
217
218 pClkDiv = &(SYSCON->SYSTICKCLKDIV0);
219 if ((div_name >= kCLOCK_DivFlexFrg0) && (div_name <= kCLOCK_DivFlexFrg7))
220 {
221 /*!< Flexcomm Interface function clock = (clock selected via FCCLKSEL) / (1+ MULT /DIV), DIV = 0xFF */
222 ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] =
223 SYSCON_FLEXFRG0CTRL_DIV_MASK | SYSCON_FLEXFRG0CTRL_MULT(divided_by_value);
224 }
225 else
226 {
227 if (reset)
228 {
229 ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = 1UL << 29U;
230 }
231 if (divided_by_value == 0U) /*!< halt */
232 {
233 ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = 1UL << 30U;
234 }
235 else
236 {
237 ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = (divided_by_value - 1U);
238 }
239 }
240}
241
242/* Set RTC 1KHz Clock Divider */
243/**
244 * brief Setup rtc 1khz clock divider.
245 * param divided_by_value: Value to be divided
246 * return Nothing
247 */
248void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value)
249{
250 PMC->RTCOSC32K =
251 (PMC->RTCOSC32K & ~PMC_RTCOSC32K_CLK1KHZDIV_MASK) | PMC_RTCOSC32K_CLK1KHZDIV(divided_by_value - 28U);
252}
253
254/* Set RTC 1KHz Clock Divider */
255/**
256 * brief Setup rtc 1hz clock divider.
257 * param divided_by_value: Value to be divided
258 * return Nothing
259 */
260void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value)
261{
262 if (divided_by_value == 0U) /*!< halt */
263 {
264 PMC->RTCOSC32K |= (1UL << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT);
265 }
266 else
267 {
268 PMC->RTCOSC32K =
269 (PMC->RTCOSC32K & ~PMC_RTCOSC32K_CLK1HZDIV_MASK) | PMC_RTCOSC32K_CLK1HZDIV(divided_by_value - 31744U);
270 }
271}
272
273/* Set FRO Clocking */
274/**
275 * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
276 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
277 * enabled.
278 * param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ)
279 * return returns success or fail status.
280 */
281status_t CLOCK_SetupFROClocking(uint32_t iFreq)
282{
283 if ((iFreq != 12000000U) && (iFreq != 96000000U))
284 {
285 return kStatus_Fail;
286 }
287 /* Enable Analog Control module */
288 SYSCON->PRESETCTRLCLR[2] = (1UL << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT);
289 SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK;
290 /* Power up the FRO192M */
291 POWER_DisablePD(kPDRUNCFG_PD_FRO192M);
292
293 if (iFreq == 96000000U)
294 {
295 ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(1);
296 }
297 /* always enable
298 else if (iFreq == 48000000U)
299 {
300 ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(1);
301 }*/
302 else
303 {
304 ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(1);
305 }
306 return kStatus_Success;
307}
308
309/* Set the FLASH wait states for the passed frequency */
310/**
311 * brief Set the flash wait states for the input freuqency.
312 * param iFreq: Input frequency
313 * return Nothing
314 */
315typedef struct
316{
317 uint32_t waitstate;
318 uint32_t freqMax;
319} WaitStateInterval_t;
320
321/* Wait state if frequency is inferior to the one specified */
322static const WaitStateInterval_t IntervalList[] = {
323 {0, 11000000}, {1, 22000000}, {2, 33000000},
324 {3, 44000000}, {4, 55000000}, {5, 66000000},
325 {6, 84000000}, {7, 104000000}, {8, 119000000},
326 {9, 129000000}, {10, 144000000}, {11, 150000000} /* Maximum allowed frequency (150 MHz) */
327};
328
329void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz)
330{
331 /* Flash Controller & FMC internal number of Wait States (minus 1) */
332 uint32_t num_wait_states = 15UL; /* Default to the maximum number of wait states */
333
334 for (size_t cnt = 0; cnt < (sizeof(IntervalList) / sizeof(WaitStateInterval_t)); cnt++)
335 {
336 if (system_freq_hz <= IntervalList[cnt].freqMax)
337 {
338 num_wait_states = IntervalList[cnt].waitstate;
339 break;
340 }
341 }
342
343 FLASH->INT_CLR_STATUS = 0x1F; /* Clear all status flags */
344
345 FLASH->DATAW[0] = (FLASH->DATAW[0] & 0xFFFFFFF0UL) |
346 (num_wait_states & (SYSCON_FMCCR_FLASHTIM_MASK >> SYSCON_FMCCR_FLASHTIM_SHIFT));
347
348 FLASH->CMD = 0x2; /* CMD_SET_READ_MODE */
349
350 /* Wait until the cmd is completed (without error) */
351 while ((FLASH->INT_STATUS & FLASH_INT_STATUS_DONE_MASK) == 0UL)
352 {
353 }
354
355 /* Adjust FMC waiting time cycles (num_wait_states) */
356 SYSCON->FMCCR = (SYSCON->FMCCR & ~SYSCON_FMCCR_FLASHTIM_MASK) |
357 ((num_wait_states << SYSCON_FMCCR_FLASHTIM_SHIFT) & SYSCON_FMCCR_FLASHTIM_MASK);
358}
359
360/* Set EXT OSC Clk */
361/**
362 * brief Initialize the external osc clock to given frequency.
363 * param iFreq : Desired frequency (must be equal to exact rate in Hz)
364 * return returns success or fail status.
365 */
366status_t CLOCK_SetupExtClocking(uint32_t iFreq)
367{
368 if (iFreq >= 32000000U)
369 {
370 return kStatus_Fail;
371 }
372 /* Turn on power for crystal 32 MHz */
373 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);
374 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);
375 /* Enable clock_in clock for clock module. */
376 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;
377
378 s_Ext_Clk_Freq = iFreq;
379 return kStatus_Success;
380}
381
382/* Set I2S MCLK Clk */
383/**
384 * brief Initialize the I2S MCLK clock to given frequency.
385 * param iFreq : Desired frequency (must be equal to exact rate in Hz)
386 * return returns success or fail status.
387 */
388status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq)
389{
390 s_I2S_Mclk_Freq = iFreq;
391 return kStatus_Success;
392}
393
394/* Set PLU CLKIN Clk */
395/**
396 * brief Initialize the PLU CLKIN clock to given frequency.
397 * param iFreq : Desired frequency (must be equal to exact rate in Hz)
398 * return returns success or fail status.
399 */
400status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq)
401{
402 s_PLU_ClkIn_Freq = iFreq;
403 return kStatus_Success;
404}
405
406/* Get CLOCK OUT Clk */
407/*! brief Return Frequency of ClockOut
408 * return Frequency of ClockOut
409 */
410uint32_t CLOCK_GetClockOutClkFreq(void)
411{
412 uint32_t freq = 0U;
413
414 switch (SYSCON->CLKOUTSEL)
415 {
416 case 0U:
417 freq = CLOCK_GetCoreSysClkFreq();
418 break;
419
420 case 1U:
421 freq = CLOCK_GetPll0OutFreq();
422 break;
423
424 case 2U:
425 freq = CLOCK_GetExtClkFreq();
426 break;
427
428 case 3U:
429 freq = CLOCK_GetFroHfFreq();
430 break;
431
432 case 4U:
433 freq = CLOCK_GetFro1MFreq();
434 break;
435
436 case 5U:
437 freq = CLOCK_GetPll1OutFreq();
438 break;
439
440 case 6U:
441 freq = CLOCK_GetOsc32KFreq();
442 break;
443
444 case 7U:
445 freq = 0U;
446 break;
447
448 default:
449 freq = 0U;
450 break;
451 }
452 return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U);
453}
454
455/* Get CAN Clk */
456/*! brief Return Frequency of Can Clock
457 * return Frequency of Can.
458 */
459uint32_t CLOCK_GetMCanClkFreq(void)
460{
461 uint32_t freq = 0U;
462
463 switch (SYSCON->CANCLKSEL)
464 {
465 case 0U:
466 freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CANCLKDIV & SYSCON_CANCLKDIV_DIV_MASK) + 1U);
467 break;
468 case 1U:
469 freq = CLOCK_GetFro1MFreq();
470 break;
471 case 2U:
472 freq = CLOCK_GetOsc32KFreq();
473 break;
474 case 7U:
475 freq = 0U;
476 break;
477
478 default:
479 freq = 0U;
480 break;
481 }
482
483 return freq;
484}
485
486/* Get ADC Clk */
487/*! brief Return Frequency of Adc Clock
488 * return Frequency of Adc.
489 */
490uint32_t CLOCK_GetAdcClkFreq(void)
491{
492 uint32_t freq = 0U;
493
494 switch (SYSCON->ADCCLKSEL)
495 {
496 case 0U:
497 freq = CLOCK_GetCoreSysClkFreq();
498 break;
499 case 1U:
500 freq = CLOCK_GetPll0OutFreq();
501 break;
502 case 2U:
503 freq = CLOCK_GetFroHfFreq();
504 break;
505 case 7U:
506 freq = 0U;
507 break;
508
509 default:
510 freq = 0U;
511 break;
512 }
513
514 return freq / ((SYSCON->ADCCLKDIV & SYSCON_ADCCLKDIV_DIV_MASK) + 1U);
515}
516
517/* Get USB0 Clk */
518/*! brief Return Frequency of Usb0 Clock
519 * return Frequency of Usb0 Clock.
520 */
521uint32_t CLOCK_GetUsb0ClkFreq(void)
522{
523 uint32_t freq = 0U;
524
525 switch (SYSCON->USB0CLKSEL)
526 {
527 case 0U:
528 freq = CLOCK_GetCoreSysClkFreq();
529 break;
530 case 1U:
531 freq = CLOCK_GetPll0OutFreq();
532 break;
533 case 3U:
534 freq = CLOCK_GetFroHfFreq();
535 break;
536 case 5U:
537 freq = CLOCK_GetPll1OutFreq();
538 break;
539 case 7U:
540 freq = 0U;
541 break;
542
543 default:
544 freq = 0U;
545 break;
546 }
547
548 return freq / ((SYSCON->USB0CLKDIV & 0xffU) + 1U);
549}
550
551/* Get USB1 Clk */
552/*! brief Return Frequency of Usb1 Clock
553 * return Frequency of Usb1 Clock.
554 */
555uint32_t CLOCK_GetUsb1ClkFreq(void)
556{
557 return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U;
558}
559
560/* Get MCLK Clk */
561/*! brief Return Frequency of MClk Clock
562 * return Frequency of MClk Clock.
563 */
564uint32_t CLOCK_GetMclkClkFreq(void)
565{
566 uint32_t freq = 0U;
567
568 switch (SYSCON->MCLKCLKSEL)
569 {
570 case 0U:
571 freq = CLOCK_GetFroHfFreq();
572 break;
573 case 1U:
574 freq = CLOCK_GetPll0OutFreq();
575 break;
576 case 7U:
577 freq = 0U;
578 break;
579
580 default:
581 freq = 0U;
582 break;
583 }
584
585 return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U);
586}
587
588/* Get SCTIMER Clk */
589/*! brief Return Frequency of SCTimer Clock
590 * return Frequency of SCTimer Clock.
591 */
592uint32_t CLOCK_GetSctClkFreq(void)
593{
594 uint32_t freq = 0U;
595
596 switch (SYSCON->SCTCLKSEL)
597 {
598 case 0U:
599 freq = CLOCK_GetCoreSysClkFreq();
600 break;
601 case 1U:
602 freq = CLOCK_GetPll0OutFreq();
603 break;
604 case 2U:
605 freq = CLOCK_GetExtClkFreq();
606 break;
607 case 3U:
608 freq = CLOCK_GetFroHfFreq();
609 break;
610 case 5U:
611 freq = CLOCK_GetI2SMClkFreq();
612 break;
613 case 7U:
614 freq = 0U;
615 break;
616
617 default:
618 freq = 0U;
619 break;
620 }
621
622 return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U);
623}
624
625/* Get FRO 12M Clk */
626/*! brief Return Frequency of FRO 12MHz
627 * return Frequency of FRO 12MHz
628 */
629uint32_t CLOCK_GetFro12MFreq(void)
630{
631 return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U;
632}
633
634/* Get FRO 1M Clk */
635/*! brief Return Frequency of FRO 1MHz
636 * return Frequency of FRO 1MHz
637 */
638uint32_t CLOCK_GetFro1MFreq(void)
639{
640 return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U;
641}
642
643/* Get EXT OSC Clk */
644/*! brief Return Frequency of External Clock
645 * return Frequency of External Clock. If no external clock is used returns 0.
646 */
647uint32_t CLOCK_GetExtClkFreq(void)
648{
649 return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U;
650}
651
652/* Get WATCH DOG Clk */
653/*! brief Return Frequency of Watchdog
654 * return Frequency of Watchdog
655 */
656uint32_t CLOCK_GetWdtClkFreq(void)
657{
658 return CLOCK_GetFro1MFreq() / ((SYSCON->WDTCLKDIV & SYSCON_WDTCLKDIV_DIV_MASK) + 1U);
659}
660
661/* Get HF FRO Clk */
662/*! brief Return Frequency of High-Freq output of FRO
663 * return Frequency of High-Freq output of FRO
664 */
665uint32_t CLOCK_GetFroHfFreq(void)
666{
667 return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U;
668}
669
670/* Get SYSTEM PLL Clk */
671/*! brief Return Frequency of PLL
672 * return Frequency of PLL
673 */
674uint32_t CLOCK_GetPll0OutFreq(void)
675{
676 return s_Pll0_Freq;
677}
678
679/* Get USB PLL Clk */
680/*! brief Return Frequency of USB PLL
681 * return Frequency of PLL
682 */
683uint32_t CLOCK_GetPll1OutFreq(void)
684{
685 return s_Pll1_Freq;
686}
687
688/* Get RTC OSC Clk */
689/*! brief Return Frequency of 32kHz osc
690 * return Frequency of 32kHz osc
691 */
692uint32_t CLOCK_GetOsc32KFreq(void)
693{
694 return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) &&
695 (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ?
696 CLK_RTC_32K_CLK :
697 ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) &&
698 ((PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK) != 0UL)) ?
699 CLK_RTC_32K_CLK :
700 0UL;
701}
702
703/* Get MAIN Clk */
704/*! brief Return Frequency of Core System
705 * return Frequency of Core System
706 */
707uint32_t CLOCK_GetCoreSysClkFreq(void)
708{
709 uint32_t freq = 0U;
710
711 switch (SYSCON->MAINCLKSELB)
712 {
713 case 0U:
714 if (SYSCON->MAINCLKSELA == 0U)
715 {
716 freq = CLOCK_GetFro12MFreq();
717 }
718 else if (SYSCON->MAINCLKSELA == 1U)
719 {
720 freq = CLOCK_GetExtClkFreq();
721 }
722 else if (SYSCON->MAINCLKSELA == 2U)
723 {
724 freq = CLOCK_GetFro1MFreq();
725 }
726 else if (SYSCON->MAINCLKSELA == 3U)
727 {
728 freq = CLOCK_GetFroHfFreq();
729 }
730 else
731 {
732 /* Added comments to avoid the violation of MISRA C-2012 rule 15.7 */
733 }
734 break;
735 case 1U:
736 freq = CLOCK_GetPll0OutFreq();
737 break;
738 case 2U:
739 freq = CLOCK_GetPll1OutFreq();
740 break;
741
742 case 3U:
743 freq = CLOCK_GetOsc32KFreq();
744 break;
745
746 default:
747 freq = 0U;
748 break;
749 }
750
751 return freq;
752}
753
754/* Get I2S MCLK Clk */
755/*! brief Return Frequency of I2S MCLK Clock
756 * return Frequency of I2S MCLK Clock
757 */
758uint32_t CLOCK_GetI2SMClkFreq(void)
759{
760 return s_I2S_Mclk_Freq;
761}
762
763/* Get PLU CLKIN Clk */
764/*! brief Return Frequency of PLU CLKIN Clock
765 * return Frequency of PLU CLKIN Clock
766 */
767uint32_t CLOCK_GetPLUClkInFreq(void)
768{
769 return s_PLU_ClkIn_Freq;
770}
771
772/* Get FLEXCOMM input clock */
773/*! brief Return Frequency of flexcomm input clock
774 * param id : flexcomm instance id
775 * return Frequency value
776 */
777uint32_t CLOCK_GetFlexCommInputClock(uint32_t id)
778{
779 uint32_t freq = 0U;
780
781 switch (SYSCON->FCCLKSELX[id])
782 {
783 case 0U:
784 freq = CLOCK_GetCoreSysClkFreq();
785 break;
786 case 1U:
787 freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U);
788 break;
789 case 2U:
790 freq = CLOCK_GetFro12MFreq();
791 break;
792 case 3U:
793 freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U);
794 break;
795 case 4U:
796 freq = CLOCK_GetFro1MFreq();
797 break;
798 case 5U:
799 freq = CLOCK_GetI2SMClkFreq();
800 break;
801 case 6U:
802 freq = CLOCK_GetOsc32KFreq();
803 break;
804 case 7U:
805 freq = 0U;
806 break;
807
808 default:
809 freq = 0U;
810 break;
811 }
812
813 return freq;
814}
815
816/* Get FLEXCOMM Clk */
817uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id)
818{
819 uint32_t freq = 0U;
820
821 freq = CLOCK_GetFlexCommInputClock(id);
822 return freq / (1UL + (SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK) /
823 ((SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK) + 1UL));
824}
825
826/* Get HS_LPSI Clk */
827uint32_t CLOCK_GetHsLspiClkFreq(void)
828{
829 uint32_t freq = 0U;
830
831 switch (SYSCON->HSLSPICLKSEL)
832 {
833 case 0U:
834 freq = CLOCK_GetCoreSysClkFreq();
835 break;
836 case 1U:
837 freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U);
838 break;
839 case 2U:
840 freq = CLOCK_GetFro12MFreq();
841 break;
842 case 3U:
843 freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U);
844 break;
845 case 4U:
846 freq = CLOCK_GetFro1MFreq();
847 break;
848 case 6U:
849 freq = CLOCK_GetOsc32KFreq();
850 break;
851 case 7U:
852 freq = 0U;
853 break;
854
855 default:
856 freq = 0U;
857 break;
858 }
859
860 return freq;
861}
862
863/* Get CTimer Clk */
864/*! brief Return Frequency of CTimer functional Clock
865 * return Frequency of CTimer functional Clock
866 */
867uint32_t CLOCK_GetCTimerClkFreq(uint32_t id)
868{
869 uint32_t freq = 0U;
870
871 switch (SYSCON->CTIMERCLKSELX[id])
872 {
873 case 0U:
874 freq = CLOCK_GetCoreSysClkFreq();
875 break;
876 case 1U:
877 freq = CLOCK_GetPll0OutFreq();
878 break;
879 case 3U:
880 freq = CLOCK_GetFroHfFreq();
881 break;
882 case 4U:
883 freq = CLOCK_GetFro1MFreq();
884 break;
885 case 5U:
886 freq = CLOCK_GetI2SMClkFreq();
887 break;
888 case 6U:
889 freq = CLOCK_GetOsc32KFreq();
890 break;
891 case 7U:
892 freq = 0U;
893 break;
894
895 default:
896 freq = 0U;
897 break;
898 }
899
900 return freq;
901}
902
903/* Get Systick Clk */
904/*! brief Return Frequency of SystickClock
905 * return Frequency of Systick Clock
906 */
907uint32_t CLOCK_GetSystickClkFreq(uint32_t id)
908{
909 uint32_t freq = 0U;
910
911 switch (SYSCON->SYSTICKCLKSELX[id])
912 {
913 case 0U:
914 /*Niobe4mini just has one SYSTICKSEL and SYSTICKDIV register, Fix coverity problem in this way temporarily
915 */
916 freq = CLOCK_GetCoreSysClkFreq() / (((SYSCON->SYSTICKCLKDIV0) & 0xffU) + 1U);
917 break;
918 case 1U:
919 freq = CLOCK_GetFro1MFreq();
920 break;
921 case 2U:
922 freq = CLOCK_GetOsc32KFreq();
923 break;
924 case 7U:
925 freq = 0U;
926 break;
927
928 default:
929 freq = 0U;
930 break;
931 }
932
933 return freq;
934}
935
936/* Set FlexComm Clock */
937/**
938 * brief Set the flexcomm output frequency.
939 * param id : flexcomm instance id
940 * freq : output frequency
941 * return 0 : the frequency range is out of range.
942 * 1 : switch successfully.
943 */
944uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq)
945{
946 uint32_t input = CLOCK_GetFlexCommClkFreq(id);
947 uint32_t mul;
948
949 if ((freq > 48000000UL) || (freq > input) || (input / freq >= 2UL))
950 {
951 /* FRG output frequency should be less than equal to 48MHz */
952 return 0UL;
953 }
954 else
955 {
956 mul = (uint32_t)((((uint64_t)input - freq) * 256ULL) / ((uint64_t)freq));
957 SYSCON->FLEXFRGXCTRL[id] = (mul << 8U) | 0xFFU;
958 return 1UL;
959 }
960}
961
962/* Get IP Clk */
963/*! brief Return Frequency of selected clock
964 * return Frequency of selected clock
965 */
966uint32_t CLOCK_GetFreq(clock_name_t clockName)
967{
968 uint32_t freq;
969 switch (clockName)
970 {
971 case kCLOCK_CoreSysClk:
972 freq = CLOCK_GetCoreSysClkFreq();
973 break;
974 case kCLOCK_BusClk:
975 freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
976 break;
977 case kCLOCK_ClockOut:
978 freq = CLOCK_GetClockOutClkFreq();
979 break;
980 case kCLOCK_Pll1Out:
981 freq = CLOCK_GetPll1OutFreq();
982 break;
983 case kCLOCK_Mclk:
984 freq = CLOCK_GetMclkClkFreq();
985 break;
986 case kCLOCK_FroHf:
987 freq = CLOCK_GetFroHfFreq();
988 break;
989 case kCLOCK_Fro12M:
990 freq = CLOCK_GetFro12MFreq();
991 break;
992 case kCLOCK_Fro1M:
993 freq = CLOCK_GetFro1MFreq();
994 break;
995 case kCLOCK_ExtClk:
996 freq = CLOCK_GetExtClkFreq();
997 break;
998 case kCLOCK_Pll0Out:
999 freq = CLOCK_GetPll0OutFreq();
1000 break;
1001 case kCLOCK_FlexI2S:
1002 freq = CLOCK_GetI2SMClkFreq();
1003 break;
1004 default:
1005 freq = 0U;
1006 break;
1007 }
1008 return freq;
1009}
1010
1011/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */
1012static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR)
1013{
1014 uint32_t seli, selp;
1015 /* bandwidth: compute selP from Multiplier */
1016 if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */
1017 {
1018 selp = (M >> 2U) + 1U;
1019 if (selp >= 31U)
1020 {
1021 selp = 31U;
1022 }
1023 *pSelP = selp;
1024
1025 if (M >= 8000UL)
1026 {
1027 seli = 1UL;
1028 }
1029 else if (M >= 122UL)
1030 {
1031 seli = (uint32_t)(8000UL / M); /*floor(8000/M) */
1032 }
1033 else
1034 {
1035 seli = 2UL * ((uint32_t)(M / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */
1036 }
1037
1038 if (seli >= 63UL)
1039 {
1040 seli = 63UL;
1041 }
1042 *pSelI = seli;
1043
1044 *pSelR = 0UL;
1045 }
1046 else
1047 {
1048 /* Note: If the spread spectrum mode, choose N to ensure 3 MHz < Fin/N < 5 MHz */
1049 *pSelP = 3U;
1050 *pSelI = 4U;
1051 *pSelR = 4U;
1052 }
1053}
1054
1055/* Get predivider (N) from PLL0 NDEC setting */
1056static uint32_t findPll0PreDiv(void)
1057{
1058 uint32_t preDiv = 1UL;
1059
1060 /* Direct input is not used? */
1061 if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL)
1062 {
1063 preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK;
1064 if (preDiv == 0UL)
1065 {
1066 preDiv = 1UL;
1067 }
1068 }
1069 return preDiv;
1070}
1071
1072/* Get predivider (N) from PLL1 NDEC setting */
1073static uint32_t findPll1PreDiv(void)
1074{
1075 uint32_t preDiv = 1UL;
1076
1077 /* Direct input is not used? */
1078 if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL)
1079 {
1080 preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK;
1081 if (preDiv == 0UL)
1082 {
1083 preDiv = 1UL;
1084 }
1085 }
1086 return preDiv;
1087}
1088
1089/* Get postdivider (P) from PLL0 PDEC setting */
1090static uint32_t findPll0PostDiv(void)
1091{
1092 uint32_t postDiv = 1UL;
1093
1094 if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL)
1095 {
1096 if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL)
1097 {
1098 postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK;
1099 }
1100 else
1101 {
1102 postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK);
1103 }
1104 if (postDiv == 0UL)
1105 {
1106 postDiv = 2UL;
1107 }
1108 }
1109 return postDiv;
1110}
1111
1112/* Get postdivider (P) from PLL1 PDEC setting. */
1113static uint32_t findPll1PostDiv(void)
1114{
1115 uint32_t postDiv = 1UL;
1116
1117 if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0UL)
1118 {
1119 if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) != 0UL)
1120 {
1121 postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK;
1122 }
1123 else
1124 {
1125 postDiv = 2UL * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK);
1126 }
1127 if (postDiv == 0UL)
1128 {
1129 postDiv = 2UL;
1130 }
1131 }
1132
1133 return postDiv;
1134}
1135
1136/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */
1137static float findPll0MMult(void)
1138{
1139 float mMult = 1.0F;
1140 float mMult_fract;
1141 uint32_t mMult_int;
1142
1143 if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL)
1144 {
1145 mMult =
1146 (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT);
1147 }
1148 else
1149 {
1150 mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U);
1151 mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P);
1152 mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M) /
1153 (float)(uint32_t)(1UL << PLL0_SSCG_MD_INT_P));
1154 mMult = (float)mMult_int + mMult_fract;
1155 }
1156 if (mMult == 0.0F)
1157 {
1158 mMult = 1.0F;
1159 }
1160 return mMult;
1161}
1162
1163/* Get multiplier (M) from PLL1 MDEC. */
1164static uint32_t findPll1MMult(void)
1165{
1166 uint32_t mMult = 1UL;
1167
1168 mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK;
1169
1170 if (mMult == 0UL)
1171 {
1172 mMult = 1UL;
1173 }
1174
1175 return mMult;
1176}
1177
1178/* Find greatest common divisor between m and n */
1179static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n)
1180{
1181 uint32_t tmp;
1182
1183 while (n != 0U)
1184 {
1185 tmp = n;
1186 n = m % n;
1187 m = tmp;
1188 }
1189
1190 return m;
1191}
1192
1193/*
1194 * Set PLL0 output based on desired output rate.
1195 * In this function, the it calculates the PLL0 setting for output frequency from input clock
1196 * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently.
1197 * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function.
1198 */
1199static pll_error_t CLOCK_GetPll0ConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS)
1200{
1201 uint32_t nDivOutHz, fccoHz;
1202 uint32_t pllPreDivider, pllMultiplier, pllPostDivider;
1203 uint32_t pllDirectInput, pllDirectOutput;
1204 uint32_t pllSelP, pllSelI, pllSelR, uplimoff;
1205
1206 /* Baseline parameters (no input or output dividers) */
1207 pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */
1208 pllPostDivider = 1U; /* 1 implies post-divider will be disabled */
1209 pllDirectOutput = 1U;
1210
1211 /* Verify output rate parameter */
1212 if (foutHz > PLL_MAX_CCO_FREQ_MHZ)
1213 {
1214 /* Maximum PLL output with post divider=1 cannot go above this frequency */
1215 return kStatus_PLL_OutputTooHigh;
1216 }
1217 if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U)))
1218 {
1219 /* Minmum PLL output with maximum post divider cannot go below this frequency */
1220 return kStatus_PLL_OutputTooLow;
1221 }
1222
1223 /* If using SS mode, input clock needs to be between 3MHz and 20MHz */
1224 if (useSS)
1225 {
1226 /* Verify input rate parameter */
1227 if (finHz < PLL_MIN_IN_SSMODE)
1228 {
1229 /* Input clock into the PLL cannot be lower than this */
1230 return kStatus_PLL_InputTooLow;
1231 }
1232 /* PLL input in SS mode must be under 20MHz */
1233 if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX))
1234 {
1235 return kStatus_PLL_InputTooHigh;
1236 }
1237 }
1238 else
1239 {
1240 /* Verify input rate parameter */
1241 if (finHz < PLL_LOWER_IN_LIMIT)
1242 {
1243 /* Input clock into the PLL cannot be lower than this */
1244 return kStatus_PLL_InputTooLow;
1245 }
1246 if (finHz > PLL_HIGHER_IN_LIMIT)
1247 {
1248 /* Input clock into the PLL cannot be higher than this */
1249 return kStatus_PLL_InputTooHigh;
1250 }
1251 }
1252
1253 /* Find the optimal CCO frequency for the output and input that
1254 will keep it inside the PLL CCO range. This may require
1255 tweaking the post-divider for the PLL. */
1256 fccoHz = foutHz;
1257 while (fccoHz < PLL_MIN_CCO_FREQ_MHZ)
1258 {
1259 /* CCO output is less than minimum CCO range, so the CCO output
1260 needs to be bumped up and the post-divider is used to bring
1261 the PLL output back down. */
1262 pllPostDivider++;
1263 if (pllPostDivider > PVALMAX)
1264 {
1265 return kStatus_PLL_OutsideIntLimit;
1266 }
1267
1268 /* Target CCO goes up, PLL output goes down */
1269 /* divide-by-2 divider in the post-divider is always work*/
1270 fccoHz = foutHz * (pllPostDivider * 2U);
1271 pllDirectOutput = 0U;
1272 }
1273
1274 /* Determine if a pre-divider is needed to get the best frequency */
1275 if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false))
1276 {
1277 uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz);
1278
1279 if (a > PLL_LOWER_IN_LIMIT)
1280 {
1281 a = finHz / a;
1282 if ((a != 0U) && (a < PLL_MAX_N_DIV))
1283 {
1284 pllPreDivider = a;
1285 }
1286 }
1287 }
1288
1289 /* Bypass pre-divider hardware if pre-divider is 1 */
1290 if (pllPreDivider > 1U)
1291 {
1292 pllDirectInput = 0U;
1293 }
1294 else
1295 {
1296 pllDirectInput = 1U;
1297 }
1298
1299 /* Determine PLL multipler */
1300 nDivOutHz = (finHz / pllPreDivider);
1301 pllMultiplier = (fccoHz / nDivOutHz);
1302
1303 /* Find optimal values for filter */
1304 if (useSS == false)
1305 {
1306 /* Will bumping up M by 1 get us closer to the desired CCO frequency? */
1307 if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U))
1308 {
1309 pllMultiplier++;
1310 }
1311
1312 /* Setup filtering */
1313 pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR);
1314 uplimoff = 0U;
1315
1316 /* Get encoded value for M (mult) and use manual filter, disable SS mode */
1317 pSetup->pllsscg[1] =
1318 (uint32_t)((PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1UL << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT));
1319 }
1320 else
1321 {
1322 uint64_t fc;
1323
1324 /* Filtering will be handled by SSC */
1325 pllSelR = 0UL;
1326 pllSelI = 0UL;
1327 pllSelP = 0UL;
1328 uplimoff = 1U;
1329
1330 /* The PLL multiplier will get very close and slightly under the
1331 desired target frequency. A small fractional component can be
1332 added to fine tune the frequency upwards to the target. */
1333 fc = ((uint64_t)(uint32_t)(fccoHz % nDivOutHz) << 25UL) / nDivOutHz;
1334
1335 /* Set multiplier */
1336 pSetup->pllsscg[0] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) | PLL0_SSCG_MD_FRACT_SET((uint32_t)fc));
1337 pSetup->pllsscg[1] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U);
1338 }
1339
1340 /* Get encoded values for N (prediv) and P (postdiv) */
1341 pSetup->pllndec = PLL_NDEC_VAL_SET(pllPreDivider);
1342 pSetup->pllpdec = PLL_PDEC_VAL_SET(pllPostDivider);
1343
1344 /* PLL control */
1345 pSetup->pllctrl = (pllSelR << SYSCON_PLL0CTRL_SELR_SHIFT) | /* Filter coefficient */
1346 (pllSelI << SYSCON_PLL0CTRL_SELI_SHIFT) | /* Filter coefficient */
1347 (pllSelP << SYSCON_PLL0CTRL_SELP_SHIFT) | /* Filter coefficient */
1348 (0UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */
1349 (uplimoff << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */
1350 (pllDirectInput << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */
1351 (pllDirectOutput << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT) | /* Bypass post-divider? */
1352 (1UL << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */
1353
1354 return kStatus_PLL_Success;
1355}
1356
1357#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
1358/* Alloct the static buffer for cache. */
1359static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT];
1360static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};
1361static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};
1362static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false};
1363static uint32_t s_PllSetupCacheIdx = 0U;
1364#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
1365
1366/*
1367 * Calculate the PLL setting values from input clock freq to output freq.
1368 */
1369static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS)
1370{
1371 pll_error_t retErr;
1372#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
1373 uint32_t i;
1374
1375 for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++)
1376 {
1377 if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i]))
1378 {
1379 /* Hit the target in cache buffer. */
1380 pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl;
1381 pSetup->pllndec = s_PllSetupCacheStruct[i].pllndec;
1382 pSetup->pllpdec = s_PllSetupCacheStruct[i].pllpdec;
1383 pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0];
1384 pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1];
1385 retErr = kStatus_PLL_Success;
1386 break;
1387 }
1388 }
1389
1390 if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
1391 {
1392 return retErr;
1393 }
1394#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
1395
1396 retErr = CLOCK_GetPll0ConfigInternal(finHz, foutHz, pSetup, useSS);
1397
1398#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
1399 /* Cache the most recent calulation result into buffer. */
1400 s_FinHzCache[s_PllSetupCacheIdx] = finHz;
1401 s_FoutHzCache[s_PllSetupCacheIdx] = foutHz;
1402 s_UseSSCache[s_PllSetupCacheIdx] = useSS;
1403
1404 s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl;
1405 s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndec = pSetup->pllndec;
1406 s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdec = pSetup->pllpdec;
1407 s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0];
1408 s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1];
1409 /* Update the index for next available buffer. */
1410 s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT;
1411#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
1412
1413 return retErr;
1414}
1415
1416/* Update local PLL rate variable */
1417static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup)
1418{
1419 s_Pll0_Freq = CLOCK_GetPLL0OutFromSetup(pSetup);
1420}
1421
1422/* Update local PLL1 rate variable */
1423static void CLOCK_GetPLL1OutFromSetupUpdate(pll_setup_t *pSetup)
1424{
1425 s_Pll1_Freq = CLOCK_GetPLL1OutFromSetup(pSetup);
1426}
1427
1428/* Return System PLL input clock rate */
1429/*! brief Return PLL0 input clock rate
1430 * return PLL0 input clock rate
1431 */
1432uint32_t CLOCK_GetPLL0InClockRate(void)
1433{
1434 uint32_t clkRate = 0U;
1435
1436 switch ((SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK))
1437 {
1438 case 0x00U:
1439 clkRate = CLK_FRO_12MHZ;
1440 break;
1441
1442 case 0x01U:
1443 clkRate = CLOCK_GetExtClkFreq();
1444 break;
1445
1446 case 0x02U:
1447 clkRate = CLOCK_GetFro1MFreq();
1448 break;
1449
1450 case 0x03U:
1451 clkRate = CLOCK_GetOsc32KFreq();
1452 break;
1453
1454 default:
1455 clkRate = 0U;
1456 break;
1457 }
1458
1459 return clkRate;
1460}
1461
1462/* Return PLL1 input clock rate */
1463uint32_t CLOCK_GetPLL1InClockRate(void)
1464{
1465 uint32_t clkRate = 0U;
1466
1467 switch ((SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK))
1468 {
1469 case 0x00U:
1470 clkRate = CLK_FRO_12MHZ;
1471 break;
1472
1473 case 0x01U:
1474 clkRate = CLOCK_GetExtClkFreq();
1475 break;
1476
1477 case 0x02U:
1478 clkRate = CLOCK_GetFro1MFreq();
1479 break;
1480
1481 case 0x03U:
1482 clkRate = CLOCK_GetOsc32KFreq();
1483 break;
1484
1485 default:
1486 clkRate = 0U;
1487 break;
1488 }
1489
1490 return clkRate;
1491}
1492
1493/* Return PLL0 output clock rate from setup structure */
1494/*! brief Return PLL0 output clock rate from setup structure
1495 * param pSetup : Pointer to a PLL setup structure
1496 * return PLL0 output clock rate the setup structure will generate
1497 */
1498uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup)
1499{
1500 uint32_t clkRate = 0;
1501 uint32_t prediv, postdiv;
1502 float workRate = 0.0F;
1503
1504 /* Get the input clock frequency of PLL. */
1505 clkRate = CLOCK_GetPLL0InClockRate();
1506
1507 if (((pSetup->pllctrl & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) &&
1508 ((pSetup->pllctrl & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) &&
1509 ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) &&
1510 ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL))
1511 {
1512 prediv = findPll0PreDiv();
1513 postdiv = findPll0PostDiv();
1514 /* Adjust input clock */
1515 clkRate = clkRate / prediv;
1516 /* MDEC used for rate */
1517 workRate = (float)clkRate * (float)findPll0MMult();
1518 workRate /= (float)postdiv;
1519 }
1520
1521 return (uint32_t)workRate;
1522}
1523
1524/* Return PLL1 output clock rate from setup structure */
1525/*! brief Return PLL1 output clock rate from setup structure
1526 * param pSetup : Pointer to a PLL setup structure
1527 * return PLL0 output clock rate the setup structure will generate
1528 */
1529uint32_t CLOCK_GetPLL1OutFromSetup(pll_setup_t *pSetup)
1530{
1531 uint32_t clkRate = 0;
1532 uint32_t prediv, postdiv;
1533 uint32_t workRate = 0UL;
1534
1535 /* Get the input clock frequency of PLL. */
1536 clkRate = CLOCK_GetPLL1InClockRate();
1537
1538 if (((pSetup->pllctrl & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0UL) &&
1539 ((pSetup->pllctrl & SYSCON_PLL1CTRL_CLKEN_MASK) != 0UL) &&
1540 ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0UL))
1541 {
1542 prediv = findPll1PreDiv();
1543 postdiv = findPll1PostDiv();
1544 /* Adjust input clock */
1545 clkRate = clkRate / prediv;
1546 /* MDEC used for rate */
1547 workRate = clkRate * findPll1MMult();
1548 workRate /= postdiv;
1549 }
1550
1551 return workRate;
1552}
1553
1554/* Set the current PLL0 Rate */
1555/*! brief Store the current PLL rate
1556 * param rate: Current rate of the PLL
1557 * return Nothing
1558 **/
1559void CLOCK_SetStoredPLL0ClockRate(uint32_t rate)
1560{
1561 s_Pll0_Freq = rate;
1562}
1563
1564/* Return PLL0 output clock rate */
1565/*! brief Return PLL0 output clock rate
1566 * param recompute : Forces a PLL rate recomputation if true
1567 * return PLL0 output clock rate
1568 * note The PLL rate is cached in the driver in a variable as
1569 * the rate computation function can take some time to perform. It
1570 * is recommended to use 'false' with the 'recompute' parameter.
1571 */
1572uint32_t CLOCK_GetPLL0OutClockRate(bool recompute)
1573{
1574 pll_setup_t Setup;
1575 uint32_t rate;
1576
1577 if ((recompute) || (s_Pll0_Freq == 0U))
1578 {
1579 Setup.pllctrl = SYSCON->PLL0CTRL;
1580 Setup.pllndec = SYSCON->PLL0NDEC;
1581 Setup.pllpdec = SYSCON->PLL0PDEC;
1582 Setup.pllsscg[0] = SYSCON->PLL0SSCG0;
1583 Setup.pllsscg[1] = SYSCON->PLL0SSCG1;
1584
1585 CLOCK_GetPLL0OutFromSetupUpdate(&Setup);
1586 }
1587
1588 rate = s_Pll0_Freq;
1589
1590 return rate;
1591}
1592
1593/*! brief Return PLL1 output clock rate
1594 * param recompute : Forces a PLL rate recomputation if true
1595 * return PLL1 output clock rate
1596 * note The PLL rate is cached in the driver in a variable as
1597 * the rate computation function can take some time to perform. It
1598 * is recommended to use 'false' with the 'recompute' parameter.
1599 */
1600uint32_t CLOCK_GetPLL1OutClockRate(bool recompute)
1601{
1602 pll_setup_t Setup;
1603 uint32_t rate;
1604
1605 if ((recompute) || (s_Pll1_Freq == 0U))
1606 {
1607 Setup.pllctrl = SYSCON->PLL1CTRL;
1608 Setup.pllndec = SYSCON->PLL1NDEC;
1609 Setup.pllpdec = SYSCON->PLL1PDEC;
1610 Setup.pllmdec = SYSCON->PLL1MDEC;
1611 CLOCK_GetPLL1OutFromSetupUpdate(&Setup);
1612 }
1613
1614 rate = s_Pll1_Freq;
1615
1616 return rate;
1617}
1618
1619/* Set PLL0 output based on the passed PLL setup data */
1620/*! brief Set PLL output based on the passed PLL setup data
1621 * param pControl : Pointer to populated PLL control structure to generate setup with
1622 * param pSetup : Pointer to PLL setup structure to be filled
1623 * return PLL_ERROR_SUCCESS on success, or PLL setup error code
1624 * note Actual frequency for setup may vary from the desired frequency based on the
1625 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1626 */
1627pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup)
1628{
1629 uint32_t inRate;
1630 bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0UL);
1631
1632 pll_error_t pllError;
1633
1634 /* Determine input rate for the PLL */
1635 if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0UL)
1636 {
1637 inRate = pControl->inputRate;
1638 }
1639 else
1640 {
1641 inRate = CLOCK_GetPLL0InClockRate();
1642 }
1643
1644 /* PLL flag options */
1645 pllError = CLOCK_GetPll0Config(inRate, pControl->desiredRate, pSetup, useSS);
1646 if ((useSS) && (pllError == kStatus_PLL_Success))
1647 {
1648 /* If using SS mode, then some tweaks are made to the generated setup */
1649 pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc;
1650 if (pControl->mfDither)
1651 {
1652 pSetup->pllsscg[1] |= (1UL << SYSCON_PLL0SSCG1_DITHER_SHIFT);
1653 }
1654 }
1655
1656 return pllError;
1657}
1658
1659/* Set PLL0 output from PLL setup structure */
1660/*! brief Set PLL output from PLL setup structure (precise frequency)
1661 * param pSetup : Pointer to populated PLL setup structure
1662 * param flagcfg : Flag configuration for PLL config structure
1663 * return PLL_ERROR_SUCCESS on success, or PLL setup error code
1664 * note This function will power off the PLL, setup the PLL with the
1665 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1666 * and adjust system voltages to the new PLL rate. The function will not
1667 * alter any source clocks (ie, main systen clock) that may use the PLL,
1668 * so these should be setup prior to and after exiting the function.
1669 */
1670pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg)
1671{
1672 uint32_t inRate, clkRate, prediv;
1673
1674 /* Power off PLL during setup changes */
1675 POWER_EnablePD(kPDRUNCFG_PD_PLL0);
1676 POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG);
1677
1678 pSetup->flags = flagcfg;
1679
1680 /* Write PLL setup data */
1681 SYSCON->PLL0CTRL = pSetup->pllctrl;
1682 SYSCON->PLL0NDEC = pSetup->pllndec;
1683 SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */
1684 SYSCON->PLL0PDEC = pSetup->pllpdec;
1685 SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */
1686 SYSCON->PLL0SSCG0 = pSetup->pllsscg[0];
1687 SYSCON->PLL0SSCG1 = pSetup->pllsscg[1];
1688 SYSCON->PLL0SSCG1 =
1689 pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */
1690
1691 POWER_DisablePD(kPDRUNCFG_PD_PLL0);
1692 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
1693
1694 if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0UL)
1695 {
1696 if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */
1697 {
1698 inRate = CLOCK_GetPLL0InClockRate();
1699 prediv = findPll0PreDiv();
1700 /* Adjust input clock */
1701 clkRate = inRate / prediv;
1702 /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */
1703 if ((clkRate >= 100000UL) && (clkRate <= 20000000UL))
1704 {
1705 while (CLOCK_IsPLL0Locked() == false)
1706 {
1707 }
1708 }
1709 else
1710 {
1711 SDK_DelayAtLeastUs(6000U,
1712 SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval
1713 to insure the PLL will be stable */
1714 }
1715 }
1716 else /* spread spectrum mode */
1717 {
1718 SDK_DelayAtLeastUs(6000U,
1719 SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to
1720 insure the PLL will be stable */
1721 }
1722 }
1723
1724 /* Update current programmed PLL rate var */
1725 CLOCK_GetPLL0OutFromSetupUpdate(pSetup);
1726
1727 /* System voltage adjustment, occurs prior to setting main system clock */
1728 if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0UL)
1729 {
1730 POWER_SetVoltageForFreq(s_Pll0_Freq);
1731 }
1732
1733 return kStatus_PLL_Success;
1734}
1735
1736/* Setup PLL Frequency from pre-calculated value */
1737/**
1738 * brief Set PLL0 output from PLL setup structure (precise frequency)
1739 * param pSetup : Pointer to populated PLL setup structure
1740 * return kStatus_PLL_Success on success, or PLL setup error code
1741 * note This function will power off the PLL, setup the PLL with the
1742 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1743 * and adjust system voltages to the new PLL rate. The function will not
1744 * alter any source clocks (ie, main systen clock) that may use the PLL,
1745 * so these should be setup prior to and after exiting the function.
1746 */
1747pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup)
1748{
1749 uint32_t inRate, clkRate, prediv;
1750 /* Power off PLL during setup changes */
1751 POWER_EnablePD(kPDRUNCFG_PD_PLL0);
1752 POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG);
1753
1754 /* Write PLL setup data */
1755 SYSCON->PLL0CTRL = pSetup->pllctrl;
1756 SYSCON->PLL0NDEC = pSetup->pllndec;
1757 SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */
1758 SYSCON->PLL0PDEC = pSetup->pllpdec;
1759 SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */
1760 SYSCON->PLL0SSCG0 = pSetup->pllsscg[0];
1761 SYSCON->PLL0SSCG1 = pSetup->pllsscg[1];
1762 SYSCON->PLL0SSCG1 =
1763 pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */
1764
1765 POWER_DisablePD(kPDRUNCFG_PD_PLL0);
1766 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
1767
1768 if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0UL)
1769 {
1770 if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */
1771 {
1772 inRate = CLOCK_GetPLL0InClockRate();
1773 prediv = findPll0PreDiv();
1774 /* Adjust input clock */
1775 clkRate = inRate / prediv;
1776 /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */
1777 if ((clkRate >= 100000UL) && (clkRate <= 20000000UL))
1778 {
1779 while (CLOCK_IsPLL0Locked() == false)
1780 {
1781 }
1782 }
1783 else
1784 {
1785 SDK_DelayAtLeastUs(6000U,
1786 SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval
1787 to insure the PLL will be stable */
1788 }
1789 }
1790 else /* spread spectrum mode */
1791 {
1792 SDK_DelayAtLeastUs(6000U,
1793 SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to
1794 insure the PLL will be stable */
1795 }
1796 }
1797
1798 /* Update current programmed PLL rate var */
1799 s_Pll0_Freq = pSetup->pllRate;
1800
1801 return kStatus_PLL_Success;
1802}
1803
1804/* Setup PLL1 Frequency from pre-calculated value */
1805/**
1806 * brief Set PLL1 output from PLL setup structure (precise frequency)
1807 * param pSetup : Pointer to populated PLL setup structure
1808 * return kStatus_PLL_Success on success, or PLL setup error code
1809 * note This function will power off the PLL, setup the PLL with the
1810 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1811 * and adjust system voltages to the new PLL rate. The function will not
1812 * alter any source clocks (ie, main systen clock) that may use the PLL,
1813 * so these should be setup prior to and after exiting the function.
1814 */
1815pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup)
1816{
1817 uint32_t inRate, clkRate, prediv;
1818 /* Power off PLL during setup changes */
1819 POWER_EnablePD(kPDRUNCFG_PD_PLL1);
1820
1821 /* Write PLL setup data */
1822 SYSCON->PLL1CTRL = pSetup->pllctrl;
1823 SYSCON->PLL1NDEC = pSetup->pllndec;
1824 SYSCON->PLL1NDEC = pSetup->pllndec | (1UL << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */
1825 SYSCON->PLL1PDEC = pSetup->pllpdec;
1826 SYSCON->PLL1PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */
1827 SYSCON->PLL1MDEC = pSetup->pllmdec;
1828 SYSCON->PLL1MDEC = pSetup->pllmdec | (1UL << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */
1829
1830 POWER_DisablePD(kPDRUNCFG_PD_PLL1);
1831
1832 if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0UL)
1833 {
1834 inRate = CLOCK_GetPLL1InClockRate();
1835 prediv = findPll1PreDiv();
1836 /* Adjust input clock */
1837 clkRate = inRate / prediv;
1838 /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */
1839 if ((clkRate >= 100000UL) && (clkRate <= 20000000UL))
1840 {
1841 while (CLOCK_IsPLL1Locked() == false)
1842 {
1843 }
1844 }
1845 else
1846 {
1847 SDK_DelayAtLeastUs(6000U,
1848 SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to
1849 insure the PLL will be stable */
1850 }
1851 }
1852
1853 /* Update current programmed PLL rate var */
1854 s_Pll1_Freq = pSetup->pllRate;
1855
1856 return kStatus_PLL_Success;
1857}
1858
1859/* Set PLL0 clock based on the input frequency and multiplier */
1860/*! brief Set PLL0 output based on the multiplier and input frequency
1861 * param multiply_by : multiplier
1862 * param input_freq : Clock input frequency of the PLL
1863 * return Nothing
1864 * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
1865 * function does not disable or enable PLL power, wait for PLL lock,
1866 * or adjust system voltages. These must be done in the application.
1867 * The function will not alter any source clocks (ie, main systen clock)
1868 * that may use the PLL, so these should be setup prior to and after
1869 * exiting the function.
1870 */
1871void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq)
1872{
1873 uint32_t cco_freq = input_freq * multiply_by;
1874 uint32_t pdec = 1U;
1875 uint32_t selr;
1876 uint32_t seli;
1877 uint32_t selp;
1878 uint32_t mdec, ndec;
1879
1880 while (cco_freq < 275000000U)
1881 {
1882 multiply_by <<= 1U; /* double value in each iteration */
1883 pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */
1884 cco_freq = input_freq * multiply_by;
1885 }
1886
1887 selr = 0U;
1888
1889 if (multiply_by >= 8000UL)
1890 {
1891 seli = 1UL;
1892 }
1893 else if (multiply_by >= 122UL)
1894 {
1895 seli = (uint32_t)(8000UL / multiply_by); /*floor(8000/M) */
1896 }
1897 else
1898 {
1899 seli = 2UL * ((uint32_t)(multiply_by / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */
1900 }
1901
1902 if (seli >= 63U)
1903 {
1904 seli = 63U;
1905 }
1906
1907 {
1908 selp = 31U;
1909 }
1910
1911 if (pdec > 1U)
1912 {
1913 pdec = pdec / 2U; /* Account for minus 1 encoding */
1914 /* Translate P value */
1915 }
1916
1917 mdec = (uint32_t)PLL_SSCG1_MDEC_VAL_SET(multiply_by);
1918 ndec = 0x1U; /* pre divide by 1 (hardcoded) */
1919
1920 SYSCON->PLL0CTRL = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_BYPASSPOSTDIV(0) |
1921 SYSCON_PLL0CTRL_BYPASSPOSTDIV2(0) | (selr << SYSCON_PLL0CTRL_SELR_SHIFT) |
1922 (seli << SYSCON_PLL0CTRL_SELI_SHIFT) | (selp << SYSCON_PLL0CTRL_SELP_SHIFT);
1923 SYSCON->PLL0PDEC = pdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */
1924 SYSCON->PLL0NDEC = ndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */
1925 SYSCON->PLL0SSCG1 =
1926 mdec | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */
1927}
1928
1929/* Enable USB DEVICE FULL SPEED clock */
1930/*! brief Enable USB Device FS clock.
1931 * param src : clock source
1932 * param freq: clock frequency
1933 * Enable USB Device Full Speed clock.
1934 */
1935bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq)
1936{
1937 bool ret = true;
1938
1939 CLOCK_DisableClock(kCLOCK_Usbd0);
1940
1941 if (kCLOCK_UsbfsSrcFro == src)
1942 {
1943 switch (freq)
1944 {
1945 case 96000000U:
1946 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */
1947 break;
1948
1949 default:
1950 ret = false;
1951 break;
1952 }
1953 /* Turn ON FRO HF */
1954 POWER_DisablePD(kPDRUNCFG_PD_FRO192M);
1955 /* Enable FRO 96MHz output */
1956 ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK;
1957 /* Select FRO 96 or 48 MHz */
1958 CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
1959 }
1960 else
1961 {
1962 /*!< Configure XTAL32M */
1963 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
1964 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
1965 (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
1966 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
1967 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
1968
1969 /*!< Set up PLL1 */
1970 POWER_DisablePD(kPDRUNCFG_PD_PLL1);
1971 CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */
1972 const pll_setup_t pll1Setup = {
1973 .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U),
1974 .pllndec = SYSCON_PLL1NDEC_NDIV(1U),
1975 .pllpdec = SYSCON_PLL1PDEC_PDIV(5U),
1976 .pllmdec = SYSCON_PLL1MDEC_MDIV(30U),
1977 .pllRate = 48000000U,
1978 .flags = PLL_SETUPFLAG_WAITLOCK};
1979 (void)CLOCK_SetPLL1Freq(&pll1Setup);
1980
1981 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false);
1982 CLOCK_AttachClk(kPLL1_to_USB0_CLK);
1983 SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
1984 }
1985 CLOCK_EnableClock(kCLOCK_Usbd0);
1986
1987 return ret;
1988}
1989
1990/* Enable USB HOST FULL SPEED clock */
1991/*! brief Enable USB HOST FS clock.
1992 * param src : clock source
1993 * param freq: clock frequency
1994 * Enable USB HOST Full Speed clock.
1995 */
1996bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq)
1997{
1998 bool ret = true;
1999
2000 CLOCK_DisableClock(kCLOCK_Usbhmr0);
2001 CLOCK_DisableClock(kCLOCK_Usbhsl0);
2002
2003 if (kCLOCK_UsbfsSrcFro == src)
2004 {
2005 switch (freq)
2006 {
2007 case 96000000U:
2008 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */
2009 break;
2010
2011 default:
2012 ret = false;
2013 break;
2014 }
2015 /* Turn ON FRO HF */
2016 POWER_DisablePD(kPDRUNCFG_PD_FRO192M);
2017 /* Enable FRO 96MHz output */
2018 ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK;
2019 /* Select FRO 96 MHz */
2020 CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
2021 }
2022 else
2023 {
2024 /*!< Configure XTAL32M */
2025 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
2026 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
2027 (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
2028 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
2029 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
2030
2031 /*!< Set up PLL1 */
2032 POWER_DisablePD(kPDRUNCFG_PD_PLL1);
2033 CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */
2034 const pll_setup_t pll1Setup = {
2035 .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U),
2036 .pllndec = SYSCON_PLL1NDEC_NDIV(1U),
2037 .pllpdec = SYSCON_PLL1PDEC_PDIV(5U),
2038 .pllmdec = SYSCON_PLL1MDEC_MDIV(30U),
2039 .pllRate = 48000000U,
2040 .flags = PLL_SETUPFLAG_WAITLOCK};
2041 (void)CLOCK_SetPLL1Freq(&pll1Setup);
2042
2043 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false);
2044 CLOCK_AttachClk(kPLL1_to_USB0_CLK);
2045 SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
2046 }
2047 CLOCK_EnableClock(kCLOCK_Usbhmr0);
2048 CLOCK_EnableClock(kCLOCK_Usbhsl0);
2049
2050 return ret;
2051}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_clock.h
new file mode 100644
index 000000000..076939b1a
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_clock.h
@@ -0,0 +1,1249 @@
1/*
2 * Copyright 2017 - 2020 , NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_common.h"
12
13/*! @addtogroup clock */
14/*! @{ */
15
16/*! @file */
17
18/*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22/*! @name Driver version */
23/*@{*/
24/*! @brief CLOCK driver version 2.3.4. */
25#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 4))
26/*@}*/
27
28/*! @brief Configure whether driver controls clock
29 *
30 * When set to 0, peripheral drivers will enable clock in initialize function
31 * and disable clock in de-initialize function. When set to 1, peripheral
32 * driver will not control the clock, application could control the clock out of
33 * the driver.
34 *
35 * @note All drivers share this feature switcher. If it is set to 1, application
36 * should handle clock enable and disable for all drivers.
37 */
38#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
39#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
40#endif
41
42/*!
43 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
44 *
45 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
46 * would cache the recent calulation and accelerate the execution to get the
47 * right settings.
48 */
49#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
50#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
51#endif
52
53/* Definition for delay API in clock driver, users can redefine it to the real application. */
54#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
55#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (100000000UL)
56#endif
57
58/*! @brief Clock ip name array for ROM. */
59#define ROM_CLOCKS \
60 { \
61 kCLOCK_Rom \
62 }
63/*! @brief Clock ip name array for SRAM. */
64#define SRAM_CLOCKS \
65 { \
66 kCLOCK_Sram1, kCLOCK_Sram2 \
67 }
68/*! @brief Clock ip name array for FLASH. */
69#define FLASH_CLOCKS \
70 { \
71 kCLOCK_Flash \
72 }
73/*! @brief Clock ip name array for FMC. */
74#define FMC_CLOCKS \
75 { \
76 kCLOCK_Fmc \
77 }
78/*! @brief Clock ip name array for INPUTMUX. */
79#define INPUTMUX_CLOCKS \
80 { \
81 kCLOCK_InputMux0 \
82 }
83/*! @brief Clock ip name array for IOCON. */
84#define IOCON_CLOCKS \
85 { \
86 kCLOCK_Iocon \
87 }
88/*! @brief Clock ip name array for GPIO. */
89#define GPIO_CLOCKS \
90 { \
91 kCLOCK_Gpio0, kCLOCK_Gpio1 \
92 }
93/*! @brief Clock ip name array for PINT. */
94#define PINT_CLOCKS \
95 { \
96 kCLOCK_Pint \
97 }
98/*! @brief Clock ip name array for GINT. */
99#define GINT_CLOCKS \
100 { \
101 kCLOCK_Gint, kCLOCK_Gint \
102 }
103/*! @brief Clock ip name array for DMA. */
104#define DMA_CLOCKS \
105 { \
106 kCLOCK_Dma0, kCLOCK_Dma1 \
107 }
108/*! @brief Clock ip name array for CRC. */
109#define CRC_CLOCKS \
110 { \
111 kCLOCK_Crc \
112 }
113/*! @brief Clock ip name array for WWDT. */
114#define WWDT_CLOCKS \
115 { \
116 kCLOCK_Wwdt \
117 }
118/*! @brief Clock ip name array for RTC. */
119#define RTC_CLOCKS \
120 { \
121 kCLOCK_Rtc \
122 }
123/*! @brief Clock ip name array for Mailbox. */
124#define MAILBOX_CLOCKS \
125 { \
126 kCLOCK_Mailbox \
127 }
128/*! @brief Clock ip name array for LPADC. */
129#define LPADC_CLOCKS \
130 { \
131 kCLOCK_Adc0 \
132 }
133/*! @brief Clock ip name array for MRT. */
134#define MRT_CLOCKS \
135 { \
136 kCLOCK_Mrt \
137 }
138/*! @brief Clock ip name array for OSTIMER. */
139#define OSTIMER_CLOCKS \
140 { \
141 kCLOCK_OsTimer0 \
142 }
143/*! @brief Clock ip name array for SCT0. */
144#define SCT_CLOCKS \
145 { \
146 kCLOCK_Sct0 \
147 }
148/*! @brief Clock ip name array for MCAN. */
149#define MCAN_CLOCKS \
150 { \
151 kCLOCK_Mcan \
152 }
153/*! @brief Clock ip name array for UTICK. */
154#define UTICK_CLOCKS \
155 { \
156 kCLOCK_Utick0 \
157 }
158/*! @brief Clock ip name array for FLEXCOMM. */
159#define FLEXCOMM_CLOCKS \
160 { \
161 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
162 kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \
163 }
164/*! @brief Clock ip name array for LPUART. */
165#define LPUART_CLOCKS \
166 { \
167 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
168 kCLOCK_MinUart6, kCLOCK_MinUart7 \
169 }
170
171/*! @brief Clock ip name array for BI2C. */
172#define BI2C_CLOCKS \
173 { \
174 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \
175 }
176/*! @brief Clock ip name array for LSPI. */
177#define LPSPI_CLOCKS \
178 { \
179 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \
180 }
181/*! @brief Clock ip name array for FLEXI2S. */
182#define FLEXI2S_CLOCKS \
183 { \
184 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
185 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \
186 }
187/*! @brief Clock ip name array for CTIMER. */
188#define CTIMER_CLOCKS \
189 { \
190 kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
191 }
192/*! @brief Clock ip name array for EZHA */
193#define EZHA_CLOCKS \
194 { \
195 kCLOCK_Ezha \
196 }
197/*! @brief Clock ip name array for EZHB */
198#define EZHB_CLOCKS \
199 { \
200 kCLOCK_Ezhb \
201 }
202/*! @brief Clock ip name array for COMP */
203#define COMP_CLOCKS \
204 { \
205 kCLOCK_Comp \
206 }
207/*! @brief Clock ip name array for USB1CLK. */
208#define USB1CLK_CLOCKS \
209 { \
210 kCLOCK_Usb1Clk \
211 }
212/*! @brief Clock ip name array for FREQME. */
213#define FREQME_CLOCKS \
214 { \
215 kCLOCK_Freqme \
216 }
217/*! @brief Clock ip name array for USBRAM. */
218#define USBRAM_CLOCKS \
219 { \
220 kCLOCK_UsbRam1 \
221 }
222/*! @brief Clock ip name array for CWT. */
223#define CWT_CLOCKS \
224 { \
225 kCLOCK_Cwt \
226 }
227/*! @brief Clock ip name array for RNG. */
228#define RNG_CLOCKS \
229 { \
230 kCLOCK_Rng \
231 }
232/*! @brief Clock ip name array for USBHMR0. */
233#define USBHMR0_CLOCKS \
234 { \
235 kCLOCK_Usbhmr0 \
236 }
237/*! @brief Clock ip name array for USBHSL0. */
238#define USBHSL0_CLOCKS \
239 { \
240 kCLOCK_Usbhsl0 \
241 }
242/*! @brief Clock ip name array for HashCrypt. */
243#define HASHCRYPT_CLOCKS \
244 { \
245 kCLOCK_HashCrypt \
246 }
247/*! @brief Clock ip name array for PLULUT. */
248#define PLULUT_CLOCKS \
249 { \
250 kCLOCK_PluLut \
251 }
252/*! @brief Clock ip name array for PUF. */
253#define PUF_CLOCKS \
254 { \
255 kCLOCK_Puf \
256 }
257/*! @brief Clock ip name array for CASPER. */
258#define CASPER_CLOCKS \
259 { \
260 kCLOCK_Casper \
261 }
262/*! @brief Clock ip name array for ANALOGCTRL. */
263#define ANALOGCTRL_CLOCKS \
264 { \
265 kCLOCK_AnalogCtrl \
266 }
267/*! @brief Clock ip name array for HS_LSPI. */
268#define HS_LSPI_CLOCKS \
269 { \
270 kCLOCK_Hs_Lspi \
271 }
272/*! @brief Clock ip name array for GPIO_SEC. */
273#define GPIO_SEC_CLOCKS \
274 { \
275 kCLOCK_Gpio_Sec \
276 }
277/*! @brief Clock ip name array for GPIO_SEC_INT. */
278#define GPIO_SEC_INT_CLOCKS \
279 { \
280 kCLOCK_Gpio_Sec_Int \
281 }
282/*! @brief Clock ip name array for USBD. */
283#define USBD_CLOCKS \
284 { \
285 kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
286 }
287/*! @brief Clock ip name array for USBH. */
288#define USBH_CLOCKS \
289 { \
290 kCLOCK_Usbh1 \
291 }
292#define PLU_CLOCKS \
293 { \
294 kCLOCK_PluLut \
295 }
296#define SYSCTL_CLOCKS \
297 { \
298 kCLOCK_Sysctl \
299 }
300/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
301/*------------------------------------------------------------------------------
302 clock_ip_name_t definition:
303------------------------------------------------------------------------------*/
304
305#define CLK_GATE_REG_OFFSET_SHIFT 8U
306#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
307#define CLK_GATE_BIT_SHIFT_SHIFT 0U
308#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
309
310#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
311 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
312 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
313
314#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
315#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
316
317#define AHB_CLK_CTRL0 0
318#define AHB_CLK_CTRL1 1
319#define AHB_CLK_CTRL2 2
320
321/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
322typedef enum _clock_ip_name
323{
324 kCLOCK_IpInvalid = 0U,
325 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
326 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
327 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
328 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),
329 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),
330 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
331 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
332 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
333 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
334 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
335 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),
336 kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
337 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
338 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
339 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
340 kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26),
341 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
342 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
343 kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),
344 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
345 kCLOCK_Mcan = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7),
346 kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
347 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
348 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
349 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
350 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
351 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
352 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
353 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
354 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
355 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
356 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
357 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
358 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
359 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
360 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
361 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
362 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
363 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
364 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
365 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
366 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
367 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
368 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
369 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
370 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
371 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
372 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
373 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
374 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
375 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
376 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
377 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
378 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
379 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
380 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
381 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
382 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
383 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
384 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
385 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
386 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
387 kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
388 kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
389 kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
390 kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
391 kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30),
392 kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
393 kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1),
394 kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),
395 kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),
396 kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),
397 kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),
398 kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),
399 kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8),
400 kCLOCK_Cwt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11),
401 kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),
402 kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
403 kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),
404 kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),
405 kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),
406 kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),
407 kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21),
408 kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22),
409 kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23),
410 kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24),
411 kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27),
412 kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28),
413 kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29),
414 kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30)
415} clock_ip_name_t;
416
417/*! @brief Peripherals clock source definition. */
418#define BUS_CLK kCLOCK_BusClk
419
420#define I2C0_CLK_SRC BUS_CLK
421
422/*! @brief Clock name used to get clock frequency. */
423typedef enum _clock_name
424{
425 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
426 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
427 kCLOCK_ClockOut, /*!< CLOCKOUT */
428 kCLOCK_FroHf, /*!< FRO48/96 */
429 kCLOCK_Pll1Out, /*!< PLL1 Output */
430 kCLOCK_Mclk, /*!< MCLK */
431 kCLOCK_Fro12M, /*!< FRO12M */
432 kCLOCK_Fro1M, /*!< FRO1M */
433 kCLOCK_ExtClk, /*!< External Clock */
434 kCLOCK_Pll0Out, /*!< PLL0 Output */
435 kCLOCK_FlexI2S, /*!< FlexI2S clock */
436
437} clock_name_t;
438
439/*! @brief Clock Mux Switches
440 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
441 * starting from LSB upwards
442 *
443 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
444 *
445 */
446
447#define CLK_ATTACH_ID(mux, sel, pos) \
448 ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U))
449#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
450#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
451
452#define GET_ID_ITEM(connection) ((connection)&0xFFFU)
453#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
454#define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU)
455#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF00U) >> 8U) - 1U))
456#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
457
458#define CM_SYSTICKCLKSEL0 0
459#define CM_TRACECLKSEL 2
460#define CM_CTIMERCLKSEL0 3
461#define CM_CTIMERCLKSEL1 4
462#define CM_CTIMERCLKSEL2 5
463#define CM_CTIMERCLKSEL3 6
464#define CM_CTIMERCLKSEL4 7
465#define CM_MAINCLKSELA 8
466#define CM_MAINCLKSELB 9
467#define CM_CLKOUTCLKSEL 10
468#define CM_PLL0CLKSEL 12
469#define CM_PLL1CLKSEL 13
470#define CM_MCANCLKSEL 16
471#define CM_ADCASYNCCLKSEL 17
472#define CM_USB0CLKSEL 18
473#define CM_CLK32KCLKSEL 19
474#define CM_FXCOMCLKSEL0 20
475#define CM_FXCOMCLKSEL1 21
476#define CM_FXCOMCLKSEL2 22
477#define CM_FXCOMCLKSEL3 23
478#define CM_FXCOMCLKSEL4 24
479#define CM_FXCOMCLKSEL5 25
480#define CM_FXCOMCLKSEL6 26
481#define CM_FXCOMCLKSEL7 27
482#define CM_HSLSPICLKSEL 28
483#define CM_MCLKCLKSEL 32
484#define CM_SCTCLKSEL 36
485
486#define CM_OSTIMERCLKSEL (62U)
487#define CM_RTCOSC32KCLKSEL 63U
488
489typedef enum _clock_attach_id
490{
491
492 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),
493 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),
494 kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),
495 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),
496 kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0),
497 kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),
498 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),
499
500 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0),
501 kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1),
502 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2),
503 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3),
504 kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4),
505 kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5),
506 kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6),
507 kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7),
508
509 kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0),
510 kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1),
511 kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2),
512 kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3),
513 kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7),
514
515 kMCAN_DIV_to_MCAN = MUX_A(CM_MCANCLKSEL, 0),
516 kFRO1M_to_MCAN = MUX_A(CM_MCANCLKSEL, 1),
517 kOSC32K_to_MCAN = MUX_A(CM_MCANCLKSEL, 2),
518 kNONE_to_MCAN = MUX_A(CM_MCANCLKSEL, 7),
519
520 kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
521 kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
522 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
523 kEXT_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 4),
524 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
525
526 kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0),
527 kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),
528 kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3),
529 kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5),
530 kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),
531
532 kOSC32K_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 0),
533 kFRO1MDIV_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 1),
534 kNONE_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 7),
535
536 kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
537 kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
538 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
539 kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
540 kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
541 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5),
542 kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6),
543 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
544
545 kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
546 kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
547 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
548 kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
549 kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
550 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5),
551 kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6),
552 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
553
554 kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
555 kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
556 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
557 kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
558 kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
559 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5),
560 kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6),
561 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
562
563 kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
564 kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
565 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
566 kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
567 kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
568 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5),
569 kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6),
570 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
571
572 kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
573 kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
574 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
575 kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
576 kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
577 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5),
578 kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6),
579 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
580
581 kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
582 kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
583 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
584 kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
585 kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
586 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5),
587 kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6),
588 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
589
590 kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
591 kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
592 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
593 kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
594 kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
595 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5),
596 kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6),
597 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
598
599 kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
600 kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
601 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
602 kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
603 kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
604 kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5),
605 kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6),
606 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
607
608 kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0),
609 kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1),
610 kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2),
611 kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3),
612 kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4),
613 kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6),
614 kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7),
615
616 kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0),
617 kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),
618 kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),
619
620 kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0),
621 kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),
622 kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),
623 kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),
624 kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5),
625 kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),
626
627 kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0),
628 kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1),
629
630 kOSC32K_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 0),
631 kFRO1M_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 1),
632 kMAIN_CLK_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 2),
633
634 kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0),
635 kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1),
636 kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2),
637 kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7),
638
639 kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0),
640 kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1),
641 kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2),
642 kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7),
643
644 kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0),
645 kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1),
646 kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2),
647 kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3),
648 kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7),
649
650 kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0),
651 kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1),
652 kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3),
653 kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4),
654 kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5),
655 kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6),
656 kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7),
657
658 kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0),
659 kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1),
660 kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3),
661 kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4),
662 kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5),
663 kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6),
664 kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7),
665
666 kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0),
667 kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1),
668 kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3),
669 kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4),
670 kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5),
671 kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6),
672 kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7),
673
674 kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0),
675 kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1),
676 kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3),
677 kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4),
678 kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5),
679 kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6),
680 kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7),
681
682 kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0),
683 kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1),
684 kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3),
685 kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4),
686 kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5),
687 kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6),
688 kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7),
689 kNONE_to_NONE = (int)0x80000000U,
690} clock_attach_id_t;
691
692/* Clock dividers */
693typedef enum _clock_div_name
694{
695 kCLOCK_DivSystickClk0 = 0,
696 kCLOCK_DivArmTrClkDiv = 2,
697 kCLOCK_DivCanClk = 3,
698 kCLOCK_DivFlexFrg0 = 8,
699 kCLOCK_DivFlexFrg1 = 9,
700 kCLOCK_DivFlexFrg2 = 10,
701 kCLOCK_DivFlexFrg3 = 11,
702 kCLOCK_DivFlexFrg4 = 12,
703 kCLOCK_DivFlexFrg5 = 13,
704 kCLOCK_DivFlexFrg6 = 14,
705 kCLOCK_DivFlexFrg7 = 15,
706 kCLOCK_DivAhbClk = 32,
707 kCLOCK_DivClkOut = 33,
708 kCLOCK_DivFrohfClk = 34,
709 kCLOCK_DivWdtClk = 35,
710 kCLOCK_DivAdcAsyncClk = 37,
711 kCLOCK_DivUsb0Clk = 38,
712 kCLOCK_DivFro1mClk = 40,
713 kCLOCK_DivMClk = 43,
714 kCLOCK_DivSctClk = 45,
715 kCLOCK_DivPll0Clk = 49
716} clock_div_name_t;
717
718/*******************************************************************************
719 * API
720 ******************************************************************************/
721
722#if defined(__cplusplus)
723extern "C" {
724#endif /* __cplusplus */
725
726/**
727 * @brief Enable the clock for specific IP.
728 * @param clk : Clock to be enabled.
729 * @return Nothing
730 */
731static inline void CLOCK_EnableClock(clock_ip_name_t clk)
732{
733 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
734 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
735}
736/**
737 * @brief Disable the clock for specific IP.
738 * @param clk : Clock to be Disabled.
739 * @return Nothing
740 */
741static inline void CLOCK_DisableClock(clock_ip_name_t clk)
742{
743 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
744 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
745}
746/**
747 * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
748 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
749 * enabled.
750 * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)
751 * @return returns success or fail status.
752 */
753status_t CLOCK_SetupFROClocking(uint32_t iFreq);
754/**
755 * @brief Set the flash wait states for the input freuqency.
756 * @param system_freq_hz : Input frequency
757 * @return Nothing
758 */
759void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz);
760/**
761 * @brief Initialize the external osc clock to given frequency.
762 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
763 * @return returns success or fail status.
764 */
765status_t CLOCK_SetupExtClocking(uint32_t iFreq);
766/**
767 * @brief Initialize the I2S MCLK clock to given frequency.
768 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
769 * @return returns success or fail status.
770 */
771status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq);
772/**
773 * @brief Initialize the PLU CLKIN clock to given frequency.
774 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
775 * @return returns success or fail status.
776 */
777status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq);
778/**
779 * @brief Configure the clock selection muxes.
780 * @param connection : Clock to be configured.
781 * @return Nothing
782 */
783void CLOCK_AttachClk(clock_attach_id_t connection);
784/**
785 * @brief Get the actual clock attach id.
786 * This fuction uses the offset in input attach id, then it reads the actual source value in
787 * the register and combine the offset to obtain an actual attach id.
788 * @param attachId : Clock attach id to get.
789 * @return Clock source value.
790 */
791clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
792/**
793 * @brief Setup peripheral clock dividers.
794 * @param div_name : Clock divider name
795 * @param divided_by_value: Value to be divided
796 * @param reset : Whether to reset the divider counter.
797 * @return Nothing
798 */
799void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
800/**
801 * @brief Setup rtc 1khz clock divider.
802 * @param divided_by_value: Value to be divided
803 * @return Nothing
804 */
805void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value);
806/**
807 * @brief Setup rtc 1hz clock divider.
808 * @param divided_by_value: Value to be divided
809 * @return Nothing
810 */
811void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value);
812
813/**
814 * @brief Set the flexcomm output frequency.
815 * @param id : flexcomm instance id
816 * @param freq : output frequency
817 * @return 0 : the frequency range is out of range.
818 * 1 : switch successfully.
819 */
820uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq);
821
822/*! @brief Return Frequency of flexcomm input clock
823 * @param id : flexcomm instance id
824 * @return Frequency value
825 */
826uint32_t CLOCK_GetFlexCommInputClock(uint32_t id);
827
828/*! @brief Return Frequency of selected clock
829 * @return Frequency of selected clock
830 */
831uint32_t CLOCK_GetFreq(clock_name_t clockName);
832/*! @brief Return Frequency of FRO 12MHz
833 * @return Frequency of FRO 12MHz
834 */
835uint32_t CLOCK_GetFro12MFreq(void);
836/*! @brief Return Frequency of FRO 1MHz
837 * @return Frequency of FRO 1MHz
838 */
839uint32_t CLOCK_GetFro1MFreq(void);
840/*! @brief Return Frequency of ClockOut
841 * @return Frequency of ClockOut
842 */
843uint32_t CLOCK_GetClockOutClkFreq(void);
844/*! @brief Return Frequency of Can Clock
845 * @return Frequency of Can.
846 */
847uint32_t CLOCK_GetMCanClkFreq(void);
848/*! @brief Return Frequency of Adc Clock
849 * @return Frequency of Adc.
850 */
851uint32_t CLOCK_GetAdcClkFreq(void);
852/*! @brief Return Frequency of Usb0 Clock
853 * @return Frequency of Usb0 Clock.
854 */
855uint32_t CLOCK_GetUsb0ClkFreq(void);
856/*! @brief Return Frequency of Usb1 Clock
857 * @return Frequency of Usb1 Clock.
858 */
859uint32_t CLOCK_GetUsb1ClkFreq(void);
860/*! @brief Return Frequency of MClk Clock
861 * @return Frequency of MClk Clock.
862 */
863uint32_t CLOCK_GetMclkClkFreq(void);
864/*! @brief Return Frequency of SCTimer Clock
865 * @return Frequency of SCTimer Clock.
866 */
867uint32_t CLOCK_GetSctClkFreq(void);
868/*! @brief Return Frequency of External Clock
869 * @return Frequency of External Clock. If no external clock is used returns 0.
870 */
871uint32_t CLOCK_GetExtClkFreq(void);
872/*! @brief Return Frequency of Watchdog
873 * @return Frequency of Watchdog
874 */
875uint32_t CLOCK_GetWdtClkFreq(void);
876/*! @brief Return Frequency of High-Freq output of FRO
877 * @return Frequency of High-Freq output of FRO
878 */
879uint32_t CLOCK_GetFroHfFreq(void);
880/*! @brief Return Frequency of PLL
881 * @return Frequency of PLL
882 */
883uint32_t CLOCK_GetPll0OutFreq(void);
884/*! @brief Return Frequency of USB PLL
885 * @return Frequency of PLL
886 */
887uint32_t CLOCK_GetPll1OutFreq(void);
888/*! @brief Return Frequency of 32kHz osc
889 * @return Frequency of 32kHz osc
890 */
891uint32_t CLOCK_GetOsc32KFreq(void);
892/*! @brief Return Frequency of Core System
893 * @return Frequency of Core System
894 */
895uint32_t CLOCK_GetCoreSysClkFreq(void);
896/*! @brief Return Frequency of I2S MCLK Clock
897 * @return Frequency of I2S MCLK Clock
898 */
899uint32_t CLOCK_GetI2SMClkFreq(void);
900/*! @brief Return Frequency of PLU CLKIN Clock
901 * @return Frequency of PLU CLKIN Clock
902 */
903uint32_t CLOCK_GetPLUClkInFreq(void);
904/*! @brief Return Frequency of FlexComm Clock
905 * @return Frequency of FlexComm Clock
906 */
907uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
908/*! @brief Return Frequency of High speed SPI Clock
909 * @return Frequency of High speed SPI Clock
910 */
911uint32_t CLOCK_GetHsLspiClkFreq(void);
912/*! @brief Return Frequency of CTimer functional Clock
913 * @return Frequency of CTimer functional Clock
914 */
915uint32_t CLOCK_GetCTimerClkFreq(uint32_t id);
916/*! @brief Return Frequency of SystickClock
917 * @return Frequency of Systick Clock
918 */
919uint32_t CLOCK_GetSystickClkFreq(uint32_t id);
920
921/*! @brief Return PLL0 input clock rate
922 * @return PLL0 input clock rate
923 */
924uint32_t CLOCK_GetPLL0InClockRate(void);
925
926/*! @brief Return PLL1 input clock rate
927 * @return PLL1 input clock rate
928 */
929uint32_t CLOCK_GetPLL1InClockRate(void);
930
931/*! @brief Return PLL0 output clock rate
932 * @param recompute : Forces a PLL rate recomputation if true
933 * @return PLL0 output clock rate
934 * @note The PLL rate is cached in the driver in a variable as
935 * the rate computation function can take some time to perform. It
936 * is recommended to use 'false' with the 'recompute' parameter.
937 */
938uint32_t CLOCK_GetPLL0OutClockRate(bool recompute);
939
940/*! @brief Return PLL1 output clock rate
941 * @param recompute : Forces a PLL rate recomputation if true
942 * @return PLL1 output clock rate
943 * @note The PLL rate is cached in the driver in a variable as
944 * the rate computation function can take some time to perform. It
945 * is recommended to use 'false' with the 'recompute' parameter.
946 */
947uint32_t CLOCK_GetPLL1OutClockRate(bool recompute);
948
949/*! @brief Enables and disables PLL0 bypass mode
950 * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass
951 * @return PLL0 output clock rate
952 */
953__STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass)
954{
955 if (bypass)
956 {
957 SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);
958 }
959 else
960 {
961 SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);
962 }
963}
964
965/*! @brief Enables and disables PLL1 bypass mode
966 * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass
967 * @return PLL1 output clock rate
968 */
969__STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass)
970{
971 if (bypass)
972 {
973 SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);
974 }
975 else
976 {
977 SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);
978 }
979}
980
981/*! @brief Check if PLL is locked or not
982 * @return true if the PLL is locked, false if not locked
983 */
984__STATIC_INLINE bool CLOCK_IsPLL0Locked(void)
985{
986 return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL);
987}
988
989/*! @brief Check if PLL1 is locked or not
990 * @return true if the PLL1 is locked, false if not locked
991 */
992__STATIC_INLINE bool CLOCK_IsPLL1Locked(void)
993{
994 return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL);
995}
996
997/*! @brief Store the current PLL0 rate
998 * @param rate: Current rate of the PLL0
999 * @return Nothing
1000 **/
1001void CLOCK_SetStoredPLL0ClockRate(uint32_t rate);
1002
1003/*! @brief PLL configuration structure flags for 'flags' field
1004 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
1005 *
1006 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
1007 * configuration structure must be assigned with the expected PLL frequency. If the
1008 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
1009 * function and the driver will determine the PLL rate from the currently selected
1010 * PLL source. This flag might be used to configure the PLL input clock more accurately
1011 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
1012 *
1013 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
1014 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
1015 * are not used.<br>
1016 */
1017#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
1018#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U)
1019/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */
1020
1021/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency
1022 * See (MF) field in the PLL0SSCG1 register in the UM.
1023 */
1024typedef enum _ss_progmodfm
1025{
1026 kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */
1027 kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */
1028 kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */
1029 kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */
1030 kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */
1031 kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */
1032 kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */
1033 kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */
1034} ss_progmodfm_t;
1035
1036/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth
1037 * See (MR) field in the PLL0SSCG1 register in the UM.
1038 */
1039typedef enum _ss_progmoddp
1040{
1041 kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */
1042 kSS_MR_K1 = (1 << 23), /*!< k = 1 */
1043 kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */
1044 kSS_MR_K2 = (3 << 23), /*!< k = 2 */
1045 kSS_MR_K3 = (4 << 23), /*!< k = 3 */
1046 kSS_MR_K4 = (5 << 23), /*!< k = 4 */
1047 kSS_MR_K6 = (6 << 23), /*!< k = 6 */
1048 kSS_MR_K8 = (7 << 23) /*!< k = 8 */
1049} ss_progmoddp_t;
1050
1051/*! @brief PLL Spread Spectrum (SS) Modulation waveform control
1052 * See (MC) field in the PLL0SSCG1 register in the UM.<br>
1053 * Compensation for low pass filtering of the PLL to get a triangular
1054 * modulation at the output of the PLL, giving a flat frequency spectrum.
1055 */
1056typedef enum _ss_modwvctrl
1057{
1058 kSS_MC_NOC = (0 << 26), /*!< no compensation */
1059 kSS_MC_RECC = (2 << 26), /*!< recommended setting */
1060 kSS_MC_MAXC = (3 << 26), /*!< max. compensation */
1061} ss_modwvctrl_t;
1062
1063/*! @brief PLL configuration structure
1064 *
1065 * This structure can be used to configure the settings for a PLL
1066 * setup structure. Fill in the desired configuration for the PLL
1067 * and call the PLL setup function to fill in a PLL setup structure.
1068 */
1069typedef struct _pll_config
1070{
1071 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
1072 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
1073 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
1074 ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using
1075 PLL_CONFIGFLAG_FORCENOFRACT flag */
1076 ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using
1077 PLL_CONFIGFLAG_FORCENOFRACT flag */
1078 ss_modwvctrl_t
1079 ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
1080 bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using
1081 PLL_CONFIGFLAG_FORCENOFRACT flag */
1082
1083} pll_config_t;
1084
1085/*! @brief PLL setup structure flags for 'flags' field
1086 * These flags control how the PLL setup function sets up the PLL
1087 */
1088#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */
1089#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
1090#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */
1091#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */
1092
1093/*! @brief PLL0 setup structure
1094 * This structure can be used to pre-build a PLL setup configuration
1095 * at run-time and quickly set the PLL to the configuration. It can be
1096 * populated with the PLL setup function. If powering up or waiting
1097 * for PLL lock, the PLL input clock source should be configured prior
1098 * to PLL setup.
1099 */
1100typedef struct _pll_setup
1101{
1102 uint32_t pllctrl; /*!< PLL control register PLL0CTRL */
1103 uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */
1104 uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */
1105 uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */
1106 uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/
1107 uint32_t pllRate; /*!< Acutal PLL rate */
1108 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
1109} pll_setup_t;
1110
1111/*! @brief PLL status definitions
1112 */
1113typedef enum _pll_error
1114{
1115 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
1116 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
1117 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
1118 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
1119 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
1120 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
1121 kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */
1122 kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */
1123} pll_error_t;
1124
1125/*! @brief USB FS clock source definition. */
1126typedef enum _clock_usbfs_src
1127{
1128 kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */
1129 kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */
1130 kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
1131 kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */
1132
1133 kCLOCK_UsbfsSrcNone =
1134 SYSCON_USB0CLKSEL_SEL(7) /*!<this may be selected in order to reduce power when no output is needed. */
1135} clock_usbfs_src_t;
1136
1137/*! @brief USBhs clock source definition. */
1138typedef enum _clock_usbhs_src
1139{
1140 kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not
1141 care the clock source. */
1142} clock_usbhs_src_t;
1143
1144/*! @brief Source of the USB HS PHY. */
1145typedef enum _clock_usb_phy_src
1146{
1147 kCLOCK_UsbPhySrcExt = 0U, /*!< Use external crystal. */
1148} clock_usb_phy_src_t;
1149
1150/*! @brief Return PLL0 output clock rate from setup structure
1151 * @param pSetup : Pointer to a PLL setup structure
1152 * @return System PLL output clock rate the setup structure will generate
1153 */
1154uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup);
1155
1156/*! @brief Return PLL1 output clock rate from setup structure
1157 * @param pSetup : Pointer to a PLL setup structure
1158 * @return PLL0 output clock rate the setup structure will generate
1159 */
1160uint32_t CLOCK_GetPLL1OutFromSetup(pll_setup_t *pSetup);
1161
1162/*! @brief Set PLL0 output based on the passed PLL setup data
1163 * @param pControl : Pointer to populated PLL control structure to generate setup with
1164 * @param pSetup : Pointer to PLL setup structure to be filled
1165 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1166 * @note Actual frequency for setup may vary from the desired frequency based on the
1167 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1168 */
1169pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup);
1170
1171/*! @brief Set PLL output from PLL setup structure (precise frequency)
1172 * @param pSetup : Pointer to populated PLL setup structure
1173 * @param flagcfg : Flag configuration for PLL config structure
1174 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1175 * @note This function will power off the PLL, setup the PLL with the
1176 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1177 * and adjust system voltages to the new PLL rate. The function will not
1178 * alter any source clocks (ie, main systen clock) that may use the PLL,
1179 * so these should be setup prior to and after exiting the function.
1180 */
1181pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg);
1182
1183/**
1184 * @brief Set PLL output from PLL setup structure (precise frequency)
1185 * @param pSetup : Pointer to populated PLL setup structure
1186 * @return kStatus_PLL_Success on success, or PLL setup error code
1187 * @note This function will power off the PLL, setup the PLL with the
1188 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1189 * and adjust system voltages to the new PLL rate. The function will not
1190 * alter any source clocks (ie, main systen clock) that may use the PLL,
1191 * so these should be setup prior to and after exiting the function.
1192 */
1193pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup);
1194
1195/**
1196 * @brief Set PLL output from PLL setup structure (precise frequency)
1197 * @param pSetup : Pointer to populated PLL setup structure
1198 * @return kStatus_PLL_Success on success, or PLL setup error code
1199 * @note This function will power off the PLL, setup the PLL with the
1200 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1201 * and adjust system voltages to the new PLL rate. The function will not
1202 * alter any source clocks (ie, main systen clock) that may use the PLL,
1203 * so these should be setup prior to and after exiting the function.
1204 */
1205pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup);
1206
1207/*! @brief Set PLL0 output based on the multiplier and input frequency
1208 * @param multiply_by : multiplier
1209 * @param input_freq : Clock input frequency of the PLL
1210 * @return Nothing
1211 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
1212 * function does not disable or enable PLL power, wait for PLL lock,
1213 * or adjust system voltages. These must be done in the application.
1214 * The function will not alter any source clocks (ie, main systen clock)
1215 * that may use the PLL, so these should be setup prior to and after
1216 * exiting the function.
1217 */
1218void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq);
1219
1220/*! @brief Disable USB clock.
1221 *
1222 * Disable USB clock.
1223 */
1224static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
1225{
1226 CLOCK_DisableClock(clk);
1227}
1228
1229/*! @brief Enable USB Device FS clock.
1230 * @param src : clock source
1231 * @param freq: clock frequency
1232 * Enable USB Device Full Speed clock.
1233 */
1234bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq);
1235
1236/*! @brief Enable USB HOST FS clock.
1237 * @param src : clock source
1238 * @param freq: clock frequency
1239 * Enable USB HOST Full Speed clock.
1240 */
1241bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq);
1242
1243#if defined(__cplusplus)
1244}
1245#endif /* __cplusplus */
1246
1247/*! @} */
1248
1249#endif /* _FSL_CLOCK_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_inputmux_connections.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_inputmux_connections.h
new file mode 100644
index 000000000..3c142c7eb
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_inputmux_connections.h
@@ -0,0 +1,481 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_INPUTMUX_CONNECTIONS_
10#define _FSL_INPUTMUX_CONNECTIONS_
11
12/*******************************************************************************
13 * Definitions
14 ******************************************************************************/
15/* Component ID definition, used by tools. */
16#ifndef FSL_COMPONENT_ID
17#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections"
18#endif
19
20/*!
21 * @addtogroup inputmux_driver
22 * @{
23 */
24
25/*!
26 * @name Input multiplexing connections
27 * @{
28 */
29
30/*! @brief Periphinmux IDs */
31#define SCT0_INMUX0 0x00U
32#define TIMER0CAPTSEL0 0x20U
33#define TIMER1CAPTSEL0 0x40U
34#define TIMER2CAPTSEL0 0x60U
35#define PINTSEL_PMUX_ID 0xC0U
36#define PINTSEL0 0xC0U
37#define DMA0_ITRIG_INMUX0 0xE0U
38#define DMA0_OTRIG_INMUX0 0x160U
39#define FREQMEAS_REF_REG 0x180U
40#define FREQMEAS_TARGET_REG 0x184U
41#define TIMER3CAPTSEL0 0x1A0U
42#define TIMER4CAPTSEL0 0x1C0U
43#define PINTSECSEL0 0x1E0U
44#define DMA1_ITRIG_INMUX0 0x200U
45#define DMA1_OTRIG_INMUX0 0x240U
46#define DMA0_REQ_ENA_ID 0x740U
47#define DMA1_REQ_ENA_ID 0x760U
48#define DMA0_ITRIG_ENA_ID 0x780U
49#define DMA1_ITRIG_ENA_ID 0x7A0U
50#define ENA_SHIFT 8U
51#define PMUX_SHIFT 20U
52
53/*! @brief INPUTMUX connections type */
54typedef enum _inputmux_connection_t
55{
56 /*!< SCT0 INMUX. */
57 kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_INMUX0 << PMUX_SHIFT),
58 kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_INMUX0 << PMUX_SHIFT),
59 kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_INMUX0 << PMUX_SHIFT),
60 kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_INMUX0 << PMUX_SHIFT),
61 kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_INMUX0 << PMUX_SHIFT),
62 kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_INMUX0 << PMUX_SHIFT),
63 kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_INMUX0 << PMUX_SHIFT),
64 kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_INMUX0 << PMUX_SHIFT),
65 kINPUTMUX_Ctimer0M0ToSct0 = 8U + (SCT0_INMUX0 << PMUX_SHIFT),
66 kINPUTMUX_Ctimer1M0ToSct0 = 9U + (SCT0_INMUX0 << PMUX_SHIFT),
67 kINPUTMUX_Ctimer2M0ToSct0 = 10U + (SCT0_INMUX0 << PMUX_SHIFT),
68 kINPUTMUX_Ctimer3M0ToSct0 = 11U + (SCT0_INMUX0 << PMUX_SHIFT),
69 kINPUTMUX_Ctimer4M0ToSct0 = 12U + (SCT0_INMUX0 << PMUX_SHIFT),
70 kINPUTMUX_AdcIrqToSct0 = 13U + (SCT0_INMUX0 << PMUX_SHIFT),
71 kINPUTMUX_GpiointBmatchToSct0 = 14U + (SCT0_INMUX0 << PMUX_SHIFT),
72 kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_INMUX0 << PMUX_SHIFT),
73 kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_INMUX0 << PMUX_SHIFT),
74 kINPUTMUX_CompOutToSct0 = 17U + (SCT0_INMUX0 << PMUX_SHIFT),
75 kINPUTMUX_I2sSharedSck0ToSct0 = 18U + (SCT0_INMUX0 << PMUX_SHIFT),
76 kINPUTMUX_I2sSharedSck1ToSct0 = 19U + (SCT0_INMUX0 << PMUX_SHIFT),
77 kINPUTMUX_I2sSharedWs0ToSct0 = 20U + (SCT0_INMUX0 << PMUX_SHIFT),
78 kINPUTMUX_I2sSharedWs1ToSct0 = 21U + (SCT0_INMUX0 << PMUX_SHIFT),
79 kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_INMUX0 << PMUX_SHIFT),
80 kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_INMUX0 << PMUX_SHIFT),
81
82 /*!< TIMER0 CAPTSEL. */
83 kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
84 kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
85 kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
86 kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
87 kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
88 kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
89 kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
90 kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
91 kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
92 kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
93 kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
94 kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
95 kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
96 kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
97 kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
98 kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
99 kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
100 kINPUTMUX_Usb0FrameToggleToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
101 kINPUTMUX_Usb1FrameToggleToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
102 kINPUTMUX_CompOutToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
103 kINPUTMUX_I2sSharedWs0ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
104 kINPUTMUX_I2sSharedWs1ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
105
106 /*!< TIMER1 CAPTSEL. */
107 kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
108 kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
109 kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
110 kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
111 kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
112 kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
113 kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
114 kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
115 kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
116 kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
117 kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
118 kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
119 kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
120 kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
121 kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
122 kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
123 kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
124 kINPUTMUX_Usb0FrameToggleToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
125 kINPUTMUX_Usb1FrameToggleToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
126 kINPUTMUX_CompOutToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
127 kINPUTMUX_I2sSharedWs0ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
128 kINPUTMUX_I2sSharedWs1ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
129
130 /*!< TIMER2 CAPTSEL. */
131 kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
132 kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
133 kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
134 kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
135 kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
136 kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
137 kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
138 kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
139 kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
140 kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
141 kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
142 kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
143 kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
144 kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
145 kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
146 kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
147 kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
148 kINPUTMUX_Usb0FrameToggleToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
149 kINPUTMUX_Usb1FrameToggleToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
150 kINPUTMUX_CompOutToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
151 kINPUTMUX_I2sSharedWs0ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
152 kINPUTMUX_I2sSharedWs1ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
153
154 /*!< Pin interrupt select. */
155 kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT),
156 kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT),
157 kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT),
158 kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT),
159 kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT),
160 kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT),
161 kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT),
162 kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT),
163 kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL0 << PMUX_SHIFT),
164 kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL0 << PMUX_SHIFT),
165 kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL0 << PMUX_SHIFT),
166 kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL0 << PMUX_SHIFT),
167 kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT),
168 kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL0 << PMUX_SHIFT),
169 kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL0 << PMUX_SHIFT),
170 kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL0 << PMUX_SHIFT),
171 kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL0 << PMUX_SHIFT),
172 kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL0 << PMUX_SHIFT),
173 kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL0 << PMUX_SHIFT),
174 kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL0 << PMUX_SHIFT),
175 kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL0 << PMUX_SHIFT),
176 kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL0 << PMUX_SHIFT),
177 kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL0 << PMUX_SHIFT),
178 kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL0 << PMUX_SHIFT),
179 kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL0 << PMUX_SHIFT),
180 kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL0 << PMUX_SHIFT),
181 kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL0 << PMUX_SHIFT),
182 kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL0 << PMUX_SHIFT),
183 kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL0 << PMUX_SHIFT),
184 kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT),
185 kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL0 << PMUX_SHIFT),
186 kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL0 << PMUX_SHIFT),
187 kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT),
188 kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT),
189 kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT),
190 kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT),
191 kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT),
192 kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT),
193 kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT),
194 kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT),
195 kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT),
196 kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT),
197 kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT),
198 kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT),
199 kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT),
200 kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL0 << PMUX_SHIFT),
201 kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL0 << PMUX_SHIFT),
202 kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL0 << PMUX_SHIFT),
203 kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL0 << PMUX_SHIFT),
204 kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL0 << PMUX_SHIFT),
205 kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL0 << PMUX_SHIFT),
206 kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL0 << PMUX_SHIFT),
207 kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL0 << PMUX_SHIFT),
208 kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL0 << PMUX_SHIFT),
209 kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL0 << PMUX_SHIFT),
210 kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL0 << PMUX_SHIFT),
211 kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL0 << PMUX_SHIFT),
212 kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL0 << PMUX_SHIFT),
213 kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL0 << PMUX_SHIFT),
214 kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL0 << PMUX_SHIFT),
215 kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL0 << PMUX_SHIFT),
216 kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL0 << PMUX_SHIFT),
217 kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL0 << PMUX_SHIFT),
218 kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT),
219
220 /*!< DMA0 Input trigger. */
221 kINPUTMUX_PinInt0ToDma0 = 0U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
222 kINPUTMUX_PinInt1ToDma0 = 1U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
223 kINPUTMUX_PinInt2ToDma0 = 2U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
224 kINPUTMUX_PinInt3ToDma0 = 3U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
225 kINPUTMUX_Ctimer0M0ToDma0 = 4U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
226 kINPUTMUX_Ctimer0M1ToDma0 = 5U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
227 kINPUTMUX_Ctimer1M0ToDma0 = 6U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
228 kINPUTMUX_Ctimer1M1ToDma0 = 7U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
229 kINPUTMUX_Ctimer2M0ToDma0 = 8U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
230 kINPUTMUX_Ctimer2M1ToDma0 = 9U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
231 kINPUTMUX_Ctimer3M0ToDma0 = 10U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
232 kINPUTMUX_Ctimer3M1ToDma0 = 11U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
233 kINPUTMUX_Ctimer4M0ToDma0 = 12U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
234 kINPUTMUX_Ctimer4M1ToDma0 = 13U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
235 kINPUTMUX_CompOutToDma0 = 14U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
236 kINPUTMUX_Otrig0ToDma0 = 15U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
237 kINPUTMUX_Otrig1ToDma0 = 16U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
238 kINPUTMUX_Otrig2ToDma0 = 17U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
239 kINPUTMUX_Otrig3ToDma0 = 18U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
240 kINPUTMUX_Sct0DmaReq0ToDma0 = 19U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
241 kINPUTMUX_Sct0DmaReq1ToDma0 = 20U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
242 kINPUTMUX_HashDmaRxToDma0 = 21U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
243
244 /*!< DMA0 output trigger. */
245 kINPUTMUX_Dma0Hash0TxTrigoutToTriginChannels = 0U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
246 kINPUTMUX_Dma0HsLspiRxTrigoutToTriginChannels = 2U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
247 kINPUTMUX_Dma0HsLspiTxTrigoutToTriginChannels = 3U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
248 kINPUTMUX_Dma0Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
249 kINPUTMUX_Dma0Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
250 kINPUTMUX_Dma0Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
251 kINPUTMUX_Dma0Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
252 kINPUTMUX_Dma0Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
253 kINPUTMUX_Dma0Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
254 kINPUTMUX_Dma0Flexcomm2RxTrigoutToTriginChannels = 10U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
255 kINPUTMUX_Dma0Flexcomm2TxTrigoutToTriginChannels = 11U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
256 kINPUTMUX_Dma0Flexcomm4RxTrigoutToTriginChannels = 12U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
257 kINPUTMUX_Dma0Flexcomm4TxTrigoutToTriginChannels = 13U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
258 kINPUTMUX_Dma0Flexcomm5RxTrigoutToTriginChannels = 14U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
259 kINPUTMUX_Dma0Flexcomm5TxTrigoutToTriginChannels = 15U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
260 kINPUTMUX_Dma0Flexcomm6RxTrigoutToTriginChannels = 16U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
261 kINPUTMUX_Dma0Flexcomm6TxTrigoutToTriginChannels = 17U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
262 kINPUTMUX_Dma0Flexcomm7RxTrigoutToTriginChannels = 18U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
263 kINPUTMUX_Dma0Flexcomm7TxTrigoutToTriginChannels = 19U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
264 kINPUTMUX_Dma0Adc0Ch0TrigoutToTriginChannels = 21U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
265 kINPUTMUX_Dma0Adc0Ch1TrigoutToTriginChannels = 22U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
266
267 /*!< Selection for frequency measurement reference clock. */
268 kINPUTMUX_ExternOscToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT),
269 kINPUTMUX_Fro12MhzToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT),
270 kINPUTMUX_Fro96MhzToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT),
271 kINPUTMUX_WdtOscToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT),
272 kINPUTMUX_32KhzOscToFreqmeasRef = 4u + (FREQMEAS_REF_REG << PMUX_SHIFT),
273 kINPUTMUX_MainClkToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT),
274 kINPUTMUX_FreqmeGpioClk_aRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT),
275 kINPUTMUX_FreqmeGpioClk_bRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT),
276
277 /*!< Selection for frequency measurement target clock. */
278 kINPUTMUX_ExternOscToFreqmeasTarget = 0U + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
279 kINPUTMUX_Fro12MhzToFreqmeasTarget = 1u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
280 kINPUTMUX_Fro96MhzToFreqmeasTarget = 2u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
281 kINPUTMUX_WdtOscToFreqmeasTarget = 3u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
282 kINPUTMUX_32KhzOscToFreqmeasTarget = 4u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
283 kINPUTMUX_MainClkToFreqmeasTarget = 5u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
284 kINPUTMUX_FreqmeGpioClk_aTarget = 6u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
285 kINPUTMUX_FreqmeGpioClk_bTarget = 7u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
286
287 /*!< TIMER3 CAPTSEL. */
288 kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
289 kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
290 kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
291 kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
292 kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
293 kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
294 kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
295 kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
296 kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
297 kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
298 kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
299 kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
300 kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
301 kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
302 kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
303 kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
304 kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
305 kINPUTMUX_Usb0FrameToggleToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
306 kINPUTMUX_Usb1FrameToggleToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
307 kINPUTMUX_CompOutToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
308 kINPUTMUX_I2sSharedWs0ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
309 kINPUTMUX_I2sSharedWs1ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
310
311 /*!< Timer4 CAPTSEL. */
312 kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
313 kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
314 kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
315 kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
316 kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
317 kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
318 kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
319 kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
320 kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
321 kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
322 kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
323 kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
324 kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
325 kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
326 kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
327 kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
328 kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
329 kINPUTMUX_Usb0FrameToggleToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
330 kINPUTMUX_Usb1FrameToggleToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
331 kINPUTMUX_CompOutToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
332 kINPUTMUX_I2sSharedWs0ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
333 kINPUTMUX_I2sSharedWs1ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
334
335 /*Pin interrupt secure select */
336 kINPUTMUX_GpioPort0Pin0ToPintSecsel = 0U + (PINTSECSEL0 << PMUX_SHIFT),
337 kINPUTMUX_GpioPort0Pin1ToPintSecsel = 1U + (PINTSECSEL0 << PMUX_SHIFT),
338 kINPUTMUX_GpioPort0Pin2ToPintSecsel = 2U + (PINTSECSEL0 << PMUX_SHIFT),
339 kINPUTMUX_GpioPort0Pin3ToPintSecsel = 3U + (PINTSECSEL0 << PMUX_SHIFT),
340 kINPUTMUX_GpioPort0Pin4ToPintSecsel = 4U + (PINTSECSEL0 << PMUX_SHIFT),
341 kINPUTMUX_GpioPort0Pin5ToPintSecsel = 5U + (PINTSECSEL0 << PMUX_SHIFT),
342 kINPUTMUX_GpioPort0Pin6ToPintSecsel = 6U + (PINTSECSEL0 << PMUX_SHIFT),
343 kINPUTMUX_GpioPort0Pin7ToPintSecsel = 7U + (PINTSECSEL0 << PMUX_SHIFT),
344 kINPUTMUX_GpioPort0Pin8ToPintSecsel = 8U + (PINTSECSEL0 << PMUX_SHIFT),
345 kINPUTMUX_GpioPort0Pin9ToPintSecsel = 9U + (PINTSECSEL0 << PMUX_SHIFT),
346 kINPUTMUX_GpioPort0Pin10ToPintSecsel = 10U + (PINTSECSEL0 << PMUX_SHIFT),
347 kINPUTMUX_GpioPort0Pin11ToPintSecsel = 11U + (PINTSECSEL0 << PMUX_SHIFT),
348 kINPUTMUX_GpioPort0Pin12ToPintSecsel = 12U + (PINTSECSEL0 << PMUX_SHIFT),
349 kINPUTMUX_GpioPort0Pin13ToPintSecsel = 13U + (PINTSECSEL0 << PMUX_SHIFT),
350 kINPUTMUX_GpioPort0Pin14ToPintSecsel = 14U + (PINTSECSEL0 << PMUX_SHIFT),
351 kINPUTMUX_GpioPort0Pin15ToPintSecsel = 15U + (PINTSECSEL0 << PMUX_SHIFT),
352 kINPUTMUX_GpioPort0Pin16ToPintSecsel = 16U + (PINTSECSEL0 << PMUX_SHIFT),
353 kINPUTMUX_GpioPort0Pin17ToPintSecsel = 17U + (PINTSECSEL0 << PMUX_SHIFT),
354 kINPUTMUX_GpioPort0Pin18ToPintSecsel = 18U + (PINTSECSEL0 << PMUX_SHIFT),
355 kINPUTMUX_GpioPort0Pin19ToPintSecsel = 19U + (PINTSECSEL0 << PMUX_SHIFT),
356 kINPUTMUX_GpioPort0Pin20ToPintSecsel = 20U + (PINTSECSEL0 << PMUX_SHIFT),
357 kINPUTMUX_GpioPort0Pin21ToPintSecsel = 21U + (PINTSECSEL0 << PMUX_SHIFT),
358 kINPUTMUX_GpioPort0Pin22ToPintSecsel = 22U + (PINTSECSEL0 << PMUX_SHIFT),
359 kINPUTMUX_GpioPort0Pin23ToPintSecsel = 23U + (PINTSECSEL0 << PMUX_SHIFT),
360 kINPUTMUX_GpioPort0Pin24ToPintSecsel = 24U + (PINTSECSEL0 << PMUX_SHIFT),
361 kINPUTMUX_GpioPort0Pin25ToPintSecsel = 25U + (PINTSECSEL0 << PMUX_SHIFT),
362 kINPUTMUX_GpioPort0Pin26ToPintSecsel = 26U + (PINTSECSEL0 << PMUX_SHIFT),
363 kINPUTMUX_GpioPort0Pin27ToPintSecsel = 27U + (PINTSECSEL0 << PMUX_SHIFT),
364 kINPUTMUX_GpioPort0Pin28ToPintSecsel = 28U + (PINTSECSEL0 << PMUX_SHIFT),
365 kINPUTMUX_GpioPort0Pin29ToPintSecsel = 29U + (PINTSECSEL0 << PMUX_SHIFT),
366 kINPUTMUX_GpioPort0Pin30ToPintSecsel = 30U + (PINTSECSEL0 << PMUX_SHIFT),
367 kINPUTMUX_GpioPort0Pin31ToPintSecsel = 31U + (PINTSECSEL0 << PMUX_SHIFT),
368
369 /*!< DMA1 Input trigger. */
370 kINPUTMUX_PinInt0ToDma1 = 0U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
371 kINPUTMUX_PinInt1ToDma1 = 1U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
372 kINPUTMUX_PinInt2ToDma1 = 2U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
373 kINPUTMUX_PinInt3ToDma1 = 3U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
374 kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
375 kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
376 kINPUTMUX_Ctimer2M0ToDma1 = 6U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
377 kINPUTMUX_Ctimer4M0ToDma1 = 7U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
378 kINPUTMUX_Otrig0ToDma1 = 8U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
379 kINPUTMUX_Otrig1ToDma1 = 9U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
380 kINPUTMUX_Otrig2ToDma1 = 10U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
381 kINPUTMUX_Otrig3ToDma1 = 11U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
382 kINPUTMUX_Sct0DmaReq0ToDma1 = 12U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
383 kINPUTMUX_Sct0DmaReq1ToDma1 = 13U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
384 kINPUTMUX_HashDmaRxToDma1 = 14U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
385
386 /*!< DMA1 output trigger. */
387 kINPUTMUX_Dma1Hash0TxTrigoutToTriginChannels = 0U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
388 kINPUTMUX_Dma1HsLspiRxTrigoutToTriginChannels = 2U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
389 kINPUTMUX_Dma1HsLspiTxTrigoutToTriginChannels = 3U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
390 kINPUTMUX_Dma1Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
391 kINPUTMUX_Dma1Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
392 kINPUTMUX_Dma1Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
393 kINPUTMUX_Dma1Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
394 kINPUTMUX_Dma1Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
395 kINPUTMUX_Dma1Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
396} inputmux_connection_t;
397
398/*! @brief INPUTMUX signal enable/disable type */
399typedef enum _inputmux_signal_t
400{
401 /*!< DMA0 REQ signal. */
402 kINPUTMUX_HashCryptToDmac0Ch0RequestEna = 0U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
403 kINPUTMUX_Flexcomm8RxToDmac0Ch2RequestEna = 2U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
404 kINPUTMUX_Flexcomm8TxToDmac0Ch3RequestEna = 3U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
405 kINPUTMUX_Flexcomm0RxToDmac0Ch4RequestEna = 4U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
406 kINPUTMUX_Flexcomm0TxToDmac0Ch5RequestEna = 5U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
407 kINPUTMUX_Flexcomm1RxToDmac0Ch6RequestEna = 6U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
408 kINPUTMUX_Flexcomm1TxToDmac0Ch7RequestEna = 7U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
409 kINPUTMUX_Flexcomm3RxToDmac0Ch8RequestEna = 8U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
410 kINPUTMUX_Flexcomm3TxToDmac0Ch9RequestEna = 9U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
411 kINPUTMUX_Flexcomm2RxToDmac0Ch10RequestEna = 10U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
412 kINPUTMUX_Flexcomm2TxToDmac0Ch11RequestEna = 11U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
413 kINPUTMUX_Flexcomm4RxToDmac0Ch12RequestEna = 12U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
414 kINPUTMUX_Flexcomm4TxToDmac0Ch13RequestEna = 13U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
415 kINPUTMUX_Flexcomm5RxToDmac0Ch14RequestEna = 14U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
416 kINPUTMUX_Flexcomm5TxToDmac0Ch15RequestEna = 15U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
417 kINPUTMUX_Flexcomm6RxToDmac0Ch16RequestEna = 16U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
418 kINPUTMUX_Flexcomm6TxToDmac0Ch17RequestEna = 17U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
419 kINPUTMUX_Flexcomm7RxToDmac0Ch18RequestEna = 18U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
420 kINPUTMUX_Flexcomm7TxToDmac0Ch19RequestEna = 19U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
421 kINPUTMUX_Adc0FIFO0ToDmac0Ch21RequestEna = 21U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
422 kINPUTMUX_Adc0FIFO1ToDmac0Ch22RequestEna = 22U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
423
424 /*!< DMA1 REQ signal. */
425 kINPUTMUX_HashCryptToDmac1Ch0RequestEna = 0U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
426 kINPUTMUX_Flexcomm8RxToDmac1Ch2RequestEna = 2U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
427 kINPUTMUX_Flexcomm8TxToDmac1Ch3RequestEna = 3U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
428 kINPUTMUX_Flexcomm0RxToDmac1Ch4RequestEna = 4U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
429 kINPUTMUX_Flexcomm0TxToDmac1Ch5RequestEna = 5U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
430 kINPUTMUX_Flexcomm1RxToDmac1Ch6RequestEna = 6U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
431 kINPUTMUX_Flexcomm1TxToDmac1Ch7RequestEna = 7U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
432 kINPUTMUX_Flexcomm3RxToDmac1Ch8RequestEna = 8U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
433 kINPUTMUX_Flexcomm3TxToDmac1Ch9RequestEna = 9U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
434
435 /*!< DMA0 input trigger source enable. */
436 kINPUTMUX_Dmac0InputTriggerPint0Ena = 0U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
437 kINPUTMUX_Dmac0InputTriggerPint1Ena = 1U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
438 kINPUTMUX_Dmac0InputTriggerPint2Ena = 2U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
439 kINPUTMUX_Dmac0InputTriggerPint3Ena = 3U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
440 kINPUTMUX_Dmac0InputTriggerCtimer0M0Ena = 4U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
441 kINPUTMUX_Dmac0InputTriggerCtimer0M1Ena = 5U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
442 kINPUTMUX_Dmac0InputTriggerCtimer1M0Ena = 6U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
443 kINPUTMUX_Dmac0InputTriggerCtimer1M1Ena = 7U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
444 kINPUTMUX_Dmac0InputTriggerCtimer2M0Ena = 8U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
445 kINPUTMUX_Dmac0InputTriggerCtimer2M1Ena = 9U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
446 kINPUTMUX_Dmac0InputTriggerCtimer3M0Ena = 10U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
447 kINPUTMUX_Dmac0InputTriggerCtimer3M1Ena = 11U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
448 kINPUTMUX_Dmac0InputTriggerCtimer4M0Ena = 12U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
449 kINPUTMUX_Dmac0InputTriggerCtimer4M1Ena = 13U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
450 kINPUTMUX_Dmac0InputTriggerCompOutEna = 14U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
451 kINPUTMUX_Dmac0InputTriggerDma0Out0Ena = 15U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
452 kINPUTMUX_Dmac0InputTriggerDma0Out1Ena = 16U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
453 kINPUTMUX_Dmac0InputTriggerDma0Out2Ena = 17U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
454 kINPUTMUX_Dmac0InputTriggerDma0Out3Ena = 18U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
455 kINPUTMUX_Dmac0InputTriggerSctDmac0Ena = 19U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
456 kINPUTMUX_Dmac0InputTriggerSctDmac1Ena = 20U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
457 kINPUTMUX_Dmac0InputTriggerHashOutEna = 21U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
458
459 /*!< DMA1 input trigger source enable. */
460 kINPUTMUX_Dmac1InputTriggerPint0Ena = 0U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
461 kINPUTMUX_Dmac1InputTriggerPint1Ena = 1U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
462 kINPUTMUX_Dmac1InputTriggerPint2Ena = 2U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
463 kINPUTMUX_Dmac1InputTriggerPint3Ena = 3U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
464 kINPUTMUX_Dmac1InputTriggerCtimer0M0Ena = 4U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
465 kINPUTMUX_Dmac1InputTriggerCtimer0M1Ena = 5U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
466 kINPUTMUX_Dmac1InputTriggerCtimer2M0Ena = 6U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
467 kINPUTMUX_Dmac1InputTriggerCtimer4M0Ena = 7U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
468 kINPUTMUX_Dmac1InputTriggerDma1Out0Ena = 8U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
469 kINPUTMUX_Dmac1InputTriggerDma1Out1Ena = 9U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
470 kINPUTMUX_Dmac1InputTriggerDma1Out2Ena = 10U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
471 kINPUTMUX_Dmac1InputTriggerDma1Out3Ena = 11U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
472 kINPUTMUX_Dmac1InputTriggerSctDmac0Ena = 12U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
473 kINPUTMUX_Dmac1InputTriggerSctDmac1Ena = 13U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
474 kINPUTMUX_Dmac1InputTriggerHashOutEna = 14U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
475} inputmux_signal_t;
476
477/*@}*/
478
479/*@}*/
480
481#endif /* _FSL_INPUTMUX_CONNECTIONS_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_power.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_power.c
new file mode 100644
index 000000000..a0b833175
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_power.c
@@ -0,0 +1,19 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8#include "fsl_common.h"
9#include "fsl_power.h"
10/* Component ID definition, used by tools. */
11#ifndef FSL_COMPONENT_ID
12#define FSL_COMPONENT_ID "platform.drivers.power"
13#endif
14
15/*******************************************************************************
16 * Code
17 ******************************************************************************/
18
19/* Empty file since implementation is in header file and power library */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_power.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_power.h
new file mode 100644
index 000000000..3c3975fa8
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5512/drivers/fsl_power.h
@@ -0,0 +1,603 @@
1/*
2 * Copyright 2017, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7#ifndef _FSL_POWER_H_
8#define _FSL_POWER_H_
9
10#include "fsl_common.h"
11#include "fsl_device_registers.h"
12#include <stdint.h>
13
14/*!
15 * @addtogroup power
16 * @{
17 */
18/*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22/*! @name Driver version */
23/*@{*/
24/*! @brief power driver version 1.0.0. */
25#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
26/*@}*/
27
28/* Power mode configuration API parameter */
29typedef enum _power_mode_config
30{
31 kPmu_Sleep = 0U,
32 kPmu_Deep_Sleep = 1U,
33 kPmu_PowerDown = 2U,
34 kPmu_Deep_PowerDown = 3U,
35} power_mode_cfg_t;
36
37/**
38 * @brief Analog components power modes control during low power modes
39 */
40typedef enum pd_bits
41{
42 kPDRUNCFG_PD_BODCORE = (1UL << 2),
43 kPDRUNCFG_PD_BODVBAT = (1UL << 3),
44 kPDRUNCFG_PD_FRO1M = (1UL << 4),
45 kPDRUNCFG_PD_FRO192M = (1UL << 5),
46 kPDRUNCFG_PD_FRO32K = (1UL << 6),
47 kPDRUNCFG_PD_XTAL32K = (1UL << 7),
48 kPDRUNCFG_PD_XTAL32M = (1UL << 8),
49 kPDRUNCFG_PD_PLL0 = (1UL << 9),
50 kPDRUNCFG_PD_PLL1 = (1UL << 10),
51 kPDRUNCFG_PD_USB0_PHY = (1UL << 11),
52 kPDRUNCFG_PD_USB1_PHY = (1UL << 12),
53 kPDRUNCFG_PD_COMP = (1UL << 13),
54 kPDRUNCFG_PD_GPADC = (1UL << 15),
55 kPDRUNCFG_PD_LDOUSBHS = (1UL << 18),
56 kPDRUNCFG_PD_LDOGPADC = (1UL << 19),
57 kPDRUNCFG_PD_LDOXO32M = (1UL << 20),
58 kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21),
59 kPDRUNCFG_PD_RNG = (1UL << 22),
60 kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23),
61 /*
62 This enum member has no practical meaning,it is used to avoid MISRA issue,
63 user should not trying to use it.
64 */
65 kPDRUNCFG_ForceUnsigned = 0x80000000U,
66} pd_bit_t;
67
68/**
69 * @brief BOD VBAT level
70 */
71typedef enum _power_bod_vbat_level
72{
73 kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */
74 kPOWER_BodVbatLevel1100mv = 1, /*!< Brown out detector VBAT level 1.1V */
75 kPOWER_BodVbatLevel1200mv = 2, /*!< Brown out detector VBAT level 1.2V */
76 kPOWER_BodVbatLevel1300mv = 3, /*!< Brown out detector VBAT level 1.3V */
77 kPOWER_BodVbatLevel1400mv = 4, /*!< Brown out detector VBAT level 1.4V */
78 kPOWER_BodVbatLevel1500mv = 5, /*!< Brown out detector VBAT level 1.5V */
79 kPOWER_BodVbatLevel1600mv = 6, /*!< Brown out detector VBAT level 1.6V */
80 kPOWER_BodVbatLevel1650mv = 7, /*!< Brown out detector VBAT level 1.65V */
81 kPOWER_BodVbatLevel1700mv = 8, /*!< Brown out detector VBAT level 1.7V */
82 kPOWER_BodVbatLevel1750mv = 9, /*!< Brown out detector VBAT level 1.75V */
83 kPOWER_BodVbatLevel1800mv = 10, /*!< Brown out detector VBAT level 1.8V */
84 kPOWER_BodVbatLevel1900mv = 11, /*!< Brown out detector VBAT level 1.9V */
85 kPOWER_BodVbatLevel2000mv = 12, /*!< Brown out detector VBAT level 2V */
86 kPOWER_BodVbatLevel2100mv = 13, /*!< Brown out detector VBAT level 2.1V */
87 kPOWER_BodVbatLevel2200mv = 14, /*!< Brown out detector VBAT level 2.2V */
88 kPOWER_BodVbatLevel2300mv = 15, /*!< Brown out detector VBAT level 2.3V */
89 kPOWER_BodVbatLevel2400mv = 16, /*!< Brown out detector VBAT level 2.4V */
90 kPOWER_BodVbatLevel2500mv = 17, /*!< Brown out detector VBAT level 2.5V */
91 kPOWER_BodVbatLevel2600mv = 18, /*!< Brown out detector VBAT level 2.6V */
92 kPOWER_BodVbatLevel2700mv = 19, /*!< Brown out detector VBAT level 2.7V */
93 kPOWER_BodVbatLevel2806mv = 20, /*!< Brown out detector VBAT level 2.806V */
94 kPOWER_BodVbatLevel2900mv = 21, /*!< Brown out detector VBAT level 2.9V */
95 kPOWER_BodVbatLevel3000mv = 22, /*!< Brown out detector VBAT level 3.0V */
96 kPOWER_BodVbatLevel3100mv = 23, /*!< Brown out detector VBAT level 3.1V */
97 kPOWER_BodVbatLevel3200mv = 24, /*!< Brown out detector VBAT level 3.2V */
98 kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */
99} power_bod_vbat_level_t;
100
101/**
102 * @brief BOD Hysteresis control
103 */
104typedef enum _power_bod_hyst
105{
106 kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */
107 kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */
108 kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */
109 kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */
110} power_bod_hyst_t;
111/**
112 * @brief BOD core level
113 */
114typedef enum _power_bod_core_level
115{
116 kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */
117 kPOWER_BodCoreLevel650mv = 1, /*!< Brown out detector core level 650mV */
118 kPOWER_BodCoreLevel700mv = 2, /*!< Brown out detector core level 700mV */
119 kPOWER_BodCoreLevel750mv = 3, /*!< Brown out detector core level 750mV */
120 kPOWER_BodCoreLevel800mv = 4, /*!< Brown out detector core level 800mV */
121 kPOWER_BodCoreLevel850mv = 5, /*!< Brown out detector core level 850mV */
122 kPOWER_BodCoreLevel900mv = 6, /*!< Brown out detector core level 900mV */
123 kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */
124} power_bod_core_level_t;
125
126/**
127 * @brief Device Reset Causes
128 */
129typedef enum _power_device_reset_cause
130{
131 kRESET_CAUSE_POR = 0UL, /*!< Power On Reset */
132 kRESET_CAUSE_PADRESET = 1UL, /*!< Hardware Pin Reset */
133 kRESET_CAUSE_BODRESET = 2UL, /*!< Brown-out Detector reset (either BODVBAT or BODCORE) */
134 kRESET_CAUSE_ARMSYSTEMRESET = 3UL, /*!< ARM System Reset */
135 kRESET_CAUSE_WDTRESET = 4UL, /*!< Watchdog Timer Reset */
136 kRESET_CAUSE_SWRRESET = 5UL, /*!< Software Reset */
137 kRESET_CAUSE_CDOGRESET = 6UL, /*!< Code Watchdog Reset */
138 /* Reset causes in DEEP-POWER-DOWN low power mode */
139 kRESET_CAUSE_DPDRESET_WAKEUPIO = 7UL, /*!< Any of the 4 wake-up pins */
140 kRESET_CAUSE_DPDRESET_RTC = 8UL, /*!< Real Time Counter (RTC) */
141 kRESET_CAUSE_DPDRESET_OSTIMER = 9UL, /*!< OS Event Timer (OSTIMER) */
142 kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC = 10UL, /*!< Any of the 4 wake-up pins and RTC (it is not possible to distinguish
143 which of these 2 events occured first) */
144 kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER = 11UL, /*!< Any of the 4 wake-up pins and OSTIMER (it is not possible to
145 distinguish which of these 2 events occured first) */
146 kRESET_CAUSE_DPDRESET_RTC_OSTIMER = 12UL, /*!< Real Time Counter or OS Event Timer (it is not possible to
147 distinguish which of these 2 events occured first) */
148 kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER = 13UL, /*!< Any of the 4 wake-up pins (it is not possible to distinguish
149 which of these 3 events occured first) */
150 /* Miscallenous */
151 kRESET_CAUSE_NOT_RELEVANT =
152 14UL, /*!< No reset cause (for example, this code is used when waking up from DEEP-SLEEP low power mode) */
153 kRESET_CAUSE_NOT_DETERMINISTIC = 15UL, /*!< Unknown Reset Cause. Should be treated like "Hardware Pin Reset" from an
154 application point of view. */
155} power_device_reset_cause_t;
156
157/**
158 * @brief Device Boot Modes
159 */
160typedef enum _power_device_boot_mode
161{
162 kBOOT_MODE_POWER_UP =
163 0UL, /*!< All non Low Power Mode wake up (Power On Reset, Pin Reset, BoD Reset, ARM System Reset ... ) */
164 kBOOT_MODE_LP_DEEP_SLEEP = 1UL, /*!< Wake up from DEEP-SLEEP Low Power mode */
165 kBOOT_MODE_LP_POWER_DOWN = 2UL, /*!< Wake up from POWER-DOWN Low Power mode */
166 kBOOT_MODE_LP_DEEP_POWER_DOWN = 4UL, /*!< Wake up from DEEP-POWER-DOWN Low Power mode */
167} power_device_boot_mode_t;
168
169/**
170 * @brief SRAM instances retention control during low power modes
171 */
172#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 \
173 (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */
174#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 \
175 (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */
176#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 \
177 (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */
178#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 \
179 (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */
180#define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 \
181 (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */
182#define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 \
183 (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */
184#define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 \
185 (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */
186#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS \
187 (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */
188
189/**
190 * @brief Low Power Modes Wake up sources
191 */
192#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/
193#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */
194#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
195#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
196#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */
197#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */
198#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */
199#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */
200#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */
201#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */
202#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */
203#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */
204#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */
205#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */
206#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */
207#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */
208#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */
209#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
210#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */
211#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */
212#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */
213#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */
214#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */
215// reserved (1ULL << 23)
216#define WAKEUP_ACMP (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
217// reserved (1ULL << 25)
218// reserved (1ULL << 26)
219#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */
220#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */
221#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */
222// reserved (1ULL << 30)
223// reserved (1ULL << 31)
224#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */
225#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */
226#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */
227#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */
228#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */
229#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */
230#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */
231// reserved (1ULL << 39)
232// reserved (1ULL << 40)
233// reserved (1ULL << 41)
234// reserved (1ULL << 42)
235#define CAN0_INT0 (1ULL << 43) /*!< [SLEEP, ] */
236#define CAN1_INT0 (1ULL << 44) /*!< [SLEEP, ] */
237// reserved (1ULL << 45)
238// reserved (1ULL << 46)
239#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */
240#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */
241#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */
242#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */
243#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */
244#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */
245#define WAKEUP_SEC_VIO (1ULL << 53)
246#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */
247#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */
248#define WAKEUP_PUF (1ULL << 56) /*!< [SLEEP, ] */
249// reserved (1ULL << 57)
250#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */
251#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */
252//#define CDOG (1ULL << 60) !< [SLEEP, ]
253// reserved (1ULL << 61)
254// reserved (1ULL << 62)
255#define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */
256
257/**
258 * @brief Sleep Postpone
259 */
260#define LOWPOWER_HWWAKE_PERIPHERALS \
261 (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \
262 peripheral clocking to wake up temporarily while the related status is asserted */
263#define LOWPOWER_HWWAKE_SDMA0 \
264 (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA \
265 completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */
266#define LOWPOWER_HWWAKE_SDMA1 \
267 (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA \
268 completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */
269
270#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */
271#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */
272/**
273 * @brief Wake up I/O sources
274 */
275#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */
276#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */
277#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */
278#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */
279
280#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */
281#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */
282#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */
283#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */
284
285#define LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX 12 /*!< Pin P1( 1) */
286#define LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX 14 /*!< Pin P0(28) */
287#define LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX 16 /*!< Pin P1(18) */
288#define LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX 18 /*!< Pin P1(30) */
289
290#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN 0 /*!< Wake up Pad is plain input */
291#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN 1 /*!< Wake up Pad is pull-down */
292#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP 2 /*!< Wake up Pad is pull-up */
293#define LOWPOWER_WAKEUPIOSRC_IO_MODE_REPEATER 3 /*!< Wake up Pad is in repeater */
294
295#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 8 /*!< Wake-up I/O 0 pull-up/down configuration index */
296#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 9 /*!< Wake-up I/O 1 pull-up/down configuration index */
297#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 10 /*!< Wake-up I/O 2 pull-up/down configuration index */
298#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 11 /*!< Wake-up I/O 3 pull-up/down configuration index */