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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5514/drivers/fsl_power.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5514/drivers/fsl_power.h
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1/*
2 * Copyright 2017, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7#ifndef _FSL_POWER_H_
8#define _FSL_POWER_H_
9
10#include "fsl_common.h"
11#include "fsl_device_registers.h"
12#include <stdint.h>
13
14/*!
15 * @addtogroup power
16 * @{
17 */
18/*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22/*! @name Driver version */
23/*@{*/
24/*! @brief power driver version 1.0.0. */
25#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
26/*@}*/
27
28/* Power mode configuration API parameter */
29typedef enum _power_mode_config
30{
31 kPmu_Sleep = 0U,
32 kPmu_Deep_Sleep = 1U,
33 kPmu_PowerDown = 2U,
34 kPmu_Deep_PowerDown = 3U,
35} power_mode_cfg_t;
36
37/**
38 * @brief Analog components power modes control during low power modes
39 */
40typedef enum pd_bits
41{
42 kPDRUNCFG_PD_BODCORE = (1UL << 2),
43 kPDRUNCFG_PD_BODVBAT = (1UL << 3),
44 kPDRUNCFG_PD_FRO1M = (1UL << 4),
45 kPDRUNCFG_PD_FRO192M = (1UL << 5),
46 kPDRUNCFG_PD_FRO32K = (1UL << 6),
47 kPDRUNCFG_PD_XTAL32K = (1UL << 7),
48 kPDRUNCFG_PD_XTAL32M = (1UL << 8),
49 kPDRUNCFG_PD_PLL0 = (1UL << 9),
50 kPDRUNCFG_PD_PLL1 = (1UL << 10),
51 kPDRUNCFG_PD_USB0_PHY = (1UL << 11),
52 kPDRUNCFG_PD_USB1_PHY = (1UL << 12),
53 kPDRUNCFG_PD_COMP = (1UL << 13),
54 kPDRUNCFG_PD_GPADC = (1UL << 15),
55 kPDRUNCFG_PD_LDOUSBHS = (1UL << 18),
56 kPDRUNCFG_PD_LDOGPADC = (1UL << 19),
57 kPDRUNCFG_PD_LDOXO32M = (1UL << 20),
58 kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21),
59 kPDRUNCFG_PD_RNG = (1UL << 22),
60 kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23),
61 /*
62 This enum member has no practical meaning,it is used to avoid MISRA issue,
63 user should not trying to use it.
64 */
65 kPDRUNCFG_ForceUnsigned = 0x80000000U,
66} pd_bit_t;
67
68/**
69 * @brief BOD VBAT level
70 */
71typedef enum _power_bod_vbat_level
72{
73 kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */
74 kPOWER_BodVbatLevel1100mv = 1, /*!< Brown out detector VBAT level 1.1V */
75 kPOWER_BodVbatLevel1200mv = 2, /*!< Brown out detector VBAT level 1.2V */
76 kPOWER_BodVbatLevel1300mv = 3, /*!< Brown out detector VBAT level 1.3V */
77 kPOWER_BodVbatLevel1400mv = 4, /*!< Brown out detector VBAT level 1.4V */
78 kPOWER_BodVbatLevel1500mv = 5, /*!< Brown out detector VBAT level 1.5V */
79 kPOWER_BodVbatLevel1600mv = 6, /*!< Brown out detector VBAT level 1.6V */
80 kPOWER_BodVbatLevel1650mv = 7, /*!< Brown out detector VBAT level 1.65V */
81 kPOWER_BodVbatLevel1700mv = 8, /*!< Brown out detector VBAT level 1.7V */
82 kPOWER_BodVbatLevel1750mv = 9, /*!< Brown out detector VBAT level 1.75V */
83 kPOWER_BodVbatLevel1800mv = 10, /*!< Brown out detector VBAT level 1.8V */
84 kPOWER_BodVbatLevel1900mv = 11, /*!< Brown out detector VBAT level 1.9V */
85 kPOWER_BodVbatLevel2000mv = 12, /*!< Brown out detector VBAT level 2V */
86 kPOWER_BodVbatLevel2100mv = 13, /*!< Brown out detector VBAT level 2.1V */
87 kPOWER_BodVbatLevel2200mv = 14, /*!< Brown out detector VBAT level 2.2V */
88 kPOWER_BodVbatLevel2300mv = 15, /*!< Brown out detector VBAT level 2.3V */
89 kPOWER_BodVbatLevel2400mv = 16, /*!< Brown out detector VBAT level 2.4V */
90 kPOWER_BodVbatLevel2500mv = 17, /*!< Brown out detector VBAT level 2.5V */
91 kPOWER_BodVbatLevel2600mv = 18, /*!< Brown out detector VBAT level 2.6V */
92 kPOWER_BodVbatLevel2700mv = 19, /*!< Brown out detector VBAT level 2.7V */
93 kPOWER_BodVbatLevel2806mv = 20, /*!< Brown out detector VBAT level 2.806V */
94 kPOWER_BodVbatLevel2900mv = 21, /*!< Brown out detector VBAT level 2.9V */
95 kPOWER_BodVbatLevel3000mv = 22, /*!< Brown out detector VBAT level 3.0V */
96 kPOWER_BodVbatLevel3100mv = 23, /*!< Brown out detector VBAT level 3.1V */
97 kPOWER_BodVbatLevel3200mv = 24, /*!< Brown out detector VBAT level 3.2V */
98 kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */
99} power_bod_vbat_level_t;
100
101/**
102 * @brief BOD Hysteresis control
103 */
104typedef enum _power_bod_hyst
105{
106 kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */
107 kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */
108 kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */
109 kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */
110} power_bod_hyst_t;
111/**
112 * @brief BOD core level
113 */
114typedef enum _power_bod_core_level
115{
116 kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */
117 kPOWER_BodCoreLevel650mv = 1, /*!< Brown out detector core level 650mV */
118 kPOWER_BodCoreLevel700mv = 2, /*!< Brown out detector core level 700mV */
119 kPOWER_BodCoreLevel750mv = 3, /*!< Brown out detector core level 750mV */
120 kPOWER_BodCoreLevel800mv = 4, /*!< Brown out detector core level 800mV */
121 kPOWER_BodCoreLevel850mv = 5, /*!< Brown out detector core level 850mV */
122 kPOWER_BodCoreLevel900mv = 6, /*!< Brown out detector core level 900mV */
123 kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */
124} power_bod_core_level_t;
125
126/**
127 * @brief Device Reset Causes
128 */
129typedef enum _power_device_reset_cause
130{
131 kRESET_CAUSE_POR = 0UL, /*!< Power On Reset */
132 kRESET_CAUSE_PADRESET = 1UL, /*!< Hardware Pin Reset */
133 kRESET_CAUSE_BODRESET = 2UL, /*!< Brown-out Detector reset (either BODVBAT or BODCORE) */
134 kRESET_CAUSE_ARMSYSTEMRESET = 3UL, /*!< ARM System Reset */
135 kRESET_CAUSE_WDTRESET = 4UL, /*!< Watchdog Timer Reset */
136 kRESET_CAUSE_SWRRESET = 5UL, /*!< Software Reset */
137 kRESET_CAUSE_CDOGRESET = 6UL, /*!< Code Watchdog Reset */
138 /* Reset causes in DEEP-POWER-DOWN low power mode */
139 kRESET_CAUSE_DPDRESET_WAKEUPIO = 7UL, /*!< Any of the 4 wake-up pins */
140 kRESET_CAUSE_DPDRESET_RTC = 8UL, /*!< Real Time Counter (RTC) */
141 kRESET_CAUSE_DPDRESET_OSTIMER = 9UL, /*!< OS Event Timer (OSTIMER) */
142 kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC = 10UL, /*!< Any of the 4 wake-up pins and RTC (it is not possible to distinguish
143 which of these 2 events occured first) */
144 kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER = 11UL, /*!< Any of the 4 wake-up pins and OSTIMER (it is not possible to
145 distinguish which of these 2 events occured first) */
146 kRESET_CAUSE_DPDRESET_RTC_OSTIMER = 12UL, /*!< Real Time Counter or OS Event Timer (it is not possible to
147 distinguish which of these 2 events occured first) */
148 kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER = 13UL, /*!< Any of the 4 wake-up pins (it is not possible to distinguish
149 which of these 3 events occured first) */
150 /* Miscallenous */
151 kRESET_CAUSE_NOT_RELEVANT =
152 14UL, /*!< No reset cause (for example, this code is used when waking up from DEEP-SLEEP low power mode) */
153 kRESET_CAUSE_NOT_DETERMINISTIC = 15UL, /*!< Unknown Reset Cause. Should be treated like "Hardware Pin Reset" from an
154 application point of view. */
155} power_device_reset_cause_t;
156
157/**
158 * @brief Device Boot Modes
159 */
160typedef enum _power_device_boot_mode
161{
162 kBOOT_MODE_POWER_UP =
163 0UL, /*!< All non Low Power Mode wake up (Power On Reset, Pin Reset, BoD Reset, ARM System Reset ... ) */
164 kBOOT_MODE_LP_DEEP_SLEEP = 1UL, /*!< Wake up from DEEP-SLEEP Low Power mode */
165 kBOOT_MODE_LP_POWER_DOWN = 2UL, /*!< Wake up from POWER-DOWN Low Power mode */
166 kBOOT_MODE_LP_DEEP_POWER_DOWN = 4UL, /*!< Wake up from DEEP-POWER-DOWN Low Power mode */
167} power_device_boot_mode_t;
168
169/**
170 * @brief SRAM instances retention control during low power modes
171 */
172#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 \
173 (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */
174#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 \
175 (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */
176#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 \
177 (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */
178#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 \
179 (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */
180#define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 \
181 (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */
182#define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 \
183 (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */
184#define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 \
185 (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */
186#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS \
187 (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */
188
189/**
190 * @brief Low Power Modes Wake up sources
191 */
192#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/
193#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */
194#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
195#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
196#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */
197#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */
198#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */
199#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */
200#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */
201#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */
202#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */
203#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */
204#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */
205#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */
206#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */
207#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */
208#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */
209#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
210#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */
211#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */
212#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */
213#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */
214#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */
215// reserved (1ULL << 23)
216#define WAKEUP_ACMP (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
217// reserved (1ULL << 25)
218// reserved (1ULL << 26)
219#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */
220#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */
221#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */
222// reserved (1ULL << 30)
223// reserved (1ULL << 31)
224#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */
225#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */
226#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */
227#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */
228#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */
229#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */
230#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */
231// reserved (1ULL << 39)
232// reserved (1ULL << 40)
233// reserved (1ULL << 41)
234// reserved (1ULL << 42)
235#define CAN0_INT0 (1ULL << 43) /*!< [SLEEP, ] */
236#define CAN1_INT0 (1ULL << 44) /*!< [SLEEP, ] */
237// reserved (1ULL << 45)
238// reserved (1ULL << 46)
239#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */
240#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */
241#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */
242#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */
243#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */
244#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */
245#define WAKEUP_SEC_VIO (1ULL << 53)
246#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */
247#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */
248#define WAKEUP_PUF (1ULL << 56) /*!< [SLEEP, ] */
249// reserved (1ULL << 57)
250#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */
251#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */
252//#define CDOG (1ULL << 60) !< [SLEEP, ]
253// reserved (1ULL << 61)
254// reserved (1ULL << 62)
255#define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */
256
257/**
258 * @brief Sleep Postpone
259 */
260#define LOWPOWER_HWWAKE_PERIPHERALS \
261 (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \
262 peripheral clocking to wake up temporarily while the related status is asserted */
263#define LOWPOWER_HWWAKE_SDMA0 \
264 (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA \
265 completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */
266#define LOWPOWER_HWWAKE_SDMA1 \
267 (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA \
268 completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */
269
270#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */
271#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */
272/**
273 * @brief Wake up I/O sources
274 */
275#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */
276#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */
277#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */
278#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */
279
280#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */
281#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */
282#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */
283#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */
284
285#define LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX 12 /*!< Pin P1( 1) */
286#define LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX 14 /*!< Pin P0(28) */
287#define LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX 16 /*!< Pin P1(18) */
288#define LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX 18 /*!< Pin P1(30) */
289
290#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN 0 /*!< Wake up Pad is plain input */
291#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN 1 /*!< Wake up Pad is pull-down */
292#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP 2 /*!< Wake up Pad is pull-up */
293#define LOWPOWER_WAKEUPIOSRC_IO_MODE_REPEATER 3 /*!< Wake up Pad is in repeater */
294
295#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 8 /*!< Wake-up I/O 0 pull-up/down configuration index */
296#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 9 /*!< Wake-up I/O 1 pull-up/down configuration index */
297#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 10 /*!< Wake-up I/O 2 pull-up/down configuration index */
298#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 11 /*!< Wake-up I/O 3 pull-up/down configuration index */
299
300#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK \
301 (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */
302#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK \
303 (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */
304#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK \
305 (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */
306#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK \
307 (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */
308
309#define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */
310#define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */
311
312#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX \
313 12 /*!< Wake-up I/O 0 pull-up/down disable/enable control index */
314#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX \
315 13 /*!< Wake-up I/O 1 pull-up/down disable/enable control index */
316#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX \
317 14 /*!< Wake-up I/O 2 pull-up/down disable/enable control index */
318#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX \
319 15 /*!< Wake-up I/O 3 pull-up/down disable/enable control index */
320#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK \
321 (1UL << LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down disable/enable mask */
322#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK \
323 (1UL << LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down disable/enable mask */
324#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK \
325 (1UL << LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down disable/enable mask */
326#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \
327 (1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */
328
329#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX \
330 (16) /*!< Wake-up I/O 0 use external pull-up/down disable/enable control index*/
331#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX \
332 (17) /*!< Wake-up I/O 1 use external pull-up/down disable/enable control index */
333#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX \
334 (18) /*!< Wake-up I/O 2 use external pull-up/down disable/enable control index */
335#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX \
336 (19) /*!< Wake-up I/O 3 use external pull-up/down disable/enable control index */
337#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK \
338 (1UL << LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 use external pull-up/down \
339 disable/enable mask, 0: disable, 1: enable */
340#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK \
341 (1UL << LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 use external pull-up/down \
342 disable/enable mask, 0: disable, 1: enable */
343#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK \
344 (1UL << LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 use external pull-up/down \
345 disable/enable mask, 0: disable, 1: enable */
346#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK \
347 (1UL << LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 use external pull-up/down \
348 disable/enable mask, 0: disable, 1: enable */
349
350#ifdef __cplusplus
351extern "C" {
352#endif
353/*******************************************************************************
354 * API
355 ******************************************************************************/
356
357/*!
358 * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
359 *
360 * @param en peripheral for which to enable the PDRUNCFG bit
361 * @return none
362 */
363static inline void POWER_EnablePD(pd_bit_t en)
364{
365 /* PDRUNCFGSET */
366 PMC->PDRUNCFGSET0 = (uint32_t)en;
367}
368
369/*!
370 * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
371 *
372 * @param en peripheral for which to disable the PDRUNCFG bit
373 * @return none
374 */
375static inline void POWER_DisablePD(pd_bit_t en)
376{
377 /* PDRUNCFGCLR */
378 PMC->PDRUNCFGCLR0 = (uint32_t)en;
379}
380
381/*!
382 * @brief set BOD VBAT level.
383 *
384 * @param level BOD detect level
385 * @param hyst BoD Hysteresis control
386 * @param enBodVbatReset VBAT brown out detect reset
387 */
388void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset);
389
390#if defined(PMC_BODCORE_TRIGLVL_MASK)
391/*!
392 * @brief set BOD core level.
393 *
394 * @param level BOD detect level
395 * @param hyst BoD Hysteresis control
396 * @param enBodCoreReset core brown out detect reset
397 */
398void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset);
399#endif
400
401/*!
402 * @brief API to enable deep sleep bit in the ARM Core.
403 *
404 * @return none
405 */
406static inline void POWER_EnableDeepSleep(void)
407{
408 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
409}
410
411/*!
412 * @brief API to disable deep sleep bit in the ARM Core.
413 *
414 * @return none
415 */
416static inline void POWER_DisableDeepSleep(void)
417{
418 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
419}
420
421/**
422 * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event
423 * This MUST BE EXECUTED outside the Flash:
424 * either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is
425 * preferable to have all functions defined in this file implemented in ROM.
426 *
427 * @return Nothing
428 */
429void POWER_CycleCpuAndFlash(void);
430
431/**
432 * @brief Configures and enters in DEEP-SLEEP low power mode
433 * @param exclude_from_pd:
434 * @param sram_retention_ctrl:
435 * @param wakeup_interrupts:
436 * @param hardware_wake_ctrl:
437
438 * @return Nothing
439 *
440 * !!! IMPORTANT NOTES :
441 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.
442 * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in
443 case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending).
444 * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be
445 restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
446 * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip
447 reset) reset)
448 */
449void POWER_EnterDeepSleep(uint32_t exclude_from_pd,
450 uint32_t sram_retention_ctrl,
451 uint64_t wakeup_interrupts,
452 uint32_t hardware_wake_ctrl);
453
454/**
455 * @brief Configures and enters in POWERDOWN low power mode
456 * @param exclude_from_pd:
457 * @param sram_retention_ctrl:
458 * @param wakeup_interrupts:
459 * @param cpu_retention_ctrl: 0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are
460 RESERVED.
461
462 * @return Nothing
463 *
464 * !!! IMPORTANT NOTES :
465 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.
466 * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in
467 case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending).
468 * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be
469 restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
470 * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance
471 containing the stack used to call this function WILL BE preserved during low power (via parameter
472 "sram_retention_ctrl")
473 * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip
474 reset) reset)
475 */
476
477void POWER_EnterPowerDown(uint32_t exclude_from_pd,
478 uint32_t sram_retention_ctrl,
479 uint64_t wakeup_interrupts,
480 uint32_t cpu_retention_ctrl);
481
482/**
483 * @brief Configures and enters in DEEPPOWERDOWN low power mode
484 * @param exclude_from_pd:
485 * @param sram_retention_ctrl:
486 * @param wakeup_interrupts:
487 * @param wakeup_io_ctrl:
488
489 * @return Nothing
490 *
491 * !!! IMPORTANT NOTES :
492 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.
493 * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if
494 DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
495 * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be
496 restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
497 * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip
498 reset)
499 */
500void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd,
501 uint32_t sram_retention_ctrl,
502 uint64_t wakeup_interrupts,
503 uint32_t wakeup_io_ctrl);
504
505/**
506 * @brief Configures and enters in SLEEP low power mode
507 *
508 * @return Nothing
509 */
510void POWER_EnterSleep(void);
511
512/*!
513 * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
514 *
515 * @param system_freq_hz - The desired frequency (in Hertz) at which the part would like to operate,
516 * note that the voltage and flash wait states should be set before changing frequency
517 * @return none
518 */
519void POWER_SetVoltageForFreq(uint32_t system_freq_hz);
520
521/*!
522 * @brief Power Library API to return the library version.
523 *
524 * @return version number of the power library
525 */
526uint32_t POWER_GetLibVersion(void);
527
528/**
529 * @brief Sets board-specific trim values for 16MHz XTAL
530 * @param pi32_16MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
531 * @param pi32_16MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
532 * becomes 120
533 * @param pi32_16MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
534 * becomes 120
535 * @return none
536 * @note Following default Values can be used:
537 * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600
538 * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20
539 * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40
540 */
541extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100,
542 int32_t pi32_16MfXtalPPcbParCappF_x100,
543 int32_t pi32_16MfXtalNPcbParCappF_x100);
544/**
545 * @brief Sets board-specific trim values for 32kHz XTAL
546 * @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
547 * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
548 becomes 120
549 * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
550 becomes 120
551
552 * @return none
553 * @note Following default Values can be used:
554 * pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600
555 * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40
556 * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40
557 */
558extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100,
559 int32_t pi32_32kfXtalPPcbParCappF_x100,
560 int32_t pi32_32kfXtalNPcbParCappF_x100);
561/**
562 * @brief Enables and sets LDO for 16MHz XTAL
563 * @return none
564 */
565extern void POWER_SetXtal16mhzLdo(void);
566
567/**
568 * @brief Set up 16-MHz XTAL Trimmings
569 * @param amp Amplitude
570 * @param gm Transconductance
571 * @return none
572 */
573extern void POWER_SetXtal16mhzTrim(uint32_t amp, uint32_t gm);
574
575/**
576 * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes.
577 * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t type.
578 * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type.
579 * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0].
580
581 * @return Nothing
582 *
583 * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!!
584 * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!!
585 * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!!
586 * - 1. p_wakeupio_cause is NOT ACCURATE
587 * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when
588 * several wake-up sources are enabled during DEEP-POWER-DOWN
589 * (like enabling wake-up on RTC and Falling edge wake-up pins)
590 *
591 */
592void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause,
593 power_device_boot_mode_t *p_boot_mode,
594 uint32_t *p_wakeupio_cause);
595#ifdef __cplusplus
596}
597#endif
598
599/**
600 * @}
601 */
602
603#endif /* _FSL_POWER_H_ */
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