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1/*
2** ###################################################################
3** Processors: LPC5526JBD100
4** LPC5526JBD64
5** LPC5526JEV98
6**
7** Compilers: GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9** Keil ARM C/C++ Compiler
10** MCUXpresso Compiler
11**
12** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
13** Version: rev. 1.1, 2019-05-16
14** Build: b200928
15**
16** Abstract:
17** CMSIS Peripheral Access Layer for LPC5526
18**
19** Copyright 1997-2016 Freescale Semiconductor, Inc.
20** Copyright 2016-2020 NXP
21** All rights reserved.
22**
23** SPDX-License-Identifier: BSD-3-Clause
24**
25** http: www.nxp.com
26** mail: [email protected]
27**
28** Revisions:
29** - rev. 1.0 (2018-08-22)
30** Initial version based on v0.2UM
31** - rev. 1.1 (2019-05-16)
32** Initial A1 version based on v1.3UM
33**
34** ###################################################################
35*/
36
37/*!
38 * @file LPC5526.h
39 * @version 1.1
40 * @date 2019-05-16
41 * @brief CMSIS Peripheral Access Layer for LPC5526
42 *
43 * CMSIS Peripheral Access Layer for LPC5526
44 */
45
46#ifndef _LPC5526_H_
47#define _LPC5526_H_ /**< Symbol preventing repeated inclusion */
48
49/** Memory map major version (memory maps with equal major version number are
50 * compatible) */
51#define MCU_MEM_MAP_VERSION 0x0100U
52/** Memory map minor version */
53#define MCU_MEM_MAP_VERSION_MINOR 0x0001U
54
55
56/* ----------------------------------------------------------------------------
57 -- Interrupt vector numbers
58 ---------------------------------------------------------------------------- */
59
60/*!
61 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
62 * @{
63 */
64
65/** Interrupt Number Definitions */
66#define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */
67
68typedef enum IRQn {
69 /* Auxiliary constants */
70 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
71
72 /* Core interrupts */
73 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
74 HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */
75 MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */
76 BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */
77 UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */
78 SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */
79 SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */
80 DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */
81 PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */
82 SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */
83
84 /* Device specific interrupts */
85 WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */
86 DMA0_IRQn = 1, /**< DMA0 controller */
87 GINT0_IRQn = 2, /**< GPIO group 0 */
88 GINT1_IRQn = 3, /**< GPIO group 1 */
89 PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */
90 PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */
91 PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */
92 PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */
93 UTICK0_IRQn = 8, /**< Micro-tick Timer */
94 MRT0_IRQn = 9, /**< Multi-rate timer */
95 CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
96 CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
97 SCT0_IRQn = 12, /**< SCTimer/PWM */
98 CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
99 FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
100 FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
101 FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
102 FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
103 FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
104 FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
105 FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
106 FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
107 ADC0_IRQn = 22, /**< ADC0 */
108 Reserved39_IRQn = 23, /**< Reserved interrupt */
109 ACMP_IRQn = 24, /**< ACMP interrupts */
110 Reserved41_IRQn = 25, /**< Reserved interrupt */
111 Reserved42_IRQn = 26, /**< Reserved interrupt */
112 USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */
113 USB0_IRQn = 28, /**< USB device */
114 RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */
115 Reserved46_IRQn = 30, /**< Reserved interrupt */
116 Reserved47_IRQn = 31, /**< Reserved interrupt */
117 PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */
118 PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */
119 PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */
120 PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */
121 CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */
122 CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */
123 OS_EVENT_IRQn = 38, /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
124 Reserved55_IRQn = 39, /**< Reserved interrupt */
125 Reserved56_IRQn = 40, /**< Reserved interrupt */
126 Reserved57_IRQn = 41, /**< Reserved interrupt */
127 SDIO_IRQn = 42, /**< SD/MMC */
128 Reserved59_IRQn = 43, /**< Reserved interrupt */
129 Reserved60_IRQn = 44, /**< Reserved interrupt */
130 Reserved61_IRQn = 45, /**< Reserved interrupt */
131 USB1_PHY_IRQn = 46, /**< USB1_PHY */
132 USB1_IRQn = 47, /**< USB1 interrupt */
133 USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */
134 SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */
135 SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */
136 SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */
137 PLU_IRQn = 52, /**< PLU interrupt */
138 SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */
139 Reserved70_IRQn = 54, /**< Reserved interrupt */
140 CASER_IRQn = 55, /**< CASPER interrupt */
141 Reserved72_IRQn = 56, /**< Reserved interrupt */
142 PQ_IRQn = 57, /**< PQ interrupt */
143 DMA1_IRQn = 58, /**< DMA1 interrupt */
144 FLEXCOMM8_IRQn = 59 /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */
145} IRQn_Type;
146
147/*!
148 * @}
149 */ /* end of group Interrupt_vector_numbers */
150
151
152/* ----------------------------------------------------------------------------
153 -- Cortex M33 Core Configuration
154 ---------------------------------------------------------------------------- */
155
156/*!
157 * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration
158 * @{
159 */
160
161#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
162#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
163#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
164#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
165#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */
166#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */
167
168#include "core_cm33.h" /* Core Peripheral Access Layer */
169#include "system_LPC5526.h" /* Device specific configuration file */
170
171/*!
172 * @}
173 */ /* end of group Cortex_Core_Configuration */
174
175
176/* ----------------------------------------------------------------------------
177 -- Mapping Information
178 ---------------------------------------------------------------------------- */
179
180/*!
181 * @addtogroup Mapping_Information Mapping Information
182 * @{
183 */
184
185/** Mapping Information */
186/*!
187 * @addtogroup dma_request
188 * @{
189 */
190
191/*******************************************************************************
192 * Definitions
193 ******************************************************************************/
194
195/*!
196 * @brief Structure for the DMA hardware request
197 *
198 * Defines the structure for the DMA hardware request collections. The user can configure the
199 * hardware request to trigger the DMA transfer accordingly. The index
200 * of the hardware request varies according to the to SoC.
201 */
202typedef enum _dma_request_source
203{
204 kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */
205 kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */
206 kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */
207 kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */
208 kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */
209 kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */
210 kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */
211 kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */
212 kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */
213 kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */
214 kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */
215 kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */
216 kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */
217 kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */
218 kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */
219 kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */
220 kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */
221 kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */
222 kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */
223 kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */
224 kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */
225 kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */
226 kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */
227 kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */
228 kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */
229 kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */
230 kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */
231 kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */
232 kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */
233 kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */
234 kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */
235} dma_request_source_t;
236
237/* @} */
238
239
240/*!
241 * @}
242 */ /* end of group Mapping_Information */
243
244
245/* ----------------------------------------------------------------------------
246 -- Device Peripheral Access Layer
247 ---------------------------------------------------------------------------- */
248
249/*!
250 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
251 * @{
252 */
253
254
255/*
256** Start of section using anonymous unions
257*/
258
259#if defined(__ARMCC_VERSION)
260 #if (__ARMCC_VERSION >= 6010050)
261 #pragma clang diagnostic push
262 #else
263 #pragma push
264 #pragma anon_unions
265 #endif
266#elif defined(__GNUC__)
267 /* anonymous unions are enabled by default */
268#elif defined(__IAR_SYSTEMS_ICC__)
269 #pragma language=extended
270#else
271 #error Not supported compiler type
272#endif
273
274/* ----------------------------------------------------------------------------
275 -- ADC Peripheral Access Layer
276 ---------------------------------------------------------------------------- */
277
278/*!
279 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
280 * @{
281 */
282
283/** ADC - Register Layout Typedef */
284typedef struct {
285 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
286 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
287 uint8_t RESERVED_0[8];
288 __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */
289 __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */
290 __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */
291 __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */
292 __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */
293 __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */
294 uint8_t RESERVED_1[12];
295 __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
296 __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */
297 uint8_t RESERVED_2[4];
298 __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */
299 uint8_t RESERVED_3[92];
300 __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */
301 __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */
302 uint8_t RESERVED_4[8];
303 __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */
304 __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */
305 struct { /* offset: 0x100, array step: 0x8 */
306 __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
307 __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
308 } CMD[15];
309 uint8_t RESERVED_5[136];
310 __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
311 uint8_t RESERVED_6[240];
312 __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */
313 uint8_t RESERVED_7[248];
314 __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */
315 uint8_t RESERVED_8[124];
316 __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */
317 uint8_t RESERVED_9[2680];
318 __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */
319} ADC_Type;
320
321/* ----------------------------------------------------------------------------
322 -- ADC Register Masks
323 ---------------------------------------------------------------------------- */
324
325/*!
326 * @addtogroup ADC_Register_Masks ADC Register Masks
327 * @{
328 */
329
330/*! @name VERID - Version ID Register */
331/*! @{ */
332#define ADC_VERID_RES_MASK (0x1U)
333#define ADC_VERID_RES_SHIFT (0U)
334/*! RES - Resolution
335 * 0b0..Up to 13-bit differential/12-bit single ended resolution supported.
336 * 0b1..Up to 16-bit differential/16-bit single ended resolution supported.
337 */
338#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
339#define ADC_VERID_DIFFEN_MASK (0x2U)
340#define ADC_VERID_DIFFEN_SHIFT (1U)
341/*! DIFFEN - Differential Supported
342 * 0b0..Differential operation not supported.
343 * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented.
344 */
345#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
346#define ADC_VERID_MVI_MASK (0x8U)
347#define ADC_VERID_MVI_SHIFT (3U)
348/*! MVI - Multi Vref Implemented
349 * 0b0..Single voltage reference high (VREFH) input supported.
350 * 0b1..Multiple voltage reference high (VREFH) inputs supported.
351 */
352#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
353#define ADC_VERID_CSW_MASK (0x70U)
354#define ADC_VERID_CSW_SHIFT (4U)
355/*! CSW - Channel Scale Width
356 * 0b000..Channel scaling not supported.
357 * 0b001..Channel scaling supported. 1-bit CSCALE control field.
358 * 0b110..Channel scaling supported. 6-bit CSCALE control field.
359 */
360#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
361#define ADC_VERID_VR1RNGI_MASK (0x100U)
362#define ADC_VERID_VR1RNGI_SHIFT (8U)
363/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
364 * 0b0..Range control not required. CFG[VREF1RNG] is not implemented.
365 * 0b1..Range control required. CFG[VREF1RNG] is implemented.
366 */
367#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
368#define ADC_VERID_IADCKI_MASK (0x200U)
369#define ADC_VERID_IADCKI_SHIFT (9U)
370/*! IADCKI - Internal ADC Clock implemented
371 * 0b0..Internal clock source not implemented.
372 * 0b1..Internal clock source (and CFG[ADCKEN]) implemented.
373 */
374#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
375#define ADC_VERID_CALOFSI_MASK (0x400U)
376#define ADC_VERID_CALOFSI_SHIFT (10U)
377/*! CALOFSI - Calibration Function Implemented
378 * 0b0..Calibration Not Implemented.
379 * 0b1..Calibration Implemented.
380 */
381#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
382#define ADC_VERID_NUM_SEC_MASK (0x800U)
383#define ADC_VERID_NUM_SEC_SHIFT (11U)
384/*! NUM_SEC - Number of Single Ended Outputs Supported
385 * 0b0..This design supports one single ended conversion at a time.
386 * 0b1..This design supports two simultanious single ended conversions.
387 */
388#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK)
389#define ADC_VERID_NUM_FIFO_MASK (0x7000U)
390#define ADC_VERID_NUM_FIFO_SHIFT (12U)
391/*! NUM_FIFO - Number of FIFOs
392 * 0b000..N/A
393 * 0b001..This design supports one result FIFO.
394 * 0b010..This design supports two result FIFOs.
395 * 0b011..This design supports three result FIFOs.
396 * 0b100..This design supports four result FIFOs.
397 */
398#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK)
399#define ADC_VERID_MINOR_MASK (0xFF0000U)
400#define ADC_VERID_MINOR_SHIFT (16U)
401/*! MINOR - Minor Version Number
402 */
403#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
404#define ADC_VERID_MAJOR_MASK (0xFF000000U)
405#define ADC_VERID_MAJOR_SHIFT (24U)
406/*! MAJOR - Major Version Number
407 */
408#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
409/*! @} */
410
411/*! @name PARAM - Parameter Register */
412/*! @{ */
413#define ADC_PARAM_TRIG_NUM_MASK (0xFFU)
414#define ADC_PARAM_TRIG_NUM_SHIFT (0U)
415/*! TRIG_NUM - Trigger Number
416 */
417#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
418#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U)
419#define ADC_PARAM_FIFOSIZE_SHIFT (8U)
420/*! FIFOSIZE - Result FIFO Depth
421 * 0b00000001..Result FIFO depth = 1 dataword.
422 * 0b00000100..Result FIFO depth = 4 datawords.
423 * 0b00001000..Result FIFO depth = 8 datawords.
424 * 0b00010000..Result FIFO depth = 16 datawords.
425 * 0b00100000..Result FIFO depth = 32 datawords.
426 * 0b01000000..Result FIFO depth = 64 datawords.
427 */
428#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
429#define ADC_PARAM_CV_NUM_MASK (0xFF0000U)
430#define ADC_PARAM_CV_NUM_SHIFT (16U)
431/*! CV_NUM - Compare Value Number
432 */
433#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
434#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U)
435#define ADC_PARAM_CMD_NUM_SHIFT (24U)
436/*! CMD_NUM - Command Buffer Number
437 */
438#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
439/*! @} */
440
441/*! @name CTRL - ADC Control Register */
442/*! @{ */
443#define ADC_CTRL_ADCEN_MASK (0x1U)
444#define ADC_CTRL_ADCEN_SHIFT (0U)
445/*! ADCEN - ADC Enable
446 * 0b0..ADC is disabled.
447 * 0b1..ADC is enabled.
448 */
449#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
450#define ADC_CTRL_RST_MASK (0x2U)
451#define ADC_CTRL_RST_SHIFT (1U)
452/*! RST - Software Reset
453 * 0b0..ADC logic is not reset.
454 * 0b1..ADC logic is reset.
455 */
456#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
457#define ADC_CTRL_DOZEN_MASK (0x4U)
458#define ADC_CTRL_DOZEN_SHIFT (2U)
459/*! DOZEN - Doze Enable
460 * 0b0..ADC is enabled in Doze mode.
461 * 0b1..ADC is disabled in Doze mode.
462 */
463#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
464#define ADC_CTRL_CAL_REQ_MASK (0x8U)
465#define ADC_CTRL_CAL_REQ_SHIFT (3U)
466/*! CAL_REQ - Auto-Calibration Request
467 * 0b0..No request for auto-calibration has been made.
468 * 0b1..A request for auto-calibration has been made
469 */
470#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK)
471#define ADC_CTRL_CALOFS_MASK (0x10U)
472#define ADC_CTRL_CALOFS_SHIFT (4U)
473/*! CALOFS - Configure for offset calibration function
474 * 0b0..Calibration function disabled
475 * 0b1..Request for offset calibration function
476 */
477#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK)
478#define ADC_CTRL_RSTFIFO0_MASK (0x100U)
479#define ADC_CTRL_RSTFIFO0_SHIFT (8U)
480/*! RSTFIFO0 - Reset FIFO 0
481 * 0b0..No effect.
482 * 0b1..FIFO 0 is reset.
483 */
484#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK)
485#define ADC_CTRL_RSTFIFO1_MASK (0x200U)
486#define ADC_CTRL_RSTFIFO1_SHIFT (9U)
487/*! RSTFIFO1 - Reset FIFO 1
488 * 0b0..No effect.
489 * 0b1..FIFO 1 is reset.
490 */
491#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK)
492#define ADC_CTRL_CAL_AVGS_MASK (0x70000U)
493#define ADC_CTRL_CAL_AVGS_SHIFT (16U)
494/*! CAL_AVGS - Auto-Calibration Averages
495 * 0b000..Single conversion.
496 * 0b001..2 conversions averaged.
497 * 0b010..4 conversions averaged.
498 * 0b011..8 conversions averaged.
499 * 0b100..16 conversions averaged.
500 * 0b101..32 conversions averaged.
501 * 0b110..64 conversions averaged.
502 * 0b111..128 conversions averaged.
503 */
504#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK)
505/*! @} */
506
507/*! @name STAT - ADC Status Register */
508/*! @{ */
509#define ADC_STAT_RDY0_MASK (0x1U)
510#define ADC_STAT_RDY0_SHIFT (0U)
511/*! RDY0 - Result FIFO 0 Ready Flag
512 * 0b0..Result FIFO 0 data level not above watermark level.
513 * 0b1..Result FIFO 0 holding data above watermark level.
514 */
515#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK)
516#define ADC_STAT_FOF0_MASK (0x2U)
517#define ADC_STAT_FOF0_SHIFT (1U)
518/*! FOF0 - Result FIFO 0 Overflow Flag
519 * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared.
520 * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.
521 */
522#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK)
523#define ADC_STAT_RDY1_MASK (0x4U)
524#define ADC_STAT_RDY1_SHIFT (2U)
525/*! RDY1 - Result FIFO1 Ready Flag
526 * 0b0..Result FIFO1 data level not above watermark level.
527 * 0b1..Result FIFO1 holding data above watermark level.
528 */
529#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK)
530#define ADC_STAT_FOF1_MASK (0x8U)
531#define ADC_STAT_FOF1_SHIFT (3U)
532/*! FOF1 - Result FIFO1 Overflow Flag
533 * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
534 * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
535 */
536#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK)
537#define ADC_STAT_TEXC_INT_MASK (0x100U)
538#define ADC_STAT_TEXC_INT_SHIFT (8U)
539/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception
540 * 0b0..No trigger exceptions have occurred.
541 * 0b1..A trigger exception has occurred and is pending acknowledgement.
542 */
543#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK)
544#define ADC_STAT_TCOMP_INT_MASK (0x200U)
545#define ADC_STAT_TCOMP_INT_SHIFT (9U)
546/*! TCOMP_INT - Interrupt Flag For Trigger Completion
547 * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion.
548 * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO.
549 */
550#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK)
551#define ADC_STAT_CAL_RDY_MASK (0x400U)
552#define ADC_STAT_CAL_RDY_SHIFT (10U)
553/*! CAL_RDY - Calibration Ready
554 * 0b0..Calibration is incomplete or hasn't been ran.
555 * 0b1..The ADC is calibrated.
556 */
557#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK)
558#define ADC_STAT_ADC_ACTIVE_MASK (0x800U)
559#define ADC_STAT_ADC_ACTIVE_SHIFT (11U)
560/*! ADC_ACTIVE - ADC Active
561 * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
562 * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
563 */
564#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
565#define ADC_STAT_TRGACT_MASK (0xF0000U)
566#define ADC_STAT_TRGACT_SHIFT (16U)
567/*! TRGACT - Trigger Active
568 * 0b0000..Command (sequence) associated with Trigger 0 currently being executed.
569 * 0b0001..Command (sequence) associated with Trigger 1 currently being executed.
570 * 0b0010..Command (sequence) associated with Trigger 2 currently being executed.
571 * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed.
572 */
573#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
574#define ADC_STAT_CMDACT_MASK (0xF000000U)
575#define ADC_STAT_CMDACT_SHIFT (24U)
576/*! CMDACT - Command Active
577 * 0b0000..No command is currently in progress.
578 * 0b0001..Command 1 currently being executed.
579 * 0b0010..Command 2 currently being executed.
580 * 0b0011-0b1111..Associated command number is currently being executed.
581 */
582#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
583/*! @} */
584
585/*! @name IE - Interrupt Enable Register */
586/*! @{ */
587#define ADC_IE_FWMIE0_MASK (0x1U)
588#define ADC_IE_FWMIE0_SHIFT (0U)
589/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable
590 * 0b0..FIFO 0 watermark interrupts are not enabled.
591 * 0b1..FIFO 0 watermark interrupts are enabled.
592 */
593#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK)
594#define ADC_IE_FOFIE0_MASK (0x2U)
595#define ADC_IE_FOFIE0_SHIFT (1U)
596/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable
597 * 0b0..FIFO 0 overflow interrupts are not enabled.
598 * 0b1..FIFO 0 overflow interrupts are enabled.
599 */
600#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK)
601#define ADC_IE_FWMIE1_MASK (0x4U)
602#define ADC_IE_FWMIE1_SHIFT (2U)
603/*! FWMIE1 - FIFO1 Watermark Interrupt Enable
604 * 0b0..FIFO1 watermark interrupts are not enabled.
605 * 0b1..FIFO1 watermark interrupts are enabled.
606 */
607#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK)
608#define ADC_IE_FOFIE1_MASK (0x8U)
609#define ADC_IE_FOFIE1_SHIFT (3U)
610/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable
611 * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
612 * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
613 */
614#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK)
615#define ADC_IE_TEXC_IE_MASK (0x100U)
616#define ADC_IE_TEXC_IE_SHIFT (8U)
617/*! TEXC_IE - Trigger Exception Interrupt Enable
618 * 0b0..Trigger exception interrupts are disabled.
619 * 0b1..Trigger exception interrupts are enabled.
620 */
621#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK)
622#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U)
623#define ADC_IE_TCOMP_IE_SHIFT (16U)
624/*! TCOMP_IE - Trigger Completion Interrupt Enable
625 * 0b0000000000000000..Trigger completion interrupts are disabled.
626 * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only.
627 * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only.
628 * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled.
629 * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source.
630 */
631#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK)
632/*! @} */
633
634/*! @name DE - DMA Enable Register */
635/*! @{ */
636#define ADC_DE_FWMDE0_MASK (0x1U)
637#define ADC_DE_FWMDE0_SHIFT (0U)
638/*! FWMDE0 - FIFO 0 Watermark DMA Enable
639 * 0b0..DMA request disabled.
640 * 0b1..DMA request enabled.
641 */
642#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK)
643#define ADC_DE_FWMDE1_MASK (0x2U)
644#define ADC_DE_FWMDE1_SHIFT (1U)
645/*! FWMDE1 - FIFO1 Watermark DMA Enable
646 * 0b0..DMA request disabled.
647 * 0b1..DMA request enabled.
648 */
649#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK)
650/*! @} */
651
652/*! @name CFG - ADC Configuration Register */
653/*! @{ */
654#define ADC_CFG_TPRICTRL_MASK (0x3U)
655#define ADC_CFG_TPRICTRL_SHIFT (0U)
656/*! TPRICTRL - ADC trigger priority control
657 * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted
658 * and the new command specified by the trigger is started.
659 * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after
660 * after completing the current conversion. If averaging is enabled, the averaging loop will be completed.
661 * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced.
662 * 0b10..If a higher priority trigger is received during command processing, the current command will be
663 * completed (averaging, looping, compare) before servicing the higher priority trigger.
664 * 0b11..RESERVED
665 */
666#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
667#define ADC_CFG_PWRSEL_MASK (0x30U)
668#define ADC_CFG_PWRSEL_SHIFT (4U)
669/*! PWRSEL - Power Configuration Select
670 * 0b00..Lowest power setting.
671 * 0b01..Higher power setting than 0b0.
672 * 0b10..Higher power setting than 0b1.
673 * 0b11..Highest power setting.
674 */
675#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
676#define ADC_CFG_REFSEL_MASK (0xC0U)
677#define ADC_CFG_REFSEL_SHIFT (6U)
678/*! REFSEL - Voltage Reference Selection
679 * 0b00..(Default) Option 1 setting.
680 * 0b01..Option 2 setting.
681 * 0b10..Option 3 setting.
682 * 0b11..Reserved
683 */
684#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
685#define ADC_CFG_TRES_MASK (0x100U)
686#define ADC_CFG_TRES_SHIFT (8U)
687/*! TRES - Trigger Resume Enable
688 * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted.
689 * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted.
690 */
691#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK)
692#define ADC_CFG_TCMDRES_MASK (0x200U)
693#define ADC_CFG_TCMDRES_SHIFT (9U)
694/*! TCMDRES - Trigger Command Resume
695 * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted.
696 * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception.
697 */
698#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK)
699#define ADC_CFG_HPT_EXDI_MASK (0x400U)
700#define ADC_CFG_HPT_EXDI_SHIFT (10U)
701/*! HPT_EXDI - High Priority Trigger Exception Disable
702 * 0b0..High priority trigger exceptions are enabled.
703 * 0b1..High priority trigger exceptions are disabled.
704 */
705#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK)
706#define ADC_CFG_PUDLY_MASK (0xFF0000U)
707#define ADC_CFG_PUDLY_SHIFT (16U)
708/*! PUDLY - Power Up Delay
709 */
710#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
711#define ADC_CFG_PWREN_MASK (0x10000000U)
712#define ADC_CFG_PWREN_SHIFT (28U)
713/*! PWREN - ADC Analog Pre-Enable
714 * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
715 * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
716 * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN
717 * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed.
718 * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be
719 * executed.
720 */
721#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
722/*! @} */
723
724/*! @name PAUSE - ADC Pause Register */
725/*! @{ */
726#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU)
727#define ADC_PAUSE_PAUSEDLY_SHIFT (0U)
728/*! PAUSEDLY - Pause Delay
729 */
730#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
731#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U)
732#define ADC_PAUSE_PAUSEEN_SHIFT (31U)
733/*! PAUSEEN - PAUSE Option Enable
734 * 0b0..Pause operation disabled
735 * 0b1..Pause operation enabled
736 */
737#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
738/*! @} */
739
740/*! @name SWTRIG - Software Trigger Register */
741/*! @{ */
742#define ADC_SWTRIG_SWT0_MASK (0x1U)
743#define ADC_SWTRIG_SWT0_SHIFT (0U)
744/*! SWT0 - Software trigger 0 event
745 * 0b0..No trigger 0 event generated.
746 * 0b1..Trigger 0 event generated.
747 */
748#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
749#define ADC_SWTRIG_SWT1_MASK (0x2U)
750#define ADC_SWTRIG_SWT1_SHIFT (1U)
751/*! SWT1 - Software trigger 1 event
752 * 0b0..No trigger 1 event generated.
753 * 0b1..Trigger 1 event generated.
754 */
755#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
756#define ADC_SWTRIG_SWT2_MASK (0x4U)
757#define ADC_SWTRIG_SWT2_SHIFT (2U)
758/*! SWT2 - Software trigger 2 event
759 * 0b0..No trigger 2 event generated.
760 * 0b1..Trigger 2 event generated.
761 */
762#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
763#define ADC_SWTRIG_SWT3_MASK (0x8U)
764#define ADC_SWTRIG_SWT3_SHIFT (3U)
765/*! SWT3 - Software trigger 3 event
766 * 0b0..No trigger 3 event generated.
767 * 0b1..Trigger 3 event generated.
768 */
769#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
770#define ADC_SWTRIG_SWT4_MASK (0x10U)
771#define ADC_SWTRIG_SWT4_SHIFT (4U)
772/*! SWT4 - Software trigger 4 event
773 * 0b0..No trigger 4 event generated.
774 * 0b1..Trigger 4 event generated.
775 */
776#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
777#define ADC_SWTRIG_SWT5_MASK (0x20U)
778#define ADC_SWTRIG_SWT5_SHIFT (5U)
779/*! SWT5 - Software trigger 5 event
780 * 0b0..No trigger 5 event generated.
781 * 0b1..Trigger 5 event generated.
782 */
783#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
784#define ADC_SWTRIG_SWT6_MASK (0x40U)
785#define ADC_SWTRIG_SWT6_SHIFT (6U)
786/*! SWT6 - Software trigger 6 event
787 * 0b0..No trigger 6 event generated.
788 * 0b1..Trigger 6 event generated.
789 */
790#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
791#define ADC_SWTRIG_SWT7_MASK (0x80U)
792#define ADC_SWTRIG_SWT7_SHIFT (7U)
793/*! SWT7 - Software trigger 7 event
794 * 0b0..No trigger 7 event generated.
795 * 0b1..Trigger 7 event generated.
796 */
797#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
798#define ADC_SWTRIG_SWT8_MASK (0x100U)
799#define ADC_SWTRIG_SWT8_SHIFT (8U)
800/*! SWT8 - Software trigger 8 event
801 * 0b0..No trigger 8 event generated.
802 * 0b1..Trigger 8 event generated.
803 */
804#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK)
805#define ADC_SWTRIG_SWT9_MASK (0x200U)
806#define ADC_SWTRIG_SWT9_SHIFT (9U)
807/*! SWT9 - Software trigger 9 event
808 * 0b0..No trigger 9 event generated.
809 * 0b1..Trigger 9 event generated.
810 */
811#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK)
812#define ADC_SWTRIG_SWT10_MASK (0x400U)
813#define ADC_SWTRIG_SWT10_SHIFT (10U)
814/*! SWT10 - Software trigger 10 event
815 * 0b0..No trigger 10 event generated.
816 * 0b1..Trigger 10 event generated.
817 */
818#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK)
819#define ADC_SWTRIG_SWT11_MASK (0x800U)
820#define ADC_SWTRIG_SWT11_SHIFT (11U)
821/*! SWT11 - Software trigger 11 event
822 * 0b0..No trigger 11 event generated.
823 * 0b1..Trigger 11 event generated.
824 */
825#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK)
826#define ADC_SWTRIG_SWT12_MASK (0x1000U)
827#define ADC_SWTRIG_SWT12_SHIFT (12U)
828/*! SWT12 - Software trigger 12 event
829 * 0b0..No trigger 12 event generated.
830 * 0b1..Trigger 12 event generated.
831 */
832#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK)
833#define ADC_SWTRIG_SWT13_MASK (0x2000U)
834#define ADC_SWTRIG_SWT13_SHIFT (13U)
835/*! SWT13 - Software trigger 13 event
836 * 0b0..No trigger 13 event generated.
837 * 0b1..Trigger 13 event generated.
838 */
839#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK)
840#define ADC_SWTRIG_SWT14_MASK (0x4000U)
841#define ADC_SWTRIG_SWT14_SHIFT (14U)
842/*! SWT14 - Software trigger 14 event
843 * 0b0..No trigger 14 event generated.
844 * 0b1..Trigger 14 event generated.
845 */
846#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK)
847#define ADC_SWTRIG_SWT15_MASK (0x8000U)
848#define ADC_SWTRIG_SWT15_SHIFT (15U)
849/*! SWT15 - Software trigger 15 event
850 * 0b0..No trigger 15 event generated.
851 * 0b1..Trigger 15 event generated.
852 */
853#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK)
854/*! @} */
855
856/*! @name TSTAT - Trigger Status Register */
857/*! @{ */
858#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU)
859#define ADC_TSTAT_TEXC_NUM_SHIFT (0U)
860/*! TEXC_NUM - Trigger Exception Number
861 * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1.
862 * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception.
863 * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception.
864 * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception.
865 * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception.
866 */
867#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK)
868#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U)
869#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U)
870/*! TCOMP_FLAG - Trigger Completion Flag
871 * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled.
872 * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts.
873 * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts.
874 * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts.
875 * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts.
876 */
877#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK)
878/*! @} */
879
880/*! @name OFSTRIM - ADC Offset Trim Register */
881/*! @{ */
882#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU)
883#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U)
884/*! OFSTRIM_A - Trim for offset
885 */
886#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK)
887#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U)
888#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U)
889/*! OFSTRIM_B - Trim for offset
890 */
891#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK)
892/*! @} */
893
894/*! @name TCTRL - Trigger Control Register */
895/*! @{ */
896#define ADC_TCTRL_HTEN_MASK (0x1U)
897#define ADC_TCTRL_HTEN_SHIFT (0U)
898/*! HTEN - Trigger enable
899 * 0b0..Hardware trigger source disabled
900 * 0b1..Hardware trigger source enabled
901 */
902#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
903#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U)
904#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U)
905/*! FIFO_SEL_A - SAR Result Destination For Channel A
906 * 0b0..Result written to FIFO 0
907 * 0b1..Result written to FIFO 1
908 */
909#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK)
910#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U)
911#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U)
912/*! FIFO_SEL_B - SAR Result Destination For Channel B
913 * 0b0..Result written to FIFO 0
914 * 0b1..Result written to FIFO 1
915 */
916#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK)
917#define ADC_TCTRL_TPRI_MASK (0xF00U)
918#define ADC_TCTRL_TPRI_SHIFT (8U)
919/*! TPRI - Trigger priority setting
920 * 0b0000..Set to highest priority, Level 1
921 * 0b0001-0b1110..Set to corresponding priority level
922 * 0b1111..Set to lowest priority, Level 16
923 */
924#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
925#define ADC_TCTRL_RSYNC_MASK (0x8000U)
926#define ADC_TCTRL_RSYNC_SHIFT (15U)
927/*! RSYNC - Trigger Resync
928 */
929#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK)
930#define ADC_TCTRL_TDLY_MASK (0xF0000U)
931#define ADC_TCTRL_TDLY_SHIFT (16U)
932/*! TDLY - Trigger delay select
933 */
934#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
935#define ADC_TCTRL_TCMD_MASK (0xF000000U)
936#define ADC_TCTRL_TCMD_SHIFT (24U)
937/*! TCMD - Trigger command select
938 * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
939 * 0b0001..CMD1 is executed
940 * 0b0010-0b1110..Corresponding CMD is executed
941 * 0b1111..CMD15 is executed
942 */
943#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
944/*! @} */
945
946/* The count of ADC_TCTRL */
947#define ADC_TCTRL_COUNT (16U)
948
949/*! @name FCTRL - FIFO Control Register */
950/*! @{ */
951#define ADC_FCTRL_FCOUNT_MASK (0x1FU)
952#define ADC_FCTRL_FCOUNT_SHIFT (0U)
953/*! FCOUNT - Result FIFO counter
954 */
955#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
956#define ADC_FCTRL_FWMARK_MASK (0xF0000U)
957#define ADC_FCTRL_FWMARK_SHIFT (16U)
958/*! FWMARK - Watermark level selection
959 */
960#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
961/*! @} */
962
963/* The count of ADC_FCTRL */
964#define ADC_FCTRL_COUNT (2U)
965
966/*! @name GCC - Gain Calibration Control */
967/*! @{ */
968#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU)
969#define ADC_GCC_GAIN_CAL_SHIFT (0U)
970/*! GAIN_CAL - Gain Calibration Value
971 */
972#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK)
973#define ADC_GCC_RDY_MASK (0x1000000U)
974#define ADC_GCC_RDY_SHIFT (24U)
975/*! RDY - Gain Calibration Value Valid
976 * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written.
977 * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field.
978 */
979#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK)
980/*! @} */
981
982/* The count of ADC_GCC */
983#define ADC_GCC_COUNT (2U)
984
985/*! @name GCR - Gain Calculation Result */
986/*! @{ */
987#define ADC_GCR_GCALR_MASK (0xFFFFU)
988#define ADC_GCR_GCALR_SHIFT (0U)
989/*! GCALR - Gain Calculation Result
990 */
991#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK)
992#define ADC_GCR_RDY_MASK (0x1000000U)
993#define ADC_GCR_RDY_SHIFT (24U)
994/*! RDY - Gain Calculation Ready
995 * 0b0..The gain offset calculation value is invalid.
996 * 0b1..The gain calibration value is valid.
997 */
998#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK)
999/*! @} */
1000
1001/* The count of ADC_GCR */
1002#define ADC_GCR_COUNT (2U)
1003
1004/*! @name CMDL - ADC Command Low Buffer Register */
1005/*! @{ */
1006#define ADC_CMDL_ADCH_MASK (0x1FU)
1007#define ADC_CMDL_ADCH_SHIFT (0U)
1008/*! ADCH - Input channel select
1009 * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
1010 * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
1011 * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
1012 * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
1013 * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
1014 * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
1015 * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
1016 */
1017#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
1018#define ADC_CMDL_CTYPE_MASK (0x60U)
1019#define ADC_CMDL_CTYPE_SHIFT (5U)
1020/*! CTYPE - Conversion Type
1021 * 0b00..Single-Ended Mode. Only A side channel is converted.
1022 * 0b01..Single-Ended Mode. Only B side channel is converted.
1023 * 0b10..Differential Mode. A-B.
1024 * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
1025 */
1026#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK)
1027#define ADC_CMDL_MODE_MASK (0x80U)
1028#define ADC_CMDL_MODE_SHIFT (7U)
1029/*! MODE - Select resolution of conversions
1030 * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
1031 * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
1032 */
1033#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK)
1034/*! @} */
1035
1036/* The count of ADC_CMDL */
1037#define ADC_CMDL_COUNT (15U)
1038
1039/*! @name CMDH - ADC Command High Buffer Register */
1040/*! @{ */
1041#define ADC_CMDH_CMPEN_MASK (0x3U)
1042#define ADC_CMDH_CMPEN_SHIFT (0U)
1043/*! CMPEN - Compare Function Enable
1044 * 0b00..Compare disabled.
1045 * 0b01..Reserved
1046 * 0b10..Compare enabled. Store on true.
1047 * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
1048 */
1049#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
1050#define ADC_CMDH_WAIT_TRIG_MASK (0x4U)
1051#define ADC_CMDH_WAIT_TRIG_SHIFT (2U)
1052/*! WAIT_TRIG - Wait for trigger assertion before execution.
1053 * 0b0..This command will be automatically executed.
1054 * 0b1..The active trigger must be asserted again before executing this command.
1055 */
1056#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK)
1057#define ADC_CMDH_LWI_MASK (0x80U)
1058#define ADC_CMDH_LWI_SHIFT (7U)
1059/*! LWI - Loop with Increment
1060 * 0b0..Auto channel increment disabled
1061 * 0b1..Auto channel increment enabled
1062 */
1063#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
1064#define ADC_CMDH_STS_MASK (0x700U)
1065#define ADC_CMDH_STS_SHIFT (8U)
1066/*! STS - Sample Time Select
1067 * 0b000..Minimum sample time of 3 ADCK cycles.
1068 * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
1069 * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
1070 * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
1071 * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
1072 * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
1073 * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
1074 * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
1075 */
1076#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
1077#define ADC_CMDH_AVGS_MASK (0x7000U)
1078#define ADC_CMDH_AVGS_SHIFT (12U)
1079/*! AVGS - Hardware Average Select
1080 * 0b000..Single conversion.
1081 * 0b001..2 conversions averaged.
1082 * 0b010..4 conversions averaged.
1083 * 0b011..8 conversions averaged.
1084 * 0b100..16 conversions averaged.
1085 * 0b101..32 conversions averaged.
1086 * 0b110..64 conversions averaged.
1087 * 0b111..128 conversions averaged.
1088 */
1089#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
1090#define ADC_CMDH_LOOP_MASK (0xF0000U)
1091#define ADC_CMDH_LOOP_SHIFT (16U)
1092/*! LOOP - Loop Count Select
1093 * 0b0000..Looping not enabled. Command executes 1 time.
1094 * 0b0001..Loop 1 time. Command executes 2 times.
1095 * 0b0010..Loop 2 times. Command executes 3 times.
1096 * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
1097 * 0b1111..Loop 15 times. Command executes 16 times.
1098 */
1099#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
1100#define ADC_CMDH_NEXT_MASK (0xF000000U)
1101#define ADC_CMDH_NEXT_SHIFT (24U)
1102/*! NEXT - Next Command Select
1103 * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
1104 * trigger pending, begin command associated with lower priority trigger.
1105 * 0b0001..Select CMD1 command buffer register as next command.
1106 * 0b0010-0b1110..Select corresponding CMD command buffer register as next command
1107 * 0b1111..Select CMD15 command buffer register as next command.
1108 */
1109#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
1110/*! @} */
1111
1112/* The count of ADC_CMDH */
1113#define ADC_CMDH_COUNT (15U)
1114
1115/*! @name CV - Compare Value Register */
1116/*! @{ */
1117#define ADC_CV_CVL_MASK (0xFFFFU)
1118#define ADC_CV_CVL_SHIFT (0U)
1119/*! CVL - Compare Value Low.
1120 */
1121#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
1122#define ADC_CV_CVH_MASK (0xFFFF0000U)
1123#define ADC_CV_CVH_SHIFT (16U)
1124/*! CVH - Compare Value High.
1125 */
1126#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
1127/*! @} */
1128
1129/* The count of ADC_CV */
1130#define ADC_CV_COUNT (4U)
1131
1132/*! @name RESFIFO - ADC Data Result FIFO Register */
1133/*! @{ */
1134#define ADC_RESFIFO_D_MASK (0xFFFFU)
1135#define ADC_RESFIFO_D_SHIFT (0U)
1136/*! D - Data result
1137 */
1138#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
1139#define ADC_RESFIFO_TSRC_MASK (0xF0000U)
1140#define ADC_RESFIFO_TSRC_SHIFT (16U)
1141/*! TSRC - Trigger Source
1142 * 0b0000..Trigger source 0 initiated this conversion.
1143 * 0b0001..Trigger source 1 initiated this conversion.
1144 * 0b0010-0b1110..Corresponding trigger source initiated this conversion.
1145 * 0b1111..Trigger source 15 initiated this conversion.
1146 */
1147#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
1148#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U)
1149#define ADC_RESFIFO_LOOPCNT_SHIFT (20U)
1150/*! LOOPCNT - Loop count value
1151 * 0b0000..Result is from initial conversion in command.
1152 * 0b0001..Result is from second conversion in command.
1153 * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
1154 * 0b1111..Result is from 16th conversion in command.
1155 */
1156#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
1157#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U)
1158#define ADC_RESFIFO_CMDSRC_SHIFT (24U)
1159/*! CMDSRC - Command Buffer Source
1160 * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
1161 * prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
1162 * 0b0001..CMD1 buffer used as control settings for this conversion.
1163 * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
1164 * 0b1111..CMD15 buffer used as control settings for this conversion.
1165 */
1166#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
1167#define ADC_RESFIFO_VALID_MASK (0x80000000U)
1168#define ADC_RESFIFO_VALID_SHIFT (31U)
1169/*! VALID - FIFO entry is valid
1170 * 0b0..FIFO is empty. Discard any read from RESFIFO.
1171 * 0b1..FIFO record read from RESFIFO is valid.
1172 */
1173#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
1174/*! @} */
1175
1176/* The count of ADC_RESFIFO */
1177#define ADC_RESFIFO_COUNT (2U)
1178
1179/*! @name CAL_GAR - Calibration General A-Side Registers */
1180/*! @{ */
1181#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU)
1182#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U)
1183/*! CAL_GAR_VAL - Calibration General A Side Register Element
1184 */
1185#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK)
1186/*! @} */
1187
1188/* The count of ADC_CAL_GAR */
1189#define ADC_CAL_GAR_COUNT (33U)
1190
1191/*! @name CAL_GBR - Calibration General B-Side Registers */
1192/*! @{ */
1193#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU)
1194#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U)
1195/*! CAL_GBR_VAL - Calibration General B Side Register Element
1196 */
1197#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK)
1198/*! @} */
1199
1200/* The count of ADC_CAL_GBR */
1201#define ADC_CAL_GBR_COUNT (33U)
1202
1203/*! @name TST - ADC Test Register */
1204/*! @{ */
1205#define ADC_TST_CST_LONG_MASK (0x1U)
1206#define ADC_TST_CST_LONG_SHIFT (0U)
1207/*! CST_LONG - Calibration Sample Time Long
1208 * 0b0..Normal sample time. Minimum sample time of 3 ADCK cycles.
1209 * 0b1..Increased sample time. 67 ADCK cycles total sample time.
1210 */
1211#define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK)
1212#define ADC_TST_FOFFM_MASK (0x100U)
1213#define ADC_TST_FOFFM_SHIFT (8U)
1214/*! FOFFM - Force M-side positive offset
1215 * 0b0..Normal operation. No forced offset.
1216 * 0b1..Test configuration. Forced positive offset on MDAC.
1217 */
1218#define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK)
1219#define ADC_TST_FOFFP_MASK (0x200U)
1220#define ADC_TST_FOFFP_SHIFT (9U)
1221/*! FOFFP - Force P-side positive offset
1222 * 0b0..Normal operation. No forced offset.
1223 * 0b1..Test configuration. Forced positive offset on PDAC.
1224 */
1225#define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK)
1226#define ADC_TST_FOFFM2_MASK (0x400U)
1227#define ADC_TST_FOFFM2_SHIFT (10U)
1228/*! FOFFM2 - Force M-side negative offset
1229 * 0b0..Normal operation. No forced offset.
1230 * 0b1..Test configuration. Forced negative offset on MDAC.
1231 */
1232#define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK)
1233#define ADC_TST_FOFFP2_MASK (0x800U)
1234#define ADC_TST_FOFFP2_SHIFT (11U)
1235/*! FOFFP2 - Force P-side negative offset
1236 * 0b0..Normal operation. No forced offset.
1237 * 0b1..Test configuration. Forced negative offset on PDAC.
1238 */
1239#define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK)
1240#define ADC_TST_TESTEN_MASK (0x800000U)
1241#define ADC_TST_TESTEN_SHIFT (23U)
1242/*! TESTEN - Enable test configuration
1243 * 0b0..Normal operation. Test configuration not enabled.
1244 * 0b1..Hardware BIST Test in progress.
1245 */
1246#define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK)
1247/*! @} */
1248
1249
1250/*!
1251 * @}
1252 */ /* end of group ADC_Register_Masks */
1253
1254
1255/* ADC - Peripheral instance base addresses */
1256#if (__ARM_FEATURE_CMSE & 0x2)
1257 /** Peripheral ADC0 base address */
1258 #define ADC0_BASE (0x500A0000u)
1259 /** Peripheral ADC0 base address */
1260 #define ADC0_BASE_NS (0x400A0000u)
1261 /** Peripheral ADC0 base pointer */
1262 #define ADC0 ((ADC_Type *)ADC0_BASE)
1263 /** Peripheral ADC0 base pointer */
1264 #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS)
1265 /** Array initializer of ADC peripheral base addresses */
1266 #define ADC_BASE_ADDRS { ADC0_BASE }
1267 /** Array initializer of ADC peripheral base pointers */
1268 #define ADC_BASE_PTRS { ADC0 }
1269 /** Array initializer of ADC peripheral base addresses */
1270 #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS }
1271 /** Array initializer of ADC peripheral base pointers */
1272 #define ADC_BASE_PTRS_NS { ADC0_NS }
1273#else
1274 /** Peripheral ADC0 base address */
1275 #define ADC0_BASE (0x400A0000u)
1276 /** Peripheral ADC0 base pointer */
1277 #define ADC0 ((ADC_Type *)ADC0_BASE)
1278 /** Array initializer of ADC peripheral base addresses */
1279 #define ADC_BASE_ADDRS { ADC0_BASE }
1280 /** Array initializer of ADC peripheral base pointers */
1281 #define ADC_BASE_PTRS { ADC0 }
1282#endif
1283/** Interrupt vectors for the ADC peripheral type */
1284#define ADC_IRQS { ADC0_IRQn }
1285
1286/*!
1287 * @}
1288 */ /* end of group ADC_Peripheral_Access_Layer */
1289
1290
1291/* ----------------------------------------------------------------------------
1292 -- AHB_SECURE_CTRL Peripheral Access Layer
1293 ---------------------------------------------------------------------------- */
1294
1295/*!
1296 * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer
1297 * @{
1298 */
1299
1300/** AHB_SECURE_CTRL - Register Layout Typedef */
1301typedef struct {
1302 struct { /* offset: 0x0, array step: 0x30 */
1303 __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */
1304 uint8_t RESERVED_0[12];
1305 __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[3]; /**< Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */
1306 uint8_t RESERVED_1[4];
1307 __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */
1308 } SEC_CTRL_FLASH_ROM[1];
1309 struct { /* offset: 0x30, array step: 0x14 */
1310 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */
1311 uint8_t RESERVED_0[12];
1312 __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */
1313 } SEC_CTRL_RAMX[1];
1314 uint8_t RESERVED_0[12];
1315 struct { /* offset: 0x50, array step: 0x18 */
1316 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */
1317 uint8_t RESERVED_0[12];
1318 __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x18, index2*0x4 */
1319 } SEC_CTRL_RAM0[1];
1320 uint8_t RESERVED_1[8];
1321 struct { /* offset: 0x70, array step: 0x18 */
1322 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */
1323 uint8_t RESERVED_0[12];
1324 __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x18, index2*0x4 */
1325 } SEC_CTRL_RAM1[1];
1326 uint8_t RESERVED_2[8];
1327 struct { /* offset: 0x90, array step: 0x18 */
1328 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */
1329 uint8_t RESERVED_0[12];
1330 __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x18, index2*0x4 */
1331 } SEC_CTRL_RAM2[1];
1332 uint8_t RESERVED_3[8];
1333 struct { /* offset: 0xB0, array step: 0x18 */
1334 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */
1335 uint8_t RESERVED_0[12];
1336 __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM3 slaves., array offset: 0xC0, array step: index*0x18, index2*0x4 */
1337 } SEC_CTRL_RAM3[1];
1338 uint8_t RESERVED_4[8];
1339 struct { /* offset: 0xD0, array step: 0x14 */
1340 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */
1341 uint8_t RESERVED_0[12];
1342 __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM4 slaves., array offset: 0xE0, array step: index*0x14, index2*0x4 */
1343 } SEC_CTRL_RAM4[1];
1344 uint8_t RESERVED_5[12];
1345 struct { /* offset: 0xF0, array step: 0x30 */
1346 __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xF0, array step: 0x30 */
1347 uint8_t RESERVED_0[12];
1348 __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */
1349 __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */
1350 __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */
1351 uint8_t RESERVED_1[4];
1352 __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */
1353 __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */
1354 __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */
1355 __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */
1356 } SEC_CTRL_APB_BRIDGE[1];
1357 __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */
1358 __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */
1359 uint8_t RESERVED_6[8];
1360 __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */
1361 __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */
1362 uint8_t RESERVED_7[8];
1363 struct { /* offset: 0x140, array step: 0x14 */
1364 __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */
1365 __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */
1366 uint8_t RESERVED_0[8];
1367 __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */
1368 } SEC_CTRL_AHB_PORT10[1];
1369 uint8_t RESERVED_8[12];
1370 struct { /* offset: 0x160, array step: 0x14 */
1371 __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0x160, array step: 0x14 */
1372 uint8_t RESERVED_0[12];
1373 __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0x170, array step: index*0x14, index2*0x4 */
1374 } SEC_CTRL_USB_HS[1];
1375 uint8_t RESERVED_9[3212];
1376 __I uint32_t SEC_VIO_ADDR[12]; /**< most recent security violation address for AHB port n, array offset: 0xE00, array step: 0x4 */
1377 uint8_t RESERVED_10[80];
1378 __I uint32_t SEC_VIO_MISC_INFO[12]; /**< most recent security violation miscellaneous information for AHB port n, array offset: 0xE80, array step: 0x4 */
1379 uint8_t RESERVED_11[80];
1380 __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */
1381 uint8_t RESERVED_12[124];
1382 __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */
1383 __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */
1384 uint8_t RESERVED_13[8];
1385 __IO uint32_t SEC_CPU_INT_MASK0; /**< Secure Interrupt mask for CPU1, offset: 0xF90 */
1386 __IO uint32_t SEC_CPU_INT_MASK1; /**< Secure Interrupt mask for CPU1, offset: 0xF94 */
1387 uint8_t RESERVED_14[36];
1388 __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */
1389 uint8_t RESERVED_15[16];
1390 __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */
1391 __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */
1392 uint8_t RESERVED_16[20];
1393 __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */
1394 __IO uint32_t CPU1_LOCK_REG; /**< Miscalleneous control signals for in micro-Cortex M33 (CPU1), offset: 0xFF0 */
1395 uint8_t RESERVED_17[4];
1396 __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */
1397 __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */
1398} AHB_SECURE_CTRL_Type;
1399
1400/* ----------------------------------------------------------------------------
1401 -- AHB_SECURE_CTRL Register Masks
1402 ---------------------------------------------------------------------------- */
1403
1404/*!
1405 * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks
1406 * @{
1407 */
1408
1409/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */
1410/*! @{ */
1411#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U)
1412#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U)
1413/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF
1414 * 0b00..Non-secure and Non-priviledge user access allowed.
1415 * 0b01..Non-secure and Privilege access allowed.
1416 * 0b10..Secure and Non-priviledge user access allowed.
1417 * 0b11..Secure and Priviledge user access allowed.
1418 */
1419#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK)
1420#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U)
1421#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U)
1422/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF
1423 * 0b00..Non-secure and Non-priviledge user access allowed.
1424 * 0b01..Non-secure and Privilege access allowed.
1425 * 0b10..Secure and Non-priviledge user access allowed.
1426 * 0b11..Secure and Priviledge user access allowed.
1427 */
1428#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK)
1429/*! @} */
1430
1431/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */
1432#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U)
1433
1434/*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */
1435/*! @{ */
1436#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U)
1437#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U)
1438/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1439 * 0b00..Non-secure and Non-priviledge user access allowed.
1440 * 0b01..Non-secure and Privilege access allowed.
1441 * 0b10..Secure and Non-priviledge user access allowed.
1442 * 0b11..Secure and Priviledge user access allowed.
1443 */
1444#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK)
1445#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U)
1446#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U)
1447/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1448 * 0b00..Non-secure and Non-priviledge user access allowed.
1449 * 0b01..Non-secure and Privilege access allowed.
1450 * 0b10..Secure and Non-priviledge user access allowed.
1451 * 0b11..Secure and Priviledge user access allowed.
1452 */
1453#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK)
1454#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U)
1455#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U)
1456/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1457 * 0b00..Non-secure and Non-priviledge user access allowed.
1458 * 0b01..Non-secure and Privilege access allowed.
1459 * 0b10..Secure and Non-priviledge user access allowed.
1460 * 0b11..Secure and Priviledge user access allowed.
1461 */
1462#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK)
1463#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U)
1464#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U)
1465/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1466 * 0b00..Non-secure and Non-priviledge user access allowed.
1467 * 0b01..Non-secure and Privilege access allowed.
1468 * 0b10..Secure and Non-priviledge user access allowed.
1469 * 0b11..Secure and Priviledge user access allowed.
1470 */
1471#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK)
1472#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U)
1473#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U)
1474/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1475 * 0b00..Non-secure and Non-priviledge user access allowed.
1476 * 0b01..Non-secure and Privilege access allowed.
1477 * 0b10..Secure and Non-priviledge user access allowed.
1478 * 0b11..Secure and Priviledge user access allowed.
1479 */
1480#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK)
1481#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U)
1482#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U)
1483/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1484 * 0b00..Non-secure and Non-priviledge user access allowed.
1485 * 0b01..Non-secure and Privilege access allowed.
1486 * 0b10..Secure and Non-priviledge user access allowed.
1487 * 0b11..Secure and Priviledge user access allowed.
1488 */
1489#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK)
1490#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U)
1491#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U)
1492/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1493 * 0b00..Non-secure and Non-priviledge user access allowed.
1494 * 0b01..Non-secure and Privilege access allowed.
1495 * 0b10..Secure and Non-priviledge user access allowed.
1496 * 0b11..Secure and Priviledge user access allowed.
1497 */
1498#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK)
1499#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U)
1500#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U)
1501/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1502 * 0b00..Non-secure and Non-priviledge user access allowed.
1503 * 0b01..Non-secure and Privilege access allowed.
1504 * 0b10..Secure and Non-priviledge user access allowed.
1505 * 0b11..Secure and Priviledge user access allowed.
1506 */
1507#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK)
1508/*! @} */
1509
1510/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */
1511#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U)
1512
1513/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */
1514#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U)
1515
1516/*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */
1517/*! @{ */
1518#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U)
1519#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U)
1520/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1521 * 0b00..Non-secure and Non-priviledge user access allowed.
1522 * 0b01..Non-secure and Privilege access allowed.
1523 * 0b10..Secure and Non-priviledge user access allowed.
1524 * 0b11..Secure and Priviledge user access allowed.
1525 */
1526#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK)
1527#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U)
1528#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U)
1529/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1530 * 0b00..Non-secure and Non-priviledge user access allowed.
1531 * 0b01..Non-secure and Privilege access allowed.
1532 * 0b10..Secure and Non-priviledge user access allowed.
1533 * 0b11..Secure and Priviledge user access allowed.
1534 */
1535#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK)
1536#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U)
1537#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U)
1538/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1539 * 0b00..Non-secure and Non-priviledge user access allowed.
1540 * 0b01..Non-secure and Privilege access allowed.
1541 * 0b10..Secure and Non-priviledge user access allowed.
1542 * 0b11..Secure and Priviledge user access allowed.
1543 */
1544#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK)
1545#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U)
1546#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U)
1547/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1548 * 0b00..Non-secure and Non-priviledge user access allowed.
1549 * 0b01..Non-secure and Privilege access allowed.
1550 * 0b10..Secure and Non-priviledge user access allowed.
1551 * 0b11..Secure and Priviledge user access allowed.
1552 */
1553#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK)
1554#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U)
1555#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U)
1556/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1557 * 0b00..Non-secure and Non-priviledge user access allowed.
1558 * 0b01..Non-secure and Privilege access allowed.
1559 * 0b10..Secure and Non-priviledge user access allowed.
1560 * 0b11..Secure and Priviledge user access allowed.
1561 */
1562#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK)
1563#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U)
1564#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U)
1565/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1566 * 0b00..Non-secure and Non-priviledge user access allowed.
1567 * 0b01..Non-secure and Privilege access allowed.
1568 * 0b10..Secure and Non-priviledge user access allowed.
1569 * 0b11..Secure and Priviledge user access allowed.
1570 */
1571#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK)
1572#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U)
1573#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U)
1574/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1575 * 0b00..Non-secure and Non-priviledge user access allowed.
1576 * 0b01..Non-secure and Privilege access allowed.
1577 * 0b10..Secure and Non-priviledge user access allowed.
1578 * 0b11..Secure and Priviledge user access allowed.
1579 */
1580#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK)
1581#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U)
1582#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U)
1583/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1584 * 0b00..Non-secure and Non-priviledge user access allowed.
1585 * 0b01..Non-secure and Privilege access allowed.
1586 * 0b10..Secure and Non-priviledge user access allowed.
1587 * 0b11..Secure and Priviledge user access allowed.
1588 */
1589#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK)
1590/*! @} */
1591
1592/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */
1593#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U)
1594
1595/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */
1596#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U)
1597
1598/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */
1599/*! @{ */
1600#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U)
1601#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U)
1602/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF
1603 * 0b00..Non-secure and Non-priviledge user access allowed.
1604 * 0b01..Non-secure and Privilege access allowed.
1605 * 0b10..Secure and Non-priviledge user access allowed.
1606 * 0b11..Secure and Priviledge user access allowed.
1607 */
1608#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK)
1609/*! @} */
1610
1611/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */
1612#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U)
1613
1614/*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */
1615/*! @{ */
1616#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U)
1617#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U)
1618/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1619 * 0b00..Non-secure and Non-priviledge user access allowed.
1620 * 0b01..Non-secure and Privilege access allowed.
1621 * 0b10..Secure and Non-priviledge user access allowed.
1622 * 0b11..Secure and Priviledge user access allowed.
1623 */
1624#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK)
1625#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U)
1626#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U)
1627/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1628 * 0b00..Non-secure and Non-priviledge user access allowed.
1629 * 0b01..Non-secure and Privilege access allowed.
1630 * 0b10..Secure and Non-priviledge user access allowed.
1631 * 0b11..Secure and Priviledge user access allowed.
1632 */
1633#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK)
1634#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U)
1635#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U)
1636/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1637 * 0b00..Non-secure and Non-priviledge user access allowed.
1638 * 0b01..Non-secure and Privilege access allowed.
1639 * 0b10..Secure and Non-priviledge user access allowed.
1640 * 0b11..Secure and Priviledge user access allowed.
1641 */
1642#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK)
1643#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U)
1644#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U)
1645/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1646 * 0b00..Non-secure and Non-priviledge user access allowed.
1647 * 0b01..Non-secure and Privilege access allowed.
1648 * 0b10..Secure and Non-priviledge user access allowed.
1649 * 0b11..Secure and Priviledge user access allowed.
1650 */
1651#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK)
1652#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK (0x30000U)
1653#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT (16U)
1654/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1655 * 0b00..Non-secure and Non-priviledge user access allowed.
1656 * 0b01..Non-secure and Privilege access allowed.
1657 * 0b10..Secure and Non-priviledge user access allowed.
1658 * 0b11..Secure and Priviledge user access allowed.
1659 */
1660#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK)
1661#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK (0x300000U)
1662#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT (20U)
1663/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1664 * 0b00..Non-secure and Non-priviledge user access allowed.
1665 * 0b01..Non-secure and Privilege access allowed.
1666 * 0b10..Secure and Non-priviledge user access allowed.
1667 * 0b11..Secure and Priviledge user access allowed.
1668 */
1669#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK)
1670#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK (0x3000000U)
1671#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT (24U)
1672/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1673 * 0b00..Non-secure and Non-priviledge user access allowed.
1674 * 0b01..Non-secure and Privilege access allowed.
1675 * 0b10..Secure and Non-priviledge user access allowed.
1676 * 0b11..Secure and Priviledge user access allowed.
1677 */
1678#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK)
1679#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK (0x30000000U)
1680#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT (28U)
1681/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1682 * 0b00..Non-secure and Non-priviledge user access allowed.
1683 * 0b01..Non-secure and Privilege access allowed.
1684 * 0b10..Secure and Non-priviledge user access allowed.
1685 * 0b11..Secure and Priviledge user access allowed.
1686 */
1687#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK)
1688/*! @} */
1689
1690/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */
1691#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U)
1692
1693/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */
1694#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U)
1695
1696/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */
1697/*! @{ */
1698#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U)
1699#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U)
1700/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF
1701 * 0b00..Non-secure and Non-priviledge user access allowed.
1702 * 0b01..Non-secure and Privilege access allowed.
1703 * 0b10..Secure and Non-priviledge user access allowed.
1704 * 0b11..Secure and Priviledge user access allowed.
1705 */
1706#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK)
1707/*! @} */
1708
1709/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */
1710#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U)
1711
1712/*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */
1713/*! @{ */
1714#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U)
1715#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U)
1716/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1717 * 0b00..Non-secure and Non-priviledge user access allowed.
1718 * 0b01..Non-secure and Privilege access allowed.
1719 * 0b10..Secure and Non-priviledge user access allowed.
1720 * 0b11..Secure and Priviledge user access allowed.
1721 */
1722#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK)
1723#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U)
1724#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U)
1725/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1726 * 0b00..Non-secure and Non-priviledge user access allowed.
1727 * 0b01..Non-secure and Privilege access allowed.
1728 * 0b10..Secure and Non-priviledge user access allowed.
1729 * 0b11..Secure and Priviledge user access allowed.
1730 */
1731#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK)
1732#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U)
1733#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U)
1734/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1735 * 0b00..Non-secure and Non-priviledge user access allowed.
1736 * 0b01..Non-secure and Privilege access allowed.
1737 * 0b10..Secure and Non-priviledge user access allowed.
1738 * 0b11..Secure and Priviledge user access allowed.
1739 */
1740#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK)
1741#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U)
1742#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U)
1743/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1744 * 0b00..Non-secure and Non-priviledge user access allowed.
1745 * 0b01..Non-secure and Privilege access allowed.
1746 * 0b10..Secure and Non-priviledge user access allowed.
1747 * 0b11..Secure and Priviledge user access allowed.
1748 */
1749#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK)
1750#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U)
1751#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U)
1752/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1753 * 0b00..Non-secure and Non-priviledge user access allowed.
1754 * 0b01..Non-secure and Privilege access allowed.
1755 * 0b10..Secure and Non-priviledge user access allowed.
1756 * 0b11..Secure and Priviledge user access allowed.
1757 */
1758#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK)
1759#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U)
1760#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U)
1761/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1762 * 0b00..Non-secure and Non-priviledge user access allowed.
1763 * 0b01..Non-secure and Privilege access allowed.
1764 * 0b10..Secure and Non-priviledge user access allowed.
1765 * 0b11..Secure and Priviledge user access allowed.
1766 */
1767#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK)
1768#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U)
1769#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U)
1770/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1771 * 0b00..Non-secure and Non-priviledge user access allowed.
1772 * 0b01..Non-secure and Privilege access allowed.
1773 * 0b10..Secure and Non-priviledge user access allowed.
1774 * 0b11..Secure and Priviledge user access allowed.
1775 */
1776#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK)
1777#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U)
1778#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U)
1779/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1780 * 0b00..Non-secure and Non-priviledge user access allowed.
1781 * 0b01..Non-secure and Privilege access allowed.
1782 * 0b10..Secure and Non-priviledge user access allowed.
1783 * 0b11..Secure and Priviledge user access allowed.
1784 */
1785#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK)
1786/*! @} */
1787
1788/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */
1789#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U)
1790
1791/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */
1792#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (2U)
1793
1794/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */
1795/*! @{ */
1796#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U)
1797#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U)
1798/*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0
1799 * 0b00..Non-secure and Non-priviledge user access allowed.
1800 * 0b01..Non-secure and Privilege access allowed.
1801 * 0b10..Secure and Non-priviledge user access allowed.
1802 * 0b11..Secure and Priviledge user access allowed.
1803 */
1804#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK)
1805/*! @} */
1806
1807/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */
1808#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U)
1809
1810/*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */
1811/*! @{ */
1812#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U)
1813#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U)
1814/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1815 * 0b00..Non-secure and Non-priviledge user access allowed.
1816 * 0b01..Non-secure and Privilege access allowed.
1817 * 0b10..Secure and Non-priviledge user access allowed.
1818 * 0b11..Secure and Priviledge user access allowed.
1819 */
1820#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK)
1821#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U)
1822#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U)
1823/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1824 * 0b00..Non-secure and Non-priviledge user access allowed.
1825 * 0b01..Non-secure and Privilege access allowed.
1826 * 0b10..Secure and Non-priviledge user access allowed.
1827 * 0b11..Secure and Priviledge user access allowed.
1828 */
1829#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK)
1830#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U)
1831#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U)
1832/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1833 * 0b00..Non-secure and Non-priviledge user access allowed.
1834 * 0b01..Non-secure and Privilege access allowed.
1835 * 0b10..Secure and Non-priviledge user access allowed.
1836 * 0b11..Secure and Priviledge user access allowed.
1837 */
1838#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK)
1839#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U)
1840#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U)
1841/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1842 * 0b00..Non-secure and Non-priviledge user access allowed.
1843 * 0b01..Non-secure and Privilege access allowed.
1844 * 0b10..Secure and Non-priviledge user access allowed.
1845 * 0b11..Secure and Priviledge user access allowed.
1846 */
1847#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK)
1848#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK (0x30000U)
1849#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT (16U)
1850/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1851 * 0b00..Non-secure and Non-priviledge user access allowed.
1852 * 0b01..Non-secure and Privilege access allowed.
1853 * 0b10..Secure and Non-priviledge user access allowed.
1854 * 0b11..Secure and Priviledge user access allowed.
1855 */
1856#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK)
1857#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK (0x300000U)
1858#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT (20U)
1859/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1860 * 0b00..Non-secure and Non-priviledge user access allowed.
1861 * 0b01..Non-secure and Privilege access allowed.
1862 * 0b10..Secure and Non-priviledge user access allowed.
1863 * 0b11..Secure and Priviledge user access allowed.
1864 */
1865#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK)
1866#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK (0x3000000U)
1867#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT (24U)
1868/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1869 * 0b00..Non-secure and Non-priviledge user access allowed.
1870 * 0b01..Non-secure and Privilege access allowed.
1871 * 0b10..Secure and Non-priviledge user access allowed.
1872 * 0b11..Secure and Priviledge user access allowed.
1873 */
1874#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK)
1875#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK (0x30000000U)
1876#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT (28U)
1877/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1878 * 0b00..Non-secure and Non-priviledge user access allowed.
1879 * 0b01..Non-secure and Privilege access allowed.
1880 * 0b10..Secure and Non-priviledge user access allowed.
1881 * 0b11..Secure and Priviledge user access allowed.
1882 */
1883#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK)
1884/*! @} */
1885
1886/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */
1887#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U)
1888
1889/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */
1890#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (2U)
1891
1892/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */
1893/*! @{ */
1894#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U)
1895#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U)
1896/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF
1897 * 0b00..Non-secure and Non-priviledge user access allowed.
1898 * 0b01..Non-secure and Privilege access allowed.
1899 * 0b10..Secure and Non-priviledge user access allowed.
1900 * 0b11..Secure and Priviledge user access allowed.
1901 */
1902#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK)
1903/*! @} */
1904
1905/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */
1906#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U)
1907
1908/*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */
1909/*! @{ */
1910#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U)
1911#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U)
1912/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1913 * 0b00..Non-secure and Non-priviledge user access allowed.
1914 * 0b01..Non-secure and Privilege access allowed.
1915 * 0b10..Secure and Non-priviledge user access allowed.
1916 * 0b11..Secure and Priviledge user access allowed.
1917 */
1918#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK)
1919#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U)
1920#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U)
1921/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1922 * 0b00..Non-secure and Non-priviledge user access allowed.
1923 * 0b01..Non-secure and Privilege access allowed.
1924 * 0b10..Secure and Non-priviledge user access allowed.
1925 * 0b11..Secure and Priviledge user access allowed.
1926 */
1927#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK)
1928#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U)
1929#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U)
1930/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1931 * 0b00..Non-secure and Non-priviledge user access allowed.
1932 * 0b01..Non-secure and Privilege access allowed.
1933 * 0b10..Secure and Non-priviledge user access allowed.
1934 * 0b11..Secure and Priviledge user access allowed.
1935 */
1936#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK)
1937#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U)
1938#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U)
1939/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1940 * 0b00..Non-secure and Non-priviledge user access allowed.
1941 * 0b01..Non-secure and Privilege access allowed.
1942 * 0b10..Secure and Non-priviledge user access allowed.
1943 * 0b11..Secure and Priviledge user access allowed.
1944 */
1945#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK)
1946#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK (0x30000U)
1947#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT (16U)
1948/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1949 * 0b00..Non-secure and Non-priviledge user access allowed.
1950 * 0b01..Non-secure and Privilege access allowed.
1951 * 0b10..Secure and Non-priviledge user access allowed.
1952 * 0b11..Secure and Priviledge user access allowed.
1953 */
1954#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK)
1955#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK (0x300000U)
1956#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT (20U)
1957/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1958 * 0b00..Non-secure and Non-priviledge user access allowed.
1959 * 0b01..Non-secure and Privilege access allowed.
1960 * 0b10..Secure and Non-priviledge user access allowed.
1961 * 0b11..Secure and Priviledge user access allowed.
1962 */
1963#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK)
1964#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK (0x3000000U)
1965#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT (24U)
1966/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1967 * 0b00..Non-secure and Non-priviledge user access allowed.
1968 * 0b01..Non-secure and Privilege access allowed.
1969 * 0b10..Secure and Non-priviledge user access allowed.
1970 * 0b11..Secure and Priviledge user access allowed.
1971 */
1972#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK)
1973#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK (0x30000000U)
1974#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT (28U)
1975/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1976 * 0b00..Non-secure and Non-priviledge user access allowed.
1977 * 0b01..Non-secure and Privilege access allowed.
1978 * 0b10..Secure and Non-priviledge user access allowed.
1979 * 0b11..Secure and Priviledge user access allowed.
1980 */
1981#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK)
1982/*! @} */
1983
1984/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */
1985#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U)
1986
1987/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */
1988#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (2U)
1989
1990/*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */
1991/*! @{ */
1992#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U)
1993#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U)
1994/*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF
1995 * 0b00..Non-secure and Non-priviledge user access allowed.
1996 * 0b01..Non-secure and Privilege access allowed.
1997 * 0b10..Secure and Non-priviledge user access allowed.
1998 * 0b11..Secure and Priviledge user access allowed.
1999 */
2000#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK)
2001/*! @} */
2002
2003/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */
2004#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U)
2005
2006/*! @name SEC_CTRL_RAM3_MEM_RULE - Security access rules for RAM3 slaves. */
2007/*! @{ */
2008#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK (0x3U)
2009#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT (0U)
2010/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
2011 * 0b00..Non-secure and Non-priviledge user access allowed.
2012 * 0b01..Non-secure and Privilege access allowed.
2013 * 0b10..Secure and Non-priviledge user access allowed.
2014 * 0b11..Secure and Priviledge user access allowed.
2015 */
2016#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK)
2017#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK (0x30U)
2018#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT (4U)
2019/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
2020 * 0b00..Non-secure and Non-priviledge user access allowed.
2021 * 0b01..Non-secure and Privilege access allowed.
2022 * 0b10..Secure and Non-priviledge user access allowed.
2023 * 0b11..Secure and Priviledge user access allowed.
2024 */
2025#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK)
2026#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK (0x300U)
2027#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT (8U)
2028/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
2029 * 0b00..Non-secure and Non-priviledge user access allowed.
2030 * 0b01..Non-secure and Privilege access allowed.
2031 * 0b10..Secure and Non-priviledge user access allowed.
2032 * 0b11..Secure and Priviledge user access allowed.
2033 */
2034#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK)
2035#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK (0x3000U)
2036#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT (12U)
2037/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
2038 * 0b00..Non-secure and Non-priviledge user access allowed.
2039 * 0b01..Non-secure and Privilege access allowed.
2040 * 0b10..Secure and Non-priviledge user access allowed.
2041 * 0b11..Secure and Priviledge user access allowed.
2042 */
2043#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK)
2044#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK (0x30000U)
2045#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT (16U)
2046/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
2047 * 0b00..Non-secure and Non-priviledge user access allowed.
2048 * 0b01..Non-secure and Privilege access allowed.
2049 * 0b10..Secure and Non-priviledge user access allowed.
2050 * 0b11..Secure and Priviledge user access allowed.
2051 */
2052#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK)
2053#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK (0x300000U)
2054#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT (20U)
2055/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
2056 * 0b00..Non-secure and Non-priviledge user access allowed.
2057 * 0b01..Non-secure and Privilege access allowed.
2058 * 0b10..Secure and Non-priviledge user access allowed.
2059 * 0b11..Secure and Priviledge user access allowed.
2060 */
2061#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK)
2062#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK (0x3000000U)
2063#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT (24U)
2064/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
2065 * 0b00..Non-secure and Non-priviledge user access allowed.
2066 * 0b01..Non-secure and Privilege access allowed.
2067 * 0b10..Secure and Non-priviledge user access allowed.
2068 * 0b11..Secure and Priviledge user access allowed.
2069 */
2070#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK)
2071#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK (0x30000000U)
2072#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT (28U)
2073/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
2074 * 0b00..Non-secure and Non-priviledge user access allowed.
2075 * 0b01..Non-secure and Privilege access allowed.
2076 * 0b10..Secure and Non-priviledge user access allowed.
2077 * 0b11..Secure and Priviledge user access allowed.
2078 */
2079#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK)
2080/*! @} */
2081
2082/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */
2083#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT (1U)
2084
2085/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */
2086#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT2 (2U)
2087
2088/*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */
2089/*! @{ */
2090#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U)
2091#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U)
2092/*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF
2093 * 0b00..Non-secure and Non-priviledge user access allowed.
2094 * 0b01..Non-secure and Privilege access allowed.
2095 * 0b10..Secure and Non-priviledge user access allowed.
2096 * 0b11..Secure and Priviledge user access allowed.
2097 */
2098#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK)
2099/*! @} */
2100
2101/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */
2102#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U)
2103
2104/*! @name SEC_CTRL_RAM4_MEM_RULE - Security access rules for RAM4 slaves. */
2105/*! @{ */
2106#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK (0x3U)
2107#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT (0U)
2108/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
2109 * 0b00..Non-secure and Non-priviledge user access allowed.
2110 * 0b01..Non-secure and Privilege access allowed.
2111 * 0b10..Secure and Non-priviledge user access allowed.
2112 * 0b11..Secure and Priviledge user access allowed.
2113 */
2114#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK)
2115#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK (0x30U)
2116#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT (4U)
2117/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
2118 * 0b00..Non-secure and Non-priviledge user access allowed.
2119 * 0b01..Non-secure and Privilege access allowed.
2120 * 0b10..Secure and Non-priviledge user access allowed.
2121 * 0b11..Secure and Priviledge user access allowed.
2122 */
2123#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK)
2124#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK (0x300U)
2125#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT (8U)
2126/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
2127 * 0b00..Non-secure and Non-priviledge user access allowed.
2128 * 0b01..Non-secure and Privilege access allowed.
2129 * 0b10..Secure and Non-priviledge user access allowed.
2130 * 0b11..Secure and Priviledge user access allowed.
2131 */
2132#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK)
2133#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK (0x3000U)
2134#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT (12U)
2135/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
2136 * 0b00..Non-secure and Non-priviledge user access allowed.
2137 * 0b01..Non-secure and Privilege access allowed.
2138 * 0b10..Secure and Non-priviledge user access allowed.
2139 * 0b11..Secure and Priviledge user access allowed.
2140 */
2141#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK)
2142/*! @} */
2143
2144/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */
2145#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT (1U)
2146
2147/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */
2148#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT2 (1U)
2149
2150/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */
2151/*! @{ */
2152#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U)
2153#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U)
2154/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0
2155 * 0b00..Non-secure and Non-priviledge user access allowed.
2156 * 0b01..Non-secure and Privilege access allowed.
2157 * 0b10..Secure and Non-priviledge user access allowed.
2158 * 0b11..Secure and Priviledge user access allowed.
2159 */
2160#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK)
2161#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U)
2162#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U)
2163/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1
2164 * 0b00..Non-secure and Non-priviledge user access allowed.
2165 * 0b01..Non-secure and Privilege access allowed.
2166 * 0b10..Secure and Non-priviledge user access allowed.
2167 * 0b11..Secure and Priviledge user access allowed.
2168 */
2169#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK)
2170/*! @} */
2171
2172/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */
2173#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U)
2174
2175/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
2176/*! @{ */
2177#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U)
2178#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U)
2179/*! SYSCON_RULE - System Configuration
2180 * 0b00..Non-secure and Non-priviledge user access allowed.
2181 * 0b01..Non-secure and Privilege access allowed.
2182 * 0b10..Secure and Non-priviledge user access allowed.
2183 * 0b11..Secure and Priviledge user access allowed.
2184 */
2185#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK)
2186#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U)
2187#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U)
2188/*! IOCON_RULE - I/O Configuration
2189 * 0b00..Non-secure and Non-priviledge user access allowed.
2190 * 0b01..Non-secure and Privilege access allowed.
2191 * 0b10..Secure and Non-priviledge user access allowed.
2192 * 0b11..Secure and Priviledge user access allowed.
2193 */
2194#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK)
2195#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U)
2196#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U)
2197/*! GINT0_RULE - GPIO input Interrupt 0
2198 * 0b00..Non-secure and Non-priviledge user access allowed.
2199 * 0b01..Non-secure and Privilege access allowed.
2200 * 0b10..Secure and Non-priviledge user access allowed.
2201 * 0b11..Secure and Priviledge user access allowed.
2202 */
2203#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK)
2204#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U)
2205#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U)
2206/*! GINT1_RULE - GPIO input Interrupt 1
2207 * 0b00..Non-secure and Non-priviledge user access allowed.
2208 * 0b01..Non-secure and Privilege access allowed.
2209 * 0b10..Secure and Non-priviledge user access allowed.
2210 * 0b11..Secure and Priviledge user access allowed.
2211 */
2212#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK)
2213#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U)
2214#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U)
2215/*! PINT_RULE - Pin Interrupt and Pattern match
2216 * 0b00..Non-secure and Non-priviledge user access allowed.
2217 * 0b01..Non-secure and Privilege access allowed.
2218 * 0b10..Secure and Non-priviledge user access allowed.
2219 * 0b11..Secure and Priviledge user access allowed.
2220 */
2221#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK)
2222#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U)
2223#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U)
2224/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match
2225 * 0b00..Non-secure and Non-priviledge user access allowed.
2226 * 0b01..Non-secure and Privilege access allowed.
2227 * 0b10..Secure and Non-priviledge user access allowed.
2228 * 0b11..Secure and Priviledge user access allowed.
2229 */
2230#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK)
2231#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U)
2232#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U)
2233/*! INPUTMUX_RULE - Peripheral input multiplexing
2234 * 0b00..Non-secure and Non-priviledge user access allowed.
2235 * 0b01..Non-secure and Privilege access allowed.
2236 * 0b10..Secure and Non-priviledge user access allowed.
2237 * 0b11..Secure and Priviledge user access allowed.
2238 */
2239#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK)
2240/*! @} */
2241
2242/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */
2243#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U)
2244
2245/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
2246/*! @{ */
2247#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U)
2248#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U)
2249/*! CTIMER0_RULE - Standard counter/Timer 0
2250 * 0b00..Non-secure and Non-priviledge user access allowed.
2251 * 0b01..Non-secure and Privilege access allowed.
2252 * 0b10..Secure and Non-priviledge user access allowed.
2253 * 0b11..Secure and Priviledge user access allowed.
2254 */
2255#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK)
2256#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U)
2257#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U)
2258/*! CTIMER1_RULE - Standard counter/Timer 1
2259 * 0b00..Non-secure and Non-priviledge user access allowed.
2260 * 0b01..Non-secure and Privilege access allowed.
2261 * 0b10..Secure and Non-priviledge user access allowed.
2262 * 0b11..Secure and Priviledge user access allowed.
2263 */
2264#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK)
2265#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U)
2266#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U)
2267/*! WWDT_RULE - Windiwed wtachdog Timer
2268 * 0b00..Non-secure and Non-priviledge user access allowed.
2269 * 0b01..Non-secure and Privilege access allowed.
2270 * 0b10..Secure and Non-priviledge user access allowed.
2271 * 0b11..Secure and Priviledge user access allowed.
2272 */
2273#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK)
2274#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U)
2275#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U)
2276/*! MRT_RULE - Multi-rate Timer
2277 * 0b00..Non-secure and Non-priviledge user access allowed.
2278 * 0b01..Non-secure and Privilege access allowed.
2279 * 0b10..Secure and Non-priviledge user access allowed.
2280 * 0b11..Secure and Priviledge user access allowed.
2281 */
2282#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK)
2283#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U)
2284#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U)
2285/*! UTICK_RULE - Micro-Timer
2286 * 0b00..Non-secure and Non-priviledge user access allowed.
2287 * 0b01..Non-secure and Privilege access allowed.
2288 * 0b10..Secure and Non-priviledge user access allowed.
2289 * 0b11..Secure and Priviledge user access allowed.
2290 */
2291#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK)
2292/*! @} */
2293
2294/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */
2295#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U)
2296
2297/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
2298/*! @{ */
2299#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U)
2300#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U)
2301/*! ANACTRL_RULE - Analog Modules controller
2302 * 0b00..Non-secure and Non-priviledge user access allowed.
2303 * 0b01..Non-secure and Privilege access allowed.
2304 * 0b10..Secure and Non-priviledge user access allowed.
2305 * 0b11..Secure and Priviledge user access allowed.
2306 */
2307#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK)
2308/*! @} */
2309
2310/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */
2311#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U)
2312
2313/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2314/*! @{ */
2315#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U)
2316#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U)
2317/*! PMC_RULE - Power Management Controller
2318 * 0b00..Non-secure and Non-priviledge user access allowed.
2319 * 0b01..Non-secure and Privilege access allowed.
2320 * 0b10..Secure and Non-priviledge user access allowed.
2321 * 0b11..Secure and Priviledge user access allowed.
2322 */
2323#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK)
2324#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U)
2325#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U)
2326/*! SYSCTRL_RULE - System Controller
2327 * 0b00..Non-secure and Non-priviledge user access allowed.
2328 * 0b01..Non-secure and Privilege access allowed.
2329 * 0b10..Secure and Non-priviledge user access allowed.
2330 * 0b11..Secure and Priviledge user access allowed.
2331 */
2332#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK)
2333/*! @} */
2334
2335/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */
2336#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U)
2337
2338/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2339/*! @{ */
2340#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U)
2341#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U)
2342/*! CTIMER2_RULE - Standard counter/Timer 2
2343 * 0b00..Non-secure and Non-priviledge user access allowed.
2344 * 0b01..Non-secure and Privilege access allowed.
2345 * 0b10..Secure and Non-priviledge user access allowed.
2346 * 0b11..Secure and Priviledge user access allowed.
2347 */
2348#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK)
2349#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U)
2350#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U)
2351/*! CTIMER3_RULE - Standard counter/Timer 3
2352 * 0b00..Non-secure and Non-priviledge user access allowed.
2353 * 0b01..Non-secure and Privilege access allowed.
2354 * 0b10..Secure and Non-priviledge user access allowed.
2355 * 0b11..Secure and Priviledge user access allowed.
2356 */
2357#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK)
2358#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U)
2359#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U)
2360/*! CTIMER4_RULE - Standard counter/Timer 4
2361 * 0b00..Non-secure and Non-priviledge user access allowed.
2362 * 0b01..Non-secure and Privilege access allowed.
2363 * 0b10..Secure and Non-priviledge user access allowed.
2364 * 0b11..Secure and Priviledge user access allowed.
2365 */
2366#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK)
2367#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U)
2368#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U)
2369/*! RTC_RULE - Real Time Counter
2370 * 0b00..Non-secure and Non-priviledge user access allowed.
2371 * 0b01..Non-secure and Privilege access allowed.
2372 * 0b10..Secure and Non-priviledge user access allowed.
2373 * 0b11..Secure and Priviledge user access allowed.
2374 */
2375#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK)
2376#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U)
2377#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U)
2378/*! OSEVENT_RULE - OS Event Timer
2379 * 0b00..Non-secure and Non-priviledge user access allowed.
2380 * 0b01..Non-secure and Privilege access allowed.
2381 * 0b10..Secure and Non-priviledge user access allowed.
2382 * 0b11..Secure and Priviledge user access allowed.
2383 */
2384#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK)
2385/*! @} */
2386
2387/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */
2388#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U)
2389
2390/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2391/*! @{ */
2392#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U)
2393#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U)
2394/*! FLASH_CTRL_RULE - Flash Controller
2395 * 0b00..Non-secure and Non-priviledge user access allowed.
2396 * 0b01..Non-secure and Privilege access allowed.
2397 * 0b10..Secure and Non-priviledge user access allowed.
2398 * 0b11..Secure and Priviledge user access allowed.
2399 */
2400#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK)
2401#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U)
2402#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U)
2403/*! PRINCE_RULE - Prince
2404 * 0b00..Non-secure and Non-priviledge user access allowed.
2405 * 0b01..Non-secure and Privilege access allowed.
2406 * 0b10..Secure and Non-priviledge user access allowed.
2407 * 0b11..Secure and Priviledge user access allowed.
2408 */
2409#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK)
2410/*! @} */
2411
2412/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */
2413#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U)
2414
2415/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2416/*! @{ */
2417#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U)
2418#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U)
2419/*! USBHPHY_RULE - USB High Speed Phy controller
2420 * 0b00..Non-secure and Non-priviledge user access allowed.
2421 * 0b01..Non-secure and Privilege access allowed.
2422 * 0b10..Secure and Non-priviledge user access allowed.
2423 * 0b11..Secure and Priviledge user access allowed.
2424 */
2425#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK)
2426#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U)
2427#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U)
2428/*! RNG_RULE - True Random Number Generator
2429 * 0b00..Non-secure and Non-priviledge user access allowed.
2430 * 0b01..Non-secure and Privilege access allowed.
2431 * 0b10..Secure and Non-priviledge user access allowed.
2432 * 0b11..Secure and Priviledge user access allowed.
2433 */
2434#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK)
2435#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U)
2436#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U)
2437/*! PUF_RULE - PUF
2438 * 0b00..Non-secure and Non-priviledge user access allowed.
2439 * 0b01..Non-secure and Privilege access allowed.
2440 * 0b10..Secure and Non-priviledge user access allowed.
2441 * 0b11..Secure and Priviledge user access allowed.
2442 */
2443#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK)
2444#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U)
2445#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U)
2446/*! PLU_RULE - Programmable Look-Up logic
2447 * 0b00..Non-secure and Non-priviledge user access allowed.
2448 * 0b01..Non-secure and Privilege access allowed.
2449 * 0b10..Secure and Non-priviledge user access allowed.
2450 * 0b11..Secure and Priviledge user access allowed.
2451 */
2452#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK)
2453/*! @} */
2454
2455/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */
2456#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U)
2457
2458/*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */
2459/*! @{ */
2460#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK (0x300U)
2461#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT (8U)
2462/*! DMA0_RULE - DMA Controller
2463 * 0b00..Non-secure and Non-priviledge user access allowed.
2464 * 0b01..Non-secure and Privilege access allowed.
2465 * 0b10..Secure and Non-priviledge user access allowed.
2466 * 0b11..Secure and Priviledge user access allowed.
2467 */
2468#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK)
2469#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U)
2470#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U)
2471/*! FS_USB_DEV_RULE - USB Full-speed device
2472 * 0b00..Non-secure and Non-priviledge user access allowed.
2473 * 0b01..Non-secure and Privilege access allowed.
2474 * 0b10..Secure and Non-priviledge user access allowed.
2475 * 0b11..Secure and Priviledge user access allowed.
2476 */
2477#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK)
2478#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK (0x300000U)
2479#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT (20U)
2480/*! SCT_RULE - SCTimer
2481 * 0b00..Non-secure and Non-priviledge user access allowed.
2482 * 0b01..Non-secure and Privilege access allowed.
2483 * 0b10..Secure and Non-priviledge user access allowed.
2484 * 0b11..Secure and Priviledge user access allowed.
2485 */
2486#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK)
2487#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U)
2488#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U)
2489/*! FLEXCOMM0_RULE - Flexcomm interface 0
2490 * 0b00..Non-secure and Non-priviledge user access allowed.
2491 * 0b01..Non-secure and Privilege access allowed.
2492 * 0b10..Secure and Non-priviledge user access allowed.
2493 * 0b11..Secure and Priviledge user access allowed.
2494 */
2495#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK)
2496#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U)
2497#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U)
2498/*! FLEXCOMM1_RULE - Flexcomm interface 1
2499 * 0b00..Non-secure and Non-priviledge user access allowed.
2500 * 0b01..Non-secure and Privilege access allowed.
2501 * 0b10..Secure and Non-priviledge user access allowed.
2502 * 0b11..Secure and Priviledge user access allowed.
2503 */
2504#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK)
2505/*! @} */
2506
2507/*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */
2508/*! @{ */
2509#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U)
2510#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U)
2511/*! FLEXCOMM2_RULE - Flexcomm interface 2
2512 * 0b00..Non-secure and Non-priviledge user access allowed.
2513 * 0b01..Non-secure and Privilege access allowed.
2514 * 0b10..Secure and Non-priviledge user access allowed.
2515 * 0b11..Secure and Priviledge user access allowed.
2516 */
2517#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK)
2518#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U)
2519#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U)
2520/*! FLEXCOMM3_RULE - Flexcomm interface 3
2521 * 0b00..Non-secure and Non-priviledge user access allowed.
2522 * 0b01..Non-secure and Privilege access allowed.
2523 * 0b10..Secure and Non-priviledge user access allowed.
2524 * 0b11..Secure and Priviledge user access allowed.
2525 */
2526#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK)
2527#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U)
2528#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U)
2529/*! FLEXCOMM4_RULE - Flexcomm interface 4
2530 * 0b00..Non-secure and Non-priviledge user access allowed.
2531 * 0b01..Non-secure and Privilege access allowed.
2532 * 0b10..Secure and Non-priviledge user access allowed.
2533 * 0b11..Secure and Priviledge user access allowed.
2534 */
2535#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK)
2536#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK (0x3000U)
2537#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT (12U)
2538/*! MAILBOX_RULE - Inter CPU communication Mailbox
2539 * 0b00..Non-secure and Non-priviledge user access allowed.
2540 * 0b01..Non-secure and Privilege access allowed.
2541 * 0b10..Secure and Non-priviledge user access allowed.
2542 * 0b11..Secure and Priviledge user access allowed.
2543 */
2544#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK)
2545#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U)
2546#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U)
2547/*! GPIO0_RULE - High Speed GPIO
2548 * 0b00..Non-secure and Non-priviledge user access allowed.
2549 * 0b01..Non-secure and Privilege access allowed.
2550 * 0b10..Secure and Non-priviledge user access allowed.
2551 * 0b11..Secure and Priviledge user access allowed.
2552 */
2553#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK)
2554/*! @} */
2555
2556/*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */
2557/*! @{ */
2558#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U)
2559#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U)
2560/*! USB_HS_DEV_RULE - USB high Speed device registers
2561 * 0b00..Non-secure and Non-priviledge user access allowed.
2562 * 0b01..Non-secure and Privilege access allowed.
2563 * 0b10..Secure and Non-priviledge user access allowed.
2564 * 0b11..Secure and Priviledge user access allowed.
2565 */
2566#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK)
2567#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK (0x300000U)
2568#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT (20U)
2569/*! CRC_RULE - CRC engine
2570 * 0b00..Non-secure and Non-priviledge user access allowed.
2571 * 0b01..Non-secure and Privilege access allowed.
2572 * 0b10..Secure and Non-priviledge user access allowed.
2573 * 0b11..Secure and Priviledge user access allowed.
2574 */
2575#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK)
2576#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U)
2577#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U)
2578/*! FLEXCOMM5_RULE - Flexcomm interface 5
2579 * 0b00..Non-secure and Non-priviledge user access allowed.
2580 * 0b01..Non-secure and Privilege access allowed.
2581 * 0b10..Secure and Non-priviledge user access allowed.
2582 * 0b11..Secure and Priviledge user access allowed.
2583 */
2584#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK)
2585#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U)
2586#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U)
2587/*! FLEXCOMM6_RULE - Flexcomm interface 6
2588 * 0b00..Non-secure and Non-priviledge user access allowed.
2589 * 0b01..Non-secure and Privilege access allowed.
2590 * 0b10..Secure and Non-priviledge user access allowed.
2591 * 0b11..Secure and Priviledge user access allowed.
2592 */
2593#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK)
2594/*! @} */
2595
2596/*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */
2597/*! @{ */
2598#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U)
2599#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U)
2600/*! FLEXCOMM7_RULE - Flexcomm interface 7
2601 * 0b00..Non-secure and Non-priviledge user access allowed.
2602 * 0b01..Non-secure and Privilege access allowed.
2603 * 0b10..Secure and Non-priviledge user access allowed.
2604 * 0b11..Secure and Priviledge user access allowed.
2605 */
2606#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK)
2607#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK (0x3000U)
2608#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT (12U)
2609/*! SDIO_RULE - SDMMC card interface
2610 * 0b00..Non-secure and Non-priviledge user access allowed.
2611 * 0b01..Non-secure and Privilege access allowed.
2612 * 0b10..Secure and Non-priviledge user access allowed.
2613 * 0b11..Secure and Priviledge user access allowed.
2614 */
2615#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK)
2616#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U)
2617#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U)
2618/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP)
2619 * 0b00..Non-secure and Non-priviledge user access allowed.
2620 * 0b01..Non-secure and Privilege access allowed.
2621 * 0b10..Secure and Non-priviledge user access allowed.
2622 * 0b11..Secure and Priviledge user access allowed.
2623 */
2624#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK)
2625#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U)
2626#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U)
2627/*! HS_LSPI_RULE - High Speed SPI
2628 * 0b00..Non-secure and Non-priviledge user access allowed.
2629 * 0b01..Non-secure and Privilege access allowed.
2630 * 0b10..Secure and Non-priviledge user access allowed.
2631 * 0b11..Secure and Priviledge user access allowed.
2632 */
2633#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK)
2634/*! @} */
2635
2636/*! @name SEC_CTRL_AHB_PORT10_SLAVE0_RULE - Security access rules for AHB peripherals. */
2637/*! @{ */
2638#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK (0x3U)
2639#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT (0U)
2640/*! ADC_RULE - ADC
2641 * 0b00..Non-secure and Non-priviledge user access allowed.
2642 * 0b01..Non-secure and Privilege access allowed.
2643 * 0b10..Secure and Non-priviledge user access allowed.
2644 * 0b11..Secure and Priviledge user access allowed.
2645 */
2646#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK)
2647#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U)
2648#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U)
2649/*! USB_FS_HOST_RULE - USB Full Speed Host registers.
2650 * 0b00..Non-secure and Non-priviledge user access allowed.
2651 * 0b01..Non-secure and Privilege access allowed.
2652 * 0b10..Secure and Non-priviledge user access allowed.
2653 * 0b11..Secure and Priviledge user access allowed.
2654 */
2655#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK)
2656#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U)
2657#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U)
2658/*! USB_HS_HOST_RULE - USB High speed host registers
2659 * 0b00..Non-secure and Non-priviledge user access allowed.
2660 * 0b01..Non-secure and Privilege access allowed.
2661 * 0b10..Secure and Non-priviledge user access allowed.
2662 * 0b11..Secure and Priviledge user access allowed.
2663 */
2664#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK)
2665#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK (0x30000U)
2666#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT (16U)
2667/*! HASH_RULE - SHA-2 crypto registers
2668 * 0b00..Non-secure and Non-priviledge user access allowed.
2669 * 0b01..Non-secure and Privilege access allowed.
2670 * 0b10..Secure and Non-priviledge user access allowed.
2671 * 0b11..Secure and Priviledge user access allowed.
2672 */
2673#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK)
2674#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U)
2675#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT (20U)
2676/*! CASPER_RULE - RSA/ECC crypto accelerator
2677 * 0b00..Non-secure and Non-priviledge user access allowed.
2678 * 0b01..Non-secure and Privilege access allowed.
2679 * 0b10..Secure and Non-priviledge user access allowed.
2680 * 0b11..Secure and Priviledge user access allowed.
2681 */
2682#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK)
2683#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK (0x3000000U)
2684#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT (24U)
2685/*! PQ_RULE - Power Quad (CPU0 processor hardware accelerator)
2686 * 0b00..Non-secure and Non-priviledge user access allowed.
2687 * 0b01..Non-secure and Privilege access allowed.
2688 * 0b10..Secure and Non-priviledge user access allowed.
2689 * 0b11..Secure and Priviledge user access allowed.
2690 */
2691#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK)
2692#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U)
2693#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT (28U)
2694/*! DMA1_RULE - DMA Controller (Secure)
2695 * 0b00..Non-secure and Non-priviledge user access allowed.
2696 * 0b01..Non-secure and Privilege access allowed.
2697 * 0b10..Secure and Non-priviledge user access allowed.
2698 * 0b11..Secure and Priviledge user access allowed.
2699 */
2700#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK)
2701/*! @} */
2702
2703/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE */
2704#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_COUNT (1U)
2705
2706/*! @name SEC_CTRL_AHB_PORT10_SLAVE1_RULE - Security access rules for AHB peripherals. */
2707/*! @{ */
2708#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U)
2709#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U)
2710/*! GPIO1_RULE - Secure High Speed GPIO
2711 * 0b00..Non-secure and Non-priviledge user access allowed.
2712 * 0b01..Non-secure and Privilege access allowed.
2713 * 0b10..Secure and Non-priviledge user access allowed.
2714 * 0b11..Secure and Priviledge user access allowed.
2715 */
2716#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK)
2717#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U)
2718#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U)
2719/*! AHB_SEC_CTRL_RULE - AHB Secure Controller
2720 * 0b00..Non-secure and Non-priviledge user access allowed.
2721 * 0b01..Non-secure and Privilege access allowed.
2722 * 0b10..Secure and Non-priviledge user access allowed.
2723 * 0b11..Secure and Priviledge user access allowed.
2724 */
2725#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK)
2726/*! @} */
2727
2728/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE */
2729#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_COUNT (1U)
2730
2731/*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */
2732/*! @{ */
2733#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U)
2734#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U)
2735/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF
2736 * 0b00..Non-secure and Non-priviledge user access allowed.
2737 * 0b01..Non-secure and Privilege access allowed.
2738 * 0b10..Secure and Non-priviledge user access allowed.
2739 * 0b11..Secure and Priviledge user access allowed.
2740 */
2741#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK)
2742#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U)
2743#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U)
2744/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF
2745 * 0b00..Non-secure and Non-priviledge user access allowed.
2746 * 0b01..Non-secure and Privilege access allowed.
2747 * 0b10..Secure and Non-priviledge user access allowed.
2748 * 0b11..Secure and Priviledge user access allowed.
2749 */
2750#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK)
2751#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U)
2752#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U)
2753/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF
2754 * 0b00..Non-secure and Non-priviledge user access allowed.
2755 * 0b01..Non-secure and Privilege access allowed.
2756 * 0b10..Secure and Non-priviledge user access allowed.
2757 * 0b11..Secure and Priviledge user access allowed.
2758 */
2759#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK)
2760#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U)
2761#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U)
2762/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF
2763 * 0b00..Non-secure and Non-priviledge user access allowed.
2764 * 0b01..Non-secure and Privilege access allowed.
2765 * 0b10..Secure and Non-priviledge user access allowed.
2766 * 0b11..Secure and Priviledge user access allowed.
2767 */
2768#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK)
2769/*! @} */
2770
2771/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */
2772#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U)
2773
2774/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */
2775#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U)
2776
2777/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */
2778/*! @{ */
2779#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U)
2780#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U)
2781/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF
2782 * 0b00..Non-secure and Non-priviledge user access allowed.
2783 * 0b01..Non-secure and Privilege access allowed.
2784 * 0b10..Secure and Non-priviledge user access allowed.
2785 * 0b11..Secure and Priviledge user access allowed.
2786 */
2787#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK)
2788/*! @} */
2789
2790/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */
2791#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U)
2792
2793/*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */
2794/*! @{ */
2795#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U)
2796#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U)
2797/*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF
2798 * 0b00..Non-secure and Non-priviledge user access allowed.
2799 * 0b01..Non-secure and Privilege access allowed.
2800 * 0b10..Secure and Non-priviledge user access allowed.
2801 * 0b11..Secure and Priviledge user access allowed.
2802 */
2803#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK)
2804#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U)
2805#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U)
2806/*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF
2807 * 0b00..Non-secure and Non-priviledge user access allowed.
2808 * 0b01..Non-secure and Privilege access allowed.
2809 * 0b10..Secure and Non-priviledge user access allowed.
2810 * 0b11..Secure and Priviledge user access allowed.
2811 */
2812#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK)
2813#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U)
2814#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U)
2815/*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF
2816 * 0b00..Non-secure and Non-priviledge user access allowed.
2817 * 0b01..Non-secure and Privilege access allowed.
2818 * 0b10..Secure and Non-priviledge user access allowed.
2819 * 0b11..Secure and Priviledge user access allowed.
2820 */
2821#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK)
2822#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U)
2823#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U)
2824/*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF
2825 * 0b00..Non-secure and Non-priviledge user access allowed.
2826 * 0b01..Non-secure and Privilege access allowed.
2827 * 0b10..Secure and Non-priviledge user access allowed.
2828 * 0b11..Secure and Priviledge user access allowed.
2829 */
2830#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK)
2831/*! @} */
2832
2833/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */
2834#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U)
2835
2836/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */
2837#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U)
2838
2839/*! @name SEC_VIO_ADDR - most recent security violation address for AHB port n */
2840/*! @{ */
2841#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU)
2842#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U)
2843/*! SEC_VIO_ADDR - security violation address for AHB port
2844 */
2845#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK)
2846/*! @} */
2847
2848/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */
2849#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (12U)
2850
2851/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB port n */
2852/*! @{ */
2853#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U)
2854#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U)
2855/*! SEC_VIO_INFO_WRITE - security violation access read/write indicator.
2856 * 0b0..Read access.
2857 * 0b1..Write access.
2858 */
2859#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK)
2860#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U)
2861#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U)
2862/*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator.
2863 * 0b0..Code access.
2864 * 0b1..Data access.
2865 */
2866#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK)
2867#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U)
2868#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U)
2869/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level
2870 */
2871#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK)
2872#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U)
2873#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U)
2874/*! SEC_VIO_INFO_MASTER - security violation master number
2875 * 0b0000..CPU0 Code.
2876 * 0b0001..CPU0 System.
2877 * 0b0010..CPU1 Data.
2878 * 0b0011..CPU1 System.
2879 * 0b0100..USB-HS Device.
2880 * 0b0101..SDMA0.
2881 * 0b1000..SDIO.
2882 * 0b1001..PowerQuad.
2883 * 0b1010..HASH.
2884 * 0b1011..USB-FS Host.
2885 * 0b1100..SDMA1.
2886 */
2887#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK)
2888/*! @} */
2889
2890/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */
2891#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (12U)
2892
2893/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */
2894/*! @{ */
2895#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U)
2896#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U)
2897/*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear.
2898 * 0b0..Not valid.
2899 * 0b1..Valid (violation occurred).
2900 */
2901#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK)
2902#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U)
2903#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U)
2904/*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear.
2905 * 0b0..Not valid.
2906 * 0b1..Valid (violation occurred).
2907 */
2908#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK)
2909#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U)
2910#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U)
2911/*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear.
2912 * 0b0..Not valid.
2913 * 0b1..Valid (violation occurred).
2914 */
2915#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK)
2916#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U)
2917#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U)
2918/*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear.
2919 * 0b0..Not valid.
2920 * 0b1..Valid (violation occurred).
2921 */
2922#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK)
2923#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U)
2924#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U)
2925/*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear.
2926 * 0b0..Not valid.
2927 * 0b1..Valid (violation occurred).
2928 */
2929#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK)
2930#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U)
2931#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U)
2932/*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear.
2933 * 0b0..Not valid.
2934 * 0b1..Valid (violation occurred).
2935 */
2936#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK)
2937#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U)
2938#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U)
2939/*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear.
2940 * 0b0..Not valid.
2941 * 0b1..Valid (violation occurred).
2942 */
2943#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK)
2944#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U)
2945#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U)
2946/*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear.
2947 * 0b0..Not valid.
2948 * 0b1..Valid (violation occurred).
2949 */
2950#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK)
2951#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U)
2952#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U)
2953/*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear.
2954 * 0b0..Not valid.
2955 * 0b1..Valid (violation occurred).
2956 */
2957#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK)
2958#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U)
2959#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U)
2960/*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear.
2961 * 0b0..Not valid.
2962 * 0b1..Valid (violation occurred).
2963 */
2964#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK)
2965#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U)
2966#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U)
2967/*! VIO_INFO_VALID10 - violation information valid flag for AHB port 10. Write 1 to clear.
2968 * 0b0..Not valid.
2969 * 0b1..Valid (violation occurred).
2970 */
2971#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK)
2972#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U)
2973#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U)
2974/*! VIO_INFO_VALID11 - violation information valid flag for AHB port 11. Write 1 to clear.
2975 * 0b0..Not valid.
2976 * 0b1..Valid (violation occurred).
2977 */
2978#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK)
2979/*! @} */
2980
2981/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */
2982/*! @{ */
2983#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U)
2984#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U)
2985/*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0
2986 * 0b1..Pin state is readable by non-secure world.
2987 * 0b0..Pin state is blocked to non-secure world.
2988 */
2989#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK)
2990#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U)
2991#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U)
2992/*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1
2993 * 0b1..Pin state is readable by non-secure world.
2994 * 0b0..Pin state is blocked to non-secure world.
2995 */
2996#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK)
2997#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U)
2998#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U)
2999/*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2
3000 * 0b1..Pin state is readable by non-secure world.
3001 * 0b0..Pin state is blocked to non-secure world.
3002 */
3003#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK)
3004#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U)
3005#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U)
3006/*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3
3007 * 0b1..Pin state is readable by non-secure world.
3008 * 0b0..Pin state is blocked to non-secure world.
3009 */
3010#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK)
3011#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U)
3012#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U)
3013/*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4
3014 * 0b1..Pin state is readable by non-secure world.
3015 * 0b0..Pin state is blocked to non-secure world.
3016 */
3017#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK)
3018#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U)
3019#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U)
3020/*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5
3021 * 0b1..Pin state is readable by non-secure world.
3022 * 0b0..Pin state is blocked to non-secure world.
3023 */
3024#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK)
3025#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U)
3026#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U)
3027/*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6
3028 * 0b1..Pin state is readable by non-secure world.
3029 * 0b0..Pin state is blocked to non-secure world.
3030 */
3031#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK)
3032#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U)
3033#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U)
3034/*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7
3035 * 0b1..Pin state is readable by non-secure world.
3036 * 0b0..Pin state is blocked to non-secure world.
3037 */
3038#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK)
3039#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U)
3040#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U)
3041/*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8
3042 * 0b1..Pin state is readable by non-secure world.
3043 * 0b0..Pin state is blocked to non-secure world.
3044 */
3045#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK)
3046#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U)
3047#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U)
3048/*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9
3049 * 0b1..Pin state is readable by non-secure world.
3050 * 0b0..Pin state is blocked to non-secure world.
3051 */
3052#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK)
3053#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U)
3054#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U)
3055/*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10
3056 * 0b1..Pin state is readable by non-secure world.
3057 * 0b0..Pin state is blocked to non-secure world.
3058 */
3059#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK)
3060#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U)
3061#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U)
3062/*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11
3063 * 0b1..Pin state is readable by non-secure world.
3064 * 0b0..Pin state is blocked to non-secure world.
3065 */
3066#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK)
3067#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U)
3068#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U)
3069/*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12
3070 * 0b1..Pin state is readable by non-secure world.
3071 * 0b0..Pin state is blocked to non-secure world.
3072 */
3073#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK)
3074#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U)
3075#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U)
3076/*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13
3077 * 0b1..Pin state is readable by non-secure world.
3078 * 0b0..Pin state is blocked to non-secure world.
3079 */
3080#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK)
3081#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U)
3082#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U)
3083/*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14
3084 * 0b1..Pin state is readable by non-secure world.
3085 * 0b0..Pin state is blocked to non-secure world.
3086 */
3087#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK)
3088#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U)
3089#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U)
3090/*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15
3091 * 0b1..Pin state is readable by non-secure world.
3092 * 0b0..Pin state is blocked to non-secure world.
3093 */
3094#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK)
3095#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U)
3096#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U)
3097/*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16
3098 * 0b1..Pin state is readable by non-secure world.
3099 * 0b0..Pin state is blocked to non-secure world.
3100 */
3101#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK)
3102#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U)
3103#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U)
3104/*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17
3105 * 0b1..Pin state is readable by non-secure world.
3106 * 0b0..Pin state is blocked to non-secure world.
3107 */
3108#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK)
3109#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U)
3110#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U)
3111/*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18
3112 * 0b1..Pin state is readable by non-secure world.
3113 * 0b0..Pin state is blocked to non-secure world.
3114 */
3115#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK)
3116#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U)
3117#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U)
3118/*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19
3119 * 0b1..Pin state is readable by non-secure world.
3120 * 0b0..Pin state is blocked to non-secure world.
3121 */
3122#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK)
3123#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U)
3124#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U)
3125/*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20
3126 * 0b1..Pin state is readable by non-secure world.
3127 * 0b0..Pin state is blocked to non-secure world.
3128 */
3129#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK)
3130#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U)
3131#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U)
3132/*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21
3133 * 0b1..Pin state is readable by non-secure world.
3134 * 0b0..Pin state is blocked to non-secure world.
3135 */
3136#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK)
3137#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U)
3138#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U)
3139/*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22
3140 * 0b1..Pin state is readable by non-secure world.
3141 * 0b0..Pin state is blocked to non-secure world.
3142 */
3143#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK)
3144#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U)
3145#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U)
3146/*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23
3147 * 0b1..Pin state is readable by non-secure world.
3148 * 0b0..Pin state is blocked to non-secure world.
3149 */
3150#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK)
3151#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U)
3152#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U)
3153/*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24
3154 * 0b1..Pin state is readable by non-secure world.
3155 * 0b0..Pin state is blocked to non-secure world.
3156 */
3157#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK)
3158#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U)
3159#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U)
3160/*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25
3161 * 0b1..Pin state is readable by non-secure world.
3162 * 0b0..Pin state is blocked to non-secure world.
3163 */
3164#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK)
3165#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U)
3166#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U)
3167/*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26
3168 * 0b1..Pin state is readable by non-secure world.
3169 * 0b0..Pin state is blocked to non-secure world.
3170 */
3171#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK)
3172#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U)
3173#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U)
3174/*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27
3175 * 0b1..Pin state is readable by non-secure world.
3176 * 0b0..Pin state is blocked to non-secure world.
3177 */
3178#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK)
3179#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U)
3180#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U)
3181/*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28
3182 * 0b1..Pin state is readable by non-secure world.
3183 * 0b0..Pin state is blocked to non-secure world.
3184 */
3185#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK)
3186#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U)
3187#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U)
3188/*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29
3189 * 0b1..Pin state is readable by non-secure world.
3190 * 0b0..Pin state is blocked to non-secure world.
3191 */
3192#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK)
3193#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U)
3194#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U)
3195/*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30
3196 * 0b1..Pin state is readable by non-secure world.
3197 * 0b0..Pin state is blocked to non-secure world.
3198 */
3199#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK)
3200#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U)
3201#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U)
3202/*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31
3203 * 0b1..Pin state is readable by non-secure world.
3204 * 0b0..Pin state is blocked to non-secure world.
3205 */
3206#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK)
3207/*! @} */
3208
3209/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */
3210/*! @{ */
3211#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U)
3212#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U)
3213/*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0
3214 * 0b1..Pin state is readable by non-secure world.
3215 * 0b0..Pin state is blocked to non-secure world.
3216 */
3217#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK)
3218#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U)
3219#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U)
3220/*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1
3221 * 0b1..Pin state is readable by non-secure world.
3222 * 0b0..Pin state is blocked to non-secure world.
3223 */
3224#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK)
3225#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U)
3226#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U)
3227/*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2
3228 * 0b1..Pin state is readable by non-secure world.
3229 * 0b0..Pin state is blocked to non-secure world.
3230 */
3231#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK)
3232#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U)
3233#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U)
3234/*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3
3235 * 0b1..Pin state is readable by non-secure world.
3236 * 0b0..Pin state is blocked to non-secure world.
3237 */
3238#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK)
3239#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U)
3240#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U)
3241/*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4
3242 * 0b1..Pin state is readable by non-secure world.
3243 * 0b0..Pin state is blocked to non-secure world.
3244 */
3245#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK)
3246#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U)
3247#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U)
3248/*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5
3249 * 0b1..Pin state is readable by non-secure world.
3250 * 0b0..Pin state is blocked to non-secure world.
3251 */
3252#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK)
3253#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U)
3254#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U)
3255/*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6
3256 * 0b1..Pin state is readable by non-secure world.
3257 * 0b0..Pin state is blocked to non-secure world.
3258 */
3259#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK)
3260#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U)
3261#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U)
3262/*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7
3263 * 0b1..Pin state is readable by non-secure world.
3264 * 0b0..Pin state is blocked to non-secure world.
3265 */
3266#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK)
3267#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U)
3268#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U)
3269/*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8
3270 * 0b1..Pin state is readable by non-secure world.
3271 * 0b0..Pin state is blocked to non-secure world.
3272 */
3273#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK)
3274#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U)
3275#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U)
3276/*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9
3277 * 0b1..Pin state is readable by non-secure world.
3278 * 0b0..Pin state is blocked to non-secure world.
3279 */
3280#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK)
3281#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U)
3282#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U)
3283/*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10
3284 * 0b1..Pin state is readable by non-secure world.
3285 * 0b0..Pin state is blocked to non-secure world.
3286 */
3287#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK)
3288#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U)
3289#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U)
3290/*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11
3291 * 0b1..Pin state is readable by non-secure world.
3292 * 0b0..Pin state is blocked to non-secure world.
3293 */
3294#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK)
3295#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U)
3296#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U)
3297/*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12
3298 * 0b1..Pin state is readable by non-secure world.
3299 * 0b0..Pin state is blocked to non-secure world.
3300 */
3301#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK)
3302#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U)
3303#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U)
3304/*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13
3305 * 0b1..Pin state is readable by non-secure world.
3306 * 0b0..Pin state is blocked to non-secure world.
3307 */
3308#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK)
3309#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U)
3310#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U)
3311/*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14
3312 * 0b1..Pin state is readable by non-secure world.
3313 * 0b0..Pin state is blocked to non-secure world.
3314 */
3315#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK)
3316#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U)
3317#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U)
3318/*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15
3319 * 0b1..Pin state is readable by non-secure world.
3320 * 0b0..Pin state is blocked to non-secure world.
3321 */
3322#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK)
3323#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U)
3324#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U)
3325/*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16
3326 * 0b1..Pin state is readable by non-secure world.
3327 * 0b0..Pin state is blocked to non-secure world.
3328 */
3329#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK)
3330#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U)
3331#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U)
3332/*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17
3333 * 0b1..Pin state is readable by non-secure world.
3334 * 0b0..Pin state is blocked to non-secure world.
3335 */
3336#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK)
3337#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U)
3338#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U)
3339/*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18
3340 * 0b1..Pin state is readable by non-secure world.
3341 * 0b0..Pin state is blocked to non-secure world.
3342 */
3343#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK)
3344#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U)
3345#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U)
3346/*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19
3347 * 0b1..Pin state is readable by non-secure world.
3348 * 0b0..Pin state is blocked to non-secure world.
3349 */
3350#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK)
3351#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U)
3352#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U)
3353/*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20
3354 * 0b1..Pin state is readable by non-secure world.
3355 * 0b0..Pin state is blocked to non-secure world.
3356 */
3357#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK)
3358#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U)
3359#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U)
3360/*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21
3361 * 0b1..Pin state is readable by non-secure world.
3362 * 0b0..Pin state is blocked to non-secure world.
3363 */
3364#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK)
3365#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U)
3366#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U)
3367/*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22
3368 * 0b1..Pin state is readable by non-secure world.
3369 * 0b0..Pin state is blocked to non-secure world.
3370 */
3371#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK)
3372#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U)
3373#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U)
3374/*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23
3375 * 0b1..Pin state is readable by non-secure world.
3376 * 0b0..Pin state is blocked to non-secure world.
3377 */
3378#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK)
3379#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U)
3380#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U)
3381/*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24
3382 * 0b1..Pin state is readable by non-secure world.
3383 * 0b0..Pin state is blocked to non-secure world.
3384 */
3385#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK)
3386#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U)
3387#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U)
3388/*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25
3389 * 0b1..Pin state is readable by non-secure world.
3390 * 0b0..Pin state is blocked to non-secure world.
3391 */
3392#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK)
3393#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U)
3394#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U)
3395/*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26
3396 * 0b1..Pin state is readable by non-secure world.
3397 * 0b0..Pin state is blocked to non-secure world.
3398 */
3399#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK)
3400#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U)
3401#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U)
3402/*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27
3403 * 0b1..Pin state is readable by non-secure world.
3404 * 0b0..Pin state is blocked to non-secure world.
3405 */
3406#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK)
3407#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U)
3408#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U)
3409/*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28
3410 * 0b1..Pin state is readable by non-secure world.
3411 * 0b0..Pin state is blocked to non-secure world.
3412 */
3413#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK)
3414#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U)
3415#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U)
3416/*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29
3417 * 0b1..Pin state is readable by non-secure world.
3418 * 0b0..Pin state is blocked to non-secure world.
3419 */
3420#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK)
3421#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U)
3422#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U)
3423/*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30
3424 * 0b1..Pin state is readable by non-secure world.
3425 * 0b0..Pin state is blocked to non-secure world.
3426 */
3427#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK)
3428#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U)
3429#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U)
3430/*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31
3431 * 0b1..Pin state is readable by non-secure world.
3432 * 0b0..Pin state is blocked to non-secure world.
3433 */
3434#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK)
3435/*! @} */
3436
3437/*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */
3438/*! @{ */
3439#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U)
3440#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U)
3441/*! SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts
3442 * 0b0..
3443 * 0b1..
3444 */
3445#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK)
3446#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U)
3447#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U)
3448/*! SDMA0_IRQ - System DMA 0 (non-secure) interrupt.
3449 * 0b0..
3450 * 0b1..
3451 */
3452#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK)
3453#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U)
3454#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U)
3455/*! GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt.
3456 * 0b0..
3457 * 0b1..
3458 */
3459#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK)
3460#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U)
3461#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U)
3462/*! GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt.
3463 * 0b0..
3464 * 0b1..
3465 */
3466#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK)
3467#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U)
3468#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U)
3469/*! GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt.
3470 * 0b0..
3471 * 0b1..
3472 */
3473#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK)
3474#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U)
3475#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U)
3476/*! GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt.
3477 * 0b0..
3478 * 0b1..
3479 */
3480#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK)
3481#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U)
3482#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U)
3483/*! GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt.
3484 * 0b0..
3485 * 0b1..
3486 */
3487#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK)
3488#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U)
3489#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U)
3490/*! GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt.
3491 * 0b0..
3492 * 0b1..
3493 */
3494#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK)
3495#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U)
3496#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U)
3497/*! UTICK_IRQ - Micro Tick Timer interrupt.
3498 * 0b0..
3499 * 0b1..
3500 */
3501#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK)
3502#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U)
3503#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U)
3504/*! MRT_IRQ - Multi-Rate Timer interrupt.
3505 * 0b0..
3506 * 0b1..
3507 */
3508#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK)
3509#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U)
3510#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U)
3511/*! CTIMER0_IRQ - Standard counter/timer 0 interrupt.
3512 * 0b0..
3513 * 0b1..
3514 */
3515#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK)
3516#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U)
3517#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U)
3518/*! CTIMER1_IRQ - Standard counter/timer 1 interrupt.
3519 * 0b0..
3520 * 0b1..
3521 */
3522#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK)
3523#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U)
3524#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U)
3525/*! SCT_IRQ - SCTimer/PWM interrupt.
3526 * 0b0..
3527 * 0b1..
3528 */
3529#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK)
3530#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U)
3531#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U)
3532/*! CTIMER3_IRQ - Standard counter/timer 3 interrupt.
3533 * 0b0..
3534 * 0b1..
3535 */
3536#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK)
3537#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U)
3538#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U)
3539/*! FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S).
3540 * 0b0..
3541 * 0b1..
3542 */
3543#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK)
3544#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U)
3545#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U)
3546/*! FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S).
3547 * 0b0..
3548 * 0b1..
3549 */
3550#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK)
3551#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U)
3552#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U)
3553/*! FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S).
3554 * 0b0..
3555 * 0b1..
3556 */
3557#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK)
3558#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U)
3559#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U)
3560/*! FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S).
3561 * 0b0..
3562 * 0b1..
3563 */
3564#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK)
3565#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U)
3566#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U)
3567/*! FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S).
3568 * 0b0..
3569 * 0b1..
3570 */
3571#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK)
3572#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U)
3573#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U)
3574/*! FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S).
3575 * 0b0..
3576 * 0b1..
3577 */
3578#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK)
3579#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U)
3580#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U)
3581/*! FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S).
3582 * 0b0..
3583 * 0b1..
3584 */
3585#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK)
3586#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U)
3587#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U)
3588/*! FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S).
3589 * 0b0..
3590 * 0b1..
3591 */
3592#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK)
3593#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U)
3594#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U)
3595/*! ADC_IRQ - General Purpose ADC interrupt.
3596 * 0b0..
3597 * 0b1..
3598 */
3599#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK)
3600#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U)
3601#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U)
3602/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written.
3603 * 0b0..
3604 * 0b1..
3605 */
3606#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK)
3607#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK (0x1000000U)
3608#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT (24U)
3609/*! ACMP_IRQ - Analog Comparator interrupt.
3610 * 0b0..
3611 * 0b1..
3612 */
3613#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK)
3614#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U)
3615#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U)
3616/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written.
3617 * 0b0..
3618 * 0b1..
3619 */
3620#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK)
3621#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U)
3622#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U)
3623/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written.
3624 * 0b0..
3625 * 0b1..
3626 */
3627#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK)
3628#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U)
3629#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U)
3630/*! USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt.
3631 * 0b0..
3632 * 0b1..
3633 */
3634#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK)
3635#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U)
3636#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U)
3637/*! USB0_IRQ - USB Full Speed Controller interrupt.
3638 * 0b0..
3639 * 0b1..
3640 */
3641#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK)
3642#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U)
3643#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U)
3644/*! RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ
3645 * 0b0..
3646 * 0b1..
3647 */
3648#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK)
3649#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK (0x40000000U)
3650#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT (30U)
3651/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written.
3652 * 0b0..
3653 * 0b1..
3654 */
3655#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK)
3656#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U)
3657#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U)
3658/*! MAILBOX_IRQ - Mailbox interrupt.
3659 * 0b0..
3660 * 0b1..
3661 */
3662#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK)
3663/*! @} */
3664
3665/*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */
3666/*! @{ */
3667#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U)
3668#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U)
3669/*! GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt.
3670 * 0b0..
3671 * 0b1..
3672 */
3673#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK)
3674#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U)
3675#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U)
3676/*! GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt.
3677 * 0b0..
3678 * 0b1..
3679 */
3680#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK)
3681#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U)
3682#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U)
3683/*! GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt.
3684 * 0b0..
3685 * 0b1..
3686 */
3687#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK)
3688#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U)
3689#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U)
3690/*! GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt.
3691 * 0b0..
3692 * 0b1..
3693 */
3694#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK)
3695#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U)
3696#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U)
3697/*! CTIMER2_IRQ - Standard counter/timer 2 interrupt.
3698 * 0b0..
3699 * 0b1..
3700 */
3701#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK)
3702#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U)
3703#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U)
3704/*! CTIMER4_IRQ - Standard counter/timer 4 interrupt.
3705 * 0b0..
3706 * 0b1..
3707 */
3708#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK)
3709#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U)
3710#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U)
3711/*! OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts
3712 * 0b0..
3713 * 0b1..
3714 */
3715#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK)
3716#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U)
3717#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U)
3718/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written.
3719 * 0b0..
3720 * 0b1..
3721 */
3722#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK)
3723#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U)
3724#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U)
3725/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written.
3726 * 0b0..
3727 * 0b1..
3728 */
3729#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK)
3730#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U)
3731#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U)
3732/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written.
3733 * 0b0..
3734 * 0b1..
3735 */
3736#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK)
3737#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U)
3738#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U)
3739/*! SDIO_IRQ - SDIO Controller interrupt.
3740 * 0b0..
3741 * 0b1..
3742 */
3743#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK)
3744#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U)
3745#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U)
3746/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written.
3747 * 0b0..
3748 * 0b1..
3749 */
3750#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK)
3751#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U)
3752#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U)
3753/*! RESERVED4 - Reserved. Read value is undefined, only zero should be written.
3754 * 0b0..
3755 * 0b1..
3756 */
3757#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK)
3758#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U)
3759#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U)
3760/*! RESERVED5 - Reserved. Read value is undefined, only zero should be written.
3761 * 0b0..
3762 * 0b1..
3763 */
3764#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK)
3765#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK (0x4000U)
3766#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT (14U)
3767/*! USB1_PHY_IRQ - USB High Speed PHY Controller interrupt.
3768 * 0b0..
3769 * 0b1..
3770 */
3771#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK)
3772#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U)
3773#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U)
3774/*! USB1_IRQ - USB High Speed Controller interrupt.
3775 * 0b0..
3776 * 0b1..
3777 */
3778#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK)
3779#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U)
3780#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U)
3781/*! USB1_NEEDCLK - USB High Speed Controller Clock request interrupt.
3782 * 0b0..
3783 * 0b1..
3784 */
3785#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK)
3786#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U)
3787#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U)
3788/*! SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt.
3789 * 0b0..
3790 * 0b1..
3791 */
3792#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK)
3793#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U)
3794#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U)
3795/*! SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt.
3796 * 0b0..
3797 * 0b1..
3798 */
3799#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK)
3800#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U)
3801#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U)
3802/*! SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt.
3803 * 0b0..
3804 * 0b1..
3805 */
3806#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK)
3807#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U)
3808#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U)
3809/*! PLU_IRQ - Programmable Look-Up Controller interrupt.
3810 * 0b0..
3811 * 0b1..
3812 */
3813#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK)
3814#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U)
3815#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U)
3816/*! SEC_VIO_IRQ - Security Violation interrupt.
3817 * 0b0..
3818 * 0b1..
3819 */
3820#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK)
3821#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U)
3822#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U)
3823/*! SHA_IRQ - HASH-AES interrupt.
3824 * 0b0..
3825 * 0b1..
3826 */
3827#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK)
3828#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U)
3829#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U)
3830/*! CASPER_IRQ - CASPER interrupt.
3831 * 0b0..
3832 * 0b1..
3833 */
3834#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK)
3835#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK (0x1000000U)
3836#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT (24U)
3837/*! PUFKEY_IRQ - PUF interrupt.
3838 * 0b0..
3839 * 0b1..
3840 */
3841#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK)
3842#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U)
3843#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U)
3844/*! PQ_IRQ - Power Quad interrupt.
3845 * 0b0..
3846 * 0b1..
3847 */
3848#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK)
3849#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U)
3850#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U)
3851/*! SDMA1_IRQ - System DMA 1 (Secure) interrupt
3852 * 0b0..
3853 * 0b1..
3854 */
3855#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK)
3856#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U)
3857#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U)
3858/*! LSPI_HS_IRQ - High Speed SPI interrupt
3859 * 0b0..
3860 * 0b1..
3861 */
3862#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK)
3863/*! @} */
3864
3865/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */
3866/*! @{ */
3867#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U)
3868#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U)
3869/*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock.
3870 * 0b10..Writable.
3871 * 0b01..Restricted mode.
3872 */
3873#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK)
3874#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU)
3875#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U)
3876/*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock.
3877 * 0b10..Writable.
3878 * 0b01..Restricted mode.
3879 */
3880#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK)
3881#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U)
3882#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U)
3883/*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock.
3884 * 0b10..Writable.
3885 * 0b01..Restricted mode.
3886 */
3887#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK)
3888#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U)
3889#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U)
3890/*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock.
3891 * 0b10..Writable.
3892 * 0b01..Restricted mode.
3893 */
3894#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK)
3895/*! @} */
3896
3897/*! @name MASTER_SEC_LEVEL - master secure level register */
3898/*! @{ */
3899#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK (0x30U)
3900#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT (4U)
3901/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus.
3902 * 0b00..Non-secure and Non-priviledge user access allowed.
3903 * 0b01..Non-secure and Privilege access allowed.
3904 * 0b10..Secure and Non-priviledge user access allowed.
3905 * 0b11..Secure and Priviledge user access allowed.
3906 */
3907#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK)
3908#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK (0xC0U)
3909#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT (6U)
3910/*! CPU1S - Micro-Cortex M33 (CPU1) System bus.
3911 * 0b00..Non-secure and Non-priviledge user access allowed.
3912 * 0b01..Non-secure and Privilege access allowed.
3913 * 0b10..Secure and Non-priviledge user access allowed.
3914 * 0b11..Secure and Priviledge user access allowed.
3915 */
3916#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK)
3917#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U)
3918#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U)
3919/*! USBFSD - USB Full Speed Device.
3920 * 0b00..Non-secure and Non-priviledge user access allowed.
3921 * 0b01..Non-secure and Privilege access allowed.
3922 * 0b10..Secure and Non-priviledge user access allowed.
3923 * 0b11..Secure and Priviledge user access allowed.
3924 */
3925#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK)
3926#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U)
3927#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U)
3928/*! SDMA0 - System DMA 0.
3929 * 0b00..Non-secure and Non-priviledge user access allowed.
3930 * 0b01..Non-secure and Privilege access allowed.
3931 * 0b10..Secure and Non-priviledge user access allowed.
3932 * 0b11..Secure and Priviledge user access allowed.
3933 */
3934#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK)
3935#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U)
3936#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U)
3937/*! SDIO - SDIO.
3938 * 0b00..Non-secure and Non-priviledge user access allowed.
3939 * 0b01..Non-secure and Privilege access allowed.
3940 * 0b10..Secure and Non-priviledge user access allowed.
3941 * 0b11..Secure and Priviledge user access allowed.
3942 */
3943#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK)
3944#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U)
3945#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U)
3946/*! PQ - Power Quad.
3947 * 0b00..Non-secure and Non-priviledge user access allowed.
3948 * 0b01..Non-secure and Privilege access allowed.
3949 * 0b10..Secure and Non-priviledge user access allowed.
3950 * 0b11..Secure and Priviledge user access allowed.
3951 */
3952#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK)
3953#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U)
3954#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U)
3955/*! HASH - Hash.
3956 * 0b00..Non-secure and Non-priviledge user access allowed.
3957 * 0b01..Non-secure and Privilege access allowed.
3958 * 0b10..Secure and Non-priviledge user access allowed.
3959 * 0b11..Secure and Priviledge user access allowed.
3960 */
3961#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK)
3962#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U)
3963#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U)
3964/*! USBFSH - USB Full speed Host.
3965 * 0b00..Non-secure and Non-priviledge user access allowed.
3966 * 0b01..Non-secure and Privilege access allowed.
3967 * 0b10..Secure and Non-priviledge user access allowed.
3968 * 0b11..Secure and Priviledge user access allowed.
3969 */
3970#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK)
3971#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U)
3972#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U)
3973/*! SDMA1 - System DMA 1 security level.
3974 * 0b00..Non-secure and Non-priviledge user access allowed.
3975 * 0b01..Non-secure and Privilege access allowed.
3976 * 0b10..Secure and Non-priviledge user access allowed.
3977 * 0b11..Secure and Priviledge user access allowed.
3978 */
3979#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK)
3980#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U)
3981#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U)
3982/*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock.
3983 * 0b10..Writable.
3984 * 0b01..Restricted mode.
3985 */
3986#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK)
3987/*! @} */
3988
3989/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */
3990/*! @{ */
3991#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK (0x30U)
3992#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT (4U)
3993/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C)
3994 * 0b11..Non-secure and Non-priviledge user access allowed.
3995 * 0b10..Non-secure and Privilege access allowed.
3996 * 0b01..Secure and Non-priviledge user access allowed.
3997 * 0b00..Secure and Priviledge user access allowed.
3998 */
3999#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK)
4000#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK (0xC0U)
4001#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT (6U)
4002/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S)
4003 * 0b11..Non-secure and Non-priviledge user access allowed.
4004 * 0b10..Non-secure and Privilege access allowed.
4005 * 0b01..Secure and Non-priviledge user access allowed.
4006 * 0b00..Secure and Priviledge user access allowed.
4007 */
4008#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK)
4009#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U)
4010#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U)
4011/*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD)
4012 * 0b11..Non-secure and Non-priviledge user access allowed.
4013 * 0b10..Non-secure and Privilege access allowed.
4014 * 0b01..Secure and Non-priviledge user access allowed.
4015 * 0b00..Secure and Priviledge user access allowed.
4016 */
4017#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK)
4018#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U)
4019#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U)
4020/*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0)
4021 * 0b11..Non-secure and Non-priviledge user access allowed.
4022 * 0b10..Non-secure and Privilege access allowed.
4023 * 0b01..Secure and Non-priviledge user access allowed.
4024 * 0b00..Secure and Priviledge user access allowed.
4025 */
4026#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK)
4027#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U)
4028#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U)
4029/*! SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO)
4030 * 0b11..Non-secure and Non-priviledge user access allowed.
4031 * 0b10..Non-secure and Privilege access allowed.
4032 * 0b01..Secure and Non-priviledge user access allowed.
4033 * 0b00..Secure and Priviledge user access allowed.
4034 */
4035#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK)
4036#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U)
4037#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U)
4038/*! PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ)
4039 * 0b11..Non-secure and Non-priviledge user access allowed.
4040 * 0b10..Non-secure and Privilege access allowed.
4041 * 0b01..Secure and Non-priviledge user access allowed.
4042 * 0b00..Secure and Priviledge user access allowed.
4043 */
4044#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK)
4045#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U)
4046#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U)
4047/*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH)
4048 * 0b11..Non-secure and Non-priviledge user access allowed.
4049 * 0b10..Non-secure and Privilege access allowed.
4050 * 0b01..Secure and Non-priviledge user access allowed.
4051 * 0b00..Secure and Priviledge user access allowed.
4052 */
4053#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK)
4054#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U)
4055#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U)
4056/*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH)
4057 * 0b11..Non-secure and Non-priviledge user access allowed.
4058 * 0b10..Non-secure and Privilege access allowed.
4059 * 0b01..Secure and Non-priviledge user access allowed.
4060 * 0b00..Secure and Priviledge user access allowed.
4061 */
4062#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK)
4063#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U)
4064#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U)
4065/*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1)
4066 * 0b11..Non-secure and Non-priviledge user access allowed.
4067 * 0b10..Non-secure and Privilege access allowed.
4068 * 0b01..Secure and Non-priviledge user access allowed.
4069 * 0b00..Secure and Priviledge user access allowed.
4070 */
4071#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK)
4072#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U)
4073#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U)
4074/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock.
4075 * 0b10..Writable.
4076 * 0b01..Restricted mode.
4077 */
4078#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK)
4079/*! @} */
4080
4081/*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */
4082/*! @{ */
4083#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U)
4084#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U)
4085/*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock.
4086 * 0b10..Writable.
4087 * 0b01..Restricted mode.
4088 */
4089#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK)
4090#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU)
4091#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U)
4092/*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock.
4093 * 0b10..Writable.
4094 * 0b01..Restricted mode.
4095 */
4096#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK)
4097#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U)
4098#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U)
4099/*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock.
4100 * 0b10..Writable.
4101 * 0b01..Restricted mode.
4102 */
4103#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK)
4104#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U)
4105#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U)
4106/*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock.
4107 * 0b10..Writable.
4108 * 0b01..Restricted mode.
4109 */
4110#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK)
4111#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U)
4112#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U)
4113/*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock.
4114 * 0b10..Writable.
4115 * 0b01..Restricted mode.
4116 */
4117#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK)
4118#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U)
4119#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U)
4120/*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock.
4121 * 0b10..Writable.
4122 * 0b01..Restricted mode.
4123 */
4124#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK)
4125/*! @} */
4126
4127/*! @name CPU1_LOCK_REG - Miscalleneous control signals for in micro-Cortex M33 (CPU1) */
4128/*! @{ */
4129#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U)
4130#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U)
4131/*! LOCK_NS_VTOR - micro-Cortex M33 (CPU1) VTOR_NS register write-lock.
4132 * 0b10..Writable.
4133 * 0b01..Restricted mode.
4134 */
4135#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK)
4136#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK (0xCU)
4137#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT (2U)
4138/*! LOCK_NS_MPU - micro-Cortex M33 (CPU1) non-secure MPU register write-lock.
4139 * 0b10..Writable.
4140 * 0b01..Restricted mode.
4141 */
4142#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK)
4143#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK (0xC0000000U)
4144#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT (30U)
4145/*! CPU1_LOCK_REG_LOCK - CPU1_LOCK_REG write-lock.
4146 * 0b10..Writable.
4147 * 0b01..Restricted mode.
4148 */
4149#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK)
4150/*! @} */
4151
4152/*! @name MISC_CTRL_DP_REG - secure control duplicate register */
4153/*! @{ */
4154#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U)
4155#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U)
4156/*! WRITE_LOCK - Write lock.
4157 * 0b10..Secure control registers can be written.
4158 * 0b01..Restricted mode.
4159 */
4160#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK)
4161#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
4162#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
4163/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix.
4164 * 0b10..Disable check.
4165 * 0b01..Restricted mode.
4166 */
4167#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK)
4168#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
4169#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
4170/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix.
4171 * 0b10..Disable check.
4172 * 0b01..Restricted mode.
4173 */
4174#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK)
4175#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
4176#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
4177/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix.
4178 * 0b10..Disable check.
4179 * 0b01..Restricted mode.
4180 */
4181#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK)
4182#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
4183#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
4184/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort.
4185 * 0b10..Enable abort fort secure checker.
4186 * 0b01..Disable abort fort secure checker.
4187 */
4188#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK)
4189#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U)
4190#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U)
4191/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode.
4192 * 0b10..Simple master in strict mode.
4193 * 0b01..Simple master in tier mode.
4194 */
4195#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK)
4196#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U)
4197#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U)
4198/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode.
4199 * 0b10..Smart master in strict mode.
4200 * 0b01..Smart master in tier mode.
4201 */
4202#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK)
4203#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U)
4204#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U)
4205/*! IDAU_ALL_NS - Disable IDAU.
4206 * 0b10..IDAU is enabled.
4207 * 0b01..IDAU is disable.
4208 */
4209#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK)
4210/*! @} */
4211
4212/*! @name MISC_CTRL_REG - secure control register */
4213/*! @{ */
4214#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U)
4215#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U)
4216/*! WRITE_LOCK - Write lock.
4217 * 0b10..Secure control registers can be written.
4218 * 0b01..Restricted mode.
4219 */
4220#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK)
4221#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
4222#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
4223/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix.
4224 * 0b10..Disable check.
4225 * 0b01..Restricted mode.
4226 */
4227#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK)
4228#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
4229#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
4230/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix.
4231 * 0b10..Disable check.
4232 * 0b01..Restricted mode.
4233 */
4234#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK)
4235#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
4236#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
4237/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix.
4238 * 0b10..Disable check.
4239 * 0b01..Restricted mode.
4240 */
4241#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK)
4242#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
4243#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
4244/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort.
4245 * 0b10..Enable abort fort secure checker.
4246 * 0b01..Disable abort fort secure checker.
4247 */
4248#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK)
4249#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U)
4250#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U)
4251/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode.
4252 * 0b10..Simple master in strict mode.
4253 * 0b01..Simple master in tier mode.
4254 */
4255#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK)
4256#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U)
4257#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U)
4258/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode.
4259 * 0b10..Smart master in strict mode.
4260 * 0b01..Smart master in tier mode.
4261 */
4262#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK)
4263#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U)
4264#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U)
4265/*! IDAU_ALL_NS - Disable IDAU.
4266 * 0b10..IDAU is enabled.
4267 * 0b01..IDAU is disable.
4268 */
4269#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK)
4270/*! @} */
4271
4272
4273/*!
4274 * @}
4275 */ /* end of group AHB_SECURE_CTRL_Register_Masks */
4276
4277
4278/* AHB_SECURE_CTRL - Peripheral instance base addresses */
4279#if (__ARM_FEATURE_CMSE & 0x2)
4280 /** Peripheral AHB_SECURE_CTRL base address */
4281 #define AHB_SECURE_CTRL_BASE (0x500AC000u)
4282 /** Peripheral AHB_SECURE_CTRL base address */
4283 #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u)
4284 /** Peripheral AHB_SECURE_CTRL base pointer */
4285 #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)
4286 /** Peripheral AHB_SECURE_CTRL base pointer */
4287 #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS)
4288 /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
4289 #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE }
4290 /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
4291 #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL }
4292 /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
4293 #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS }
4294 /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
4295 #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS }
4296#else
4297 /** Peripheral AHB_SECURE_CTRL base address */
4298 #define AHB_SECURE_CTRL_BASE (0x400AC000u)
4299 /** Peripheral AHB_SECURE_CTRL base pointer */
4300 #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)
4301 /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
4302 #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE }
4303 /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
4304 #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL }
4305#endif
4306
4307/*!
4308 * @}
4309 */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */
4310
4311
4312/* ----------------------------------------------------------------------------
4313 -- ANACTRL Peripheral Access Layer
4314 ---------------------------------------------------------------------------- */
4315
4316/*!
4317 * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer
4318 * @{
4319 */
4320
4321/** ANACTRL - Register Layout Typedef */
4322typedef struct {
4323 uint8_t RESERVED_0[4];
4324 __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */
4325 uint8_t RESERVED_1[4];
4326 __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */
4327 __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */
4328 __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */
4329 uint8_t RESERVED_2[8];
4330 __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */
4331 __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */
4332 uint8_t RESERVED_3[8];
4333 __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */
4334 __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */
4335 uint8_t RESERVED_4[8];
4336 __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */
4337 __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */
4338 __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */
4339 uint8_t RESERVED_5[180];
4340 __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */
4341} ANACTRL_Type;
4342
4343/* ----------------------------------------------------------------------------
4344 -- ANACTRL Register Masks
4345 ---------------------------------------------------------------------------- */
4346
4347/*!
4348 * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks
4349 * @{
4350 */
4351
4352/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */
4353/*! @{ */
4354#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U)
4355#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U)
4356/*! FLASH_PWRDWN - Flash Power Down status.
4357 * 0b0..Flash is not in power down mode.
4358 * 0b1..Flash is in power down mode.
4359 */
4360#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK)
4361#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U)
4362#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U)
4363/*! FLASH_INIT_ERROR - Flash initialization error status.
4364 * 0b0..No error.
4365 * 0b1..At least one error occured during flash initialization..
4366 */
4367#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK)
4368/*! @} */
4369
4370/*! @name FREQ_ME_CTRL - Frequency Measure function control register */
4371/*! @{ */
4372#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU)
4373#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U)
4374/*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale
4375 */
4376#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK)
4377#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U)
4378#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U)
4379/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit
4380 * when the measurement cycle has completed and there is valid capture data in the CAPVAL field
4381 * (bits 30:0).
4382 */
4383#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK)
4384/*! @} */
4385
4386/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */
4387/*! @{ */
4388#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U)
4389#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U)
4390/*! ENA_12MHZCLK - 12 MHz clock control.
4391 * 0b0..12 MHz clock is disabled.
4392 * 0b1..12 MHz clock is enabled.
4393 */
4394#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK)
4395#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U)
4396#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U)
4397/*! ENA_48MHZCLK - 48 MHz clock control.
4398 * 0b0..Reserved.
4399 * 0b1..48 MHz clock is enabled.
4400 */
4401#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK)
4402#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U)
4403#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U)
4404/*! DAC_TRIM - Frequency trim.
4405 */
4406#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK)
4407#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U)
4408#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U)
4409/*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode,
4410 * the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF
4411 * packets.
4412 */
4413#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK)
4414#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U)
4415#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U)
4416/*! USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0.
4417 */
4418#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK)
4419#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U)
4420#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U)
4421/*! ENA_96MHZCLK - 96 MHz clock control.
4422 * 0b0..96 MHz clock is disabled.
4423 * 0b1..96 MHz clock is enabled.
4424 */
4425#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK)
4426/*! @} */
4427
4428/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */
4429/*! @{ */
4430#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U)
4431#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U)
4432/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled.
4433 * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available).
4434 * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by
4435 * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK).
4436 */
4437#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK)
4438#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U)
4439#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U)
4440/*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses
4441 * the threshold voltage of a SLVT transistor, this output signal will go high. It is also
4442 * possible to observe the clk_valid signal.
4443 */
4444#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK)
4445/*! @} */
4446
4447/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */
4448/*! @{ */
4449#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U)
4450#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U)
4451/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level.
4452 * 0b0..XO AC buffer bypass is disabled.
4453 * 0b1..XO AC buffer bypass is enabled.
4454 */
4455#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK)
4456#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U)
4457#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U)
4458/*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL.
4459 * 0b0..High speed Crystal oscillator output to USB HS PLL is disabled.
4460 * 0b1..High speed Crystal oscillator output to USB HS PLL is enabled.
4461 */
4462#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK)
4463#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U)
4464#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U)
4465/*! ENABLE_SYSTEM_CLK_OUT - Enable XO 32 MHz output to CPU system.
4466 * 0b0..High speed Crystal oscillator output to CPU system is disabled.
4467 * 0b1..High speed Crystal oscillator output to CPU system is enabled.
4468 */
4469#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK)
4470/*! @} */
4471
4472/*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */
4473/*! @{ */
4474#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U)
4475#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U)
4476/*! XO_READY - Indicates XO out frequency statibilty.
4477 * 0b0..XO output frequency is not yet stable.
4478 * 0b1..XO output frequency is stable.
4479 */
4480#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK)
4481/*! @} */
4482
4483/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */
4484/*! @{ */
4485#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U)
4486#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U)
4487/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control.
4488 * 0b0..BOD VBAT interrupt is disabled.
4489 * 0b1..BOD VBAT interrupt is enabled.
4490 */
4491#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK)
4492#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U)
4493#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U)
4494/*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit.
4495 */
4496#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK)
4497#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U)
4498#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U)
4499/*! BODCORE_INT_ENABLE - BOD CORE interrupt control.
4500 * 0b0..BOD CORE interrupt is disabled.
4501 * 0b1..BOD CORE interrupt is enabled.
4502 */
4503#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK)
4504#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U)
4505#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U)
4506/*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit.
4507 */
4508#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK)
4509#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U)
4510#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U)
4511/*! DCDC_INT_ENABLE - DCDC interrupt control.
4512 * 0b0..DCDC interrupt is disabled.
4513 * 0b1..DCDC interrupt is enabled.
4514 */
4515#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK)
4516#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U)
4517#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U)
4518/*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit.
4519 */
4520#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK)
4521/*! @} */
4522
4523/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */
4524/*! @{ */
4525#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U)
4526#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U)
4527/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable.
4528 * 0b0..No interrupt pending..
4529 * 0b1..Interrupt pending..
4530 */
4531#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK)
4532#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U)
4533#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U)
4534/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable.
4535 * 0b0..No interrupt pending..
4536 * 0b1..Interrupt pending..
4537 */
4538#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK)
4539#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U)
4540#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U)
4541/*! BODVBAT_VAL - Current value of BOD VBAT power status output.
4542 * 0b0..VBAT voltage level is below the threshold.
4543 * 0b1..VBAT voltage level is above the threshold.
4544 */
4545#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK)
4546#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U)
4547#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U)
4548/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable.
4549 * 0b0..No interrupt pending..
4550 * 0b1..Interrupt pending..
4551 */
4552#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK)
4553#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U)
4554#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U)
4555/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable.
4556 * 0b0..No interrupt pending..
4557 * 0b1..Interrupt pending..
4558 */
4559#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK)
4560#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U)
4561#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U)
4562/*! BODCORE_VAL - Current value of BOD CORE power status output.
4563 * 0b0..CORE voltage level is below the threshold.
4564 * 0b1..CORE voltage level is above the threshold.
4565 */
4566#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK)
4567#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U)
4568#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U)
4569/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable.
4570 * 0b0..No interrupt pending..
4571 * 0b1..Interrupt pending..
4572 */
4573#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK)
4574#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U)
4575#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U)
4576/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable.
4577 * 0b0..No interrupt pending..
4578 * 0b1..Interrupt pending..
4579 */
4580#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK)
4581#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U)
4582#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U)
4583/*! DCDC_VAL - Current value of DCDC power status output.
4584 * 0b0..DCDC output Voltage is below the targeted regulation level.
4585 * 0b1..DCDC output Voltage is above the targeted regulation level.
4586 */
4587#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK)
4588/*! @} */
4589
4590/*! @name RINGO0_CTRL - First Ring Oscillator module control register. */
4591/*! @{ */
4592#define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U)
4593#define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U)
4594/*! SL - Select short or long ringo (for all ringos types).
4595 * 0b0..Select short ringo (few elements).
4596 * 0b1..Select long ringo (many elements).
4597 */
4598#define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK)
4599#define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U)
4600#define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U)
4601/*! FS - Ringo frequency output divider.
4602 * 0b0..High frequency output (frequency lower than 100 MHz).
4603 * 0b1..Low frequency output (frequency lower than 10 MHz).
4604 */
4605#define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK)
4606#define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU)
4607#define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U)
4608/*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control.
4609 * 0b00..Normal mode.
4610 * 0b01..P-Monitor mode. Measure with weak P transistor.
4611 * 0b10..P-Monitor mode. Measure with weak N transistor.
4612 * 0b11..Don't use.
4613 */
4614#define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK)
4615#define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U)
4616#define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U)
4617/*! PD - Ringo module Power control.
4618 * 0b0..The Ringo module is enabled.
4619 * 0b1..The Ringo module is disabled.
4620 */
4621#define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK)
4622#define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U)
4623#define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U)
4624/*! E_ND0 - First NAND2-based ringo control.
4625 * 0b0..First NAND2-based ringo is disabled.
4626 * 0b1..First NAND2-based ringo is enabled.
4627 */
4628#define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK)
4629#define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U)
4630#define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U)
4631/*! E_ND1 - Second NAND2-based ringo control.
4632 * 0b0..Second NAND2-based ringo is disabled.
4633 * 0b1..Second NAND2-based ringo is enabled.
4634 */
4635#define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK)
4636#define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U)
4637#define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U)
4638/*! E_NR0 - First NOR2-based ringo control.
4639 * 0b0..First NOR2-based ringo is disabled.
4640 * 0b1..First NOR2-based ringo is enabled.
4641 */
4642#define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK)
4643#define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U)
4644#define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U)
4645/*! E_NR1 - Second NOR2-based ringo control.
4646 * 0b0..Second NORD2-based ringo is disabled.
4647 * 0b1..Second NORD2-based ringo is enabled.
4648 */
4649#define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK)
4650#define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U)
4651#define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U)
4652/*! E_IV0 - First Inverter-based ringo control.
4653 * 0b0..First INV-based ringo is disabled.
4654 * 0b1..First INV-based ringo is enabled.
4655 */
4656#define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK)
4657#define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U)
4658#define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U)
4659/*! E_IV1 - Second Inverter-based ringo control.
4660 * 0b0..Second INV-based ringo is disabled.
4661 * 0b1..Second INV-based ringo is enabled.
4662 */
4663#define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK)
4664#define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U)
4665#define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U)
4666/*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control.
4667 * 0b0..First PN-based ringo is disabled.
4668 * 0b1..First PN-based ringo is enabled.
4669 */
4670#define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK)
4671#define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U)
4672#define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U)
4673/*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control.
4674 * 0b0..Second PN-based ringo is disabled.
4675 * 0b1..Second PN-based ringo is enabled.
4676 */
4677#define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK)
4678#define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U)
4679#define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U)
4680/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16)
4681 */
4682#define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK)
4683#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U)
4684#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U)
4685/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider
4686 * value, cleared when the change is complete.
4687 */
4688#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK)
4689/*! @} */
4690
4691/*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */
4692/*! @{ */
4693#define ANACTRL_RINGO1_CTRL_S_MASK (0x1U)
4694#define ANACTRL_RINGO1_CTRL_S_SHIFT (0U)
4695/*! S - Select short or long ringo (for all ringos types).
4696 * 0b0..Select short ringo (few elements).
4697 * 0b1..Select long ringo (many elements).
4698 */
4699#define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK)
4700#define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U)
4701#define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U)
4702/*! FS - Ringo frequency output divider.
4703 * 0b0..High frequency output (frequency lower than 100 MHz).
4704 * 0b1..Low frequency output (frequency lower than 10 MHz).
4705 */
4706#define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK)
4707#define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U)
4708#define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U)
4709/*! PD - Ringo module Power control.
4710 * 0b0..The Ringo module is enabled.
4711 * 0b1..The Ringo module is disabled.
4712 */
4713#define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK)
4714#define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U)
4715#define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U)
4716/*! E_R24 - .
4717 * 0b0..Ringo is disabled.
4718 * 0b1..Ringo is enabled.
4719 */
4720#define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK)
4721#define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U)
4722#define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U)
4723/*! E_R35 - .
4724 * 0b0..Ringo is disabled.
4725 * 0b1..Ringo is enabled.
4726 */
4727#define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK)
4728#define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U)
4729#define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U)
4730/*! E_M2 - Metal 2 (M2) monitor control.
4731 * 0b0..Ringo is disabled.
4732 * 0b1..Ringo is enabled.
4733 */
4734#define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK)
4735#define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U)
4736#define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U)
4737/*! E_M3 - Metal 3 (M3) monitor control.
4738 * 0b0..Ringo is disabled.
4739 * 0b1..Ringo is enabled.
4740 */
4741#define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK)
4742#define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U)
4743#define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U)
4744/*! E_M4 - Metal 4 (M4) monitor control.
4745 * 0b0..Ringo is disabled.
4746 * 0b1..Ringo is enabled.
4747 */
4748#define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK)
4749#define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U)
4750#define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U)
4751/*! E_M5 - Metal 5 (M5) monitor control.
4752 * 0b0..Ringo is disabled.
4753 * 0b1..Ringo is enabled.
4754 */
4755#define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK)
4756#define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U)
4757#define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U)
4758/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16)
4759 */
4760#define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK)
4761#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U)
4762#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U)
4763/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider
4764 * value, cleared when the change is complete.
4765 */
4766#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK)
4767/*! @} */
4768
4769/*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */
4770/*! @{ */
4771#define ANACTRL_RINGO2_CTRL_S_MASK (0x1U)
4772#define ANACTRL_RINGO2_CTRL_S_SHIFT (0U)
4773/*! S - Select short or long ringo (for all ringos types).
4774 * 0b0..Select short ringo (few elements).
4775 * 0b1..Select long ringo (many elements).
4776 */
4777#define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK)
4778#define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U)
4779#define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U)
4780/*! FS - Ringo frequency output divider.
4781 * 0b0..High frequency output (frequency lower than 100 MHz).
4782 * 0b1..Low frequency output (frequency lower than 10 MHz).
4783 */
4784#define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK)
4785#define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U)
4786#define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U)
4787/*! PD - Ringo module Power control.
4788 * 0b0..The Ringo module is enabled.
4789 * 0b1..The Ringo module is disabled.
4790 */
4791#define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK)
4792#define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U)
4793#define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U)
4794/*! E_R24 - .
4795 * 0b0..Ringo is disabled.
4796 * 0b1..Ringo is enabled.
4797 */
4798#define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK)
4799#define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U)
4800#define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U)
4801/*! E_R35 - .
4802 * 0b0..Ringo is disabled.
4803 * 0b1..Ringo is enabled.
4804 */
4805#define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK)
4806#define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U)
4807#define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U)
4808/*! E_M2 - Metal 2 (M2) monitor control.
4809 * 0b0..Ringo is disabled.
4810 * 0b1..Ringo is enabled.
4811 */
4812#define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK)
4813#define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U)
4814#define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U)
4815/*! E_M3 - Metal 3 (M3) monitor control.
4816 * 0b0..Ringo is disabled.
4817 * 0b1..Ringo is enabled.
4818 */
4819#define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK)
4820#define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U)
4821#define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U)
4822/*! E_M4 - Metal 4 (M4) monitor control.
4823 * 0b0..Ringo is disabled.
4824 * 0b1..Ringo is enabled.
4825 */
4826#define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK)
4827#define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U)
4828#define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U)
4829/*! E_M5 - Metal 5 (M5) monitor control.
4830 * 0b0..Ringo is disabled.
4831 * 0b1..Ringo is enabled.
4832 */
4833#define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK)
4834#define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U)
4835#define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U)
4836/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16)
4837 */
4838#define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK)
4839#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U)
4840#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U)
4841/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider
4842 * value, cleared when the change is complete.
4843 */
4844#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK)
4845/*! @} */
4846
4847/*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */
4848/*! @{ */
4849#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U)
4850#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U)
4851/*! usb_vbusvalid_ext - Override value for Vbus if using external detectors.
4852 */
4853#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK)
4854#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U)
4855#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U)
4856/*! usb_id_ext - Override value for ID if using external detectors.
4857 */
4858#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK)
4859/*! @} */
4860
4861
4862/*!
4863 * @}
4864 */ /* end of group ANACTRL_Register_Masks */
4865
4866
4867/* ANACTRL - Peripheral instance base addresses */
4868#if (__ARM_FEATURE_CMSE & 0x2)
4869 /** Peripheral ANACTRL base address */
4870 #define ANACTRL_BASE (0x50013000u)
4871 /** Peripheral ANACTRL base address */
4872 #define ANACTRL_BASE_NS (0x40013000u)
4873 /** Peripheral ANACTRL base pointer */
4874 #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE)
4875 /** Peripheral ANACTRL base pointer */
4876 #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS)
4877 /** Array initializer of ANACTRL peripheral base addresses */
4878 #define ANACTRL_BASE_ADDRS { ANACTRL_BASE }
4879 /** Array initializer of ANACTRL peripheral base pointers */
4880 #define ANACTRL_BASE_PTRS { ANACTRL }
4881 /** Array initializer of ANACTRL peripheral base addresses */
4882 #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS }
4883 /** Array initializer of ANACTRL peripheral base pointers */
4884 #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS }
4885#else
4886 /** Peripheral ANACTRL base address */
4887 #define ANACTRL_BASE (0x40013000u)
4888 /** Peripheral ANACTRL base pointer */
4889 #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE)
4890 /** Array initializer of ANACTRL peripheral base addresses */
4891 #define ANACTRL_BASE_ADDRS { ANACTRL_BASE }
4892 /** Array initializer of ANACTRL peripheral base pointers */
4893 #define ANACTRL_BASE_PTRS { ANACTRL }
4894#endif
4895
4896/*!
4897 * @}
4898 */ /* end of group ANACTRL_Peripheral_Access_Layer */
4899
4900
4901/* ----------------------------------------------------------------------------
4902 -- CRC Peripheral Access Layer
4903 ---------------------------------------------------------------------------- */
4904
4905/*!
4906 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
4907 * @{
4908 */
4909
4910/** CRC - Register Layout Typedef */
4911typedef struct {
4912 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
4913 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
4914 union { /* offset: 0x8 */
4915 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
4916 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
4917 };
4918} CRC_Type;
4919
4920/* ----------------------------------------------------------------------------
4921 -- CRC Register Masks
4922 ---------------------------------------------------------------------------- */
4923
4924/*!
4925 * @addtogroup CRC_Register_Masks CRC Register Masks
4926 * @{
4927 */
4928
4929/*! @name MODE - CRC mode register */
4930/*! @{ */
4931#define CRC_MODE_CRC_POLY_MASK (0x3U)
4932#define CRC_MODE_CRC_POLY_SHIFT (0U)
4933/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
4934 */
4935#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
4936#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
4937#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
4938/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
4939 */
4940#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
4941#define CRC_MODE_CMPL_WR_MASK (0x8U)
4942#define CRC_MODE_CMPL_WR_SHIFT (3U)
4943/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
4944 */
4945#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
4946#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
4947#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
4948/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
4949 */
4950#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
4951#define CRC_MODE_CMPL_SUM_MASK (0x20U)
4952#define CRC_MODE_CMPL_SUM_SHIFT (5U)
4953/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
4954 */
4955#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
4956/*! @} */
4957
4958/*! @name SEED - CRC seed register */
4959/*! @{ */
4960#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
4961#define CRC_SEED_CRC_SEED_SHIFT (0U)
4962/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
4963 * selected bit order and 1's complement pre-processes. A write access to this register will
4964 * overrule the CRC calculation in progresses.
4965 */
4966#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
4967/*! @} */
4968
4969/*! @name SUM - CRC checksum register */
4970/*! @{ */
4971#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
4972#define CRC_SUM_CRC_SUM_SHIFT (0U)
4973/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
4974 */
4975#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
4976/*! @} */
4977
4978/*! @name WR_DATA - CRC data register */
4979/*! @{ */
4980#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
4981#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
4982/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
4983 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
4984 * accept back-to-back transactions.
4985 */
4986#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
4987/*! @} */
4988
4989
4990/*!
4991 * @}
4992 */ /* end of group CRC_Register_Masks */
4993
4994
4995/* CRC - Peripheral instance base addresses */
4996#if (__ARM_FEATURE_CMSE & 0x2)
4997 /** Peripheral CRC_ENGINE base address */
4998 #define CRC_ENGINE_BASE (0x50095000u)
4999 /** Peripheral CRC_ENGINE base address */
5000 #define CRC_ENGINE_BASE_NS (0x40095000u)
5001 /** Peripheral CRC_ENGINE base pointer */
5002 #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
5003 /** Peripheral CRC_ENGINE base pointer */
5004 #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS)
5005 /** Array initializer of CRC peripheral base addresses */
5006 #define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
5007 /** Array initializer of CRC peripheral base pointers */
5008 #define CRC_BASE_PTRS { CRC_ENGINE }
5009 /** Array initializer of CRC peripheral base addresses */
5010 #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS }
5011 /** Array initializer of CRC peripheral base pointers */
5012 #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS }
5013#else
5014 /** Peripheral CRC_ENGINE base address */
5015 #define CRC_ENGINE_BASE (0x40095000u)
5016 /** Peripheral CRC_ENGINE base pointer */
5017 #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
5018 /** Array initializer of CRC peripheral base addresses */
5019 #define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
5020 /** Array initializer of CRC peripheral base pointers */
5021 #define CRC_BASE_PTRS { CRC_ENGINE }
5022#endif
5023
5024/*!
5025 * @}
5026 */ /* end of group CRC_Peripheral_Access_Layer */
5027
5028
5029/* ----------------------------------------------------------------------------
5030 -- CTIMER Peripheral Access Layer
5031 ---------------------------------------------------------------------------- */
5032
5033/*!
5034 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
5035 * @{
5036 */
5037
5038/** CTIMER - Register Layout Typedef */
5039typedef struct {
5040 __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
5041 __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
5042 __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */
5043 __IO uint32_t PR; /**< Prescale Register, offset: 0xC */
5044 __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */
5045 __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */
5046 __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
5047 __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
5048 __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
5049 __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
5050 uint8_t RESERVED_0[48];
5051 __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
5052 __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */
5053 __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
5054} CTIMER_Type;
5055
5056/* ----------------------------------------------------------------------------
5057 -- CTIMER Register Masks
5058 ---------------------------------------------------------------------------- */
5059
5060/*!
5061 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
5062 * @{
5063 */
5064
5065/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
5066/*! @{ */
5067#define CTIMER_IR_MR0INT_MASK (0x1U)
5068#define CTIMER_IR_MR0INT_SHIFT (0U)
5069/*! MR0INT - Interrupt flag for match channel 0.
5070 */
5071#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
5072#define CTIMER_IR_MR1INT_MASK (0x2U)
5073#define CTIMER_IR_MR1INT_SHIFT (1U)
5074/*! MR1INT - Interrupt flag for match channel 1.
5075 */
5076#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
5077#define CTIMER_IR_MR2INT_MASK (0x4U)
5078#define CTIMER_IR_MR2INT_SHIFT (2U)
5079/*! MR2INT - Interrupt flag for match channel 2.
5080 */
5081#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
5082#define CTIMER_IR_MR3INT_MASK (0x8U)
5083#define CTIMER_IR_MR3INT_SHIFT (3U)
5084/*! MR3INT - Interrupt flag for match channel 3.
5085 */
5086#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
5087#define CTIMER_IR_CR0INT_MASK (0x10U)
5088#define CTIMER_IR_CR0INT_SHIFT (4U)
5089/*! CR0INT - Interrupt flag for capture channel 0 event.
5090 */
5091#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
5092#define CTIMER_IR_CR1INT_MASK (0x20U)
5093#define CTIMER_IR_CR1INT_SHIFT (5U)
5094/*! CR1INT - Interrupt flag for capture channel 1 event.
5095 */
5096#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
5097#define CTIMER_IR_CR2INT_MASK (0x40U)
5098#define CTIMER_IR_CR2INT_SHIFT (6U)
5099/*! CR2INT - Interrupt flag for capture channel 2 event.
5100 */
5101#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
5102#define CTIMER_IR_CR3INT_MASK (0x80U)
5103#define CTIMER_IR_CR3INT_SHIFT (7U)
5104/*! CR3INT - Interrupt flag for capture channel 3 event.
5105 */
5106#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
5107/*! @} */
5108
5109/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
5110/*! @{ */
5111#define CTIMER_TCR_CEN_MASK (0x1U)
5112#define CTIMER_TCR_CEN_SHIFT (0U)
5113/*! CEN - Counter enable.
5114 * 0b0..Disabled.The counters are disabled.
5115 * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
5116 */
5117#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
5118#define CTIMER_TCR_CRST_MASK (0x2U)
5119#define CTIMER_TCR_CRST_SHIFT (1U)
5120/*! CRST - Counter reset.
5121 * 0b0..Disabled. Do nothing.
5122 * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
5123 * the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
5124 */
5125#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
5126/*! @} */
5127
5128/*! @name TC - Timer Counter */
5129/*! @{ */
5130#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
5131#define CTIMER_TC_TCVAL_SHIFT (0U)
5132/*! TCVAL - Timer counter value.
5133 */
5134#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
5135/*! @} */
5136
5137/*! @name PR - Prescale Register */
5138/*! @{ */
5139#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
5140#define CTIMER_PR_PRVAL_SHIFT (0U)
5141/*! PRVAL - Prescale counter value.
5142 */
5143#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
5144/*! @} */
5145
5146/*! @name PC - Prescale Counter */
5147/*! @{ */
5148#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
5149#define CTIMER_PC_PCVAL_SHIFT (0U)
5150/*! PCVAL - Prescale counter value.
5151 */
5152#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
5153/*! @} */
5154
5155/*! @name MCR - Match Control Register */
5156/*! @{ */
5157#define CTIMER_MCR_MR0I_MASK (0x1U)
5158#define CTIMER_MCR_MR0I_SHIFT (0U)
5159/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
5160 */
5161#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
5162#define CTIMER_MCR_MR0R_MASK (0x2U)
5163#define CTIMER_MCR_MR0R_SHIFT (1U)
5164/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it.
5165 */
5166#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
5167#define CTIMER_MCR_MR0S_MASK (0x4U)
5168#define CTIMER_MCR_MR0S_SHIFT (2U)
5169/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
5170 */
5171#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
5172#define CTIMER_MCR_MR1I_MASK (0x8U)
5173#define CTIMER_MCR_MR1I_SHIFT (3U)
5174/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
5175 */
5176#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
5177#define CTIMER_MCR_MR1R_MASK (0x10U)
5178#define CTIMER_MCR_MR1R_SHIFT (4U)
5179/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it.
5180 */
5181#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
5182#define CTIMER_MCR_MR1S_MASK (0x20U)
5183#define CTIMER_MCR_MR1S_SHIFT (5U)
5184/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
5185 */
5186#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
5187#define CTIMER_MCR_MR2I_MASK (0x40U)
5188#define CTIMER_MCR_MR2I_SHIFT (6U)
5189/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
5190 */
5191#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
5192#define CTIMER_MCR_MR2R_MASK (0x80U)
5193#define CTIMER_MCR_MR2R_SHIFT (7U)
5194/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it.
5195 */
5196#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
5197#define CTIMER_MCR_MR2S_MASK (0x100U)
5198#define CTIMER_MCR_MR2S_SHIFT (8U)
5199/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
5200 */
5201#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
5202#define CTIMER_MCR_MR3I_MASK (0x200U)
5203#define CTIMER_MCR_MR3I_SHIFT (9U)
5204/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
5205 */
5206#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
5207#define CTIMER_MCR_MR3R_MASK (0x400U)
5208#define CTIMER_MCR_MR3R_SHIFT (10U)
5209/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it.
5210 */
5211#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
5212#define CTIMER_MCR_MR3S_MASK (0x800U)
5213#define CTIMER_MCR_MR3S_SHIFT (11U)
5214/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
5215 */
5216#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
5217#define CTIMER_MCR_MR0RL_MASK (0x1000000U)
5218#define CTIMER_MCR_MR0RL_SHIFT (24U)
5219/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
5220 * (either via a match event or a write to bit 1 of the TCR).
5221 */
5222#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
5223#define CTIMER_MCR_MR1RL_MASK (0x2000000U)
5224#define CTIMER_MCR_MR1RL_SHIFT (25U)
5225/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
5226 * (either via a match event or a write to bit 1 of the TCR).
5227 */
5228#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
5229#define CTIMER_MCR_MR2RL_MASK (0x4000000U)
5230#define CTIMER_MCR_MR2RL_SHIFT (26U)
5231/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
5232 * (either via a match event or a write to bit 1 of the TCR).
5233 */
5234#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
5235#define CTIMER_MCR_MR3RL_MASK (0x8000000U)
5236#define CTIMER_MCR_MR3RL_SHIFT (27U)
5237/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
5238 * (either via a match event or a write to bit 1 of the TCR).
5239 */
5240#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
5241/*! @} */
5242
5243/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
5244/*! @{ */
5245#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
5246#define CTIMER_MR_MATCH_SHIFT (0U)
5247/*! MATCH - Timer counter match value.
5248 */
5249#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
5250/*! @} */
5251
5252/* The count of CTIMER_MR */
5253#define CTIMER_MR_COUNT (4U)
5254
5255/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
5256/*! @{ */
5257#define CTIMER_CCR_CAP0RE_MASK (0x1U)
5258#define CTIMER_CCR_CAP0RE_SHIFT (0U)
5259/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
5260 * the contents of TC. 0 = disabled. 1 = enabled.
5261 */
5262#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
5263#define CTIMER_CCR_CAP0FE_MASK (0x2U)
5264#define CTIMER_CCR_CAP0FE_SHIFT (1U)
5265/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
5266 * the contents of TC. 0 = disabled. 1 = enabled.
5267 */
5268#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
5269#define CTIMER_CCR_CAP0I_MASK (0x4U)
5270#define CTIMER_CCR_CAP0I_SHIFT (2U)
5271/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
5272 */
5273#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
5274#define CTIMER_CCR_CAP1RE_MASK (0x8U)
5275#define CTIMER_CCR_CAP1RE_SHIFT (3U)
5276/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
5277 * the contents of TC. 0 = disabled. 1 = enabled.
5278 */
5279#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
5280#define CTIMER_CCR_CAP1FE_MASK (0x10U)
5281#define CTIMER_CCR_CAP1FE_SHIFT (4U)
5282/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
5283 * the contents of TC. 0 = disabled. 1 = enabled.
5284 */
5285#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
5286#define CTIMER_CCR_CAP1I_MASK (0x20U)
5287#define CTIMER_CCR_CAP1I_SHIFT (5U)
5288/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
5289 */
5290#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
5291#define CTIMER_CCR_CAP2RE_MASK (0x40U)
5292#define CTIMER_CCR_CAP2RE_SHIFT (6U)
5293/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
5294 * the contents of TC. 0 = disabled. 1 = enabled.
5295 */
5296#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
5297#define CTIMER_CCR_CAP2FE_MASK (0x80U)
5298#define CTIMER_CCR_CAP2FE_SHIFT (7U)
5299/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
5300 * the contents of TC. 0 = disabled. 1 = enabled.
5301 */
5302#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
5303#define CTIMER_CCR_CAP2I_MASK (0x100U)
5304#define CTIMER_CCR_CAP2I_SHIFT (8U)
5305/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
5306 */
5307#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
5308#define CTIMER_CCR_CAP3RE_MASK (0x200U)
5309#define CTIMER_CCR_CAP3RE_SHIFT (9U)
5310/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with
5311 * the contents of TC. 0 = disabled. 1 = enabled.
5312 */
5313#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
5314#define CTIMER_CCR_CAP3FE_MASK (0x400U)
5315#define CTIMER_CCR_CAP3FE_SHIFT (10U)
5316/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with
5317 * the contents of TC. 0 = disabled. 1 = enabled.
5318 */
5319#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
5320#define CTIMER_CCR_CAP3I_MASK (0x800U)
5321#define CTIMER_CCR_CAP3I_SHIFT (11U)
5322/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
5323 */
5324#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
5325/*! @} */
5326
5327/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
5328/*! @{ */
5329#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
5330#define CTIMER_CR_CAP_SHIFT (0U)
5331/*! CAP - Timer counter capture value.
5332 */
5333#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
5334/*! @} */
5335
5336/* The count of CTIMER_CR */
5337#define CTIMER_CR_COUNT (4U)
5338
5339/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
5340/*! @{ */
5341#define CTIMER_EMR_EM0_MASK (0x1U)
5342#define CTIMER_EMR_EM0_SHIFT (0U)
5343/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
5344 * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
5345 * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
5346 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
5347 */
5348#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
5349#define CTIMER_EMR_EM1_MASK (0x2U)
5350#define CTIMER_EMR_EM1_SHIFT (1U)
5351/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
5352 * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
5353 * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
5354 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
5355 */
5356#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
5357#define CTIMER_EMR_EM2_MASK (0x4U)
5358#define CTIMER_EMR_EM2_SHIFT (2U)
5359/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
5360 * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
5361 * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
5362 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
5363 */
5364#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
5365#define CTIMER_EMR_EM3_MASK (0x8U)
5366#define CTIMER_EMR_EM3_SHIFT (3U)
5367/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
5368 * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
5369 * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
5370 * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
5371 */
5372#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
5373#define CTIMER_EMR_EMC0_MASK (0x30U)
5374#define CTIMER_EMR_EMC0_SHIFT (4U)
5375/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
5376 * 0b00..Do Nothing.
5377 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
5378 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
5379 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
5380 */
5381#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
5382#define CTIMER_EMR_EMC1_MASK (0xC0U)
5383#define CTIMER_EMR_EMC1_SHIFT (6U)
5384/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
5385 * 0b00..Do Nothing.
5386 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
5387 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
5388 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
5389 */
5390#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
5391#define CTIMER_EMR_EMC2_MASK (0x300U)
5392#define CTIMER_EMR_EMC2_SHIFT (8U)
5393/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
5394 * 0b00..Do Nothing.
5395 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
5396 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
5397 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
5398 */
5399#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
5400#define CTIMER_EMR_EMC3_MASK (0xC00U)
5401#define CTIMER_EMR_EMC3_SHIFT (10U)
5402/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
5403 * 0b00..Do Nothing.
5404 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
5405 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
5406 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
5407 */
5408#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
5409/*! @} */
5410
5411/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
5412/*! @{ */
5413#define CTIMER_CTCR_CTMODE_MASK (0x3U)
5414#define CTIMER_CTCR_CTMODE_SHIFT (0U)
5415/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
5416 * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
5417 * is incremented when the Prescale Counter matches the Prescale Register.
5418 * 0b00..Timer Mode. Incremented every rising APB bus clock edge.
5419 * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
5420 * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
5421 * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
5422 */
5423#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
5424#define CTIMER_CTCR_CINSEL_MASK (0xCU)
5425#define CTIMER_CTCR_CINSEL_SHIFT (2U)
5426/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
5427 * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
5428 * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
5429 * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
5430 * same timer.
5431 * 0b00..Channel 0. CAPn.0 for CTIMERn
5432 * 0b01..Channel 1. CAPn.1 for CTIMERn
5433 * 0b10..Channel 2. CAPn.2 for CTIMERn
5434 * 0b11..Channel 3. CAPn.3 for CTIMERn
5435 */
5436#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
5437#define CTIMER_CTCR_ENCC_MASK (0x10U)
5438#define CTIMER_CTCR_ENCC_SHIFT (4U)
5439/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
5440 * capture-edge event specified in bits 7:5 occurs.
5441 */
5442#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
5443#define CTIMER_CTCR_SELCC_MASK (0xE0U)
5444#define CTIMER_CTCR_SELCC_SHIFT (5U)
5445/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
5446 * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
5447 * 0x3 and 0x6 to 0x7 are reserved.
5448 * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
5449 * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
5450 * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
5451 * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
5452 * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
5453 * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
5454 */
5455#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
5456/*! @} */
5457
5458/*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */
5459/*! @{ */
5460#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
5461#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
5462/*! PWMEN0 - PWM mode enable for channel0.
5463 * 0b0..Match. CTIMERn_MAT0 is controlled by EM0.
5464 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
5465 */
5466#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
5467#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
5468#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
5469/*! PWMEN1 - PWM mode enable for channel1.
5470 * 0b0..Match. CTIMERn_MAT01 is controlled by EM1.
5471 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
5472 */
5473#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
5474#define CTIMER_PWMC_PWMEN2_MASK (0x4U)
5475#define CTIMER_PWMC_PWMEN2_SHIFT (2U)
5476/*! PWMEN2 - PWM mode enable for channel2.
5477 * 0b0..Match. CTIMERn_MAT2 is controlled by EM2.
5478 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
5479 */
5480#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
5481#define CTIMER_PWMC_PWMEN3_MASK (0x8U)
5482#define CTIMER_PWMC_PWMEN3_SHIFT (3U)
5483/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
5484 * 0b0..Match. CTIMERn_MAT3 is controlled by EM3.
5485 * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
5486 */
5487#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
5488/*! @} */
5489
5490/*! @name MSR - Match Shadow Register */
5491/*! @{ */
5492#define CTIMER_MSR_SHADOW_MASK (0xFFFFFFFFU)
5493#define CTIMER_MSR_SHADOW_SHIFT (0U)
5494/*! SHADOW - Timer counter match shadow value.
5495 */
5496#define CTIMER_MSR_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOW_SHIFT)) & CTIMER_MSR_SHADOW_MASK)
5497/*! @} */
5498
5499/* The count of CTIMER_MSR */
5500#define CTIMER_MSR_COUNT (4U)
5501
5502
5503/*!
5504 * @}
5505 */ /* end of group CTIMER_Register_Masks */
5506
5507
5508/* CTIMER - Peripheral instance base addresses */
5509#if (__ARM_FEATURE_CMSE & 0x2)
5510 /** Peripheral CTIMER0 base address */
5511 #define CTIMER0_BASE (0x50008000u)
5512 /** Peripheral CTIMER0 base address */
5513 #define CTIMER0_BASE_NS (0x40008000u)
5514 /** Peripheral CTIMER0 base pointer */
5515 #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
5516 /** Peripheral CTIMER0 base pointer */
5517 #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS)
5518 /** Peripheral CTIMER1 base address */
5519 #define CTIMER1_BASE (0x50009000u)
5520 /** Peripheral CTIMER1 base address */
5521 #define CTIMER1_BASE_NS (0x40009000u)
5522 /** Peripheral CTIMER1 base pointer */
5523 #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
5524 /** Peripheral CTIMER1 base pointer */
5525 #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS)
5526 /** Peripheral CTIMER2 base address */
5527 #define CTIMER2_BASE (0x50028000u)
5528 /** Peripheral CTIMER2 base address */
5529 #define CTIMER2_BASE_NS (0x40028000u)
5530 /** Peripheral CTIMER2 base pointer */
5531 #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
5532 /** Peripheral CTIMER2 base pointer */
5533 #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS)
5534 /** Peripheral CTIMER3 base address */
5535 #define CTIMER3_BASE (0x50029000u)
5536 /** Peripheral CTIMER3 base address */
5537 #define CTIMER3_BASE_NS (0x40029000u)
5538 /** Peripheral CTIMER3 base pointer */
5539 #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
5540 /** Peripheral CTIMER3 base pointer */
5541 #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS)
5542 /** Peripheral CTIMER4 base address */
5543 #define CTIMER4_BASE (0x5002A000u)
5544 /** Peripheral CTIMER4 base address */
5545 #define CTIMER4_BASE_NS (0x4002A000u)
5546 /** Peripheral CTIMER4 base pointer */
5547 #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
5548 /** Peripheral CTIMER4 base pointer */
5549 #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS)
5550 /** Array initializer of CTIMER peripheral base addresses */
5551 #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
5552 /** Array initializer of CTIMER peripheral base pointers */
5553 #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
5554 /** Array initializer of CTIMER peripheral base addresses */
5555 #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS }
5556 /** Array initializer of CTIMER peripheral base pointers */
5557 #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS }
5558#else
5559 /** Peripheral CTIMER0 base address */
5560 #define CTIMER0_BASE (0x40008000u)
5561 /** Peripheral CTIMER0 base pointer */
5562 #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
5563 /** Peripheral CTIMER1 base address */
5564 #define CTIMER1_BASE (0x40009000u)
5565 /** Peripheral CTIMER1 base pointer */
5566 #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
5567 /** Peripheral CTIMER2 base address */
5568 #define CTIMER2_BASE (0x40028000u)
5569 /** Peripheral CTIMER2 base pointer */
5570 #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
5571 /** Peripheral CTIMER3 base address */
5572 #define CTIMER3_BASE (0x40029000u)
5573 /** Peripheral CTIMER3 base pointer */
5574 #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
5575 /** Peripheral CTIMER4 base address */
5576 #define CTIMER4_BASE (0x4002A000u)
5577 /** Peripheral CTIMER4 base pointer */
5578 #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
5579 /** Array initializer of CTIMER peripheral base addresses */
5580 #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
5581 /** Array initializer of CTIMER peripheral base pointers */
5582 #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
5583#endif
5584/** Interrupt vectors for the CTIMER peripheral type */
5585#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
5586
5587/*!
5588 * @}
5589 */ /* end of group CTIMER_Peripheral_Access_Layer */
5590
5591
5592/* ----------------------------------------------------------------------------
5593 -- DBGMAILBOX Peripheral Access Layer
5594 ---------------------------------------------------------------------------- */
5595
5596/*!
5597 * @addtogroup DBGMAILBOX_Peripheral_Access_Layer DBGMAILBOX Peripheral Access Layer
5598 * @{
5599 */
5600
5601/** DBGMAILBOX - Register Layout Typedef */
5602typedef struct {
5603 __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */
5604 __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */
5605 __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */
5606 uint8_t RESERVED_0[240];
5607 __I uint32_t ID; /**< Identification register, offset: 0xFC */
5608} DBGMAILBOX_Type;
5609
5610/* ----------------------------------------------------------------------------
5611 -- DBGMAILBOX Register Masks
5612 ---------------------------------------------------------------------------- */
5613
5614/*!
5615 * @addtogroup DBGMAILBOX_Register_Masks DBGMAILBOX Register Masks
5616 * @{
5617 */
5618
5619/*! @name CSW - CRC mode register */
5620/*! @{ */
5621#define DBGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U)
5622#define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U)
5623/*! RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation
5624 */
5625#define DBGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK)
5626#define DBGMAILBOX_CSW_REQ_PENDING_MASK (0x2U)
5627#define DBGMAILBOX_CSW_REQ_PENDING_SHIFT (1U)
5628/*! REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST)
5629 */
5630#define DBGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK)
5631#define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U)
5632#define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U)
5633/*! DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM)
5634 */
5635#define DBGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
5636#define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U)
5637#define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U)
5638/*! AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM)
5639 */
5640#define DBGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
5641#define DBGMAILBOX_CSW_SOFT_RESET_MASK (0x10U)
5642#define DBGMAILBOX_CSW_SOFT_RESET_SHIFT (4U)
5643/*! SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to
5644 * this bit will cause a soft reset for DM.
5645 */
5646#define DBGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK)
5647#define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U)
5648#define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U)
5649/*! CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is
5650 * not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event)
5651 */
5652#define DBGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK)
5653/*! @} */
5654
5655/*! @name REQUEST - CRC seed register */
5656/*! @{ */
5657#define DBGMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU)
5658#define DBGMAILBOX_REQUEST_REQ_SHIFT (0U)
5659/*! REQ - Request Value
5660 */
5661#define DBGMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQ_SHIFT)) & DBGMAILBOX_REQUEST_REQ_MASK)
5662/*! @} */
5663
5664/*! @name RETURN - Return value from ROM. */
5665/*! @{ */
5666#define DBGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU)
5667#define DBGMAILBOX_RETURN_RET_SHIFT (0U)
5668/*! RET - The Return value from ROM.
5669 */
5670#define DBGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK)
5671/*! @} */
5672
5673/*! @name ID - Identification register */
5674/*! @{ */
5675#define DBGMAILBOX_ID_ID_MASK (0xFFFFFFFFU)
5676#define DBGMAILBOX_ID_ID_SHIFT (0U)
5677/*! ID - Identification value.
5678 */
5679#define DBGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK)
5680/*! @} */
5681
5682
5683/*!
5684 * @}
5685 */ /* end of group DBGMAILBOX_Register_Masks */
5686
5687
5688/* DBGMAILBOX - Peripheral instance base addresses */
5689#if (__ARM_FEATURE_CMSE & 0x2)
5690 /** Peripheral DBGMAILBOX base address */
5691 #define DBGMAILBOX_BASE (0x5009C000u)
5692 /** Peripheral DBGMAILBOX base address */
5693 #define DBGMAILBOX_BASE_NS (0x4009C000u)
5694 /** Peripheral DBGMAILBOX base pointer */
5695 #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE)
5696 /** Peripheral DBGMAILBOX base pointer */
5697 #define DBGMAILBOX_NS ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS)
5698 /** Array initializer of DBGMAILBOX peripheral base addresses */
5699 #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE }
5700 /** Array initializer of DBGMAILBOX peripheral base pointers */
5701 #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX }
5702 /** Array initializer of DBGMAILBOX peripheral base addresses */
5703 #define DBGMAILBOX_BASE_ADDRS_NS { DBGMAILBOX_BASE_NS }
5704 /** Array initializer of DBGMAILBOX peripheral base pointers */
5705 #define DBGMAILBOX_BASE_PTRS_NS { DBGMAILBOX_NS }
5706#else
5707 /** Peripheral DBGMAILBOX base address */
5708 #define DBGMAILBOX_BASE (0x4009C000u)
5709 /** Peripheral DBGMAILBOX base pointer */
5710 #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE)
5711 /** Array initializer of DBGMAILBOX peripheral base addresses */
5712 #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE }
5713 /** Array initializer of DBGMAILBOX peripheral base pointers */
5714 #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX }
5715#endif
5716
5717/*!
5718 * @}
5719 */ /* end of group DBGMAILBOX_Peripheral_Access_Layer */
5720
5721
5722/* ----------------------------------------------------------------------------
5723 -- DMA Peripheral Access Layer
5724 ---------------------------------------------------------------------------- */
5725
5726/*!
5727 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
5728 * @{
5729 */
5730
5731/** DMA - Register Layout Typedef */
5732typedef struct {
5733 __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
5734 __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
5735 __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
5736 uint8_t RESERVED_0[20];
5737 struct { /* offset: 0x20, array step: 0x5C */
5738 __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
5739 uint8_t RESERVED_0[4];
5740 __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
5741 uint8_t RESERVED_1[4];
5742 __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
5743 uint8_t RESERVED_2[4];
5744 __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
5745 uint8_t RESERVED_3[4];
5746 __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
5747 uint8_t RESERVED_4[4];
5748 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
5749 uint8_t RESERVED_5[4];
5750 __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
5751 uint8_t RESERVED_6[4];
5752 __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
5753 uint8_t RESERVED_7[4];
5754 __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
5755 uint8_t RESERVED_8[4];
5756 __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
5757 uint8_t RESERVED_9[4];
5758 __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
5759 uint8_t RESERVED_10[4];
5760 __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
5761 } COMMON[1];
5762 uint8_t RESERVED_1[900];
5763 struct { /* offset: 0x400, array step: 0x10 */
5764 __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
5765 __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
5766 __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
5767 uint8_t RESERVED_0[4];
5768 } CHANNEL[23];
5769} DMA_Type;
5770
5771/* ----------------------------------------------------------------------------
5772 -- DMA Register Masks
5773 ---------------------------------------------------------------------------- */
5774
5775/*!
5776 * @addtogroup DMA_Register_Masks DMA Register Masks
5777 * @{
5778 */
5779
5780/*! @name CTRL - DMA control. */
5781/*! @{ */
5782#define DMA_CTRL_ENABLE_MASK (0x1U)
5783#define DMA_CTRL_ENABLE_SHIFT (0U)
5784/*! ENABLE - DMA controller master enable.
5785 * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
5786 * disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
5787 * 0b1..Enabled. The DMA controller is enabled.
5788 */
5789#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
5790/*! @} */
5791
5792/*! @name INTSTAT - Interrupt status. */
5793/*! @{ */
5794#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
5795#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
5796/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
5797 * 0b0..Not pending. No enabled interrupts are pending.
5798 * 0b1..Pending. At least one enabled interrupt is pending.
5799 */
5800#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
5801#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
5802#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
5803/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
5804 * 0b0..Not pending. No error interrupts are pending.
5805 * 0b1..Pending. At least one error interrupt is pending.
5806 */
5807#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
5808/*! @} */
5809
5810/*! @name SRAMBASE - SRAM address of the channel configuration table. */
5811/*! @{ */
5812#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
5813#define DMA_SRAMBASE_OFFSET_SHIFT (9U)
5814/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
5815 * table must begin on a 512 byte boundary.
5816 */
5817#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
5818/*! @} */
5819
5820/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
5821/*! @{ */
5822#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)
5823#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
5824/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
5825 * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
5826 */
5827#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
5828/*! @} */
5829
5830/* The count of DMA_COMMON_ENABLESET */
5831#define DMA_COMMON_ENABLESET_COUNT (1U)
5832
5833/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
5834/*! @{ */
5835#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)
5836#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
5837/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
5838 * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
5839 * are reserved.
5840 */
5841#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
5842/*! @} */
5843
5844/* The count of DMA_COMMON_ENABLECLR */
5845#define DMA_COMMON_ENABLECLR_COUNT (1U)
5846
5847/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
5848/*! @{ */
5849#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)
5850#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
5851/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
5852 * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
5853 */
5854#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
5855/*! @} */
5856
5857/* The count of DMA_COMMON_ACTIVE */
5858#define DMA_COMMON_ACTIVE_COUNT (1U)
5859
5860/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
5861/*! @{ */
5862#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)
5863#define DMA_COMMON_BUSY_BSY_SHIFT (0U)
5864/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
5865 * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
5866 */
5867#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
5868/*! @} */
5869
5870/* The count of DMA_COMMON_BUSY */
5871#define DMA_COMMON_BUSY_COUNT (1U)
5872
5873/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
5874/*! @{ */
5875#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)
5876#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
5877/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
5878 * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
5879 * not active. 1 = error interrupt is active.
5880 */
5881#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
5882/*! @} */
5883
5884/* The count of DMA_COMMON_ERRINT */
5885#define DMA_COMMON_ERRINT_COUNT (1U)
5886
5887/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
5888/*! @{ */
5889#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)
5890#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
5891/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
5892 * number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
5893 * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
5894 */
5895#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
5896/*! @} */
5897
5898/* The count of DMA_COMMON_INTENSET */
5899#define DMA_COMMON_INTENSET_COUNT (1U)
5900
5901/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
5902/*! @{ */
5903#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)
5904#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
5905/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
5906 * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
5907 * reserved.
5908 */
5909#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
5910/*! @} */
5911
5912/* The count of DMA_COMMON_INTENCLR */
5913#define DMA_COMMON_INTENCLR_COUNT (1U)
5914
5915/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
5916/*! @{ */
5917#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)
5918#define DMA_COMMON_INTA_IA_SHIFT (0U)
5919/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
5920 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
5921 * interrupt A is not active. 1 = the DMA channel interrupt A is active.
5922 */
5923#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
5924/*! @} */
5925
5926/* The count of DMA_COMMON_INTA */
5927#define DMA_COMMON_INTA_COUNT (1U)
5928
5929/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
5930/*! @{ */
5931#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)
5932#define DMA_COMMON_INTB_IB_SHIFT (0U)
5933/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
5934 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
5935 * interrupt B is not active. 1 = the DMA channel interrupt B is active.
5936 */
5937#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
5938/*! @} */
5939
5940/* The count of DMA_COMMON_INTB */
5941#define DMA_COMMON_INTB_COUNT (1U)
5942
5943/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
5944/*! @{ */
5945#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)
5946#define DMA_COMMON_SETVALID_SV_SHIFT (0U)
5947/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
5948 * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
5949 * VALIDPENDING control bit for DMA channel n
5950 */
5951#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
5952/*! @} */
5953
5954/* The count of DMA_COMMON_SETVALID */
5955#define DMA_COMMON_SETVALID_COUNT (1U)
5956
5957/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
5958/*! @{ */
5959#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)
5960#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
5961/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
5962 * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
5963 * sets the TRIG bit for DMA channel n.
5964 */
5965#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
5966/*! @} */
5967
5968/* The count of DMA_COMMON_SETTRIG */
5969#define DMA_COMMON_SETTRIG_COUNT (1U)
5970
5971/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
5972/*! @{ */
5973#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)
5974#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
5975/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
5976 * 1 = aborts DMA operations on channel n.
5977 */
5978#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
5979/*! @} */
5980
5981/* The count of DMA_COMMON_ABORT */
5982#define DMA_COMMON_ABORT_COUNT (1U)
5983
5984/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
5985/*! @{ */
5986#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
5987#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
5988/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
5989 * move, any peripheral DMA request associated with that channel can be disabled to prevent any
5990 * interaction between the peripheral and the DMA controller.
5991 * 0b0..Disabled. Peripheral DMA requests are disabled.
5992 * 0b1..Enabled. Peripheral DMA requests are enabled.
5993 */
5994#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
5995#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
5996#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
5997/*! HWTRIGEN - Hardware Triggering Enable for this channel.
5998 * 0b0..Disabled. Hardware triggering is not used.
5999 * 0b1..Enabled. Use hardware triggering.
6000 */
6001#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
6002#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
6003#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
6004/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
6005 * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
6006 * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
6007 */
6008#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
6009#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
6010#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
6011/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
6012 * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
6013 * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
6014 * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
6015 * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
6016 * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
6017 * current BURSTPOWER length are completed.
6018 */
6019#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
6020#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
6021#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
6022/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6023 * 0b0..Single transfer. Hardware trigger causes a single transfer.
6024 * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
6025 * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a
6026 * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
6027 * complete.
6028 */
6029#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
6030#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
6031#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
6032/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
6033 * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
6034 * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
6035 * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that
6036 * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:
6037 * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =
6038 * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The
6039 * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
6040 * multiple of the burst size.
6041 */
6042#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
6043#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
6044#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
6045/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
6046 * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this
6047 * could be used to read several sequential registers from a peripheral for each DMA burst,
6048 * reading the same registers again for each burst.
6049 * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
6050 * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
6051 */
6052#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
6053#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
6054#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
6055/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
6056 * 'wrapped', meaning that the destination address range for each burst will be the same. As an
6057 * example, this could be used to write several sequential registers to a peripheral for each DMA
6058 * burst, writing the same registers again for each burst.
6059 * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
6060 * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
6061 */
6062#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
6063#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
6064#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
6065/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority
6066 * levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
6067 */
6068#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
6069/*! @} */
6070
6071/* The count of DMA_CHANNEL_CFG */
6072#define DMA_CHANNEL_CFG_COUNT (23U)
6073
6074/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
6075/*! @{ */
6076#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
6077#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
6078/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the
6079 * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
6080 * 0b0..No effect. No effect on DMA operation.
6081 * 0b1..Valid pending.
6082 */
6083#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
6084#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
6085#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
6086/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is
6087 * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
6088 * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
6089 * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
6090 */
6091#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
6092/*! @} */
6093
6094/* The count of DMA_CHANNEL_CTLSTAT */
6095#define DMA_CHANNEL_CTLSTAT_COUNT (23U)
6096
6097/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
6098/*! @{ */
6099#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
6100#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
6101/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor
6102 * is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
6103 * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
6104 * 0b1..Valid. The current channel descriptor is considered valid.
6105 */
6106#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
6107#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
6108#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
6109/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current
6110 * descriptor is exhausted. Reloading allows ping-pong and linked transfers.
6111 * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
6112 * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.
6113 */
6114#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
6115#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
6116#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
6117/*! SWTRIG - Software Trigger.
6118 * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by
6119 * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
6120 * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not
6121 * be used with level triggering when TRIGBURST = 0.
6122 */
6123#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
6124#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)
6125#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)
6126/*! CLRTRIG - Clear Trigger.
6127 * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
6128 * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted
6129 */
6130#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
6131#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)
6132#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)
6133/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between
6134 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
6135 * convention, interrupt A may be used when only one interrupt flag is needed.
6136 * 0b0..No effect.
6137 * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
6138 */
6139#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
6140#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)
6141#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)
6142/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between
6143 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
6144 * convention, interrupt A may be used when only one interrupt flag is needed.
6145 * 0b0..No effect.
6146 * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
6147 */
6148#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
6149#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)
6150#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)
6151/*! WIDTH - Transfer width used for this DMA channel.
6152 * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
6153 * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
6154 * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
6155 * 0b11..Reserved. Reserved setting, do not use.
6156 */
6157#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
6158#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)
6159#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)
6160/*! SRCINC - Determines whether the source address is incremented for each DMA transfer.
6161 * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
6162 * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is
6163 * the usual case when the source is memory.
6164 * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
6165 * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
6166 */
6167#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
6168#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)
6169#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)
6170/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer.
6171 * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when
6172 * the destination is a peripheral device.
6173 * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer.
6174 * This is the usual case when the destination is memory.
6175 * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
6176 * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
6177 */
6178#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
6179#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)
6180#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)
6181/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes
6182 * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller
6183 * uses this bit field during transfer to count down. Hence, it cannot be used by software to read
6184 * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1
6185 * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of
6186 * 1,024 transfers will be performed.
6187 */
6188#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
6189/*! @} */
6190
6191/* The count of DMA_CHANNEL_XFERCFG */
6192#define DMA_CHANNEL_XFERCFG_COUNT (23U)
6193
6194
6195/*!
6196 * @}
6197 */ /* end of group DMA_Register_Masks */
6198
6199
6200/* DMA - Peripheral instance base addresses */
6201#if (__ARM_FEATURE_CMSE & 0x2)
6202 /** Peripheral DMA0 base address */
6203 #define DMA0_BASE (0x50082000u)
6204 /** Peripheral DMA0 base address */
6205 #define DMA0_BASE_NS (0x40082000u)
6206 /** Peripheral DMA0 base pointer */
6207 #define DMA0 ((DMA_Type *)DMA0_BASE)
6208 /** Peripheral DMA0 base pointer */
6209 #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS)
6210 /** Peripheral DMA1 base address */
6211 #define DMA1_BASE (0x500A7000u)
6212 /** Peripheral DMA1 base address */
6213 #define DMA1_BASE_NS (0x400A7000u)
6214 /** Peripheral DMA1 base pointer */
6215 #define DMA1 ((DMA_Type *)DMA1_BASE)
6216 /** Peripheral DMA1 base pointer */
6217 #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS)
6218 /** Array initializer of DMA peripheral base addresses */
6219 #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE }
6220 /** Array initializer of DMA peripheral base pointers */
6221 #define DMA_BASE_PTRS { DMA0, DMA1 }
6222 /** Array initializer of DMA peripheral base addresses */
6223 #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS }
6224 /** Array initializer of DMA peripheral base pointers */
6225 #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS }
6226#else
6227 /** Peripheral DMA0 base address */
6228 #define DMA0_BASE (0x40082000u)
6229 /** Peripheral DMA0 base pointer */
6230 #define DMA0 ((DMA_Type *)DMA0_BASE)
6231 /** Peripheral DMA1 base address */
6232 #define DMA1_BASE (0x400A7000u)
6233 /** Peripheral DMA1 base pointer */
6234 #define DMA1 ((DMA_Type *)DMA1_BASE)
6235 /** Array initializer of DMA peripheral base addresses */
6236 #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE }
6237 /** Array initializer of DMA peripheral base pointers */
6238 #define DMA_BASE_PTRS { DMA0, DMA1 }
6239#endif
6240/** Interrupt vectors for the DMA peripheral type */
6241#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn }
6242
6243/*!
6244 * @}
6245 */ /* end of group DMA_Peripheral_Access_Layer */
6246
6247
6248/* ----------------------------------------------------------------------------
6249 -- FLASH Peripheral Access Layer
6250 ---------------------------------------------------------------------------- */
6251
6252/*!
6253 * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer
6254 * @{
6255 */
6256
6257/** FLASH - Register Layout Typedef */
6258typedef struct {
6259 __O uint32_t CMD; /**< command register, offset: 0x0 */
6260 __O uint32_t EVENT; /**< event register, offset: 0x4 */
6261 uint8_t RESERVED_0[8];
6262 __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */
6263 __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */
6264 uint8_t RESERVED_1[104];
6265 __IO uint32_t DATAW[4]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */
6266 uint8_t RESERVED_2[3912];
6267 __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */
6268 __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */
6269 __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */
6270 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */
6271 __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */
6272 __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */
6273 uint8_t RESERVED_3[12];
6274 __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */
6275} FLASH_Type;
6276
6277/* ----------------------------------------------------------------------------
6278 -- FLASH Register Masks
6279 ---------------------------------------------------------------------------- */
6280
6281/*!
6282 * @addtogroup FLASH_Register_Masks FLASH Register Masks
6283 * @{
6284 */
6285
6286/*! @name CMD - command register */
6287/*! @{ */
6288#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU)
6289#define FLASH_CMD_CMD_SHIFT (0U)
6290/*! CMD - command register.
6291 */
6292#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK)
6293/*! @} */
6294
6295/*! @name EVENT - event register */
6296/*! @{ */
6297#define FLASH_EVENT_RST_MASK (0x1U)
6298#define FLASH_EVENT_RST_SHIFT (0U)
6299/*! RST - When bit is set, the controller and flash are reset.
6300 */
6301#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK)
6302#define FLASH_EVENT_WAKEUP_MASK (0x2U)
6303#define FLASH_EVENT_WAKEUP_SHIFT (1U)
6304/*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active.
6305 */
6306#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK)
6307#define FLASH_EVENT_ABORT_MASK (0x4U)
6308#define FLASH_EVENT_ABORT_SHIFT (2U)
6309/*! ABORT - When bit is set, a running program/erase command is aborted.
6310 */
6311#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK)
6312/*! @} */
6313
6314/*! @name STARTA - start (or only) address for next flash command */
6315/*! @{ */
6316#define FLASH_STARTA_STARTA_MASK (0x3FFFFU)
6317#define FLASH_STARTA_STARTA_SHIFT (0U)
6318/*! STARTA - Address / Start address for commands that take an address (range) as a parameter.
6319 */
6320#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK)
6321/*! @} */
6322
6323/*! @name STOPA - end address for next flash command, if command operates on address ranges */
6324/*! @{ */
6325#define FLASH_STOPA_STOPA_MASK (0x3FFFFU)
6326#define FLASH_STOPA_STOPA_SHIFT (0U)
6327/*! STOPA - Stop address for commands that take an address range as a parameter (the word specified
6328 * by STOPA is included in the address range).
6329 */
6330#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK)
6331/*! @} */
6332
6333/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */
6334/*! @{ */
6335#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU)
6336#define FLASH_DATAW_DATAW_SHIFT (0U)
6337#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK)
6338/*! @} */
6339
6340/* The count of FLASH_DATAW */
6341#define FLASH_DATAW_COUNT (4U)
6342
6343/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */
6344/*! @{ */
6345#define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U)
6346#define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U)
6347/*! FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.
6348 */
6349#define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK)
6350#define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U)
6351#define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U)
6352/*! ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.
6353 */
6354#define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK)
6355#define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U)
6356#define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U)
6357/*! DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.
6358 */
6359#define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK)
6360#define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U)
6361#define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U)
6362/*! ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.
6363 */
6364#define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK)
6365/*! @} */
6366
6367/*! @name INT_SET_ENABLE - Set interrupt enable bits */
6368/*! @{ */
6369#define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U)
6370#define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U)
6371/*! FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.
6372 */
6373#define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK)
6374#define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U)
6375#define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U)
6376/*! ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.
6377 */
6378#define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK)
6379#define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U)
6380#define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U)
6381/*! DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.
6382 */
6383#define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK)
6384#define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U)
6385#define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U)
6386/*! ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.
6387 */
6388#define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK)
6389/*! @} */
6390
6391/*! @name INT_STATUS - Interrupt status bits */
6392/*! @{ */
6393#define FLASH_INT_STATUS_FAIL_MASK (0x1U)
6394#define FLASH_INT_STATUS_FAIL_SHIFT (0U)
6395/*! FAIL - This status bit is set if execution of a (legal) command failed.
6396 */
6397#define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK)
6398#define FLASH_INT_STATUS_ERR_MASK (0x2U)
6399#define FLASH_INT_STATUS_ERR_SHIFT (1U)
6400/*! ERR - This status bit is set if execution of an illegal command is detected.
6401 */
6402#define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK)
6403#define FLASH_INT_STATUS_DONE_MASK (0x4U)
6404#define FLASH_INT_STATUS_DONE_SHIFT (2U)
6405/*! DONE - This status bit is set at the end of command execution.
6406 */
6407#define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK)
6408#define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U)
6409#define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U)
6410/*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested
6411 * read, or a speculative read, or reads performed by a controller command), a correctable or
6412 * uncorrectable error is detected by ECC decoding logic.
6413 */
6414#define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK)
6415/*! @} */
6416
6417/*! @name INT_ENABLE - Interrupt enable bits */
6418/*! @{ */
6419#define FLASH_INT_ENABLE_FAIL_MASK (0x1U)
6420#define FLASH_INT_ENABLE_FAIL_SHIFT (0U)
6421/*! FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high.
6422 */
6423#define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK)
6424#define FLASH_INT_ENABLE_ERR_MASK (0x2U)
6425#define FLASH_INT_ENABLE_ERR_SHIFT (1U)
6426/*! ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high.
6427 */
6428#define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK)
6429#define FLASH_INT_ENABLE_DONE_MASK (0x4U)
6430#define FLASH_INT_ENABLE_DONE_SHIFT (2U)
6431/*! DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high.
6432 */
6433#define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK)
6434#define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U)
6435#define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U)
6436/*! ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high.
6437 */
6438#define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK)
6439/*! @} */
6440
6441/*! @name INT_CLR_STATUS - Clear interrupt status bits */
6442/*! @{ */
6443#define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U)
6444#define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U)
6445/*! FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.
6446 */
6447#define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK)
6448#define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U)
6449#define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U)
6450/*! ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.
6451 */
6452#define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK)
6453#define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U)
6454#define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U)
6455/*! DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.
6456 */
6457#define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK)
6458#define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U)
6459#define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U)
6460/*! ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.
6461 */
6462#define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK)
6463/*! @} */
6464
6465/*! @name INT_SET_STATUS - Set interrupt status bits */
6466/*! @{ */
6467#define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U)
6468#define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U)
6469/*! FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.
6470 */
6471#define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK)
6472#define FLASH_INT_SET_STATUS_ERR_MASK (0x2U)
6473#define FLASH_INT_SET_STATUS_ERR_SHIFT (1U)
6474/*! ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.
6475 */
6476#define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK)
6477#define FLASH_INT_SET_STATUS_DONE_MASK (0x4U)
6478#define FLASH_INT_SET_STATUS_DONE_SHIFT (2U)
6479/*! DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.
6480 */
6481#define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK)
6482#define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U)
6483#define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U)
6484/*! ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.
6485 */
6486#define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK)
6487/*! @} */
6488
6489/*! @name MODULE_ID - Controller+Memory module identification */
6490/*! @{ */
6491#define FLASH_MODULE_ID_APERTURE_MASK (0xFFU)
6492#define FLASH_MODULE_ID_APERTURE_SHIFT (0U)
6493/*! APERTURE - Aperture i.
6494 */
6495#define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK)
6496#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U)
6497#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U)
6498/*! MINOR_REV - Minor revision i.
6499 */
6500#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK)
6501#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U)
6502#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U)
6503/*! MAJOR_REV - Major revision i.
6504 */
6505#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK)
6506#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U)
6507#define FLASH_MODULE_ID_ID_SHIFT (16U)
6508/*! ID - Identifier.
6509 */
6510#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK)
6511/*! @} */
6512
6513
6514/*!
6515 * @}
6516 */ /* end of group FLASH_Register_Masks */
6517
6518
6519/* FLASH - Peripheral instance base addresses */
6520#if (__ARM_FEATURE_CMSE & 0x2)
6521 /** Peripheral FLASH base address */
6522 #define FLASH_BASE (0x50034000u)
6523 /** Peripheral FLASH base address */
6524 #define FLASH_BASE_NS (0x40034000u)
6525 /** Peripheral FLASH base pointer */
6526 #define FLASH ((FLASH_Type *)FLASH_BASE)
6527 /** Peripheral FLASH base pointer */
6528 #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS)
6529 /** Array initializer of FLASH peripheral base addresses */
6530 #define FLASH_BASE_ADDRS { FLASH_BASE }
6531 /** Array initializer of FLASH peripheral base pointers */
6532 #define FLASH_BASE_PTRS { FLASH }
6533 /** Array initializer of FLASH peripheral base addresses */
6534 #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS }
6535 /** Array initializer of FLASH peripheral base pointers */
6536 #define FLASH_BASE_PTRS_NS { FLASH_NS }
6537#else
6538 /** Peripheral FLASH base address */
6539 #define FLASH_BASE (0x40034000u)
6540 /** Peripheral FLASH base pointer */
6541 #define FLASH ((FLASH_Type *)FLASH_BASE)
6542 /** Array initializer of FLASH peripheral base addresses */
6543 #define FLASH_BASE_ADDRS { FLASH_BASE }
6544 /** Array initializer of FLASH peripheral base pointers */
6545 #define FLASH_BASE_PTRS { FLASH }
6546#endif
6547
6548/*!
6549 * @}
6550 */ /* end of group FLASH_Peripheral_Access_Layer */
6551
6552
6553/* ----------------------------------------------------------------------------
6554 -- FLASH_CFPA Peripheral Access Layer
6555 ---------------------------------------------------------------------------- */
6556
6557/*!
6558 * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer
6559 * @{
6560 */
6561
6562/** FLASH_CFPA - Register Layout Typedef */
6563typedef struct {
6564 __IO uint32_t HEADER; /**< ., offset: 0x0 */
6565 __IO uint32_t VERSION; /**< ., offset: 0x4 */
6566 __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */
6567 __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */
6568 __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */
6569 uint8_t RESERVED_0[4];
6570 __IO uint32_t ROTKH_REVOKE; /**< ., offset: 0x18 */
6571 __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x1C */
6572 __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */
6573 __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */
6574 __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */
6575 __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */
6576 union { /* offset: 0x30 */
6577 __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< ., array offset: 0x30, array step: 0x4 */
6578 struct { /* offset: 0x30 */
6579 __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< ., offset: 0x30 */
6580 __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< ., offset: 0x34 */
6581 __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< ., array offset: 0x38, array step: 0x4 */
6582 } PRINCE_REGION0_IV_CODE_CORE;
6583 };
6584 union { /* offset: 0x68 */
6585 __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< ., array offset: 0x68, array step: 0x4 */
6586 struct { /* offset: 0x68 */
6587 __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< ., offset: 0x68 */
6588 __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< ., offset: 0x6C */
6589 __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< ., array offset: 0x70, array step: 0x4 */
6590 } PRINCE_REGION1_IV_CODE_CORE;
6591 };
6592 union { /* offset: 0xA0 */
6593 __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< ., array offset: 0xA0, array step: 0x4 */
6594 struct { /* offset: 0xA0 */
6595 __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< ., offset: 0xA0 */
6596 __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< ., offset: 0xA4 */
6597 __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< ., array offset: 0xA8, array step: 0x4 */
6598 } PRINCE_REGION2_IV_CODE_CORE;
6599 };
6600 uint8_t RESERVED_1[40];
6601 __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */
6602 __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */
6603} FLASH_CFPA_Type;
6604
6605/* ----------------------------------------------------------------------------
6606 -- FLASH_CFPA Register Masks
6607 ---------------------------------------------------------------------------- */
6608
6609/*!
6610 * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks
6611 * @{
6612 */
6613
6614/*! @name HEADER - . */
6615/*! @{ */
6616#define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU)
6617#define FLASH_CFPA_HEADER_FIELD_SHIFT (0U)
6618/*! FIELD - .
6619 */
6620#define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK)
6621/*! @} */
6622
6623/*! @name VERSION - . */
6624/*! @{ */
6625#define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU)
6626#define FLASH_CFPA_VERSION_FIELD_SHIFT (0U)
6627/*! FIELD - .
6628 */
6629#define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK)
6630/*! @} */
6631
6632/*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */
6633/*! @{ */
6634#define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU)
6635#define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U)
6636/*! FIELD - .
6637 */
6638#define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK)
6639/*! @} */
6640
6641/*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */
6642/*! @{ */
6643#define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU)
6644#define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U)
6645/*! FIELD - .
6646 */
6647#define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK)
6648/*! @} */
6649
6650/*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */
6651/*! @{ */
6652#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU)
6653#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U)
6654/*! FIELD - .
6655 */
6656#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK)
6657/*! @} */
6658
6659/*! @name ROTKH_REVOKE - . */
6660/*! @{ */
6661#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U)
6662#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U)
6663/*! RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked
6664 */
6665#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK)
6666#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU)
6667#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U)
6668/*! RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked
6669 */
6670#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK)
6671#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U)
6672#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U)
6673/*! RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked
6674 */
6675#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK)
6676#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK (0xC0U)
6677#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT (6U)
6678/*! RoTK3_EN - RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked
6679 */
6680#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK)
6681/*! @} */
6682
6683/*! @name VENDOR_USAGE - . */
6684/*! @{ */
6685#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU)
6686#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U)
6687/*! DBG_VENDOR_USAGE - DBG_VENDOR_USAGE.
6688 */
6689#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK)
6690#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U)
6691#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U)
6692/*! INVERSE_VALUE - inverse value of bits [15:0]
6693 */
6694#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK)
6695/*! @} */
6696
6697/*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */
6698/*! @{ */
6699#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U)
6700#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U)
6701/*! NIDEN - Non Secure non-invasive debug enable
6702 * 0b0..Use DAP to enable
6703 * 0b1..Fixed state
6704 */
6705#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK)
6706#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U)
6707#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U)
6708/*! DBGEN - Non Secure debug enable
6709 * 0b0..Use DAP to enable
6710 * 0b1..Fixed state
6711 */
6712#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK)
6713#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U)
6714#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U)
6715/*! SPNIDEN - Secure non-invasive debug enable
6716 * 0b0..Use DAP to enable
6717 * 0b1..Fixed state
6718 */
6719#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK)
6720#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U)
6721#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U)
6722/*! SPIDEN - Secure invasive debug enable
6723 * 0b0..Use DAP to enable
6724 * 0b1..Fixed state
6725 */
6726#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK)
6727#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U)
6728#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U)
6729/*! TAPEN - JTAG TAP enable
6730 * 0b0..Use DAP to enable
6731 * 0b1..Fixed state
6732 */
6733#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK)
6734#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U)
6735#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U)
6736/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable
6737 * 0b0..Use DAP to enable
6738 * 0b1..Fixed state
6739 */
6740#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK)
6741#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U)
6742#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U)
6743/*! ISP_CMD_EN - ISP Boot Command enable
6744 * 0b0..Use DAP to enable
6745 * 0b1..Fixed state
6746 */
6747#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK)
6748#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U)
6749#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U)
6750/*! FA_CMD_EN - FA Command enable
6751 * 0b0..Use DAP to enable
6752 * 0b1..Fixed state
6753 */
6754#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK)
6755#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U)
6756#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U)
6757/*! ME_CMD_EN - Flash Mass Erase Command enable
6758 * 0b0..Use DAP to enable
6759 * 0b1..Fixed state
6760 */
6761#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK)
6762#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U)
6763#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U)
6764/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable
6765 * 0b0..Use DAP to enable
6766 * 0b1..Fixed state
6767 */
6768#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK)
6769#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U)
6770#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U)
6771/*! UUID_CHECK - Enforce UUID match during Debug authentication.
6772 */
6773#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK)
6774#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U)
6775#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U)
6776/*! INVERSE_VALUE - inverse value of bits [15:0]
6777 */
6778#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK)
6779/*! @} */
6780
6781/*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */
6782/*! @{ */
6783#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U)
6784#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U)
6785/*! NIDEN - Non Secure non-invasive debug fixed state
6786 * 0b0..Disable
6787 * 0b1..Enable
6788 */
6789#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK)
6790#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U)
6791#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U)
6792/*! DBGEN - Non Secure debug fixed state
6793 * 0b0..Disable
6794 * 0b1..Enable
6795 */
6796#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK)
6797#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U)
6798#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U)
6799/*! SPNIDEN - Secure non-invasive debug fixed state
6800 * 0b0..Disable
6801 * 0b1..Enable
6802 */
6803#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK)
6804#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U)
6805#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U)
6806/*! SPIDEN - Secure invasive debug fixed state
6807 * 0b0..Disable
6808 * 0b1..Enable
6809 */
6810#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK)
6811#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U)
6812#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U)
6813/*! TAPEN - JTAG TAP fixed state
6814 * 0b0..Disable
6815 * 0b1..Enable
6816 */
6817#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK)
6818#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U)
6819#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U)
6820/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state
6821 * 0b0..Disable
6822 * 0b1..Enable
6823 */
6824#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK)
6825#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U)
6826#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U)
6827/*! ISP_CMD_EN - ISP Boot Command fixed state
6828 * 0b0..Disable
6829 * 0b1..Enable
6830 */
6831#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK)
6832#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U)
6833#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U)
6834/*! FA_CMD_EN - FA Command fixed state
6835 * 0b0..Disable
6836 * 0b1..Enable
6837 */
6838#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK)
6839#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U)
6840#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U)
6841/*! ME_CMD_EN - Flash Mass Erase Command fixed state
6842 * 0b0..Disable
6843 * 0b1..Enable
6844 */
6845#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK)
6846#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U)
6847#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U)
6848/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state
6849 * 0b0..Disable
6850 * 0b1..Enable
6851 */
6852#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK)
6853#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U)
6854#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U)
6855/*! INVERSE_VALUE - inverse value of bits [15:0]
6856 */
6857#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK)
6858/*! @} */
6859
6860/*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */
6861/*! @{ */
6862#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU)
6863#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U)
6864/*! FIELD - .
6865 */
6866#define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK)
6867/*! @} */
6868
6869/*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */
6870/*! @{ */
6871#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU)
6872#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U)
6873/*! FIELD - .
6874 */
6875#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK)
6876/*! @} */
6877
6878/*! @name PRINCE_REGION0_IV_CODE - . */
6879/*! @{ */
6880#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU)
6881#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U)
6882/*! FIELD - .
6883 */
6884#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK)
6885/*! @} */
6886
6887/* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */
6888#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U)
6889
6890/*! @name PRINCE_REGION0_IV_HEADER0 - . */
6891/*! @{ */
6892#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU)
6893#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U)
6894/*! FIELD - .
6895 */
6896#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK)
6897/*! @} */
6898
6899/*! @name PRINCE_REGION0_IV_HEADER1 - . */
6900/*! @{ */
6901#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U)
6902#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U)
6903/*! TYPE - .
6904 */
6905#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK)
6906#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U)
6907#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U)
6908/*! INDEX - .
6909 */
6910#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK)
6911#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U)
6912#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U)
6913/*! SIZE - .
6914 */
6915#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK)
6916/*! @} */
6917
6918/*! @name PRINCE_REGION0_IV_BODY - . */
6919/*! @{ */
6920#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU)
6921#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U)
6922/*! FIELD - .
6923 */
6924#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK)
6925/*! @} */
6926
6927/* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */
6928#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U)
6929
6930/*! @name PRINCE_REGION1_IV_CODE - . */
6931/*! @{ */
6932#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU)
6933#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U)
6934/*! FIELD - .
6935 */
6936#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK)
6937/*! @} */
6938
6939/* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */
6940#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U)
6941
6942/*! @name PRINCE_REGION1_IV_HEADER0 - . */
6943/*! @{ */
6944#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU)
6945#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U)
6946/*! FIELD - .
6947 */
6948#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK)
6949/*! @} */
6950
6951/*! @name PRINCE_REGION1_IV_HEADER1 - . */
6952/*! @{ */
6953#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U)
6954#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U)
6955/*! TYPE - .
6956 */
6957#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK)
6958#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U)
6959#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U)
6960/*! INDEX - .
6961 */
6962#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK)
6963#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U)
6964#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U)
6965/*! SIZE - .
6966 */
6967#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK)
6968/*! @} */
6969
6970/*! @name PRINCE_REGION1_IV_BODY - . */
6971/*! @{ */
6972#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU)
6973#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U)
6974/*! FIELD - .
6975 */
6976#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK)
6977/*! @} */
6978
6979/* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */
6980#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U)
6981
6982/*! @name PRINCE_REGION2_IV_CODE - . */
6983/*! @{ */
6984#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU)
6985#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U)
6986/*! FIELD - .
6987 */
6988#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK)
6989/*! @} */
6990
6991/* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */
6992#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U)
6993
6994/*! @name PRINCE_REGION2_IV_HEADER0 - . */
6995/*! @{ */
6996#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU)
6997#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U)
6998/*! FIELD - .
6999 */
7000#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK)
7001/*! @} */
7002
7003/*! @name PRINCE_REGION2_IV_HEADER1 - . */
7004/*! @{ */
7005#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U)
7006#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U)
7007/*! TYPE - .
7008 */
7009#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK)
7010#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U)
7011#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U)
7012/*! INDEX - .
7013 */
7014#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK)
7015#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U)
7016#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U)
7017/*! SIZE - .
7018 */
7019#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK)
7020/*! @} */
7021
7022/*! @name PRINCE_REGION2_IV_BODY - . */
7023/*! @{ */
7024#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU)
7025#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U)
7026/*! FIELD - .
7027 */
7028#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK)
7029/*! @} */
7030
7031/* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */
7032#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U)
7033
7034/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */
7035/*! @{ */
7036#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU)
7037#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U)
7038/*! FIELD - .
7039 */
7040#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK)
7041/*! @} */
7042
7043/* The count of FLASH_CFPA_CUSTOMER_DEFINED */
7044#define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U)
7045
7046/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */
7047/*! @{ */
7048#define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU)
7049#define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U)
7050/*! FIELD - .
7051 */
7052#define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK)
7053/*! @} */
7054
7055/* The count of FLASH_CFPA_SHA256_DIGEST */
7056#define FLASH_CFPA_SHA256_DIGEST_COUNT (8U)
7057
7058
7059/*!
7060 * @}
7061 */ /* end of group FLASH_CFPA_Register_Masks */
7062
7063
7064/* FLASH_CFPA - Peripheral instance base addresses */
7065#if (__ARM_FEATURE_CMSE & 0x2)
7066 /** Peripheral FLASH_CFPA0 base address */
7067 #define FLASH_CFPA0_BASE (0x1009E000u)
7068 /** Peripheral FLASH_CFPA0 base address */
7069 #define FLASH_CFPA0_BASE_NS (0x9E000u)
7070 /** Peripheral FLASH_CFPA0 base pointer */
7071 #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE)
7072 /** Peripheral FLASH_CFPA0 base pointer */
7073 #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS)
7074 /** Peripheral FLASH_CFPA1 base address */
7075 #define FLASH_CFPA1_BASE (0x1009E200u)
7076 /** Peripheral FLASH_CFPA1 base address */
7077 #define FLASH_CFPA1_BASE_NS (0x9E200u)
7078 /** Peripheral FLASH_CFPA1 base pointer */
7079 #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE)
7080 /** Peripheral FLASH_CFPA1 base pointer */
7081 #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS)
7082 /** Peripheral FLASH_CFPA_SCRATCH base address */
7083 #define FLASH_CFPA_SCRATCH_BASE (0x1009DE00u)
7084 /** Peripheral FLASH_CFPA_SCRATCH base address */
7085 #define FLASH_CFPA_SCRATCH_BASE_NS (0x9DE00u)
7086 /** Peripheral FLASH_CFPA_SCRATCH base pointer */
7087 #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE)
7088 /** Peripheral FLASH_CFPA_SCRATCH base pointer */
7089 #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS)
7090 /** Array initializer of FLASH_CFPA peripheral base addresses */
7091 #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE }
7092 /** Array initializer of FLASH_CFPA peripheral base pointers */
7093 #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH }
7094 /** Array initializer of FLASH_CFPA peripheral base addresses */
7095 #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS }
7096 /** Array initializer of FLASH_CFPA peripheral base pointers */
7097 #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS }
7098#else
7099 /** Peripheral FLASH_CFPA0 base address */
7100 #define FLASH_CFPA0_BASE (0x9E000u)
7101 /** Peripheral FLASH_CFPA0 base pointer */
7102 #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE)
7103 /** Peripheral FLASH_CFPA1 base address */
7104 #define FLASH_CFPA1_BASE (0x9E200u)
7105 /** Peripheral FLASH_CFPA1 base pointer */
7106 #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE)
7107 /** Peripheral FLASH_CFPA_SCRATCH base address */
7108 #define FLASH_CFPA_SCRATCH_BASE (0x9DE00u)
7109 /** Peripheral FLASH_CFPA_SCRATCH base pointer */
7110 #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE)
7111 /** Array initializer of FLASH_CFPA peripheral base addresses */
7112 #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE }
7113 /** Array initializer of FLASH_CFPA peripheral base pointers */
7114 #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH }
7115#endif
7116
7117/*!
7118 * @}
7119 */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */
7120
7121
7122/* ----------------------------------------------------------------------------
7123 -- FLASH_CMPA Peripheral Access Layer
7124 ---------------------------------------------------------------------------- */
7125
7126/*!
7127 * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer
7128 * @{
7129 */
7130
7131/** FLASH_CMPA - Register Layout Typedef */
7132typedef struct {
7133 __IO uint32_t BOOT_CFG; /**< ., offset: 0x0 */
7134 __IO uint32_t SPI_FLASH_CFG; /**< ., offset: 0x4 */
7135 __IO uint32_t USB_ID; /**< ., offset: 0x8 */
7136 __IO uint32_t SDIO_CFG; /**< ., offset: 0xC */
7137 __IO uint32_t CC_SOCU_PIN; /**< ., offset: 0x10 */
7138 __IO uint32_t CC_SOCU_DFLT; /**< ., offset: 0x14 */
7139 __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x18 */
7140 __IO uint32_t SECURE_BOOT_CFG; /**< ., offset: 0x1C */
7141 __IO uint32_t PRINCE_BASE_ADDR; /**< ., offset: 0x20 */
7142 __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */
7143 __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */
7144 __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */
7145 __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM; /**< Xtal 32kHz capabank triming., offset: 0x30 */
7146 __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM; /**< Xtal 16MHz capabank triming., offset: 0x34 */
7147 uint8_t RESERVED_0[24];
7148 __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */
7149 uint8_t RESERVED_1[144];
7150 __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */
7151 __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */
7152} FLASH_CMPA_Type;
7153
7154/* ----------------------------------------------------------------------------
7155 -- FLASH_CMPA Register Masks
7156 ---------------------------------------------------------------------------- */
7157
7158/*!
7159 * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks
7160 * @{
7161 */
7162
7163/*! @name BOOT_CFG - . */
7164/*! @{ */
7165#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U)
7166#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U)
7167/*! DEFAULT_ISP_MODE - Default ISP mode:
7168 * 0b000..Auto ISP
7169 * 0b001..USB_HID_MSC
7170 * 0b010..SPI Slave ISP
7171 * 0b011..I2C Slave ISP
7172 * 0b111..Disable ISP fall through
7173 */
7174#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK)
7175#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U)
7176#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U)
7177/*! BOOT_SPEED - Core clock:
7178 * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE
7179 * 0b01..96MHz FRO
7180 * 0b10..48MHz FRO
7181 */
7182#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK)
7183#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U)
7184#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U)
7185/*! BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle
7186 * rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO
7187 * pin
7188 */
7189#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK)
7190/*! @} */
7191
7192/*! @name SPI_FLASH_CFG - . */
7193/*! @{ */
7194#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK (0x1FU)
7195#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT (0U)
7196/*! SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field.
7197 */
7198#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK)
7199/*! @} */
7200
7201/*! @name USB_ID - . */
7202/*! @{ */
7203#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU)
7204#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U)
7205/*! USB_VENDOR_ID - .
7206 */
7207#define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK)
7208#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U)
7209#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U)
7210/*! USB_PRODUCT_ID - .
7211 */
7212#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK)
7213/*! @} */
7214
7215/*! @name SDIO_CFG - . */
7216/*! @{ */
7217#define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU)
7218#define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U)
7219/*! FIELD - .
7220 */
7221#define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK)
7222/*! @} */
7223
7224/*! @name CC_SOCU_PIN - . */
7225/*! @{ */
7226#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK (0x1U)
7227#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT (0U)
7228/*! NIDEN - Non Secure non-invasive debug enable
7229 * 0b0..Use DAP to enable
7230 * 0b1..Fixed state
7231 */
7232#define FLASH_CMPA_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK)
7233#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK (0x2U)
7234#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT (1U)
7235/*! DBGEN - Non Secure debug enable
7236 * 0b0..Use DAP to enable
7237 * 0b1..Fixed state
7238 */
7239#define FLASH_CMPA_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK)
7240#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK (0x4U)
7241#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT (2U)
7242/*! SPNIDEN - Secure non-invasive debug enable
7243 * 0b0..Use DAP to enable
7244 * 0b1..Fixed state
7245 */
7246#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK)
7247#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK (0x8U)
7248#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT (3U)
7249/*! SPIDEN - Secure invasive debug enable
7250 * 0b0..Use DAP to enable
7251 * 0b1..Fixed state
7252 */
7253#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK)
7254#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK (0x10U)
7255#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT (4U)
7256/*! TAPEN - JTAG TAP enable
7257 * 0b0..Use DAP to enable
7258 * 0b1..Fixed state
7259 */
7260#define FLASH_CMPA_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK)
7261#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U)
7262#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U)
7263/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable
7264 * 0b0..Use DAP to enable
7265 * 0b1..Fixed state
7266 */
7267#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK)
7268#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U)
7269#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U)
7270/*! ISP_CMD_EN - ISP Boot Command enable
7271 * 0b0..Use DAP to enable
7272 * 0b1..Fixed state
7273 */
7274#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK)
7275#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U)
7276#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U)
7277/*! FA_CMD_EN - FA Command enable
7278 * 0b0..Use DAP to enable
7279 * 0b1..Fixed state
7280 */
7281#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK)
7282#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U)
7283#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U)
7284/*! ME_CMD_EN - Flash Mass Erase Command enable
7285 * 0b0..Use DAP to enable
7286 * 0b1..Fixed state
7287 */
7288#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK)
7289#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U)
7290#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U)
7291/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable
7292 * 0b0..Use DAP to enable
7293 * 0b1..Fixed state
7294 */
7295#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK)
7296#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U)
7297#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U)
7298/*! UUID_CHECK - Enforce UUID match during Debug authentication.
7299 */
7300#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK)
7301#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U)
7302#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U)
7303/*! INVERSE_VALUE - inverse value of bits [15:0]
7304 */
7305#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK)
7306/*! @} */
7307
7308/*! @name CC_SOCU_DFLT - . */
7309/*! @{ */
7310#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK (0x1U)
7311#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT (0U)
7312/*! NIDEN - Non Secure non-invasive debug fixed state
7313 * 0b0..Disable
7314 * 0b1..Enable
7315 */
7316#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK)
7317#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK (0x2U)
7318#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT (1U)
7319/*! DBGEN - Non Secure debug fixed state
7320 * 0b0..Disable
7321 * 0b1..Enable
7322 */
7323#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK)
7324#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U)
7325#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U)
7326/*! SPNIDEN - Secure non-invasive debug fixed state
7327 * 0b0..Disable
7328 * 0b1..Enable
7329 */
7330#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK)
7331#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK (0x8U)
7332#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT (3U)
7333/*! SPIDEN - Secure invasive debug fixed state
7334 * 0b0..Disable
7335 * 0b1..Enable
7336 */
7337#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK)
7338#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK (0x10U)
7339#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT (4U)
7340/*! TAPEN - JTAG TAP fixed state
7341 * 0b0..Disable
7342 * 0b1..Enable
7343 */
7344#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK)
7345#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U)
7346#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U)
7347/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state
7348 * 0b0..Disable
7349 * 0b1..Enable
7350 */
7351#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK)
7352#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U)
7353#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U)
7354/*! ISP_CMD_EN - ISP Boot Command fixed state
7355 * 0b0..Disable
7356 * 0b1..Enable
7357 */
7358#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK)
7359#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U)
7360#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U)
7361/*! FA_CMD_EN - FA Command fixed state
7362 * 0b0..Disable
7363 * 0b1..Enable
7364 */
7365#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK)
7366#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U)
7367#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U)
7368/*! ME_CMD_EN - Flash Mass Erase Command fixed state
7369 * 0b0..Disable
7370 * 0b1..Enable
7371 */
7372#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK)
7373#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U)
7374#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U)
7375/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state
7376 * 0b0..Disable
7377 * 0b1..Enable
7378 */
7379#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK)
7380#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U)
7381#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U)
7382/*! INVERSE_VALUE - inverse value of bits [15:0]
7383 */
7384#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK)
7385/*! @} */
7386
7387/*! @name VENDOR_USAGE - . */
7388/*! @{ */
7389#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK (0xFFFF0000U)
7390#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT (16U)
7391/*! VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area.
7392 */
7393#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK)
7394/*! @} */
7395
7396/*! @name SECURE_BOOT_CFG - . */
7397/*! @{ */
7398#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U)
7399#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U)
7400/*! RSA4K - Use RSA4096 keys only. 00- RSA2048 keys 01, 10, 11 - RSA4096 keys
7401 */
7402#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK)
7403#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK (0xCU)
7404#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT (2U)
7405/*! DICE_ENC_NXP_CFG - Include NXP area in DICE computation. 00 - not included 01, 10, 11 - included
7406 */
7407#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK)
7408#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U)
7409#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U)
7410/*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. 00 - not included 01, 10, 11 - included
7411 */
7412#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK)
7413#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U)
7414#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U)
7415/*! SKIP_DICE - Skip DICE computation. 00 - Enable DICE 01,10,11 - Disable DICE
7416 */
7417#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK)
7418#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U)
7419#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U)
7420/*! TZM_IMAGE_TYPE - TrustZone-M mode. 00 - TZM mode in image header. 01 - Disable TZ-M. Boots to
7421 * NonSecure. 10 - TZ-M enable boots to secure mode. 11 - Preset TZM checker from image header.
7422 */
7423#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK)
7424#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U)
7425#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U)
7426/*! BLOCK_SET_KEY - Block PUF key code generation. 00 - Enable Key code generation 01, 10, 11 - Disable key code generation
7427 */
7428#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK)
7429#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U)
7430#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U)
7431/*! BLOCK_ENROLL - Block PUF enrollement. 00 - Enable enrollment mode 01, 10, 11 - Disable further enrollmnet
7432 */
7433#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK)
7434#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK (0xC000U)
7435#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT (14U)
7436/*! DICE_INC_SEC_EPOCH - Include security EPOCH in DICE
7437 */
7438#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK)
7439#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U)
7440#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U)
7441/*! SEC_BOOT_EN - Secure boot enable. 00 - Plain image (internal flash with or without CRC) 01, 10,
7442 * 11 - Boot signed images. (internal flash, RSA signed)
7443 */
7444#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK)
7445/*! @} */
7446
7447/*! @name PRINCE_BASE_ADDR - . */
7448/*! @{ */
7449#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU)
7450#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U)
7451/*! ADDR0_PRG - Programmable portion of the base address of region 0.
7452 */
7453#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK)
7454#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U)
7455#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U)
7456/*! ADDR1_PRG - Programmable portion of the base address of region 1.
7457 */
7458#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK)
7459#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U)
7460#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U)
7461/*! ADDR2_PRG - Programmable portion of the base address of region 2.
7462 */
7463#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK)
7464#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x30000U)
7465#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16U)
7466/*! LOCK_REG0 - Lock PRINCE region0 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked.
7467 */
7468#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK)
7469#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0xC0000U)
7470#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18U)
7471/*! LOCK_REG1 - Lock PRINCE region1 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked.
7472 */
7473#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK)
7474#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x300000U)
7475#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20U)
7476/*! LOCK_REG2 - Lock PRINCE region2 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked.
7477 */
7478#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK)
7479#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U)
7480#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U)
7481/*! REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased
7482 * together. 00 - Check is disabled. 01, 10, 11 - Check is enabled.
7483 */
7484#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK)
7485#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U)
7486#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U)
7487/*! REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased
7488 * together. 00 - Check is disabled. 01, 10, 11 - Check is enabled.
7489 */
7490#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK)
7491#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U)
7492#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U)
7493/*! REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased
7494 * together. 00 - Check is disabled. 01, 10, 11 - Check is enabled.
7495 */
7496#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK)
7497/*! @} */
7498
7499/*! @name PRINCE_SR_0 - Region 0, sub-region enable */
7500/*! @{ */
7501#define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU)
7502#define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U)
7503/*! FIELD - .
7504 */
7505#define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK)
7506/*! @} */
7507
7508/*! @name PRINCE_SR_1 - Region 1, sub-region enable */
7509/*! @{ */
7510#define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU)
7511#define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U)
7512/*! FIELD - .
7513 */
7514#define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK)
7515/*! @} */
7516
7517/*! @name PRINCE_SR_2 - Region 2, sub-region enable */
7518/*! @{ */
7519#define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU)
7520#define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U)
7521/*! FIELD - .
7522 */
7523#define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK)
7524/*! @} */
7525
7526/*! @name XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. */
7527/*! @{ */
7528#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U)
7529#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U)
7530/*! TRIM_VALID - 0 : Capa Bank trimmings not valid. Default trimmings value are used. 1 : Capa Bank trimmings valid.
7531 */
7532#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK)
7533#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU)
7534#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U)
7535/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600.
7536 */
7537#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK)
7538#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U)
7539#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U)
7540/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600.
7541 */
7542#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK)
7543#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U)
7544#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U)
7545/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600.
7546 */
7547#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK)
7548/*! @} */
7549
7550/*! @name XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. */
7551/*! @{ */
7552#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U)
7553#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U)
7554/*! TRIM_VALID - 0 : Capa Bank trimmings not valid. Default trimmings value are used. 1 : Capa Bank trimmings valid.
7555 */
7556#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK)
7557#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU)
7558#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U)
7559/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600.
7560 */
7561#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK)
7562#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U)
7563#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U)
7564/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600.
7565 */
7566#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK)
7567#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U)
7568#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U)
7569/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600.
7570 */
7571#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK)
7572/*! @} */
7573
7574/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] */
7575/*! @{ */
7576#define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU)
7577#define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U)
7578/*! FIELD - .
7579 */
7580#define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK)
7581/*! @} */
7582
7583/* The count of FLASH_CMPA_ROTKH */
7584#define FLASH_CMPA_ROTKH_COUNT (8U)
7585
7586/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */
7587/*! @{ */
7588#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU)
7589#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U)
7590/*! FIELD - .
7591 */
7592#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK)
7593/*! @} */
7594
7595/* The count of FLASH_CMPA_CUSTOMER_DEFINED */
7596#define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U)
7597
7598/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */
7599/*! @{ */
7600#define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU)
7601#define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U)
7602/*! FIELD - .
7603 */
7604#define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK)
7605/*! @} */
7606
7607/* The count of FLASH_CMPA_SHA256_DIGEST */
7608#define FLASH_CMPA_SHA256_DIGEST_COUNT (8U)
7609
7610
7611/*!
7612 * @}
7613 */ /* end of group FLASH_CMPA_Register_Masks */
7614
7615
7616/* FLASH_CMPA - Peripheral instance base addresses */
7617#if (__ARM_FEATURE_CMSE & 0x2)
7618 /** Peripheral FLASH_CMPA base address */
7619 #define FLASH_CMPA_BASE (0x1009E400u)
7620 /** Peripheral FLASH_CMPA base address */
7621 #define FLASH_CMPA_BASE_NS (0x9E400u)
7622 /** Peripheral FLASH_CMPA base pointer */
7623 #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE)
7624 /** Peripheral FLASH_CMPA base pointer */
7625 #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS)
7626 /** Array initializer of FLASH_CMPA peripheral base addresses */
7627 #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE }
7628 /** Array initializer of FLASH_CMPA peripheral base pointers */
7629 #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA }
7630 /** Array initializer of FLASH_CMPA peripheral base addresses */
7631 #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS }
7632 /** Array initializer of FLASH_CMPA peripheral base pointers */
7633 #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS }
7634#else
7635 /** Peripheral FLASH_CMPA base address */
7636 #define FLASH_CMPA_BASE (0x9E400u)
7637 /** Peripheral FLASH_CMPA base pointer */
7638 #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE)
7639 /** Array initializer of FLASH_CMPA peripheral base addresses */
7640 #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE }
7641 /** Array initializer of FLASH_CMPA peripheral base pointers */
7642 #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA }
7643#endif
7644
7645/*!
7646 * @}
7647 */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */
7648
7649
7650/* ----------------------------------------------------------------------------
7651 -- FLASH_KEY_STORE Peripheral Access Layer
7652 ---------------------------------------------------------------------------- */
7653
7654/*!
7655 * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer
7656 * @{
7657 */
7658
7659/** FLASH_KEY_STORE - Register Layout Typedef */
7660typedef struct {
7661 struct { /* offset: 0x0 */
7662 __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */
7663 __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */
7664 } KEY_STORE_HEADER;
7665 __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */
7666 union { /* offset: 0x4B0 */
7667 __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */
7668 struct { /* offset: 0x4B0 */
7669 __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */
7670 __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */
7671 __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */
7672 } SBKEY_KEY_CODE_CORE;
7673 };
7674 union { /* offset: 0x4E8 */
7675 __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */
7676 struct { /* offset: 0x4E8 */
7677 __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */
7678 __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */
7679 __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */
7680 } USER_KEK_KEY_CODE_CORE;
7681 };
7682 union { /* offset: 0x520 */
7683 __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */
7684 struct { /* offset: 0x520 */
7685 __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */
7686 __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */
7687 __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */
7688 } UDS_KEY_CODE_CORE;
7689 };
7690 union { /* offset: 0x558 */
7691 __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */
7692 struct { /* offset: 0x558 */
7693 __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */
7694 __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */
7695 __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */
7696 } PRINCE_REGION0_KEY_CODE_CORE;
7697 };
7698 union { /* offset: 0x590 */
7699 __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */
7700 struct { /* offset: 0x590 */
7701 __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */
7702 __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */
7703 __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */
7704 } PRINCE_REGION1_KEY_CODE_CORE;
7705 };
7706 union { /* offset: 0x5C8 */
7707 __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */
7708 struct { /* offset: 0x5C8 */
7709 __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */
7710 __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */
7711 __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */
7712 } PRINCE_REGION2_KEY_CODE_CORE;
7713 };
7714} FLASH_KEY_STORE_Type;
7715
7716/* ----------------------------------------------------------------------------
7717 -- FLASH_KEY_STORE Register Masks
7718 ---------------------------------------------------------------------------- */
7719
7720/*!
7721 * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks
7722 * @{
7723 */
7724
7725/*! @name HEADER - Valid Key Sore Header : 0x95959595 */
7726/*! @{ */
7727#define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU)
7728#define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U)
7729/*! FIELD - .
7730 */
7731#define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK)
7732/*! @} */
7733
7734/*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */
7735/*! @{ */
7736#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU)
7737#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U)
7738/*! FIELD - .
7739 */
7740#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK)
7741/*! @} */
7742
7743/*! @name ACTIVATION_CODE - . */
7744/*! @{ */
7745#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU)
7746#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U)
7747/*! FIELD - .
7748 */
7749#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK)
7750/*! @} */
7751
7752/* The count of FLASH_KEY_STORE_ACTIVATION_CODE */
7753#define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U)
7754
7755/*! @name SBKEY_KEY_CODE - . */
7756/*! @{ */
7757#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)
7758#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U)
7759/*! FIELD - .
7760 */
7761#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK)
7762/*! @} */
7763
7764/* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */
7765#define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U)
7766
7767/*! @name SBKEY_HEADER0 - . */
7768/*! @{ */
7769#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU)
7770#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U)
7771/*! FIELD - .
7772 */
7773#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK)
7774/*! @} */
7775
7776/*! @name SBKEY_HEADER1 - . */
7777/*! @{ */
7778#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U)
7779#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U)
7780/*! TYPE - .
7781 */
7782#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK)
7783#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U)
7784#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U)
7785/*! INDEX - .
7786 */
7787#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK)
7788#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U)
7789#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U)
7790/*! SIZE - .
7791 */
7792#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK)
7793/*! @} */
7794
7795/*! @name SBKEY_BODY - . */
7796/*! @{ */
7797#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU)
7798#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U)
7799/*! FIELD - .
7800 */
7801#define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK)
7802/*! @} */
7803
7804/* The count of FLASH_KEY_STORE_SBKEY_BODY */
7805#define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U)
7806
7807/*! @name USER_KEK_KEY_CODE - . */
7808/*! @{ */
7809#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)
7810#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U)
7811/*! FIELD - .
7812 */
7813#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK)
7814/*! @} */
7815
7816/* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */
7817#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U)
7818
7819/*! @name USER_KEK_HEADER0 - . */
7820/*! @{ */
7821#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU)
7822#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U)
7823/*! FIELD - .
7824 */
7825#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK)
7826/*! @} */
7827
7828/*! @name USER_KEK_HEADER1 - . */
7829/*! @{ */
7830#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U)
7831#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U)
7832/*! TYPE - .
7833 */
7834#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK)
7835#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U)
7836#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U)
7837/*! INDEX - .
7838 */
7839#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK)
7840#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U)
7841#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U)
7842/*! SIZE - .
7843 */
7844#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK)
7845/*! @} */
7846
7847/*! @name USER_KEK_BODY - . */
7848/*! @{ */
7849#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU)
7850#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U)
7851/*! FIELD - .
7852 */
7853#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK)
7854/*! @} */
7855
7856/* The count of FLASH_KEY_STORE_USER_KEK_BODY */
7857#define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U)
7858
7859/*! @name UDS_KEY_CODE - . */
7860/*! @{ */
7861#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)
7862#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U)
7863/*! FIELD - .
7864 */
7865#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK)
7866/*! @} */
7867
7868/* The count of FLASH_KEY_STORE_UDS_KEY_CODE */
7869#define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U)
7870
7871/*! @name UDS_HEADER0 - . */
7872/*! @{ */
7873#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU)
7874#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U)
7875/*! FIELD - .
7876 */
7877#define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK)
7878/*! @} */
7879
7880/*! @name UDS_HEADER1 - . */
7881/*! @{ */
7882#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U)
7883#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U)
7884/*! TYPE - .
7885 */
7886#define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK)
7887#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U)
7888#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U)
7889/*! INDEX - .
7890 */
7891#define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK)
7892#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U)
7893#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U)
7894/*! SIZE - .
7895 */
7896#define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK)
7897/*! @} */
7898
7899/*! @name UDS_BODY - . */
7900/*! @{ */
7901#define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU)
7902#define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U)
7903/*! FIELD - .
7904 */
7905#define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK)
7906/*! @} */
7907
7908/* The count of FLASH_KEY_STORE_UDS_BODY */
7909#define FLASH_KEY_STORE_UDS_BODY_COUNT (12U)
7910
7911/*! @name PRINCE_REGION0_KEY_CODE - . */
7912/*! @{ */
7913#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)
7914#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U)
7915/*! FIELD - .
7916 */
7917#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK)
7918/*! @} */
7919
7920/* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */
7921#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U)
7922
7923/*! @name PRINCE_REGION0_HEADER0 - . */
7924/*! @{ */
7925#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU)
7926#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U)
7927/*! FIELD - .
7928 */
7929#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK)
7930/*! @} */
7931
7932/*! @name PRINCE_REGION0_HEADER1 - . */
7933/*! @{ */
7934#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U)
7935#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U)
7936/*! TYPE - .
7937 */
7938#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK)
7939#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U)
7940#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U)
7941/*! INDEX - .
7942 */
7943#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK)
7944#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U)
7945#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U)
7946/*! SIZE - .
7947 */
7948#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK)
7949/*! @} */
7950
7951/*! @name PRINCE_REGION0_BODY - . */
7952/*! @{ */
7953#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU)
7954#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U)
7955/*! FIELD - .
7956 */
7957#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK)
7958/*! @} */
7959
7960/* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */
7961#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U)
7962
7963/*! @name PRINCE_REGION1_KEY_CODE - . */
7964/*! @{ */
7965#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)
7966#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U)
7967/*! FIELD - .
7968 */
7969#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK)
7970/*! @} */
7971
7972/* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */
7973#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U)
7974
7975/*! @name PRINCE_REGION1_HEADER0 - . */
7976/*! @{ */
7977#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU)
7978#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U)
7979/*! FIELD - .
7980 */
7981#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK)
7982/*! @} */
7983
7984/*! @name PRINCE_REGION1_HEADER1 - . */
7985/*! @{ */
7986#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U)
7987#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U)
7988/*! TYPE - .
7989 */
7990#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK)
7991#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U)
7992#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U)
7993/*! INDEX - .
7994 */
7995#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK)
7996#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U)
7997#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U)
7998/*! SIZE - .
7999 */
8000#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK)
8001/*! @} */
8002
8003/*! @name PRINCE_REGION1_BODY - . */
8004/*! @{ */
8005#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU)
8006#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U)
8007/*! FIELD - .
8008 */
8009#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK)
8010/*! @} */
8011
8012/* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */
8013#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U)
8014
8015/*! @name PRINCE_REGION2_KEY_CODE - . */
8016/*! @{ */
8017#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)
8018#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U)
8019/*! FIELD - .
8020 */
8021#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK)
8022/*! @} */
8023
8024/* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */
8025#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U)
8026
8027/*! @name PRINCE_REGION2_HEADER0 - . */
8028/*! @{ */
8029#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU)
8030#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U)
8031/*! FIELD - .
8032 */
8033#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK)
8034/*! @} */
8035
8036/*! @name PRINCE_REGION2_HEADER1 - . */
8037/*! @{ */
8038#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U)
8039#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U)
8040/*! TYPE - .
8041 */
8042#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK)
8043#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U)
8044#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U)
8045/*! INDEX - .
8046 */
8047#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK)
8048#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U)
8049#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U)
8050/*! SIZE - .
8051 */
8052#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK)
8053/*! @} */
8054
8055/*! @name PRINCE_REGION2_BODY - . */
8056/*! @{ */
8057#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU)
8058#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U)
8059/*! FIELD - .
8060 */
8061#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK)
8062/*! @} */
8063
8064/* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */
8065#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U)
8066
8067
8068/*!
8069 * @}
8070 */ /* end of group FLASH_KEY_STORE_Register_Masks */
8071
8072
8073/* FLASH_KEY_STORE - Peripheral instance base addresses */
8074#if (__ARM_FEATURE_CMSE & 0x2)
8075 /** Peripheral FLASH_KEY_STORE base address */
8076 #define FLASH_KEY_STORE_BASE (0x1009E600u)
8077 /** Peripheral FLASH_KEY_STORE base address */
8078 #define FLASH_KEY_STORE_BASE_NS (0x9E600u)
8079 /** Peripheral FLASH_KEY_STORE base pointer */
8080 #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE)
8081 /** Peripheral FLASH_KEY_STORE base pointer */
8082 #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS)
8083 /** Array initializer of FLASH_KEY_STORE peripheral base addresses */
8084 #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE }
8085 /** Array initializer of FLASH_KEY_STORE peripheral base pointers */
8086 #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE }
8087 /** Array initializer of FLASH_KEY_STORE peripheral base addresses */
8088 #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS }
8089 /** Array initializer of FLASH_KEY_STORE peripheral base pointers */
8090 #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS }
8091#else
8092 /** Peripheral FLASH_KEY_STORE base address */
8093 #define FLASH_KEY_STORE_BASE (0x9E600u)
8094 /** Peripheral FLASH_KEY_STORE base pointer */
8095 #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE)
8096 /** Array initializer of FLASH_KEY_STORE peripheral base addresses */
8097 #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE }
8098 /** Array initializer of FLASH_KEY_STORE peripheral base pointers */
8099 #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE }
8100#endif
8101
8102/*!
8103 * @}
8104 */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */
8105
8106
8107/* ----------------------------------------------------------------------------
8108 -- FLEXCOMM Peripheral Access Layer
8109 ---------------------------------------------------------------------------- */
8110
8111/*!
8112 * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
8113 * @{
8114 */
8115
8116/** FLEXCOMM - Register Layout Typedef */
8117typedef struct {
8118 uint8_t RESERVED_0[4088];
8119 __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
8120 __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */
8121} FLEXCOMM_Type;
8122
8123/* ----------------------------------------------------------------------------
8124 -- FLEXCOMM Register Masks
8125 ---------------------------------------------------------------------------- */
8126
8127/*!
8128 * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
8129 * @{
8130 */
8131
8132/*! @name PSELID - Peripheral Select and Flexcomm ID register. */
8133/*! @{ */
8134#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U)
8135#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U)
8136/*! PERSEL - Peripheral Select. This field is writabl