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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5526/drivers/fsl_inputmux_connections.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5526/drivers/fsl_inputmux_connections.h
new file mode 100644
index 000000000..6031941dc
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5526/drivers/fsl_inputmux_connections.h
@@ -0,0 +1,496 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_INPUTMUX_CONNECTIONS_
10#define _FSL_INPUTMUX_CONNECTIONS_
11
12/*******************************************************************************
13 * Definitions
14 ******************************************************************************/
15/* Component ID definition, used by tools. */
16#ifndef FSL_COMPONENT_ID
17#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections"
18#endif
19
20/*!
21 * @addtogroup inputmux_driver
22 * @{
23 */
24
25/*!
26 * @name Input multiplexing connections
27 * @{
28 */
29
30/*! @brief Periphinmux IDs */
31#define SCT0_INMUX0 0x00U
32#define TIMER0CAPTSEL0 0x20U
33#define TIMER1CAPTSEL0 0x40U
34#define TIMER2CAPTSEL0 0x60U
35#define PINTSEL_PMUX_ID 0xC0U
36#define PINTSEL0 0xC0U
37#define DMA0_ITRIG_INMUX0 0xE0U
38#define DMA0_OTRIG_INMUX0 0x160U
39#define FREQMEAS_REF_REG 0x180U
40#define FREQMEAS_TARGET_REG 0x184U
41#define TIMER3CAPTSEL0 0x1A0U
42#define TIMER4CAPTSEL0 0x1C0U
43#define PINTSECSEL0 0x1E0U
44#define DMA1_ITRIG_INMUX0 0x200U
45#define DMA1_OTRIG_INMUX0 0x240U
46#define DMA0_REQ_ENA_ID 0x740U
47#define DMA1_REQ_ENA_ID 0x760U
48#define DMA0_ITRIG_ENA_ID 0x780U
49#define DMA1_ITRIG_ENA_ID 0x7A0U
50#define ENA_SHIFT 8U
51#define PMUX_SHIFT 20U
52
53/*! @brief INPUTMUX connections type */
54typedef enum _inputmux_connection_t
55{
56 /*!< SCT0 INMUX. */
57 kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_INMUX0 << PMUX_SHIFT),
58 kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_INMUX0 << PMUX_SHIFT),
59 kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_INMUX0 << PMUX_SHIFT),
60 kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_INMUX0 << PMUX_SHIFT),
61 kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_INMUX0 << PMUX_SHIFT),
62 kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_INMUX0 << PMUX_SHIFT),
63 kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_INMUX0 << PMUX_SHIFT),
64 kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_INMUX0 << PMUX_SHIFT),
65 kINPUTMUX_Ctimer0M0ToSct0 = 8U + (SCT0_INMUX0 << PMUX_SHIFT),
66 kINPUTMUX_Ctimer1M0ToSct0 = 9U + (SCT0_INMUX0 << PMUX_SHIFT),
67 kINPUTMUX_Ctimer2M0ToSct0 = 10U + (SCT0_INMUX0 << PMUX_SHIFT),
68 kINPUTMUX_Ctimer3M0ToSct0 = 11U + (SCT0_INMUX0 << PMUX_SHIFT),
69 kINPUTMUX_Ctimer4M0ToSct0 = 12U + (SCT0_INMUX0 << PMUX_SHIFT),
70 kINPUTMUX_AdcIrqToSct0 = 13U + (SCT0_INMUX0 << PMUX_SHIFT),
71 kINPUTMUX_GpiointBmatchToSct0 = 14U + (SCT0_INMUX0 << PMUX_SHIFT),
72 kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_INMUX0 << PMUX_SHIFT),
73 kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_INMUX0 << PMUX_SHIFT),
74 kINPUTMUX_CompOutToSct0 = 17U + (SCT0_INMUX0 << PMUX_SHIFT),
75 kINPUTMUX_I2sSharedSck0ToSct0 = 18U + (SCT0_INMUX0 << PMUX_SHIFT),
76 kINPUTMUX_I2sSharedSck1ToSct0 = 19U + (SCT0_INMUX0 << PMUX_SHIFT),
77 kINPUTMUX_I2sSharedWs0ToSct0 = 20U + (SCT0_INMUX0 << PMUX_SHIFT),
78 kINPUTMUX_I2sSharedWs1ToSct0 = 21U + (SCT0_INMUX0 << PMUX_SHIFT),
79 kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_INMUX0 << PMUX_SHIFT),
80 kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_INMUX0 << PMUX_SHIFT),
81
82 /*!< TIMER0 CAPTSEL. */
83 kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
84 kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
85 kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
86 kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
87 kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
88 kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
89 kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
90 kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
91 kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
92 kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
93 kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
94 kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
95 kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
96 kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
97 kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
98 kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
99 kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
100 kINPUTMUX_CtimerInp17ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
101 kINPUTMUX_CtimerInp18ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
102 kINPUTMUX_CtimerInp19ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
103 kINPUTMUX_Usb0FrameToggleToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
104 kINPUTMUX_Usb1FrameToggleToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
105 kINPUTMUX_CompOutToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
106 kINPUTMUX_I2sSharedWs0ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
107 kINPUTMUX_I2sSharedWs1ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
108
109 /*!< TIMER1 CAPTSEL. */
110 kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
111 kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
112 kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
113 kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
114 kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
115 kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
116 kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
117 kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
118 kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
119 kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
120 kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
121 kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
122 kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
123 kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
124 kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
125 kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
126 kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
127 kINPUTMUX_CtimerInp17ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
128 kINPUTMUX_CtimerInp18ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
129 kINPUTMUX_CtimerInp19ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
130 kINPUTMUX_Usb0FrameToggleToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
131 kINPUTMUX_Usb1FrameToggleToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
132 kINPUTMUX_CompOutToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
133 kINPUTMUX_I2sSharedWs0ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
134 kINPUTMUX_I2sSharedWs1ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
135
136 /*!< TIMER2 CAPTSEL. */
137 kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
138 kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
139 kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
140 kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
141 kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
142 kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
143 kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
144 kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
145 kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
146 kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
147 kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
148 kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
149 kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
150 kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
151 kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
152 kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
153 kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
154 kINPUTMUX_CtimerInp17ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
155 kINPUTMUX_CtimerInp18ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
156 kINPUTMUX_CtimerInp19ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
157 kINPUTMUX_Usb0FrameToggleToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
158 kINPUTMUX_Usb1FrameToggleToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
159 kINPUTMUX_CompOutToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
160 kINPUTMUX_I2sSharedWs0ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
161 kINPUTMUX_I2sSharedWs1ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
162
163 /*!< Pin interrupt select. */
164 kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT),
165 kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT),
166 kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT),
167 kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT),
168 kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT),
169 kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT),
170 kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT),
171 kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT),
172 kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL0 << PMUX_SHIFT),
173 kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL0 << PMUX_SHIFT),
174 kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL0 << PMUX_SHIFT),
175 kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL0 << PMUX_SHIFT),
176 kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT),
177 kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL0 << PMUX_SHIFT),
178 kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL0 << PMUX_SHIFT),
179 kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL0 << PMUX_SHIFT),
180 kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL0 << PMUX_SHIFT),
181 kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL0 << PMUX_SHIFT),
182 kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL0 << PMUX_SHIFT),
183 kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL0 << PMUX_SHIFT),
184 kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL0 << PMUX_SHIFT),
185 kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL0 << PMUX_SHIFT),
186 kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL0 << PMUX_SHIFT),
187 kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL0 << PMUX_SHIFT),
188 kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL0 << PMUX_SHIFT),
189 kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL0 << PMUX_SHIFT),
190 kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL0 << PMUX_SHIFT),
191 kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL0 << PMUX_SHIFT),
192 kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL0 << PMUX_SHIFT),
193 kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT),
194 kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL0 << PMUX_SHIFT),
195 kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL0 << PMUX_SHIFT),
196 kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT),
197 kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT),
198 kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT),
199 kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT),
200 kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT),
201 kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT),
202 kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT),
203 kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT),
204 kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT),
205 kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT),
206 kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT),
207 kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT),
208 kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT),
209 kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL0 << PMUX_SHIFT),
210 kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL0 << PMUX_SHIFT),
211 kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL0 << PMUX_SHIFT),
212 kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL0 << PMUX_SHIFT),
213 kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL0 << PMUX_SHIFT),
214 kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL0 << PMUX_SHIFT),
215 kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL0 << PMUX_SHIFT),
216 kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL0 << PMUX_SHIFT),
217 kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL0 << PMUX_SHIFT),
218 kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL0 << PMUX_SHIFT),
219 kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL0 << PMUX_SHIFT),
220 kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL0 << PMUX_SHIFT),
221 kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL0 << PMUX_SHIFT),
222 kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL0 << PMUX_SHIFT),
223 kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL0 << PMUX_SHIFT),
224 kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL0 << PMUX_SHIFT),
225 kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL0 << PMUX_SHIFT),
226 kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL0 << PMUX_SHIFT),
227 kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT),
228
229 /*!< DMA0 Input trigger. */
230 kINPUTMUX_PinInt0ToDma0 = 0U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
231 kINPUTMUX_PinInt1ToDma0 = 1U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
232 kINPUTMUX_PinInt2ToDma0 = 2U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
233 kINPUTMUX_PinInt3ToDma0 = 3U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
234 kINPUTMUX_Ctimer0M0ToDma0 = 4U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
235 kINPUTMUX_Ctimer0M1ToDma0 = 5U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
236 kINPUTMUX_Ctimer1M0ToDma0 = 6U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
237 kINPUTMUX_Ctimer1M1ToDma0 = 7U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
238 kINPUTMUX_Ctimer2M0ToDma0 = 8U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
239 kINPUTMUX_Ctimer2M1ToDma0 = 9U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
240 kINPUTMUX_Ctimer3M0ToDma0 = 10U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
241 kINPUTMUX_Ctimer3M1ToDma0 = 11U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
242 kINPUTMUX_Ctimer4M0ToDma0 = 12U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
243 kINPUTMUX_Ctimer4M1ToDma0 = 13U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
244 kINPUTMUX_CompOutToDma0 = 14U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
245 kINPUTMUX_Otrig0ToDma0 = 15U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
246 kINPUTMUX_Otrig1ToDma0 = 16U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
247 kINPUTMUX_Otrig2ToDma0 = 17U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
248 kINPUTMUX_Otrig3ToDma0 = 18U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
249 kINPUTMUX_Sct0DmaReq0ToDma0 = 19U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
250 kINPUTMUX_Sct0DmaReq1ToDma0 = 20U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
251 kINPUTMUX_HashDmaRxToDma0 = 21U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
252
253 /*!< DMA0 output trigger. */
254 kINPUTMUX_Dma0Hash0TxTrigoutToTriginChannels = 0U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
255 kINPUTMUX_Dma0HsLspiRxTrigoutToTriginChannels = 2U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
256 kINPUTMUX_Dma0HsLspiTxTrigoutToTriginChannels = 3U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
257 kINPUTMUX_Dma0Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
258 kINPUTMUX_Dma0Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
259 kINPUTMUX_Dma0Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
260 kINPUTMUX_Dma0Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
261 kINPUTMUX_Dma0Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
262 kINPUTMUX_Dma0Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
263 kINPUTMUX_Dma0Flexcomm2RxTrigoutToTriginChannels = 10U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
264 kINPUTMUX_Dma0Flexcomm2TxTrigoutToTriginChannels = 11U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
265 kINPUTMUX_Dma0Flexcomm4RxTrigoutToTriginChannels = 12U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
266 kINPUTMUX_Dma0Flexcomm4TxTrigoutToTriginChannels = 13U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
267 kINPUTMUX_Dma0Flexcomm5RxTrigoutToTriginChannels = 14U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
268 kINPUTMUX_Dma0Flexcomm5TxTrigoutToTriginChannels = 15U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
269 kINPUTMUX_Dma0Flexcomm6RxTrigoutToTriginChannels = 16U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
270 kINPUTMUX_Dma0Flexcomm6TxTrigoutToTriginChannels = 17U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
271 kINPUTMUX_Dma0Flexcomm7RxTrigoutToTriginChannels = 18U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
272 kINPUTMUX_Dma0Flexcomm7TxTrigoutToTriginChannels = 19U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
273 kINPUTMUX_Dma0Adc0Ch0TrigoutToTriginChannels = 21U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
274 kINPUTMUX_Dma0Adc0Ch1TrigoutToTriginChannels = 22U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
275
276 /*!< Selection for frequency measurement reference clock. */
277 kINPUTMUX_ExternOscToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT),
278 kINPUTMUX_Fro12MhzToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT),
279 kINPUTMUX_Fro96MhzToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT),
280 kINPUTMUX_WdtOscToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT),
281 kINPUTMUX_32KhzOscToFreqmeasRef = 4u + (FREQMEAS_REF_REG << PMUX_SHIFT),
282 kINPUTMUX_MainClkToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT),
283 kINPUTMUX_FreqmeGpioClk_aRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT),
284 kINPUTMUX_FreqmeGpioClk_bRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT),
285
286 /*!< Selection for frequency measurement target clock. */
287 kINPUTMUX_ExternOscToFreqmeasTarget = 0U + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
288 kINPUTMUX_Fro12MhzToFreqmeasTarget = 1u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
289 kINPUTMUX_Fro96MhzToFreqmeasTarget = 2u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
290 kINPUTMUX_WdtOscToFreqmeasTarget = 3u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
291 kINPUTMUX_32KhzOscToFreqmeasTarget = 4u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
292 kINPUTMUX_MainClkToFreqmeasTarget = 5u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
293 kINPUTMUX_FreqmeGpioClk_aTarget = 6u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
294 kINPUTMUX_FreqmeGpioClk_bTarget = 7u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
295
296 /*!< TIMER3 CAPTSEL. */
297 kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
298 kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
299 kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
300 kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
301 kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
302 kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
303 kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
304 kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
305 kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
306 kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
307 kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
308 kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
309 kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
310 kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
311 kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
312 kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
313 kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
314 kINPUTMUX_CtimerInp17ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
315 kINPUTMUX_CtimerInp18ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
316 kINPUTMUX_CtimerInp19ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
317 kINPUTMUX_Usb0FrameToggleToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
318 kINPUTMUX_Usb1FrameToggleToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
319 kINPUTMUX_CompOutToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
320 kINPUTMUX_I2sSharedWs0ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
321 kINPUTMUX_I2sSharedWs1ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
322
323 /*!< Timer4 CAPTSEL. */
324 kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
325 kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
326 kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
327 kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
328 kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
329 kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
330 kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
331 kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
332 kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
333 kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
334 kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
335 kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
336 kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
337 kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
338 kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
339 kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
340 kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
341 kINPUTMUX_CtimerInp17ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
342 kINPUTMUX_CtimerInp18ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
343 kINPUTMUX_CtimerInp19ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
344 kINPUTMUX_Usb0FrameToggleToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
345 kINPUTMUX_Usb1FrameToggleToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
346 kINPUTMUX_CompOutToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
347 kINPUTMUX_I2sSharedWs0ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
348 kINPUTMUX_I2sSharedWs1ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
349
350 /*Pin interrupt secure select */
351 kINPUTMUX_GpioPort0Pin0ToPintSecsel = 0U + (PINTSECSEL0 << PMUX_SHIFT),
352 kINPUTMUX_GpioPort0Pin1ToPintSecsel = 1U + (PINTSECSEL0 << PMUX_SHIFT),
353 kINPUTMUX_GpioPort0Pin2ToPintSecsel = 2U + (PINTSECSEL0 << PMUX_SHIFT),
354 kINPUTMUX_GpioPort0Pin3ToPintSecsel = 3U + (PINTSECSEL0 << PMUX_SHIFT),
355 kINPUTMUX_GpioPort0Pin4ToPintSecsel = 4U + (PINTSECSEL0 << PMUX_SHIFT),
356 kINPUTMUX_GpioPort0Pin5ToPintSecsel = 5U + (PINTSECSEL0 << PMUX_SHIFT),
357 kINPUTMUX_GpioPort0Pin6ToPintSecsel = 6U + (PINTSECSEL0 << PMUX_SHIFT),
358 kINPUTMUX_GpioPort0Pin7ToPintSecsel = 7U + (PINTSECSEL0 << PMUX_SHIFT),
359 kINPUTMUX_GpioPort0Pin8ToPintSecsel = 8U + (PINTSECSEL0 << PMUX_SHIFT),
360 kINPUTMUX_GpioPort0Pin9ToPintSecsel = 9U + (PINTSECSEL0 << PMUX_SHIFT),
361 kINPUTMUX_GpioPort0Pin10ToPintSecsel = 10U + (PINTSECSEL0 << PMUX_SHIFT),
362 kINPUTMUX_GpioPort0Pin11ToPintSecsel = 11U + (PINTSECSEL0 << PMUX_SHIFT),
363 kINPUTMUX_GpioPort0Pin12ToPintSecsel = 12U + (PINTSECSEL0 << PMUX_SHIFT),
364 kINPUTMUX_GpioPort0Pin13ToPintSecsel = 13U + (PINTSECSEL0 << PMUX_SHIFT),
365 kINPUTMUX_GpioPort0Pin14ToPintSecsel = 14U + (PINTSECSEL0 << PMUX_SHIFT),
366 kINPUTMUX_GpioPort0Pin15ToPintSecsel = 15U + (PINTSECSEL0 << PMUX_SHIFT),
367 kINPUTMUX_GpioPort0Pin16ToPintSecsel = 16U + (PINTSECSEL0 << PMUX_SHIFT),
368 kINPUTMUX_GpioPort0Pin17ToPintSecsel = 17U + (PINTSECSEL0 << PMUX_SHIFT),
369 kINPUTMUX_GpioPort0Pin18ToPintSecsel = 18U + (PINTSECSEL0 << PMUX_SHIFT),
370 kINPUTMUX_GpioPort0Pin19ToPintSecsel = 19U + (PINTSECSEL0 << PMUX_SHIFT),
371 kINPUTMUX_GpioPort0Pin20ToPintSecsel = 20U + (PINTSECSEL0 << PMUX_SHIFT),
372 kINPUTMUX_GpioPort0Pin21ToPintSecsel = 21U + (PINTSECSEL0 << PMUX_SHIFT),
373 kINPUTMUX_GpioPort0Pin22ToPintSecsel = 22U + (PINTSECSEL0 << PMUX_SHIFT),
374 kINPUTMUX_GpioPort0Pin23ToPintSecsel = 23U + (PINTSECSEL0 << PMUX_SHIFT),
375 kINPUTMUX_GpioPort0Pin24ToPintSecsel = 24U + (PINTSECSEL0 << PMUX_SHIFT),
376 kINPUTMUX_GpioPort0Pin25ToPintSecsel = 25U + (PINTSECSEL0 << PMUX_SHIFT),
377 kINPUTMUX_GpioPort0Pin26ToPintSecsel = 26U + (PINTSECSEL0 << PMUX_SHIFT),
378 kINPUTMUX_GpioPort0Pin27ToPintSecsel = 27U + (PINTSECSEL0 << PMUX_SHIFT),
379 kINPUTMUX_GpioPort0Pin28ToPintSecsel = 28U + (PINTSECSEL0 << PMUX_SHIFT),
380 kINPUTMUX_GpioPort0Pin29ToPintSecsel = 29U + (PINTSECSEL0 << PMUX_SHIFT),
381 kINPUTMUX_GpioPort0Pin30ToPintSecsel = 30U + (PINTSECSEL0 << PMUX_SHIFT),
382 kINPUTMUX_GpioPort0Pin31ToPintSecsel = 31U + (PINTSECSEL0 << PMUX_SHIFT),
383
384 /*!< DMA1 Input trigger. */
385 kINPUTMUX_PinInt0ToDma1 = 0U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
386 kINPUTMUX_PinInt1ToDma1 = 1U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
387 kINPUTMUX_PinInt2ToDma1 = 2U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
388 kINPUTMUX_PinInt3ToDma1 = 3U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
389 kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
390 kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
391 kINPUTMUX_Ctimer2M0ToDma1 = 6U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
392 kINPUTMUX_Ctimer4M0ToDma1 = 7U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
393 kINPUTMUX_Otrig0ToDma1 = 8U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
394 kINPUTMUX_Otrig1ToDma1 = 9U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
395 kINPUTMUX_Otrig2ToDma1 = 10U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
396 kINPUTMUX_Otrig3ToDma1 = 11U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
397 kINPUTMUX_Sct0DmaReq0ToDma1 = 12U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
398 kINPUTMUX_Sct0DmaReq1ToDma1 = 13U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
399 kINPUTMUX_HashDmaRxToDma1 = 14U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
400
401 /*!< DMA1 output trigger. */
402 kINPUTMUX_Dma1Hash0TxTrigoutToTriginChannels = 0U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
403 kINPUTMUX_Dma1HsLspiRxTrigoutToTriginChannels = 2U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
404 kINPUTMUX_Dma1HsLspiTxTrigoutToTriginChannels = 3U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
405 kINPUTMUX_Dma1Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
406 kINPUTMUX_Dma1Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
407 kINPUTMUX_Dma1Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
408 kINPUTMUX_Dma1Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
409 kINPUTMUX_Dma1Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
410 kINPUTMUX_Dma1Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
411} inputmux_connection_t;
412
413/*! @brief INPUTMUX signal enable/disable type */
414typedef enum _inputmux_signal_t
415{
416 /*!< DMA0 REQ signal. */
417 kINPUTMUX_HashCryptToDmac0Ch0RequestEna = 0U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
418 kINPUTMUX_Flexcomm8RxToDmac0Ch2RequestEna = 2U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
419 kINPUTMUX_Flexcomm8TxToDmac0Ch3RequestEna = 3U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
420 kINPUTMUX_Flexcomm0RxToDmac0Ch4RequestEna = 4U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
421 kINPUTMUX_Flexcomm0TxToDmac0Ch5RequestEna = 5U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
422 kINPUTMUX_Flexcomm1RxToDmac0Ch6RequestEna = 6U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
423 kINPUTMUX_Flexcomm1TxToDmac0Ch7RequestEna = 7U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
424 kINPUTMUX_Flexcomm3RxToDmac0Ch8RequestEna = 8U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
425 kINPUTMUX_Flexcomm3TxToDmac0Ch9RequestEna = 9U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
426 kINPUTMUX_Flexcomm2RxToDmac0Ch10RequestEna = 10U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
427 kINPUTMUX_Flexcomm2TxToDmac0Ch11RequestEna = 11U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
428 kINPUTMUX_Flexcomm4RxToDmac0Ch12RequestEna = 12U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
429 kINPUTMUX_Flexcomm4TxToDmac0Ch13RequestEna = 13U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
430 kINPUTMUX_Flexcomm5RxToDmac0Ch14RequestEna = 14U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
431 kINPUTMUX_Flexcomm5TxToDmac0Ch15RequestEna = 15U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
432 kINPUTMUX_Flexcomm6RxToDmac0Ch16RequestEna = 16U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
433 kINPUTMUX_Flexcomm6TxToDmac0Ch17RequestEna = 17U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
434 kINPUTMUX_Flexcomm7RxToDmac0Ch18RequestEna = 18U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
435 kINPUTMUX_Flexcomm7TxToDmac0Ch19RequestEna = 19U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
436 kINPUTMUX_Adc0FIFO0ToDmac0Ch21RequestEna = 21U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
437 kINPUTMUX_Adc0FIFO1ToDmac0Ch22RequestEna = 22U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
438
439 /*!< DMA1 REQ signal. */
440 kINPUTMUX_HashCryptToDmac1Ch0RequestEna = 0U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
441 kINPUTMUX_Flexcomm8RxToDmac1Ch2RequestEna = 2U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
442 kINPUTMUX_Flexcomm8TxToDmac1Ch3RequestEna = 3U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
443 kINPUTMUX_Flexcomm0RxToDmac1Ch4RequestEna = 4U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
444 kINPUTMUX_Flexcomm0TxToDmac1Ch5RequestEna = 5U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
445 kINPUTMUX_Flexcomm1RxToDmac1Ch6RequestEna = 6U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
446 kINPUTMUX_Flexcomm1TxToDmac1Ch7RequestEna = 7U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
447 kINPUTMUX_Flexcomm3RxToDmac1Ch8RequestEna = 8U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
448 kINPUTMUX_Flexcomm3TxToDmac1Ch9RequestEna = 9U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
449
450 /*!< DMA0 input trigger source enable. */
451 kINPUTMUX_Dmac0InputTriggerPint0Ena = 0U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
452 kINPUTMUX_Dmac0InputTriggerPint1Ena = 1U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
453 kINPUTMUX_Dmac0InputTriggerPint2Ena = 2U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
454 kINPUTMUX_Dmac0InputTriggerPint3Ena = 3U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
455 kINPUTMUX_Dmac0InputTriggerCtimer0M0Ena = 4U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
456 kINPUTMUX_Dmac0InputTriggerCtimer0M1Ena = 5U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
457 kINPUTMUX_Dmac0InputTriggerCtimer1M0Ena = 6U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
458 kINPUTMUX_Dmac0InputTriggerCtimer1M1Ena = 7U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
459 kINPUTMUX_Dmac0InputTriggerCtimer2M0Ena = 8U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
460 kINPUTMUX_Dmac0InputTriggerCtimer2M1Ena = 9U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
461 kINPUTMUX_Dmac0InputTriggerCtimer3M0Ena = 10U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
462 kINPUTMUX_Dmac0InputTriggerCtimer3M1Ena = 11U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
463 kINPUTMUX_Dmac0InputTriggerCtimer4M0Ena = 12U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
464 kINPUTMUX_Dmac0InputTriggerCtimer4M1Ena = 13U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
465 kINPUTMUX_Dmac0InputTriggerCompOutEna = 14U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
466 kINPUTMUX_Dmac0InputTriggerDma0Out0Ena = 15U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
467 kINPUTMUX_Dmac0InputTriggerDma0Out1Ena = 16U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
468 kINPUTMUX_Dmac0InputTriggerDma0Out2Ena = 17U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
469 kINPUTMUX_Dmac0InputTriggerDma0Out3Ena = 18U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
470 kINPUTMUX_Dmac0InputTriggerSctDmac0Ena = 19U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
471 kINPUTMUX_Dmac0InputTriggerSctDmac1Ena = 20U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
472 kINPUTMUX_Dmac0InputTriggerHashOutEna = 21U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
473
474 /*!< DMA1 input trigger source enable. */
475 kINPUTMUX_Dmac1InputTriggerPint0Ena = 0U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
476 kINPUTMUX_Dmac1InputTriggerPint1Ena = 1U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
477 kINPUTMUX_Dmac1InputTriggerPint2Ena = 2U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
478 kINPUTMUX_Dmac1InputTriggerPint3Ena = 3U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
479 kINPUTMUX_Dmac1InputTriggerCtimer0M0Ena = 4U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
480 kINPUTMUX_Dmac1InputTriggerCtimer0M1Ena = 5U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
481 kINPUTMUX_Dmac1InputTriggerCtimer2M0Ena = 6U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
482 kINPUTMUX_Dmac1InputTriggerCtimer4M0Ena = 7U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
483 kINPUTMUX_Dmac1InputTriggerDma1Out0Ena = 8U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
484 kINPUTMUX_Dmac1InputTriggerDma1Out1Ena = 9U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
485 kINPUTMUX_Dmac1InputTriggerDma1Out2Ena = 10U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
486 kINPUTMUX_Dmac1InputTriggerDma1Out3Ena = 11U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
487 kINPUTMUX_Dmac1InputTriggerSctDmac0Ena = 12U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
488 kINPUTMUX_Dmac1InputTriggerSctDmac1Ena = 13U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
489 kINPUTMUX_Dmac1InputTriggerHashOutEna = 14U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
490} inputmux_signal_t;
491
492/*@}*/
493
494/*@}*/
495
496#endif /* _FSL_INPUTMUX_CONNECTIONS_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 22:57:08 +0100