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1/*
2** ###################################################################
3** Processors: LPC55S14JBD100
4** LPC55S14JBD64
5**
6** Compilers: GNU C Compiler
7** IAR ANSI C/C++ Compiler for ARM
8** Keil ARM C/C++ Compiler
9** MCUXpresso Compiler
10**
11** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019
12** Version: rev. 1.1, 2019-12-03
13** Build: b200311
14**
15** Abstract:
16** CMSIS Peripheral Access Layer for LPC55S14
17**
18** Copyright 1997-2016 Freescale Semiconductor, Inc.
19** Copyright 2016-2020 NXP
20** All rights reserved.
21**
22** SPDX-License-Identifier: BSD-3-Clause
23**
24** http: www.nxp.com
25** mail: [email protected]
26**
27** Revisions:
28** - rev. 1.0 (2018-08-22)
29** Initial version based on v0.2UM
30** - rev. 1.1 (2019-12-03)
31** Initial version based on v0.6UM
32**
33** ###################################################################
34*/
35
36/*!
37 * @file LPC55S14.h
38 * @version 1.1
39 * @date 2019-12-03
40 * @brief CMSIS Peripheral Access Layer for LPC55S14
41 *
42 * CMSIS Peripheral Access Layer for LPC55S14
43 */
44
45#ifndef _LPC55S14_H_
46#define _LPC55S14_H_ /**< Symbol preventing repeated inclusion */
47
48/** Memory map major version (memory maps with equal major version number are
49 * compatible) */
50#define MCU_MEM_MAP_VERSION 0x0100U
51/** Memory map minor version */
52#define MCU_MEM_MAP_VERSION_MINOR 0x0001U
53
54
55/* ----------------------------------------------------------------------------
56 -- Interrupt vector numbers
57 ---------------------------------------------------------------------------- */
58
59/*!
60 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
61 * @{
62 */
63
64/** Interrupt Number Definitions */
65#define NUMBER_OF_INT_VECTORS 77 /**< Number of interrupts in the Vector table */
66
67typedef enum IRQn {
68 /* Auxiliary constants */
69 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
70
71 /* Core interrupts */
72 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
73 HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */
74 MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */
75 BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */
76 UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */
77 SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */
78 SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */
79 DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */
80 PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */
81 SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */
82
83 /* Device specific interrupts */
84 WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */
85 DMA0_IRQn = 1, /**< DMA0 controller */
86 GINT0_IRQn = 2, /**< GPIO group 0 */
87 GINT1_IRQn = 3, /**< GPIO group 1 */
88 PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */
89 PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */
90 PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */
91 PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */
92 UTICK0_IRQn = 8, /**< Micro-tick Timer */
93 MRT0_IRQn = 9, /**< Multi-rate timer */
94 CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
95 CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
96 SCT0_IRQn = 12, /**< SCTimer/PWM */
97 CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
98 FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
99 FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
100 FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
101 FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
102 FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
103 FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
104 FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
105 FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
106 ADC0_IRQn = 22, /**< ADC0 */
107 Reserved39_IRQn = 23, /**< Reserved interrupt */
108 ACMP_IRQn = 24, /**< ACMP interrupts */
109 Reserved41_IRQn = 25, /**< Reserved interrupt */
110 Reserved42_IRQn = 26, /**< Reserved interrupt */
111 USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */
112 USB0_IRQn = 28, /**< USB device */
113 RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */
114 Reserved46_IRQn = 30, /**< Reserved interrupt */
115 Reserved47_IRQn = 31, /**< Reserved interrupt */
116 PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */
117 PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */
118 PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */
119 PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */
120 CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */
121 CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */
122 OS_EVENT_IRQn = 38, /**< OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */
123 Reserved55_IRQn = 39, /**< Reserved interrupt */
124 Reserved56_IRQn = 40, /**< Reserved interrupt */
125 Reserved57_IRQn = 41, /**< Reserved interrupt */
126 Reserved58_IRQn = 42, /**< Reserved interrupt */
127 CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */
128 CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */
129 Reserved61_IRQn = 45, /**< Reserved interrupt */
130 USB1_PHY_IRQn = 46, /**< USB1_PHY */
131 USB1_IRQn = 47, /**< USB1 interrupt */
132 USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */
133 SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */
134 SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */
135 SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */
136 PLU_IRQn = 52, /**< PLU interrupt */
137 SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */
138 HASHCRYPT_IRQn = 54, /**< SHA interrupt */
139 CASER_IRQn = 55, /**< CASPER interrupt */
140 PUF_IRQn = 56, /**< PUF interrupt */
141 Reserved73_IRQn = 57, /**< Reserved interrupt */
142 DMA1_IRQn = 58, /**< DMA1 interrupt */
143 FLEXCOMM8_IRQn = 59, /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */
144 CodeWDG_IRQn = 60 /**< CodeWDG interrupt */
145} IRQn_Type;
146
147/*!
148 * @}
149 */ /* end of group Interrupt_vector_numbers */
150
151
152/* ----------------------------------------------------------------------------
153 -- Cortex M33 Core Configuration
154 ---------------------------------------------------------------------------- */
155
156/*!
157 * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration
158 * @{
159 */
160
161#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
162#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
163#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
164#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
165#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */
166#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */
167
168#include "core_cm33.h" /* Core Peripheral Access Layer */
169#include "system_LPC55S14.h" /* Device specific configuration file */
170
171/*!
172 * @}
173 */ /* end of group Cortex_Core_Configuration */
174
175
176/* ----------------------------------------------------------------------------
177 -- Mapping Information
178 ---------------------------------------------------------------------------- */
179
180/*!
181 * @addtogroup Mapping_Information Mapping Information
182 * @{
183 */
184
185/** Mapping Information */
186/*!
187 * @addtogroup dma_request
188 * @{
189 */
190
191/*******************************************************************************
192 * Definitions
193 ******************************************************************************/
194
195/*!
196 * @brief Structure for the DMA hardware request
197 *
198 * Defines the structure for the DMA hardware request collections. The user can configure the
199 * hardware request to trigger the DMA transfer accordingly. The index
200 * of the hardware request varies according to the to SoC.
201 */
202typedef enum _dma_request_source
203{
204 kDma0RequestHashCrypt = 0U, /**< HashCrypt */
205 kDma1RequestHashCrypt = 0U, /**< HashCrypt */
206 kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */
207 kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */
208 kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */
209 kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */
210 kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */
211 kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */
212 kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */
213 kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */
214 kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */
215 kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */
216 kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */
217 kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */
218 kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */
219 kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */
220 kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */
221 kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */
222 kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */
223 kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */
224 kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */
225 kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */
226 kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */
227 kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */
228 kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */
229 kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */
230 kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */
231 kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */
232 kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */
233 kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */
234 kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */
235 kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */
236 kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */
237} dma_request_source_t;
238
239/* @} */
240
241
242/*!
243 * @}
244 */ /* end of group Mapping_Information */
245
246
247/* ----------------------------------------------------------------------------
248 -- Device Peripheral Access Layer
249 ---------------------------------------------------------------------------- */
250
251/*!
252 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
253 * @{
254 */
255
256
257/*
258** Start of section using anonymous unions
259*/
260
261#if defined(__ARMCC_VERSION)
262 #if (__ARMCC_VERSION >= 6010050)
263 #pragma clang diagnostic push
264 #else
265 #pragma push
266 #pragma anon_unions
267 #endif
268#elif defined(__GNUC__)
269 /* anonymous unions are enabled by default */
270#elif defined(__IAR_SYSTEMS_ICC__)
271 #pragma language=extended
272#else
273 #error Not supported compiler type
274#endif
275
276/* ----------------------------------------------------------------------------
277 -- ADC Peripheral Access Layer
278 ---------------------------------------------------------------------------- */
279
280/*!
281 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
282 * @{
283 */
284
285/** ADC - Register Layout Typedef */
286typedef struct {
287 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
288 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
289 uint8_t RESERVED_0[8];
290 __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */
291 __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */
292 __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */
293 __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */
294 __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */
295 __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */
296 uint8_t RESERVED_1[12];
297 __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
298 __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */
299 uint8_t RESERVED_2[4];
300 __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */
301 uint8_t RESERVED_3[92];
302 __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */
303 __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */
304 uint8_t RESERVED_4[8];
305 __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */
306 __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */
307 struct { /* offset: 0x100, array step: 0x8 */
308 __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
309 __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
310 } CMD[15];
311 uint8_t RESERVED_5[136];
312 __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
313 uint8_t RESERVED_6[240];
314 __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */
315 uint8_t RESERVED_7[248];
316 __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */
317 uint8_t RESERVED_8[124];
318 __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */
319} ADC_Type;
320
321/* ----------------------------------------------------------------------------
322 -- ADC Register Masks
323 ---------------------------------------------------------------------------- */
324
325/*!
326 * @addtogroup ADC_Register_Masks ADC Register Masks
327 * @{
328 */
329
330/*! @name VERID - Version ID Register */
331/*! @{ */
332#define ADC_VERID_RES_MASK (0x1U)
333#define ADC_VERID_RES_SHIFT (0U)
334/*! RES - Resolution
335 * 0b0..Up to 13-bit differential/12-bit single ended resolution supported.
336 * 0b1..Up to 16-bit differential/16-bit single ended resolution supported.
337 */
338#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
339#define ADC_VERID_DIFFEN_MASK (0x2U)
340#define ADC_VERID_DIFFEN_SHIFT (1U)
341/*! DIFFEN - Differential Supported
342 * 0b0..Differential operation not supported.
343 * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented.
344 */
345#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
346#define ADC_VERID_MVI_MASK (0x8U)
347#define ADC_VERID_MVI_SHIFT (3U)
348/*! MVI - Multi Vref Implemented
349 * 0b0..Single voltage reference high (VREFH) input supported.
350 * 0b1..Multiple voltage reference high (VREFH) inputs supported.
351 */
352#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
353#define ADC_VERID_CSW_MASK (0x70U)
354#define ADC_VERID_CSW_SHIFT (4U)
355/*! CSW - Channel Scale Width
356 * 0b000..Channel scaling not supported.
357 * 0b001..Channel scaling supported. 1-bit CSCALE control field.
358 * 0b110..Channel scaling supported. 6-bit CSCALE control field.
359 */
360#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
361#define ADC_VERID_VR1RNGI_MASK (0x100U)
362#define ADC_VERID_VR1RNGI_SHIFT (8U)
363/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
364 * 0b0..Range control not required. CFG[VREF1RNG] is not implemented.
365 * 0b1..Range control required. CFG[VREF1RNG] is implemented.
366 */
367#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
368#define ADC_VERID_IADCKI_MASK (0x200U)
369#define ADC_VERID_IADCKI_SHIFT (9U)
370/*! IADCKI - Internal ADC Clock implemented
371 * 0b0..Internal clock source not implemented.
372 * 0b1..Internal clock source (and CFG[ADCKEN]) implemented.
373 */
374#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
375#define ADC_VERID_CALOFSI_MASK (0x400U)
376#define ADC_VERID_CALOFSI_SHIFT (10U)
377/*! CALOFSI - Calibration Function Implemented
378 * 0b0..Calibration Not Implemented.
379 * 0b1..Calibration Implemented.
380 */
381#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
382#define ADC_VERID_NUM_SEC_MASK (0x800U)
383#define ADC_VERID_NUM_SEC_SHIFT (11U)
384/*! NUM_SEC - Number of Single Ended Outputs Supported
385 * 0b0..This design supports one single ended conversion at a time.
386 * 0b1..This design supports two simultanious single ended conversions.
387 */
388#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK)
389#define ADC_VERID_NUM_FIFO_MASK (0x7000U)
390#define ADC_VERID_NUM_FIFO_SHIFT (12U)
391/*! NUM_FIFO - Number of FIFOs
392 * 0b000..N/A
393 * 0b001..This design supports one result FIFO.
394 * 0b010..This design supports two result FIFOs.
395 * 0b011..This design supports three result FIFOs.
396 * 0b100..This design supports four result FIFOs.
397 */
398#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK)
399#define ADC_VERID_MINOR_MASK (0xFF0000U)
400#define ADC_VERID_MINOR_SHIFT (16U)
401/*! MINOR - Minor Version Number
402 */
403#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
404#define ADC_VERID_MAJOR_MASK (0xFF000000U)
405#define ADC_VERID_MAJOR_SHIFT (24U)
406/*! MAJOR - Major Version Number
407 */
408#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
409/*! @} */
410
411/*! @name PARAM - Parameter Register */
412/*! @{ */
413#define ADC_PARAM_TRIG_NUM_MASK (0xFFU)
414#define ADC_PARAM_TRIG_NUM_SHIFT (0U)
415/*! TRIG_NUM - Trigger Number
416 */
417#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
418#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U)
419#define ADC_PARAM_FIFOSIZE_SHIFT (8U)
420/*! FIFOSIZE - Result FIFO Depth
421 * 0b00000001..Result FIFO depth = 1 dataword.
422 * 0b00000100..Result FIFO depth = 4 datawords.
423 * 0b00001000..Result FIFO depth = 8 datawords.
424 * 0b00010000..Result FIFO depth = 16 datawords.
425 * 0b00100000..Result FIFO depth = 32 datawords.
426 * 0b01000000..Result FIFO depth = 64 datawords.
427 */
428#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
429#define ADC_PARAM_CV_NUM_MASK (0xFF0000U)
430#define ADC_PARAM_CV_NUM_SHIFT (16U)
431/*! CV_NUM - Compare Value Number
432 */
433#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
434#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U)
435#define ADC_PARAM_CMD_NUM_SHIFT (24U)
436/*! CMD_NUM - Command Buffer Number
437 */
438#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
439/*! @} */
440
441/*! @name CTRL - ADC Control Register */
442/*! @{ */
443#define ADC_CTRL_ADCEN_MASK (0x1U)
444#define ADC_CTRL_ADCEN_SHIFT (0U)
445/*! ADCEN - ADC Enable
446 * 0b0..ADC is disabled.
447 * 0b1..ADC is enabled.
448 */
449#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
450#define ADC_CTRL_RST_MASK (0x2U)
451#define ADC_CTRL_RST_SHIFT (1U)
452/*! RST - Software Reset
453 * 0b0..ADC logic is not reset.
454 * 0b1..ADC logic is reset.
455 */
456#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
457#define ADC_CTRL_DOZEN_MASK (0x4U)
458#define ADC_CTRL_DOZEN_SHIFT (2U)
459/*! DOZEN - Doze Enable
460 * 0b0..ADC is enabled in Doze mode.
461 * 0b1..ADC is disabled in Doze mode.
462 */
463#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
464#define ADC_CTRL_CAL_REQ_MASK (0x8U)
465#define ADC_CTRL_CAL_REQ_SHIFT (3U)
466/*! CAL_REQ - Auto-Calibration Request
467 * 0b0..No request for auto-calibration has been made.
468 * 0b1..A request for auto-calibration has been made
469 */
470#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK)
471#define ADC_CTRL_CALOFS_MASK (0x10U)
472#define ADC_CTRL_CALOFS_SHIFT (4U)
473/*! CALOFS - Configure for offset calibration function
474 * 0b0..Calibration function disabled
475 * 0b1..Request for offset calibration function
476 */
477#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK)
478#define ADC_CTRL_RSTFIFO0_MASK (0x100U)
479#define ADC_CTRL_RSTFIFO0_SHIFT (8U)
480/*! RSTFIFO0 - Reset FIFO 0
481 * 0b0..No effect.
482 * 0b1..FIFO 0 is reset.
483 */
484#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK)
485#define ADC_CTRL_RSTFIFO1_MASK (0x200U)
486#define ADC_CTRL_RSTFIFO1_SHIFT (9U)
487/*! RSTFIFO1 - Reset FIFO 1
488 * 0b0..No effect.
489 * 0b1..FIFO 1 is reset.
490 */
491#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK)
492#define ADC_CTRL_CAL_AVGS_MASK (0x70000U)
493#define ADC_CTRL_CAL_AVGS_SHIFT (16U)
494/*! CAL_AVGS - Auto-Calibration Averages
495 * 0b000..Single conversion.
496 * 0b001..2 conversions averaged.
497 * 0b010..4 conversions averaged.
498 * 0b011..8 conversions averaged.
499 * 0b100..16 conversions averaged.
500 * 0b101..32 conversions averaged.
501 * 0b110..64 conversions averaged.
502 * 0b111..128 conversions averaged.
503 */
504#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK)
505/*! @} */
506
507/*! @name STAT - ADC Status Register */
508/*! @{ */
509#define ADC_STAT_RDY0_MASK (0x1U)
510#define ADC_STAT_RDY0_SHIFT (0U)
511/*! RDY0 - Result FIFO 0 Ready Flag
512 * 0b0..Result FIFO 0 data level not above watermark level.
513 * 0b1..Result FIFO 0 holding data above watermark level.
514 */
515#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK)
516#define ADC_STAT_FOF0_MASK (0x2U)
517#define ADC_STAT_FOF0_SHIFT (1U)
518/*! FOF0 - Result FIFO 0 Overflow Flag
519 * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared.
520 * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.
521 */
522#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK)
523#define ADC_STAT_RDY1_MASK (0x4U)
524#define ADC_STAT_RDY1_SHIFT (2U)
525/*! RDY1 - Result FIFO1 Ready Flag
526 * 0b0..Result FIFO1 data level not above watermark level.
527 * 0b1..Result FIFO1 holding data above watermark level.
528 */
529#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK)
530#define ADC_STAT_FOF1_MASK (0x8U)
531#define ADC_STAT_FOF1_SHIFT (3U)
532/*! FOF1 - Result FIFO1 Overflow Flag
533 * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
534 * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
535 */
536#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK)
537#define ADC_STAT_TEXC_INT_MASK (0x100U)
538#define ADC_STAT_TEXC_INT_SHIFT (8U)
539/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception
540 * 0b0..No trigger exceptions have occurred.
541 * 0b1..A trigger exception has occurred and is pending acknowledgement.
542 */
543#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK)
544#define ADC_STAT_TCOMP_INT_MASK (0x200U)
545#define ADC_STAT_TCOMP_INT_SHIFT (9U)
546/*! TCOMP_INT - Interrupt Flag For Trigger Completion
547 * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion.
548 * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO.
549 */
550#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK)
551#define ADC_STAT_CAL_RDY_MASK (0x400U)
552#define ADC_STAT_CAL_RDY_SHIFT (10U)
553/*! CAL_RDY - Calibration Ready
554 * 0b0..Calibration is incomplete or hasn't been ran.
555 * 0b1..The ADC is calibrated.
556 */
557#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK)
558#define ADC_STAT_ADC_ACTIVE_MASK (0x800U)
559#define ADC_STAT_ADC_ACTIVE_SHIFT (11U)
560/*! ADC_ACTIVE - ADC Active
561 * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
562 * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
563 */
564#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
565#define ADC_STAT_TRGACT_MASK (0xF0000U)
566#define ADC_STAT_TRGACT_SHIFT (16U)
567/*! TRGACT - Trigger Active
568 * 0b0000..Command (sequence) associated with Trigger 0 currently being executed.
569 * 0b0001..Command (sequence) associated with Trigger 1 currently being executed.
570 * 0b0010..Command (sequence) associated with Trigger 2 currently being executed.
571 * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed.
572 */
573#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
574#define ADC_STAT_CMDACT_MASK (0xF000000U)
575#define ADC_STAT_CMDACT_SHIFT (24U)
576/*! CMDACT - Command Active
577 * 0b0000..No command is currently in progress.
578 * 0b0001..Command 1 currently being executed.
579 * 0b0010..Command 2 currently being executed.
580 * 0b0011-0b1111..Associated command number is currently being executed.
581 */
582#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
583/*! @} */
584
585/*! @name IE - Interrupt Enable Register */
586/*! @{ */
587#define ADC_IE_FWMIE0_MASK (0x1U)
588#define ADC_IE_FWMIE0_SHIFT (0U)
589/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable
590 * 0b0..FIFO 0 watermark interrupts are not enabled.
591 * 0b1..FIFO 0 watermark interrupts are enabled.
592 */
593#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK)
594#define ADC_IE_FOFIE0_MASK (0x2U)
595#define ADC_IE_FOFIE0_SHIFT (1U)
596/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable
597 * 0b0..FIFO 0 overflow interrupts are not enabled.
598 * 0b1..FIFO 0 overflow interrupts are enabled.
599 */
600#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK)
601#define ADC_IE_FWMIE1_MASK (0x4U)
602#define ADC_IE_FWMIE1_SHIFT (2U)
603/*! FWMIE1 - FIFO1 Watermark Interrupt Enable
604 * 0b0..FIFO1 watermark interrupts are not enabled.
605 * 0b1..FIFO1 watermark interrupts are enabled.
606 */
607#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK)
608#define ADC_IE_FOFIE1_MASK (0x8U)
609#define ADC_IE_FOFIE1_SHIFT (3U)
610/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable
611 * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
612 * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
613 */
614#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK)
615#define ADC_IE_TEXC_IE_MASK (0x100U)
616#define ADC_IE_TEXC_IE_SHIFT (8U)
617/*! TEXC_IE - Trigger Exception Interrupt Enable
618 * 0b0..Trigger exception interrupts are disabled.
619 * 0b1..Trigger exception interrupts are enabled.
620 */
621#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK)
622#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U)
623#define ADC_IE_TCOMP_IE_SHIFT (16U)
624/*! TCOMP_IE - Trigger Completion Interrupt Enable
625 * 0b0000000000000000..Trigger completion interrupts are disabled.
626 * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only.
627 * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only.
628 * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled.
629 * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source.
630 */
631#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK)
632/*! @} */
633
634/*! @name DE - DMA Enable Register */
635/*! @{ */
636#define ADC_DE_FWMDE0_MASK (0x1U)
637#define ADC_DE_FWMDE0_SHIFT (0U)
638/*! FWMDE0 - FIFO 0 Watermark DMA Enable
639 * 0b0..DMA request disabled.
640 * 0b1..DMA request enabled.
641 */
642#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK)
643#define ADC_DE_FWMDE1_MASK (0x2U)
644#define ADC_DE_FWMDE1_SHIFT (1U)
645/*! FWMDE1 - FIFO1 Watermark DMA Enable
646 * 0b0..DMA request disabled.
647 * 0b1..DMA request enabled.
648 */
649#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK)
650/*! @} */
651
652/*! @name CFG - ADC Configuration Register */
653/*! @{ */
654#define ADC_CFG_TPRICTRL_MASK (0x3U)
655#define ADC_CFG_TPRICTRL_SHIFT (0U)
656/*! TPRICTRL - ADC trigger priority control
657 * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted
658 * and the new command specified by the trigger is started.
659 * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after
660 * after completing the current conversion. If averaging is enabled, the averaging loop will be completed.
661 * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced.
662 * 0b10..If a higher priority trigger is received during command processing, the current command will be
663 * completed (averaging, looping, compare) before servicing the higher priority trigger.
664 * 0b11..RESERVED
665 */
666#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
667#define ADC_CFG_PWRSEL_MASK (0x30U)
668#define ADC_CFG_PWRSEL_SHIFT (4U)
669/*! PWRSEL - Power Configuration Select
670 * 0b00..Lowest power setting.
671 * 0b01..Higher power setting than 0b0.
672 * 0b10..Higher power setting than 0b1.
673 * 0b11..Highest power setting.
674 */
675#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
676#define ADC_CFG_REFSEL_MASK (0xC0U)
677#define ADC_CFG_REFSEL_SHIFT (6U)
678/*! REFSEL - Voltage Reference Selection
679 * 0b00..(Default) Option 1 setting.
680 * 0b01..Option 2 setting.
681 * 0b10..Option 3 setting.
682 * 0b11..Reserved
683 */
684#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
685#define ADC_CFG_TRES_MASK (0x100U)
686#define ADC_CFG_TRES_SHIFT (8U)
687/*! TRES - Trigger Resume Enable
688 * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted.
689 * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted.
690 */
691#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK)
692#define ADC_CFG_TCMDRES_MASK (0x200U)
693#define ADC_CFG_TCMDRES_SHIFT (9U)
694/*! TCMDRES - Trigger Command Resume
695 * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted.
696 * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception.
697 */
698#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK)
699#define ADC_CFG_HPT_EXDI_MASK (0x400U)
700#define ADC_CFG_HPT_EXDI_SHIFT (10U)
701/*! HPT_EXDI - High Priority Trigger Exception Disable
702 * 0b0..High priority trigger exceptions are enabled.
703 * 0b1..High priority trigger exceptions are disabled.
704 */
705#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK)
706#define ADC_CFG_PUDLY_MASK (0xFF0000U)
707#define ADC_CFG_PUDLY_SHIFT (16U)
708/*! PUDLY - Power Up Delay
709 */
710#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
711#define ADC_CFG_PWREN_MASK (0x10000000U)
712#define ADC_CFG_PWREN_SHIFT (28U)
713/*! PWREN - ADC Analog Pre-Enable
714 * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
715 * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
716 * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN
717 * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed.
718 * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be
719 * executed.
720 */
721#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
722/*! @} */
723
724/*! @name PAUSE - ADC Pause Register */
725/*! @{ */
726#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU)
727#define ADC_PAUSE_PAUSEDLY_SHIFT (0U)
728/*! PAUSEDLY - Pause Delay
729 */
730#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
731#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U)
732#define ADC_PAUSE_PAUSEEN_SHIFT (31U)
733/*! PAUSEEN - PAUSE Option Enable
734 * 0b0..Pause operation disabled
735 * 0b1..Pause operation enabled
736 */
737#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
738/*! @} */
739
740/*! @name SWTRIG - Software Trigger Register */
741/*! @{ */
742#define ADC_SWTRIG_SWT0_MASK (0x1U)
743#define ADC_SWTRIG_SWT0_SHIFT (0U)
744/*! SWT0 - Software trigger 0 event
745 * 0b0..No trigger 0 event generated.
746 * 0b1..Trigger 0 event generated.
747 */
748#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
749#define ADC_SWTRIG_SWT1_MASK (0x2U)
750#define ADC_SWTRIG_SWT1_SHIFT (1U)
751/*! SWT1 - Software trigger 1 event
752 * 0b0..No trigger 1 event generated.
753 * 0b1..Trigger 1 event generated.
754 */
755#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
756#define ADC_SWTRIG_SWT2_MASK (0x4U)
757#define ADC_SWTRIG_SWT2_SHIFT (2U)
758/*! SWT2 - Software trigger 2 event
759 * 0b0..No trigger 2 event generated.
760 * 0b1..Trigger 2 event generated.
761 */
762#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
763#define ADC_SWTRIG_SWT3_MASK (0x8U)
764#define ADC_SWTRIG_SWT3_SHIFT (3U)
765/*! SWT3 - Software trigger 3 event
766 * 0b0..No trigger 3 event generated.
767 * 0b1..Trigger 3 event generated.
768 */
769#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
770#define ADC_SWTRIG_SWT4_MASK (0x10U)
771#define ADC_SWTRIG_SWT4_SHIFT (4U)
772/*! SWT4 - Software trigger 4 event
773 * 0b0..No trigger 4 event generated.
774 * 0b1..Trigger 4 event generated.
775 */
776#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
777#define ADC_SWTRIG_SWT5_MASK (0x20U)
778#define ADC_SWTRIG_SWT5_SHIFT (5U)
779/*! SWT5 - Software trigger 5 event
780 * 0b0..No trigger 5 event generated.
781 * 0b1..Trigger 5 event generated.
782 */
783#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
784#define ADC_SWTRIG_SWT6_MASK (0x40U)
785#define ADC_SWTRIG_SWT6_SHIFT (6U)
786/*! SWT6 - Software trigger 6 event
787 * 0b0..No trigger 6 event generated.
788 * 0b1..Trigger 6 event generated.
789 */
790#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
791#define ADC_SWTRIG_SWT7_MASK (0x80U)
792#define ADC_SWTRIG_SWT7_SHIFT (7U)
793/*! SWT7 - Software trigger 7 event
794 * 0b0..No trigger 7 event generated.
795 * 0b1..Trigger 7 event generated.
796 */
797#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
798#define ADC_SWTRIG_SWT8_MASK (0x100U)
799#define ADC_SWTRIG_SWT8_SHIFT (8U)
800/*! SWT8 - Software trigger 8 event
801 * 0b0..No trigger 8 event generated.
802 * 0b1..Trigger 8 event generated.
803 */
804#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK)
805#define ADC_SWTRIG_SWT9_MASK (0x200U)
806#define ADC_SWTRIG_SWT9_SHIFT (9U)
807/*! SWT9 - Software trigger 9 event
808 * 0b0..No trigger 9 event generated.
809 * 0b1..Trigger 9 event generated.
810 */
811#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK)
812#define ADC_SWTRIG_SWT10_MASK (0x400U)
813#define ADC_SWTRIG_SWT10_SHIFT (10U)
814/*! SWT10 - Software trigger 10 event
815 * 0b0..No trigger 10 event generated.
816 * 0b1..Trigger 10 event generated.
817 */
818#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK)
819#define ADC_SWTRIG_SWT11_MASK (0x800U)
820#define ADC_SWTRIG_SWT11_SHIFT (11U)
821/*! SWT11 - Software trigger 11 event
822 * 0b0..No trigger 11 event generated.
823 * 0b1..Trigger 11 event generated.
824 */
825#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK)
826#define ADC_SWTRIG_SWT12_MASK (0x1000U)
827#define ADC_SWTRIG_SWT12_SHIFT (12U)
828/*! SWT12 - Software trigger 12 event
829 * 0b0..No trigger 12 event generated.
830 * 0b1..Trigger 12 event generated.
831 */
832#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK)
833#define ADC_SWTRIG_SWT13_MASK (0x2000U)
834#define ADC_SWTRIG_SWT13_SHIFT (13U)
835/*! SWT13 - Software trigger 13 event
836 * 0b0..No trigger 13 event generated.
837 * 0b1..Trigger 13 event generated.
838 */
839#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK)
840#define ADC_SWTRIG_SWT14_MASK (0x4000U)
841#define ADC_SWTRIG_SWT14_SHIFT (14U)
842/*! SWT14 - Software trigger 14 event
843 * 0b0..No trigger 14 event generated.
844 * 0b1..Trigger 14 event generated.
845 */
846#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK)
847#define ADC_SWTRIG_SWT15_MASK (0x8000U)
848#define ADC_SWTRIG_SWT15_SHIFT (15U)
849/*! SWT15 - Software trigger 15 event
850 * 0b0..No trigger 15 event generated.
851 * 0b1..Trigger 15 event generated.
852 */
853#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK)
854/*! @} */
855
856/*! @name TSTAT - Trigger Status Register */
857/*! @{ */
858#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU)
859#define ADC_TSTAT_TEXC_NUM_SHIFT (0U)
860/*! TEXC_NUM - Trigger Exception Number
861 * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1.
862 * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception.
863 * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception.
864 * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception.
865 * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception.
866 */
867#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK)
868#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U)
869#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U)
870/*! TCOMP_FLAG - Trigger Completion Flag
871 * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled.
872 * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts.
873 * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts.
874 * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts.
875 * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts.
876 */
877#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK)
878/*! @} */
879
880/*! @name OFSTRIM - ADC Offset Trim Register */
881/*! @{ */
882#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU)
883#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U)
884/*! OFSTRIM_A - Trim for offset
885 */
886#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK)
887#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U)
888#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U)
889/*! OFSTRIM_B - Trim for offset
890 */
891#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK)
892/*! @} */
893
894/*! @name TCTRL - Trigger Control Register */
895/*! @{ */
896#define ADC_TCTRL_HTEN_MASK (0x1U)
897#define ADC_TCTRL_HTEN_SHIFT (0U)
898/*! HTEN - Trigger enable
899 * 0b0..Hardware trigger source disabled
900 * 0b1..Hardware trigger source enabled
901 */
902#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
903#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U)
904#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U)
905/*! FIFO_SEL_A - SAR Result Destination For Channel A
906 * 0b0..Result written to FIFO 0
907 * 0b1..Result written to FIFO 1
908 */
909#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK)
910#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U)
911#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U)
912/*! FIFO_SEL_B - SAR Result Destination For Channel B
913 * 0b0..Result written to FIFO 0
914 * 0b1..Result written to FIFO 1
915 */
916#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK)
917#define ADC_TCTRL_TPRI_MASK (0xF00U)
918#define ADC_TCTRL_TPRI_SHIFT (8U)
919/*! TPRI - Trigger priority setting
920 * 0b0000..Set to highest priority, Level 1
921 * 0b0001-0b1110..Set to corresponding priority level
922 * 0b1111..Set to lowest priority, Level 16
923 */
924#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
925#define ADC_TCTRL_RSYNC_MASK (0x8000U)
926#define ADC_TCTRL_RSYNC_SHIFT (15U)
927/*! RSYNC - Trigger Resync
928 */
929#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK)
930#define ADC_TCTRL_TDLY_MASK (0xF0000U)
931#define ADC_TCTRL_TDLY_SHIFT (16U)
932/*! TDLY - Trigger delay select
933 */
934#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
935#define ADC_TCTRL_TCMD_MASK (0xF000000U)
936#define ADC_TCTRL_TCMD_SHIFT (24U)
937/*! TCMD - Trigger command select
938 * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
939 * 0b0001..CMD1 is executed
940 * 0b0010-0b1110..Corresponding CMD is executed
941 * 0b1111..CMD15 is executed
942 */
943#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
944/*! @} */
945
946/* The count of ADC_TCTRL */
947#define ADC_TCTRL_COUNT (16U)
948
949/*! @name FCTRL - FIFO Control Register */
950/*! @{ */
951#define ADC_FCTRL_FCOUNT_MASK (0x1FU)
952#define ADC_FCTRL_FCOUNT_SHIFT (0U)
953/*! FCOUNT - Result FIFO counter
954 */
955#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
956#define ADC_FCTRL_FWMARK_MASK (0xF0000U)
957#define ADC_FCTRL_FWMARK_SHIFT (16U)
958/*! FWMARK - Watermark level selection
959 */
960#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
961/*! @} */
962
963/* The count of ADC_FCTRL */
964#define ADC_FCTRL_COUNT (2U)
965
966/*! @name GCC - Gain Calibration Control */
967/*! @{ */
968#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU)
969#define ADC_GCC_GAIN_CAL_SHIFT (0U)
970/*! GAIN_CAL - Gain Calibration Value
971 */
972#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK)
973#define ADC_GCC_RDY_MASK (0x1000000U)
974#define ADC_GCC_RDY_SHIFT (24U)
975/*! RDY - Gain Calibration Value Valid
976 * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written.
977 * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field.
978 */
979#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK)
980/*! @} */
981
982/* The count of ADC_GCC */
983#define ADC_GCC_COUNT (2U)
984
985/*! @name GCR - Gain Calculation Result */
986/*! @{ */
987#define ADC_GCR_GCALR_MASK (0xFFFFU)
988#define ADC_GCR_GCALR_SHIFT (0U)
989/*! GCALR - Gain Calculation Result
990 */
991#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK)
992#define ADC_GCR_RDY_MASK (0x1000000U)
993#define ADC_GCR_RDY_SHIFT (24U)
994/*! RDY - Gain Calculation Ready
995 * 0b0..The gain offset calculation value is invalid.
996 * 0b1..The gain calibration value is valid.
997 */
998#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK)
999/*! @} */
1000
1001/* The count of ADC_GCR */
1002#define ADC_GCR_COUNT (2U)
1003
1004/*! @name CMDL - ADC Command Low Buffer Register */
1005/*! @{ */
1006#define ADC_CMDL_ADCH_MASK (0x1FU)
1007#define ADC_CMDL_ADCH_SHIFT (0U)
1008/*! ADCH - Input channel select
1009 * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
1010 * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
1011 * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
1012 * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
1013 * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
1014 * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
1015 * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
1016 */
1017#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
1018#define ADC_CMDL_CTYPE_MASK (0x60U)
1019#define ADC_CMDL_CTYPE_SHIFT (5U)
1020/*! CTYPE - Conversion Type
1021 * 0b00..Single-Ended Mode. Only A side channel is converted.
1022 * 0b01..Single-Ended Mode. Only B side channel is converted.
1023 * 0b10..Differential Mode. A-B.
1024 * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
1025 */
1026#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK)
1027#define ADC_CMDL_MODE_MASK (0x80U)
1028#define ADC_CMDL_MODE_SHIFT (7U)
1029/*! MODE - Select resolution of conversions
1030 * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
1031 * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
1032 */
1033#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK)
1034/*! @} */
1035
1036/* The count of ADC_CMDL */
1037#define ADC_CMDL_COUNT (15U)
1038
1039/*! @name CMDH - ADC Command High Buffer Register */
1040/*! @{ */
1041#define ADC_CMDH_CMPEN_MASK (0x3U)
1042#define ADC_CMDH_CMPEN_SHIFT (0U)
1043/*! CMPEN - Compare Function Enable
1044 * 0b00..Compare disabled.
1045 * 0b01..Reserved
1046 * 0b10..Compare enabled. Store on true.
1047 * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
1048 */
1049#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
1050#define ADC_CMDH_WAIT_TRIG_MASK (0x4U)
1051#define ADC_CMDH_WAIT_TRIG_SHIFT (2U)
1052/*! WAIT_TRIG - Wait for trigger assertion before execution.
1053 * 0b0..This command will be automatically executed.
1054 * 0b1..The active trigger must be asserted again before executing this command.
1055 */
1056#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK)
1057#define ADC_CMDH_LWI_MASK (0x80U)
1058#define ADC_CMDH_LWI_SHIFT (7U)
1059/*! LWI - Loop with Increment
1060 * 0b0..Auto channel increment disabled
1061 * 0b1..Auto channel increment enabled
1062 */
1063#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
1064#define ADC_CMDH_STS_MASK (0x700U)
1065#define ADC_CMDH_STS_SHIFT (8U)
1066/*! STS - Sample Time Select
1067 * 0b000..Minimum sample time of 3 ADCK cycles.
1068 * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
1069 * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
1070 * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
1071 * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
1072 * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
1073 * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
1074 * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
1075 */
1076#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
1077#define ADC_CMDH_AVGS_MASK (0x7000U)
1078#define ADC_CMDH_AVGS_SHIFT (12U)
1079/*! AVGS - Hardware Average Select
1080 * 0b000..Single conversion.
1081 * 0b001..2 conversions averaged.
1082 * 0b010..4 conversions averaged.
1083 * 0b011..8 conversions averaged.
1084 * 0b100..16 conversions averaged.
1085 * 0b101..32 conversions averaged.
1086 * 0b110..64 conversions averaged.
1087 * 0b111..128 conversions averaged.
1088 */
1089#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
1090#define ADC_CMDH_LOOP_MASK (0xF0000U)
1091#define ADC_CMDH_LOOP_SHIFT (16U)
1092/*! LOOP - Loop Count Select
1093 * 0b0000..Looping not enabled. Command executes 1 time.
1094 * 0b0001..Loop 1 time. Command executes 2 times.
1095 * 0b0010..Loop 2 times. Command executes 3 times.
1096 * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
1097 * 0b1111..Loop 15 times. Command executes 16 times.
1098 */
1099#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
1100#define ADC_CMDH_NEXT_MASK (0xF000000U)
1101#define ADC_CMDH_NEXT_SHIFT (24U)
1102/*! NEXT - Next Command Select
1103 * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
1104 * trigger pending, begin command associated with lower priority trigger.
1105 * 0b0001..Select CMD1 command buffer register as next command.
1106 * 0b0010-0b1110..Select corresponding CMD command buffer register as next command
1107 * 0b1111..Select CMD15 command buffer register as next command.
1108 */
1109#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
1110/*! @} */
1111
1112/* The count of ADC_CMDH */
1113#define ADC_CMDH_COUNT (15U)
1114
1115/*! @name CV - Compare Value Register */
1116/*! @{ */
1117#define ADC_CV_CVL_MASK (0xFFFFU)
1118#define ADC_CV_CVL_SHIFT (0U)
1119/*! CVL - Compare Value Low.
1120 */
1121#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
1122#define ADC_CV_CVH_MASK (0xFFFF0000U)
1123#define ADC_CV_CVH_SHIFT (16U)
1124/*! CVH - Compare Value High.
1125 */
1126#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
1127/*! @} */
1128
1129/* The count of ADC_CV */
1130#define ADC_CV_COUNT (4U)
1131
1132/*! @name RESFIFO - ADC Data Result FIFO Register */
1133/*! @{ */
1134#define ADC_RESFIFO_D_MASK (0xFFFFU)
1135#define ADC_RESFIFO_D_SHIFT (0U)
1136/*! D - Data result
1137 */
1138#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
1139#define ADC_RESFIFO_TSRC_MASK (0xF0000U)
1140#define ADC_RESFIFO_TSRC_SHIFT (16U)
1141/*! TSRC - Trigger Source
1142 * 0b0000..Trigger source 0 initiated this conversion.
1143 * 0b0001..Trigger source 1 initiated this conversion.
1144 * 0b0010-0b1110..Corresponding trigger source initiated this conversion.
1145 * 0b1111..Trigger source 15 initiated this conversion.
1146 */
1147#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
1148#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U)
1149#define ADC_RESFIFO_LOOPCNT_SHIFT (20U)
1150/*! LOOPCNT - Loop count value
1151 * 0b0000..Result is from initial conversion in command.
1152 * 0b0001..Result is from second conversion in command.
1153 * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
1154 * 0b1111..Result is from 16th conversion in command.
1155 */
1156#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
1157#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U)
1158#define ADC_RESFIFO_CMDSRC_SHIFT (24U)
1159/*! CMDSRC - Command Buffer Source
1160 * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
1161 * prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
1162 * 0b0001..CMD1 buffer used as control settings for this conversion.
1163 * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
1164 * 0b1111..CMD15 buffer used as control settings for this conversion.
1165 */
1166#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
1167#define ADC_RESFIFO_VALID_MASK (0x80000000U)
1168#define ADC_RESFIFO_VALID_SHIFT (31U)
1169/*! VALID - FIFO entry is valid
1170 * 0b0..FIFO is empty. Discard any read from RESFIFO.
1171 * 0b1..FIFO record read from RESFIFO is valid.
1172 */
1173#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
1174/*! @} */
1175
1176/* The count of ADC_RESFIFO */
1177#define ADC_RESFIFO_COUNT (2U)
1178
1179/*! @name CAL_GAR - Calibration General A-Side Registers */
1180/*! @{ */
1181#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU)
1182#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U)
1183/*! CAL_GAR_VAL - Calibration General A Side Register Element
1184 */
1185#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK)
1186/*! @} */
1187
1188/* The count of ADC_CAL_GAR */
1189#define ADC_CAL_GAR_COUNT (33U)
1190
1191/*! @name CAL_GBR - Calibration General B-Side Registers */
1192/*! @{ */
1193#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU)
1194#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U)
1195/*! CAL_GBR_VAL - Calibration General B Side Register Element
1196 */
1197#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK)
1198/*! @} */
1199
1200/* The count of ADC_CAL_GBR */
1201#define ADC_CAL_GBR_COUNT (33U)
1202
1203
1204/*!
1205 * @}
1206 */ /* end of group ADC_Register_Masks */
1207
1208
1209/* ADC - Peripheral instance base addresses */
1210#if (__ARM_FEATURE_CMSE & 0x2)
1211 /** Peripheral ADC0 base address */
1212 #define ADC0_BASE (0x500A0000u)
1213 /** Peripheral ADC0 base address */
1214 #define ADC0_BASE_NS (0x400A0000u)
1215 /** Peripheral ADC0 base pointer */
1216 #define ADC0 ((ADC_Type *)ADC0_BASE)
1217 /** Peripheral ADC0 base pointer */
1218 #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS)
1219 /** Array initializer of ADC peripheral base addresses */
1220 #define ADC_BASE_ADDRS { ADC0_BASE }
1221 /** Array initializer of ADC peripheral base pointers */
1222 #define ADC_BASE_PTRS { ADC0 }
1223 /** Array initializer of ADC peripheral base addresses */
1224 #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS }
1225 /** Array initializer of ADC peripheral base pointers */
1226 #define ADC_BASE_PTRS_NS { ADC0_NS }
1227#else
1228 /** Peripheral ADC0 base address */
1229 #define ADC0_BASE (0x400A0000u)
1230 /** Peripheral ADC0 base pointer */
1231 #define ADC0 ((ADC_Type *)ADC0_BASE)
1232 /** Array initializer of ADC peripheral base addresses */
1233 #define ADC_BASE_ADDRS { ADC0_BASE }
1234 /** Array initializer of ADC peripheral base pointers */
1235 #define ADC_BASE_PTRS { ADC0 }
1236#endif
1237/** Interrupt vectors for the ADC peripheral type */
1238#define ADC_IRQS { ADC0_IRQn }
1239
1240/*!
1241 * @}
1242 */ /* end of group ADC_Peripheral_Access_Layer */
1243
1244
1245/* ----------------------------------------------------------------------------
1246 -- AHB_SECURE_CTRL Peripheral Access Layer
1247 ---------------------------------------------------------------------------- */
1248
1249/*!
1250 * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer
1251 * @{
1252 */
1253
1254/** AHB_SECURE_CTRL - Register Layout Typedef */
1255typedef struct {
1256 struct { /* offset: 0x0, array step: 0x30 */
1257 __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */
1258 uint8_t RESERVED_0[12];
1259 __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[1]; /**< Security access rules for FLASH sector 0 to sector 7. Each Flash sector is 32 Kbytes. There are 8 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */
1260 uint8_t RESERVED_1[12];
1261 __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */
1262 } SEC_CTRL_FLASH_ROM[1];
1263 struct { /* offset: 0x30, array step: 0x14 */
1264 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */
1265 uint8_t RESERVED_0[12];
1266 __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */
1267 } SEC_CTRL_RAMX[1];
1268 uint8_t RESERVED_0[12];
1269 struct { /* offset: 0x50, array step: 0x14 */
1270 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x14 */
1271 uint8_t RESERVED_0[12];
1272 __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x14, index2*0x4 */
1273 } SEC_CTRL_RAM0[1];
1274 uint8_t RESERVED_1[12];
1275 struct { /* offset: 0x70, array step: 0x14 */
1276 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x14 */
1277 uint8_t RESERVED_0[12];
1278 __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x14, index2*0x4 */
1279 } SEC_CTRL_RAM1[1];
1280 uint8_t RESERVED_2[12];
1281 struct { /* offset: 0x90, array step: 0x14 */
1282 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x14 */
1283 uint8_t RESERVED_0[12];
1284 __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x14, index2*0x4 */
1285 } SEC_CTRL_RAM2[1];
1286 uint8_t RESERVED_3[12];
1287 struct { /* offset: 0xB0, array step: 0x14 */
1288 __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0xB0, array step: 0x14 */
1289 uint8_t RESERVED_0[12];
1290 __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0xC0, array step: index*0x14, index2*0x4 */
1291 } SEC_CTRL_USB_HS[1];
1292 uint8_t RESERVED_4[12];
1293 struct { /* offset: 0xD0, array step: 0x30 */
1294 __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xD0, array step: 0x30 */
1295 uint8_t RESERVED_0[12];
1296 __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0xE0, array step: 0x30 */
1297 __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0xE4, array step: 0x30 */
1298 __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0xE8, array step: 0x30 */
1299 uint8_t RESERVED_1[4];
1300 __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xF0, array step: 0x30 */
1301 __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xF4, array step: 0x30 */
1302 __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xF8, array step: 0x30 */
1303 __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xFC, array step: 0x30 */
1304 } SEC_CTRL_APB_BRIDGE[1];
1305 __IO uint32_t SEC_CTRL_AHB_PORT7_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x100 */
1306 __IO uint32_t SEC_CTRL_AHB_PORT7_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x104 */
1307 uint8_t RESERVED_5[8];
1308 __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x110 */
1309 __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x114 */
1310 uint8_t RESERVED_6[8];
1311 struct { /* offset: 0x120, array step: 0x14 */
1312 __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x120, array step: 0x14 */
1313 __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x124, array step: 0x14 */
1314 uint8_t RESERVED_0[8];
1315 __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x130, array step: index*0x14, index2*0x4 */
1316 } SEC_CTRL_AHB_PORT9[1];
1317 uint8_t RESERVED_7[3276];
1318 __I uint32_t SEC_VIO_ADDR[10]; /**< most recent security violation address for AHB layer n, array offset: 0xE00, array step: 0x4 */
1319 uint8_t RESERVED_8[88];
1320 __I uint32_t SEC_VIO_MISC_INFO[10]; /**< most recent security violation miscellaneous information for AHB layer n, array offset: 0xE80, array step: 0x4 */
1321 uint8_t RESERVED_9[88];
1322 __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */
1323 uint8_t RESERVED_10[124];
1324 __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */
1325 __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */
1326 uint8_t RESERVED_11[52];
1327 __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */
1328 uint8_t RESERVED_12[16];
1329 __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */
1330 __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */
1331 uint8_t RESERVED_13[20];
1332 __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */
1333 uint8_t RESERVED_14[8];
1334 __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */
1335 __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */
1336} AHB_SECURE_CTRL_Type;
1337
1338/* ----------------------------------------------------------------------------
1339 -- AHB_SECURE_CTRL Register Masks
1340 ---------------------------------------------------------------------------- */
1341
1342/*!
1343 * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks
1344 * @{
1345 */
1346
1347/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */
1348/*! @{ */
1349#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U)
1350#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U)
1351/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0003_FFFF
1352 * 0b00..Non-secure and Non-priviledge user access allowed.
1353 * 0b01..Non-secure and Privilege access allowed.
1354 * 0b10..Secure and Non-priviledge user access allowed.
1355 * 0b11..Secure and Priviledge user access allowed.
1356 */
1357#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK)
1358#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U)
1359#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U)
1360/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF
1361 * 0b00..Non-secure and Non-priviledge user access allowed.
1362 * 0b01..Non-secure and Privilege access allowed.
1363 * 0b10..Secure and Non-priviledge user access allowed.
1364 * 0b11..Secure and Priviledge user access allowed.
1365 */
1366#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK)
1367/*! @} */
1368
1369/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */
1370#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U)
1371
1372/*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 7. Each Flash sector is 32 Kbytes. There are 8 FLASH sectors in total. */
1373/*! @{ */
1374#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U)
1375#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U)
1376/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1377 * 0b00..Non-secure and Non-priviledge user access allowed.
1378 * 0b01..Non-secure and Privilege access allowed.
1379 * 0b10..Secure and Non-priviledge user access allowed.
1380 * 0b11..Secure and Priviledge user access allowed.
1381 */
1382#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK)
1383#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U)
1384#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U)
1385/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1386 * 0b00..Non-secure and Non-priviledge user access allowed.
1387 * 0b01..Non-secure and Privilege access allowed.
1388 * 0b10..Secure and Non-priviledge user access allowed.
1389 * 0b11..Secure and Priviledge user access allowed.
1390 */
1391#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK)
1392#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U)
1393#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U)
1394/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1395 * 0b00..Non-secure and Non-priviledge user access allowed.
1396 * 0b01..Non-secure and Privilege access allowed.
1397 * 0b10..Secure and Non-priviledge user access allowed.
1398 * 0b11..Secure and Priviledge user access allowed.
1399 */
1400#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK)
1401#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U)
1402#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U)
1403/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1404 * 0b00..Non-secure and Non-priviledge user access allowed.
1405 * 0b01..Non-secure and Privilege access allowed.
1406 * 0b10..Secure and Non-priviledge user access allowed.
1407 * 0b11..Secure and Priviledge user access allowed.
1408 */
1409#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK)
1410#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U)
1411#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U)
1412/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1413 * 0b00..Non-secure and Non-priviledge user access allowed.
1414 * 0b01..Non-secure and Privilege access allowed.
1415 * 0b10..Secure and Non-priviledge user access allowed.
1416 * 0b11..Secure and Priviledge user access allowed.
1417 */
1418#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK)
1419#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U)
1420#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U)
1421/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1422 * 0b00..Non-secure and Non-priviledge user access allowed.
1423 * 0b01..Non-secure and Privilege access allowed.
1424 * 0b10..Secure and Non-priviledge user access allowed.
1425 * 0b11..Secure and Priviledge user access allowed.
1426 */
1427#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK)
1428#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U)
1429#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U)
1430/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1431 * 0b00..Non-secure and Non-priviledge user access allowed.
1432 * 0b01..Non-secure and Privilege access allowed.
1433 * 0b10..Secure and Non-priviledge user access allowed.
1434 * 0b11..Secure and Priviledge user access allowed.
1435 */
1436#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK)
1437#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U)
1438#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U)
1439/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1440 * 0b00..Non-secure and Non-priviledge user access allowed.
1441 * 0b01..Non-secure and Privilege access allowed.
1442 * 0b10..Secure and Non-priviledge user access allowed.
1443 * 0b11..Secure and Priviledge user access allowed.
1444 */
1445#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK)
1446/*! @} */
1447
1448/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */
1449#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U)
1450
1451/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */
1452#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (1U)
1453
1454/*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */
1455/*! @{ */
1456#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U)
1457#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U)
1458/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1459 * 0b00..Non-secure and Non-priviledge user access allowed.
1460 * 0b01..Non-secure and Privilege access allowed.
1461 * 0b10..Secure and Non-priviledge user access allowed.
1462 * 0b11..Secure and Priviledge user access allowed.
1463 */
1464#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK)
1465#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U)
1466#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U)
1467/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1468 * 0b00..Non-secure and Non-priviledge user access allowed.
1469 * 0b01..Non-secure and Privilege access allowed.
1470 * 0b10..Secure and Non-priviledge user access allowed.
1471 * 0b11..Secure and Priviledge user access allowed.
1472 */
1473#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK)
1474#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U)
1475#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U)
1476/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1477 * 0b00..Non-secure and Non-priviledge user access allowed.
1478 * 0b01..Non-secure and Privilege access allowed.
1479 * 0b10..Secure and Non-priviledge user access allowed.
1480 * 0b11..Secure and Priviledge user access allowed.
1481 */
1482#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK)
1483#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U)
1484#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U)
1485/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1486 * 0b00..Non-secure and Non-priviledge user access allowed.
1487 * 0b01..Non-secure and Privilege access allowed.
1488 * 0b10..Secure and Non-priviledge user access allowed.
1489 * 0b11..Secure and Priviledge user access allowed.
1490 */
1491#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK)
1492#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U)
1493#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U)
1494/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1495 * 0b00..Non-secure and Non-priviledge user access allowed.
1496 * 0b01..Non-secure and Privilege access allowed.
1497 * 0b10..Secure and Non-priviledge user access allowed.
1498 * 0b11..Secure and Priviledge user access allowed.
1499 */
1500#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK)
1501#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U)
1502#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U)
1503/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1504 * 0b00..Non-secure and Non-priviledge user access allowed.
1505 * 0b01..Non-secure and Privilege access allowed.
1506 * 0b10..Secure and Non-priviledge user access allowed.
1507 * 0b11..Secure and Priviledge user access allowed.
1508 */
1509#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK)
1510#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U)
1511#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U)
1512/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1513 * 0b00..Non-secure and Non-priviledge user access allowed.
1514 * 0b01..Non-secure and Privilege access allowed.
1515 * 0b10..Secure and Non-priviledge user access allowed.
1516 * 0b11..Secure and Priviledge user access allowed.
1517 */
1518#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK)
1519#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U)
1520#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U)
1521/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1522 * 0b00..Non-secure and Non-priviledge user access allowed.
1523 * 0b01..Non-secure and Privilege access allowed.
1524 * 0b10..Secure and Non-priviledge user access allowed.
1525 * 0b11..Secure and Priviledge user access allowed.
1526 */
1527#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK)
1528/*! @} */
1529
1530/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */
1531#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U)
1532
1533/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */
1534#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U)
1535
1536/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */
1537/*! @{ */
1538#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U)
1539#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U)
1540/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF
1541 * 0b00..Non-secure and Non-priviledge user access allowed.
1542 * 0b01..Non-secure and Privilege access allowed.
1543 * 0b10..Secure and Non-priviledge user access allowed.
1544 * 0b11..Secure and Priviledge user access allowed.
1545 */
1546#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK)
1547/*! @} */
1548
1549/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */
1550#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U)
1551
1552/*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */
1553/*! @{ */
1554#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U)
1555#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U)
1556/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1557 * 0b00..Non-secure and Non-priviledge user access allowed.
1558 * 0b01..Non-secure and Privilege access allowed.
1559 * 0b10..Secure and Non-priviledge user access allowed.
1560 * 0b11..Secure and Priviledge user access allowed.
1561 */
1562#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK)
1563#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U)
1564#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U)
1565/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1566 * 0b00..Non-secure and Non-priviledge user access allowed.
1567 * 0b01..Non-secure and Privilege access allowed.
1568 * 0b10..Secure and Non-priviledge user access allowed.
1569 * 0b11..Secure and Priviledge user access allowed.
1570 */
1571#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK)
1572#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U)
1573#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U)
1574/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1575 * 0b00..Non-secure and Non-priviledge user access allowed.
1576 * 0b01..Non-secure and Privilege access allowed.
1577 * 0b10..Secure and Non-priviledge user access allowed.
1578 * 0b11..Secure and Priviledge user access allowed.
1579 */
1580#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK)
1581#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U)
1582#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U)
1583/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1584 * 0b00..Non-secure and Non-priviledge user access allowed.
1585 * 0b01..Non-secure and Privilege access allowed.
1586 * 0b10..Secure and Non-priviledge user access allowed.
1587 * 0b11..Secure and Priviledge user access allowed.
1588 */
1589#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK)
1590/*! @} */
1591
1592/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */
1593#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U)
1594
1595/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */
1596#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U)
1597
1598/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */
1599/*! @{ */
1600#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U)
1601#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U)
1602/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_7FFF
1603 * 0b00..Non-secure and Non-priviledge user access allowed.
1604 * 0b01..Non-secure and Privilege access allowed.
1605 * 0b10..Secure and Non-priviledge user access allowed.
1606 * 0b11..Secure and Priviledge user access allowed.
1607 */
1608#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK)
1609/*! @} */
1610
1611/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */
1612#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U)
1613
1614/*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */
1615/*! @{ */
1616#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U)
1617#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U)
1618/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1619 * 0b00..Non-secure and Non-priviledge user access allowed.
1620 * 0b01..Non-secure and Privilege access allowed.
1621 * 0b10..Secure and Non-priviledge user access allowed.
1622 * 0b11..Secure and Priviledge user access allowed.
1623 */
1624#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK)
1625#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U)
1626#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U)
1627/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1628 * 0b00..Non-secure and Non-priviledge user access allowed.
1629 * 0b01..Non-secure and Privilege access allowed.
1630 * 0b10..Secure and Non-priviledge user access allowed.
1631 * 0b11..Secure and Priviledge user access allowed.
1632 */
1633#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK)
1634#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U)
1635#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U)
1636/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1637 * 0b00..Non-secure and Non-priviledge user access allowed.
1638 * 0b01..Non-secure and Privilege access allowed.
1639 * 0b10..Secure and Non-priviledge user access allowed.
1640 * 0b11..Secure and Priviledge user access allowed.
1641 */
1642#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK)
1643#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U)
1644#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U)
1645/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1646 * 0b00..Non-secure and Non-priviledge user access allowed.
1647 * 0b01..Non-secure and Privilege access allowed.
1648 * 0b10..Secure and Non-priviledge user access allowed.
1649 * 0b11..Secure and Priviledge user access allowed.
1650 */
1651#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK)
1652#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U)
1653#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U)
1654/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1655 * 0b00..Non-secure and Non-priviledge user access allowed.
1656 * 0b01..Non-secure and Privilege access allowed.
1657 * 0b10..Secure and Non-priviledge user access allowed.
1658 * 0b11..Secure and Priviledge user access allowed.
1659 */
1660#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK)
1661#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U)
1662#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U)
1663/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1664 * 0b00..Non-secure and Non-priviledge user access allowed.
1665 * 0b01..Non-secure and Privilege access allowed.
1666 * 0b10..Secure and Non-priviledge user access allowed.
1667 * 0b11..Secure and Priviledge user access allowed.
1668 */
1669#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK)
1670#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U)
1671#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U)
1672/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1673 * 0b00..Non-secure and Non-priviledge user access allowed.
1674 * 0b01..Non-secure and Privilege access allowed.
1675 * 0b10..Secure and Non-priviledge user access allowed.
1676 * 0b11..Secure and Priviledge user access allowed.
1677 */
1678#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK)
1679#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U)
1680#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U)
1681/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1682 * 0b00..Non-secure and Non-priviledge user access allowed.
1683 * 0b01..Non-secure and Privilege access allowed.
1684 * 0b10..Secure and Non-priviledge user access allowed.
1685 * 0b11..Secure and Priviledge user access allowed.
1686 */
1687#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK)
1688/*! @} */
1689
1690/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */
1691#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U)
1692
1693/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */
1694#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (1U)
1695
1696/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */
1697/*! @{ */
1698#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U)
1699#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U)
1700/*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2000_8000 - 0x2000_BFFF
1701 * 0b00..Non-secure and Non-priviledge user access allowed.
1702 * 0b01..Non-secure and Privilege access allowed.
1703 * 0b10..Secure and Non-priviledge user access allowed.
1704 * 0b11..Secure and Priviledge user access allowed.
1705 */
1706#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK)
1707/*! @} */
1708
1709/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */
1710#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U)
1711
1712/*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */
1713/*! @{ */
1714#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U)
1715#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U)
1716/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1717 * 0b00..Non-secure and Non-priviledge user access allowed.
1718 * 0b01..Non-secure and Privilege access allowed.
1719 * 0b10..Secure and Non-priviledge user access allowed.
1720 * 0b11..Secure and Priviledge user access allowed.
1721 */
1722#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK)
1723#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U)
1724#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U)
1725/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1726 * 0b00..Non-secure and Non-priviledge user access allowed.
1727 * 0b01..Non-secure and Privilege access allowed.
1728 * 0b10..Secure and Non-priviledge user access allowed.
1729 * 0b11..Secure and Priviledge user access allowed.
1730 */
1731#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK)
1732#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U)
1733#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U)
1734/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1735 * 0b00..Non-secure and Non-priviledge user access allowed.
1736 * 0b01..Non-secure and Privilege access allowed.
1737 * 0b10..Secure and Non-priviledge user access allowed.
1738 * 0b11..Secure and Priviledge user access allowed.
1739 */
1740#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK)
1741#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U)
1742#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U)
1743/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1744 * 0b00..Non-secure and Non-priviledge user access allowed.
1745 * 0b01..Non-secure and Privilege access allowed.
1746 * 0b10..Secure and Non-priviledge user access allowed.
1747 * 0b11..Secure and Priviledge user access allowed.
1748 */
1749#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK)
1750/*! @} */
1751
1752/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */
1753#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U)
1754
1755/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */
1756#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (1U)
1757
1758/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */
1759/*! @{ */
1760#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U)
1761#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U)
1762/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2000_C000 - 0x2000_FFFF
1763 * 0b00..Non-secure and Non-priviledge user access allowed.
1764 * 0b01..Non-secure and Privilege access allowed.
1765 * 0b10..Secure and Non-priviledge user access allowed.
1766 * 0b11..Secure and Priviledge user access allowed.
1767 */
1768#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK)
1769/*! @} */
1770
1771/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */
1772#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U)
1773
1774/*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */
1775/*! @{ */
1776#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U)
1777#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U)
1778/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1779 * 0b00..Non-secure and Non-priviledge user access allowed.
1780 * 0b01..Non-secure and Privilege access allowed.
1781 * 0b10..Secure and Non-priviledge user access allowed.
1782 * 0b11..Secure and Priviledge user access allowed.
1783 */
1784#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK)
1785#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U)
1786#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U)
1787/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1788 * 0b00..Non-secure and Non-priviledge user access allowed.
1789 * 0b01..Non-secure and Privilege access allowed.
1790 * 0b10..Secure and Non-priviledge user access allowed.
1791 * 0b11..Secure and Priviledge user access allowed.
1792 */
1793#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK)
1794#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U)
1795#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U)
1796/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1797 * 0b00..Non-secure and Non-priviledge user access allowed.
1798 * 0b01..Non-secure and Privilege access allowed.
1799 * 0b10..Secure and Non-priviledge user access allowed.
1800 * 0b11..Secure and Priviledge user access allowed.
1801 */
1802#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK)
1803#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U)
1804#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U)
1805/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1806 * 0b00..Non-secure and Non-priviledge user access allowed.
1807 * 0b01..Non-secure and Privilege access allowed.
1808 * 0b10..Secure and Non-priviledge user access allowed.
1809 * 0b11..Secure and Priviledge user access allowed.
1810 */
1811#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK)
1812/*! @} */
1813
1814/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */
1815#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U)
1816
1817/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */
1818#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (1U)
1819
1820/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */
1821/*! @{ */
1822#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U)
1823#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U)
1824/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x2001_0000 - 0x2001_3FFF
1825 * 0b00..Non-secure and Non-priviledge user access allowed.
1826 * 0b01..Non-secure and Privilege access allowed.
1827 * 0b10..Secure and Non-priviledge user access allowed.
1828 * 0b11..Secure and Priviledge user access allowed.
1829 */
1830#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK)
1831/*! @} */
1832
1833/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */
1834#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U)
1835
1836/*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */
1837/*! @{ */
1838#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U)
1839#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U)
1840/*! SRAM_SECT_0_RULE - Address space: 0x2001_0000 - 0x2001_0FFF
1841 * 0b00..Non-secure and Non-priviledge user access allowed.
1842 * 0b01..Non-secure and Privilege access allowed.
1843 * 0b10..Secure and Non-priviledge user access allowed.
1844 * 0b11..Secure and Priviledge user access allowed.
1845 */
1846#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK)
1847#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U)
1848#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U)
1849/*! SRAM_SECT_1_RULE - Address space: 0x2001_1000 - 0x2001_1FFF
1850 * 0b00..Non-secure and Non-priviledge user access allowed.
1851 * 0b01..Non-secure and Privilege access allowed.
1852 * 0b10..Secure and Non-priviledge user access allowed.
1853 * 0b11..Secure and Priviledge user access allowed.
1854 */
1855#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK)
1856#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U)
1857#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U)
1858/*! SRAM_SECT_2_RULE - Address space: 0x2001_2000 - 0x2001_2FFF
1859 * 0b00..Non-secure and Non-priviledge user access allowed.
1860 * 0b01..Non-secure and Privilege access allowed.
1861 * 0b10..Secure and Non-priviledge user access allowed.
1862 * 0b11..Secure and Priviledge user access allowed.
1863 */
1864#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK)
1865#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U)
1866#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U)
1867/*! SRAM_SECT_3_RULE - Address space: 0x2001_3000 - 0x2001_3FFF
1868 * 0b00..Non-secure and Non-priviledge user access allowed.
1869 * 0b01..Non-secure and Privilege access allowed.
1870 * 0b10..Secure and Non-priviledge user access allowed.
1871 * 0b11..Secure and Priviledge user access allowed.
1872 */
1873#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK)
1874/*! @} */
1875
1876/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */
1877#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U)
1878
1879/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */
1880#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U)
1881
1882/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */
1883/*! @{ */
1884#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U)
1885#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U)
1886/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0
1887 * 0b00..Non-secure and Non-priviledge user access allowed.
1888 * 0b01..Non-secure and Privilege access allowed.
1889 * 0b10..Secure and Non-priviledge user access allowed.
1890 * 0b11..Secure and Priviledge user access allowed.
1891 */
1892#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK)
1893#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U)
1894#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U)
1895/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1
1896 * 0b00..Non-secure and Non-priviledge user access allowed.
1897 * 0b01..Non-secure and Privilege access allowed.
1898 * 0b10..Secure and Non-priviledge user access allowed.
1899 * 0b11..Secure and Priviledge user access allowed.
1900 */
1901#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK)
1902/*! @} */
1903
1904/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */
1905#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U)
1906
1907/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
1908/*! @{ */
1909#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U)
1910#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U)
1911/*! SYSCON_RULE - System Configuration
1912 * 0b00..Non-secure and Non-priviledge user access allowed.
1913 * 0b01..Non-secure and Privilege access allowed.
1914 * 0b10..Secure and Non-priviledge user access allowed.
1915 * 0b11..Secure and Priviledge user access allowed.
1916 */
1917#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK)
1918#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U)
1919#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U)
1920/*! IOCON_RULE - I/O Configuration
1921 * 0b00..Non-secure and Non-priviledge user access allowed.
1922 * 0b01..Non-secure and Privilege access allowed.
1923 * 0b10..Secure and Non-priviledge user access allowed.
1924 * 0b11..Secure and Priviledge user access allowed.
1925 */
1926#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK)
1927#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U)
1928#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U)
1929/*! GINT0_RULE - GPIO input Interrupt 0
1930 * 0b00..Non-secure and Non-priviledge user access allowed.
1931 * 0b01..Non-secure and Privilege access allowed.
1932 * 0b10..Secure and Non-priviledge user access allowed.
1933 * 0b11..Secure and Priviledge user access allowed.
1934 */
1935#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK)
1936#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U)
1937#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U)
1938/*! GINT1_RULE - GPIO input Interrupt 1
1939 * 0b00..Non-secure and Non-priviledge user access allowed.
1940 * 0b01..Non-secure and Privilege access allowed.
1941 * 0b10..Secure and Non-priviledge user access allowed.
1942 * 0b11..Secure and Priviledge user access allowed.
1943 */
1944#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK)
1945#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U)
1946#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U)
1947/*! PINT_RULE - Pin Interrupt and Pattern match
1948 * 0b00..Non-secure and Non-priviledge user access allowed.
1949 * 0b01..Non-secure and Privilege access allowed.
1950 * 0b10..Secure and Non-priviledge user access allowed.
1951 * 0b11..Secure and Priviledge user access allowed.
1952 */
1953#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK)
1954#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U)
1955#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U)
1956/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match
1957 * 0b00..Non-secure and Non-priviledge user access allowed.
1958 * 0b01..Non-secure and Privilege access allowed.
1959 * 0b10..Secure and Non-priviledge user access allowed.
1960 * 0b11..Secure and Priviledge user access allowed.
1961 */
1962#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK)
1963#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U)
1964#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U)
1965/*! INPUTMUX_RULE - Peripheral input multiplexing
1966 * 0b00..Non-secure and Non-priviledge user access allowed.
1967 * 0b01..Non-secure and Privilege access allowed.
1968 * 0b10..Secure and Non-priviledge user access allowed.
1969 * 0b11..Secure and Priviledge user access allowed.
1970 */
1971#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK)
1972/*! @} */
1973
1974/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */
1975#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U)
1976
1977/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
1978/*! @{ */
1979#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U)
1980#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U)
1981/*! CTIMER0_RULE - Standard counter/Timer 0
1982 * 0b00..Non-secure and Non-priviledge user access allowed.
1983 * 0b01..Non-secure and Privilege access allowed.
1984 * 0b10..Secure and Non-priviledge user access allowed.
1985 * 0b11..Secure and Priviledge user access allowed.
1986 */
1987#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK)
1988#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U)
1989#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U)
1990/*! CTIMER1_RULE - Standard counter/Timer 1
1991 * 0b00..Non-secure and Non-priviledge user access allowed.
1992 * 0b01..Non-secure and Privilege access allowed.
1993 * 0b10..Secure and Non-priviledge user access allowed.
1994 * 0b11..Secure and Priviledge user access allowed.
1995 */
1996#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK)
1997#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U)
1998#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U)
1999/*! WWDT_RULE - Windiwed wtachdog Timer
2000 * 0b00..Non-secure and Non-priviledge user access allowed.
2001 * 0b01..Non-secure and Privilege access allowed.
2002 * 0b10..Secure and Non-priviledge user access allowed.
2003 * 0b11..Secure and Priviledge user access allowed.
2004 */
2005#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK)
2006#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U)
2007#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U)
2008/*! MRT_RULE - Multi-rate Timer
2009 * 0b00..Non-secure and Non-priviledge user access allowed.
2010 * 0b01..Non-secure and Privilege access allowed.
2011 * 0b10..Secure and Non-priviledge user access allowed.
2012 * 0b11..Secure and Priviledge user access allowed.
2013 */
2014#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK)
2015#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U)
2016#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U)
2017/*! UTICK_RULE - Micro-Timer
2018 * 0b00..Non-secure and Non-priviledge user access allowed.
2019 * 0b01..Non-secure and Privilege access allowed.
2020 * 0b10..Secure and Non-priviledge user access allowed.
2021 * 0b11..Secure and Priviledge user access allowed.
2022 */
2023#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK)
2024/*! @} */
2025
2026/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */
2027#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U)
2028
2029/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
2030/*! @{ */
2031#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U)
2032#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U)
2033/*! ANACTRL_RULE - Analog Modules controller
2034 * 0b00..Non-secure and Non-priviledge user access allowed.
2035 * 0b01..Non-secure and Privilege access allowed.
2036 * 0b10..Secure and Non-priviledge user access allowed.
2037 * 0b11..Secure and Priviledge user access allowed.
2038 */
2039#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK)
2040/*! @} */
2041
2042/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */
2043#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U)
2044
2045/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2046/*! @{ */
2047#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U)
2048#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U)
2049/*! PMC_RULE - Power Management Controller
2050 * 0b00..Non-secure and Non-priviledge user access allowed.
2051 * 0b01..Non-secure and Privilege access allowed.
2052 * 0b10..Secure and Non-priviledge user access allowed.
2053 * 0b11..Secure and Priviledge user access allowed.
2054 */
2055#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK)
2056#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U)
2057#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U)
2058/*! SYSCTRL_RULE - System Controller
2059 * 0b00..Non-secure and Non-priviledge user access allowed.
2060 * 0b01..Non-secure and Privilege access allowed.
2061 * 0b10..Secure and Non-priviledge user access allowed.
2062 * 0b11..Secure and Priviledge user access allowed.
2063 */
2064#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK)
2065#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_MASK (0x30000U)
2066#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_SHIFT (16U)
2067/*! SPI_FILTER_RULE - SPI FILTER control
2068 * 0b00..Non-secure and Non-priviledge user access allowed.
2069 * 0b01..Non-secure and Privilege access allowed.
2070 * 0b10..Secure and Non-priviledge user access allowed.
2071 * 0b11..Secure and Priviledge user access allowed.
2072 */
2073#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_MASK)
2074/*! @} */
2075
2076/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */
2077#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U)
2078
2079/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2080/*! @{ */
2081#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U)
2082#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U)
2083/*! CTIMER2_RULE - Standard counter/Timer 2
2084 * 0b00..Non-secure and Non-priviledge user access allowed.
2085 * 0b01..Non-secure and Privilege access allowed.
2086 * 0b10..Secure and Non-priviledge user access allowed.
2087 * 0b11..Secure and Priviledge user access allowed.
2088 */
2089#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK)
2090#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U)
2091#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U)
2092/*! CTIMER3_RULE - Standard counter/Timer 3
2093 * 0b00..Non-secure and Non-priviledge user access allowed.
2094 * 0b01..Non-secure and Privilege access allowed.
2095 * 0b10..Secure and Non-priviledge user access allowed.
2096 * 0b11..Secure and Priviledge user access allowed.
2097 */
2098#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK)
2099#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U)
2100#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U)
2101/*! CTIMER4_RULE - Standard counter/Timer 4
2102 * 0b00..Non-secure and Non-priviledge user access allowed.
2103 * 0b01..Non-secure and Privilege access allowed.
2104 * 0b10..Secure and Non-priviledge user access allowed.
2105 * 0b11..Secure and Priviledge user access allowed.
2106 */
2107#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK)
2108#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U)
2109#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U)
2110/*! RTC_RULE - Real Time Counter
2111 * 0b00..Non-secure and Non-priviledge user access allowed.
2112 * 0b01..Non-secure and Privilege access allowed.
2113 * 0b10..Secure and Non-priviledge user access allowed.
2114 * 0b11..Secure and Priviledge user access allowed.
2115 */
2116#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK)
2117#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U)
2118#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U)
2119/*! OSEVENT_RULE - OS Event Timer
2120 * 0b00..Non-secure and Non-priviledge user access allowed.
2121 * 0b01..Non-secure and Privilege access allowed.
2122 * 0b10..Secure and Non-priviledge user access allowed.
2123 * 0b11..Secure and Priviledge user access allowed.
2124 */
2125#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK)
2126/*! @} */
2127
2128/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */
2129#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U)
2130
2131/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2132/*! @{ */
2133#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U)
2134#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U)
2135/*! FLASH_CTRL_RULE - Flash Controller
2136 * 0b00..Non-secure and Non-priviledge user access allowed.
2137 * 0b01..Non-secure and Privilege access allowed.
2138 * 0b10..Secure and Non-priviledge user access allowed.
2139 * 0b11..Secure and Priviledge user access allowed.
2140 */
2141#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK)
2142#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U)
2143#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U)
2144/*! PRINCE_RULE - Prince
2145 * 0b00..Non-secure and Non-priviledge user access allowed.
2146 * 0b01..Non-secure and Privilege access allowed.
2147 * 0b10..Secure and Non-priviledge user access allowed.
2148 * 0b11..Secure and Priviledge user access allowed.
2149 */
2150#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK)
2151/*! @} */
2152
2153/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */
2154#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U)
2155
2156/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2157/*! @{ */
2158#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U)
2159#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U)
2160/*! USBHPHY_RULE - USB High Speed Phy controller
2161 * 0b00..Non-secure and Non-priviledge user access allowed.
2162 * 0b01..Non-secure and Privilege access allowed.
2163 * 0b10..Secure and Non-priviledge user access allowed.
2164 * 0b11..Secure and Priviledge user access allowed.
2165 */
2166#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK)
2167#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U)
2168#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U)
2169/*! RNG_RULE - True Random Number Generator
2170 * 0b00..Non-secure and Non-priviledge user access allowed.
2171 * 0b01..Non-secure and Privilege access allowed.
2172 * 0b10..Secure and Non-priviledge user access allowed.
2173 * 0b11..Secure and Priviledge user access allowed.
2174 */
2175#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK)
2176#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U)
2177#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U)
2178/*! PUF_RULE - PUF
2179 * 0b00..Non-secure and Non-priviledge user access allowed.
2180 * 0b01..Non-secure and Privilege access allowed.
2181 * 0b10..Secure and Non-priviledge user access allowed.
2182 * 0b11..Secure and Priviledge user access allowed.
2183 */
2184#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK)
2185#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U)
2186#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U)
2187/*! PLU_RULE - Programmable Look-Up logic
2188 * 0b00..Non-secure and Non-priviledge user access allowed.
2189 * 0b01..Non-secure and Privilege access allowed.
2190 * 0b10..Secure and Non-priviledge user access allowed.
2191 * 0b11..Secure and Priviledge user access allowed.
2192 */
2193#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK)
2194/*! @} */
2195
2196/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */
2197#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U)
2198
2199/*! @name SEC_CTRL_AHB_PORT7_SLAVE0_RULE - Security access rules for AHB peripherals. */
2200/*! @{ */
2201#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_MASK (0x300U)
2202#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_SHIFT (8U)
2203/*! DMA0_RULE - DMA Controller
2204 * 0b00..Non-secure and Non-priviledge user access allowed.
2205 * 0b01..Non-secure and Privilege access allowed.
2206 * 0b10..Secure and Non-priviledge user access allowed.
2207 * 0b11..Secure and Priviledge user access allowed.
2208 */
2209#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_MASK)
2210#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U)
2211#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U)
2212/*! FS_USB_DEV_RULE - USB Full-speed device
2213 * 0b00..Non-secure and Non-priviledge user access allowed.
2214 * 0b01..Non-secure and Privilege access allowed.
2215 * 0b10..Secure and Non-priviledge user access allowed.
2216 * 0b11..Secure and Priviledge user access allowed.
2217 */
2218#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_MASK)
2219#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_MASK (0x300000U)
2220#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_SHIFT (20U)
2221/*! SCT_RULE - SCTimer
2222 * 0b00..Non-secure and Non-priviledge user access allowed.
2223 * 0b01..Non-secure and Privilege access allowed.
2224 * 0b10..Secure and Non-priviledge user access allowed.
2225 * 0b11..Secure and Priviledge user access allowed.
2226 */
2227#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_MASK)
2228#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U)
2229#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U)
2230/*! FLEXCOMM0_RULE - Flexcomm interface 0
2231 * 0b00..Non-secure and Non-priviledge user access allowed.
2232 * 0b01..Non-secure and Privilege access allowed.
2233 * 0b10..Secure and Non-priviledge user access allowed.
2234 * 0b11..Secure and Priviledge user access allowed.
2235 */
2236#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_MASK)
2237#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U)
2238#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U)
2239/*! FLEXCOMM1_RULE - Flexcomm interface 1
2240 * 0b00..Non-secure and Non-priviledge user access allowed.
2241 * 0b01..Non-secure and Privilege access allowed.
2242 * 0b10..Secure and Non-priviledge user access allowed.
2243 * 0b11..Secure and Priviledge user access allowed.
2244 */
2245#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_MASK)
2246/*! @} */
2247
2248/*! @name SEC_CTRL_AHB_PORT7_SLAVE1_RULE - Security access rules for AHB peripherals. */
2249/*! @{ */
2250#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U)
2251#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U)
2252/*! FLEXCOMM2_RULE - Flexcomm interface 2
2253 * 0b00..Non-secure and Non-priviledge user access allowed.
2254 * 0b01..Non-secure and Privilege access allowed.
2255 * 0b10..Secure and Non-priviledge user access allowed.
2256 * 0b11..Secure and Priviledge user access allowed.
2257 */
2258#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_MASK)
2259#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U)
2260#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U)
2261/*! FLEXCOMM3_RULE - Flexcomm interface 3
2262 * 0b00..Non-secure and Non-priviledge user access allowed.
2263 * 0b01..Non-secure and Privilege access allowed.
2264 * 0b10..Secure and Non-priviledge user access allowed.
2265 * 0b11..Secure and Priviledge user access allowed.
2266 */
2267#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_MASK)
2268#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U)
2269#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U)
2270/*! FLEXCOMM4_RULE - Flexcomm interface 4
2271 * 0b00..Non-secure and Non-priviledge user access allowed.
2272 * 0b01..Non-secure and Privilege access allowed.
2273 * 0b10..Secure and Non-priviledge user access allowed.
2274 * 0b11..Secure and Priviledge user access allowed.
2275 */
2276#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_MASK)
2277#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U)
2278#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U)
2279/*! GPIO0_RULE - High Speed GPIO
2280 * 0b00..Non-secure and Non-priviledge user access allowed.
2281 * 0b01..Non-secure and Privilege access allowed.
2282 * 0b10..Secure and Non-priviledge user access allowed.
2283 * 0b11..Secure and Priviledge user access allowed.
2284 */
2285#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_MASK)
2286/*! @} */
2287
2288/*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */
2289/*! @{ */
2290#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U)
2291#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U)
2292/*! USB_HS_DEV_RULE - USB high Speed device registers
2293 * 0b00..Non-secure and Non-priviledge user access allowed.
2294 * 0b01..Non-secure and Privilege access allowed.
2295 * 0b10..Secure and Non-priviledge user access allowed.
2296 * 0b11..Secure and Priviledge user access allowed.
2297 */
2298#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_MASK)
2299#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_MASK (0x300000U)
2300#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_SHIFT (20U)
2301/*! CRC_RULE - CRC engine
2302 * 0b00..Non-secure and Non-priviledge user access allowed.
2303 * 0b01..Non-secure and Privilege access allowed.
2304 * 0b10..Secure and Non-priviledge user access allowed.
2305 * 0b11..Secure and Priviledge user access allowed.
2306 */
2307#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_MASK)
2308#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U)
2309#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U)
2310/*! FLEXCOMM5_RULE - Flexcomm interface 5
2311 * 0b00..Non-secure and Non-priviledge user access allowed.
2312 * 0b01..Non-secure and Privilege access allowed.
2313 * 0b10..Secure and Non-priviledge user access allowed.
2314 * 0b11..Secure and Priviledge user access allowed.
2315 */
2316#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_MASK)
2317#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U)
2318#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U)
2319/*! FLEXCOMM6_RULE - Flexcomm interface 6
2320 * 0b00..Non-secure and Non-priviledge user access allowed.
2321 * 0b01..Non-secure and Privilege access allowed.
2322 * 0b10..Secure and Non-priviledge user access allowed.
2323 * 0b11..Secure and Priviledge user access allowed.
2324 */
2325#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_MASK)
2326/*! @} */
2327
2328/*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */
2329/*! @{ */
2330#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U)
2331#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U)
2332/*! FLEXCOMM7_RULE - Flexcomm interface 7
2333 * 0b00..Non-secure and Non-priviledge user access allowed.
2334 * 0b01..Non-secure and Privilege access allowed.
2335 * 0b10..Secure and Non-priviledge user access allowed.
2336 * 0b11..Secure and Priviledge user access allowed.
2337 */
2338#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_MASK)
2339#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U)
2340#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U)
2341/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP)
2342 * 0b00..Non-secure and Non-priviledge user access allowed.
2343 * 0b01..Non-secure and Privilege access allowed.
2344 * 0b10..Secure and Non-priviledge user access allowed.
2345 * 0b11..Secure and Priviledge user access allowed.
2346 */
2347#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK)
2348#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_MASK (0x300000U)
2349#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_SHIFT (20U)
2350/*! CAN0_RULE - CAN-FD
2351 * 0b00..Non-secure and Non-priviledge user access allowed.
2352 * 0b01..Non-secure and Privilege access allowed.
2353 * 0b10..Secure and Non-priviledge user access allowed.
2354 * 0b11..Secure and Priviledge user access allowed.
2355 */
2356#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_MASK)
2357#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U)
2358#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U)
2359/*! HS_LSPI_RULE - High Speed SPI
2360 * 0b00..Non-secure and Non-priviledge user access allowed.
2361 * 0b01..Non-secure and Privilege access allowed.
2362 * 0b10..Secure and Non-priviledge user access allowed.
2363 * 0b11..Secure and Priviledge user access allowed.
2364 */
2365#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_MASK)
2366/*! @} */
2367
2368/*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */
2369/*! @{ */
2370#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_MASK (0x3U)
2371#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_SHIFT (0U)
2372/*! ADC_RULE - ADC
2373 * 0b00..Non-secure and Non-priviledge user access allowed.
2374 * 0b01..Non-secure and Privilege access allowed.
2375 * 0b10..Secure and Non-priviledge user access allowed.
2376 * 0b11..Secure and Priviledge user access allowed.
2377 */
2378#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_MASK)
2379#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U)
2380#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U)
2381/*! USB_FS_HOST_RULE - USB Full Speed Host registers.
2382 * 0b00..Non-secure and Non-priviledge user access allowed.
2383 * 0b01..Non-secure and Privilege access allowed.
2384 * 0b10..Secure and Non-priviledge user access allowed.
2385 * 0b11..Secure and Priviledge user access allowed.
2386 */
2387#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_MASK)
2388#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U)
2389#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U)
2390/*! USB_HS_HOST_RULE - USB High speed host registers
2391 * 0b00..Non-secure and Non-priviledge user access allowed.
2392 * 0b01..Non-secure and Privilege access allowed.
2393 * 0b10..Secure and Non-priviledge user access allowed.
2394 * 0b11..Secure and Priviledge user access allowed.
2395 */
2396#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_MASK)
2397#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_MASK (0x30000U)
2398#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_SHIFT (16U)
2399/*! HASH_RULE - SHA-2 crypto registers
2400 * 0b00..Non-secure and Non-priviledge user access allowed.
2401 * 0b01..Non-secure and Privilege access allowed.
2402 * 0b10..Secure and Non-priviledge user access allowed.
2403 * 0b11..Secure and Priviledge user access allowed.
2404 */
2405#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_MASK)
2406#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U)
2407#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_SHIFT (20U)
2408/*! CASPER_RULE - RSA/ECC crypto accelerator
2409 * 0b00..Non-secure and Non-priviledge user access allowed.
2410 * 0b01..Non-secure and Privilege access allowed.
2411 * 0b10..Secure and Non-priviledge user access allowed.
2412 * 0b11..Secure and Priviledge user access allowed.
2413 */
2414#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_MASK)
2415#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U)
2416#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_SHIFT (28U)
2417/*! DMA1_RULE - DMA Controller (Secure)
2418 * 0b00..Non-secure and Non-priviledge user access allowed.
2419 * 0b01..Non-secure and Privilege access allowed.
2420 * 0b10..Secure and Non-priviledge user access allowed.
2421 * 0b11..Secure and Priviledge user access allowed.
2422 */
2423#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_MASK)
2424/*! @} */
2425
2426/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE */
2427#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_COUNT (1U)
2428
2429/*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */
2430/*! @{ */
2431#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U)
2432#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U)
2433/*! GPIO1_RULE - Secure High Speed GPIO
2434 * 0b00..Non-secure and Non-priviledge user access allowed.
2435 * 0b01..Non-secure and Privilege access allowed.
2436 * 0b10..Secure and Non-priviledge user access allowed.
2437 * 0b11..Secure and Priviledge user access allowed.
2438 */
2439#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_MASK)
2440#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U)
2441#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U)
2442/*! AHB_SEC_CTRL_RULE - AHB Secure Controller
2443 * 0b00..Non-secure and Non-priviledge user access allowed.
2444 * 0b01..Non-secure and Privilege access allowed.
2445 * 0b10..Secure and Non-priviledge user access allowed.
2446 * 0b11..Secure and Priviledge user access allowed.
2447 */
2448#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK)
2449/*! @} */
2450
2451/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE */
2452#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_COUNT (1U)
2453
2454/*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */
2455/*! @{ */
2456#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U)
2457#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U)
2458/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF
2459 * 0b00..Non-secure and Non-priviledge user access allowed.
2460 * 0b01..Non-secure and Privilege access allowed.
2461 * 0b10..Secure and Non-priviledge user access allowed.
2462 * 0b11..Secure and Priviledge user access allowed.
2463 */
2464#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK)
2465#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U)
2466#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U)
2467/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF
2468 * 0b00..Non-secure and Non-priviledge user access allowed.
2469 * 0b01..Non-secure and Privilege access allowed.
2470 * 0b10..Secure and Non-priviledge user access allowed.
2471 * 0b11..Secure and Priviledge user access allowed.
2472 */
2473#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK)
2474#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U)
2475#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U)
2476/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF
2477 * 0b00..Non-secure and Non-priviledge user access allowed.
2478 * 0b01..Non-secure and Privilege access allowed.
2479 * 0b10..Secure and Non-priviledge user access allowed.
2480 * 0b11..Secure and Priviledge user access allowed.
2481 */
2482#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK)
2483#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U)
2484#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U)
2485/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF
2486 * 0b00..Non-secure and Non-priviledge user access allowed.
2487 * 0b01..Non-secure and Privilege access allowed.
2488 * 0b10..Secure and Non-priviledge user access allowed.
2489 * 0b11..Secure and Priviledge user access allowed.
2490 */
2491#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK)
2492/*! @} */
2493
2494/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */
2495#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U)
2496
2497/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */
2498#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U)
2499
2500/*! @name SEC_VIO_ADDR - most recent security violation address for AHB layer n */
2501/*! @{ */
2502#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU)
2503#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U)
2504/*! SEC_VIO_ADDR - security violation address for AHB layer
2505 */
2506#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK)
2507/*! @} */
2508
2509/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */
2510#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (10U)
2511
2512/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB layer n */
2513/*! @{ */
2514#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U)
2515#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U)
2516/*! SEC_VIO_INFO_WRITE - security violation access read/write indicator.
2517 * 0b0..Read access.
2518 * 0b1..Write access.
2519 */
2520#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK)
2521#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U)
2522#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U)
2523/*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator.
2524 * 0b0..Code access.
2525 * 0b1..Data access.
2526 */
2527#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK)
2528#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U)
2529#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U)
2530/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level
2531 */
2532#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK)
2533#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U)
2534#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U)
2535/*! SEC_VIO_INFO_MASTER - security violation master number
2536 * 0b0000..CPU0 Code.
2537 * 0b0001..CPU0 System.
2538 * 0b0100..USB-HS Device.
2539 * 0b0101..SDMA0.
2540 * 0b1010..HASH.
2541 * 0b1011..USB-FS Host.
2542 * 0b1100..SDMA1.
2543 * 0b1101..CAN-FD.
2544 */
2545#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK)
2546/*! @} */
2547
2548/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */
2549#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (10U)
2550
2551/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */
2552/*! @{ */
2553#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U)
2554#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U)
2555/*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear.
2556 * 0b0..Not valid.
2557 * 0b1..Valid (violation occurred).
2558 */
2559#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK)
2560#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U)
2561#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U)
2562/*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear.
2563 * 0b0..Not valid.
2564 * 0b1..Valid (violation occurred).
2565 */
2566#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK)
2567#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U)
2568#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U)
2569/*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear.
2570 * 0b0..Not valid.
2571 * 0b1..Valid (violation occurred).
2572 */
2573#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK)
2574#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U)
2575#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U)
2576/*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear.
2577 * 0b0..Not valid.
2578 * 0b1..Valid (violation occurred).
2579 */
2580#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK)
2581#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U)
2582#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U)
2583/*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear.
2584 * 0b0..Not valid.
2585 * 0b1..Valid (violation occurred).
2586 */
2587#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK)
2588#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U)
2589#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U)
2590/*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear.
2591 * 0b0..Not valid.
2592 * 0b1..Valid (violation occurred).
2593 */
2594#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK)
2595#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U)
2596#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U)
2597/*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear.
2598 * 0b0..Not valid.
2599 * 0b1..Valid (violation occurred).
2600 */
2601#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK)
2602#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U)
2603#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U)
2604/*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear.
2605 * 0b0..Not valid.
2606 * 0b1..Valid (violation occurred).
2607 */
2608#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK)
2609#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U)
2610#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U)
2611/*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear.
2612 * 0b0..Not valid.
2613 * 0b1..Valid (violation occurred).
2614 */
2615#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK)
2616#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U)
2617#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U)
2618/*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear.
2619 * 0b0..Not valid.
2620 * 0b1..Valid (violation occurred).
2621 */
2622#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK)
2623/*! @} */
2624
2625/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */
2626/*! @{ */
2627#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U)
2628#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U)
2629/*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0
2630 * 0b1..Pin state is readable by non-secure world.
2631 * 0b0..Pin state is blocked to non-secure world.
2632 */
2633#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK)
2634#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U)
2635#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U)
2636/*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1
2637 * 0b1..Pin state is readable by non-secure world.
2638 * 0b0..Pin state is blocked to non-secure world.
2639 */
2640#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK)
2641#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U)
2642#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U)
2643/*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2
2644 * 0b1..Pin state is readable by non-secure world.
2645 * 0b0..Pin state is blocked to non-secure world.
2646 */
2647#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK)
2648#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U)
2649#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U)
2650/*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3
2651 * 0b1..Pin state is readable by non-secure world.
2652 * 0b0..Pin state is blocked to non-secure world.
2653 */
2654#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK)
2655#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U)
2656#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U)
2657/*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4
2658 * 0b1..Pin state is readable by non-secure world.
2659 * 0b0..Pin state is blocked to non-secure world.
2660 */
2661#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK)
2662#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U)
2663#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U)
2664/*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5
2665 * 0b1..Pin state is readable by non-secure world.
2666 * 0b0..Pin state is blocked to non-secure world.
2667 */
2668#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK)
2669#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U)
2670#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U)
2671/*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6
2672 * 0b1..Pin state is readable by non-secure world.
2673 * 0b0..Pin state is blocked to non-secure world.
2674 */
2675#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK)
2676#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U)
2677#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U)
2678/*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7
2679 * 0b1..Pin state is readable by non-secure world.
2680 * 0b0..Pin state is blocked to non-secure world.
2681 */
2682#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK)
2683#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U)
2684#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U)
2685/*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8
2686 * 0b1..Pin state is readable by non-secure world.
2687 * 0b0..Pin state is blocked to non-secure world.
2688 */
2689#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK)
2690#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U)
2691#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U)
2692/*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9
2693 * 0b1..Pin state is readable by non-secure world.
2694 * 0b0..Pin state is blocked to non-secure world.
2695 */
2696#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK)
2697#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U)
2698#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U)
2699/*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10
2700 * 0b1..Pin state is readable by non-secure world.
2701 * 0b0..Pin state is blocked to non-secure world.
2702 */
2703#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK)
2704#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U)
2705#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U)
2706/*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11
2707 * 0b1..Pin state is readable by non-secure world.
2708 * 0b0..Pin state is blocked to non-secure world.
2709 */
2710#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK)
2711#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U)
2712#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U)
2713/*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12
2714 * 0b1..Pin state is readable by non-secure world.
2715 * 0b0..Pin state is blocked to non-secure world.
2716 */
2717#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK)
2718#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U)
2719#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U)
2720/*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13
2721 * 0b1..Pin state is readable by non-secure world.
2722 * 0b0..Pin state is blocked to non-secure world.
2723 */
2724#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK)
2725#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U)
2726#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U)
2727/*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14
2728 * 0b1..Pin state is readable by non-secure world.
2729 * 0b0..Pin state is blocked to non-secure world.
2730 */
2731#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK)
2732#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U)
2733#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U)
2734/*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15
2735 * 0b1..Pin state is readable by non-secure world.
2736 * 0b0..Pin state is blocked to non-secure world.
2737 */
2738#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK)
2739#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U)
2740#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U)
2741/*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16
2742 * 0b1..Pin state is readable by non-secure world.
2743 * 0b0..Pin state is blocked to non-secure world.
2744 */
2745#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK)
2746#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U)
2747#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U)
2748/*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17
2749 * 0b1..Pin state is readable by non-secure world.
2750 * 0b0..Pin state is blocked to non-secure world.
2751 */
2752#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK)
2753#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U)
2754#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U)
2755/*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18
2756 * 0b1..Pin state is readable by non-secure world.
2757 * 0b0..Pin state is blocked to non-secure world.
2758 */
2759#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK)
2760#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U)
2761#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U)
2762/*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19
2763 * 0b1..Pin state is readable by non-secure world.
2764 * 0b0..Pin state is blocked to non-secure world.
2765 */
2766#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK)
2767#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U)
2768#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U)
2769/*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20
2770 * 0b1..Pin state is readable by non-secure world.
2771 * 0b0..Pin state is blocked to non-secure world.
2772 */
2773#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK)
2774#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U)
2775#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U)
2776/*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21
2777 * 0b1..Pin state is readable by non-secure world.
2778 * 0b0..Pin state is blocked to non-secure world.
2779 */
2780#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK)
2781#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U)
2782#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U)
2783/*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22
2784 * 0b1..Pin state is readable by non-secure world.
2785 * 0b0..Pin state is blocked to non-secure world.
2786 */
2787#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK)
2788#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U)
2789#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U)
2790/*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23
2791 * 0b1..Pin state is readable by non-secure world.
2792 * 0b0..Pin state is blocked to non-secure world.
2793 */
2794#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK)
2795#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U)
2796#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U)
2797/*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24
2798 * 0b1..Pin state is readable by non-secure world.
2799 * 0b0..Pin state is blocked to non-secure world.
2800 */
2801#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK)
2802#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U)
2803#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U)
2804/*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25
2805 * 0b1..Pin state is readable by non-secure world.
2806 * 0b0..Pin state is blocked to non-secure world.
2807 */
2808#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK)
2809#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U)
2810#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U)
2811/*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26
2812 * 0b1..Pin state is readable by non-secure world.
2813 * 0b0..Pin state is blocked to non-secure world.
2814 */
2815#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK)
2816#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U)
2817#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U)
2818/*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27
2819 * 0b1..Pin state is readable by non-secure world.
2820 * 0b0..Pin state is blocked to non-secure world.
2821 */
2822#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK)
2823#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U)
2824#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U)
2825/*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28
2826 * 0b1..Pin state is readable by non-secure world.
2827 * 0b0..Pin state is blocked to non-secure world.
2828 */
2829#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK)
2830#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U)
2831#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U)
2832/*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29
2833 * 0b1..Pin state is readable by non-secure world.
2834 * 0b0..Pin state is blocked to non-secure world.
2835 */
2836#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK)
2837#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U)
2838#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U)
2839/*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30
2840 * 0b1..Pin state is readable by non-secure world.
2841 * 0b0..Pin state is blocked to non-secure world.
2842 */
2843#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK)
2844#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U)
2845#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U)
2846/*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31
2847 * 0b1..Pin state is readable by non-secure world.
2848 * 0b0..Pin state is blocked to non-secure world.
2849 */
2850#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK)
2851/*! @} */
2852
2853/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */
2854/*! @{ */
2855#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U)
2856#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U)
2857/*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0
2858 * 0b1..Pin state is readable by non-secure world.
2859 * 0b0..Pin state is blocked to non-secure world.
2860 */
2861#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK)
2862#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U)
2863#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U)
2864/*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1
2865 * 0b1..Pin state is readable by non-secure world.
2866 * 0b0..Pin state is blocked to non-secure world.
2867 */
2868#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK)
2869#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U)
2870#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U)
2871/*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2
2872 * 0b1..Pin state is readable by non-secure world.
2873 * 0b0..Pin state is blocked to non-secure world.
2874 */
2875#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK)
2876#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U)
2877#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U)
2878/*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3
2879 * 0b1..Pin state is readable by non-secure world.
2880 * 0b0..Pin state is blocked to non-secure world.
2881 */
2882#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK)
2883#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U)
2884#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U)
2885/*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4
2886 * 0b1..Pin state is readable by non-secure world.
2887 * 0b0..Pin state is blocked to non-secure world.
2888 */
2889#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK)
2890#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U)
2891#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U)
2892/*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5
2893 * 0b1..Pin state is readable by non-secure world.
2894 * 0b0..Pin state is blocked to non-secure world.
2895 */
2896#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK)
2897#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U)
2898#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U)
2899/*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6
2900 * 0b1..Pin state is readable by non-secure world.
2901 * 0b0..Pin state is blocked to non-secure world.
2902 */
2903#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK)
2904#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U)
2905#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U)
2906/*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7
2907 * 0b1..Pin state is readable by non-secure world.
2908 * 0b0..Pin state is blocked to non-secure world.
2909 */
2910#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK)
2911#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U)
2912#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U)
2913/*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8
2914 * 0b1..Pin state is readable by non-secure world.
2915 * 0b0..Pin state is blocked to non-secure world.
2916 */
2917#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK)
2918#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U)
2919#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U)
2920/*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9
2921 * 0b1..Pin state is readable by non-secure world.
2922 * 0b0..Pin state is blocked to non-secure world.
2923 */
2924#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK)
2925#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U)
2926#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U)
2927/*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10
2928 * 0b1..Pin state is readable by non-secure world.
2929 * 0b0..Pin state is blocked to non-secure world.
2930 */
2931#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK)
2932#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U)
2933#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U)
2934/*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11
2935 * 0b1..Pin state is readable by non-secure world.
2936 * 0b0..Pin state is blocked to non-secure world.
2937 */
2938#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK)
2939#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U)
2940#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U)
2941/*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12
2942 * 0b1..Pin state is readable by non-secure world.
2943 * 0b0..Pin state is blocked to non-secure world.
2944 */
2945#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK)
2946#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U)
2947#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U)
2948/*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13
2949 * 0b1..Pin state is readable by non-secure world.
2950 * 0b0..Pin state is blocked to non-secure world.
2951 */
2952#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK)
2953#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U)
2954#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U)
2955/*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14
2956 * 0b1..Pin state is readable by non-secure world.
2957 * 0b0..Pin state is blocked to non-secure world.
2958 */
2959#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK)
2960#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U)
2961#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U)
2962/*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15
2963 * 0b1..Pin state is readable by non-secure world.
2964 * 0b0..Pin state is blocked to non-secure world.
2965 */
2966#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK)
2967#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U)
2968#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U)
2969/*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16
2970 * 0b1..Pin state is readable by non-secure world.
2971 * 0b0..Pin state is blocked to non-secure world.
2972 */
2973#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK)
2974#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U)
2975#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U)
2976/*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17
2977 * 0b1..Pin state is readable by non-secure world.
2978 * 0b0..Pin state is blocked to non-secure world.
2979 */
2980#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK)
2981#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U)
2982#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U)
2983/*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18
2984 * 0b1..Pin state is readable by non-secure world.
2985 * 0b0..Pin state is blocked to non-secure world.
2986 */
2987#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK)
2988#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U)
2989#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U)
2990/*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19
2991 * 0b1..Pin state is readable by non-secure world.
2992 * 0b0..Pin state is blocked to non-secure world.
2993 */
2994#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK)
2995#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U)
2996#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U)
2997/*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20
2998 * 0b1..Pin state is readable by non-secure world.
2999 * 0b0..Pin state is blocked to non-secure world.
3000 */
3001#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK)
3002#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U)
3003#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U)
3004/*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21
3005 * 0b1..Pin state is readable by non-secure world.
3006 * 0b0..Pin state is blocked to non-secure world.
3007 */
3008#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK)
3009#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U)
3010#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U)
3011/*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22
3012 * 0b1..Pin state is readable by non-secure world.
3013 * 0b0..Pin state is blocked to non-secure world.
3014 */
3015#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK)
3016#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U)
3017#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U)
3018/*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23
3019 * 0b1..Pin state is readable by non-secure world.
3020 * 0b0..Pin state is blocked to non-secure world.
3021 */
3022#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK)
3023#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U)
3024#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U)
3025/*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24
3026 * 0b1..Pin state is readable by non-secure world.
3027 * 0b0..Pin state is blocked to non-secure world.
3028 */
3029#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK)
3030#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U)
3031#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U)
3032/*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25
3033 * 0b1..Pin state is readable by non-secure world.
3034 * 0b0..Pin state is blocked to non-secure world.
3035 */
3036#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK)
3037#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U)
3038#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U)
3039/*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26
3040 * 0b1..Pin state is readable by non-secure world.
3041 * 0b0..Pin state is blocked to non-secure world.
3042 */
3043#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK)
3044#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U)
3045#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U)
3046/*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27
3047 * 0b1..Pin state is readable by non-secure world.
3048 * 0b0..Pin state is blocked to non-secure world.
3049 */
3050#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK)
3051#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U)
3052#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U)
3053/*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28
3054 * 0b1..Pin state is readable by non-secure world.
3055 * 0b0..Pin state is blocked to non-secure world.
3056 */
3057#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK)
3058#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U)
3059#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U)
3060/*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29
3061 * 0b1..Pin state is readable by non-secure world.
3062 * 0b0..Pin state is blocked to non-secure world.
3063 */
3064#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK)
3065#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U)
3066#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U)
3067/*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30
3068 * 0b1..Pin state is readable by non-secure world.
3069 * 0b0..Pin state is blocked to non-secure world.
3070 */
3071#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK)
3072#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U)
3073#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U)
3074/*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31
3075 * 0b1..Pin state is readable by non-secure world.
3076 * 0b0..Pin state is blocked to non-secure world.
3077 */
3078#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK)
3079/*! @} */
3080
3081/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */
3082/*! @{ */
3083#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U)
3084#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U)
3085/*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock.
3086 * 0b10..Writable.
3087 * 0b01..Restricted mode.
3088 */
3089#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK)
3090#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU)
3091#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U)
3092/*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock.
3093 * 0b10..Writable.
3094 * 0b01..Restricted mode.
3095 */
3096#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK)
3097/*! @} */
3098
3099/*! @name MASTER_SEC_LEVEL - master secure level register */
3100/*! @{ */
3101#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U)
3102#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U)
3103/*! USBFSD - USB Full Speed Device.
3104 * 0b00..Non-secure and Non-priviledge user access allowed.
3105 * 0b01..Non-secure and Privilege access allowed.
3106 * 0b10..Secure and Non-priviledge user access allowed.
3107 * 0b11..Secure and Priviledge user access allowed.
3108 */
3109#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK)
3110#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U)
3111#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U)
3112/*! SDMA0 - System DMA 0.
3113 * 0b00..Non-secure and Non-priviledge user access allowed.
3114 * 0b01..Non-secure and Privilege access allowed.
3115 * 0b10..Secure and Non-priviledge user access allowed.
3116 * 0b11..Secure and Priviledge user access allowed.
3117 */
3118#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK)
3119#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U)
3120#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U)
3121/*! HASH - Hash.
3122 * 0b00..Non-secure and Non-priviledge user access allowed.
3123 * 0b01..Non-secure and Privilege access allowed.
3124 * 0b10..Secure and Non-priviledge user access allowed.
3125 * 0b11..Secure and Priviledge user access allowed.
3126 */
3127#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK)
3128#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U)
3129#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U)
3130/*! USBFSH - USB Full speed Host.
3131 * 0b00..Non-secure and Non-priviledge user access allowed.
3132 * 0b01..Non-secure and Privilege access allowed.
3133 * 0b10..Secure and Non-priviledge user access allowed.
3134 * 0b11..Secure and Priviledge user access allowed.
3135 */
3136#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK)
3137#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U)
3138#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U)
3139/*! SDMA1 - System DMA 1 security level.
3140 * 0b00..Non-secure and Non-priviledge user access allowed.
3141 * 0b01..Non-secure and Privilege access allowed.
3142 * 0b10..Secure and Non-priviledge user access allowed.
3143 * 0b11..Secure and Priviledge user access allowed.
3144 */
3145#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK)
3146#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_MASK (0xC000000U)
3147#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_SHIFT (26U)
3148/*! CANFD - CAN FD.
3149 * 0b00..Non-secure and Non-priviledge user access allowed.
3150 * 0b01..Non-secure and Privilege access allowed.
3151 * 0b10..Secure and Non-priviledge user access allowed.
3152 * 0b11..Secure and Priviledge user access allowed.
3153 */
3154#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_MASK)
3155#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U)
3156#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U)
3157/*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock.
3158 * 0b10..Writable.
3159 * 0b01..Restricted mode.
3160 */
3161#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK)
3162/*! @} */
3163
3164/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */
3165/*! @{ */
3166#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U)
3167#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U)
3168/*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD)
3169 * 0b11..Non-secure and Non-priviledge user access allowed.
3170 * 0b10..Non-secure and Privilege access allowed.
3171 * 0b01..Secure and Non-priviledge user access allowed.
3172 * 0b00..Secure and Priviledge user access allowed.
3173 */
3174#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK)
3175#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U)
3176#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U)
3177/*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0)
3178 * 0b11..Non-secure and Non-priviledge user access allowed.
3179 * 0b10..Non-secure and Privilege access allowed.
3180 * 0b01..Secure and Non-priviledge user access allowed.
3181 * 0b00..Secure and Priviledge user access allowed.
3182 */
3183#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK)
3184#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U)
3185#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U)
3186/*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH)
3187 * 0b11..Non-secure and Non-priviledge user access allowed.
3188 * 0b10..Non-secure and Privilege access allowed.
3189 * 0b01..Secure and Non-priviledge user access allowed.
3190 * 0b00..Secure and Priviledge user access allowed.
3191 */
3192#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK)
3193#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U)
3194#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U)
3195/*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH)
3196 * 0b11..Non-secure and Non-priviledge user access allowed.
3197 * 0b10..Non-secure and Privilege access allowed.
3198 * 0b01..Secure and Non-priviledge user access allowed.
3199 * 0b00..Secure and Priviledge user access allowed.
3200 */
3201#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK)
3202#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U)
3203#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U)
3204/*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1)
3205 * 0b11..Non-secure and Non-priviledge user access allowed.
3206 * 0b10..Non-secure and Privilege access allowed.
3207 * 0b01..Secure and Non-priviledge user access allowed.
3208 * 0b00..Secure and Priviledge user access allowed.
3209 */
3210#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK)
3211#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_MASK (0xC000000U)
3212#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_SHIFT (26U)
3213/*! CANFD - CAN FD. Must be equal to NOT(MASTER_SEC_LEVEL.CANFD)
3214 * 0b11..Non-secure and Non-priviledge user access allowed.
3215 * 0b10..Non-secure and Privilege access allowed.
3216 * 0b01..Secure and Non-priviledge user access allowed.
3217 * 0b00..Secure and Priviledge user access allowed.
3218 */
3219#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_MASK)
3220#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U)
3221#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U)
3222/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock.
3223 * 0b10..Writable.
3224 * 0b01..Restricted mode.
3225 */
3226#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK)
3227/*! @} */
3228
3229/*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */
3230/*! @{ */
3231#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U)
3232#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U)
3233/*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock.
3234 * 0b10..Writable.
3235 * 0b01..Restricted mode.
3236 */
3237#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK)
3238#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU)
3239#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U)
3240/*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock.
3241 * 0b10..Writable.
3242 * 0b01..Restricted mode.
3243 */
3244#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK)
3245#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U)
3246#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U)
3247/*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock.
3248 * 0b10..Writable.
3249 * 0b01..Restricted mode.
3250 */
3251#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK)
3252#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U)
3253#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U)
3254/*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock.
3255 * 0b10..Writable.
3256 * 0b01..Restricted mode.
3257 */
3258#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK)
3259#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U)
3260#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U)
3261/*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock.
3262 * 0b10..Writable.
3263 * 0b01..Restricted mode.
3264 */
3265#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK)
3266#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U)
3267#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U)
3268/*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock.
3269 * 0b10..Writable.
3270 * 0b01..Restricted mode.
3271 */
3272#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK)
3273/*! @} */
3274
3275/*! @name MISC_CTRL_DP_REG - secure control duplicate register */
3276/*! @{ */
3277#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U)
3278#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U)
3279/*! WRITE_LOCK - Write lock.
3280 * 0b10..Secure control registers can be written.
3281 * 0b01..Restricted mode.
3282 */
3283#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK)
3284#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
3285#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
3286/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix.
3287 * 0b10..Disable check.
3288 * 0b01..Restricted mode.
3289 */
3290#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK)
3291#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
3292#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
3293/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix.
3294 * 0b10..Disable check.
3295 * 0b01..Restricted mode.
3296 */
3297#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK)
3298#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
3299#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
3300/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix.
3301 * 0b10..Disable check.
3302 * 0b01..Restricted mode.
3303 */
3304#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK)
3305#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
3306#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
3307/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort.
3308 * 0b10..Enable abort fort secure checker.
3309 * 0b01..Disable abort fort secure checker.
3310 */
3311#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK)
3312#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U)
3313#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U)
3314/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode.
3315 * 0b10..Simple master in strict mode.
3316 * 0b01..Simple master in tier mode.
3317 */
3318#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK)
3319#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U)
3320#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U)
3321/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode.
3322 * 0b10..Smart master in strict mode.
3323 * 0b01..Smart master in tier mode.
3324 */
3325#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK)
3326#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U)
3327#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U)
3328/*! IDAU_ALL_NS - Disable IDAU.
3329 * 0b10..IDAU is enabled.
3330 * 0b01..IDAU is disable.
3331 */
3332#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK)
3333/*! @} */
3334
3335/*! @name MISC_CTRL_REG - secure control register */
3336/*! @{ */
3337#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U)
3338#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U)
3339/*! WRITE_LOCK - Write lock.
3340 * 0b10..Secure control registers can be written.
3341 * 0b01..Restricted mode.
3342 */
3343#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK)
3344#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
3345#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
3346/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix.
3347 * 0b10..Disable check.
3348 * 0b01..Restricted mode.
3349 */
3350#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK)
3351#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
3352#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
3353/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix.
3354 * 0b10..Disable check.
3355 * 0b01..Restricted mode.
3356 */
3357#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK)
3358#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
3359#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
3360/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix.
3361 * 0b10..Disable check.
3362 * 0b01..Restricted mode.
3363 */
3364#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK)
3365#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
3366#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
3367/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort.
3368 * 0b10..Enable abort fort secure checker.
3369 * 0b01..Disable abort fort secure checker.
3370 */
3371#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK)
3372#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U)
3373#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U)
3374/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode.
3375 * 0b10..Simple master in strict mode.
3376 * 0b01..Simple master in tier mode.
3377 */
3378#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK)
3379#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U)
3380#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U)
3381/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode.
3382 * 0b10..Smart master in strict mode.
3383 * 0b01..Smart master in tier mode.
3384 */
3385#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK)
3386#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U)
3387#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U)
3388/*! IDAU_ALL_NS - Disable IDAU.
3389 * 0b10..IDAU is enabled.
3390 * 0b01..IDAU is disable.
3391 */
3392#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK)
3393/*! @} */
3394
3395
3396/*!
3397 * @}
3398 */ /* end of group AHB_SECURE_CTRL_Register_Masks */
3399
3400
3401/* AHB_SECURE_CTRL - Peripheral instance base addresses */
3402#if (__ARM_FEATURE_CMSE & 0x2)
3403 /** Peripheral AHB_SECURE_CTRL base address */
3404 #define AHB_SECURE_CTRL_BASE (0x500AC000u)
3405 /** Peripheral AHB_SECURE_CTRL base address */
3406 #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u)
3407 /** Peripheral AHB_SECURE_CTRL base pointer */
3408 #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)
3409 /** Peripheral AHB_SECURE_CTRL base pointer */
3410 #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS)
3411 /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
3412 #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE }
3413 /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
3414 #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL }
3415 /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
3416 #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS }
3417 /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
3418 #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS }
3419#else
3420 /** Peripheral AHB_SECURE_CTRL base address */
3421 #define AHB_SECURE_CTRL_BASE (0x400AC000u)
3422 /** Peripheral AHB_SECURE_CTRL base pointer */
3423 #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)
3424 /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
3425 #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE }
3426 /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
3427 #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL }
3428#endif
3429
3430/*!
3431 * @}
3432 */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */
3433
3434
3435/* ----------------------------------------------------------------------------
3436 -- ANACTRL Peripheral Access Layer
3437 ---------------------------------------------------------------------------- */
3438
3439/*!
3440 * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer
3441 * @{
3442 */
3443
3444/** ANACTRL - Register Layout Typedef */
3445typedef struct {
3446 uint8_t RESERVED_0[4];
3447 __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */
3448 uint8_t RESERVED_1[4];
3449 __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */
3450 __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */
3451 __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */
3452 uint8_t RESERVED_2[8];
3453 __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */
3454 __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */
3455 uint8_t RESERVED_3[8];
3456 __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */
3457 __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */
3458 uint8_t RESERVED_4[192];
3459 __IO uint32_t DUMMY_CTRL; /**< Dummy Control bus to analog modules, offset: 0xF8 */
3460} ANACTRL_Type;
3461
3462/* ----------------------------------------------------------------------------
3463 -- ANACTRL Register Masks
3464 ---------------------------------------------------------------------------- */
3465
3466/*!
3467 * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks
3468 * @{
3469 */
3470
3471/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */
3472/*! @{ */
3473#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U)
3474#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U)
3475/*! FLASH_PWRDWN - Flash Power Down status.
3476 * 0b0..Flash is not in power down mode.
3477 * 0b1..Flash is in power down mode.
3478 */
3479#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK)
3480#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U)
3481#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U)
3482/*! FLASH_INIT_ERROR - Flash initialization error status.
3483 * 0b0..No error.
3484 * 0b1..At least one error occured during flash initialization..
3485 */
3486#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK)
3487/*! @} */
3488
3489/*! @name FREQ_ME_CTRL - Frequency Measure function control register */
3490/*! @{ */
3491#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU)
3492#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U)
3493/*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale
3494 */
3495#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK)
3496#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U)
3497#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U)
3498/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit
3499 * when the measurement cycle has completed and there is valid capture data in the CAPVAL field
3500 * (bits 30:0).
3501 */
3502#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK)
3503/*! @} */
3504
3505/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */
3506/*! @{ */
3507#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U)
3508#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U)
3509/*! ENA_12MHZCLK - 12 MHz clock control.
3510 * 0b0..12 MHz clock is disabled.
3511 * 0b1..12 MHz clock is enabled.
3512 */
3513#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK)
3514#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U)
3515#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U)
3516/*! DAC_TRIM - Frequency trim.
3517 */
3518#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK)
3519#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U)
3520#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U)
3521/*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode,
3522 * the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF
3523 * packets.
3524 */
3525#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK)
3526#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U)
3527#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U)
3528/*! USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0.
3529 */
3530#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK)
3531#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U)
3532#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U)
3533/*! ENA_96MHZCLK - 96 MHz clock control.
3534 * 0b0..96 MHz clock is disabled.
3535 * 0b1..96 MHz clock is enabled.
3536 */
3537#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK)
3538/*! @} */
3539
3540/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */
3541/*! @{ */
3542#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U)
3543#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U)
3544/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled.
3545 * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available).
3546 * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by
3547 * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK).
3548 */
3549#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK)
3550#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U)
3551#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U)
3552/*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses
3553 * the threshold voltage of a SLVT transistor, this output signal will go high. It is also
3554 * possible to observe the clk_valid signal.
3555 */
3556#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK)
3557/*! @} */
3558
3559/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */
3560/*! @{ */
3561#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U)
3562#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U)
3563/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level.
3564 * 0b0..XO AC buffer bypass is disabled.
3565 * 0b1..XO AC buffer bypass is enabled.
3566 */
3567#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK)
3568#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U)
3569#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U)
3570/*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL.
3571 * 0b0..High speed Crystal oscillator output to USB HS PLL is disabled.
3572 * 0b1..High speed Crystal oscillator output to USB HS PLL is enabled.
3573 */
3574#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK)
3575#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U)
3576#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U)
3577/*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system.
3578 * 0b0..High speed Crystal oscillator output to CPU system is disabled.
3579 * 0b1..High speed Crystal oscillator output to CPU system is enabled.
3580 */
3581#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK)
3582/*! @} */
3583
3584/*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */
3585/*! @{ */
3586#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U)
3587#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U)
3588/*! XO_READY - Indicates XO out frequency statibilty.
3589 * 0b0..XO output frequency is not yet stable.
3590 * 0b1..XO output frequency is stable.
3591 */
3592#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK)
3593/*! @} */
3594
3595/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */
3596/*! @{ */
3597#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U)
3598#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U)
3599/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control.
3600 * 0b0..BOD VBAT interrupt is disabled.
3601 * 0b1..BOD VBAT interrupt is enabled.
3602 */
3603#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK)
3604#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U)
3605#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U)
3606/*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit.
3607 */
3608#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK)
3609#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U)
3610#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U)
3611/*! BODCORE_INT_ENABLE - BOD CORE interrupt control.
3612 * 0b0..BOD CORE interrupt is disabled.
3613 * 0b1..BOD CORE interrupt is enabled.
3614 */
3615#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK)
3616#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U)
3617#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U)
3618/*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit.
3619 */
3620#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK)
3621#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U)
3622#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U)
3623/*! DCDC_INT_ENABLE - DCDC interrupt control.
3624 * 0b0..DCDC interrupt is disabled.
3625 * 0b1..DCDC interrupt is enabled.
3626 */
3627#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK)
3628#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U)
3629#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U)
3630/*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit.
3631 */
3632#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK)
3633/*! @} */
3634
3635/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */
3636/*! @{ */
3637#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U)
3638#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U)
3639/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable.
3640 * 0b0..No interrupt pending..
3641 * 0b1..Interrupt pending..
3642 */
3643#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK)
3644#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U)
3645#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U)
3646/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable.
3647 * 0b0..No interrupt pending..
3648 * 0b1..Interrupt pending..
3649 */
3650#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK)
3651#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U)
3652#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U)
3653/*! BODVBAT_VAL - Current value of BOD VBAT power status output.
3654 * 0b0..VBAT voltage level is below the threshold.
3655 * 0b1..VBAT voltage level is above the threshold.
3656 */
3657#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK)
3658#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U)
3659#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U)
3660/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable.
3661 * 0b0..No interrupt pending..
3662 * 0b1..Interrupt pending..
3663 */
3664#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK)
3665#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U)
3666#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U)
3667/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable.
3668 * 0b0..No interrupt pending..
3669 * 0b1..Interrupt pending..
3670 */
3671#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK)
3672#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U)
3673#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U)
3674/*! BODCORE_VAL - Current value of BOD CORE power status output.
3675 * 0b0..CORE voltage level is below the threshold.
3676 * 0b1..CORE voltage level is above the threshold.
3677 */
3678#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK)
3679#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U)
3680#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U)
3681/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable.
3682 * 0b0..No interrupt pending..
3683 * 0b1..Interrupt pending..
3684 */
3685#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK)
3686#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U)
3687#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U)
3688/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable.
3689 * 0b0..No interrupt pending..
3690 * 0b1..Interrupt pending..
3691 */
3692#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK)
3693#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U)
3694#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U)
3695/*! DCDC_VAL - Current value of DCDC power status output.
3696 * 0b0..DCDC output Voltage is below the targeted regulation level.
3697 * 0b1..DCDC output Voltage is above the targeted regulation level.
3698 */
3699#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK)
3700/*! @} */
3701
3702/*! @name DUMMY_CTRL - Dummy Control bus to analog modules */
3703/*! @{ */
3704#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK (0xC00U)
3705#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_SHIFT (10U)
3706/*! XO32M_ADC_CLK_MODE - Control High speed Crystal oscillator mode of the ADC clock.
3707 * 0b00..High speed Crystal oscillator output to ADC is disabled.
3708 * 0b01..High speed Crystal oscillator output to ADC is enable.
3709 */
3710#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_SHIFT)) & ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK)
3711/*! @} */
3712
3713
3714/*!
3715 * @}
3716 */ /* end of group ANACTRL_Register_Masks */
3717
3718
3719/* ANACTRL - Peripheral instance base addresses */
3720#if (__ARM_FEATURE_CMSE & 0x2)
3721 /** Peripheral ANACTRL base address */
3722 #define ANACTRL_BASE (0x50013000u)
3723 /** Peripheral ANACTRL base address */
3724 #define ANACTRL_BASE_NS (0x40013000u)
3725 /** Peripheral ANACTRL base pointer */
3726 #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE)
3727 /** Peripheral ANACTRL base pointer */
3728 #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS)
3729 /** Array initializer of ANACTRL peripheral base addresses */
3730 #define ANACTRL_BASE_ADDRS { ANACTRL_BASE }
3731 /** Array initializer of ANACTRL peripheral base pointers */
3732 #define ANACTRL_BASE_PTRS { ANACTRL }
3733 /** Array initializer of ANACTRL peripheral base addresses */
3734 #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS }
3735 /** Array initializer of ANACTRL peripheral base pointers */
3736 #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS }
3737#else
3738 /** Peripheral ANACTRL base address */
3739 #define ANACTRL_BASE (0x40013000u)
3740 /** Peripheral ANACTRL base pointer */
3741 #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE)
3742 /** Array initializer of ANACTRL peripheral base addresses */
3743 #define ANACTRL_BASE_ADDRS { ANACTRL_BASE }
3744 /** Array initializer of ANACTRL peripheral base pointers */
3745 #define ANACTRL_BASE_PTRS { ANACTRL }
3746#endif
3747
3748/*!
3749 * @}
3750 */ /* end of group ANACTRL_Peripheral_Access_Layer */
3751
3752
3753/* ----------------------------------------------------------------------------
3754 -- CAN Peripheral Access Layer
3755 ---------------------------------------------------------------------------- */
3756
3757/*!
3758 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
3759 * @{
3760 */
3761
3762/** CAN - Register Layout Typedef */
3763typedef struct {
3764 uint8_t RESERVED_0[12];
3765 __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */
3766 __IO uint32_t TEST; /**< Test Register, offset: 0x10 */
3767 uint8_t RESERVED_1[4];
3768 __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */
3769 __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */
3770 __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */
3771 __I uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */
3772 __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */
3773 __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */
3774 uint8_t RESERVED_2[16];
3775 __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */
3776 __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */
3777 __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */
3778 uint8_t RESERVED_3[4];
3779 __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */
3780 __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */
3781 __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */
3782 __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */
3783 uint8_t RESERVED_4[32];
3784 __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */
3785 __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */
3786 __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */
3787 uint8_t RESERVED_5[4];
3788 __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */
3789 __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */
3790 __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */
3791 __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */
3792 __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */
3793 __I uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */
3794 __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */
3795 __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */
3796 __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */
3797 __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */
3798 __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */
3799 __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */
3800 __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */
3801 __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */
3802 __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */
3803 __I uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */
3804 __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */
3805 __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */
3806 __I uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */
3807 __I uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */
3808 __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */
3809 __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */
3810 uint8_t RESERVED_6[8];
3811 __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */
3812 __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */
3813 __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */
3814 uint8_t RESERVED_7[260];
3815 __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */
3816 uint8_t RESERVED_8[508];
3817 __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */
3818 uint8_t RESERVED_9[508];
3819 __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */
3820} CAN_Type;
3821
3822/* ----------------------------------------------------------------------------
3823 -- CAN Register Masks
3824 ---------------------------------------------------------------------------- */
3825
3826/*!
3827 * @addtogroup CAN_Register_Masks CAN Register Masks
3828 * @{
3829 */
3830
3831/*! @name DBTP - Data Bit Timing Prescaler Register */
3832/*! @{ */
3833#define CAN_DBTP_DSJW_MASK (0xFU)
3834#define CAN_DBTP_DSJW_SHIFT (0U)
3835/*! DSJW - Data (re)synchronization jump width.
3836 */
3837#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK)
3838#define CAN_DBTP_DTSEG2_MASK (0xF0U)
3839#define CAN_DBTP_DTSEG2_SHIFT (4U)
3840/*! DTSEG2 - Data time segment after sample point.
3841 */
3842#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK)
3843#define CAN_DBTP_DTSEG1_MASK (0x1F00U)
3844#define CAN_DBTP_DTSEG1_SHIFT (8U)
3845/*! DTSEG1 - Data time segment before sample point.
3846 */
3847#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK)
3848#define CAN_DBTP_DBRP_MASK (0x1F0000U)
3849#define CAN_DBTP_DBRP_SHIFT (16U)
3850/*! DBRP - Data bit rate prescaler.
3851 */
3852#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK)
3853#define CAN_DBTP_TDC_MASK (0x800000U)
3854#define CAN_DBTP_TDC_SHIFT (23U)
3855/*! TDC - Transmitter delay compensation.
3856 */
3857#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK)
3858/*! @} */
3859
3860/*! @name TEST - Test Register */
3861/*! @{ */
3862#define CAN_TEST_LBCK_MASK (0x10U)
3863#define CAN_TEST_LBCK_SHIFT (4U)
3864/*! LBCK - Loop back mode.
3865 */
3866#define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)
3867#define CAN_TEST_TX_MASK (0x60U)
3868#define CAN_TEST_TX_SHIFT (5U)
3869/*! TX - Control of transmit pin.
3870 */
3871#define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)
3872#define CAN_TEST_RX_MASK (0x80U)
3873#define CAN_TEST_RX_SHIFT (7U)
3874/*! RX - Monitors the actual value of the CAN_RXD.
3875 */
3876#define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)
3877/*! @} */
3878
3879/*! @name CCCR - CC Control Register */
3880/*! @{ */
3881#define CAN_CCCR_INIT_MASK (0x1U)
3882#define CAN_CCCR_INIT_SHIFT (0U)
3883/*! INIT - Initialization.
3884 */
3885#define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)
3886#define CAN_CCCR_CCE_MASK (0x2U)
3887#define CAN_CCCR_CCE_SHIFT (1U)
3888/*! CCE - Configuration change enable.
3889 */
3890#define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)
3891#define CAN_CCCR_ASM_MASK (0x4U)
3892#define CAN_CCCR_ASM_SHIFT (2U)
3893/*! ASM - Restricted operational mode.
3894 */
3895#define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)
3896#define CAN_CCCR_CSA_MASK (0x8U)
3897#define CAN_CCCR_CSA_SHIFT (3U)
3898/*! CSA - Clock Stop Acknowledge.
3899 */
3900#define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)
3901#define CAN_CCCR_CSR_MASK (0x10U)
3902#define CAN_CCCR_CSR_SHIFT (4U)
3903/*! CSR - Clock Stop Request.
3904 */
3905#define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)
3906#define CAN_CCCR_MON_MASK (0x20U)
3907#define CAN_CCCR_MON_SHIFT (5U)
3908/*! MON - Bus monitoring mode.
3909 */
3910#define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)
3911#define CAN_CCCR_DAR_MASK (0x40U)
3912#define CAN_CCCR_DAR_SHIFT (6U)
3913/*! DAR - Disable automatic retransmission.
3914 */
3915#define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)
3916#define CAN_CCCR_TEST_MASK (0x80U)
3917#define CAN_CCCR_TEST_SHIFT (7U)
3918/*! TEST - Test mode enable.
3919 */
3920#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
3921#define CAN_CCCR_FDOE_MASK (0x100U)
3922#define CAN_CCCR_FDOE_SHIFT (8U)
3923/*! FDOE - CAN FD operation enable.
3924 */
3925#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK)
3926#define CAN_CCCR_BRSE_MASK (0x200U)
3927#define CAN_CCCR_BRSE_SHIFT (9U)
3928/*! BRSE - When CAN FD operation is disabled, this bit is not evaluated.
3929 */
3930#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK)
3931#define CAN_CCCR_PXHD_MASK (0x1000U)
3932#define CAN_CCCR_PXHD_SHIFT (12U)
3933/*! PXHD - Protocol exception handling disable.
3934 */
3935#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
3936#define CAN_CCCR_EFBI_MASK (0x2000U)
3937#define CAN_CCCR_EFBI_SHIFT (13U)
3938/*! EFBI - Edge filtering during bus integration.
3939 */
3940#define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)
3941#define CAN_CCCR_TXP_MASK (0x4000U)
3942#define CAN_CCCR_TXP_SHIFT (14U)
3943/*! TXP - Transmit pause.
3944 */
3945#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
3946#define CAN_CCCR_NISO_MASK (0x8000U)
3947#define CAN_CCCR_NISO_SHIFT (15U)
3948/*! NISO - Non ISO operation.
3949 */
3950#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK)
3951/*! @} */
3952
3953/*! @name NBTP - Nominal Bit Timing and Prescaler Register */
3954/*! @{ */
3955#define CAN_NBTP_NTSEG2_MASK (0x7FU)
3956#define CAN_NBTP_NTSEG2_SHIFT (0U)
3957/*! NTSEG2 - Nominal time segment after sample point.
3958 */
3959#define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)
3960#define CAN_NBTP_NTSEG1_MASK (0xFF00U)
3961#define CAN_NBTP_NTSEG1_SHIFT (8U)
3962/*! NTSEG1 - Nominal time segment before sample point.
3963 */
3964#define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)
3965#define CAN_NBTP_NBRP_MASK (0x1FF0000U)
3966#define CAN_NBTP_NBRP_SHIFT (16U)
3967/*! NBRP - Nominal bit rate prescaler.
3968 */
3969#define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)
3970#define CAN_NBTP_NSJW_MASK (0xFE000000U)
3971#define CAN_NBTP_NSJW_SHIFT (25U)
3972/*! NSJW - Nominal (re)synchronization jump width.
3973 */
3974#define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)
3975/*! @} */
3976
3977/*! @name TSCC - Timestamp Counter Configuration */
3978/*! @{ */
3979#define CAN_TSCC_TSS_MASK (0x3U)
3980#define CAN_TSCC_TSS_SHIFT (0U)
3981/*! TSS - Timestamp select.
3982 */
3983#define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)
3984#define CAN_TSCC_TCP_MASK (0xF0000U)
3985#define CAN_TSCC_TCP_SHIFT (16U)
3986/*! TCP - Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times.
3987 */
3988#define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)
3989/*! @} */
3990
3991/*! @name TSCV - Timestamp Counter Value */
3992/*! @{ */
3993#define CAN_TSCV_TSC_MASK (0xFFFFU)
3994#define CAN_TSCV_TSC_SHIFT (0U)
3995/*! TSC - Timestamp counter.
3996 */
3997#define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)
3998/*! @} */
3999
4000/*! @name TOCC - Timeout Counter Configuration */
4001/*! @{ */
4002#define CAN_TOCC_ETOC_MASK (0x1U)
4003#define CAN_TOCC_ETOC_SHIFT (0U)
4004/*! ETOC - Enable timeout counter.
4005 */
4006#define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)
4007#define CAN_TOCC_TOS_MASK (0x6U)
4008#define CAN_TOCC_TOS_SHIFT (1U)
4009/*! TOS - Timeout select.
4010 */
4011#define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)
4012#define CAN_TOCC_TOP_MASK (0xFFFF0000U)
4013#define CAN_TOCC_TOP_SHIFT (16U)
4014/*! TOP - Timeout period.
4015 */
4016#define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)
4017/*! @} */
4018
4019/*! @name TOCV - Timeout Counter Value */
4020/*! @{ */
4021#define CAN_TOCV_TOC_MASK (0xFFFFU)
4022#define CAN_TOCV_TOC_SHIFT (0U)
4023/*! TOC - Timeout counter.
4024 */
4025#define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)
4026/*! @} */
4027
4028/*! @name ECR - Error Counter Register */
4029/*! @{ */
4030#define CAN_ECR_TEC_MASK (0xFFU)
4031#define CAN_ECR_TEC_SHIFT (0U)
4032/*! TEC - Transmit error counter.
4033 */
4034#define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)
4035#define CAN_ECR_REC_MASK (0x7F00U)
4036#define CAN_ECR_REC_SHIFT (8U)
4037/*! REC - Receive error counter.
4038 */
4039#define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)
4040#define CAN_ECR_RP_MASK (0x8000U)
4041#define CAN_ECR_RP_SHIFT (15U)
4042/*! RP - Receive error passive.
4043 */
4044#define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)
4045#define CAN_ECR_CEL_MASK (0xFF0000U)
4046#define CAN_ECR_CEL_SHIFT (16U)
4047/*! CEL - CAN error logging.
4048 */
4049#define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)
4050/*! @} */
4051
4052/*! @name PSR - Protocol Status Register */
4053/*! @{ */
4054#define CAN_PSR_LEC_MASK (0x7U)
4055#define CAN_PSR_LEC_SHIFT (0U)
4056/*! LEC - Last error code.
4057 */
4058#define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)
4059#define CAN_PSR_ACT_MASK (0x18U)
4060#define CAN_PSR_ACT_SHIFT (3U)
4061/*! ACT - Activity.
4062 */
4063#define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)
4064#define CAN_PSR_EP_MASK (0x20U)
4065#define CAN_PSR_EP_SHIFT (5U)
4066/*! EP - Error Passive.
4067 */
4068#define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)
4069#define CAN_PSR_EW_MASK (0x40U)
4070#define CAN_PSR_EW_SHIFT (6U)
4071/*! EW - Warning status.
4072 */
4073#define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)
4074#define CAN_PSR_BO_MASK (0x80U)
4075#define CAN_PSR_BO_SHIFT (7U)
4076/*! BO - Bus Off Status.
4077 */
4078#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
4079#define CAN_PSR_DLEC_MASK (0x700U)
4080#define CAN_PSR_DLEC_SHIFT (8U)
4081/*! DLEC - Data phase last error code.
4082 */
4083#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK)
4084#define CAN_PSR_RESI_MASK (0x800U)
4085#define CAN_PSR_RESI_SHIFT (11U)
4086/*! RESI - ESI flag of the last received CAN FD message.
4087 */
4088#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK)
4089#define CAN_PSR_RBRS_MASK (0x1000U)
4090#define CAN_PSR_RBRS_SHIFT (12U)
4091/*! RBRS - BRS flag of last received CAN FD message.
4092 */
4093#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK)
4094#define CAN_PSR_RFDF_MASK (0x2000U)
4095#define CAN_PSR_RFDF_SHIFT (13U)
4096/*! RFDF - Received a CAN FD message.
4097 */
4098#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK)
4099#define CAN_PSR_PXE_MASK (0x4000U)
4100#define CAN_PSR_PXE_SHIFT (14U)
4101/*! PXE - Protocol exception event.
4102 */
4103#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
4104#define CAN_PSR_TDCV_MASK (0x7F0000U)
4105#define CAN_PSR_TDCV_SHIFT (16U)
4106/*! TDCV - Transmitter delay compensation value.
4107 */
4108#define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)
4109/*! @} */
4110
4111/*! @name TDCR - Transmitter Delay Compensator Register */
4112/*! @{ */
4113#define CAN_TDCR_TDCF_MASK (0x7FU)
4114#define CAN_TDCR_TDCF_SHIFT (0U)
4115/*! TDCF - Transmitter delay compensation filter window length.
4116 */
4117#define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)
4118#define CAN_TDCR_TDCO_MASK (0x7F00U)
4119#define CAN_TDCR_TDCO_SHIFT (8U)
4120/*! TDCO - Transmitter delay compensation offset.
4121 */
4122#define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)
4123/*! @} */
4124
4125/*! @name IR - Interrupt Register */
4126/*! @{ */
4127#define CAN_IR_RF0N_MASK (0x1U)
4128#define CAN_IR_RF0N_SHIFT (0U)
4129/*! RF0N - Rx FIFO 0 new message.
4130 */
4131#define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)
4132#define CAN_IR_RF0W_MASK (0x2U)
4133#define CAN_IR_RF0W_SHIFT (1U)
4134/*! RF0W - Rx FIFO 0 watermark reached.
4135 */
4136#define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)
4137#define CAN_IR_RF0F_MASK (0x4U)
4138#define CAN_IR_RF0F_SHIFT (2U)
4139/*! RF0F - Rx FIFO 0 full.
4140 */
4141#define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)
4142#define CAN_IR_RF0L_MASK (0x8U)
4143#define CAN_IR_RF0L_SHIFT (3U)
4144/*! RF0L - Rx FIFO 0 message lost.
4145 */
4146#define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)
4147#define CAN_IR_RF1N_MASK (0x10U)
4148#define CAN_IR_RF1N_SHIFT (4U)
4149/*! RF1N - Rx FIFO 1 new message.
4150 */
4151#define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)
4152#define CAN_IR_RF1W_MASK (0x20U)
4153#define CAN_IR_RF1W_SHIFT (5U)
4154/*! RF1W - Rx FIFO 1 watermark reached.
4155 */
4156#define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)
4157#define CAN_IR_RF1F_MASK (0x40U)
4158#define CAN_IR_RF1F_SHIFT (6U)
4159/*! RF1F - Rx FIFO 1 full.
4160 */
4161#define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)
4162#define CAN_IR_RF1L_MASK (0x80U)
4163#define CAN_IR_RF1L_SHIFT (7U)
4164/*! RF1L - Rx FIFO 1 message lost.
4165 */
4166#define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)
4167#define CAN_IR_HPM_MASK (0x100U)
4168#define CAN_IR_HPM_SHIFT (8U)
4169/*! HPM - High priority message.
4170 */
4171#define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)
4172#define CAN_IR_TC_MASK (0x200U)
4173#define CAN_IR_TC_SHIFT (9U)
4174/*! TC - Transmission completed.
4175 */
4176#define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)
4177#define CAN_IR_TCF_MASK (0x400U)
4178#define CAN_IR_TCF_SHIFT (10U)
4179/*! TCF - Transmission cancellation finished.
4180 */
4181#define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)
4182#define CAN_IR_TFE_MASK (0x800U)
4183#define CAN_IR_TFE_SHIFT (11U)
4184/*! TFE - Tx FIFO empty.
4185 */
4186#define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)
4187#define CAN_IR_TEFN_MASK (0x1000U)
4188#define CAN_IR_TEFN_SHIFT (12U)
4189/*! TEFN - Tx event FIFO new entry.
4190 */
4191#define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)
4192#define CAN_IR_TEFW_MASK (0x2000U)
4193#define CAN_IR_TEFW_SHIFT (13U)
4194/*! TEFW - Tx event FIFO watermark reached.
4195 */
4196#define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)
4197#define CAN_IR_TEFF_MASK (0x4000U)
4198#define CAN_IR_TEFF_SHIFT (14U)
4199/*! TEFF - Tx event FIFO full.
4200 */
4201#define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)
4202#define CAN_IR_TEFL_MASK (0x8000U)
4203#define CAN_IR_TEFL_SHIFT (15U)
4204/*! TEFL - Tx event FIFO element lost.
4205 */
4206#define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)
4207#define CAN_IR_TSW_MASK (0x10000U)
4208#define CAN_IR_TSW_SHIFT (16U)
4209/*! TSW - Timestamp wraparound.
4210 */
4211#define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)
4212#define CAN_IR_MRAF_MASK (0x20000U)
4213#define CAN_IR_MRAF_SHIFT (17U)
4214/*! MRAF - Message RAM access failure.
4215 */
4216#define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)
4217#define CAN_IR_TOO_MASK (0x40000U)
4218#define CAN_IR_TOO_SHIFT (18U)
4219/*! TOO - Timeout occurred.
4220 */
4221#define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)
4222#define CAN_IR_DRX_MASK (0x80000U)
4223#define CAN_IR_DRX_SHIFT (19U)
4224/*! DRX - Message stored in dedicated Rx buffer.
4225 */
4226#define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)
4227#define CAN_IR_BEC_MASK (0x100000U)
4228#define CAN_IR_BEC_SHIFT (20U)
4229/*! BEC - Bit error corrected.
4230 */
4231#define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)
4232#define CAN_IR_BEU_MASK (0x200000U)
4233#define CAN_IR_BEU_SHIFT (21U)
4234/*! BEU - Bit error uncorrected.
4235 */
4236#define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)
4237#define CAN_IR_ELO_MASK (0x400000U)
4238#define CAN_IR_ELO_SHIFT (22U)