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1/*
2** ###################################################################
3** Processors: LPC55S26JBD100
4** LPC55S26JBD64
5** LPC55S26JEV98
6**
7** Compilers: GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9** Keil ARM C/C++ Compiler
10** MCUXpresso Compiler
11**
12** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
13** Version: rev. 1.1, 2019-05-16
14** Build: b200928
15**
16** Abstract:
17** CMSIS Peripheral Access Layer for LPC55S26
18**
19** Copyright 1997-2016 Freescale Semiconductor, Inc.
20** Copyright 2016-2020 NXP
21** All rights reserved.
22**
23** SPDX-License-Identifier: BSD-3-Clause
24**
25** http: www.nxp.com
26** mail: [email protected]
27**
28** Revisions:
29** - rev. 1.0 (2018-08-22)
30** Initial version based on v0.2UM
31** - rev. 1.1 (2019-05-16)
32** Initial A1 version based on v1.3UM
33**
34** ###################################################################
35*/
36
37/*!
38 * @file LPC55S26.h
39 * @version 1.1
40 * @date 2019-05-16
41 * @brief CMSIS Peripheral Access Layer for LPC55S26
42 *
43 * CMSIS Peripheral Access Layer for LPC55S26
44 */
45
46#ifndef _LPC55S26_H_
47#define _LPC55S26_H_ /**< Symbol preventing repeated inclusion */
48
49/** Memory map major version (memory maps with equal major version number are
50 * compatible) */
51#define MCU_MEM_MAP_VERSION 0x0100U
52/** Memory map minor version */
53#define MCU_MEM_MAP_VERSION_MINOR 0x0001U
54
55
56/* ----------------------------------------------------------------------------
57 -- Interrupt vector numbers
58 ---------------------------------------------------------------------------- */
59
60/*!
61 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
62 * @{
63 */
64
65/** Interrupt Number Definitions */
66#define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */
67
68typedef enum IRQn {
69 /* Auxiliary constants */
70 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
71
72 /* Core interrupts */
73 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
74 HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */
75 MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */
76 BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */
77 UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */
78 SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */
79 SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */
80 DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */
81 PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */
82 SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */
83
84 /* Device specific interrupts */
85 WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */
86 DMA0_IRQn = 1, /**< DMA0 controller */
87 GINT0_IRQn = 2, /**< GPIO group 0 */
88 GINT1_IRQn = 3, /**< GPIO group 1 */
89 PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */
90 PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */
91 PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */
92 PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */
93 UTICK0_IRQn = 8, /**< Micro-tick Timer */
94 MRT0_IRQn = 9, /**< Multi-rate timer */
95 CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
96 CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
97 SCT0_IRQn = 12, /**< SCTimer/PWM */
98 CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
99 FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
100 FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
101 FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
102 FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
103 FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
104 FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
105 FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
106 FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
107 ADC0_IRQn = 22, /**< ADC0 */
108 Reserved39_IRQn = 23, /**< Reserved interrupt */
109 ACMP_IRQn = 24, /**< ACMP interrupts */
110 Reserved41_IRQn = 25, /**< Reserved interrupt */
111 Reserved42_IRQn = 26, /**< Reserved interrupt */
112 USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */
113 USB0_IRQn = 28, /**< USB device */
114 RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */
115 Reserved46_IRQn = 30, /**< Reserved interrupt */
116 Reserved47_IRQn = 31, /**< Reserved interrupt */
117 PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */
118 PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */
119 PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */
120 PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */
121 CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */
122 CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */
123 OS_EVENT_IRQn = 38, /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
124 Reserved55_IRQn = 39, /**< Reserved interrupt */
125 Reserved56_IRQn = 40, /**< Reserved interrupt */
126 Reserved57_IRQn = 41, /**< Reserved interrupt */
127 SDIO_IRQn = 42, /**< SD/MMC */
128 Reserved59_IRQn = 43, /**< Reserved interrupt */
129 Reserved60_IRQn = 44, /**< Reserved interrupt */
130 Reserved61_IRQn = 45, /**< Reserved interrupt */
131 USB1_PHY_IRQn = 46, /**< USB1_PHY */
132 USB1_IRQn = 47, /**< USB1 interrupt */
133 USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */
134 SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */
135 SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */
136 SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */
137 PLU_IRQn = 52, /**< PLU interrupt */
138 SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */
139 HASHCRYPT_IRQn = 54, /**< HASHCRYPT interrupt */
140 CASER_IRQn = 55, /**< CASPER interrupt */
141 PUF_IRQn = 56, /**< PUF interrupt */
142 PQ_IRQn = 57, /**< PQ interrupt */
143 DMA1_IRQn = 58, /**< DMA1 interrupt */
144 FLEXCOMM8_IRQn = 59 /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */
145} IRQn_Type;
146
147/*!
148 * @}
149 */ /* end of group Interrupt_vector_numbers */
150
151
152/* ----------------------------------------------------------------------------
153 -- Cortex M33 Core Configuration
154 ---------------------------------------------------------------------------- */
155
156/*!
157 * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration
158 * @{
159 */
160
161#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
162#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
163#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
164#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
165#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */
166#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */
167
168#include "core_cm33.h" /* Core Peripheral Access Layer */
169#include "system_LPC55S26.h" /* Device specific configuration file */
170
171/*!
172 * @}
173 */ /* end of group Cortex_Core_Configuration */
174
175
176/* ----------------------------------------------------------------------------
177 -- Mapping Information
178 ---------------------------------------------------------------------------- */
179
180/*!
181 * @addtogroup Mapping_Information Mapping Information
182 * @{
183 */
184
185/** Mapping Information */
186/*!
187 * @addtogroup dma_request
188 * @{
189 */
190
191/*******************************************************************************
192 * Definitions
193 ******************************************************************************/
194
195/*!
196 * @brief Structure for the DMA hardware request
197 *
198 * Defines the structure for the DMA hardware request collections. The user can configure the
199 * hardware request to trigger the DMA transfer accordingly. The index
200 * of the hardware request varies according to the to SoC.
201 */
202typedef enum _dma_request_source
203{
204 kDma0RequestHashCrypt = 0U, /**< HashCrypt */
205 kDma1RequestHashCrypt = 0U, /**< HashCrypt */
206 kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */
207 kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */
208 kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */
209 kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */
210 kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */
211 kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */
212 kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */
213 kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */
214 kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */
215 kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */
216 kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */
217 kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */
218 kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */
219 kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */
220 kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */
221 kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */
222 kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */
223 kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */
224 kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */
225 kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */
226 kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */
227 kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */
228 kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */
229 kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */
230 kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */
231 kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */
232 kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */
233 kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */
234 kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */
235 kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */
236 kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */
237} dma_request_source_t;
238
239/* @} */
240
241
242/*!
243 * @}
244 */ /* end of group Mapping_Information */
245
246
247/* ----------------------------------------------------------------------------
248 -- Device Peripheral Access Layer
249 ---------------------------------------------------------------------------- */
250
251/*!
252 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
253 * @{
254 */
255
256
257/*
258** Start of section using anonymous unions
259*/
260
261#if defined(__ARMCC_VERSION)
262 #if (__ARMCC_VERSION >= 6010050)
263 #pragma clang diagnostic push
264 #else
265 #pragma push
266 #pragma anon_unions
267 #endif
268#elif defined(__GNUC__)
269 /* anonymous unions are enabled by default */
270#elif defined(__IAR_SYSTEMS_ICC__)
271 #pragma language=extended
272#else
273 #error Not supported compiler type
274#endif
275
276/* ----------------------------------------------------------------------------
277 -- ADC Peripheral Access Layer
278 ---------------------------------------------------------------------------- */
279
280/*!
281 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
282 * @{
283 */
284
285/** ADC - Register Layout Typedef */
286typedef struct {
287 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
288 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
289 uint8_t RESERVED_0[8];
290 __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */
291 __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */
292 __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */
293 __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */
294 __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */
295 __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */
296 uint8_t RESERVED_1[12];
297 __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
298 __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */
299 uint8_t RESERVED_2[4];
300 __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */
301 uint8_t RESERVED_3[92];
302 __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */
303 __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */
304 uint8_t RESERVED_4[8];
305 __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */
306 __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */
307 struct { /* offset: 0x100, array step: 0x8 */
308 __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
309 __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
310 } CMD[15];
311 uint8_t RESERVED_5[136];
312 __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
313 uint8_t RESERVED_6[240];
314 __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */
315 uint8_t RESERVED_7[248];
316 __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */
317 uint8_t RESERVED_8[124];
318 __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */
319 uint8_t RESERVED_9[2680];
320 __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */
321} ADC_Type;
322
323/* ----------------------------------------------------------------------------
324 -- ADC Register Masks
325 ---------------------------------------------------------------------------- */
326
327/*!
328 * @addtogroup ADC_Register_Masks ADC Register Masks
329 * @{
330 */
331
332/*! @name VERID - Version ID Register */
333/*! @{ */
334#define ADC_VERID_RES_MASK (0x1U)
335#define ADC_VERID_RES_SHIFT (0U)
336/*! RES - Resolution
337 * 0b0..Up to 13-bit differential/12-bit single ended resolution supported.
338 * 0b1..Up to 16-bit differential/16-bit single ended resolution supported.
339 */
340#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
341#define ADC_VERID_DIFFEN_MASK (0x2U)
342#define ADC_VERID_DIFFEN_SHIFT (1U)
343/*! DIFFEN - Differential Supported
344 * 0b0..Differential operation not supported.
345 * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented.
346 */
347#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
348#define ADC_VERID_MVI_MASK (0x8U)
349#define ADC_VERID_MVI_SHIFT (3U)
350/*! MVI - Multi Vref Implemented
351 * 0b0..Single voltage reference high (VREFH) input supported.
352 * 0b1..Multiple voltage reference high (VREFH) inputs supported.
353 */
354#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
355#define ADC_VERID_CSW_MASK (0x70U)
356#define ADC_VERID_CSW_SHIFT (4U)
357/*! CSW - Channel Scale Width
358 * 0b000..Channel scaling not supported.
359 * 0b001..Channel scaling supported. 1-bit CSCALE control field.
360 * 0b110..Channel scaling supported. 6-bit CSCALE control field.
361 */
362#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
363#define ADC_VERID_VR1RNGI_MASK (0x100U)
364#define ADC_VERID_VR1RNGI_SHIFT (8U)
365/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
366 * 0b0..Range control not required. CFG[VREF1RNG] is not implemented.
367 * 0b1..Range control required. CFG[VREF1RNG] is implemented.
368 */
369#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
370#define ADC_VERID_IADCKI_MASK (0x200U)
371#define ADC_VERID_IADCKI_SHIFT (9U)
372/*! IADCKI - Internal ADC Clock implemented
373 * 0b0..Internal clock source not implemented.
374 * 0b1..Internal clock source (and CFG[ADCKEN]) implemented.
375 */
376#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
377#define ADC_VERID_CALOFSI_MASK (0x400U)
378#define ADC_VERID_CALOFSI_SHIFT (10U)
379/*! CALOFSI - Calibration Function Implemented
380 * 0b0..Calibration Not Implemented.
381 * 0b1..Calibration Implemented.
382 */
383#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
384#define ADC_VERID_NUM_SEC_MASK (0x800U)
385#define ADC_VERID_NUM_SEC_SHIFT (11U)
386/*! NUM_SEC - Number of Single Ended Outputs Supported
387 * 0b0..This design supports one single ended conversion at a time.
388 * 0b1..This design supports two simultanious single ended conversions.
389 */
390#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK)
391#define ADC_VERID_NUM_FIFO_MASK (0x7000U)
392#define ADC_VERID_NUM_FIFO_SHIFT (12U)
393/*! NUM_FIFO - Number of FIFOs
394 * 0b000..N/A
395 * 0b001..This design supports one result FIFO.
396 * 0b010..This design supports two result FIFOs.
397 * 0b011..This design supports three result FIFOs.
398 * 0b100..This design supports four result FIFOs.
399 */
400#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK)
401#define ADC_VERID_MINOR_MASK (0xFF0000U)
402#define ADC_VERID_MINOR_SHIFT (16U)
403/*! MINOR - Minor Version Number
404 */
405#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
406#define ADC_VERID_MAJOR_MASK (0xFF000000U)
407#define ADC_VERID_MAJOR_SHIFT (24U)
408/*! MAJOR - Major Version Number
409 */
410#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
411/*! @} */
412
413/*! @name PARAM - Parameter Register */
414/*! @{ */
415#define ADC_PARAM_TRIG_NUM_MASK (0xFFU)
416#define ADC_PARAM_TRIG_NUM_SHIFT (0U)
417/*! TRIG_NUM - Trigger Number
418 */
419#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
420#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U)
421#define ADC_PARAM_FIFOSIZE_SHIFT (8U)
422/*! FIFOSIZE - Result FIFO Depth
423 * 0b00000001..Result FIFO depth = 1 dataword.
424 * 0b00000100..Result FIFO depth = 4 datawords.
425 * 0b00001000..Result FIFO depth = 8 datawords.
426 * 0b00010000..Result FIFO depth = 16 datawords.
427 * 0b00100000..Result FIFO depth = 32 datawords.
428 * 0b01000000..Result FIFO depth = 64 datawords.
429 */
430#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
431#define ADC_PARAM_CV_NUM_MASK (0xFF0000U)
432#define ADC_PARAM_CV_NUM_SHIFT (16U)
433/*! CV_NUM - Compare Value Number
434 */
435#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
436#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U)
437#define ADC_PARAM_CMD_NUM_SHIFT (24U)
438/*! CMD_NUM - Command Buffer Number
439 */
440#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
441/*! @} */
442
443/*! @name CTRL - ADC Control Register */
444/*! @{ */
445#define ADC_CTRL_ADCEN_MASK (0x1U)
446#define ADC_CTRL_ADCEN_SHIFT (0U)
447/*! ADCEN - ADC Enable
448 * 0b0..ADC is disabled.
449 * 0b1..ADC is enabled.
450 */
451#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
452#define ADC_CTRL_RST_MASK (0x2U)
453#define ADC_CTRL_RST_SHIFT (1U)
454/*! RST - Software Reset
455 * 0b0..ADC logic is not reset.
456 * 0b1..ADC logic is reset.
457 */
458#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
459#define ADC_CTRL_DOZEN_MASK (0x4U)
460#define ADC_CTRL_DOZEN_SHIFT (2U)
461/*! DOZEN - Doze Enable
462 * 0b0..ADC is enabled in Doze mode.
463 * 0b1..ADC is disabled in Doze mode.
464 */
465#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
466#define ADC_CTRL_CAL_REQ_MASK (0x8U)
467#define ADC_CTRL_CAL_REQ_SHIFT (3U)
468/*! CAL_REQ - Auto-Calibration Request
469 * 0b0..No request for auto-calibration has been made.
470 * 0b1..A request for auto-calibration has been made
471 */
472#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK)
473#define ADC_CTRL_CALOFS_MASK (0x10U)
474#define ADC_CTRL_CALOFS_SHIFT (4U)
475/*! CALOFS - Configure for offset calibration function
476 * 0b0..Calibration function disabled
477 * 0b1..Request for offset calibration function
478 */
479#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK)
480#define ADC_CTRL_RSTFIFO0_MASK (0x100U)
481#define ADC_CTRL_RSTFIFO0_SHIFT (8U)
482/*! RSTFIFO0 - Reset FIFO 0
483 * 0b0..No effect.
484 * 0b1..FIFO 0 is reset.
485 */
486#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK)
487#define ADC_CTRL_RSTFIFO1_MASK (0x200U)
488#define ADC_CTRL_RSTFIFO1_SHIFT (9U)
489/*! RSTFIFO1 - Reset FIFO 1
490 * 0b0..No effect.
491 * 0b1..FIFO 1 is reset.
492 */
493#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK)
494#define ADC_CTRL_CAL_AVGS_MASK (0x70000U)
495#define ADC_CTRL_CAL_AVGS_SHIFT (16U)
496/*! CAL_AVGS - Auto-Calibration Averages
497 * 0b000..Single conversion.
498 * 0b001..2 conversions averaged.
499 * 0b010..4 conversions averaged.
500 * 0b011..8 conversions averaged.
501 * 0b100..16 conversions averaged.
502 * 0b101..32 conversions averaged.
503 * 0b110..64 conversions averaged.
504 * 0b111..128 conversions averaged.
505 */
506#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK)
507/*! @} */
508
509/*! @name STAT - ADC Status Register */
510/*! @{ */
511#define ADC_STAT_RDY0_MASK (0x1U)
512#define ADC_STAT_RDY0_SHIFT (0U)
513/*! RDY0 - Result FIFO 0 Ready Flag
514 * 0b0..Result FIFO 0 data level not above watermark level.
515 * 0b1..Result FIFO 0 holding data above watermark level.
516 */
517#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK)
518#define ADC_STAT_FOF0_MASK (0x2U)
519#define ADC_STAT_FOF0_SHIFT (1U)
520/*! FOF0 - Result FIFO 0 Overflow Flag
521 * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared.
522 * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.
523 */
524#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK)
525#define ADC_STAT_RDY1_MASK (0x4U)
526#define ADC_STAT_RDY1_SHIFT (2U)
527/*! RDY1 - Result FIFO1 Ready Flag
528 * 0b0..Result FIFO1 data level not above watermark level.
529 * 0b1..Result FIFO1 holding data above watermark level.
530 */
531#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK)
532#define ADC_STAT_FOF1_MASK (0x8U)
533#define ADC_STAT_FOF1_SHIFT (3U)
534/*! FOF1 - Result FIFO1 Overflow Flag
535 * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
536 * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
537 */
538#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK)
539#define ADC_STAT_TEXC_INT_MASK (0x100U)
540#define ADC_STAT_TEXC_INT_SHIFT (8U)
541/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception
542 * 0b0..No trigger exceptions have occurred.
543 * 0b1..A trigger exception has occurred and is pending acknowledgement.
544 */
545#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK)
546#define ADC_STAT_TCOMP_INT_MASK (0x200U)
547#define ADC_STAT_TCOMP_INT_SHIFT (9U)
548/*! TCOMP_INT - Interrupt Flag For Trigger Completion
549 * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion.
550 * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO.
551 */
552#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK)
553#define ADC_STAT_CAL_RDY_MASK (0x400U)
554#define ADC_STAT_CAL_RDY_SHIFT (10U)
555/*! CAL_RDY - Calibration Ready
556 * 0b0..Calibration is incomplete or hasn't been ran.
557 * 0b1..The ADC is calibrated.
558 */
559#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK)
560#define ADC_STAT_ADC_ACTIVE_MASK (0x800U)
561#define ADC_STAT_ADC_ACTIVE_SHIFT (11U)
562/*! ADC_ACTIVE - ADC Active
563 * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
564 * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
565 */
566#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
567#define ADC_STAT_TRGACT_MASK (0xF0000U)
568#define ADC_STAT_TRGACT_SHIFT (16U)
569/*! TRGACT - Trigger Active
570 * 0b0000..Command (sequence) associated with Trigger 0 currently being executed.
571 * 0b0001..Command (sequence) associated with Trigger 1 currently being executed.
572 * 0b0010..Command (sequence) associated with Trigger 2 currently being executed.
573 * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed.
574 */
575#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
576#define ADC_STAT_CMDACT_MASK (0xF000000U)
577#define ADC_STAT_CMDACT_SHIFT (24U)
578/*! CMDACT - Command Active
579 * 0b0000..No command is currently in progress.
580 * 0b0001..Command 1 currently being executed.
581 * 0b0010..Command 2 currently being executed.
582 * 0b0011-0b1111..Associated command number is currently being executed.
583 */
584#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
585/*! @} */
586
587/*! @name IE - Interrupt Enable Register */
588/*! @{ */
589#define ADC_IE_FWMIE0_MASK (0x1U)
590#define ADC_IE_FWMIE0_SHIFT (0U)
591/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable
592 * 0b0..FIFO 0 watermark interrupts are not enabled.
593 * 0b1..FIFO 0 watermark interrupts are enabled.
594 */
595#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK)
596#define ADC_IE_FOFIE0_MASK (0x2U)
597#define ADC_IE_FOFIE0_SHIFT (1U)
598/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable
599 * 0b0..FIFO 0 overflow interrupts are not enabled.
600 * 0b1..FIFO 0 overflow interrupts are enabled.
601 */
602#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK)
603#define ADC_IE_FWMIE1_MASK (0x4U)
604#define ADC_IE_FWMIE1_SHIFT (2U)
605/*! FWMIE1 - FIFO1 Watermark Interrupt Enable
606 * 0b0..FIFO1 watermark interrupts are not enabled.
607 * 0b1..FIFO1 watermark interrupts are enabled.
608 */
609#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK)
610#define ADC_IE_FOFIE1_MASK (0x8U)
611#define ADC_IE_FOFIE1_SHIFT (3U)
612/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable
613 * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
614 * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
615 */
616#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK)
617#define ADC_IE_TEXC_IE_MASK (0x100U)
618#define ADC_IE_TEXC_IE_SHIFT (8U)
619/*! TEXC_IE - Trigger Exception Interrupt Enable
620 * 0b0..Trigger exception interrupts are disabled.
621 * 0b1..Trigger exception interrupts are enabled.
622 */
623#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK)
624#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U)
625#define ADC_IE_TCOMP_IE_SHIFT (16U)
626/*! TCOMP_IE - Trigger Completion Interrupt Enable
627 * 0b0000000000000000..Trigger completion interrupts are disabled.
628 * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only.
629 * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only.
630 * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled.
631 * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source.
632 */
633#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK)
634/*! @} */
635
636/*! @name DE - DMA Enable Register */
637/*! @{ */
638#define ADC_DE_FWMDE0_MASK (0x1U)
639#define ADC_DE_FWMDE0_SHIFT (0U)
640/*! FWMDE0 - FIFO 0 Watermark DMA Enable
641 * 0b0..DMA request disabled.
642 * 0b1..DMA request enabled.
643 */
644#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK)
645#define ADC_DE_FWMDE1_MASK (0x2U)
646#define ADC_DE_FWMDE1_SHIFT (1U)
647/*! FWMDE1 - FIFO1 Watermark DMA Enable
648 * 0b0..DMA request disabled.
649 * 0b1..DMA request enabled.
650 */
651#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK)
652/*! @} */
653
654/*! @name CFG - ADC Configuration Register */
655/*! @{ */
656#define ADC_CFG_TPRICTRL_MASK (0x3U)
657#define ADC_CFG_TPRICTRL_SHIFT (0U)
658/*! TPRICTRL - ADC trigger priority control
659 * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted
660 * and the new command specified by the trigger is started.
661 * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after
662 * after completing the current conversion. If averaging is enabled, the averaging loop will be completed.
663 * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced.
664 * 0b10..If a higher priority trigger is received during command processing, the current command will be
665 * completed (averaging, looping, compare) before servicing the higher priority trigger.
666 * 0b11..RESERVED
667 */
668#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
669#define ADC_CFG_PWRSEL_MASK (0x30U)
670#define ADC_CFG_PWRSEL_SHIFT (4U)
671/*! PWRSEL - Power Configuration Select
672 * 0b00..Lowest power setting.
673 * 0b01..Higher power setting than 0b0.
674 * 0b10..Higher power setting than 0b1.
675 * 0b11..Highest power setting.
676 */
677#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
678#define ADC_CFG_REFSEL_MASK (0xC0U)
679#define ADC_CFG_REFSEL_SHIFT (6U)
680/*! REFSEL - Voltage Reference Selection
681 * 0b00..(Default) Option 1 setting.
682 * 0b01..Option 2 setting.
683 * 0b10..Option 3 setting.
684 * 0b11..Reserved
685 */
686#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
687#define ADC_CFG_TRES_MASK (0x100U)
688#define ADC_CFG_TRES_SHIFT (8U)
689/*! TRES - Trigger Resume Enable
690 * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted.
691 * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted.
692 */
693#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK)
694#define ADC_CFG_TCMDRES_MASK (0x200U)
695#define ADC_CFG_TCMDRES_SHIFT (9U)
696/*! TCMDRES - Trigger Command Resume
697 * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted.
698 * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception.
699 */
700#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK)
701#define ADC_CFG_HPT_EXDI_MASK (0x400U)
702#define ADC_CFG_HPT_EXDI_SHIFT (10U)
703/*! HPT_EXDI - High Priority Trigger Exception Disable
704 * 0b0..High priority trigger exceptions are enabled.
705 * 0b1..High priority trigger exceptions are disabled.
706 */
707#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK)
708#define ADC_CFG_PUDLY_MASK (0xFF0000U)
709#define ADC_CFG_PUDLY_SHIFT (16U)
710/*! PUDLY - Power Up Delay
711 */
712#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
713#define ADC_CFG_PWREN_MASK (0x10000000U)
714#define ADC_CFG_PWREN_SHIFT (28U)
715/*! PWREN - ADC Analog Pre-Enable
716 * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
717 * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
718 * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN
719 * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed.
720 * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be
721 * executed.
722 */
723#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
724/*! @} */
725
726/*! @name PAUSE - ADC Pause Register */
727/*! @{ */
728#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU)
729#define ADC_PAUSE_PAUSEDLY_SHIFT (0U)
730/*! PAUSEDLY - Pause Delay
731 */
732#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
733#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U)
734#define ADC_PAUSE_PAUSEEN_SHIFT (31U)
735/*! PAUSEEN - PAUSE Option Enable
736 * 0b0..Pause operation disabled
737 * 0b1..Pause operation enabled
738 */
739#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
740/*! @} */
741
742/*! @name SWTRIG - Software Trigger Register */
743/*! @{ */
744#define ADC_SWTRIG_SWT0_MASK (0x1U)
745#define ADC_SWTRIG_SWT0_SHIFT (0U)
746/*! SWT0 - Software trigger 0 event
747 * 0b0..No trigger 0 event generated.
748 * 0b1..Trigger 0 event generated.
749 */
750#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
751#define ADC_SWTRIG_SWT1_MASK (0x2U)
752#define ADC_SWTRIG_SWT1_SHIFT (1U)
753/*! SWT1 - Software trigger 1 event
754 * 0b0..No trigger 1 event generated.
755 * 0b1..Trigger 1 event generated.
756 */
757#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
758#define ADC_SWTRIG_SWT2_MASK (0x4U)
759#define ADC_SWTRIG_SWT2_SHIFT (2U)
760/*! SWT2 - Software trigger 2 event
761 * 0b0..No trigger 2 event generated.
762 * 0b1..Trigger 2 event generated.
763 */
764#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
765#define ADC_SWTRIG_SWT3_MASK (0x8U)
766#define ADC_SWTRIG_SWT3_SHIFT (3U)
767/*! SWT3 - Software trigger 3 event
768 * 0b0..No trigger 3 event generated.
769 * 0b1..Trigger 3 event generated.
770 */
771#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
772#define ADC_SWTRIG_SWT4_MASK (0x10U)
773#define ADC_SWTRIG_SWT4_SHIFT (4U)
774/*! SWT4 - Software trigger 4 event
775 * 0b0..No trigger 4 event generated.
776 * 0b1..Trigger 4 event generated.
777 */
778#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
779#define ADC_SWTRIG_SWT5_MASK (0x20U)
780#define ADC_SWTRIG_SWT5_SHIFT (5U)
781/*! SWT5 - Software trigger 5 event
782 * 0b0..No trigger 5 event generated.
783 * 0b1..Trigger 5 event generated.
784 */
785#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
786#define ADC_SWTRIG_SWT6_MASK (0x40U)
787#define ADC_SWTRIG_SWT6_SHIFT (6U)
788/*! SWT6 - Software trigger 6 event
789 * 0b0..No trigger 6 event generated.
790 * 0b1..Trigger 6 event generated.
791 */
792#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
793#define ADC_SWTRIG_SWT7_MASK (0x80U)
794#define ADC_SWTRIG_SWT7_SHIFT (7U)
795/*! SWT7 - Software trigger 7 event
796 * 0b0..No trigger 7 event generated.
797 * 0b1..Trigger 7 event generated.
798 */
799#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
800#define ADC_SWTRIG_SWT8_MASK (0x100U)
801#define ADC_SWTRIG_SWT8_SHIFT (8U)
802/*! SWT8 - Software trigger 8 event
803 * 0b0..No trigger 8 event generated.
804 * 0b1..Trigger 8 event generated.
805 */
806#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK)
807#define ADC_SWTRIG_SWT9_MASK (0x200U)
808#define ADC_SWTRIG_SWT9_SHIFT (9U)
809/*! SWT9 - Software trigger 9 event
810 * 0b0..No trigger 9 event generated.
811 * 0b1..Trigger 9 event generated.
812 */
813#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK)
814#define ADC_SWTRIG_SWT10_MASK (0x400U)
815#define ADC_SWTRIG_SWT10_SHIFT (10U)
816/*! SWT10 - Software trigger 10 event
817 * 0b0..No trigger 10 event generated.
818 * 0b1..Trigger 10 event generated.
819 */
820#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK)
821#define ADC_SWTRIG_SWT11_MASK (0x800U)
822#define ADC_SWTRIG_SWT11_SHIFT (11U)
823/*! SWT11 - Software trigger 11 event
824 * 0b0..No trigger 11 event generated.
825 * 0b1..Trigger 11 event generated.
826 */
827#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK)
828#define ADC_SWTRIG_SWT12_MASK (0x1000U)
829#define ADC_SWTRIG_SWT12_SHIFT (12U)
830/*! SWT12 - Software trigger 12 event
831 * 0b0..No trigger 12 event generated.
832 * 0b1..Trigger 12 event generated.
833 */
834#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK)
835#define ADC_SWTRIG_SWT13_MASK (0x2000U)
836#define ADC_SWTRIG_SWT13_SHIFT (13U)
837/*! SWT13 - Software trigger 13 event
838 * 0b0..No trigger 13 event generated.
839 * 0b1..Trigger 13 event generated.
840 */
841#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK)
842#define ADC_SWTRIG_SWT14_MASK (0x4000U)
843#define ADC_SWTRIG_SWT14_SHIFT (14U)
844/*! SWT14 - Software trigger 14 event
845 * 0b0..No trigger 14 event generated.
846 * 0b1..Trigger 14 event generated.
847 */
848#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK)
849#define ADC_SWTRIG_SWT15_MASK (0x8000U)
850#define ADC_SWTRIG_SWT15_SHIFT (15U)
851/*! SWT15 - Software trigger 15 event
852 * 0b0..No trigger 15 event generated.
853 * 0b1..Trigger 15 event generated.
854 */
855#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK)
856/*! @} */
857
858/*! @name TSTAT - Trigger Status Register */
859/*! @{ */
860#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU)
861#define ADC_TSTAT_TEXC_NUM_SHIFT (0U)
862/*! TEXC_NUM - Trigger Exception Number
863 * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1.
864 * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception.
865 * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception.
866 * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception.
867 * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception.
868 */
869#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK)
870#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U)
871#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U)
872/*! TCOMP_FLAG - Trigger Completion Flag
873 * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled.
874 * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts.
875 * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts.
876 * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts.
877 * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts.
878 */
879#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK)
880/*! @} */
881
882/*! @name OFSTRIM - ADC Offset Trim Register */
883/*! @{ */
884#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU)
885#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U)
886/*! OFSTRIM_A - Trim for offset
887 */
888#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK)
889#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U)
890#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U)
891/*! OFSTRIM_B - Trim for offset
892 */
893#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK)
894/*! @} */
895
896/*! @name TCTRL - Trigger Control Register */
897/*! @{ */
898#define ADC_TCTRL_HTEN_MASK (0x1U)
899#define ADC_TCTRL_HTEN_SHIFT (0U)
900/*! HTEN - Trigger enable
901 * 0b0..Hardware trigger source disabled
902 * 0b1..Hardware trigger source enabled
903 */
904#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
905#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U)
906#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U)
907/*! FIFO_SEL_A - SAR Result Destination For Channel A
908 * 0b0..Result written to FIFO 0
909 * 0b1..Result written to FIFO 1
910 */
911#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK)
912#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U)
913#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U)
914/*! FIFO_SEL_B - SAR Result Destination For Channel B
915 * 0b0..Result written to FIFO 0
916 * 0b1..Result written to FIFO 1
917 */
918#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK)
919#define ADC_TCTRL_TPRI_MASK (0xF00U)
920#define ADC_TCTRL_TPRI_SHIFT (8U)
921/*! TPRI - Trigger priority setting
922 * 0b0000..Set to highest priority, Level 1
923 * 0b0001-0b1110..Set to corresponding priority level
924 * 0b1111..Set to lowest priority, Level 16
925 */
926#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
927#define ADC_TCTRL_RSYNC_MASK (0x8000U)
928#define ADC_TCTRL_RSYNC_SHIFT (15U)
929/*! RSYNC - Trigger Resync
930 */
931#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK)
932#define ADC_TCTRL_TDLY_MASK (0xF0000U)
933#define ADC_TCTRL_TDLY_SHIFT (16U)
934/*! TDLY - Trigger delay select
935 */
936#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
937#define ADC_TCTRL_TCMD_MASK (0xF000000U)
938#define ADC_TCTRL_TCMD_SHIFT (24U)
939/*! TCMD - Trigger command select
940 * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
941 * 0b0001..CMD1 is executed
942 * 0b0010-0b1110..Corresponding CMD is executed
943 * 0b1111..CMD15 is executed
944 */
945#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
946/*! @} */
947
948/* The count of ADC_TCTRL */
949#define ADC_TCTRL_COUNT (16U)
950
951/*! @name FCTRL - FIFO Control Register */
952/*! @{ */
953#define ADC_FCTRL_FCOUNT_MASK (0x1FU)
954#define ADC_FCTRL_FCOUNT_SHIFT (0U)
955/*! FCOUNT - Result FIFO counter
956 */
957#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
958#define ADC_FCTRL_FWMARK_MASK (0xF0000U)
959#define ADC_FCTRL_FWMARK_SHIFT (16U)
960/*! FWMARK - Watermark level selection
961 */
962#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
963/*! @} */
964
965/* The count of ADC_FCTRL */
966#define ADC_FCTRL_COUNT (2U)
967
968/*! @name GCC - Gain Calibration Control */
969/*! @{ */
970#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU)
971#define ADC_GCC_GAIN_CAL_SHIFT (0U)
972/*! GAIN_CAL - Gain Calibration Value
973 */
974#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK)
975#define ADC_GCC_RDY_MASK (0x1000000U)
976#define ADC_GCC_RDY_SHIFT (24U)
977/*! RDY - Gain Calibration Value Valid
978 * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written.
979 * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field.
980 */
981#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK)
982/*! @} */
983
984/* The count of ADC_GCC */
985#define ADC_GCC_COUNT (2U)
986
987/*! @name GCR - Gain Calculation Result */
988/*! @{ */
989#define ADC_GCR_GCALR_MASK (0xFFFFU)
990#define ADC_GCR_GCALR_SHIFT (0U)
991/*! GCALR - Gain Calculation Result
992 */
993#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK)
994#define ADC_GCR_RDY_MASK (0x1000000U)
995#define ADC_GCR_RDY_SHIFT (24U)
996/*! RDY - Gain Calculation Ready
997 * 0b0..The gain offset calculation value is invalid.
998 * 0b1..The gain calibration value is valid.
999 */
1000#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK)
1001/*! @} */
1002
1003/* The count of ADC_GCR */
1004#define ADC_GCR_COUNT (2U)
1005
1006/*! @name CMDL - ADC Command Low Buffer Register */
1007/*! @{ */
1008#define ADC_CMDL_ADCH_MASK (0x1FU)
1009#define ADC_CMDL_ADCH_SHIFT (0U)
1010/*! ADCH - Input channel select
1011 * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
1012 * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
1013 * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
1014 * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
1015 * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
1016 * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
1017 * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
1018 */
1019#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
1020#define ADC_CMDL_CTYPE_MASK (0x60U)
1021#define ADC_CMDL_CTYPE_SHIFT (5U)
1022/*! CTYPE - Conversion Type
1023 * 0b00..Single-Ended Mode. Only A side channel is converted.
1024 * 0b01..Single-Ended Mode. Only B side channel is converted.
1025 * 0b10..Differential Mode. A-B.
1026 * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
1027 */
1028#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK)
1029#define ADC_CMDL_MODE_MASK (0x80U)
1030#define ADC_CMDL_MODE_SHIFT (7U)
1031/*! MODE - Select resolution of conversions
1032 * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
1033 * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
1034 */
1035#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK)
1036/*! @} */
1037
1038/* The count of ADC_CMDL */
1039#define ADC_CMDL_COUNT (15U)
1040
1041/*! @name CMDH - ADC Command High Buffer Register */
1042/*! @{ */
1043#define ADC_CMDH_CMPEN_MASK (0x3U)
1044#define ADC_CMDH_CMPEN_SHIFT (0U)
1045/*! CMPEN - Compare Function Enable
1046 * 0b00..Compare disabled.
1047 * 0b01..Reserved
1048 * 0b10..Compare enabled. Store on true.
1049 * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
1050 */
1051#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
1052#define ADC_CMDH_WAIT_TRIG_MASK (0x4U)
1053#define ADC_CMDH_WAIT_TRIG_SHIFT (2U)
1054/*! WAIT_TRIG - Wait for trigger assertion before execution.
1055 * 0b0..This command will be automatically executed.
1056 * 0b1..The active trigger must be asserted again before executing this command.
1057 */
1058#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK)
1059#define ADC_CMDH_LWI_MASK (0x80U)
1060#define ADC_CMDH_LWI_SHIFT (7U)
1061/*! LWI - Loop with Increment
1062 * 0b0..Auto channel increment disabled
1063 * 0b1..Auto channel increment enabled
1064 */
1065#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
1066#define ADC_CMDH_STS_MASK (0x700U)
1067#define ADC_CMDH_STS_SHIFT (8U)
1068/*! STS - Sample Time Select
1069 * 0b000..Minimum sample time of 3 ADCK cycles.
1070 * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
1071 * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
1072 * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
1073 * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
1074 * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
1075 * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
1076 * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
1077 */
1078#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
1079#define ADC_CMDH_AVGS_MASK (0x7000U)
1080#define ADC_CMDH_AVGS_SHIFT (12U)
1081/*! AVGS - Hardware Average Select
1082 * 0b000..Single conversion.
1083 * 0b001..2 conversions averaged.
1084 * 0b010..4 conversions averaged.
1085 * 0b011..8 conversions averaged.
1086 * 0b100..16 conversions averaged.
1087 * 0b101..32 conversions averaged.
1088 * 0b110..64 conversions averaged.
1089 * 0b111..128 conversions averaged.
1090 */
1091#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
1092#define ADC_CMDH_LOOP_MASK (0xF0000U)
1093#define ADC_CMDH_LOOP_SHIFT (16U)
1094/*! LOOP - Loop Count Select
1095 * 0b0000..Looping not enabled. Command executes 1 time.
1096 * 0b0001..Loop 1 time. Command executes 2 times.
1097 * 0b0010..Loop 2 times. Command executes 3 times.
1098 * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
1099 * 0b1111..Loop 15 times. Command executes 16 times.
1100 */
1101#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
1102#define ADC_CMDH_NEXT_MASK (0xF000000U)
1103#define ADC_CMDH_NEXT_SHIFT (24U)
1104/*! NEXT - Next Command Select
1105 * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
1106 * trigger pending, begin command associated with lower priority trigger.
1107 * 0b0001..Select CMD1 command buffer register as next command.
1108 * 0b0010-0b1110..Select corresponding CMD command buffer register as next command
1109 * 0b1111..Select CMD15 command buffer register as next command.
1110 */
1111#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
1112/*! @} */
1113
1114/* The count of ADC_CMDH */
1115#define ADC_CMDH_COUNT (15U)
1116
1117/*! @name CV - Compare Value Register */
1118/*! @{ */
1119#define ADC_CV_CVL_MASK (0xFFFFU)
1120#define ADC_CV_CVL_SHIFT (0U)
1121/*! CVL - Compare Value Low.
1122 */
1123#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
1124#define ADC_CV_CVH_MASK (0xFFFF0000U)
1125#define ADC_CV_CVH_SHIFT (16U)
1126/*! CVH - Compare Value High.
1127 */
1128#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
1129/*! @} */
1130
1131/* The count of ADC_CV */
1132#define ADC_CV_COUNT (4U)
1133
1134/*! @name RESFIFO - ADC Data Result FIFO Register */
1135/*! @{ */
1136#define ADC_RESFIFO_D_MASK (0xFFFFU)
1137#define ADC_RESFIFO_D_SHIFT (0U)
1138/*! D - Data result
1139 */
1140#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
1141#define ADC_RESFIFO_TSRC_MASK (0xF0000U)
1142#define ADC_RESFIFO_TSRC_SHIFT (16U)
1143/*! TSRC - Trigger Source
1144 * 0b0000..Trigger source 0 initiated this conversion.
1145 * 0b0001..Trigger source 1 initiated this conversion.
1146 * 0b0010-0b1110..Corresponding trigger source initiated this conversion.
1147 * 0b1111..Trigger source 15 initiated this conversion.
1148 */
1149#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
1150#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U)
1151#define ADC_RESFIFO_LOOPCNT_SHIFT (20U)
1152/*! LOOPCNT - Loop count value
1153 * 0b0000..Result is from initial conversion in command.
1154 * 0b0001..Result is from second conversion in command.
1155 * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
1156 * 0b1111..Result is from 16th conversion in command.
1157 */
1158#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
1159#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U)
1160#define ADC_RESFIFO_CMDSRC_SHIFT (24U)
1161/*! CMDSRC - Command Buffer Source
1162 * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
1163 * prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
1164 * 0b0001..CMD1 buffer used as control settings for this conversion.
1165 * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
1166 * 0b1111..CMD15 buffer used as control settings for this conversion.
1167 */
1168#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
1169#define ADC_RESFIFO_VALID_MASK (0x80000000U)
1170#define ADC_RESFIFO_VALID_SHIFT (31U)
1171/*! VALID - FIFO entry is valid
1172 * 0b0..FIFO is empty. Discard any read from RESFIFO.
1173 * 0b1..FIFO record read from RESFIFO is valid.
1174 */
1175#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
1176/*! @} */
1177
1178/* The count of ADC_RESFIFO */
1179#define ADC_RESFIFO_COUNT (2U)
1180
1181/*! @name CAL_GAR - Calibration General A-Side Registers */
1182/*! @{ */
1183#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU)
1184#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U)
1185/*! CAL_GAR_VAL - Calibration General A Side Register Element
1186 */
1187#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK)
1188/*! @} */
1189
1190/* The count of ADC_CAL_GAR */
1191#define ADC_CAL_GAR_COUNT (33U)
1192
1193/*! @name CAL_GBR - Calibration General B-Side Registers */
1194/*! @{ */
1195#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU)
1196#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U)
1197/*! CAL_GBR_VAL - Calibration General B Side Register Element
1198 */
1199#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK)
1200/*! @} */
1201
1202/* The count of ADC_CAL_GBR */
1203#define ADC_CAL_GBR_COUNT (33U)
1204
1205/*! @name TST - ADC Test Register */
1206/*! @{ */
1207#define ADC_TST_CST_LONG_MASK (0x1U)
1208#define ADC_TST_CST_LONG_SHIFT (0U)
1209/*! CST_LONG - Calibration Sample Time Long
1210 * 0b0..Normal sample time. Minimum sample time of 3 ADCK cycles.
1211 * 0b1..Increased sample time. 67 ADCK cycles total sample time.
1212 */
1213#define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK)
1214#define ADC_TST_FOFFM_MASK (0x100U)
1215#define ADC_TST_FOFFM_SHIFT (8U)
1216/*! FOFFM - Force M-side positive offset
1217 * 0b0..Normal operation. No forced offset.
1218 * 0b1..Test configuration. Forced positive offset on MDAC.
1219 */
1220#define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK)
1221#define ADC_TST_FOFFP_MASK (0x200U)
1222#define ADC_TST_FOFFP_SHIFT (9U)
1223/*! FOFFP - Force P-side positive offset
1224 * 0b0..Normal operation. No forced offset.
1225 * 0b1..Test configuration. Forced positive offset on PDAC.
1226 */
1227#define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK)
1228#define ADC_TST_FOFFM2_MASK (0x400U)
1229#define ADC_TST_FOFFM2_SHIFT (10U)
1230/*! FOFFM2 - Force M-side negative offset
1231 * 0b0..Normal operation. No forced offset.
1232 * 0b1..Test configuration. Forced negative offset on MDAC.
1233 */
1234#define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK)
1235#define ADC_TST_FOFFP2_MASK (0x800U)
1236#define ADC_TST_FOFFP2_SHIFT (11U)
1237/*! FOFFP2 - Force P-side negative offset
1238 * 0b0..Normal operation. No forced offset.
1239 * 0b1..Test configuration. Forced negative offset on PDAC.
1240 */
1241#define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK)
1242#define ADC_TST_TESTEN_MASK (0x800000U)
1243#define ADC_TST_TESTEN_SHIFT (23U)
1244/*! TESTEN - Enable test configuration
1245 * 0b0..Normal operation. Test configuration not enabled.
1246 * 0b1..Hardware BIST Test in progress.
1247 */
1248#define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK)
1249/*! @} */
1250
1251
1252/*!
1253 * @}
1254 */ /* end of group ADC_Register_Masks */
1255
1256
1257/* ADC - Peripheral instance base addresses */
1258#if (__ARM_FEATURE_CMSE & 0x2)
1259 /** Peripheral ADC0 base address */
1260 #define ADC0_BASE (0x500A0000u)
1261 /** Peripheral ADC0 base address */
1262 #define ADC0_BASE_NS (0x400A0000u)
1263 /** Peripheral ADC0 base pointer */
1264 #define ADC0 ((ADC_Type *)ADC0_BASE)
1265 /** Peripheral ADC0 base pointer */
1266 #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS)
1267 /** Array initializer of ADC peripheral base addresses */
1268 #define ADC_BASE_ADDRS { ADC0_BASE }
1269 /** Array initializer of ADC peripheral base pointers */
1270 #define ADC_BASE_PTRS { ADC0 }
1271 /** Array initializer of ADC peripheral base addresses */
1272 #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS }
1273 /** Array initializer of ADC peripheral base pointers */
1274 #define ADC_BASE_PTRS_NS { ADC0_NS }
1275#else
1276 /** Peripheral ADC0 base address */
1277 #define ADC0_BASE (0x400A0000u)
1278 /** Peripheral ADC0 base pointer */
1279 #define ADC0 ((ADC_Type *)ADC0_BASE)
1280 /** Array initializer of ADC peripheral base addresses */
1281 #define ADC_BASE_ADDRS { ADC0_BASE }
1282 /** Array initializer of ADC peripheral base pointers */
1283 #define ADC_BASE_PTRS { ADC0 }
1284#endif
1285/** Interrupt vectors for the ADC peripheral type */
1286#define ADC_IRQS { ADC0_IRQn }
1287
1288/*!
1289 * @}
1290 */ /* end of group ADC_Peripheral_Access_Layer */
1291
1292
1293/* ----------------------------------------------------------------------------
1294 -- AHB_SECURE_CTRL Peripheral Access Layer
1295 ---------------------------------------------------------------------------- */
1296
1297/*!
1298 * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer
1299 * @{
1300 */
1301
1302/** AHB_SECURE_CTRL - Register Layout Typedef */
1303typedef struct {
1304 struct { /* offset: 0x0, array step: 0x30 */
1305 __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */
1306 uint8_t RESERVED_0[12];
1307 __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[3]; /**< Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */
1308 uint8_t RESERVED_1[4];
1309 __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */
1310 } SEC_CTRL_FLASH_ROM[1];
1311 struct { /* offset: 0x30, array step: 0x14 */
1312 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */
1313 uint8_t RESERVED_0[12];
1314 __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */
1315 } SEC_CTRL_RAMX[1];
1316 uint8_t RESERVED_0[12];
1317 struct { /* offset: 0x50, array step: 0x18 */
1318 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */
1319 uint8_t RESERVED_0[12];
1320 __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x18, index2*0x4 */
1321 } SEC_CTRL_RAM0[1];
1322 uint8_t RESERVED_1[8];
1323 struct { /* offset: 0x70, array step: 0x18 */
1324 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */
1325 uint8_t RESERVED_0[12];
1326 __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x18, index2*0x4 */
1327 } SEC_CTRL_RAM1[1];
1328 uint8_t RESERVED_2[8];
1329 struct { /* offset: 0x90, array step: 0x18 */
1330 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */
1331 uint8_t RESERVED_0[12];
1332 __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x18, index2*0x4 */
1333 } SEC_CTRL_RAM2[1];
1334 uint8_t RESERVED_3[8];
1335 struct { /* offset: 0xB0, array step: 0x18 */
1336 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */
1337 uint8_t RESERVED_0[12];
1338 __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM3 slaves., array offset: 0xC0, array step: index*0x18, index2*0x4 */
1339 } SEC_CTRL_RAM3[1];
1340 uint8_t RESERVED_4[8];
1341 struct { /* offset: 0xD0, array step: 0x14 */
1342 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */
1343 uint8_t RESERVED_0[12];
1344 __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM4 slaves., array offset: 0xE0, array step: index*0x14, index2*0x4 */
1345 } SEC_CTRL_RAM4[1];
1346 uint8_t RESERVED_5[12];
1347 struct { /* offset: 0xF0, array step: 0x30 */
1348 __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xF0, array step: 0x30 */
1349 uint8_t RESERVED_0[12];
1350 __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */
1351 __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */
1352 __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */
1353 uint8_t RESERVED_1[4];
1354 __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */
1355 __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */
1356 __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */
1357 __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */
1358 } SEC_CTRL_APB_BRIDGE[1];
1359 __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */
1360 __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */
1361 uint8_t RESERVED_6[8];
1362 __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */
1363 __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */
1364 uint8_t RESERVED_7[8];
1365 struct { /* offset: 0x140, array step: 0x14 */
1366 __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */
1367 __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */
1368 uint8_t RESERVED_0[8];
1369 __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */
1370 } SEC_CTRL_AHB_PORT10[1];
1371 uint8_t RESERVED_8[12];
1372 struct { /* offset: 0x160, array step: 0x14 */
1373 __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0x160, array step: 0x14 */
1374 uint8_t RESERVED_0[12];
1375 __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0x170, array step: index*0x14, index2*0x4 */
1376 } SEC_CTRL_USB_HS[1];
1377 uint8_t RESERVED_9[3212];
1378 __I uint32_t SEC_VIO_ADDR[12]; /**< most recent security violation address for AHB port n, array offset: 0xE00, array step: 0x4 */
1379 uint8_t RESERVED_10[80];
1380 __I uint32_t SEC_VIO_MISC_INFO[12]; /**< most recent security violation miscellaneous information for AHB port n, array offset: 0xE80, array step: 0x4 */
1381 uint8_t RESERVED_11[80];
1382 __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */
1383 uint8_t RESERVED_12[124];
1384 __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */
1385 __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */
1386 uint8_t RESERVED_13[8];
1387 __IO uint32_t SEC_CPU_INT_MASK0; /**< Secure Interrupt mask for CPU1, offset: 0xF90 */
1388 __IO uint32_t SEC_CPU_INT_MASK1; /**< Secure Interrupt mask for CPU1, offset: 0xF94 */
1389 uint8_t RESERVED_14[36];
1390 __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */
1391 uint8_t RESERVED_15[16];
1392 __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */
1393 __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */
1394 uint8_t RESERVED_16[20];
1395 __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */
1396 __IO uint32_t CPU1_LOCK_REG; /**< Miscalleneous control signals for in micro-Cortex M33 (CPU1), offset: 0xFF0 */
1397 uint8_t RESERVED_17[4];
1398 __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */
1399 __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */
1400} AHB_SECURE_CTRL_Type;
1401
1402/* ----------------------------------------------------------------------------
1403 -- AHB_SECURE_CTRL Register Masks
1404 ---------------------------------------------------------------------------- */
1405
1406/*!
1407 * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks
1408 * @{
1409 */
1410
1411/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */
1412/*! @{ */
1413#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U)
1414#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U)
1415/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF
1416 * 0b00..Non-secure and Non-priviledge user access allowed.
1417 * 0b01..Non-secure and Privilege access allowed.
1418 * 0b10..Secure and Non-priviledge user access allowed.
1419 * 0b11..Secure and Priviledge user access allowed.
1420 */
1421#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK)
1422#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U)
1423#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U)
1424/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF
1425 * 0b00..Non-secure and Non-priviledge user access allowed.
1426 * 0b01..Non-secure and Privilege access allowed.
1427 * 0b10..Secure and Non-priviledge user access allowed.
1428 * 0b11..Secure and Priviledge user access allowed.
1429 */
1430#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK)
1431/*! @} */
1432
1433/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */
1434#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U)
1435
1436/*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */
1437/*! @{ */
1438#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U)
1439#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U)
1440/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1441 * 0b00..Non-secure and Non-priviledge user access allowed.
1442 * 0b01..Non-secure and Privilege access allowed.
1443 * 0b10..Secure and Non-priviledge user access allowed.
1444 * 0b11..Secure and Priviledge user access allowed.
1445 */
1446#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK)
1447#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U)
1448#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U)
1449/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1450 * 0b00..Non-secure and Non-priviledge user access allowed.
1451 * 0b01..Non-secure and Privilege access allowed.
1452 * 0b10..Secure and Non-priviledge user access allowed.
1453 * 0b11..Secure and Priviledge user access allowed.
1454 */
1455#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK)
1456#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U)
1457#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U)
1458/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1459 * 0b00..Non-secure and Non-priviledge user access allowed.
1460 * 0b01..Non-secure and Privilege access allowed.
1461 * 0b10..Secure and Non-priviledge user access allowed.
1462 * 0b11..Secure and Priviledge user access allowed.
1463 */
1464#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK)
1465#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U)
1466#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U)
1467/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1468 * 0b00..Non-secure and Non-priviledge user access allowed.
1469 * 0b01..Non-secure and Privilege access allowed.
1470 * 0b10..Secure and Non-priviledge user access allowed.
1471 * 0b11..Secure and Priviledge user access allowed.
1472 */
1473#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK)
1474#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U)
1475#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U)
1476/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1477 * 0b00..Non-secure and Non-priviledge user access allowed.
1478 * 0b01..Non-secure and Privilege access allowed.
1479 * 0b10..Secure and Non-priviledge user access allowed.
1480 * 0b11..Secure and Priviledge user access allowed.
1481 */
1482#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK)
1483#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U)
1484#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U)
1485/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1486 * 0b00..Non-secure and Non-priviledge user access allowed.
1487 * 0b01..Non-secure and Privilege access allowed.
1488 * 0b10..Secure and Non-priviledge user access allowed.
1489 * 0b11..Secure and Priviledge user access allowed.
1490 */
1491#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK)
1492#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U)
1493#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U)
1494/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1495 * 0b00..Non-secure and Non-priviledge user access allowed.
1496 * 0b01..Non-secure and Privilege access allowed.
1497 * 0b10..Secure and Non-priviledge user access allowed.
1498 * 0b11..Secure and Priviledge user access allowed.
1499 */
1500#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK)
1501#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U)
1502#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U)
1503/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1504 * 0b00..Non-secure and Non-priviledge user access allowed.
1505 * 0b01..Non-secure and Privilege access allowed.
1506 * 0b10..Secure and Non-priviledge user access allowed.
1507 * 0b11..Secure and Priviledge user access allowed.
1508 */
1509#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK)
1510/*! @} */
1511
1512/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */
1513#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U)
1514
1515/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */
1516#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U)
1517
1518/*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */
1519/*! @{ */
1520#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U)
1521#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U)
1522/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1523 * 0b00..Non-secure and Non-priviledge user access allowed.
1524 * 0b01..Non-secure and Privilege access allowed.
1525 * 0b10..Secure and Non-priviledge user access allowed.
1526 * 0b11..Secure and Priviledge user access allowed.
1527 */
1528#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK)
1529#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U)
1530#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U)
1531/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1532 * 0b00..Non-secure and Non-priviledge user access allowed.
1533 * 0b01..Non-secure and Privilege access allowed.
1534 * 0b10..Secure and Non-priviledge user access allowed.
1535 * 0b11..Secure and Priviledge user access allowed.
1536 */
1537#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK)
1538#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U)
1539#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U)
1540/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1541 * 0b00..Non-secure and Non-priviledge user access allowed.
1542 * 0b01..Non-secure and Privilege access allowed.
1543 * 0b10..Secure and Non-priviledge user access allowed.
1544 * 0b11..Secure and Priviledge user access allowed.
1545 */
1546#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK)
1547#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U)
1548#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U)
1549/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1550 * 0b00..Non-secure and Non-priviledge user access allowed.
1551 * 0b01..Non-secure and Privilege access allowed.
1552 * 0b10..Secure and Non-priviledge user access allowed.
1553 * 0b11..Secure and Priviledge user access allowed.
1554 */
1555#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK)
1556#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U)
1557#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U)
1558/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1559 * 0b00..Non-secure and Non-priviledge user access allowed.
1560 * 0b01..Non-secure and Privilege access allowed.
1561 * 0b10..Secure and Non-priviledge user access allowed.
1562 * 0b11..Secure and Priviledge user access allowed.
1563 */
1564#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK)
1565#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U)
1566#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U)
1567/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1568 * 0b00..Non-secure and Non-priviledge user access allowed.
1569 * 0b01..Non-secure and Privilege access allowed.
1570 * 0b10..Secure and Non-priviledge user access allowed.
1571 * 0b11..Secure and Priviledge user access allowed.
1572 */
1573#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK)
1574#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U)
1575#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U)
1576/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1577 * 0b00..Non-secure and Non-priviledge user access allowed.
1578 * 0b01..Non-secure and Privilege access allowed.
1579 * 0b10..Secure and Non-priviledge user access allowed.
1580 * 0b11..Secure and Priviledge user access allowed.
1581 */
1582#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK)
1583#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U)
1584#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U)
1585/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1586 * 0b00..Non-secure and Non-priviledge user access allowed.
1587 * 0b01..Non-secure and Privilege access allowed.
1588 * 0b10..Secure and Non-priviledge user access allowed.
1589 * 0b11..Secure and Priviledge user access allowed.
1590 */
1591#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK)
1592/*! @} */
1593
1594/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */
1595#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U)
1596
1597/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */
1598#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U)
1599
1600/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */
1601/*! @{ */
1602#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U)
1603#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U)
1604/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF
1605 * 0b00..Non-secure and Non-priviledge user access allowed.
1606 * 0b01..Non-secure and Privilege access allowed.
1607 * 0b10..Secure and Non-priviledge user access allowed.
1608 * 0b11..Secure and Priviledge user access allowed.
1609 */
1610#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK)
1611/*! @} */
1612
1613/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */
1614#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U)
1615
1616/*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */
1617/*! @{ */
1618#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U)
1619#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U)
1620/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1621 * 0b00..Non-secure and Non-priviledge user access allowed.
1622 * 0b01..Non-secure and Privilege access allowed.
1623 * 0b10..Secure and Non-priviledge user access allowed.
1624 * 0b11..Secure and Priviledge user access allowed.
1625 */
1626#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK)
1627#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U)
1628#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U)
1629/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1630 * 0b00..Non-secure and Non-priviledge user access allowed.
1631 * 0b01..Non-secure and Privilege access allowed.
1632 * 0b10..Secure and Non-priviledge user access allowed.
1633 * 0b11..Secure and Priviledge user access allowed.
1634 */
1635#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK)
1636#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U)
1637#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U)
1638/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1639 * 0b00..Non-secure and Non-priviledge user access allowed.
1640 * 0b01..Non-secure and Privilege access allowed.
1641 * 0b10..Secure and Non-priviledge user access allowed.
1642 * 0b11..Secure and Priviledge user access allowed.
1643 */
1644#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK)
1645#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U)
1646#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U)
1647/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1648 * 0b00..Non-secure and Non-priviledge user access allowed.
1649 * 0b01..Non-secure and Privilege access allowed.
1650 * 0b10..Secure and Non-priviledge user access allowed.
1651 * 0b11..Secure and Priviledge user access allowed.
1652 */
1653#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK)
1654#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK (0x30000U)
1655#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT (16U)
1656/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1657 * 0b00..Non-secure and Non-priviledge user access allowed.
1658 * 0b01..Non-secure and Privilege access allowed.
1659 * 0b10..Secure and Non-priviledge user access allowed.
1660 * 0b11..Secure and Priviledge user access allowed.
1661 */
1662#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK)
1663#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK (0x300000U)
1664#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT (20U)
1665/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1666 * 0b00..Non-secure and Non-priviledge user access allowed.
1667 * 0b01..Non-secure and Privilege access allowed.
1668 * 0b10..Secure and Non-priviledge user access allowed.
1669 * 0b11..Secure and Priviledge user access allowed.
1670 */
1671#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK)
1672#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK (0x3000000U)
1673#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT (24U)
1674/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1675 * 0b00..Non-secure and Non-priviledge user access allowed.
1676 * 0b01..Non-secure and Privilege access allowed.
1677 * 0b10..Secure and Non-priviledge user access allowed.
1678 * 0b11..Secure and Priviledge user access allowed.
1679 */
1680#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK)
1681#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK (0x30000000U)
1682#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT (28U)
1683/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1684 * 0b00..Non-secure and Non-priviledge user access allowed.
1685 * 0b01..Non-secure and Privilege access allowed.
1686 * 0b10..Secure and Non-priviledge user access allowed.
1687 * 0b11..Secure and Priviledge user access allowed.
1688 */
1689#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK)
1690/*! @} */
1691
1692/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */
1693#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U)
1694
1695/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */
1696#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U)
1697
1698/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */
1699/*! @{ */
1700#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U)
1701#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U)
1702/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF
1703 * 0b00..Non-secure and Non-priviledge user access allowed.
1704 * 0b01..Non-secure and Privilege access allowed.
1705 * 0b10..Secure and Non-priviledge user access allowed.
1706 * 0b11..Secure and Priviledge user access allowed.
1707 */
1708#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK)
1709/*! @} */
1710
1711/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */
1712#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U)
1713
1714/*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */
1715/*! @{ */
1716#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U)
1717#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U)
1718/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1719 * 0b00..Non-secure and Non-priviledge user access allowed.
1720 * 0b01..Non-secure and Privilege access allowed.
1721 * 0b10..Secure and Non-priviledge user access allowed.
1722 * 0b11..Secure and Priviledge user access allowed.
1723 */
1724#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK)
1725#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U)
1726#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U)
1727/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1728 * 0b00..Non-secure and Non-priviledge user access allowed.
1729 * 0b01..Non-secure and Privilege access allowed.
1730 * 0b10..Secure and Non-priviledge user access allowed.
1731 * 0b11..Secure and Priviledge user access allowed.
1732 */
1733#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK)
1734#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U)
1735#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U)
1736/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1737 * 0b00..Non-secure and Non-priviledge user access allowed.
1738 * 0b01..Non-secure and Privilege access allowed.
1739 * 0b10..Secure and Non-priviledge user access allowed.
1740 * 0b11..Secure and Priviledge user access allowed.
1741 */
1742#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK)
1743#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U)
1744#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U)
1745/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1746 * 0b00..Non-secure and Non-priviledge user access allowed.
1747 * 0b01..Non-secure and Privilege access allowed.
1748 * 0b10..Secure and Non-priviledge user access allowed.
1749 * 0b11..Secure and Priviledge user access allowed.
1750 */
1751#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK)
1752#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U)
1753#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U)
1754/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1755 * 0b00..Non-secure and Non-priviledge user access allowed.
1756 * 0b01..Non-secure and Privilege access allowed.
1757 * 0b10..Secure and Non-priviledge user access allowed.
1758 * 0b11..Secure and Priviledge user access allowed.
1759 */
1760#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK)
1761#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U)
1762#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U)
1763/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1764 * 0b00..Non-secure and Non-priviledge user access allowed.
1765 * 0b01..Non-secure and Privilege access allowed.
1766 * 0b10..Secure and Non-priviledge user access allowed.
1767 * 0b11..Secure and Priviledge user access allowed.
1768 */
1769#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK)
1770#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U)
1771#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U)
1772/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1773 * 0b00..Non-secure and Non-priviledge user access allowed.
1774 * 0b01..Non-secure and Privilege access allowed.
1775 * 0b10..Secure and Non-priviledge user access allowed.
1776 * 0b11..Secure and Priviledge user access allowed.
1777 */
1778#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK)
1779#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U)
1780#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U)
1781/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1782 * 0b00..Non-secure and Non-priviledge user access allowed.
1783 * 0b01..Non-secure and Privilege access allowed.
1784 * 0b10..Secure and Non-priviledge user access allowed.
1785 * 0b11..Secure and Priviledge user access allowed.
1786 */
1787#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK)
1788/*! @} */
1789
1790/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */
1791#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U)
1792
1793/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */
1794#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (2U)
1795
1796/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */
1797/*! @{ */
1798#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U)
1799#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U)
1800/*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0
1801 * 0b00..Non-secure and Non-priviledge user access allowed.
1802 * 0b01..Non-secure and Privilege access allowed.
1803 * 0b10..Secure and Non-priviledge user access allowed.
1804 * 0b11..Secure and Priviledge user access allowed.
1805 */
1806#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK)
1807/*! @} */
1808
1809/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */
1810#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U)
1811
1812/*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */
1813/*! @{ */
1814#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U)
1815#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U)
1816/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1817 * 0b00..Non-secure and Non-priviledge user access allowed.
1818 * 0b01..Non-secure and Privilege access allowed.
1819 * 0b10..Secure and Non-priviledge user access allowed.
1820 * 0b11..Secure and Priviledge user access allowed.
1821 */
1822#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK)
1823#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U)
1824#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U)
1825/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1826 * 0b00..Non-secure and Non-priviledge user access allowed.
1827 * 0b01..Non-secure and Privilege access allowed.
1828 * 0b10..Secure and Non-priviledge user access allowed.
1829 * 0b11..Secure and Priviledge user access allowed.
1830 */
1831#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK)
1832#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U)
1833#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U)
1834/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1835 * 0b00..Non-secure and Non-priviledge user access allowed.
1836 * 0b01..Non-secure and Privilege access allowed.
1837 * 0b10..Secure and Non-priviledge user access allowed.
1838 * 0b11..Secure and Priviledge user access allowed.
1839 */
1840#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK)
1841#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U)
1842#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U)
1843/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1844 * 0b00..Non-secure and Non-priviledge user access allowed.
1845 * 0b01..Non-secure and Privilege access allowed.
1846 * 0b10..Secure and Non-priviledge user access allowed.
1847 * 0b11..Secure and Priviledge user access allowed.
1848 */
1849#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK)
1850#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK (0x30000U)
1851#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT (16U)
1852/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1853 * 0b00..Non-secure and Non-priviledge user access allowed.
1854 * 0b01..Non-secure and Privilege access allowed.
1855 * 0b10..Secure and Non-priviledge user access allowed.
1856 * 0b11..Secure and Priviledge user access allowed.
1857 */
1858#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK)
1859#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK (0x300000U)
1860#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT (20U)
1861/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1862 * 0b00..Non-secure and Non-priviledge user access allowed.
1863 * 0b01..Non-secure and Privilege access allowed.
1864 * 0b10..Secure and Non-priviledge user access allowed.
1865 * 0b11..Secure and Priviledge user access allowed.
1866 */
1867#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK)
1868#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK (0x3000000U)
1869#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT (24U)
1870/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1871 * 0b00..Non-secure and Non-priviledge user access allowed.
1872 * 0b01..Non-secure and Privilege access allowed.
1873 * 0b10..Secure and Non-priviledge user access allowed.
1874 * 0b11..Secure and Priviledge user access allowed.
1875 */
1876#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK)
1877#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK (0x30000000U)
1878#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT (28U)
1879/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1880 * 0b00..Non-secure and Non-priviledge user access allowed.
1881 * 0b01..Non-secure and Privilege access allowed.
1882 * 0b10..Secure and Non-priviledge user access allowed.
1883 * 0b11..Secure and Priviledge user access allowed.
1884 */
1885#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK)
1886/*! @} */
1887
1888/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */
1889#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U)
1890
1891/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */
1892#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (2U)
1893
1894/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */
1895/*! @{ */
1896#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U)
1897#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U)
1898/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF
1899 * 0b00..Non-secure and Non-priviledge user access allowed.
1900 * 0b01..Non-secure and Privilege access allowed.
1901 * 0b10..Secure and Non-priviledge user access allowed.
1902 * 0b11..Secure and Priviledge user access allowed.
1903 */
1904#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK)
1905/*! @} */
1906
1907/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */
1908#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U)
1909
1910/*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */
1911/*! @{ */
1912#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U)
1913#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U)
1914/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1915 * 0b00..Non-secure and Non-priviledge user access allowed.
1916 * 0b01..Non-secure and Privilege access allowed.
1917 * 0b10..Secure and Non-priviledge user access allowed.
1918 * 0b11..Secure and Priviledge user access allowed.
1919 */
1920#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK)
1921#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U)
1922#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U)
1923/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1924 * 0b00..Non-secure and Non-priviledge user access allowed.
1925 * 0b01..Non-secure and Privilege access allowed.
1926 * 0b10..Secure and Non-priviledge user access allowed.
1927 * 0b11..Secure and Priviledge user access allowed.
1928 */
1929#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK)
1930#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U)
1931#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U)
1932/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1933 * 0b00..Non-secure and Non-priviledge user access allowed.
1934 * 0b01..Non-secure and Privilege access allowed.
1935 * 0b10..Secure and Non-priviledge user access allowed.
1936 * 0b11..Secure and Priviledge user access allowed.
1937 */
1938#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK)
1939#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U)
1940#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U)
1941/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1942 * 0b00..Non-secure and Non-priviledge user access allowed.
1943 * 0b01..Non-secure and Privilege access allowed.
1944 * 0b10..Secure and Non-priviledge user access allowed.
1945 * 0b11..Secure and Priviledge user access allowed.
1946 */
1947#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK)
1948#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK (0x30000U)
1949#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT (16U)
1950/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1951 * 0b00..Non-secure and Non-priviledge user access allowed.
1952 * 0b01..Non-secure and Privilege access allowed.
1953 * 0b10..Secure and Non-priviledge user access allowed.
1954 * 0b11..Secure and Priviledge user access allowed.
1955 */
1956#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK)
1957#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK (0x300000U)
1958#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT (20U)
1959/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1960 * 0b00..Non-secure and Non-priviledge user access allowed.
1961 * 0b01..Non-secure and Privilege access allowed.
1962 * 0b10..Secure and Non-priviledge user access allowed.
1963 * 0b11..Secure and Priviledge user access allowed.
1964 */
1965#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK)
1966#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK (0x3000000U)
1967#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT (24U)
1968/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1969 * 0b00..Non-secure and Non-priviledge user access allowed.
1970 * 0b01..Non-secure and Privilege access allowed.
1971 * 0b10..Secure and Non-priviledge user access allowed.
1972 * 0b11..Secure and Priviledge user access allowed.
1973 */
1974#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK)
1975#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK (0x30000000U)
1976#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT (28U)
1977/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1978 * 0b00..Non-secure and Non-priviledge user access allowed.
1979 * 0b01..Non-secure and Privilege access allowed.
1980 * 0b10..Secure and Non-priviledge user access allowed.
1981 * 0b11..Secure and Priviledge user access allowed.
1982 */
1983#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK)
1984/*! @} */
1985
1986/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */
1987#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U)
1988
1989/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */
1990#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (2U)
1991
1992/*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */
1993/*! @{ */
1994#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U)
1995#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U)
1996/*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF
1997 * 0b00..Non-secure and Non-priviledge user access allowed.
1998 * 0b01..Non-secure and Privilege access allowed.
1999 * 0b10..Secure and Non-priviledge user access allowed.
2000 * 0b11..Secure and Priviledge user access allowed.
2001 */
2002#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK)
2003/*! @} */
2004
2005/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */
2006#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U)
2007
2008/*! @name SEC_CTRL_RAM3_MEM_RULE - Security access rules for RAM3 slaves. */
2009/*! @{ */
2010#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK (0x3U)
2011#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT (0U)
2012/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
2013 * 0b00..Non-secure and Non-priviledge user access allowed.
2014 * 0b01..Non-secure and Privilege access allowed.
2015 * 0b10..Secure and Non-priviledge user access allowed.
2016 * 0b11..Secure and Priviledge user access allowed.
2017 */
2018#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK)
2019#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK (0x30U)
2020#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT (4U)
2021/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
2022 * 0b00..Non-secure and Non-priviledge user access allowed.
2023 * 0b01..Non-secure and Privilege access allowed.
2024 * 0b10..Secure and Non-priviledge user access allowed.
2025 * 0b11..Secure and Priviledge user access allowed.
2026 */
2027#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK)
2028#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK (0x300U)
2029#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT (8U)
2030/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
2031 * 0b00..Non-secure and Non-priviledge user access allowed.
2032 * 0b01..Non-secure and Privilege access allowed.
2033 * 0b10..Secure and Non-priviledge user access allowed.
2034 * 0b11..Secure and Priviledge user access allowed.
2035 */
2036#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK)
2037#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK (0x3000U)
2038#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT (12U)
2039/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
2040 * 0b00..Non-secure and Non-priviledge user access allowed.
2041 * 0b01..Non-secure and Privilege access allowed.
2042 * 0b10..Secure and Non-priviledge user access allowed.
2043 * 0b11..Secure and Priviledge user access allowed.
2044 */
2045#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK)
2046#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK (0x30000U)
2047#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT (16U)
2048/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
2049 * 0b00..Non-secure and Non-priviledge user access allowed.
2050 * 0b01..Non-secure and Privilege access allowed.
2051 * 0b10..Secure and Non-priviledge user access allowed.
2052 * 0b11..Secure and Priviledge user access allowed.
2053 */
2054#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK)
2055#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK (0x300000U)
2056#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT (20U)
2057/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
2058 * 0b00..Non-secure and Non-priviledge user access allowed.
2059 * 0b01..Non-secure and Privilege access allowed.
2060 * 0b10..Secure and Non-priviledge user access allowed.
2061 * 0b11..Secure and Priviledge user access allowed.
2062 */
2063#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK)
2064#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK (0x3000000U)
2065#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT (24U)
2066/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
2067 * 0b00..Non-secure and Non-priviledge user access allowed.
2068 * 0b01..Non-secure and Privilege access allowed.
2069 * 0b10..Secure and Non-priviledge user access allowed.
2070 * 0b11..Secure and Priviledge user access allowed.
2071 */
2072#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK)
2073#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK (0x30000000U)
2074#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT (28U)
2075/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
2076 * 0b00..Non-secure and Non-priviledge user access allowed.
2077 * 0b01..Non-secure and Privilege access allowed.
2078 * 0b10..Secure and Non-priviledge user access allowed.
2079 * 0b11..Secure and Priviledge user access allowed.
2080 */
2081#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK)
2082/*! @} */
2083
2084/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */
2085#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT (1U)
2086
2087/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */
2088#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT2 (2U)
2089
2090/*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */
2091/*! @{ */
2092#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U)
2093#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U)
2094/*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF
2095 * 0b00..Non-secure and Non-priviledge user access allowed.
2096 * 0b01..Non-secure and Privilege access allowed.
2097 * 0b10..Secure and Non-priviledge user access allowed.
2098 * 0b11..Secure and Priviledge user access allowed.
2099 */
2100#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK)
2101/*! @} */
2102
2103/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */
2104#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U)
2105
2106/*! @name SEC_CTRL_RAM4_MEM_RULE - Security access rules for RAM4 slaves. */
2107/*! @{ */
2108#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK (0x3U)
2109#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT (0U)
2110/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
2111 * 0b00..Non-secure and Non-priviledge user access allowed.
2112 * 0b01..Non-secure and Privilege access allowed.
2113 * 0b10..Secure and Non-priviledge user access allowed.
2114 * 0b11..Secure and Priviledge user access allowed.
2115 */
2116#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK)
2117#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK (0x30U)
2118#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT (4U)
2119/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
2120 * 0b00..Non-secure and Non-priviledge user access allowed.
2121 * 0b01..Non-secure and Privilege access allowed.
2122 * 0b10..Secure and Non-priviledge user access allowed.
2123 * 0b11..Secure and Priviledge user access allowed.
2124 */
2125#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK)
2126#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK (0x300U)
2127#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT (8U)
2128/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
2129 * 0b00..Non-secure and Non-priviledge user access allowed.
2130 * 0b01..Non-secure and Privilege access allowed.
2131 * 0b10..Secure and Non-priviledge user access allowed.
2132 * 0b11..Secure and Priviledge user access allowed.
2133 */
2134#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK)
2135#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK (0x3000U)
2136#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT (12U)
2137/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
2138 * 0b00..Non-secure and Non-priviledge user access allowed.
2139 * 0b01..Non-secure and Privilege access allowed.
2140 * 0b10..Secure and Non-priviledge user access allowed.
2141 * 0b11..Secure and Priviledge user access allowed.
2142 */
2143#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK)
2144/*! @} */
2145
2146/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */
2147#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT (1U)
2148
2149/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */
2150#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT2 (1U)
2151
2152/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */
2153/*! @{ */
2154#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U)
2155#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U)
2156/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0
2157 * 0b00..Non-secure and Non-priviledge user access allowed.
2158 * 0b01..Non-secure and Privilege access allowed.
2159 * 0b10..Secure and Non-priviledge user access allowed.
2160 * 0b11..Secure and Priviledge user access allowed.
2161 */
2162#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK)
2163#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U)
2164#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U)
2165/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1
2166 * 0b00..Non-secure and Non-priviledge user access allowed.
2167 * 0b01..Non-secure and Privilege access allowed.
2168 * 0b10..Secure and Non-priviledge user access allowed.
2169 * 0b11..Secure and Priviledge user access allowed.
2170 */
2171#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK)
2172/*! @} */
2173
2174/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */
2175#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U)
2176
2177/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
2178/*! @{ */
2179#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U)
2180#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U)
2181/*! SYSCON_RULE - System Configuration
2182 * 0b00..Non-secure and Non-priviledge user access allowed.
2183 * 0b01..Non-secure and Privilege access allowed.
2184 * 0b10..Secure and Non-priviledge user access allowed.
2185 * 0b11..Secure and Priviledge user access allowed.
2186 */
2187#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK)
2188#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U)
2189#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U)
2190/*! IOCON_RULE - I/O Configuration
2191 * 0b00..Non-secure and Non-priviledge user access allowed.
2192 * 0b01..Non-secure and Privilege access allowed.
2193 * 0b10..Secure and Non-priviledge user access allowed.
2194 * 0b11..Secure and Priviledge user access allowed.
2195 */
2196#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK)
2197#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U)
2198#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U)
2199/*! GINT0_RULE - GPIO input Interrupt 0
2200 * 0b00..Non-secure and Non-priviledge user access allowed.
2201 * 0b01..Non-secure and Privilege access allowed.
2202 * 0b10..Secure and Non-priviledge user access allowed.
2203 * 0b11..Secure and Priviledge user access allowed.
2204 */
2205#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK)
2206#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U)
2207#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U)
2208/*! GINT1_RULE - GPIO input Interrupt 1
2209 * 0b00..Non-secure and Non-priviledge user access allowed.
2210 * 0b01..Non-secure and Privilege access allowed.
2211 * 0b10..Secure and Non-priviledge user access allowed.
2212 * 0b11..Secure and Priviledge user access allowed.
2213 */
2214#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK)
2215#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U)
2216#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U)
2217/*! PINT_RULE - Pin Interrupt and Pattern match
2218 * 0b00..Non-secure and Non-priviledge user access allowed.
2219 * 0b01..Non-secure and Privilege access allowed.
2220 * 0b10..Secure and Non-priviledge user access allowed.
2221 * 0b11..Secure and Priviledge user access allowed.
2222 */
2223#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK)
2224#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U)
2225#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U)
2226/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match
2227 * 0b00..Non-secure and Non-priviledge user access allowed.
2228 * 0b01..Non-secure and Privilege access allowed.
2229 * 0b10..Secure and Non-priviledge user access allowed.
2230 * 0b11..Secure and Priviledge user access allowed.
2231 */
2232#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK)
2233#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U)
2234#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U)
2235/*! INPUTMUX_RULE - Peripheral input multiplexing
2236 * 0b00..Non-secure and Non-priviledge user access allowed.
2237 * 0b01..Non-secure and Privilege access allowed.
2238 * 0b10..Secure and Non-priviledge user access allowed.
2239 * 0b11..Secure and Priviledge user access allowed.
2240 */
2241#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK)
2242/*! @} */
2243
2244/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */
2245#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U)
2246
2247/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
2248/*! @{ */
2249#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U)
2250#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U)
2251/*! CTIMER0_RULE - Standard counter/Timer 0
2252 * 0b00..Non-secure and Non-priviledge user access allowed.
2253 * 0b01..Non-secure and Privilege access allowed.
2254 * 0b10..Secure and Non-priviledge user access allowed.
2255 * 0b11..Secure and Priviledge user access allowed.
2256 */
2257#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK)
2258#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U)
2259#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U)
2260/*! CTIMER1_RULE - Standard counter/Timer 1
2261 * 0b00..Non-secure and Non-priviledge user access allowed.
2262 * 0b01..Non-secure and Privilege access allowed.
2263 * 0b10..Secure and Non-priviledge user access allowed.
2264 * 0b11..Secure and Priviledge user access allowed.
2265 */
2266#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK)
2267#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U)
2268#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U)
2269/*! WWDT_RULE - Windiwed wtachdog Timer
2270 * 0b00..Non-secure and Non-priviledge user access allowed.
2271 * 0b01..Non-secure and Privilege access allowed.
2272 * 0b10..Secure and Non-priviledge user access allowed.
2273 * 0b11..Secure and Priviledge user access allowed.
2274 */
2275#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK)
2276#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U)
2277#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U)
2278/*! MRT_RULE - Multi-rate Timer
2279 * 0b00..Non-secure and Non-priviledge user access allowed.
2280 * 0b01..Non-secure and Privilege access allowed.
2281 * 0b10..Secure and Non-priviledge user access allowed.
2282 * 0b11..Secure and Priviledge user access allowed.
2283 */
2284#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK)
2285#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U)
2286#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U)
2287/*! UTICK_RULE - Micro-Timer
2288 * 0b00..Non-secure and Non-priviledge user access allowed.
2289 * 0b01..Non-secure and Privilege access allowed.
2290 * 0b10..Secure and Non-priviledge user access allowed.
2291 * 0b11..Secure and Priviledge user access allowed.
2292 */
2293#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK)
2294/*! @} */
2295
2296/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */
2297#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U)
2298
2299/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
2300/*! @{ */
2301#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U)
2302#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U)
2303/*! ANACTRL_RULE - Analog Modules controller
2304 * 0b00..Non-secure and Non-priviledge user access allowed.
2305 * 0b01..Non-secure and Privilege access allowed.
2306 * 0b10..Secure and Non-priviledge user access allowed.
2307 * 0b11..Secure and Priviledge user access allowed.
2308 */
2309#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK)
2310/*! @} */
2311
2312/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */
2313#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U)
2314
2315/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2316/*! @{ */
2317#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U)
2318#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U)
2319/*! PMC_RULE - Power Management Controller
2320 * 0b00..Non-secure and Non-priviledge user access allowed.
2321 * 0b01..Non-secure and Privilege access allowed.
2322 * 0b10..Secure and Non-priviledge user access allowed.
2323 * 0b11..Secure and Priviledge user access allowed.
2324 */
2325#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK)
2326#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U)
2327#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U)
2328/*! SYSCTRL_RULE - System Controller
2329 * 0b00..Non-secure and Non-priviledge user access allowed.
2330 * 0b01..Non-secure and Privilege access allowed.
2331 * 0b10..Secure and Non-priviledge user access allowed.
2332 * 0b11..Secure and Priviledge user access allowed.
2333 */
2334#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK)
2335/*! @} */
2336
2337/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */
2338#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U)
2339
2340/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2341/*! @{ */
2342#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U)
2343#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U)
2344/*! CTIMER2_RULE - Standard counter/Timer 2
2345 * 0b00..Non-secure and Non-priviledge user access allowed.
2346 * 0b01..Non-secure and Privilege access allowed.
2347 * 0b10..Secure and Non-priviledge user access allowed.
2348 * 0b11..Secure and Priviledge user access allowed.
2349 */
2350#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK)
2351#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U)
2352#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U)
2353/*! CTIMER3_RULE - Standard counter/Timer 3
2354 * 0b00..Non-secure and Non-priviledge user access allowed.
2355 * 0b01..Non-secure and Privilege access allowed.
2356 * 0b10..Secure and Non-priviledge user access allowed.
2357 * 0b11..Secure and Priviledge user access allowed.
2358 */
2359#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK)
2360#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U)
2361#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U)
2362/*! CTIMER4_RULE - Standard counter/Timer 4
2363 * 0b00..Non-secure and Non-priviledge user access allowed.
2364 * 0b01..Non-secure and Privilege access allowed.
2365 * 0b10..Secure and Non-priviledge user access allowed.
2366 * 0b11..Secure and Priviledge user access allowed.
2367 */
2368#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK)
2369#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U)
2370#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U)
2371/*! RTC_RULE - Real Time Counter
2372 * 0b00..Non-secure and Non-priviledge user access allowed.
2373 * 0b01..Non-secure and Privilege access allowed.
2374 * 0b10..Secure and Non-priviledge user access allowed.
2375 * 0b11..Secure and Priviledge user access allowed.
2376 */
2377#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK)
2378#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U)
2379#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U)
2380/*! OSEVENT_RULE - OS Event Timer
2381 * 0b00..Non-secure and Non-priviledge user access allowed.
2382 * 0b01..Non-secure and Privilege access allowed.
2383 * 0b10..Secure and Non-priviledge user access allowed.
2384 * 0b11..Secure and Priviledge user access allowed.
2385 */
2386#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK)
2387/*! @} */
2388
2389/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */
2390#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U)
2391
2392/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2393/*! @{ */
2394#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U)
2395#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U)
2396/*! FLASH_CTRL_RULE - Flash Controller
2397 * 0b00..Non-secure and Non-priviledge user access allowed.
2398 * 0b01..Non-secure and Privilege access allowed.
2399 * 0b10..Secure and Non-priviledge user access allowed.
2400 * 0b11..Secure and Priviledge user access allowed.
2401 */
2402#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK)
2403#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U)
2404#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U)
2405/*! PRINCE_RULE - Prince
2406 * 0b00..Non-secure and Non-priviledge user access allowed.
2407 * 0b01..Non-secure and Privilege access allowed.
2408 * 0b10..Secure and Non-priviledge user access allowed.
2409 * 0b11..Secure and Priviledge user access allowed.
2410 */
2411#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK)
2412/*! @} */
2413
2414/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */
2415#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U)
2416
2417/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2418/*! @{ */
2419#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U)
2420#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U)
2421/*! USBHPHY_RULE - USB High Speed Phy controller
2422 * 0b00..Non-secure and Non-priviledge user access allowed.
2423 * 0b01..Non-secure and Privilege access allowed.
2424 * 0b10..Secure and Non-priviledge user access allowed.
2425 * 0b11..Secure and Priviledge user access allowed.
2426 */
2427#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK)
2428#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U)
2429#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U)
2430/*! RNG_RULE - True Random Number Generator
2431 * 0b00..Non-secure and Non-priviledge user access allowed.
2432 * 0b01..Non-secure and Privilege access allowed.
2433 * 0b10..Secure and Non-priviledge user access allowed.
2434 * 0b11..Secure and Priviledge user access allowed.
2435 */
2436#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK)
2437#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U)
2438#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U)
2439/*! PUF_RULE - PUF
2440 * 0b00..Non-secure and Non-priviledge user access allowed.
2441 * 0b01..Non-secure and Privilege access allowed.
2442 * 0b10..Secure and Non-priviledge user access allowed.
2443 * 0b11..Secure and Priviledge user access allowed.
2444 */
2445#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK)
2446#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U)
2447#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U)
2448/*! PLU_RULE - Programmable Look-Up logic
2449 * 0b00..Non-secure and Non-priviledge user access allowed.
2450 * 0b01..Non-secure and Privilege access allowed.
2451 * 0b10..Secure and Non-priviledge user access allowed.
2452 * 0b11..Secure and Priviledge user access allowed.
2453 */
2454#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK)
2455/*! @} */
2456
2457/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */
2458#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U)
2459
2460/*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */
2461/*! @{ */
2462#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK (0x300U)
2463#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT (8U)
2464/*! DMA0_RULE - DMA Controller
2465 * 0b00..Non-secure and Non-priviledge user access allowed.
2466 * 0b01..Non-secure and Privilege access allowed.
2467 * 0b10..Secure and Non-priviledge user access allowed.
2468 * 0b11..Secure and Priviledge user access allowed.
2469 */
2470#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK)
2471#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U)
2472#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U)
2473/*! FS_USB_DEV_RULE - USB Full-speed device
2474 * 0b00..Non-secure and Non-priviledge user access allowed.
2475 * 0b01..Non-secure and Privilege access allowed.
2476 * 0b10..Secure and Non-priviledge user access allowed.
2477 * 0b11..Secure and Priviledge user access allowed.
2478 */
2479#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK)
2480#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK (0x300000U)
2481#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT (20U)
2482/*! SCT_RULE - SCTimer
2483 * 0b00..Non-secure and Non-priviledge user access allowed.
2484 * 0b01..Non-secure and Privilege access allowed.
2485 * 0b10..Secure and Non-priviledge user access allowed.
2486 * 0b11..Secure and Priviledge user access allowed.
2487 */
2488#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK)
2489#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U)
2490#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U)
2491/*! FLEXCOMM0_RULE - Flexcomm interface 0
2492 * 0b00..Non-secure and Non-priviledge user access allowed.
2493 * 0b01..Non-secure and Privilege access allowed.
2494 * 0b10..Secure and Non-priviledge user access allowed.
2495 * 0b11..Secure and Priviledge user access allowed.
2496 */
2497#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK)
2498#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U)
2499#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U)
2500/*! FLEXCOMM1_RULE - Flexcomm interface 1
2501 * 0b00..Non-secure and Non-priviledge user access allowed.
2502 * 0b01..Non-secure and Privilege access allowed.
2503 * 0b10..Secure and Non-priviledge user access allowed.
2504 * 0b11..Secure and Priviledge user access allowed.
2505 */
2506#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK)
2507/*! @} */
2508
2509/*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */
2510/*! @{ */
2511#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U)
2512#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U)
2513/*! FLEXCOMM2_RULE - Flexcomm interface 2
2514 * 0b00..Non-secure and Non-priviledge user access allowed.
2515 * 0b01..Non-secure and Privilege access allowed.
2516 * 0b10..Secure and Non-priviledge user access allowed.
2517 * 0b11..Secure and Priviledge user access allowed.
2518 */
2519#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK)
2520#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U)
2521#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U)
2522/*! FLEXCOMM3_RULE - Flexcomm interface 3
2523 * 0b00..Non-secure and Non-priviledge user access allowed.
2524 * 0b01..Non-secure and Privilege access allowed.
2525 * 0b10..Secure and Non-priviledge user access allowed.
2526 * 0b11..Secure and Priviledge user access allowed.
2527 */
2528#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK)
2529#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U)
2530#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U)
2531/*! FLEXCOMM4_RULE - Flexcomm interface 4
2532 * 0b00..Non-secure and Non-priviledge user access allowed.
2533 * 0b01..Non-secure and Privilege access allowed.
2534 * 0b10..Secure and Non-priviledge user access allowed.
2535 * 0b11..Secure and Priviledge user access allowed.
2536 */
2537#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK)
2538#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK (0x3000U)
2539#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT (12U)
2540/*! MAILBOX_RULE - Inter CPU communication Mailbox
2541 * 0b00..Non-secure and Non-priviledge user access allowed.
2542 * 0b01..Non-secure and Privilege access allowed.
2543 * 0b10..Secure and Non-priviledge user access allowed.
2544 * 0b11..Secure and Priviledge user access allowed.
2545 */
2546#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK)
2547#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U)
2548#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U)
2549/*! GPIO0_RULE - High Speed GPIO
2550 * 0b00..Non-secure and Non-priviledge user access allowed.
2551 * 0b01..Non-secure and Privilege access allowed.
2552 * 0b10..Secure and Non-priviledge user access allowed.
2553 * 0b11..Secure and Priviledge user access allowed.
2554 */
2555#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK)
2556/*! @} */
2557
2558/*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */
2559/*! @{ */
2560#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U)
2561#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U)
2562/*! USB_HS_DEV_RULE - USB high Speed device registers
2563 * 0b00..Non-secure and Non-priviledge user access allowed.
2564 * 0b01..Non-secure and Privilege access allowed.
2565 * 0b10..Secure and Non-priviledge user access allowed.
2566 * 0b11..Secure and Priviledge user access allowed.
2567 */
2568#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK)
2569#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK (0x300000U)
2570#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT (20U)
2571/*! CRC_RULE - CRC engine
2572 * 0b00..Non-secure and Non-priviledge user access allowed.
2573 * 0b01..Non-secure and Privilege access allowed.
2574 * 0b10..Secure and Non-priviledge user access allowed.
2575 * 0b11..Secure and Priviledge user access allowed.
2576 */
2577#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK)
2578#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U)
2579#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U)
2580/*! FLEXCOMM5_RULE - Flexcomm interface 5
2581 * 0b00..Non-secure and Non-priviledge user access allowed.
2582 * 0b01..Non-secure and Privilege access allowed.
2583 * 0b10..Secure and Non-priviledge user access allowed.
2584 * 0b11..Secure and Priviledge user access allowed.
2585 */
2586#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK)
2587#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U)
2588#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U)
2589/*! FLEXCOMM6_RULE - Flexcomm interface 6
2590 * 0b00..Non-secure and Non-priviledge user access allowed.
2591 * 0b01..Non-secure and Privilege access allowed.
2592 * 0b10..Secure and Non-priviledge user access allowed.
2593 * 0b11..Secure and Priviledge user access allowed.
2594 */
2595#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK)
2596/*! @} */
2597
2598/*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */
2599/*! @{ */
2600#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U)
2601#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U)
2602/*! FLEXCOMM7_RULE - Flexcomm interface 7
2603 * 0b00..Non-secure and Non-priviledge user access allowed.
2604 * 0b01..Non-secure and Privilege access allowed.
2605 * 0b10..Secure and Non-priviledge user access allowed.
2606 * 0b11..Secure and Priviledge user access allowed.
2607 */
2608#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK)
2609#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK (0x3000U)
2610#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT (12U)
2611/*! SDIO_RULE - SDMMC card interface
2612 * 0b00..Non-secure and Non-priviledge user access allowed.
2613 * 0b01..Non-secure and Privilege access allowed.
2614 * 0b10..Secure and Non-priviledge user access allowed.
2615 * 0b11..Secure and Priviledge user access allowed.
2616 */
2617#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK)
2618#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U)
2619#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U)
2620/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP)
2621 * 0b00..Non-secure and Non-priviledge user access allowed.
2622 * 0b01..Non-secure and Privilege access allowed.
2623 * 0b10..Secure and Non-priviledge user access allowed.
2624 * 0b11..Secure and Priviledge user access allowed.
2625 */
2626#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK)
2627#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U)
2628#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U)
2629/*! HS_LSPI_RULE - High Speed SPI
2630 * 0b00..Non-secure and Non-priviledge user access allowed.
2631 * 0b01..Non-secure and Privilege access allowed.
2632 * 0b10..Secure and Non-priviledge user access allowed.
2633 * 0b11..Secure and Priviledge user access allowed.
2634 */
2635#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK)
2636/*! @} */
2637
2638/*! @name SEC_CTRL_AHB_PORT10_SLAVE0_RULE - Security access rules for AHB peripherals. */
2639/*! @{ */
2640#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK (0x3U)
2641#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT (0U)
2642/*! ADC_RULE - ADC
2643 * 0b00..Non-secure and Non-priviledge user access allowed.
2644 * 0b01..Non-secure and Privilege access allowed.
2645 * 0b10..Secure and Non-priviledge user access allowed.
2646 * 0b11..Secure and Priviledge user access allowed.
2647 */
2648#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK)
2649#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U)
2650#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U)
2651/*! USB_FS_HOST_RULE - USB Full Speed Host registers.
2652 * 0b00..Non-secure and Non-priviledge user access allowed.
2653 * 0b01..Non-secure and Privilege access allowed.
2654 * 0b10..Secure and Non-priviledge user access allowed.
2655 * 0b11..Secure and Priviledge user access allowed.
2656 */
2657#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK)
2658#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U)
2659#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U)
2660/*! USB_HS_HOST_RULE - USB High speed host registers
2661 * 0b00..Non-secure and Non-priviledge user access allowed.
2662 * 0b01..Non-secure and Privilege access allowed.
2663 * 0b10..Secure and Non-priviledge user access allowed.
2664 * 0b11..Secure and Priviledge user access allowed.
2665 */
2666#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK)
2667#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK (0x30000U)
2668#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT (16U)
2669/*! HASH_RULE - SHA-2 crypto registers
2670 * 0b00..Non-secure and Non-priviledge user access allowed.
2671 * 0b01..Non-secure and Privilege access allowed.
2672 * 0b10..Secure and Non-priviledge user access allowed.
2673 * 0b11..Secure and Priviledge user access allowed.
2674 */
2675#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK)
2676#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U)
2677#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT (20U)
2678/*! CASPER_RULE - RSA/ECC crypto accelerator
2679 * 0b00..Non-secure and Non-priviledge user access allowed.
2680 * 0b01..Non-secure and Privilege access allowed.
2681 * 0b10..Secure and Non-priviledge user access allowed.
2682 * 0b11..Secure and Priviledge user access allowed.
2683 */
2684#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK)
2685#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK (0x3000000U)
2686#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT (24U)
2687/*! PQ_RULE - Power Quad (CPU0 processor hardware accelerator)
2688 * 0b00..Non-secure and Non-priviledge user access allowed.
2689 * 0b01..Non-secure and Privilege access allowed.
2690 * 0b10..Secure and Non-priviledge user access allowed.
2691 * 0b11..Secure and Priviledge user access allowed.
2692 */
2693#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK)
2694#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U)
2695#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT (28U)
2696/*! DMA1_RULE - DMA Controller (Secure)
2697 * 0b00..Non-secure and Non-priviledge user access allowed.
2698 * 0b01..Non-secure and Privilege access allowed.
2699 * 0b10..Secure and Non-priviledge user access allowed.
2700 * 0b11..Secure and Priviledge user access allowed.
2701 */
2702#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK)
2703/*! @} */
2704
2705/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE */
2706#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_COUNT (1U)
2707
2708/*! @name SEC_CTRL_AHB_PORT10_SLAVE1_RULE - Security access rules for AHB peripherals. */
2709/*! @{ */
2710#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U)
2711#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U)
2712/*! GPIO1_RULE - Secure High Speed GPIO
2713 * 0b00..Non-secure and Non-priviledge user access allowed.
2714 * 0b01..Non-secure and Privilege access allowed.
2715 * 0b10..Secure and Non-priviledge user access allowed.
2716 * 0b11..Secure and Priviledge user access allowed.
2717 */
2718#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK)
2719#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U)
2720#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U)
2721/*! AHB_SEC_CTRL_RULE - AHB Secure Controller
2722 * 0b00..Non-secure and Non-priviledge user access allowed.
2723 * 0b01..Non-secure and Privilege access allowed.
2724 * 0b10..Secure and Non-priviledge user access allowed.
2725 * 0b11..Secure and Priviledge user access allowed.
2726 */
2727#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK)
2728/*! @} */
2729
2730/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE */
2731#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_COUNT (1U)
2732
2733/*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */
2734/*! @{ */
2735#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U)
2736#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U)
2737/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF
2738 * 0b00..Non-secure and Non-priviledge user access allowed.
2739 * 0b01..Non-secure and Privilege access allowed.
2740 * 0b10..Secure and Non-priviledge user access allowed.
2741 * 0b11..Secure and Priviledge user access allowed.
2742 */
2743#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK)
2744#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U)
2745#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U)
2746/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF
2747 * 0b00..Non-secure and Non-priviledge user access allowed.
2748 * 0b01..Non-secure and Privilege access allowed.
2749 * 0b10..Secure and Non-priviledge user access allowed.
2750 * 0b11..Secure and Priviledge user access allowed.
2751 */
2752#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK)
2753#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U)
2754#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U)
2755/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF
2756 * 0b00..Non-secure and Non-priviledge user access allowed.
2757 * 0b01..Non-secure and Privilege access allowed.
2758 * 0b10..Secure and Non-priviledge user access allowed.
2759 * 0b11..Secure and Priviledge user access allowed.
2760 */
2761#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK)
2762#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U)
2763#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U)
2764/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF
2765 * 0b00..Non-secure and Non-priviledge user access allowed.
2766 * 0b01..Non-secure and Privilege access allowed.
2767 * 0b10..Secure and Non-priviledge user access allowed.
2768 * 0b11..Secure and Priviledge user access allowed.
2769 */
2770#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK)
2771/*! @} */
2772
2773/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */
2774#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U)
2775
2776/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */
2777#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U)
2778
2779/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */
2780/*! @{ */
2781#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U)
2782#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U)
2783/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF
2784 * 0b00..Non-secure and Non-priviledge user access allowed.
2785 * 0b01..Non-secure and Privilege access allowed.
2786 * 0b10..Secure and Non-priviledge user access allowed.
2787 * 0b11..Secure and Priviledge user access allowed.
2788 */
2789#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK)
2790/*! @} */
2791
2792/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */
2793#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U)
2794
2795/*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */
2796/*! @{ */
2797#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U)
2798#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U)
2799/*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF
2800 * 0b00..Non-secure and Non-priviledge user access allowed.
2801 * 0b01..Non-secure and Privilege access allowed.
2802 * 0b10..Secure and Non-priviledge user access allowed.
2803 * 0b11..Secure and Priviledge user access allowed.
2804 */
2805#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK)
2806#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U)
2807#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U)
2808/*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF
2809 * 0b00..Non-secure and Non-priviledge user access allowed.
2810 * 0b01..Non-secure and Privilege access allowed.
2811 * 0b10..Secure and Non-priviledge user access allowed.
2812 * 0b11..Secure and Priviledge user access allowed.
2813 */
2814#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK)
2815#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U)
2816#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U)
2817/*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF
2818 * 0b00..Non-secure and Non-priviledge user access allowed.
2819 * 0b01..Non-secure and Privilege access allowed.
2820 * 0b10..Secure and Non-priviledge user access allowed.
2821 * 0b11..Secure and Priviledge user access allowed.
2822 */
2823#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK)
2824#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U)
2825#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U)
2826/*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF
2827 * 0b00..Non-secure and Non-priviledge user access allowed.
2828 * 0b01..Non-secure and Privilege access allowed.
2829 * 0b10..Secure and Non-priviledge user access allowed.
2830 * 0b11..Secure and Priviledge user access allowed.
2831 */
2832#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK)
2833/*! @} */
2834
2835/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */
2836#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U)
2837
2838/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */
2839#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U)
2840
2841/*! @name SEC_VIO_ADDR - most recent security violation address for AHB port n */
2842/*! @{ */
2843#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU)
2844#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U)
2845/*! SEC_VIO_ADDR - security violation address for AHB port
2846 */
2847#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK)
2848/*! @} */
2849
2850/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */
2851#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (12U)
2852
2853/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB port n */
2854/*! @{ */
2855#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U)
2856#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U)
2857/*! SEC_VIO_INFO_WRITE - security violation access read/write indicator.
2858 * 0b0..Read access.
2859 * 0b1..Write access.
2860 */
2861#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK)
2862#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U)
2863#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U)
2864/*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator.
2865 * 0b0..Code access.
2866 * 0b1..Data access.
2867 */
2868#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK)
2869#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U)
2870#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U)
2871/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level
2872 */
2873#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK)
2874#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U)
2875#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U)
2876/*! SEC_VIO_INFO_MASTER - security violation master number
2877 * 0b0000..CPU0 Code.
2878 * 0b0001..CPU0 System.
2879 * 0b0010..CPU1 Data.
2880 * 0b0011..CPU1 System.
2881 * 0b0100..USB-HS Device.
2882 * 0b0101..SDMA0.
2883 * 0b1000..SDIO.
2884 * 0b1001..PowerQuad.
2885 * 0b1010..HASH.
2886 * 0b1011..USB-FS Host.
2887 * 0b1100..SDMA1.
2888 */
2889#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK)
2890/*! @} */
2891
2892/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */
2893#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (12U)
2894
2895/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */
2896/*! @{ */
2897#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U)
2898#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U)
2899/*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear.
2900 * 0b0..Not valid.
2901 * 0b1..Valid (violation occurred).
2902 */
2903#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK)
2904#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U)
2905#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U)
2906/*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear.
2907 * 0b0..Not valid.
2908 * 0b1..Valid (violation occurred).
2909 */
2910#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK)
2911#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U)
2912#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U)
2913/*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear.
2914 * 0b0..Not valid.
2915 * 0b1..Valid (violation occurred).
2916 */
2917#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK)
2918#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U)
2919#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U)
2920/*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear.
2921 * 0b0..Not valid.
2922 * 0b1..Valid (violation occurred).
2923 */
2924#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK)
2925#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U)
2926#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U)
2927/*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear.
2928 * 0b0..Not valid.
2929 * 0b1..Valid (violation occurred).
2930 */
2931#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK)
2932#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U)
2933#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U)
2934/*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear.
2935 * 0b0..Not valid.
2936 * 0b1..Valid (violation occurred).
2937 */
2938#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK)
2939#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U)
2940#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U)
2941/*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear.
2942 * 0b0..Not valid.
2943 * 0b1..Valid (violation occurred).
2944 */
2945#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK)
2946#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U)
2947#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U)
2948/*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear.
2949 * 0b0..Not valid.
2950 * 0b1..Valid (violation occurred).
2951 */
2952#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK)
2953#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U)
2954#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U)
2955/*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear.
2956 * 0b0..Not valid.
2957 * 0b1..Valid (violation occurred).
2958 */
2959#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK)
2960#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U)
2961#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U)
2962/*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear.
2963 * 0b0..Not valid.
2964 * 0b1..Valid (violation occurred).
2965 */
2966#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK)
2967#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U)
2968#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U)
2969/*! VIO_INFO_VALID10 - violation information valid flag for AHB port 10. Write 1 to clear.
2970 * 0b0..Not valid.
2971 * 0b1..Valid (violation occurred).
2972 */
2973#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK)
2974#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U)
2975#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U)
2976/*! VIO_INFO_VALID11 - violation information valid flag for AHB port 11. Write 1 to clear.
2977 * 0b0..Not valid.
2978 * 0b1..Valid (violation occurred).
2979 */
2980#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK)
2981/*! @} */
2982
2983/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */
2984/*! @{ */
2985#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U)
2986#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U)
2987/*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0
2988 * 0b1..Pin state is readable by non-secure world.
2989 * 0b0..Pin state is blocked to non-secure world.
2990 */
2991#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK)
2992#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U)
2993#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U)
2994/*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1
2995 * 0b1..Pin state is readable by non-secure world.
2996 * 0b0..Pin state is blocked to non-secure world.
2997 */
2998#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK)
2999#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U)
3000#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U)
3001/*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2
3002 * 0b1..Pin state is readable by non-secure world.
3003 * 0b0..Pin state is blocked to non-secure world.
3004 */
3005#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK)
3006#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U)
3007#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U)
3008/*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3
3009 * 0b1..Pin state is readable by non-secure world.
3010 * 0b0..Pin state is blocked to non-secure world.
3011 */
3012#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK)
3013#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U)
3014#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U)
3015/*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4
3016 * 0b1..Pin state is readable by non-secure world.
3017 * 0b0..Pin state is blocked to non-secure world.
3018 */
3019#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK)
3020#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U)
3021#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U)
3022/*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5
3023 * 0b1..Pin state is readable by non-secure world.
3024 * 0b0..Pin state is blocked to non-secure world.
3025 */
3026#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK)
3027#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U)
3028#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U)
3029/*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6
3030 * 0b1..Pin state is readable by non-secure world.
3031 * 0b0..Pin state is blocked to non-secure world.
3032 */
3033#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK)
3034#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U)
3035#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U)
3036/*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7
3037 * 0b1..Pin state is readable by non-secure world.
3038 * 0b0..Pin state is blocked to non-secure world.
3039 */
3040#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK)
3041#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U)
3042#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U)
3043/*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8
3044 * 0b1..Pin state is readable by non-secure world.
3045 * 0b0..Pin state is blocked to non-secure world.
3046 */
3047#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK)
3048#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U)
3049#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U)
3050/*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9
3051 * 0b1..Pin state is readable by non-secure world.
3052 * 0b0..Pin state is blocked to non-secure world.
3053 */
3054#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK)
3055#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U)
3056#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U)
3057/*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10
3058 * 0b1..Pin state is readable by non-secure world.
3059 * 0b0..Pin state is blocked to non-secure world.
3060 */
3061#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK)
3062#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U)
3063#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U)
3064/*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11
3065 * 0b1..Pin state is readable by non-secure world.
3066 * 0b0..Pin state is blocked to non-secure world.
3067 */
3068#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK)
3069#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U)
3070#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U)
3071/*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12
3072 * 0b1..Pin state is readable by non-secure world.
3073 * 0b0..Pin state is blocked to non-secure world.
3074 */
3075#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK)
3076#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U)
3077#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U)
3078/*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13
3079 * 0b1..Pin state is readable by non-secure world.
3080 * 0b0..Pin state is blocked to non-secure world.
3081 */
3082#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK)
3083#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U)
3084#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U)
3085/*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14
3086 * 0b1..Pin state is readable by non-secure world.
3087 * 0b0..Pin state is blocked to non-secure world.
3088 */
3089#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK)
3090#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U)
3091#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U)
3092/*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15
3093 * 0b1..Pin state is readable by non-secure world.
3094 * 0b0..Pin state is blocked to non-secure world.
3095 */
3096#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK)
3097#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U)
3098#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U)
3099/*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16
3100 * 0b1..Pin state is readable by non-secure world.
3101 * 0b0..Pin state is blocked to non-secure world.
3102 */
3103#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK)
3104#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U)
3105#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U)
3106/*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17
3107 * 0b1..Pin state is readable by non-secure world.
3108 * 0b0..Pin state is blocked to non-secure world.
3109 */
3110#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK)
3111#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U)
3112#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U)
3113/*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18
3114 * 0b1..Pin state is readable by non-secure world.
3115 * 0b0..Pin state is blocked to non-secure world.
3116 */
3117#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK)
3118#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U)
3119#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U)
3120/*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19
3121 * 0b1..Pin state is readable by non-secure world.
3122 * 0b0..Pin state is blocked to non-secure world.
3123 */
3124#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK)
3125#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U)
3126#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U)
3127/*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20
3128 * 0b1..Pin state is readable by non-secure world.
3129 * 0b0..Pin state is blocked to non-secure world.
3130 */
3131#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK)
3132#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U)
3133#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U)
3134/*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21
3135 * 0b1..Pin state is readable by non-secure world.
3136 * 0b0..Pin state is blocked to non-secure world.
3137 */
3138#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK)
3139#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U)
3140#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U)
3141/*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22
3142 * 0b1..Pin state is readable by non-secure world.
3143 * 0b0..Pin state is blocked to non-secure world.
3144 */
3145#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK)
3146#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U)
3147#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U)
3148/*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23
3149 * 0b1..Pin state is readable by non-secure world.
3150 * 0b0..Pin state is blocked to non-secure world.
3151 */
3152#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK)
3153#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U)
3154#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U)
3155/*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24
3156 * 0b1..Pin state is readable by non-secure world.
3157 * 0b0..Pin state is blocked to non-secure world.
3158 */
3159#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK)
3160#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U)
3161#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U)
3162/*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25
3163 * 0b1..Pin state is readable by non-secure world.
3164 * 0b0..Pin state is blocked to non-secure world.
3165 */
3166#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK)
3167#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U)
3168#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U)
3169/*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26
3170 * 0b1..Pin state is readable by non-secure world.
3171 * 0b0..Pin state is blocked to non-secure world.
3172 */
3173#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK)
3174#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U)
3175#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U)
3176/*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27
3177 * 0b1..Pin state is readable by non-secure world.
3178 * 0b0..Pin state is blocked to non-secure world.
3179 */
3180#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK)
3181#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U)
3182#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U)
3183/*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28
3184 * 0b1..Pin state is readable by non-secure world.
3185 * 0b0..Pin state is blocked to non-secure world.
3186 */
3187#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK)
3188#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U)
3189#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U)
3190/*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29
3191 * 0b1..Pin state is readable by non-secure world.
3192 * 0b0..Pin state is blocked to non-secure world.
3193 */
3194#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK)
3195#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U)
3196#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U)
3197/*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30
3198 * 0b1..Pin state is readable by non-secure world.
3199 * 0b0..Pin state is blocked to non-secure world.
3200 */
3201#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK)
3202#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U)
3203#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U)
3204/*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31
3205 * 0b1..Pin state is readable by non-secure world.
3206 * 0b0..Pin state is blocked to non-secure world.
3207 */
3208#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK)
3209/*! @} */
3210
3211/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */
3212/*! @{ */
3213#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U)
3214#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U)
3215/*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0
3216 * 0b1..Pin state is readable by non-secure world.
3217 * 0b0..Pin state is blocked to non-secure world.
3218 */
3219#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK)
3220#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U)
3221#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U)
3222/*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1
3223 * 0b1..Pin state is readable by non-secure world.
3224 * 0b0..Pin state is blocked to non-secure world.
3225 */
3226#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK)
3227#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U)
3228#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U)
3229/*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2
3230 * 0b1..Pin state is readable by non-secure world.
3231 * 0b0..Pin state is blocked to non-secure world.
3232 */
3233#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK)
3234#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U)
3235#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U)
3236/*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3
3237 * 0b1..Pin state is readable by non-secure world.
3238 * 0b0..Pin state is blocked to non-secure world.
3239 */
3240#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK)
3241#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U)
3242#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U)
3243/*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4
3244 * 0b1..Pin state is readable by non-secure world.
3245 * 0b0..Pin state is blocked to non-secure world.
3246 */
3247#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK)
3248#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U)
3249#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U)
3250/*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5
3251 * 0b1..Pin state is readable by non-secure world.
3252 * 0b0..Pin state is blocked to non-secure world.
3253 */
3254#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK)
3255#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U)
3256#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U)
3257/*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6
3258 * 0b1..Pin state is readable by non-secure world.
3259 * 0b0..Pin state is blocked to non-secure world.
3260 */
3261#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK)
3262#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U)
3263#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U)
3264/*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7
3265 * 0b1..Pin state is readable by non-secure world.
3266 * 0b0..Pin state is blocked to non-secure world.
3267 */
3268#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK)
3269#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U)
3270#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U)
3271/*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8
3272 * 0b1..Pin state is readable by non-secure world.
3273 * 0b0..Pin state is blocked to non-secure world.
3274 */
3275#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK)
3276#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U)
3277#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U)
3278/*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9
3279 * 0b1..Pin state is readable by non-secure world.
3280 * 0b0..Pin state is blocked to non-secure world.
3281 */
3282#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK)
3283#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U)
3284#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U)
3285/*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10
3286 * 0b1..Pin state is readable by non-secure world.
3287 * 0b0..Pin state is blocked to non-secure world.
3288 */
3289#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK)
3290#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U)
3291#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U)
3292/*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11
3293 * 0b1..Pin state is readable by non-secure world.
3294 * 0b0..Pin state is blocked to non-secure world.
3295 */
3296#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK)
3297#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U)
3298#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U)
3299/*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12
3300 * 0b1..Pin state is readable by non-secure world.
3301 * 0b0..Pin state is blocked to non-secure world.
3302 */
3303#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK)
3304#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U)
3305#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U)
3306/*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13
3307 * 0b1..Pin state is readable by non-secure world.
3308 * 0b0..Pin state is blocked to non-secure world.
3309 */
3310#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK)
3311#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U)
3312#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U)
3313/*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14
3314 * 0b1..Pin state is readable by non-secure world.
3315 * 0b0..Pin state is blocked to non-secure world.
3316 */
3317#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK)
3318#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U)
3319#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U)
3320/*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15
3321 * 0b1..Pin state is readable by non-secure world.
3322 * 0b0..Pin state is blocked to non-secure world.
3323 */
3324#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK)
3325#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U)
3326#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U)
3327/*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16
3328 * 0b1..Pin state is readable by non-secure world.
3329 * 0b0..Pin state is blocked to non-secure world.
3330 */
3331#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK)
3332#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U)
3333#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U)
3334/*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17
3335 * 0b1..Pin state is readable by non-secure world.
3336 * 0b0..Pin state is blocked to non-secure world.
3337 */
3338#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK)
3339#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U)
3340#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U)
3341/*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18
3342 * 0b1..Pin state is readable by non-secure world.
3343 * 0b0..Pin state is blocked to non-secure world.
3344 */
3345#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK)
3346#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U)
3347#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U)
3348/*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19
3349 * 0b1..Pin state is readable by non-secure world.
3350 * 0b0..Pin state is blocked to non-secure world.
3351 */
3352#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK)
3353#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U)
3354#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U)
3355/*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20
3356 * 0b1..Pin state is readable by non-secure world.
3357 * 0b0..Pin state is blocked to non-secure world.
3358 */
3359#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK)
3360#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U)
3361#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U)
3362/*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21
3363 * 0b1..Pin state is readable by non-secure world.
3364 * 0b0..Pin state is blocked to non-secure world.
3365 */
3366#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK)
3367#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U)
3368#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U)
3369/*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22
3370 * 0b1..Pin state is readable by non-secure world.
3371 * 0b0..Pin state is blocked to non-secure world.
3372 */
3373#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK)
3374#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U)
3375#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U)
3376/*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23
3377 * 0b1..Pin state is readable by non-secure world.
3378 * 0b0..Pin state is blocked to non-secure world.
3379 */
3380#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK)
3381#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U)
3382#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U)
3383/*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24
3384 * 0b1..Pin state is readable by non-secure world.
3385 * 0b0..Pin state is blocked to non-secure world.
3386 */
3387#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK)
3388#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U)
3389#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U)
3390/*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25
3391 * 0b1..Pin state is readable by non-secure world.
3392 * 0b0..Pin state is blocked to non-secure world.
3393 */
3394#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK)
3395#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U)
3396#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U)
3397/*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26
3398 * 0b1..Pin state is readable by non-secure world.
3399 * 0b0..Pin state is blocked to non-secure world.
3400 */
3401#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK)
3402#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U)
3403#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U)
3404/*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27
3405 * 0b1..Pin state is readable by non-secure world.
3406 * 0b0..Pin state is blocked to non-secure world.
3407 */
3408#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK)
3409#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U)
3410#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U)
3411/*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28
3412 * 0b1..Pin state is readable by non-secure world.
3413 * 0b0..Pin state is blocked to non-secure world.
3414 */
3415#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK)
3416#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U)
3417#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U)
3418/*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29
3419 * 0b1..Pin state is readable by non-secure world.
3420 * 0b0..Pin state is blocked to non-secure world.
3421 */
3422#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK)
3423#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U)
3424#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U)
3425/*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30
3426 * 0b1..Pin state is readable by non-secure world.
3427 * 0b0..Pin state is blocked to non-secure world.
3428 */
3429#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK)
3430#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U)
3431#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U)
3432/*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31
3433 * 0b1..Pin state is readable by non-secure world.
3434 * 0b0..Pin state is blocked to non-secure world.
3435 */
3436#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK)
3437/*! @} */
3438
3439/*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */
3440/*! @{ */
3441#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U)
3442#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U)
3443/*! SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts
3444 * 0b0..
3445 * 0b1..
3446 */
3447#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK)
3448#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U)
3449#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U)
3450/*! SDMA0_IRQ - System DMA 0 (non-secure) interrupt.
3451 * 0b0..
3452 * 0b1..
3453 */
3454#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK)
3455#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U)
3456#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U)
3457/*! GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt.
3458 * 0b0..
3459 * 0b1..
3460 */
3461#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK)
3462#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U)
3463#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U)
3464/*! GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt.
3465 * 0b0..
3466 * 0b1..
3467 */
3468#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK)
3469#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U)
3470#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U)
3471/*! GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt.
3472 * 0b0..
3473 * 0b1..
3474 */
3475#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK)
3476#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U)
3477#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U)
3478/*! GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt.
3479 * 0b0..
3480 * 0b1..
3481 */
3482#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK)
3483#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U)
3484#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U)
3485/*! GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt.
3486 * 0b0..
3487 * 0b1..
3488 */
3489#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK)
3490#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U)
3491#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U)
3492/*! GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt.
3493 * 0b0..
3494 * 0b1..
3495 */
3496#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK)
3497#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U)
3498#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U)
3499/*! UTICK_IRQ - Micro Tick Timer interrupt.
3500 * 0b0..
3501 * 0b1..
3502 */
3503#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK)
3504#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U)
3505#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U)
3506/*! MRT_IRQ - Multi-Rate Timer interrupt.
3507 * 0b0..
3508 * 0b1..
3509 */
3510#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK)
3511#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U)
3512#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U)
3513/*! CTIMER0_IRQ - Standard counter/timer 0 interrupt.
3514 * 0b0..
3515 * 0b1..
3516 */
3517#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK)
3518#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U)
3519#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U)
3520/*! CTIMER1_IRQ - Standard counter/timer 1 interrupt.
3521 * 0b0..
3522 * 0b1..
3523 */
3524#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK)
3525#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U)
3526#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U)
3527/*! SCT_IRQ - SCTimer/PWM interrupt.
3528 * 0b0..
3529 * 0b1..
3530 */
3531#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK)
3532#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U)
3533#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U)
3534/*! CTIMER3_IRQ - Standard counter/timer 3 interrupt.
3535 * 0b0..
3536 * 0b1..
3537 */
3538#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK)
3539#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U)
3540#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U)
3541/*! FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S).
3542 * 0b0..
3543 * 0b1..
3544 */
3545#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK)
3546#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U)
3547#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U)
3548/*! FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S).
3549 * 0b0..
3550 * 0b1..
3551 */
3552#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK)
3553#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U)
3554#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U)
3555/*! FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S).
3556 * 0b0..
3557 * 0b1..
3558 */
3559#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK)
3560#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U)
3561#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U)
3562/*! FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S).
3563 * 0b0..
3564 * 0b1..
3565 */
3566#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK)
3567#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U)
3568#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U)
3569/*! FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S).
3570 * 0b0..
3571 * 0b1..
3572 */
3573#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK)
3574#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U)
3575#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U)
3576/*! FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S).
3577 * 0b0..
3578 * 0b1..
3579 */
3580#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK)
3581#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U)
3582#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U)
3583/*! FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S).
3584 * 0b0..
3585 * 0b1..
3586 */
3587#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK)
3588#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U)
3589#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U)
3590/*! FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S).
3591 * 0b0..
3592 * 0b1..
3593 */
3594#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK)
3595#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U)
3596#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U)
3597/*! ADC_IRQ - General Purpose ADC interrupt.
3598 * 0b0..
3599 * 0b1..
3600 */
3601#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK)
3602#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U)
3603#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U)
3604/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written.
3605 * 0b0..
3606 * 0b1..
3607 */
3608#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK)
3609#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK (0x1000000U)
3610#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT (24U)
3611/*! ACMP_IRQ - Analog Comparator interrupt.
3612 * 0b0..
3613 * 0b1..
3614 */
3615#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK)
3616#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U)
3617#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U)
3618/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written.
3619 * 0b0..
3620 * 0b1..
3621 */
3622#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK)
3623#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U)
3624#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U)
3625/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written.
3626 * 0b0..
3627 * 0b1..
3628 */
3629#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK)
3630#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U)
3631#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U)
3632/*! USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt.
3633 * 0b0..
3634 * 0b1..
3635 */
3636#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK)
3637#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U)
3638#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U)
3639/*! USB0_IRQ - USB Full Speed Controller interrupt.
3640 * 0b0..
3641 * 0b1..
3642 */
3643#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK)
3644#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U)
3645#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U)
3646/*! RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ
3647 * 0b0..
3648 * 0b1..
3649 */
3650#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK)
3651#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK (0x40000000U)
3652#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT (30U)
3653/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written.
3654 * 0b0..
3655 * 0b1..
3656 */
3657#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK)
3658#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U)
3659#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U)
3660/*! MAILBOX_IRQ - Mailbox interrupt.
3661 * 0b0..
3662 * 0b1..
3663 */
3664#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK)
3665/*! @} */
3666
3667/*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */
3668/*! @{ */
3669#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U)
3670#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U)
3671/*! GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt.
3672 * 0b0..
3673 * 0b1..
3674 */
3675#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK)
3676#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U)
3677#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U)
3678/*! GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt.
3679 * 0b0..
3680 * 0b1..
3681 */
3682#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK)
3683#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U)
3684#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U)
3685/*! GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt.
3686 * 0b0..
3687 * 0b1..
3688 */
3689#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK)
3690#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U)
3691#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U)
3692/*! GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt.
3693 * 0b0..
3694 * 0b1..
3695 */
3696#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK)
3697#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U)
3698#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U)
3699/*! CTIMER2_IRQ - Standard counter/timer 2 interrupt.
3700 * 0b0..
3701 * 0b1..
3702 */
3703#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK)
3704#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U)
3705#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U)
3706/*! CTIMER4_IRQ - Standard counter/timer 4 interrupt.
3707 * 0b0..
3708 * 0b1..
3709 */
3710#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK)
3711#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U)
3712#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U)
3713/*! OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts
3714 * 0b0..
3715 * 0b1..
3716 */
3717#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK)
3718#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U)
3719#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U)
3720/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written.
3721 * 0b0..
3722 * 0b1..
3723 */
3724#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK)
3725#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U)
3726#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U)
3727/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written.
3728 * 0b0..
3729 * 0b1..
3730 */
3731#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK)
3732#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U)
3733#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U)
3734/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written.
3735 * 0b0..
3736 * 0b1..
3737 */
3738#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK)
3739#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U)
3740#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U)
3741/*! SDIO_IRQ - SDIO Controller interrupt.
3742 * 0b0..
3743 * 0b1..
3744 */
3745#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK)
3746#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U)
3747#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U)
3748/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written.
3749 * 0b0..
3750 * 0b1..
3751 */
3752#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK)
3753#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U)
3754#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U)
3755/*! RESERVED4 - Reserved. Read value is undefined, only zero should be written.
3756 * 0b0..
3757 * 0b1..
3758 */
3759#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK)
3760#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U)
3761#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U)
3762/*! RESERVED5 - Reserved. Read value is undefined, only zero should be written.
3763 * 0b0..
3764 * 0b1..
3765 */
3766#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK)
3767#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK (0x4000U)
3768#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT (14U)
3769/*! USB1_PHY_IRQ - USB High Speed PHY Controller interrupt.
3770 * 0b0..
3771 * 0b1..
3772 */
3773#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK)
3774#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U)
3775#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U)
3776/*! USB1_IRQ - USB High Speed Controller interrupt.
3777 * 0b0..
3778 * 0b1..
3779 */
3780#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK)
3781#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U)
3782#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U)
3783/*! USB1_NEEDCLK - USB High Speed Controller Clock request interrupt.
3784 * 0b0..
3785 * 0b1..
3786 */
3787#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK)
3788#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U)
3789#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U)
3790/*! SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt.
3791 * 0b0..
3792 * 0b1..
3793 */
3794#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK)
3795#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U)
3796#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U)
3797/*! SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt.
3798 * 0b0..
3799 * 0b1..
3800 */
3801#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK)
3802#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U)
3803#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U)
3804/*! SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt.
3805 * 0b0..
3806 * 0b1..
3807 */
3808#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK)
3809#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U)
3810#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U)
3811/*! PLU_IRQ - Programmable Look-Up Controller interrupt.
3812 * 0b0..
3813 * 0b1..
3814 */
3815#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK)
3816#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U)
3817#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U)
3818/*! SEC_VIO_IRQ - Security Violation interrupt.
3819 * 0b0..
3820 * 0b1..
3821 */
3822#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK)
3823#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U)
3824#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U)
3825/*! SHA_IRQ - HASH-AES interrupt.
3826 * 0b0..
3827 * 0b1..
3828 */
3829#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK)
3830#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U)
3831#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U)
3832/*! CASPER_IRQ - CASPER interrupt.
3833 * 0b0..
3834 * 0b1..
3835 */
3836#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK)
3837#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK (0x1000000U)
3838#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT (24U)
3839/*! PUFKEY_IRQ - PUF interrupt.
3840 * 0b0..
3841 * 0b1..
3842 */
3843#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK)
3844#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U)
3845#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U)
3846/*! PQ_IRQ - Power Quad interrupt.
3847 * 0b0..
3848 * 0b1..
3849 */
3850#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK)
3851#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U)
3852#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U)
3853/*! SDMA1_IRQ - System DMA 1 (Secure) interrupt
3854 * 0b0..
3855 * 0b1..
3856 */
3857#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK)
3858#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U)
3859#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U)
3860/*! LSPI_HS_IRQ - High Speed SPI interrupt
3861 * 0b0..
3862 * 0b1..
3863 */
3864#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK)
3865/*! @} */
3866
3867/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */
3868/*! @{ */
3869#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U)
3870#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U)
3871/*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock.
3872 * 0b10..Writable.
3873 * 0b01..Restricted mode.
3874 */
3875#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK)
3876#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU)
3877#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U)
3878/*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock.
3879 * 0b10..Writable.
3880 * 0b01..Restricted mode.
3881 */
3882#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK)
3883#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U)
3884#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U)
3885/*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock.
3886 * 0b10..Writable.
3887 * 0b01..Restricted mode.
3888 */
3889#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK)
3890#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U)
3891#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U)
3892/*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock.
3893 * 0b10..Writable.
3894 * 0b01..Restricted mode.
3895 */
3896#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK)
3897/*! @} */
3898
3899/*! @name MASTER_SEC_LEVEL - master secure level register */
3900/*! @{ */
3901#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK (0x30U)
3902#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT (4U)
3903/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus.
3904 * 0b00..Non-secure and Non-priviledge user access allowed.
3905 * 0b01..Non-secure and Privilege access allowed.
3906 * 0b10..Secure and Non-priviledge user access allowed.
3907 * 0b11..Secure and Priviledge user access allowed.
3908 */
3909#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK)
3910#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK (0xC0U)
3911#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT (6U)
3912/*! CPU1S - Micro-Cortex M33 (CPU1) System bus.
3913 * 0b00..Non-secure and Non-priviledge user access allowed.
3914 * 0b01..Non-secure and Privilege access allowed.
3915 * 0b10..Secure and Non-priviledge user access allowed.
3916 * 0b11..Secure and Priviledge user access allowed.
3917 */
3918#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK)
3919#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U)
3920#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U)
3921/*! USBFSD - USB Full Speed Device.
3922 * 0b00..Non-secure and Non-priviledge user access allowed.
3923 * 0b01..Non-secure and Privilege access allowed.
3924 * 0b10..Secure and Non-priviledge user access allowed.
3925 * 0b11..Secure and Priviledge user access allowed.
3926 */
3927#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK)
3928#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U)
3929#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U)
3930/*! SDMA0 - System DMA 0.
3931 * 0b00..Non-secure and Non-priviledge user access allowed.
3932 * 0b01..Non-secure and Privilege access allowed.
3933 * 0b10..Secure and Non-priviledge user access allowed.
3934 * 0b11..Secure and Priviledge user access allowed.
3935 */
3936#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK)
3937#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U)
3938#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U)
3939/*! SDIO - SDIO.
3940 * 0b00..Non-secure and Non-priviledge user access allowed.
3941 * 0b01..Non-secure and Privilege access allowed.
3942 * 0b10..Secure and Non-priviledge user access allowed.
3943 * 0b11..Secure and Priviledge user access allowed.
3944 */
3945#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK)
3946#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U)
3947#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U)
3948/*! PQ - Power Quad.
3949 * 0b00..Non-secure and Non-priviledge user access allowed.
3950 * 0b01..Non-secure and Privilege access allowed.
3951 * 0b10..Secure and Non-priviledge user access allowed.
3952 * 0b11..Secure and Priviledge user access allowed.
3953 */
3954#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK)
3955#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U)
3956#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U)
3957/*! HASH - Hash.
3958 * 0b00..Non-secure and Non-priviledge user access allowed.
3959 * 0b01..Non-secure and Privilege access allowed.
3960 * 0b10..Secure and Non-priviledge user access allowed.
3961 * 0b11..Secure and Priviledge user access allowed.
3962 */
3963#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK)
3964#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U)
3965#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U)
3966/*! USBFSH - USB Full speed Host.
3967 * 0b00..Non-secure and Non-priviledge user access allowed.
3968 * 0b01..Non-secure and Privilege access allowed.
3969 * 0b10..Secure and Non-priviledge user access allowed.
3970 * 0b11..Secure and Priviledge user access allowed.
3971 */
3972#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK)
3973#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U)
3974#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U)
3975/*! SDMA1 - System DMA 1 security level.
3976 * 0b00..Non-secure and Non-priviledge user access allowed.
3977 * 0b01..Non-secure and Privilege access allowed.
3978 * 0b10..Secure and Non-priviledge user access allowed.
3979 * 0b11..Secure and Priviledge user access allowed.
3980 */
3981#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK)
3982#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U)
3983#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U)
3984/*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock.
3985 * 0b10..Writable.
3986 * 0b01..Restricted mode.
3987 */
3988#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK)
3989/*! @} */
3990
3991/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */
3992/*! @{ */
3993#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK (0x30U)
3994#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT (4U)
3995/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C)
3996 * 0b11..Non-secure and Non-priviledge user access allowed.
3997 * 0b10..Non-secure and Privilege access allowed.
3998 * 0b01..Secure and Non-priviledge user access allowed.
3999 * 0b00..Secure and Priviledge user access allowed.
4000 */
4001#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK)
4002#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK (0xC0U)
4003#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT (6U)
4004/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S)
4005 * 0b11..Non-secure and Non-priviledge user access allowed.
4006 * 0b10..Non-secure and Privilege access allowed.
4007 * 0b01..Secure and Non-priviledge user access allowed.
4008 * 0b00..Secure and Priviledge user access allowed.
4009 */
4010#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK)
4011#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U)
4012#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U)
4013/*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD)
4014 * 0b11..Non-secure and Non-priviledge user access allowed.
4015 * 0b10..Non-secure and Privilege access allowed.
4016 * 0b01..Secure and Non-priviledge user access allowed.
4017 * 0b00..Secure and Priviledge user access allowed.
4018 */
4019#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK)
4020#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U)
4021#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U)
4022/*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0)
4023 * 0b11..Non-secure and Non-priviledge user access allowed.
4024 * 0b10..Non-secure and Privilege access allowed.
4025 * 0b01..Secure and Non-priviledge user access allowed.
4026 * 0b00..Secure and Priviledge user access allowed.
4027 */
4028#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK)
4029#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U)
4030#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U)
4031/*! SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO)
4032 * 0b11..Non-secure and Non-priviledge user access allowed.
4033 * 0b10..Non-secure and Privilege access allowed.
4034 * 0b01..Secure and Non-priviledge user access allowed.
4035 * 0b00..Secure and Priviledge user access allowed.
4036 */
4037#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK)
4038#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U)
4039#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U)
4040/*! PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ)
4041 * 0b11..Non-secure and Non-priviledge user access allowed.
4042 * 0b10..Non-secure and Privilege access allowed.
4043 * 0b01..Secure and Non-priviledge user access allowed.
4044 * 0b00..Secure and Priviledge user access allowed.
4045 */
4046#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK)
4047#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U)
4048#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U)
4049/*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH)
4050 * 0b11..Non-secure and Non-priviledge user access allowed.
4051 * 0b10..Non-secure and Privilege access allowed.
4052 * 0b01..Secure and Non-priviledge user access allowed.
4053 * 0b00..Secure and Priviledge user access allowed.
4054 */
4055#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK)
4056#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U)
4057#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U)
4058/*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH)
4059 * 0b11..Non-secure and Non-priviledge user access allowed.
4060 * 0b10..Non-secure and Privilege access allowed.
4061 * 0b01..Secure and Non-priviledge user access allowed.
4062 * 0b00..Secure and Priviledge user access allowed.
4063 */
4064#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK)
4065#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U)
4066#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U)
4067/*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1)
4068 * 0b11..Non-secure and Non-priviledge user access allowed.
4069 * 0b10..Non-secure and Privilege access allowed.
4070 * 0b01..Secure and Non-priviledge user access allowed.
4071 * 0b00..Secure and Priviledge user access allowed.
4072 */
4073#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK)
4074#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U)
4075#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U)
4076/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock.
4077 * 0b10..Writable.
4078 * 0b01..Restricted mode.
4079 */
4080#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK)
4081/*! @} */
4082
4083/*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */
4084/*! @{ */
4085#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U)
4086#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U)
4087/*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock.
4088 * 0b10..Writable.
4089 * 0b01..Restricted mode.
4090 */
4091#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK)
4092#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU)
4093#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U)
4094/*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock.
4095 * 0b10..Writable.
4096 * 0b01..Restricted mode.
4097 */
4098#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK)
4099#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U)
4100#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U)
4101/*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock.
4102 * 0b10..Writable.
4103 * 0b01..Restricted mode.
4104 */
4105#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK)
4106#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U)
4107#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U)
4108/*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock.
4109 * 0b10..Writable.
4110 * 0b01..Restricted mode.
4111 */
4112#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK)
4113#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U)
4114#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U)
4115/*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock.
4116 * 0b10..Writable.
4117 * 0b01..Restricted mode.
4118 */
4119#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK)
4120#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U)
4121#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U)
4122/*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock.
4123 * 0b10..Writable.
4124 * 0b01..Restricted mode.
4125 */
4126#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK)
4127/*! @} */
4128
4129/*! @name CPU1_LOCK_REG - Miscalleneous control signals for in micro-Cortex M33 (CPU1) */
4130/*! @{ */
4131#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U)
4132#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U)
4133/*! LOCK_NS_VTOR - micro-Cortex M33 (CPU1) VTOR_NS register write-lock.
4134 * 0b10..Writable.
4135 * 0b01..Restricted mode.
4136 */
4137#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK)
4138#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK (0xCU)
4139#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT (2U)
4140/*! LOCK_NS_MPU - micro-Cortex M33 (CPU1) non-secure MPU register write-lock.
4141 * 0b10..Writable.
4142 * 0b01..Restricted mode.
4143 */
4144#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK)
4145#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK (0xC0000000U)
4146#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT (30U)
4147/*! CPU1_LOCK_REG_LOCK - CPU1_LOCK_REG write-lock.
4148 * 0b10..Writable.
4149 * 0b01..Restricted mode.
4150 */
4151#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK)
4152/*! @} */
4153
4154/*! @name MISC_CTRL_DP_REG - secure control duplicate register */
4155/*! @{ */
4156#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U)
4157#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U)
4158/*! WRITE_LOCK - Write lock.
4159 * 0b10..Secure control registers can be written.
4160 * 0b01..Restricted mode.
4161 */
4162#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK)
4163#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
4164#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
4165/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix.
4166 * 0b10..Disable check.
4167 * 0b01..Restricted mode.
4168 */
4169#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK)
4170#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
4171#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
4172/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix.
4173 * 0b10..Disable check.
4174 * 0b01..Restricted mode.
4175 */
4176#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK)
4177#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
4178#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
4179/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix.
4180 * 0b10..Disable check.
4181 * 0b01..Restricted mode.
4182 */
4183#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK)
4184#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
4185#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
4186/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort.
4187 * 0b10..Enable abort fort secure checker.
4188 * 0b01..Disable abort fort secure checker.
4189 */
4190#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK)
4191#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U)
4192#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U)
4193/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode.
4194 * 0b10..Simple master in strict mode.
4195 * 0b01..Simple master in tier mode.
4196 */
4197#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK)
4198#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U)
4199#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U)
4200/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode.
4201 * 0b10..Smart master in strict mode.
4202 * 0b01..Smart master in tier mode.
4203 */
4204#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK)
4205#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U)
4206#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U)
4207/*! IDAU_ALL_NS - Disable IDAU.
4208 * 0b10..IDAU is enabled.
4209 * 0b01..IDAU is disable.
4210 */
4211#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK)
4212/*! @} */
4213
4214/*! @name MISC_CTRL_REG - secure control register */
4215/*! @{ */
4216#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U)
4217#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U)
4218/*! WRITE_LOCK - Write lock.
4219 * 0b10..Secure control registers can be written.
4220 * 0b01..Restricted mode.
4221 */
4222#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK)
4223#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
4224#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
4225/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix.
4226 * 0b10..Disable check.
4227 * 0b01..Restricted mode.
4228 */
4229#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK)
4230#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
4231#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
4232/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix.
4233 * 0b10..Disable check.
4234 * 0b01..Restricted mode.
4235 */
4236#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK)
4237#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
4238#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
4239/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix.
4240 * 0b10..Disable check.
4241 * 0b01..Restricted mode.
4242 */
4243#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK)
4244#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
4245#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
4246/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort.
4247 * 0b10..Enable abort fort secure checker.
4248 * 0b01..Disable abort fort secure checker.
4249 */
4250#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK)
4251#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U)
4252#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U)
4253/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode.
4254 * 0b10..Simple master in strict mode.
4255 * 0b01..Simple master in tier mode.
4256 */
4257#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK)
4258#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U)
4259#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U)
4260/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode.
4261 * 0b10..Smart master in strict mode.
4262 * 0b01..Smart master in tier mode.
4263 */
4264#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK)
4265#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U)
4266#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U)
4267/*! IDAU_ALL_NS - Disable IDAU.
4268 * 0b10..IDAU is enabled.
4269 * 0b01..IDAU is disable.
4270 */
4271#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK)
4272/*! @} */
4273
4274
4275/*!
4276 * @}
4277 */ /* end of group AHB_SECURE_CTRL_Register_Masks */
4278
4279
4280/* AHB_SECURE_CTRL - Peripheral instance base addresses */
4281#if (__ARM_FEATURE_CMSE & 0x2)
4282 /** Peripheral AHB_SECURE_CTRL base address */
4283 #define AHB_SECURE_CTRL_BASE (0x500AC000u)
4284 /** Peripheral AHB_SECURE_CTRL base address */
4285 #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u)
4286 /** Peripheral AHB_SECURE_CTRL base pointer */
4287 #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)
4288 /** Peripheral AHB_SECURE_CTRL base pointer */
4289 #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS)
4290 /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
4291 #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE }
4292 /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
4293 #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL }
4294 /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
4295 #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS }
4296 /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
4297 #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS }
4298#else
4299 /** Peripheral AHB_SECURE_CTRL base address */
4300 #define AHB_SECURE_CTRL_BASE (0x400AC000u)
4301 /** Peripheral AHB_SECURE_CTRL base pointer */
4302 #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)
4303 /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
4304 #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE }
4305 /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
4306 #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL }
4307#endif
4308
4309/*!
4310 * @}
4311 */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */
4312
4313
4314/* ----------------------------------------------------------------------------
4315 -- ANACTRL Peripheral Access Layer
4316 ---------------------------------------------------------------------------- */
4317
4318/*!
4319 * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer
4320 * @{
4321 */
4322
4323/** ANACTRL - Register Layout Typedef */
4324typedef struct {
4325 uint8_t RESERVED_0[4];
4326 __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */
4327 uint8_t RESERVED_1[4];
4328 __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */
4329 __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */
4330 __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */
4331 uint8_t RESERVED_2[8];
4332 __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */
4333 __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */
4334 uint8_t RESERVED_3[8];
4335 __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */
4336 __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */
4337 uint8_t RESERVED_4[8];
4338 __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */
4339 __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */
4340 __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */
4341 uint8_t RESERVED_5[180];
4342 __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */
4343} ANACTRL_Type;
4344
4345/* ----------------------------------------------------------------------------
4346 -- ANACTRL Register Masks
4347 ---------------------------------------------------------------------------- */
4348
4349/*!
4350 * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks
4351 * @{
4352 */
4353
4354/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */
4355/*! @{ */
4356#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U)
4357#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U)
4358/*! FLASH_PWRDWN - Flash Power Down status.
4359 * 0b0..Flash is not in power down mode.
4360 * 0b1..Flash is in power down mode.
4361 */
4362#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK)
4363#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U)
4364#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U)
4365/*! FLASH_INIT_ERROR - Flash initialization error status.
4366 * 0b0..No error.
4367 * 0b1..At least one error occured during flash initialization..
4368 */
4369#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK)
4370/*! @} */
4371
4372/*! @name FREQ_ME_CTRL - Frequency Measure function control register */
4373/*! @{ */
4374#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU)
4375#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U)
4376/*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale
4377 */
4378#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK)
4379#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U)
4380#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U)
4381/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit
4382 * when the measurement cycle has completed and there is valid capture data in the CAPVAL field
4383 * (bits 30:0).
4384 */
4385#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK)
4386/*! @} */
4387
4388/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */
4389/*! @{ */
4390#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U)
4391#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U)
4392/*! ENA_12MHZCLK - 12 MHz clock control.
4393 * 0b0..12 MHz clock is disabled.
4394 * 0b1..12 MHz clock is enabled.
4395 */
4396#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK)
4397#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U)
4398#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U)
4399/*! ENA_48MHZCLK - 48 MHz clock control.
4400 * 0b0..Reserved.
4401 * 0b1..48 MHz clock is enabled.
4402 */
4403#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK)
4404#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U)
4405#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U)
4406/*! DAC_TRIM - Frequency trim.
4407 */
4408#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK)
4409#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U)
4410#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U)
4411/*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode,
4412 * the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF
4413 * packets.
4414 */
4415#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK)
4416#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U)
4417#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U)
4418/*! USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0.
4419 */
4420#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK)
4421#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U)
4422#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U)
4423/*! ENA_96MHZCLK - 96 MHz clock control.
4424 * 0b0..96 MHz clock is disabled.
4425 * 0b1..96 MHz clock is enabled.
4426 */
4427#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK)
4428/*! @} */
4429
4430/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */
4431/*! @{ */
4432#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U)
4433#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U)
4434/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled.
4435 * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available).
4436 * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by
4437 * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK).
4438 */
4439#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK)
4440#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U)
4441#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U)
4442/*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses
4443 * the threshold voltage of a SLVT transistor, this output signal will go high. It is also
4444 * possible to observe the clk_valid signal.
4445 */
4446#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK)
4447/*! @} */
4448
4449/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */
4450/*! @{ */
4451#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U)
4452#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U)
4453/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level.
4454 * 0b0..XO AC buffer bypass is disabled.
4455 * 0b1..XO AC buffer bypass is enabled.
4456 */
4457#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK)
4458#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U)
4459#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U)
4460/*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL.
4461 * 0b0..High speed Crystal oscillator output to USB HS PLL is disabled.
4462 * 0b1..High speed Crystal oscillator output to USB HS PLL is enabled.
4463 */
4464#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK)
4465#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U)
4466#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U)
4467/*! ENABLE_SYSTEM_CLK_OUT - Enable XO 32 MHz output to CPU system.
4468 * 0b0..High speed Crystal oscillator output to CPU system is disabled.
4469 * 0b1..High speed Crystal oscillator output to CPU system is enabled.
4470 */
4471#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK)
4472/*! @} */
4473
4474/*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */
4475/*! @{ */
4476#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U)
4477#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U)
4478/*! XO_READY - Indicates XO out frequency statibilty.
4479 * 0b0..XO output frequency is not yet stable.
4480 * 0b1..XO output frequency is stable.
4481 */
4482#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK)
4483/*! @} */
4484
4485/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */
4486/*! @{ */
4487#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U)
4488#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U)
4489/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control.
4490 * 0b0..BOD VBAT interrupt is disabled.
4491 * 0b1..BOD VBAT interrupt is enabled.
4492 */
4493#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK)
4494#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U)
4495#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U)
4496/*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit.
4497 */
4498#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK)
4499#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U)
4500#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U)
4501/*! BODCORE_INT_ENABLE - BOD CORE interrupt control.
4502 * 0b0..BOD CORE interrupt is disabled.
4503 * 0b1..BOD CORE interrupt is enabled.
4504 */
4505#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK)
4506#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U)
4507#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U)
4508/*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit.
4509 */
4510#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK)
4511#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U)
4512#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U)
4513/*! DCDC_INT_ENABLE - DCDC interrupt control.
4514 * 0b0..DCDC interrupt is disabled.
4515 * 0b1..DCDC interrupt is enabled.
4516 */
4517#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK)
4518#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U)
4519#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U)
4520/*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit.
4521 */
4522#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK)
4523/*! @} */
4524
4525/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */
4526/*! @{ */
4527#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U)
4528#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U)
4529/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable.
4530 * 0b0..No interrupt pending..
4531 * 0b1..Interrupt pending..
4532 */
4533#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK)
4534#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U)
4535#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U)
4536/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable.
4537 * 0b0..No interrupt pending..
4538 * 0b1..Interrupt pending..
4539 */
4540#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK)
4541#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U)
4542#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U)
4543/*! BODVBAT_VAL - Current value of BOD VBAT power status output.
4544 * 0b0..VBAT voltage level is below the threshold.
4545 * 0b1..VBAT voltage level is above the threshold.
4546 */
4547#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK)
4548#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U)
4549#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U)
4550/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable.
4551 * 0b0..No interrupt pending..
4552 * 0b1..Interrupt pending..
4553 */
4554#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK)
4555#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U)
4556#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U)
4557/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable.
4558 * 0b0..No interrupt pending..
4559 * 0b1..Interrupt pending..
4560 */
4561#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK)
4562#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U)
4563#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U)
4564/*! BODCORE_VAL - Current value of BOD CORE power status output.
4565 * 0b0..CORE voltage level is below the threshold.
4566 * 0b1..CORE voltage level is above the threshold.
4567 */
4568#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK)
4569#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U)
4570#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U)
4571/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable.
4572 * 0b0..No interrupt pending..
4573 * 0b1..Interrupt pending..
4574 */
4575#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK)
4576#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U)
4577#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U)
4578/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable.
4579 * 0b0..No interrupt pending..
4580 * 0b1..Interrupt pending..
4581 */
4582#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK)
4583#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U)
4584#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U)
4585/*! DCDC_VAL - Current value of DCDC power status output.
4586 * 0b0..DCDC output Voltage is below the targeted regulation level.
4587 * 0b1..DCDC output Voltage is above the targeted regulation level.
4588 */
4589#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK)
4590/*! @} */
4591
4592/*! @name RINGO0_CTRL - First Ring Oscillator module control register. */
4593/*! @{ */
4594#define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U)
4595#define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U)
4596/*! SL - Select short or long ringo (for all ringos types).
4597 * 0b0..Select short ringo (few elements).
4598 * 0b1..Select long ringo (many elements).
4599 */
4600#define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK)
4601#define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U)
4602#define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U)
4603/*! FS - Ringo frequency output divider.
4604 * 0b0..High frequency output (frequency lower than 100 MHz).
4605 * 0b1..Low frequency output (frequency lower than 10 MHz).
4606 */
4607#define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK)
4608#define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU)
4609#define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U)
4610/*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control.
4611 * 0b00..Normal mode.
4612 * 0b01..P-Monitor mode. Measure with weak P transistor.
4613 * 0b10..P-Monitor mode. Measure with weak N transistor.
4614 * 0b11..Don't use.
4615 */
4616#define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK)
4617#define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U)
4618#define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U)
4619/*! PD - Ringo module Power control.
4620 * 0b0..The Ringo module is enabled.
4621 * 0b1..The Ringo module is disabled.
4622 */
4623#define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK)
4624#define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U)
4625#define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U)
4626/*! E_ND0 - First NAND2-based ringo control.
4627 * 0b0..First NAND2-based ringo is disabled.
4628 * 0b1..First NAND2-based ringo is enabled.
4629 */
4630#define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK)
4631#define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U)
4632#define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U)
4633/*! E_ND1 - Second NAND2-based ringo control.
4634 * 0b0..Second NAND2-based ringo is disabled.
4635 * 0b1..Second NAND2-based ringo is enabled.
4636 */
4637#define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK)
4638#define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U)
4639#define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U)
4640/*! E_NR0 - First NOR2-based ringo control.
4641 * 0b0..First NOR2-based ringo is disabled.
4642 * 0b1..First NOR2-based ringo is enabled.
4643 */
4644#define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK)
4645#define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U)
4646#define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U)
4647/*! E_NR1 - Second NOR2-based ringo control.
4648 * 0b0..Second NORD2-based ringo is disabled.
4649 * 0b1..Second NORD2-based ringo is enabled.
4650 */
4651#define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK)
4652#define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U)
4653#define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U)
4654/*! E_IV0 - First Inverter-based ringo control.
4655 * 0b0..First INV-based ringo is disabled.
4656 * 0b1..First INV-based ringo is enabled.
4657 */
4658#define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK)
4659#define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U)
4660#define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U)
4661/*! E_IV1 - Second Inverter-based ringo control.
4662 * 0b0..Second INV-based ringo is disabled.
4663 * 0b1..Second INV-based ringo is enabled.
4664 */
4665#define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK)
4666#define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U)
4667#define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U)
4668/*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control.
4669 * 0b0..First PN-based ringo is disabled.
4670 * 0b1..First PN-based ringo is enabled.
4671 */
4672#define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK)
4673#define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U)
4674#define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U)
4675/*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control.
4676 * 0b0..Second PN-based ringo is disabled.
4677 * 0b1..Second PN-based ringo is enabled.
4678 */
4679#define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK)
4680#define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U)
4681#define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U)
4682/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16)
4683 */
4684#define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK)
4685#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U)
4686#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U)
4687/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider
4688 * value, cleared when the change is complete.
4689 */
4690#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK)
4691/*! @} */
4692
4693/*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */
4694/*! @{ */
4695#define ANACTRL_RINGO1_CTRL_S_MASK (0x1U)
4696#define ANACTRL_RINGO1_CTRL_S_SHIFT (0U)
4697/*! S - Select short or long ringo (for all ringos types).
4698 * 0b0..Select short ringo (few elements).
4699 * 0b1..Select long ringo (many elements).
4700 */
4701#define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK)
4702#define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U)
4703#define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U)
4704/*! FS - Ringo frequency output divider.
4705 * 0b0..High frequency output (frequency lower than 100 MHz).
4706 * 0b1..Low frequency output (frequency lower than 10 MHz).
4707 */
4708#define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK)
4709#define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U)
4710#define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U)
4711/*! PD - Ringo module Power control.
4712 * 0b0..The Ringo module is enabled.
4713 * 0b1..The Ringo module is disabled.
4714 */
4715#define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK)
4716#define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U)
4717#define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U)
4718/*! E_R24 - .
4719 * 0b0..Ringo is disabled.
4720 * 0b1..Ringo is enabled.
4721 */
4722#define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK)
4723#define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U)
4724#define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U)
4725/*! E_R35 - .
4726 * 0b0..Ringo is disabled.
4727 * 0b1..Ringo is enabled.
4728 */
4729#define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK)
4730#define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U)
4731#define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U)
4732/*! E_M2 - Metal 2 (M2) monitor control.
4733 * 0b0..Ringo is disabled.
4734 * 0b1..Ringo is enabled.
4735 */
4736#define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK)
4737#define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U)
4738#define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U)
4739/*! E_M3 - Metal 3 (M3) monitor control.
4740 * 0b0..Ringo is disabled.
4741 * 0b1..Ringo is enabled.
4742 */
4743#define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK)
4744#define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U)
4745#define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U)
4746/*! E_M4 - Metal 4 (M4) monitor control.
4747 * 0b0..Ringo is disabled.
4748 * 0b1..Ringo is enabled.
4749 */
4750#define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK)
4751#define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U)
4752#define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U)
4753/*! E_M5 - Metal 5 (M5) monitor control.
4754 * 0b0..Ringo is disabled.
4755 * 0b1..Ringo is enabled.
4756 */
4757#define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK)
4758#define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U)
4759#define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U)
4760/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16)
4761 */
4762#define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK)
4763#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U)
4764#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U)
4765/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider
4766 * value, cleared when the change is complete.
4767 */
4768#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK)
4769/*! @} */
4770
4771/*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */
4772/*! @{ */
4773#define ANACTRL_RINGO2_CTRL_S_MASK (0x1U)
4774#define ANACTRL_RINGO2_CTRL_S_SHIFT (0U)
4775/*! S - Select short or long ringo (for all ringos types).
4776 * 0b0..Select short ringo (few elements).
4777 * 0b1..Select long ringo (many elements).
4778 */
4779#define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK)
4780#define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U)
4781#define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U)
4782/*! FS - Ringo frequency output divider.
4783 * 0b0..High frequency output (frequency lower than 100 MHz).
4784 * 0b1..Low frequency output (frequency lower than 10 MHz).
4785 */
4786#define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK)
4787#define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U)
4788#define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U)
4789/*! PD - Ringo module Power control.
4790 * 0b0..The Ringo module is enabled.
4791 * 0b1..The Ringo module is disabled.
4792 */
4793#define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK)
4794#define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U)
4795#define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U)
4796/*! E_R24 - .
4797 * 0b0..Ringo is disabled.
4798 * 0b1..Ringo is enabled.
4799 */
4800#define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK)
4801#define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U)
4802#define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U)
4803/*! E_R35 - .
4804 * 0b0..Ringo is disabled.
4805 * 0b1..Ringo is enabled.
4806 */
4807#define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK)
4808#define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U)
4809#define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U)
4810/*! E_M2 - Metal 2 (M2) monitor control.
4811 * 0b0..Ringo is disabled.
4812 * 0b1..Ringo is enabled.
4813 */
4814#define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK)
4815#define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U)
4816#define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U)
4817/*! E_M3 - Metal 3 (M3) monitor control.
4818 * 0b0..Ringo is disabled.
4819 * 0b1..Ringo is enabled.
4820 */
4821#define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK)
4822#define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U)
4823#define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U)
4824/*! E_M4 - Metal 4 (M4) monitor control.
4825 * 0b0..Ringo is disabled.
4826 * 0b1..Ringo is enabled.
4827 */
4828#define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK)
4829#define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U)
4830#define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U)
4831/*! E_M5 - Metal 5 (M5) monitor control.
4832 * 0b0..Ringo is disabled.
4833 * 0b1..Ringo is enabled.
4834 */
4835#define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK)
4836#define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U)
4837#define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U)
4838/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16)
4839 */
4840#define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK)
4841#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U)
4842#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U)
4843/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider
4844 * value, cleared when the change is complete.
4845 */
4846#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK)
4847/*! @} */
4848
4849/*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */
4850/*! @{ */
4851#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U)
4852#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U)
4853/*! usb_vbusvalid_ext - Override value for Vbus if using external detectors.
4854 */
4855#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK)
4856#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U)
4857#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U)
4858/*! usb_id_ext - Override value for ID if using external detectors.
4859 */
4860#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK)
4861/*! @} */
4862
4863
4864/*!
4865 * @}
4866 */ /* end of group ANACTRL_Register_Masks */
4867
4868
4869/* ANACTRL - Peripheral instance base addresses */
4870#if (__ARM_FEATURE_CMSE & 0x2)
4871 /** Peripheral ANACTRL base address */
4872 #define ANACTRL_BASE (0x50013000u)
4873 /** Peripheral ANACTRL base address */
4874 #define ANACTRL_BASE_NS (0x40013000u)
4875 /** Peripheral ANACTRL base pointer */
4876 #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE)
4877 /** Peripheral ANACTRL base pointer */
4878 #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS)
4879 /** Array initializer of ANACTRL peripheral base addresses */
4880 #define ANACTRL_BASE_ADDRS { ANACTRL_BASE }
4881 /** Array initializer of ANACTRL peripheral base pointers */
4882 #define ANACTRL_BASE_PTRS { ANACTRL }
4883 /** Array initializer of ANACTRL peripheral base addresses */
4884 #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS }
4885 /** Array initializer of ANACTRL peripheral base pointers */
4886 #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS }
4887#else
4888 /** Peripheral ANACTRL base address */
4889 #define ANACTRL_BASE (0x40013000u)
4890 /** Peripheral ANACTRL base pointer */
4891 #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE)
4892 /** Array initializer of ANACTRL peripheral base addresses */
4893 #define ANACTRL_BASE_ADDRS { ANACTRL_BASE }
4894 /** Array initializer of ANACTRL peripheral base pointers */
4895 #define ANACTRL_BASE_PTRS { ANACTRL }
4896#endif
4897
4898/*!
4899 * @}
4900 */ /* end of group ANACTRL_Peripheral_Access_Layer */
4901
4902
4903/* ----------------------------------------------------------------------------
4904 -- CASPER Peripheral Access Layer
4905 ---------------------------------------------------------------------------- */
4906
4907/*!
4908 * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer
4909 * @{
4910 */
4911
4912/** CASPER - Register Layout Typedef */
4913typedef struct {
4914 __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */
4915 __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */
4916 __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */
4917 __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */
4918 __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */
4919 __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */
4920 __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */
4921 uint8_t RESERVED_0[4];
4922 __IO uint32_t AREG; /**< A register, offset: 0x20 */
4923 __IO uint32_t BREG; /**< B register, offset: 0x24 */
4924 __IO uint32_t CREG; /**< C register, offset: 0x28 */
4925 __IO uint32_t DREG; /**< D register, offset: 0x2C */
4926 __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */
4927 __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */
4928 __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */
4929 __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */
4930 uint8_t RESERVED_1[32];
4931 __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */
4932 __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */
4933 uint8_t RESERVED_2[24];
4934 __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */
4935} CASPER_Type;
4936
4937/* ----------------------------------------------------------------------------
4938 -- CASPER Register Masks
4939 ---------------------------------------------------------------------------- */
4940
4941/*!
4942 * @addtogroup CASPER_Register_Masks CASPER Register Masks
4943 * @{
4944 */
4945
4946/*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */
4947/*! @{ */
4948#define CASPER_CTRL0_ABBPAIR_MASK (0x1U)
4949#define CASPER_CTRL0_ABBPAIR_SHIFT (0U)
4950/*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up
4951 * 0b0..Bank-pair 0 (1st)
4952 * 0b1..Bank-pair 1 (2nd)
4953 */
4954#define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK)
4955#define CASPER_CTRL0_ABOFF_MASK (0x4U)
4956#define CASPER_CTRL0_ABOFF_SHIFT (2U)
4957/*! ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code
4958 * sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed
4959 * if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up
4960 */
4961#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK)
4962#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U)
4963#define CASPER_CTRL0_CDBPAIR_SHIFT (16U)
4964/*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up
4965 * 0b0..Bank-pair 0 (1st)
4966 * 0b1..Bank-pair 1 (2nd)
4967 */
4968#define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK)
4969#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U)
4970#define CASPER_CTRL0_CDOFF_SHIFT (18U)
4971/*! CDOFF - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees
4972 * (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32
4973 * bit operation. Ideally not in the same RAM as the AB values
4974 */
4975#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK)
4976/*! @} */
4977
4978/*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */
4979/*! @{ */
4980#define CASPER_CTRL1_ITER_MASK (0xFFU)
4981#define CASPER_CTRL1_ITER_SHIFT (0U)
4982/*! ITER - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate.
4983 */
4984#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK)
4985#define CASPER_CTRL1_MODE_MASK (0xFF00U)
4986#define CASPER_CTRL1_MODE_SHIFT (8U)
4987/*! MODE - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active.
4988 */
4989#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
4990#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U)
4991#define CASPER_CTRL1_RESBPAIR_SHIFT (16U)
4992/*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally
4993 * this is not the same bank as ABBPAIR (when 4-up supported)
4994 * 0b0..Bank-pair 0 (1st)
4995 * 0b1..Bank-pair 1 (2nd)
4996 */
4997#define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK)
4998#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U)
4999#define CASPER_CTRL1_RESOFF_SHIFT (18U)
5000/*! RESOFF - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally
5001 * not in the same RAM as the AB and CD values
5002 */
5003#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK)
5004#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U)
5005#define CASPER_CTRL1_CSKIP_SHIFT (30U)
5006/*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0:
5007 * 0b00..No Skip
5008 * 0b01..Skip if Carry is 1
5009 * 0b10..Skip if Carry is 0
5010 * 0b11..Set CTRLOFF to CDOFF and Skip
5011 */
5012#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK)
5013/*! @} */
5014
5015/*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */
5016/*! @{ */
5017#define CASPER_LOADER_COUNT_MASK (0xFFU)
5018#define CASPER_LOADER_COUNT_SHIFT (0U)
5019/*! COUNT - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one
5020 * op - does not iterate, write N means N control pairs to load
5021 */
5022#define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK)
5023#define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U)
5024#define CASPER_LOADER_CTRLBPAIR_SHIFT (16U)
5025/*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not
5026 * matter which bank is used as this is loaded when not performing an operation.
5027 * 0b0..Bank-pair 0 (1st)
5028 * 0b1..Bank-pair 1 (2nd)
5029 */
5030#define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK)
5031#define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U)
5032#define CASPER_LOADER_CTRLOFF_SHIFT (18U)
5033/*! CTRLOFF - DWord Offset of CTRL pair to load next.
5034 */
5035#define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK)
5036/*! @} */
5037
5038/*! @name STATUS - Indicates operational status and would contain the carry bit if used. */
5039/*! @{ */
5040#define CASPER_STATUS_DONE_MASK (0x1U)
5041#define CASPER_STATUS_DONE_SHIFT (0U)
5042/*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear.
5043 * 0b0..Busy or just cleared
5044 * 0b1..Completed last operation
5045 */
5046#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK)
5047#define CASPER_STATUS_CARRY_MASK (0x10U)
5048#define CASPER_STATUS_CARRY_SHIFT (4U)
5049/*! CARRY - Last carry value if operation produced a carry bit
5050 * 0b0..Carry was 0 or no carry
5051 * 0b1..Carry was 1
5052 */
5053#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK)
5054#define CASPER_STATUS_BUSY_MASK (0x20U)
5055#define CASPER_STATUS_BUSY_SHIFT (5U)
5056/*! BUSY - Indicates if the accelerator is busy performing an operation
5057 * 0b0..Not busy - is idle
5058 * 0b1..Is busy
5059 */
5060#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK)
5061/*! @} */
5062
5063/*! @name INTENSET - Sets interrupts */
5064/*! @{ */
5065#define CASPER_INTENSET_DONE_MASK (0x1U)
5066#define CASPER_INTENSET_DONE_SHIFT (0U)
5067/*! DONE - Set if the accelerator should interrupt when done.
5068 * 0b0..Do not interrupt when done
5069 * 0b1..Interrupt when done
5070 */
5071#define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK)
5072/*! @} */
5073
5074/*! @name INTENCLR - Clears interrupts */
5075/*! @{ */
5076#define CASPER_INTENCLR_DONE_MASK (0x1U)
5077#define CASPER_INTENCLR_DONE_SHIFT (0U)
5078/*! DONE - Written to clear an interrupt set with INTENSET.
5079 * 0b0..If written 0, ignored
5080 * 0b1..If written 1, do not Interrupt when done
5081 */
5082#define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK)
5083/*! @} */
5084
5085/*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */
5086/*! @{ */
5087#define CASPER_INTSTAT_DONE_MASK (0x1U)
5088#define CASPER_INTSTAT_DONE_SHIFT (0U)
5089/*! DONE - If set, interrupt is caused by accelerator being done.
5090 * 0b0..Not caused by accelerator being done
5091 * 0b1..Caused by accelerator being done
5092 */
5093#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK)
5094/*! @} */
5095
5096/*! @name AREG - A register */
5097/*! @{ */
5098#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU)
5099#define CASPER_AREG_REG_VALUE_SHIFT (0U)
5100/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application,
5101 * but is available when accelerator not busy.
5102 */
5103#define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK)
5104/*! @} */
5105
5106/*! @name BREG - B register */
5107/*! @{ */
5108#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU)
5109#define CASPER_BREG_REG_VALUE_SHIFT (0U)
5110/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application,
5111 * but is available when accelerator not busy.
5112 */
5113#define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK)
5114/*! @} */
5115
5116/*! @name CREG - C register */
5117/*! @{ */
5118#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU)
5119#define CASPER_CREG_REG_VALUE_SHIFT (0U)
5120/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application,
5121 * but is available when accelerator not busy.
5122 */
5123#define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK)
5124/*! @} */
5125
5126/*! @name DREG - D register */
5127/*! @{ */
5128#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU)
5129#define CASPER_DREG_REG_VALUE_SHIFT (0U)
5130/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application,
5131 * but is available when accelerator not busy.
5132 */
5133#define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK)
5134/*! @} */
5135
5136/*! @name RES0 - Result register 0 */
5137/*! @{ */
5138#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU)
5139#define CASPER_RES0_REG_VALUE_SHIFT (0U)
5140/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally
5141 * written or read by application, but is available when accelerator not busy.
5142 */
5143#define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK)
5144/*! @} */
5145
5146/*! @name RES1 - Result register 1 */
5147/*! @{ */
5148#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU)
5149#define CASPER_RES1_REG_VALUE_SHIFT (0U)
5150/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally
5151 * written or read by application, but is available when accelerator not busy.
5152 */
5153#define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK)
5154/*! @} */
5155
5156/*! @name RES2 - Result register 2 */
5157/*! @{ */
5158#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU)
5159#define CASPER_RES2_REG_VALUE_SHIFT (0U)
5160/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally
5161 * written or read by application, but is available when accelerator not busy.
5162 */
5163#define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK)
5164/*! @} */
5165
5166/*! @name RES3 - Result register 3 */
5167/*! @{ */
5168#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU)
5169#define CASPER_RES3_REG_VALUE_SHIFT (0U)
5170/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally
5171 * written or read by application, but is available when accelerator not busy.
5172 */
5173#define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK)
5174/*! @} */
5175
5176/*! @name MASK - Optional mask register */
5177/*! @{ */
5178#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU)
5179#define CASPER_MASK_MASK_SHIFT (0U)
5180/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values
5181 */
5182#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK)
5183/*! @} */
5184
5185/*! @name REMASK - Optional re-mask register */
5186/*! @{ */
5187#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU)
5188#define CASPER_REMASK_MASK_SHIFT (0U)
5189/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values
5190 */
5191#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK)
5192/*! @} */
5193
5194/*! @name LOCK - Security lock register */
5195/*! @{ */
5196#define CASPER_LOCK_LOCK_MASK (0x1U)
5197#define CASPER_LOCK_LOCK_SHIFT (0U)
5198/*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock.
5199 * 0b0..unlock
5200 * 0b1..Lock to current security level
5201 */
5202#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK)
5203#define CASPER_LOCK_KEY_MASK (0x1FFF0U)
5204#define CASPER_LOCK_KEY_SHIFT (4U)
5205/*! KEY - Must be written as 0x73D to change the register.
5206 * 0b0011100111101..If set during write, will allow lock or unlock
5207 */
5208#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK)
5209/*! @} */
5210
5211
5212/*!
5213 * @}
5214 */ /* end of group CASPER_Register_Masks */
5215
5216
5217/* CASPER - Peripheral instance base addresses */
5218#if (__ARM_FEATURE_CMSE & 0x2)
5219 /** Peripheral CASPER base address */
5220 #define CASPER_BASE (0x500A5000u)
5221 /** Peripheral CASPER base address */
5222 #define CASPER_BASE_NS (0x400A5000u)
5223 /** Peripheral CASPER base pointer */
5224 #define CASPER ((CASPER_Type *)CASPER_BASE)
5225 /** Peripheral CASPER base pointer */
5226 #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS)
5227 /** Array initializer of CASPER peripheral base addresses */
5228 #define CASPER_BASE_ADDRS { CASPER_BASE }
5229 /** Array initializer of CASPER peripheral base pointers */
5230 #define CASPER_BASE_PTRS { CASPER }
5231 /** Array initializer of CASPER peripheral base addresses */
5232 #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS }
5233 /** Array initializer of CASPER peripheral base pointers */
5234 #define CASPER_BASE_PTRS_NS { CASPER_NS }
5235#else
5236 /** Peripheral CASPER base address */
5237 #define CASPER_BASE (0x400A5000u)
5238 /** Peripheral CASPER base pointer */
5239 #define CASPER ((CASPER_Type *)CASPER_BASE)
5240 /** Array initializer of CASPER peripheral base addresses */
5241 #define CASPER_BASE_ADDRS { CASPER_BASE }
5242 /** Array initializer of CASPER peripheral base pointers */
5243 #define CASPER_BASE_PTRS { CASPER }
5244#endif
5245/** Interrupt vectors for the CASPER peripheral type */
5246#define CASPER_IRQS { CASER_IRQn }
5247
5248/*!
5249 * @}
5250 */ /* end of group CASPER_Peripheral_Access_Layer */
5251
5252
5253/* ----------------------------------------------------------------------------
5254 -- CRC Peripheral Access Layer
5255 ---------------------------------------------------------------------------- */
5256
5257/*!
5258 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
5259 * @{
5260 */
5261
5262/** CRC - Register Layout Typedef */
5263typedef struct {
5264 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
5265 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
5266 union { /* offset: 0x8 */
5267 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
5268 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
5269 };
5270} CRC_Type;
5271
5272/* ----------------------------------------------------------------------------
5273 -- CRC Register Masks
5274 ---------------------------------------------------------------------------- */
5275
5276/*!
5277 * @addtogroup CRC_Register_Masks CRC Register Masks
5278 * @{
5279 */
5280
5281/*! @name MODE - CRC mode register */
5282/*! @{ */
5283#define CRC_MODE_CRC_POLY_MASK (0x3U)
5284#define CRC_MODE_CRC_POLY_SHIFT (0U)
5285/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
5286 */
5287#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
5288#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
5289#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
5290/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
5291 */
5292#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
5293#define CRC_MODE_CMPL_WR_MASK (0x8U)
5294#define CRC_MODE_CMPL_WR_SHIFT (3U)
5295/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
5296 */
5297#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
5298#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
5299#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
5300/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
5301 */
5302#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
5303#define CRC_MODE_CMPL_SUM_MASK (0x20U)
5304#define CRC_MODE_CMPL_SUM_SHIFT (5U)
5305/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
5306 */
5307#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
5308/*! @} */
5309
5310/*! @name SEED - CRC seed register */
5311/*! @{ */
5312#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
5313#define CRC_SEED_CRC_SEED_SHIFT (0U)
5314/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
5315 * selected bit order and 1's complement pre-processes. A write access to this register will
5316 * overrule the CRC calculation in progresses.
5317 */
5318#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
5319/*! @} */
5320
5321/*! @name SUM - CRC checksum register */
5322/*! @{ */
5323#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
5324#define CRC_SUM_CRC_SUM_SHIFT (0U)
5325/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
5326 */
5327#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
5328/*! @} */
5329
5330/*! @name WR_DATA - CRC data register */
5331/*! @{ */
5332#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
5333#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
5334/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
5335 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
5336 * accept back-to-back transactions.
5337 */
5338#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
5339/*! @} */
5340
5341
5342/*!
5343 * @}
5344 */ /* end of group CRC_Register_Masks */
5345
5346
5347/* CRC - Peripheral instance base addresses */
5348#if (__ARM_FEATURE_CMSE & 0x2)
5349 /** Peripheral CRC_ENGINE base address */
5350 #define CRC_ENGINE_BASE (0x50095000u)
5351 /** Peripheral CRC_ENGINE base address */
5352 #define CRC_ENGINE_BASE_NS (0x40095000u)
5353 /** Peripheral CRC_ENGINE base pointer */
5354 #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
5355 /** Peripheral CRC_ENGINE base pointer */
5356 #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS)
5357 /** Array initializer of CRC peripheral base addresses */
5358 #define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
5359 /** Array initializer of CRC peripheral base pointers */
5360 #define CRC_BASE_PTRS { CRC_ENGINE }
5361 /** Array initializer of CRC peripheral base addresses */
5362 #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS }
5363 /** Array initializer of CRC peripheral base pointers */
5364 #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS }
5365#else
5366 /** Peripheral CRC_ENGINE base address */
5367 #define CRC_ENGINE_BASE (0x40095000u)
5368 /** Peripheral CRC_ENGINE base pointer */
5369 #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
5370 /** Array initializer of CRC peripheral base addresses */
5371 #define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
5372 /** Array initializer of CRC peripheral base pointers */
5373 #define CRC_BASE_PTRS { CRC_ENGINE }
5374#endif
5375
5376/*!
5377 * @}
5378 */ /* end of group CRC_Peripheral_Access_Layer */
5379
5380
5381/* ----------------------------------------------------------------------------
5382 -- CTIMER Peripheral Access Layer
5383 ---------------------------------------------------------------------------- */
5384
5385/*!
5386 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
5387 * @{
5388 */
5389
5390/** CTIMER - Register Layout Typedef */
5391typedef struct {
5392 __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
5393 __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
5394 __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */
5395 __IO uint32_t PR; /**< Prescale Register, offset: 0xC */
5396 __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */
5397 __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */
5398 __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
5399 __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
5400 __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
5401 __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
5402 uint8_t RESERVED_0[48];
5403 __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
5404 __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */
5405 __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
5406} CTIMER_Type;
5407
5408/* ----------------------------------------------------------------------------
5409 -- CTIMER Register Masks
5410 ---------------------------------------------------------------------------- */
5411
5412/*!
5413 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
5414 * @{
5415 */
5416
5417/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
5418/*! @{ */
5419#define CTIMER_IR_MR0INT_MASK (0x1U)
5420#define CTIMER_IR_MR0INT_SHIFT (0U)
5421/*! MR0INT - Interrupt flag for match channel 0.
5422 */
5423#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
5424#define CTIMER_IR_MR1INT_MASK (0x2U)
5425#define CTIMER_IR_MR1INT_SHIFT (1U)
5426/*! MR1INT - Interrupt flag for match channel 1.
5427 */
5428#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
5429#define CTIMER_IR_MR2INT_MASK (0x4U)
5430#define CTIMER_IR_MR2INT_SHIFT (2U)
5431/*! MR2INT - Interrupt flag for match channel 2.
5432 */
5433#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
5434#define CTIMER_IR_MR3INT_MASK (0x8U)
5435#define CTIMER_IR_MR3INT_SHIFT (3U)
5436/*! MR3INT - Interrupt flag for match channel 3.
5437 */
5438#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
5439#define CTIMER_IR_CR0INT_MASK (0x10U)
5440#define CTIMER_IR_CR0INT_SHIFT (4U)
5441/*! CR0INT - Interrupt flag for capture channel 0 event.
5442 */
5443#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
5444#define CTIMER_IR_CR1INT_MASK (0x20U)
5445#define CTIMER_IR_CR1INT_SHIFT (5U)
5446/*! CR1INT - Interrupt flag for capture channel 1 event.
5447 */
5448#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
5449#define CTIMER_IR_CR2INT_MASK (0x40U)
5450#define CTIMER_IR_CR2INT_SHIFT (6U)
5451/*! CR2INT - Interrupt flag for capture channel 2 event.
5452 */
5453#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
5454#define CTIMER_IR_CR3INT_MASK (0x80U)
5455#define CTIMER_IR_CR3INT_SHIFT (7U)
5456/*! CR3INT - Interrupt flag for capture channel 3 event.
5457 */
5458#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
5459/*! @} */
5460
5461/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
5462/*! @{ */
5463#define CTIMER_TCR_CEN_MASK (0x1U)
5464#define CTIMER_TCR_CEN_SHIFT (0U)
5465/*! CEN - Counter enable.
5466 * 0b0..Disabled.The counters are disabled.
5467 * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
5468 */
5469#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
5470#define CTIMER_TCR_CRST_MASK (0x2U)
5471#define CTIMER_TCR_CRST_SHIFT (1U)
5472/*! CRST - Counter reset.
5473 * 0b0..Disabled. Do nothing.
5474 * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
5475 * the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
5476 */
5477#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
5478/*! @} */
5479
5480/*! @name TC - Timer Counter */
5481/*! @{ */
5482#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
5483#define CTIMER_TC_TCVAL_SHIFT (0U)
5484/*! TCVAL - Timer counter value.
5485 */
5486#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
5487/*! @} */
5488
5489/*! @name PR - Prescale Register */
5490/*! @{ */
5491#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
5492#define CTIMER_PR_PRVAL_SHIFT (0U)
5493/*! PRVAL - Prescale counter value.
5494 */
5495#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
5496/*! @} */
5497
5498/*! @name PC - Prescale Counter */
5499/*! @{ */
5500#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
5501#define CTIMER_PC_PCVAL_SHIFT (0U)
5502/*! PCVAL - Prescale counter value.
5503 */
5504#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
5505/*! @} */
5506
5507/*! @name MCR - Match Control Register */
5508/*! @{ */
5509#define CTIMER_MCR_MR0I_MASK (0x1U)
5510#define CTIMER_MCR_MR0I_SHIFT (0U)
5511/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
5512 */
5513#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
5514#define CTIMER_MCR_MR0R_MASK (0x2U)
5515#define CTIMER_MCR_MR0R_SHIFT (1U)
5516/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it.
5517 */
5518#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
5519#define CTIMER_MCR_MR0S_MASK (0x4U)
5520#define CTIMER_MCR_MR0S_SHIFT (2U)
5521/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
5522 */
5523#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
5524#define CTIMER_MCR_MR1I_MASK (0x8U)
5525#define CTIMER_MCR_MR1I_SHIFT (3U)
5526/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
5527 */
5528#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
5529#define CTIMER_MCR_MR1R_MASK (0x10U)
5530#define CTIMER_MCR_MR1R_SHIFT (4U)
5531/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it.
5532 */
5533#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
5534#define CTIMER_MCR_MR1S_MASK (0x20U)
5535#define CTIMER_MCR_MR1S_SHIFT (5U)
5536/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
5537 */
5538#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
5539#define CTIMER_MCR_MR2I_MASK (0x40U)
5540#define CTIMER_MCR_MR2I_SHIFT (6U)
5541/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
5542 */
5543#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
5544#define CTIMER_MCR_MR2R_MASK (0x80U)
5545#define CTIMER_MCR_MR2R_SHIFT (7U)
5546/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it.
5547 */
5548#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
5549#define CTIMER_MCR_MR2S_MASK (0x100U)
5550#define CTIMER_MCR_MR2S_SHIFT (8U)
5551/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
5552 */
5553#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
5554#define CTIMER_MCR_MR3I_MASK (0x200U)
5555#define CTIMER_MCR_MR3I_SHIFT (9U)
5556/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
5557 */
5558#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
5559#define CTIMER_MCR_MR3R_MASK (0x400U)
5560#define CTIMER_MCR_MR3R_SHIFT (10U)
5561/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it.
5562 */
5563#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
5564#define CTIMER_MCR_MR3S_MASK (0x800U)
5565#define CTIMER_MCR_MR3S_SHIFT (11U)
5566/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
5567 */
5568#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
5569#define CTIMER_MCR_MR0RL_MASK (0x1000000U)
5570#define CTIMER_MCR_MR0RL_SHIFT (24U)
5571/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
5572 * (either via a match event or a write to bit 1 of the TCR).
5573 */
5574#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
5575#define CTIMER_MCR_MR1RL_MASK (0x2000000U)
5576#define CTIMER_MCR_MR1RL_SHIFT (25U)
5577/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
5578 * (either via a match event or a write to bit 1 of the TCR).
5579 */
5580#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
5581#define CTIMER_MCR_MR2RL_MASK (0x4000000U)
5582#define CTIMER_MCR_MR2RL_SHIFT (26U)
5583/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
5584 * (either via a match event or a write to bit 1 of the TCR).
5585 */
5586#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
5587#define CTIMER_MCR_MR3RL_MASK (0x8000000U)
5588#define CTIMER_MCR_MR3RL_SHIFT (27U)
5589/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
5590 * (either via a match event or a write to bit 1 of the TCR).
5591 */
5592#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
5593/*! @} */
5594
5595/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
5596/*! @{ */
5597#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
5598#define CTIMER_MR_MATCH_SHIFT (0U)
5599/*! MATCH - Timer counter match value.
5600 */
5601#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
5602/*! @} */
5603
5604/* The count of CTIMER_MR */
5605#define CTIMER_MR_COUNT (4U)
5606
5607/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
5608/*! @{ */
5609#define CTIMER_CCR_CAP0RE_MASK (0x1U)
5610#define CTIMER_CCR_CAP0RE_SHIFT (0U)
5611/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
5612 * the contents of TC. 0 = disabled. 1 = enabled.
5613 */
5614#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
5615#define CTIMER_CCR_CAP0FE_MASK (0x2U)
5616#define CTIMER_CCR_CAP0FE_SHIFT (1U)
5617/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
5618 * the contents of TC. 0 = disabled. 1 = enabled.
5619 */
5620#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
5621#define CTIMER_CCR_CAP0I_MASK (0x4U)
5622#define CTIMER_CCR_CAP0I_SHIFT (2U)
5623/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
5624 */
5625#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
5626#define CTIMER_CCR_CAP1RE_MASK (0x8U)
5627#define CTIMER_CCR_CAP1RE_SHIFT (3U)
5628/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
5629 * the contents of TC. 0 = disabled. 1 = enabled.
5630 */
5631#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
5632#define CTIMER_CCR_CAP1FE_MASK (0x10U)
5633#define CTIMER_CCR_CAP1FE_SHIFT (4U)
5634/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
5635 * the contents of TC. 0 = disabled. 1 = enabled.
5636 */
5637#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
5638#define CTIMER_CCR_CAP1I_MASK (0x20U)
5639#define CTIMER_CCR_CAP1I_SHIFT (5U)
5640/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
5641 */
5642#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
5643#define CTIMER_CCR_CAP2RE_MASK (0x40U)
5644#define CTIMER_CCR_CAP2RE_SHIFT (6U)
5645/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
5646 * the contents of TC. 0 = disabled. 1 = enabled.
5647 */
5648#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
5649#define CTIMER_CCR_CAP2FE_MASK (0x80U)
5650#define CTIMER_CCR_CAP2FE_SHIFT (7U)
5651/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
5652 * the contents of TC. 0 = disabled. 1 = enabled.
5653 */
5654#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
5655#define CTIMER_CCR_CAP2I_MASK (0x100U)
5656#define CTIMER_CCR_CAP2I_SHIFT (8U)
5657/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
5658 */
5659#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
5660#define CTIMER_CCR_CAP3RE_MASK (0x200U)
5661#define CTIMER_CCR_CAP3RE_SHIFT (9U)
5662/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with
5663 * the contents of TC. 0 = disabled. 1 = enabled.
5664 */
5665#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
5666#define CTIMER_CCR_CAP3FE_MASK (0x400U)
5667#define CTIMER_CCR_CAP3FE_SHIFT (10U)
5668/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with
5669 * the contents of TC. 0 = disabled. 1 = enabled.
5670 */
5671#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
5672#define CTIMER_CCR_CAP3I_MASK (0x800U)
5673#define CTIMER_CCR_CAP3I_SHIFT (11U)
5674/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
5675 */
5676#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
5677/*! @} */
5678
5679/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
5680/*! @{ */
5681#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
5682#define CTIMER_CR_CAP_SHIFT (0U)
5683/*! CAP - Timer counter capture value.
5684 */
5685#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
5686/*! @} */
5687
5688/* The count of CTIMER_CR */
5689#define CTIMER_CR_COUNT (4U)
5690
5691/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
5692/*! @{ */
5693#define CTIMER_EMR_EM0_MASK (0x1U)
5694#define CTIMER_EMR_EM0_SHIFT (0U)
5695/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
5696 * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
5697 * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
5698 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
5699 */
5700#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
5701#define CTIMER_EMR_EM1_MASK (0x2U)
5702#define CTIMER_EMR_EM1_SHIFT (1U)
5703/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
5704 * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
5705 * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
5706 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
5707 */
5708#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
5709#define CTIMER_EMR_EM2_MASK (0x4U)
5710#define CTIMER_EMR_EM2_SHIFT (2U)
5711/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
5712 * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
5713 * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
5714 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
5715 */
5716#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
5717#define CTIMER_EMR_EM3_MASK (0x8U)
5718#define CTIMER_EMR_EM3_SHIFT (3U)
5719/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
5720 * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
5721 * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
5722 * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
5723 */
5724#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
5725#define CTIMER_EMR_EMC0_MASK (0x30U)
5726#define CTIMER_EMR_EMC0_SHIFT (4U)
5727/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
5728 * 0b00..Do Nothing.
5729 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
5730 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
5731 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
5732 */
5733#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
5734#define CTIMER_EMR_EMC1_MASK (0xC0U)
5735#define CTIMER_EMR_EMC1_SHIFT (6U)
5736/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
5737 * 0b00..Do Nothing.
5738 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
5739 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
5740 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
5741 */
5742#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
5743#define CTIMER_EMR_EMC2_MASK (0x300U)
5744#define CTIMER_EMR_EMC2_SHIFT (8U)
5745/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
5746 * 0b00..Do Nothing.
5747 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
5748 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
5749 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
5750 */
5751#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
5752#define CTIMER_EMR_EMC3_MASK (0xC00U)
5753#define CTIMER_EMR_EMC3_SHIFT (10U)
5754/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
5755 * 0b00..Do Nothing.
5756 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
5757 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
5758 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
5759 */
5760#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
5761/*! @} */
5762
5763/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
5764/*! @{ */
5765#define CTIMER_CTCR_CTMODE_MASK (0x3U)
5766#define CTIMER_CTCR_CTMODE_SHIFT (0U)
5767/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
5768 * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
5769 * is incremented when the Prescale Counter matches the Prescale Register.
5770 * 0b00..Timer Mode. Incremented every rising APB bus clock edge.
5771 * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
5772 * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
5773 * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
5774 */
5775#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
5776#define CTIMER_CTCR_CINSEL_MASK (0xCU)
5777#define CTIMER_CTCR_CINSEL_SHIFT (2U)
5778/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
5779 * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
5780 * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
5781 * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
5782 * same timer.
5783 * 0b00..Channel 0. CAPn.0 for CTIMERn
5784 * 0b01..Channel 1. CAPn.1 for CTIMERn
5785 * 0b10..Channel 2. CAPn.2 for CTIMERn
5786 * 0b11..Channel 3. CAPn.3 for CTIMERn
5787 */
5788#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
5789#define CTIMER_CTCR_ENCC_MASK (0x10U)
5790#define CTIMER_CTCR_ENCC_SHIFT (4U)
5791/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
5792 * capture-edge event specified in bits 7:5 occurs.
5793 */
5794#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
5795#define CTIMER_CTCR_SELCC_MASK (0xE0U)
5796#define CTIMER_CTCR_SELCC_SHIFT (5U)
5797/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
5798 * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
5799 * 0x3 and 0x6 to 0x7 are reserved.
5800 * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
5801 * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
5802 * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
5803 * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
5804 * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
5805 * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
5806 */
5807#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
5808/*! @} */
5809
5810/*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */
5811/*! @{ */
5812#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
5813#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
5814/*! PWMEN0 - PWM mode enable for channel0.
5815 * 0b0..Match. CTIMERn_MAT0 is controlled by EM0.
5816 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
5817 */
5818#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
5819#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
5820#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
5821/*! PWMEN1 - PWM mode enable for channel1.
5822 * 0b0..Match. CTIMERn_MAT01 is controlled by EM1.