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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S28/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S28/drivers/fsl_clock.h
new file mode 100644
index 000000000..7d28cee7b
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S28/drivers/fsl_clock.h
@@ -0,0 +1,1240 @@
1/*
2 * Copyright 2017 - 2020, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_common.h"
12
13/*! @addtogroup clock */
14/*! @{ */
15
16/*! @file */
17
18/*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22/*! @name Driver version */
23/*@{*/
24/*! @brief CLOCK driver version 2.3.4. */
25#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 4))
26/*@}*/
27
28/*! @brief Configure whether driver controls clock
29 *
30 * When set to 0, peripheral drivers will enable clock in initialize function
31 * and disable clock in de-initialize function. When set to 1, peripheral
32 * driver will not control the clock, application could control the clock out of
33 * the driver.
34 *
35 * @note All drivers share this feature switcher. If it is set to 1, application
36 * should handle clock enable and disable for all drivers.
37 */
38#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
39#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
40#endif
41
42/*!
43 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
44 *
45 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
46 * would cache the recent calulation and accelerate the execution to get the
47 * right settings.
48 */
49#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
50#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
51#endif
52
53/* Definition for delay API in clock driver, users can redefine it to the real application. */
54#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
55#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (150000000UL)
56#endif
57
58/*! @brief Clock ip name array for ROM. */
59#define ROM_CLOCKS \
60 { \
61 kCLOCK_Rom \
62 }
63/*! @brief Clock ip name array for SRAM. */
64#define SRAM_CLOCKS \
65 { \
66 kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4 \
67 }
68/*! @brief Clock ip name array for FLASH. */
69#define FLASH_CLOCKS \
70 { \
71 kCLOCK_Flash \
72 }
73/*! @brief Clock ip name array for FMC. */
74#define FMC_CLOCKS \
75 { \
76 kCLOCK_Fmc \
77 }
78/*! @brief Clock ip name array for INPUTMUX. */
79#define INPUTMUX_CLOCKS \
80 { \
81 kCLOCK_InputMux0 \
82 }
83/*! @brief Clock ip name array for IOCON. */
84#define IOCON_CLOCKS \
85 { \
86 kCLOCK_Iocon \
87 }
88/*! @brief Clock ip name array for GPIO. */
89#define GPIO_CLOCKS \
90 { \
91 kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3 \
92 }
93/*! @brief Clock ip name array for PINT. */
94#define PINT_CLOCKS \
95 { \
96 kCLOCK_Pint \
97 }
98/*! @brief Clock ip name array for GINT. */
99#define GINT_CLOCKS \
100 { \
101 kCLOCK_Gint, kCLOCK_Gint \
102 }
103/*! @brief Clock ip name array for DMA. */
104#define DMA_CLOCKS \
105 { \
106 kCLOCK_Dma0, kCLOCK_Dma1 \
107 }
108/*! @brief Clock ip name array for CRC. */
109#define CRC_CLOCKS \
110 { \
111 kCLOCK_Crc \
112 }
113/*! @brief Clock ip name array for WWDT. */
114#define WWDT_CLOCKS \
115 { \
116 kCLOCK_Wwdt \
117 }
118/*! @brief Clock ip name array for RTC. */
119#define RTC_CLOCKS \
120 { \
121 kCLOCK_Rtc \
122 }
123/*! @brief Clock ip name array for Mailbox. */
124#define MAILBOX_CLOCKS \
125 { \
126 kCLOCK_Mailbox \
127 }
128/*! @brief Clock ip name array for LPADC. */
129#define LPADC_CLOCKS \
130 { \
131 kCLOCK_Adc0 \
132 }
133/*! @brief Clock ip name array for MRT. */
134#define MRT_CLOCKS \
135 { \
136 kCLOCK_Mrt \
137 }
138/*! @brief Clock ip name array for OSTIMER. */
139#define OSTIMER_CLOCKS \
140 { \
141 kCLOCK_OsTimer0 \
142 }
143/*! @brief Clock ip name array for SCT0. */
144#define SCT_CLOCKS \
145 { \
146 kCLOCK_Sct0 \
147 }
148/*! @brief Clock ip name array for UTICK. */
149#define UTICK_CLOCKS \
150 { \
151 kCLOCK_Utick0 \
152 }
153/*! @brief Clock ip name array for FLEXCOMM. */
154#define FLEXCOMM_CLOCKS \
155 { \
156 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
157 kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \
158 }
159/*! @brief Clock ip name array for LPUART. */
160#define LPUART_CLOCKS \
161 { \
162 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
163 kCLOCK_MinUart6, kCLOCK_MinUart7 \
164 }
165
166/*! @brief Clock ip name array for BI2C. */
167#define BI2C_CLOCKS \
168 { \
169 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \
170 }
171/*! @brief Clock ip name array for LSPI. */
172#define LPSPI_CLOCKS \
173 { \
174 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \
175 }
176/*! @brief Clock ip name array for FLEXI2S. */
177#define FLEXI2S_CLOCKS \
178 { \
179 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
180 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \
181 }
182/*! @brief Clock ip name array for CTIMER. */
183#define CTIMER_CLOCKS \
184 { \
185 kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
186 }
187/*! @brief Clock ip name array for COMP */
188#define COMP_CLOCKS \
189 { \
190 kCLOCK_Comp \
191 }
192/*! @brief Clock ip name array for SDIO. */
193#define SDIO_CLOCKS \
194 { \
195 kCLOCK_Sdio \
196 }
197/*! @brief Clock ip name array for USB1CLK. */
198#define USB1CLK_CLOCKS \
199 { \
200 kCLOCK_Usb1Clk \
201 }
202/*! @brief Clock ip name array for FREQME. */
203#define FREQME_CLOCKS \
204 { \
205 kCLOCK_Freqme \
206 }
207/*! @brief Clock ip name array for USBRAM. */
208#define USBRAM_CLOCKS \
209 { \
210 kCLOCK_UsbRam1 \
211 }
212/*! @brief Clock ip name array for RNG. */
213#define RNG_CLOCKS \
214 { \
215 kCLOCK_Rng \
216 }
217/*! @brief Clock ip name array for USBHMR0. */
218#define USBHMR0_CLOCKS \
219 { \
220 kCLOCK_Usbhmr0 \
221 }
222/*! @brief Clock ip name array for USBHSL0. */
223#define USBHSL0_CLOCKS \
224 { \
225 kCLOCK_Usbhsl0 \
226 }
227/*! @brief Clock ip name array for HashCrypt. */
228#define HASHCRYPT_CLOCKS \
229 { \
230 kCLOCK_HashCrypt \
231 }
232/*! @brief Clock ip name array for PowerQuad. */
233#define POWERQUAD_CLOCKS \
234 { \
235 kCLOCK_PowerQuad \
236 }
237/*! @brief Clock ip name array for PLULUT. */
238#define PLULUT_CLOCKS \
239 { \
240 kCLOCK_PluLut \
241 }
242/*! @brief Clock ip name array for PUF. */
243#define PUF_CLOCKS \
244 { \
245 kCLOCK_Puf \
246 }
247/*! @brief Clock ip name array for CASPER. */
248#define CASPER_CLOCKS \
249 { \
250 kCLOCK_Casper \
251 }
252/*! @brief Clock ip name array for ANALOGCTRL. */
253#define ANALOGCTRL_CLOCKS \
254 { \
255 kCLOCK_AnalogCtrl \
256 }
257/*! @brief Clock ip name array for HS_LSPI. */
258#define HS_LSPI_CLOCKS \
259 { \
260 kCLOCK_Hs_Lspi \
261 }
262/*! @brief Clock ip name array for GPIO_SEC. */
263#define GPIO_SEC_CLOCKS \
264 { \
265 kCLOCK_Gpio_Sec \
266 }
267/*! @brief Clock ip name array for GPIO_SEC_INT. */
268#define GPIO_SEC_INT_CLOCKS \
269 { \
270 kCLOCK_Gpio_Sec_Int \
271 }
272/*! @brief Clock ip name array for USBD. */
273#define USBD_CLOCKS \
274 { \
275 kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
276 }
277/*! @brief Clock ip name array for USBH. */
278#define USBH_CLOCKS \
279 { \
280 kCLOCK_Usbh1 \
281 }
282#define PLU_CLOCKS \
283 { \
284 kCLOCK_PluLut \
285 }
286#define SYSCTL_CLOCKS \
287 { \
288 kCLOCK_Sysctl \
289 }
290/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
291/*------------------------------------------------------------------------------
292 clock_ip_name_t definition:
293------------------------------------------------------------------------------*/
294
295#define CLK_GATE_REG_OFFSET_SHIFT 8U
296#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
297#define CLK_GATE_BIT_SHIFT_SHIFT 0U
298#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
299
300#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
301 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
302 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
303
304#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
305#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
306
307#define AHB_CLK_CTRL0 0
308#define AHB_CLK_CTRL1 1
309#define AHB_CLK_CTRL2 2
310
311/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
312typedef enum _clock_ip_name
313{
314 kCLOCK_IpInvalid = 0U,
315 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
316 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
317 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
318 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),
319 kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6),
320 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),
321 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),
322 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
323 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
324 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
325 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
326 kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),
327 kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),
328 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
329 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),
330 kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
331 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
332 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
333 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
334 kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26),
335 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
336 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
337 kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),
338 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
339 kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
340 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
341 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
342 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
343 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
344 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
345 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
346 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
347 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
348 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
349 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
350 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
351 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
352 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
353 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
354 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
355 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
356 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
357 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
358 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
359 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
360 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
361 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
362 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
363 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
364 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
365 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
366 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
367 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
368 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
369 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
370 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
371 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
372 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
373 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
374 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
375 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
376 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
377 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
378 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
379 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
380 kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
381 kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
382 kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
383 kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
384 kCLOCK_Pvt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28),
385 kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30),
386 kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
387 kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1),
388 kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),
389 kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3),
390 kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),
391 kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),
392 kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),
393 kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),
394 kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8),
395 kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),
396 kCLOCK_InputMux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
397 kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
398 kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),
399 kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),
400 kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),
401 kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19),
402 kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),
403 kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21),
404 kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22),
405 kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23),
406 kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24),
407 kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27),
408 kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28),
409 kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29),
410 kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30)
411} clock_ip_name_t;
412
413/*! @brief Peripherals clock source definition. */
414#define BUS_CLK kCLOCK_BusClk
415
416#define I2C0_CLK_SRC BUS_CLK
417
418/*! @brief Clock name used to get clock frequency. */
419typedef enum _clock_name
420{
421 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
422 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
423 kCLOCK_ClockOut, /*!< CLOCKOUT */
424 kCLOCK_FroHf, /*!< FRO48/96 */
425 kCLOCK_Pll1Out, /*!< PLL1 Output */
426 kCLOCK_Mclk, /*!< MCLK */
427 kCLOCK_Fro12M, /*!< FRO12M */
428 kCLOCK_ExtClk, /*!< External Clock */
429 kCLOCK_Pll0Out, /*!< PLL0 Output */
430 kCLOCK_FlexI2S, /*!< FlexI2S clock */
431
432} clock_name_t;
433
434/*! @brief Clock Mux Switches
435 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
436 * starting from LSB upwards
437 *
438 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
439 *
440 */
441
442#define CLK_ATTACH_ID(mux, sel, pos) \
443 ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U))
444#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
445#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
446
447#define GET_ID_ITEM(connection) ((connection)&0xFFFU)
448#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
449#define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU)
450#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF00U) >> 8U) - 1U))
451#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
452
453#define CM_SYSTICKCLKSEL0 0U
454#define CM_SYSTICKCLKSEL1 1U
455#define CM_TRACECLKSEL 2U
456#define CM_CTIMERCLKSEL0 3U
457#define CM_CTIMERCLKSEL1 4U
458#define CM_CTIMERCLKSEL2 5U
459#define CM_CTIMERCLKSEL3 6U
460#define CM_CTIMERCLKSEL4 7U
461#define CM_MAINCLKSELA 8U
462#define CM_MAINCLKSELB 9U
463#define CM_CLKOUTCLKSEL 10U
464#define CM_PLL0CLKSEL 12U
465#define CM_PLL1CLKSEL 13U
466#define CM_ADCASYNCCLKSEL 17U
467#define CM_USB0CLKSEL 18U
468#define CM_FXCOMCLKSEL0 20U
469#define CM_FXCOMCLKSEL1 21U
470#define CM_FXCOMCLKSEL2 22U
471#define CM_FXCOMCLKSEL3 23U
472#define CM_FXCOMCLKSEL4 24U
473#define CM_FXCOMCLKSEL5 25U
474#define CM_FXCOMCLKSEL6 26U
475#define CM_FXCOMCLKSEL7 27U
476#define CM_HSLSPICLKSEL 28U
477#define CM_MCLKCLKSEL 32U
478#define CM_SCTCLKSEL 36U
479#define CM_SDIOCLKSEL 38U
480
481#define CM_RTCOSC32KCLKSEL 63U
482
483typedef enum _clock_attach_id
484{
485
486 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),
487 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),
488 kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),
489 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),
490 kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0),
491 kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),
492 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),
493
494 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0),
495 kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1),
496 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2),
497 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3),
498 kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4),
499 kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5),
500 kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6),
501 kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7),
502
503 kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0),
504 kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1),
505 kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2),
506 kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3),
507 kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7),
508
509 kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
510 kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
511 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
512 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
513
514 kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0),
515 kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),
516 kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3),
517 kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5),
518 kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),
519
520 kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
521 kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
522 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
523 kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
524 kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
525 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5),
526 kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6),
527 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
528
529 kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
530 kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
531 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
532 kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
533 kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
534 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5),
535 kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6),
536 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
537
538 kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
539 kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
540 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
541 kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
542 kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
543 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5),
544 kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6),
545 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
546
547 kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
548 kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
549 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
550 kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
551 kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
552 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5),
553 kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6),
554 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
555
556 kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
557 kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
558 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
559 kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
560 kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
561 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5),
562 kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6),
563 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
564
565 kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
566 kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
567 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
568 kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
569 kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
570 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5),
571 kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6),
572 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
573
574 kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
575 kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
576 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
577 kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
578 kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
579 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5),
580 kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6),
581 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
582
583 kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
584 kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
585 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
586 kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
587 kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
588 kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5),
589 kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6),
590 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
591
592 kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0),
593 kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1),
594 kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2),
595 kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3),
596 kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4),
597 kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6),
598 kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7),
599
600 kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0),
601 kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),
602 kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),
603
604 kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0),
605 kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),
606 kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),
607 kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),
608 kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5),
609 kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),
610
611 kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0),
612 kPLL0_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),
613 kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
614 kPLL1_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 5),
615 kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),
616
617 kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0),
618 kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1),
619
620 kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0),
621 kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1),
622 kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2),
623 kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7),
624
625 kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0),
626 kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1),
627 kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2),
628 kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7),
629
630 kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0),
631 kFRO1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1),
632 kOSC32K_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2),
633 kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7),
634
635 kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0),
636 kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1),
637 kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2),
638 kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3),
639 kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7),
640
641 kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0),
642 kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1),
643 kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3),
644 kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4),
645 kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5),
646 kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6),
647 kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7),
648
649 kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0),
650 kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1),
651 kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3),
652 kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4),
653 kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5),
654 kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6),
655 kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7),
656
657 kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0),
658 kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1),
659 kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3),
660 kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4),
661 kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5),
662 kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6),
663 kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7),
664
665 kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0),
666 kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1),
667 kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3),
668 kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4),
669 kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5),
670 kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6),
671 kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7),
672
673 kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0),
674 kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1),
675 kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3),
676 kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4),
677 kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5),
678 kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6),
679 kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7),
680 kNONE_to_NONE = (int)0x80000000U,
681} clock_attach_id_t;
682
683/* Clock dividers */
684typedef enum _clock_div_name
685{
686 kCLOCK_DivSystickClk0 = 0,
687 kCLOCK_DivSystickClk1 = 1,
688 kCLOCK_DivArmTrClkDiv = 2,
689 kCLOCK_DivFlexFrg0 = 8,
690 kCLOCK_DivFlexFrg1 = 9,
691 kCLOCK_DivFlexFrg2 = 10,
692 kCLOCK_DivFlexFrg3 = 11,
693 kCLOCK_DivFlexFrg4 = 12,
694 kCLOCK_DivFlexFrg5 = 13,
695 kCLOCK_DivFlexFrg6 = 14,
696 kCLOCK_DivFlexFrg7 = 15,
697 kCLOCK_DivAhbClk = 32,
698 kCLOCK_DivClkOut = 33,
699 kCLOCK_DivFrohfClk = 34,
700 kCLOCK_DivWdtClk = 35,
701 kCLOCK_DivAdcAsyncClk = 37,
702 kCLOCK_DivUsb0Clk = 38,
703 kCLOCK_DivMClk = 43,
704 kCLOCK_DivSctClk = 45,
705 kCLOCK_DivSdioClk = 47,
706 kCLOCK_DivPll0Clk = 49
707} clock_div_name_t;
708
709/*******************************************************************************
710 * API
711 ******************************************************************************/
712
713#if defined(__cplusplus)
714extern "C" {
715#endif /* __cplusplus */
716
717/**
718 * @brief Enable the clock for specific IP.
719 * @param clk Clock to be enabled.
720 * @return Nothing
721 */
722static inline void CLOCK_EnableClock(clock_ip_name_t clk)
723{
724 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
725 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
726}
727/**
728 * @brief Disable the clock for specific IP.
729 * @param clk Clock to be Disabled.
730 * @return Nothing
731 */
732static inline void CLOCK_DisableClock(clock_ip_name_t clk)
733{
734 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
735 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
736}
737/**
738 * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
739 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
740 * enabled.
741 * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)
742 * @return returns success or fail status.
743 */
744status_t CLOCK_SetupFROClocking(uint32_t iFreq);
745/**
746 * @brief Set the flash wait states for the input freuqency.
747 * @param iFreq : Input frequency
748 * @return Nothing
749 */
750void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);
751/**
752 * @brief Initialize the external osc clock to given frequency.
753 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
754 * @return returns success or fail status.
755 */
756status_t CLOCK_SetupExtClocking(uint32_t iFreq);
757/**
758 * @brief Initialize the I2S MCLK clock to given frequency.
759 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
760 * @return returns success or fail status.
761 */
762status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq);
763/**
764 * @brief Initialize the PLU CLKIN clock to given frequency.
765 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
766 * @return returns success or fail status.
767 */
768status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq);
769/**
770 * @brief Configure the clock selection muxes.
771 * @param connection : Clock to be configured.
772 * @return Nothing
773 */
774void CLOCK_AttachClk(clock_attach_id_t connection);
775/**
776 * @brief Get the actual clock attach id.
777 * This fuction uses the offset in input attach id, then it reads the actual source value in
778 * the register and combine the offset to obtain an actual attach id.
779 * @param attachId : Clock attach id to get.
780 * @return Clock source value.
781 */
782clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
783/**
784 * @brief Setup peripheral clock dividers.
785 * @param div_name : Clock divider name
786 * @param divided_by_value: Value to be divided
787 * @param reset : Whether to reset the divider counter.
788 * @return Nothing
789 */
790void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
791/**
792 * @brief Setup rtc 1khz clock divider.
793 * @param divided_by_value: Value to be divided
794 * @return Nothing
795 */
796void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value);
797/**
798 * @brief Setup rtc 1hz clock divider.
799 * @param divided_by_value: Value to be divided
800 * @return Nothing
801 */
802void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value);
803
804/**
805 * @brief Set the flexcomm output frequency.
806 * @param id : flexcomm instance id
807 * @param freq : output frequency
808 * @return 0 : the frequency range is out of range.
809 * 1 : switch successfully.
810 */
811uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq);
812
813/*! @brief Return Frequency of flexcomm input clock
814 * @param id : flexcomm instance id
815 * @return Frequency value
816 */
817uint32_t CLOCK_GetFlexCommInputClock(uint32_t id);
818
819/*! @brief Return Frequency of selected clock
820 * @return Frequency of selected clock
821 */
822uint32_t CLOCK_GetFreq(clock_name_t clockName);
823/*! @brief Return Frequency of FRO 12MHz
824 * @return Frequency of FRO 12MHz
825 */
826uint32_t CLOCK_GetFro12MFreq(void);
827/*! @brief Return Frequency of FRO 1MHz
828 * @return Frequency of FRO 1MHz
829 */
830uint32_t CLOCK_GetFro1MFreq(void);
831/*! @brief Return Frequency of ClockOut
832 * @return Frequency of ClockOut
833 */
834uint32_t CLOCK_GetClockOutClkFreq(void);
835/*! @brief Return Frequency of Adc Clock
836 * @return Frequency of Adc.
837 */
838uint32_t CLOCK_GetAdcClkFreq(void);
839/*! @brief Return Frequency of Usb0 Clock
840 * @return Frequency of Usb0 Clock.
841 */
842uint32_t CLOCK_GetUsb0ClkFreq(void);
843/*! @brief Return Frequency of Usb1 Clock
844 * @return Frequency of Usb1 Clock.
845 */
846uint32_t CLOCK_GetUsb1ClkFreq(void);
847/*! @brief Return Frequency of MClk Clock
848 * @return Frequency of MClk Clock.
849 */
850uint32_t CLOCK_GetMclkClkFreq(void);
851/*! @brief Return Frequency of SCTimer Clock
852 * @return Frequency of SCTimer Clock.
853 */
854uint32_t CLOCK_GetSctClkFreq(void);
855/*! @brief Return Frequency of SDIO Clock
856 * @return Frequency of SDIO Clock.
857 */
858uint32_t CLOCK_GetSdioClkFreq(void);
859/*! @brief Return Frequency of External Clock
860 * @return Frequency of External Clock. If no external clock is used returns 0.
861 */
862uint32_t CLOCK_GetExtClkFreq(void);
863/*! @brief Return Frequency of Watchdog
864 * @return Frequency of Watchdog
865 */
866uint32_t CLOCK_GetWdtClkFreq(void);
867/*! @brief Return Frequency of High-Freq output of FRO
868 * @return Frequency of High-Freq output of FRO
869 */
870uint32_t CLOCK_GetFroHfFreq(void);
871/*! @brief Return Frequency of PLL
872 * @return Frequency of PLL
873 */
874uint32_t CLOCK_GetPll0OutFreq(void);
875/*! @brief Return Frequency of USB PLL
876 * @return Frequency of PLL
877 */
878uint32_t CLOCK_GetPll1OutFreq(void);
879/*! @brief Return Frequency of 32kHz osc
880 * @return Frequency of 32kHz osc
881 */
882uint32_t CLOCK_GetOsc32KFreq(void);
883/*! @brief Return Frequency of Core System
884 * @return Frequency of Core System
885 */
886uint32_t CLOCK_GetCoreSysClkFreq(void);
887/*! @brief Return Frequency of I2S MCLK Clock
888 * @return Frequency of I2S MCLK Clock
889 */
890uint32_t CLOCK_GetI2SMClkFreq(void);
891/*! @brief Return Frequency of PLU CLKIN Clock
892 * @return Frequency of PLU CLKIN Clock
893 */
894uint32_t CLOCK_GetPLUClkInFreq(void);
895/*! @brief Return Frequency of FlexComm Clock
896 * @return Frequency of FlexComm Clock
897 */
898uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
899/*! @brief Return Frequency of High speed SPI Clock
900 * @return Frequency of High speed SPI Clock
901 */
902uint32_t CLOCK_GetHsLspiClkFreq(void);
903/*! @brief Return Frequency of CTimer functional Clock
904 * @return Frequency of CTimer functional Clock
905 */
906uint32_t CLOCK_GetCTimerClkFreq(uint32_t id);
907/*! @brief Return Frequency of SystickClock
908 * @return Frequency of Systick Clock
909 */
910uint32_t CLOCK_GetSystickClkFreq(uint32_t id);
911
912/*! @brief Return PLL0 input clock rate
913 * @return PLL0 input clock rate
914 */
915uint32_t CLOCK_GetPLL0InClockRate(void);
916
917/*! @brief Return PLL1 input clock rate
918 * @return PLL1 input clock rate
919 */
920uint32_t CLOCK_GetPLL1InClockRate(void);
921
922/*! @brief Return PLL0 output clock rate
923 * @param recompute : Forces a PLL rate recomputation if true
924 * @return PLL0 output clock rate
925 * @note The PLL rate is cached in the driver in a variable as
926 * the rate computation function can take some time to perform. It
927 * is recommended to use 'false' with the 'recompute' parameter.
928 */
929uint32_t CLOCK_GetPLL0OutClockRate(bool recompute);
930
931/*! @brief Enables and disables PLL0 bypass mode
932 * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass
933 * @return PLL0 output clock rate
934 */
935__STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass)
936{
937 if (bypass)
938 {
939 SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);
940 }
941 else
942 {
943 SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);
944 }
945}
946
947/*! @brief Enables and disables PLL1 bypass mode
948 * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass
949 * @return PLL1 output clock rate
950 */
951__STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass)
952{
953 if (bypass)
954 {
955 SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);
956 }
957 else
958 {
959 SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);
960 }
961}
962
963/*! @brief Check if PLL is locked or not
964 * @return true if the PLL is locked, false if not locked
965 */
966__STATIC_INLINE bool CLOCK_IsPLL0Locked(void)
967{
968 return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL);
969}
970
971/*! @brief Check if PLL1 is locked or not
972 * @return true if the PLL1 is locked, false if not locked
973 */
974__STATIC_INLINE bool CLOCK_IsPLL1Locked(void)
975{
976 return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL);
977}
978
979/*! @brief Store the current PLL0 rate
980 * @param rate: Current rate of the PLL0
981 * @return Nothing
982 **/
983void CLOCK_SetStoredPLL0ClockRate(uint32_t rate);
984
985/*! @brief PLL configuration structure flags for 'flags' field
986 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
987 *
988 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
989 * configuration structure must be assigned with the expected PLL frequency. If the
990 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
991 * function and the driver will determine the PLL rate from the currently selected
992 * PLL source. This flag might be used to configure the PLL input clock more accurately
993 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
994 *
995 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
996 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
997 * are not used.<br>
998 */
999#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
1000#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U)
1001/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */
1002
1003/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency
1004 * See (MF) field in the PLL0SSCG1 register in the UM.
1005 */
1006typedef enum _ss_progmodfm
1007{
1008 kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */
1009 kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */
1010 kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */
1011 kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */
1012 kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */
1013 kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */
1014 kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */
1015 kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */
1016} ss_progmodfm_t;
1017
1018/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth
1019 * See (MR) field in the PLL0SSCG1 register in the UM.
1020 */
1021typedef enum _ss_progmoddp
1022{
1023 kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */
1024 kSS_MR_K1 = (1 << 23), /*!< k = 1 */
1025 kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */
1026 kSS_MR_K2 = (3 << 23), /*!< k = 2 */
1027 kSS_MR_K3 = (4 << 23), /*!< k = 3 */
1028 kSS_MR_K4 = (5 << 23), /*!< k = 4 */
1029 kSS_MR_K6 = (6 << 23), /*!< k = 6 */
1030 kSS_MR_K8 = (7 << 23) /*!< k = 8 */
1031} ss_progmoddp_t;
1032
1033/*! @brief PLL Spread Spectrum (SS) Modulation waveform control
1034 * See (MC) field in the PLL0SSCG1 register in the UM.<br>
1035 * Compensation for low pass filtering of the PLL to get a triangular
1036 * modulation at the output of the PLL, giving a flat frequency spectrum.
1037 */
1038typedef enum _ss_modwvctrl
1039{
1040 kSS_MC_NOC = (0 << 26), /*!< no compensation */
1041 kSS_MC_RECC = (2 << 26), /*!< recommended setting */
1042 kSS_MC_MAXC = (3 << 26), /*!< max. compensation */
1043} ss_modwvctrl_t;
1044
1045/*! @brief PLL configuration structure
1046 *
1047 * This structure can be used to configure the settings for a PLL
1048 * setup structure. Fill in the desired configuration for the PLL
1049 * and call the PLL setup function to fill in a PLL setup structure.
1050 */
1051typedef struct _pll_config
1052{
1053 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
1054 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
1055 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
1056 ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using
1057 PLL_CONFIGFLAG_FORCENOFRACT flag */
1058 ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using
1059 PLL_CONFIGFLAG_FORCENOFRACT flag */
1060 ss_modwvctrl_t
1061 ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
1062 bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using
1063 PLL_CONFIGFLAG_FORCENOFRACT flag */
1064
1065} pll_config_t;
1066
1067/*! @brief PLL setup structure flags for 'flags' field
1068 * These flags control how the PLL setup function sets up the PLL
1069 */
1070#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */
1071#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
1072#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */
1073#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */
1074
1075/*! @brief PLL0 setup structure
1076 * This structure can be used to pre-build a PLL setup configuration
1077 * at run-time and quickly set the PLL to the configuration. It can be
1078 * populated with the PLL setup function. If powering up or waiting
1079 * for PLL lock, the PLL input clock source should be configured prior
1080 * to PLL setup.
1081 */
1082typedef struct _pll_setup
1083{
1084 uint32_t pllctrl; /*!< PLL control register PLL0CTRL */
1085 uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */
1086 uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */
1087 uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */
1088 uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/
1089 uint32_t pllRate; /*!< Acutal PLL rate */
1090 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
1091} pll_setup_t;
1092
1093/*! @brief PLL status definitions
1094 */
1095typedef enum _pll_error
1096{
1097 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
1098 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
1099 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
1100 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
1101 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
1102 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
1103 kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */
1104 kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */
1105} pll_error_t;
1106
1107/*! @brief USB FS clock source definition. */
1108typedef enum _clock_usbfs_src
1109{
1110 kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */
1111 kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */
1112 kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
1113 kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */
1114
1115 kCLOCK_UsbfsSrcNone =
1116 SYSCON_USB0CLKSEL_SEL(7) /*!<this may be selected in order to reduce power when no output is needed. */
1117} clock_usbfs_src_t;
1118
1119/*! @brief USBhs clock source definition. */
1120typedef enum _clock_usbhs_src
1121{
1122 kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not
1123 care the clock source. */
1124} clock_usbhs_src_t;
1125
1126/*! @brief Source of the USB HS PHY. */
1127typedef enum _clock_usb_phy_src
1128{
1129 kCLOCK_UsbPhySrcExt = 0U, /*!< Use external crystal. */
1130} clock_usb_phy_src_t;
1131
1132/*! @brief Return PLL0 output clock rate from setup structure
1133 * @param pSetup : Pointer to a PLL setup structure
1134 * @return System PLL output clock rate the setup structure will generate
1135 */
1136uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup);
1137
1138/*! @brief Set PLL0 output based on the passed PLL setup data
1139 * @param pControl : Pointer to populated PLL control structure to generate setup with
1140 * @param pSetup : Pointer to PLL setup structure to be filled
1141 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1142 * @note Actual frequency for setup may vary from the desired frequency based on the
1143 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1144 */
1145pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup);
1146
1147/*! @brief Set PLL output from PLL setup structure (precise frequency)
1148 * @param pSetup : Pointer to populated PLL setup structure
1149 * @param flagcfg : Flag configuration for PLL config structure
1150 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1151 * @note This function will power off the PLL, setup the PLL with the
1152 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1153 * and adjust system voltages to the new PLL rate. The function will not
1154 * alter any source clocks (ie, main systen clock) that may use the PLL,
1155 * so these should be setup prior to and after exiting the function.
1156 */
1157pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg);
1158
1159/**
1160 * @brief Set PLL output from PLL setup structure (precise frequency)
1161 * @param pSetup : Pointer to populated PLL setup structure
1162 * @return kStatus_PLL_Success on success, or PLL setup error code
1163 * @note This function will power off the PLL, setup the PLL with the
1164 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1165 * and adjust system voltages to the new PLL rate. The function will not
1166 * alter any source clocks (ie, main systen clock) that may use the PLL,
1167 * so these should be setup prior to and after exiting the function.
1168 */
1169pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup);
1170
1171/**
1172 * @brief Set PLL output from PLL setup structure (precise frequency)
1173 * @param pSetup : Pointer to populated PLL setup structure
1174 * @return kStatus_PLL_Success on success, or PLL setup error code
1175 * @note This function will power off the PLL, setup the PLL with the
1176 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1177 * and adjust system voltages to the new PLL rate. The function will not
1178 * alter any source clocks (ie, main systen clock) that may use the PLL,
1179 * so these should be setup prior to and after exiting the function.
1180 */
1181pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup);
1182
1183/*! @brief Set PLL0 output based on the multiplier and input frequency
1184 * @param multiply_by : multiplier
1185 * @param input_freq : Clock input frequency of the PLL
1186 * @return Nothing
1187 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
1188 * function does not disable or enable PLL power, wait for PLL lock,
1189 * or adjust system voltages. These must be done in the application.
1190 * The function will not alter any source clocks (ie, main systen clock)
1191 * that may use the PLL, so these should be setup prior to and after
1192 * exiting the function.
1193 */
1194void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq);
1195
1196/*! @brief Disable USB clock.
1197 *
1198 * Disable USB clock.
1199 */
1200static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
1201{
1202 CLOCK_DisableClock(clk);
1203}
1204
1205/*! @brief Enable USB Device FS clock.
1206 * @param src : clock source
1207 * @param freq: clock frequency
1208 * Enable USB Device Full Speed clock.
1209 */
1210bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq);
1211
1212/*! @brief Enable USB HOST FS clock.
1213 * @param src : clock source
1214 * @param freq: clock frequency
1215 * Enable USB HOST Full Speed clock.
1216 */
1217bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq);
1218
1219/*! @brief Enable USB phy clock.
1220 * Enable USB phy clock.
1221 */
1222bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1223
1224/*! @brief Enable USB Device HS clock.
1225 * Enable USB Device High Speed clock.
1226 */
1227bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq);
1228
1229/*! @brief Enable USB HOST HS clock.
1230 * Enable USB HOST High Speed clock.
1231 */
1232bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq);
1233
1234#if defined(__cplusplus)
1235}
1236#endif /* __cplusplus */
1237
1238/*! @} */
1239
1240#endif /* _FSL_CLOCK_H_ */
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