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1/*
2** ###################################################################
3** Processors: LPC802M001JDH16
4** LPC802M001JDH20
5** LPC802M001JHI33
6** LPC802M011JDH20
7** LPC802UK
8**
9** Compilers: GNU C Compiler
10** IAR ANSI C/C++ Compiler for ARM
11** Keil ARM C/C++ Compiler
12** MCUXpresso Compiler
13**
14** Reference manual: LPC802 User manual Rev.1.0 1 Dec 2017
15** Version: rev. 1.0, 2018-01-09
16** Build: b200513
17**
18** Abstract:
19** CMSIS Peripheral Access Layer for LPC802
20**
21** Copyright 1997-2016 Freescale Semiconductor, Inc.
22** Copyright 2016-2020 NXP
23** All rights reserved.
24**
25** SPDX-License-Identifier: BSD-3-Clause
26**
27** http: www.nxp.com
28** mail: [email protected]
29**
30** Revisions:
31** - rev. 1.0 (2018-01-09)
32** Initial version.
33**
34** ###################################################################
35*/
36
37/*!
38 * @file LPC802.h
39 * @version 1.0
40 * @date 2018-01-09
41 * @brief CMSIS Peripheral Access Layer for LPC802
42 *
43 * CMSIS Peripheral Access Layer for LPC802
44 */
45
46#ifndef _LPC802_H_
47#define _LPC802_H_ /**< Symbol preventing repeated inclusion */
48
49/** Memory map major version (memory maps with equal major version number are
50 * compatible) */
51#define MCU_MEM_MAP_VERSION 0x0100U
52/** Memory map minor version */
53#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
54
55
56/* ----------------------------------------------------------------------------
57 -- Interrupt vector numbers
58 ---------------------------------------------------------------------------- */
59
60/*!
61 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
62 * @{
63 */
64
65/** Interrupt Number Definitions */
66#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
67
68typedef enum IRQn {
69 /* Auxiliary constants */
70 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
71
72 /* Core interrupts */
73 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
74 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
75 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
76 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
77 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
78
79 /* Device specific interrupts */
80 SPI0_IRQn = 0, /**< SPI0 interrupt */
81 Reserved17_IRQn = 1, /**< Reserved interrupt */
82 Reserved18_IRQn = 2, /**< Reserved interrupt */
83 USART0_IRQn = 3, /**< USART0 interrupt */
84 USART1_IRQn = 4, /**< USART1 interrupt */
85 Reserved21_IRQn = 5, /**< Reserved interrupt */
86 Reserved22_IRQn = 6, /**< Reserved interrupt */
87 Reserved23_IRQn = 7, /**< Reserved interrupt */
88 I2C0_IRQn = 8, /**< I2C0 interrupt */
89 Reserved25_IRQn = 9, /**< Reserved interrupt */
90 MRT0_IRQn = 10, /**< Multi-rate timer interrupt */
91 CMP_IRQn = 11, /**< Analog comparator interrupt */
92 WDT_IRQn = 12, /**< Windowed watchdog timer interrupt */
93 BOD_IRQn = 13, /**< BOD interrupts */
94 FLASH_IRQn = 14, /**< flash interrupt */
95 WKT_IRQn = 15, /**< Self-wake-up timer interrupt */
96 ADC0_SEQA_IRQn = 16, /**< ADC0 sequence A completion. */
97 ADC0_SEQB_IRQn = 17, /**< ADC0 sequence B completion. */
98 ADC0_THCMP_IRQn = 18, /**< ADC0 threshold compare and error. */
99 ADC0_OVR_IRQn = 19, /**< ADC0 overrun */
100 Reserved36_IRQn = 20, /**< Reserved interrupt */
101 Reserved37_IRQn = 21, /**< Reserved interrupt */
102 Reserved38_IRQn = 22, /**< Reserved interrupt */
103 CTIMER0_IRQn = 23, /**< Timer interrupt */
104 PIN_INT0_IRQn = 24, /**< Pin interrupt 0 or pattern match engine slice 0 interrupt */
105 PIN_INT1_IRQn = 25, /**< Pin interrupt 1 or pattern match engine slice 1 interrupt */
106 PIN_INT2_IRQn = 26, /**< Pin interrupt 2 or pattern match engine slice 2 interrupt */
107 PIN_INT3_IRQn = 27, /**< Pin interrupt 3 or pattern match engine slice 3 interrupt */
108 PIN_INT4_IRQn = 28, /**< Pin interrupt 4 or pattern match engine slice 4 interrupt */
109 PIN_INT5_IRQn = 29, /**< Pin interrupt 5 or pattern match engine slice 5 interrupt */
110 PIN_INT6_IRQn = 30, /**< Pin interrupt 6 or pattern match engine slice 6 interrupt */
111 PIN_INT7_IRQn = 31 /**< Pin interrupt 7 or pattern match engine slice 7 interrupt */
112} IRQn_Type;
113
114/*!
115 * @}
116 */ /* end of group Interrupt_vector_numbers */
117
118
119/* ----------------------------------------------------------------------------
120 -- Cortex M0 Core Configuration
121 ---------------------------------------------------------------------------- */
122
123/*!
124 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
125 * @{
126 */
127
128#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
129#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
130#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */
131#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
132#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
133
134#include "core_cm0plus.h" /* Core Peripheral Access Layer */
135#include "system_LPC802.h" /* Device specific configuration file */
136
137/*!
138 * @}
139 */ /* end of group Cortex_Core_Configuration */
140
141
142/* ----------------------------------------------------------------------------
143 -- Device Peripheral Access Layer
144 ---------------------------------------------------------------------------- */
145
146/*!
147 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
148 * @{
149 */
150
151
152/*
153** Start of section using anonymous unions
154*/
155
156#if defined(__ARMCC_VERSION)
157 #if (__ARMCC_VERSION >= 6010050)
158 #pragma clang diagnostic push
159 #else
160 #pragma push
161 #pragma anon_unions
162 #endif
163#elif defined(__GNUC__)
164 /* anonymous unions are enabled by default */
165#elif defined(__IAR_SYSTEMS_ICC__)
166 #pragma language=extended
167#else
168 #error Not supported compiler type
169#endif
170
171/* ----------------------------------------------------------------------------
172 -- ACOMP Peripheral Access Layer
173 ---------------------------------------------------------------------------- */
174
175/*!
176 * @addtogroup ACOMP_Peripheral_Access_Layer ACOMP Peripheral Access Layer
177 * @{
178 */
179
180/** ACOMP - Register Layout Typedef */
181typedef struct {
182 __IO uint32_t CTRL; /**< Comparator control register, offset: 0x0 */
183 __IO uint32_t LAD; /**< Voltage ladder register, offset: 0x4 */
184} ACOMP_Type;
185
186/* ----------------------------------------------------------------------------
187 -- ACOMP Register Masks
188 ---------------------------------------------------------------------------- */
189
190/*!
191 * @addtogroup ACOMP_Register_Masks ACOMP Register Masks
192 * @{
193 */
194
195/*! @name CTRL - Comparator control register */
196/*! @{ */
197#define ACOMP_CTRL_EDGESEL_MASK (0x18U)
198#define ACOMP_CTRL_EDGESEL_SHIFT (3U)
199/*! EDGESEL - This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below):
200 * 0b00..Falling edges
201 * 0b01..Rising edges
202 * 0b10..Both edges
203 * 0b11..Both edges
204 */
205#define ACOMP_CTRL_EDGESEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_EDGESEL_SHIFT)) & ACOMP_CTRL_EDGESEL_MASK)
206#define ACOMP_CTRL_COMPSA_MASK (0x40U)
207#define ACOMP_CTRL_COMPSA_SHIFT (6U)
208/*! COMPSA - Comparator output control
209 * 0b0..Comparator output is used directly.
210 * 0b1..Comparator output is synchronized to the bus clock for output to other modules.
211 */
212#define ACOMP_CTRL_COMPSA(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPSA_SHIFT)) & ACOMP_CTRL_COMPSA_MASK)
213#define ACOMP_CTRL_COMP_VP_SEL_MASK (0x700U)
214#define ACOMP_CTRL_COMP_VP_SEL_SHIFT (8U)
215/*! COMP_VP_SEL - Selects positive voltage input
216 * 0b000..VOLTAGE_LADDER_OUTPUT
217 * 0b001..ACMP_I1
218 * 0b010..ACMP_I2
219 * 0b011..ACMP_I3
220 * 0b100..ACMP_I4
221 * 0b101..ACMP_I5
222 * 0b110..Band gap. Internal reference voltage.
223 * 0b111..DAC0 output
224 */
225#define ACOMP_CTRL_COMP_VP_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMP_VP_SEL_SHIFT)) & ACOMP_CTRL_COMP_VP_SEL_MASK)
226#define ACOMP_CTRL_COMP_VM_SEL_MASK (0x3800U)
227#define ACOMP_CTRL_COMP_VM_SEL_SHIFT (11U)
228/*! COMP_VM_SEL - Selects negative voltage input
229 * 0b000..VOLTAGE_LADDER_OUTPUT
230 * 0b001..ACMP_I1
231 * 0b010..ACMP_I2
232 * 0b011..ACMP_I3
233 * 0b100..ACMP_I4
234 * 0b101..ACMP_I5
235 * 0b110..Band gap. Internal reference voltage.
236 * 0b111..DAC0 output
237 */
238#define ACOMP_CTRL_COMP_VM_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMP_VM_SEL_SHIFT)) & ACOMP_CTRL_COMP_VM_SEL_MASK)
239#define ACOMP_CTRL_EDGECLR_MASK (0x100000U)
240#define ACOMP_CTRL_EDGECLR_SHIFT (20U)
241/*! EDGECLR - Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request,
242 * toggle the EDGECLR bit by first writing a 1 and then a 0.
243 */
244#define ACOMP_CTRL_EDGECLR(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_EDGECLR_SHIFT)) & ACOMP_CTRL_EDGECLR_MASK)
245#define ACOMP_CTRL_COMPSTAT_MASK (0x200000U)
246#define ACOMP_CTRL_COMPSTAT_SHIFT (21U)
247/*! COMPSTAT - Comparator status. This bit reflects the state of the comparator output.
248 */
249#define ACOMP_CTRL_COMPSTAT(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPSTAT_SHIFT)) & ACOMP_CTRL_COMPSTAT_MASK)
250#define ACOMP_CTRL_COMPEDGE_MASK (0x800000U)
251#define ACOMP_CTRL_COMPEDGE_SHIFT (23U)
252/*! COMPEDGE - Comparator edge-detect status.
253 */
254#define ACOMP_CTRL_COMPEDGE(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPEDGE_SHIFT)) & ACOMP_CTRL_COMPEDGE_MASK)
255#define ACOMP_CTRL_INTENA_MASK (0x1000000U)
256#define ACOMP_CTRL_INTENA_SHIFT (24U)
257/*! INTENA - Must be set to generate interrupts.
258 */
259#define ACOMP_CTRL_INTENA(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_INTENA_SHIFT)) & ACOMP_CTRL_INTENA_MASK)
260#define ACOMP_CTRL_HYS_MASK (0x6000000U)
261#define ACOMP_CTRL_HYS_SHIFT (25U)
262/*! HYS - Controls the hysteresis of the comparator. When the comparator is outputting a certain
263 * state, this is the difference between the selected signals, in the opposite direction from the
264 * state being output, that will switch the output.
265 * 0b00..None (the output will switch as the voltages cross)
266 * 0b01..5 mv
267 * 0b10..10 mv
268 * 0b11..20 mv
269 */
270#define ACOMP_CTRL_HYS(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_HYS_SHIFT)) & ACOMP_CTRL_HYS_MASK)
271/*! @} */
272
273/*! @name LAD - Voltage ladder register */
274/*! @{ */
275#define ACOMP_LAD_LADEN_MASK (0x1U)
276#define ACOMP_LAD_LADEN_SHIFT (0U)
277/*! LADEN - Voltage ladder enable
278 */
279#define ACOMP_LAD_LADEN(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADEN_SHIFT)) & ACOMP_LAD_LADEN_MASK)
280#define ACOMP_LAD_LADSEL_MASK (0x3EU)
281#define ACOMP_LAD_LADSEL_SHIFT (1U)
282/*! LADSEL - Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000
283 * = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref
284 */
285#define ACOMP_LAD_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADSEL_SHIFT)) & ACOMP_LAD_LADSEL_MASK)
286#define ACOMP_LAD_LADREF_MASK (0x40U)
287#define ACOMP_LAD_LADREF_SHIFT (6U)
288/*! LADREF - Selects the reference voltage Vref for the voltage ladder.
289 * 0b0..Supply pin VDD
290 * 0b1..VDDCMP pin
291 */
292#define ACOMP_LAD_LADREF(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADREF_SHIFT)) & ACOMP_LAD_LADREF_MASK)
293/*! @} */
294
295
296/*!
297 * @}
298 */ /* end of group ACOMP_Register_Masks */
299
300
301/* ACOMP - Peripheral instance base addresses */
302/** Peripheral ACOMP base address */
303#define ACOMP_BASE (0x40024000u)
304/** Peripheral ACOMP base pointer */
305#define ACOMP ((ACOMP_Type *)ACOMP_BASE)
306/** Array initializer of ACOMP peripheral base addresses */
307#define ACOMP_BASE_ADDRS { ACOMP_BASE }
308/** Array initializer of ACOMP peripheral base pointers */
309#define ACOMP_BASE_PTRS { ACOMP }
310
311/*!
312 * @}
313 */ /* end of group ACOMP_Peripheral_Access_Layer */
314
315
316/* ----------------------------------------------------------------------------
317 -- ADC Peripheral Access Layer
318 ---------------------------------------------------------------------------- */
319
320/*!
321 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
322 * @{
323 */
324
325/** ADC - Register Layout Typedef */
326typedef struct {
327 __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
328 uint8_t RESERVED_0[4];
329 __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
330 __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
331 uint8_t RESERVED_1[8];
332 __I uint32_t DAT[12]; /**< ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N., array offset: 0x20, array step: 0x4 */
333 __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
334 __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
335 __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
336 __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
337 __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
338 __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
339 __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
340} ADC_Type;
341
342/* ----------------------------------------------------------------------------
343 -- ADC Register Masks
344 ---------------------------------------------------------------------------- */
345
346/*!
347 * @addtogroup ADC_Register_Masks ADC Register Masks
348 * @{
349 */
350
351/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
352/*! @{ */
353#define ADC_CTRL_CLKDIV_MASK (0xFFU)
354#define ADC_CTRL_CLKDIV_SHIFT (0U)
355/*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce
356 * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically,
357 * software should program the smallest value in this field that yields this maximum clock rate or
358 * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may
359 * be desirable. This field is ignored in the asynchronous operating mode.
360 */
361#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
362#define ADC_CTRL_ASYNMODE_MASK (0x100U)
363#define ADC_CTRL_ASYNMODE_SHIFT (8U)
364/*! ASYNMODE - Select clock mode.
365 * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in
366 * the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to
367 * eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger.
368 * In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC
369 * input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger
370 * pulse.
371 * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
372 */
373#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
374#define ADC_CTRL_LPWRMODE_MASK (0x400U)
375#define ADC_CTRL_LPWRMODE_SHIFT (10U)
376/*! LPWRMODE - The low-power ADC mode
377 * 0b0..The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested.
378 * 0b1..The low-power ADC mode is enabled. The analog circuitry is automatically powered-down when no conversions
379 * are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is
380 * enabled. After the required start-up time, the requested conversion will be launched. Once the conversion
381 * completes, the analog-circuitry will again be powered-down provided no further conversions are pending.
382 * Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are
383 * required relatively infrequently. The penalty for using this mode is an approximately FIFTEEN ADC CLOCK delay (30
384 * clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger
385 * event occurs until sampling of the A/D input commences. Note: This mode will NOT power-up the A/D if the
386 * ADC_ENA bit is low.
387 */
388#define ADC_CTRL_LPWRMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_LPWRMODE_SHIFT)) & ADC_CTRL_LPWRMODE_MASK)
389/*! @} */
390
391/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
392/*! @{ */
393#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU)
394#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U)
395/*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this
396 * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be
397 * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1
398 * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via
399 * software command, ADC conversions will be performed on each enabled channel, in sequence,
400 * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31)
401 * is LOW. It is allowed to change this field and set bit 31 in the same write.
402 */
403#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
404#define ADC_SEQ_CTRL_TRIGGER_MASK (0x7000U)
405#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U)
406/*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion
407 * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order
408 * to avoid generating a spurious trigger, it is recommended writing to this field only when
409 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
410 */
411#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
412#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U)
413#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U)
414/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In
415 * order to avoid generating a spurious trigger, it is recommended writing to this field only when
416 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
417 * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
418 * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
419 */
420#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
421#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U)
422#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U)
423/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization
424 * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a
425 * conversion. There are slightly different criteria for whether or not this bit can be set
426 * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0):
427 * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already
428 * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer).
429 * Whether this bit is set or not, a trigger pulse must be maintained for at least one system
430 * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be
431 * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse
432 * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and
433 * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be
434 * maintained for one system clock period.
435 * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled.
436 * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled.
437 */
438#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
439#define ADC_SEQ_CTRL_TSAMP_MASK (0x1F00000U)
440#define ADC_SEQ_CTRL_TSAMP_SHIFT (20U)
441/*! TSAMP - Sample Time The default sample period (TSAMP = "00000") at the beginning of each new
442 * conversion is 6.5 ADC clock periods. Depending on a variety of factors including ADC clock rate,
443 * output impedance of the analog source driver, ADC resolution, and the selection of channels,
444 * the sample time may need to be increased. The value programmed into the TSAMP fields dictates
445 * the number of additional ADC clock cycles (beyond 6.5) that the sample period will be extended
446 * by. Note that any additional clocks of sample time inserted will add directly to the overall
447 * number of clocks required for a conversion, effectively reducing the overall conversion
448 * throughput rate.
449 */
450#define ADC_SEQ_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TSAMP_SHIFT)) & ADC_SEQ_CTRL_TSAMP_MASK)
451#define ADC_SEQ_CTRL_START_MASK (0x4000000U)
452#define ADC_SEQ_CTRL_START_SHIFT (26U)
453/*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The
454 * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this
455 * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a
456 * conversion sequence. It will consequently always read back as a zero.
457 */
458#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
459#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U)
460#define ADC_SEQ_CTRL_BURST_SHIFT (27U)
461/*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled
462 * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions
463 * can be halted by clearing this bit. The sequence currently in progress will be completed before
464 * conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
465 */
466#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
467#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U)
468#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U)
469/*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a
470 * single conversion on the next channel in the sequence instead of the default response of
471 * launching an entire sequence of conversions. Once all of the channels comprising a sequence have
472 * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled
473 * channel. Interrupt generation will still occur either after each individual conversion or at
474 * the end of the entire sequence, depending on the state of the MODE bit.
475 */
476#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
477#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U)
478#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U)
479/*! LOWPRIO - Set priority for sequence A.
480 * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
481 * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence
482 * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion
483 * currently in progress will be terminated. The A sequence that was interrupted will automatically resume
484 * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the
485 * conversion sequence will resume from that point.
486 */
487#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
488#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U)
489#define ADC_SEQ_CTRL_MODE_SHIFT (30U)
490/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence
491 * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each
492 * conversion, or the individual channel result registers at the end of the entire sequence. Impacts
493 * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which
494 * overrun conditions contribute to an overrun interrupt as described below.
495 * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC
496 * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The
497 * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger
498 * if enabled.
499 * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A
500 * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in
501 * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun
502 * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
503 */
504#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
505#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U)
506#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U)
507/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be
508 * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state
509 * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered
510 * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care
511 * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE
512 * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be
513 * triggered immediately upon being enabled.
514 * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence
515 * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is
516 * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
517 * 0b1..Enabled. Sequence n is enabled.
518 */
519#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
520/*! @} */
521
522/* The count of ADC_SEQ_CTRL */
523#define ADC_SEQ_CTRL_COUNT (2U)
524
525/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
526/*! @{ */
527#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U)
528#define ADC_SEQ_GDAT_RESULT_SHIFT (4U)
529/*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion
530 * performed under conversion sequence associated with this register. The result is a binary
531 * fraction representing the voltage on the currently-selected input channel as it falls within the
532 * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less
533 * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input
534 * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this
535 * result has not yet been read.
536 */
537#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
538#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U)
539#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U)
540/*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or
541 * within the range established by the designated threshold comparison registers (THRn_LOW and
542 * THRn_HIGH).
543 */
544#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
545#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U)
546#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U)
547/*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a
548 * crossing of the threshold level established by the designated LOW threshold comparison register
549 * (THRn_LOW) and, if so, in what direction the crossing occurred.
550 */
551#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
552#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U)
553#define ADC_SEQ_GDAT_CHN_SHIFT (26U)
554/*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000
555 * identifies channel 0, 0001 channel 1, etc.).
556 */
557#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
558#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U)
559#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U)
560/*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a
561 * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along
562 * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun
563 * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set
564 * to '0' (and if the overrun interrupt is enabled).
565 */
566#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
567#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U)
568#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U)
569/*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded
570 * into the RESULT field. It is cleared whenever this register is read. This bit will cause a
571 * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that
572 * sequence is set to 0 (and if the interrupt is enabled).
573 */
574#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
575/*! @} */
576
577/* The count of ADC_SEQ_GDAT */
578#define ADC_SEQ_GDAT_COUNT (2U)
579
580/*! @name DAT - ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. */
581/*! @{ */
582#define ADC_DAT_RESULT_MASK (0xFFF0U)
583#define ADC_DAT_RESULT_SHIFT (4U)
584/*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed
585 * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin,
586 * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on
587 * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that
588 * the voltage on the input was close to, equal to, or greater than that on VREFP.
589 */
590#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
591#define ADC_DAT_THCMPRANGE_MASK (0x30000U)
592#define ADC_DAT_THCMPRANGE_SHIFT (16U)
593/*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion
594 * was greater than or equal to the value programmed into the designated LOW threshold register
595 * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold
596 * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value
597 * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last
598 * completed conversion was greater than the value programmed into the designated HIGH threshold
599 * register (THRn_HIGH). 0x3 = Reserved.
600 */
601#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
602#define ADC_DAT_THCMPCROSS_MASK (0xC0000U)
603#define ADC_DAT_THCMPCROSS_SHIFT (18U)
604/*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The
605 * most recent completed conversion on this channel had the same relationship (above or below) to
606 * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the
607 * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing
608 * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the
609 * previous sample on this channel was above the threshold value established by the designated LOW
610 * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward
611 * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred
612 * - i.e. the previous sample on this channel was below the threshold value established by the
613 * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
614 */
615#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
616#define ADC_DAT_CHANNEL_MASK (0x3C000000U)
617#define ADC_DAT_CHANNEL_SHIFT (26U)
618/*! CHANNEL - This field is hard-coded to contain the channel number that this particular register
619 * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1
620 * register, etc)
621 */
622#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
623#define ADC_DAT_OVERRUN_MASK (0x40000000U)
624#define ADC_DAT_OVERRUN_SHIFT (30U)
625/*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and
626 * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit
627 * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when
628 * the data related to this channel is read from either of the global SEQn_GDAT registers. This
629 * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if
630 * the overrun interrupt is enabled. While it is allowed to include the same channels in both
631 * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the
632 * data registers associated with any of the channels that are shared between the two sequences. Any
633 * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
634 */
635#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
636#define ADC_DAT_DATAVALID_MASK (0x80000000U)
637#define ADC_DAT_DATAVALID_SHIFT (31U)
638/*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is
639 * cleared whenever this register is read or when the data related to this channel is read from
640 * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in
641 * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in
642 * the data registers associated with any of the channels that are shared between the two
643 * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
644 */
645#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
646/*! @} */
647
648/* The count of ADC_DAT */
649#define ADC_DAT_COUNT (12U)
650
651/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
652/*! @{ */
653#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U)
654#define ADC_THR0_LOW_THRLOW_SHIFT (4U)
655/*! THRLOW - Low threshold value against which ADC results will be compared
656 */
657#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
658/*! @} */
659
660/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
661/*! @{ */
662#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U)
663#define ADC_THR1_LOW_THRLOW_SHIFT (4U)
664/*! THRLOW - Low threshold value against which ADC results will be compared
665 */
666#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
667/*! @} */
668
669/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
670/*! @{ */
671#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U)
672#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U)
673/*! THRHIGH - High threshold value against which ADC results will be compared
674 */
675#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
676/*! @} */
677
678/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
679/*! @{ */
680#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U)
681#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U)
682/*! THRHIGH - High threshold value against which ADC results will be compared
683 */
684#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
685/*! @} */
686
687/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
688/*! @{ */
689#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U)
690#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U)
691/*! CH0_THRSEL - Threshold select for channel 0.
692 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
693 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
694 */
695#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
696#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U)
697#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U)
698/*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0.
699 */
700#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
701#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U)
702#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U)
703/*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0.
704 */
705#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
706#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U)
707#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U)
708/*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0.
709 */
710#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
711#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U)
712#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U)
713/*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0.
714 */
715#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
716#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U)
717#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U)
718/*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0.
719 */
720#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
721#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U)
722#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U)
723/*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0.
724 */
725#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
726#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U)
727#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U)
728/*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0.
729 */
730#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
731#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U)
732#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U)
733/*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0.
734 */
735#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
736#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U)
737#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U)
738/*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0.
739 */
740#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
741#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U)
742#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U)
743/*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0.
744 */
745#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
746#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U)
747#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U)
748/*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0.
749 */
750#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
751/*! @} */
752
753/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
754/*! @{ */
755#define ADC_INTEN_SEQA_INTEN_MASK (0x1U)
756#define ADC_INTEN_SEQA_INTEN_SHIFT (0U)
757/*! SEQA_INTEN - Sequence A interrupt enable.
758 * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled.
759 * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of
760 * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of
761 * conversions, depending on the MODE bit in the SEQA_CTRL register.
762 */
763#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
764#define ADC_INTEN_SEQB_INTEN_MASK (0x2U)
765#define ADC_INTEN_SEQB_INTEN_SHIFT (1U)
766/*! SEQB_INTEN - Sequence B interrupt enable.
767 * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled.
768 * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of
769 * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of
770 * conversions, depending on the MODE bit in the SEQB_CTRL register.
771 */
772#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
773#define ADC_INTEN_OVR_INTEN_MASK (0x4U)
774#define ADC_INTEN_OVR_INTEN_SHIFT (2U)
775/*! OVR_INTEN - Overrun interrupt enable.
776 * 0b0..Disabled. The overrun interrupt is disabled.
777 * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel
778 * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular
779 * sequence is 0, then an overrun in the global data register for that sequence will also cause this
780 * interrupt/DMA trigger to be asserted.
781 */
782#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
783#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U)
784#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U)
785/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0.
786 * 0b00..Disabled.
787 * 0b01..Outside threshold.
788 * 0b10..Crossing threshold.
789 * 0b11..Reserved
790 */
791#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
792#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U)
793#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U)
794/*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0.
795 */
796#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
797#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U)
798#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U)
799/*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0.
800 */
801#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
802#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U)
803#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U)
804/*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0.
805 */
806#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
807#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U)
808#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U)
809/*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0.
810 */
811#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
812#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U)
813#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U)
814/*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0.
815 */
816#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
817#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U)
818#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U)
819/*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0.
820 */
821#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
822#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U)
823#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U)
824/*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0.
825 */
826#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
827#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U)
828#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U)
829/*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0.
830 */
831#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
832#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U)
833#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U)
834/*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0.
835 */
836#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
837#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U)
838#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U)
839/*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0.
840 */
841#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
842#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U)
843#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U)
844/*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0.
845 */
846#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
847/*! @} */
848
849/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
850/*! @{ */
851#define ADC_FLAGS_THCMP0_MASK (0x1U)
852#define ADC_FLAGS_THCMP0_SHIFT (0U)
853/*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or
854 * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by
855 * writing a 1.
856 */
857#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
858#define ADC_FLAGS_THCMP1_MASK (0x2U)
859#define ADC_FLAGS_THCMP1_SHIFT (1U)
860/*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0.
861 */
862#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
863#define ADC_FLAGS_THCMP2_MASK (0x4U)
864#define ADC_FLAGS_THCMP2_SHIFT (2U)
865/*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0.
866 */
867#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
868#define ADC_FLAGS_THCMP3_MASK (0x8U)
869#define ADC_FLAGS_THCMP3_SHIFT (3U)
870/*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0.
871 */
872#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
873#define ADC_FLAGS_THCMP4_MASK (0x10U)
874#define ADC_FLAGS_THCMP4_SHIFT (4U)
875/*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0.
876 */
877#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
878#define ADC_FLAGS_THCMP5_MASK (0x20U)
879#define ADC_FLAGS_THCMP5_SHIFT (5U)
880/*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0.
881 */
882#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
883#define ADC_FLAGS_THCMP6_MASK (0x40U)
884#define ADC_FLAGS_THCMP6_SHIFT (6U)
885/*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0.
886 */
887#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
888#define ADC_FLAGS_THCMP7_MASK (0x80U)
889#define ADC_FLAGS_THCMP7_SHIFT (7U)
890/*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0.
891 */
892#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
893#define ADC_FLAGS_THCMP8_MASK (0x100U)
894#define ADC_FLAGS_THCMP8_SHIFT (8U)
895/*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0.
896 */
897#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
898#define ADC_FLAGS_THCMP9_MASK (0x200U)
899#define ADC_FLAGS_THCMP9_SHIFT (9U)
900/*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0.
901 */
902#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
903#define ADC_FLAGS_THCMP10_MASK (0x400U)
904#define ADC_FLAGS_THCMP10_SHIFT (10U)
905/*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0.
906 */
907#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
908#define ADC_FLAGS_THCMP11_MASK (0x800U)
909#define ADC_FLAGS_THCMP11_SHIFT (11U)
910/*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0.
911 */
912#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
913#define ADC_FLAGS_OVERRUN0_MASK (0x1000U)
914#define ADC_FLAGS_OVERRUN0_SHIFT (12U)
915/*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0
916 */
917#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
918#define ADC_FLAGS_OVERRUN1_MASK (0x2000U)
919#define ADC_FLAGS_OVERRUN1_SHIFT (13U)
920/*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1
921 */
922#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
923#define ADC_FLAGS_OVERRUN2_MASK (0x4000U)
924#define ADC_FLAGS_OVERRUN2_SHIFT (14U)
925/*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2
926 */
927#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
928#define ADC_FLAGS_OVERRUN3_MASK (0x8000U)
929#define ADC_FLAGS_OVERRUN3_SHIFT (15U)
930/*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3
931 */
932#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
933#define ADC_FLAGS_OVERRUN4_MASK (0x10000U)
934#define ADC_FLAGS_OVERRUN4_SHIFT (16U)
935/*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4
936 */
937#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
938#define ADC_FLAGS_OVERRUN5_MASK (0x20000U)
939#define ADC_FLAGS_OVERRUN5_SHIFT (17U)
940/*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5
941 */
942#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
943#define ADC_FLAGS_OVERRUN6_MASK (0x40000U)
944#define ADC_FLAGS_OVERRUN6_SHIFT (18U)
945/*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6
946 */
947#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
948#define ADC_FLAGS_OVERRUN7_MASK (0x80000U)
949#define ADC_FLAGS_OVERRUN7_SHIFT (19U)
950/*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7
951 */
952#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
953#define ADC_FLAGS_OVERRUN8_MASK (0x100000U)
954#define ADC_FLAGS_OVERRUN8_SHIFT (20U)
955/*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8
956 */
957#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
958#define ADC_FLAGS_OVERRUN9_MASK (0x200000U)
959#define ADC_FLAGS_OVERRUN9_SHIFT (21U)
960/*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9
961 */
962#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
963#define ADC_FLAGS_OVERRUN10_MASK (0x400000U)
964#define ADC_FLAGS_OVERRUN10_SHIFT (22U)
965/*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10
966 */
967#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
968#define ADC_FLAGS_OVERRUN11_MASK (0x800000U)
969#define ADC_FLAGS_OVERRUN11_SHIFT (23U)
970/*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11
971 */
972#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
973#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U)
974#define ADC_FLAGS_SEQA_OVR_SHIFT (24U)
975/*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register
976 */
977#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
978#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U)
979#define ADC_FLAGS_SEQB_OVR_SHIFT (25U)
980/*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register
981 */
982#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
983#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U)
984#define ADC_FLAGS_SEQA_INT_SHIFT (28U)
985/*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0,
986 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which
987 * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared
988 * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register
989 * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be
990 * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN
991 * register.
992 */
993#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
994#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U)
995#define ADC_FLAGS_SEQB_INT_SHIFT (29U)
996/*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0,
997 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which
998 * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared
999 * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register
1000 * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be
1001 * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN
1002 * register.
1003 */
1004#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
1005#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U)
1006#define ADC_FLAGS_THCMP_INT_SHIFT (30U)
1007/*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in
1008 * the lower bits of this register are set to 1 (due to an enabled out-of-range or
1009 * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be
1010 * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared
1011 * when all of the individual threshold flags are cleared via writing 1s to those bits.
1012 */
1013#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
1014#define ADC_FLAGS_OVR_INT_MASK (0x80000000U)
1015#define ADC_FLAGS_OVR_INT_SHIFT (31U)
1016/*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data
1017 * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers
1018 * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this
1019 * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all
1020 * of the individual overrun bits have been cleared via reading the corresponding data registers.
1021 */
1022#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
1023/*! @} */
1024
1025
1026/*!
1027 * @}
1028 */ /* end of group ADC_Register_Masks */
1029
1030
1031/* ADC - Peripheral instance base addresses */
1032/** Peripheral ADC0 base address */
1033#define ADC0_BASE (0x4001C000u)
1034/** Peripheral ADC0 base pointer */
1035#define ADC0 ((ADC_Type *)ADC0_BASE)
1036/** Array initializer of ADC peripheral base addresses */
1037#define ADC_BASE_ADDRS { ADC0_BASE }
1038/** Array initializer of ADC peripheral base pointers */
1039#define ADC_BASE_PTRS { ADC0 }
1040/** Interrupt vectors for the ADC peripheral type */
1041#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
1042#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn }
1043
1044/*!
1045 * @}
1046 */ /* end of group ADC_Peripheral_Access_Layer */
1047
1048
1049/* ----------------------------------------------------------------------------
1050 -- CRC Peripheral Access Layer
1051 ---------------------------------------------------------------------------- */
1052
1053/*!
1054 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
1055 * @{
1056 */
1057
1058/** CRC - Register Layout Typedef */
1059typedef struct {
1060 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
1061 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
1062 union { /* offset: 0x8 */
1063 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
1064 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
1065 };
1066} CRC_Type;
1067
1068/* ----------------------------------------------------------------------------
1069 -- CRC Register Masks
1070 ---------------------------------------------------------------------------- */
1071
1072/*!
1073 * @addtogroup CRC_Register_Masks CRC Register Masks
1074 * @{
1075 */
1076
1077/*! @name MODE - CRC mode register */
1078/*! @{ */
1079#define CRC_MODE_CRC_POLY_MASK (0x3U)
1080#define CRC_MODE_CRC_POLY_SHIFT (0U)
1081/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
1082 */
1083#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
1084#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
1085#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
1086/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
1087 */
1088#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
1089#define CRC_MODE_CMPL_WR_MASK (0x8U)
1090#define CRC_MODE_CMPL_WR_SHIFT (3U)
1091/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
1092 */
1093#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
1094#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
1095#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
1096/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
1097 */
1098#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
1099#define CRC_MODE_CMPL_SUM_MASK (0x20U)
1100#define CRC_MODE_CMPL_SUM_SHIFT (5U)
1101/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
1102 */
1103#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
1104/*! @} */
1105
1106/*! @name SEED - CRC seed register */
1107/*! @{ */
1108#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
1109#define CRC_SEED_CRC_SEED_SHIFT (0U)
1110/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
1111 * selected bit order and 1's complement pre-processes. A write access to this register will
1112 * overrule the CRC calculation in progresses.
1113 */
1114#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
1115/*! @} */
1116
1117/*! @name SUM - CRC checksum register */
1118/*! @{ */
1119#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
1120#define CRC_SUM_CRC_SUM_SHIFT (0U)
1121/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
1122 */
1123#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
1124/*! @} */
1125
1126/*! @name WR_DATA - CRC data register */
1127/*! @{ */
1128#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
1129#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
1130/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
1131 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
1132 * accept back-to-back transactions.
1133 */
1134#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
1135/*! @} */
1136
1137
1138/*!
1139 * @}
1140 */ /* end of group CRC_Register_Masks */
1141
1142
1143/* CRC - Peripheral instance base addresses */
1144/** Peripheral CRC base address */
1145#define CRC_BASE (0x50000000u)
1146/** Peripheral CRC base pointer */
1147#define CRC ((CRC_Type *)CRC_BASE)
1148/** Array initializer of CRC peripheral base addresses */
1149#define CRC_BASE_ADDRS { CRC_BASE }
1150/** Array initializer of CRC peripheral base pointers */
1151#define CRC_BASE_PTRS { CRC }
1152
1153/*!
1154 * @}
1155 */ /* end of group CRC_Peripheral_Access_Layer */
1156
1157
1158/* ----------------------------------------------------------------------------
1159 -- CTIMER Peripheral Access Layer
1160 ---------------------------------------------------------------------------- */
1161
1162/*!
1163 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
1164 * @{
1165 */
1166
1167/** CTIMER - Register Layout Typedef */
1168typedef struct {
1169 __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
1170 __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
1171 __IO uint32_t TC; /**< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR., offset: 0x8 */
1172 __IO uint32_t PR; /**< Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC., offset: 0xC */
1173 __IO uint32_t PC; /**< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface., offset: 0x10 */
1174 __IO uint32_t MCR; /**< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs., offset: 0x14 */
1175 __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
1176 __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
1177 __I uint32_t CR[3]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
1178 uint8_t RESERVED_0[4];
1179 __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
1180 uint8_t RESERVED_1[48];
1181 __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
1182 __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
1183 __IO uint32_t MSR[4]; /**< Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero., array offset: 0x78, array step: 0x4 */
1184} CTIMER_Type;
1185
1186/* ----------------------------------------------------------------------------
1187 -- CTIMER Register Masks
1188 ---------------------------------------------------------------------------- */
1189
1190/*!
1191 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
1192 * @{
1193 */
1194
1195/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
1196/*! @{ */
1197#define CTIMER_IR_MR0INT_MASK (0x1U)
1198#define CTIMER_IR_MR0INT_SHIFT (0U)
1199/*! MR0INT - Interrupt flag for match channel 0.
1200 */
1201#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
1202#define CTIMER_IR_MR1INT_MASK (0x2U)
1203#define CTIMER_IR_MR1INT_SHIFT (1U)
1204/*! MR1INT - Interrupt flag for match channel 1.
1205 */
1206#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
1207#define CTIMER_IR_MR2INT_MASK (0x4U)
1208#define CTIMER_IR_MR2INT_SHIFT (2U)
1209/*! MR2INT - Interrupt flag for match channel 2.
1210 */
1211#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
1212#define CTIMER_IR_MR3INT_MASK (0x8U)
1213#define CTIMER_IR_MR3INT_SHIFT (3U)
1214/*! MR3INT - Interrupt flag for match channel 3.
1215 */
1216#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
1217#define CTIMER_IR_CR0INT_MASK (0x10U)
1218#define CTIMER_IR_CR0INT_SHIFT (4U)
1219/*! CR0INT - Interrupt flag for capture channel 0 event.
1220 */
1221#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
1222#define CTIMER_IR_CR1INT_MASK (0x20U)
1223#define CTIMER_IR_CR1INT_SHIFT (5U)
1224/*! CR1INT - Interrupt flag for capture channel 1 event.
1225 */
1226#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
1227#define CTIMER_IR_CR2INT_MASK (0x40U)
1228#define CTIMER_IR_CR2INT_SHIFT (6U)
1229/*! CR2INT - Interrupt flag for capture channel 2 event.
1230 */
1231#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
1232/*! @} */
1233
1234/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
1235/*! @{ */
1236#define CTIMER_TCR_CEN_MASK (0x1U)
1237#define CTIMER_TCR_CEN_SHIFT (0U)
1238/*! CEN - Counter enable.
1239 * 0b0..Disabled.The counters are disabled.
1240 * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
1241 */
1242#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
1243#define CTIMER_TCR_CRST_MASK (0x2U)
1244#define CTIMER_TCR_CRST_SHIFT (1U)
1245/*! CRST - Counter reset.
1246 * 0b0..Disabled. Do nothing.
1247 * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
1248 * the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
1249 */
1250#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
1251/*! @} */
1252
1253/*! @name TC - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. */
1254/*! @{ */
1255#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
1256#define CTIMER_TC_TCVAL_SHIFT (0U)
1257/*! TCVAL - Timer counter value.
1258 */
1259#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
1260/*! @} */
1261
1262/*! @name PR - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. */
1263/*! @{ */
1264#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
1265#define CTIMER_PR_PRVAL_SHIFT (0U)
1266/*! PRVAL - Prescale counter value.
1267 */
1268#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
1269/*! @} */
1270
1271/*! @name PC - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
1272/*! @{ */
1273#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
1274#define CTIMER_PC_PCVAL_SHIFT (0U)
1275/*! PCVAL - Prescale counter value.
1276 */
1277#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
1278/*! @} */
1279
1280/*! @name MCR - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
1281/*! @{ */
1282#define CTIMER_MCR_MR0I_MASK (0x1U)
1283#define CTIMER_MCR_MR0I_SHIFT (0U)
1284/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled.
1285 */
1286#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
1287#define CTIMER_MCR_MR0R_MASK (0x2U)
1288#define CTIMER_MCR_MR0R_SHIFT (1U)
1289/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled.
1290 */
1291#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
1292#define CTIMER_MCR_MR0S_MASK (0x4U)
1293#define CTIMER_MCR_MR0S_SHIFT (2U)
1294/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled.
1295 */
1296#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
1297#define CTIMER_MCR_MR1I_MASK (0x8U)
1298#define CTIMER_MCR_MR1I_SHIFT (3U)
1299/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 =
1300 * disabled. 1 = enabled. 0 = disabled. 1 = enabled.
1301 */
1302#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
1303#define CTIMER_MCR_MR1R_MASK (0x10U)
1304#define CTIMER_MCR_MR1R_SHIFT (4U)
1305/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled.
1306 */
1307#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
1308#define CTIMER_MCR_MR1S_MASK (0x20U)
1309#define CTIMER_MCR_MR1S_SHIFT (5U)
1310/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled.
1311 */
1312#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
1313#define CTIMER_MCR_MR2I_MASK (0x40U)
1314#define CTIMER_MCR_MR2I_SHIFT (6U)
1315/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled.
1316 */
1317#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
1318#define CTIMER_MCR_MR2R_MASK (0x80U)
1319#define CTIMER_MCR_MR2R_SHIFT (7U)
1320/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled.
1321 */
1322#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
1323#define CTIMER_MCR_MR2S_MASK (0x100U)
1324#define CTIMER_MCR_MR2S_SHIFT (8U)
1325/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled.
1326 */
1327#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
1328#define CTIMER_MCR_MR3I_MASK (0x200U)
1329#define CTIMER_MCR_MR3I_SHIFT (9U)
1330/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled.
1331 */
1332#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
1333#define CTIMER_MCR_MR3R_MASK (0x400U)
1334#define CTIMER_MCR_MR3R_SHIFT (10U)
1335/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled.
1336 */
1337#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
1338#define CTIMER_MCR_MR3S_MASK (0x800U)
1339#define CTIMER_MCR_MR3S_SHIFT (11U)
1340/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled.
1341 */
1342#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
1343#define CTIMER_MCR_MR0RL_MASK (0x1000000U)
1344#define CTIMER_MCR_MR0RL_SHIFT (24U)
1345/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
1346 * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.
1347 */
1348#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
1349#define CTIMER_MCR_MR1RL_MASK (0x2000000U)
1350#define CTIMER_MCR_MR1RL_SHIFT (25U)
1351/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
1352 * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.
1353 */
1354#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
1355#define CTIMER_MCR_MR2RL_MASK (0x4000000U)
1356#define CTIMER_MCR_MR2RL_SHIFT (26U)
1357/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
1358 * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.
1359 */
1360#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
1361#define CTIMER_MCR_MR3RL_MASK (0x8000000U)
1362#define CTIMER_MCR_MR3RL_SHIFT (27U)
1363/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
1364 * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.
1365 */
1366#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
1367/*! @} */
1368
1369/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
1370/*! @{ */
1371#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
1372#define CTIMER_MR_MATCH_SHIFT (0U)
1373/*! MATCH - Timer counter match value.
1374 */
1375#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
1376/*! @} */
1377
1378/* The count of CTIMER_MR */
1379#define CTIMER_MR_COUNT (4U)
1380
1381/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
1382/*! @{ */
1383#define CTIMER_CCR_CAP0RE_MASK (0x1U)
1384#define CTIMER_CCR_CAP0RE_SHIFT (0U)
1385/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
1386 * the contents of TC. 0 = disabled. 1 = enabled.
1387 */
1388#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
1389#define CTIMER_CCR_CAP0FE_MASK (0x2U)
1390#define CTIMER_CCR_CAP0FE_SHIFT (1U)
1391/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
1392 * the contents of TC. 0 = disabled. 1 = enabled.
1393 */
1394#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
1395#define CTIMER_CCR_CAP0I_MASK (0x4U)
1396#define CTIMER_CCR_CAP0I_SHIFT (2U)
1397/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
1398 */
1399#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
1400#define CTIMER_CCR_CAP1RE_MASK (0x8U)
1401#define CTIMER_CCR_CAP1RE_SHIFT (3U)
1402/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
1403 * the contents of TC. 0 = disabled. 1 = enabled.
1404 */
1405#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
1406#define CTIMER_CCR_CAP1FE_MASK (0x10U)
1407#define CTIMER_CCR_CAP1FE_SHIFT (4U)
1408/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
1409 * the contents of TC. 0 = disabled. 1 = enabled.
1410 */
1411#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
1412#define CTIMER_CCR_CAP1I_MASK (0x20U)
1413#define CTIMER_CCR_CAP1I_SHIFT (5U)
1414/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
1415 */
1416#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
1417#define CTIMER_CCR_CAP2RE_MASK (0x40U)
1418#define CTIMER_CCR_CAP2RE_SHIFT (6U)
1419/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
1420 * the contents of TC. 0 = disabled. 1 = enabled.
1421 */
1422#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
1423#define CTIMER_CCR_CAP2FE_MASK (0x80U)
1424#define CTIMER_CCR_CAP2FE_SHIFT (7U)
1425/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
1426 * the contents of TC. 0 = disabled. 1 = enabled.
1427 */
1428#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
1429#define CTIMER_CCR_CAP2I_MASK (0x100U)
1430#define CTIMER_CCR_CAP2I_SHIFT (8U)
1431/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
1432 */
1433#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
1434/*! @} */
1435
1436/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
1437/*! @{ */
1438#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
1439#define CTIMER_CR_CAP_SHIFT (0U)
1440/*! CAP - Timer counter capture value.
1441 */
1442#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
1443/*! @} */
1444
1445/* The count of CTIMER_CR */
1446#define CTIMER_CR_COUNT (3U)
1447
1448/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
1449/*! @{ */
1450#define CTIMER_EMR_EM0_MASK (0x1U)
1451#define CTIMER_EMR_EM0_SHIFT (0U)
1452/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
1453 * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
1454 * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
1455 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1456 */
1457#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
1458#define CTIMER_EMR_EM1_MASK (0x2U)
1459#define CTIMER_EMR_EM1_SHIFT (1U)
1460/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
1461 * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
1462 * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
1463 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1464 */
1465#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
1466#define CTIMER_EMR_EM2_MASK (0x4U)
1467#define CTIMER_EMR_EM2_SHIFT (2U)
1468/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
1469 * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
1470 * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
1471 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1472 */
1473#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
1474#define CTIMER_EMR_EM3_MASK (0x8U)
1475#define CTIMER_EMR_EM3_SHIFT (3U)
1476/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
1477 * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
1478 * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
1479 * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1480 */
1481#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
1482#define CTIMER_EMR_EMC0_MASK (0x30U)
1483#define CTIMER_EMR_EMC0_SHIFT (4U)
1484/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
1485 * 0b00..Do Nothing.
1486 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
1487 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
1488 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
1489 */
1490#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
1491#define CTIMER_EMR_EMC1_MASK (0xC0U)
1492#define CTIMER_EMR_EMC1_SHIFT (6U)
1493/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
1494 * 0b00..Do Nothing.
1495 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
1496 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
1497 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
1498 */
1499#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
1500#define CTIMER_EMR_EMC2_MASK (0x300U)
1501#define CTIMER_EMR_EMC2_SHIFT (8U)
1502/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
1503 * 0b00..Do Nothing.
1504 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
1505 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
1506 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
1507 */
1508#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
1509#define CTIMER_EMR_EMC3_MASK (0xC00U)
1510#define CTIMER_EMR_EMC3_SHIFT (10U)
1511/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
1512 * 0b00..Do Nothing.
1513 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
1514 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
1515 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
1516 */
1517#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
1518/*! @} */
1519
1520/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
1521/*! @{ */
1522#define CTIMER_CTCR_CTMODE_MASK (0x3U)
1523#define CTIMER_CTCR_CTMODE_SHIFT (0U)
1524/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
1525 * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
1526 * is incremented when the Prescale Counter matches the Prescale Register.
1527 * 0b00..Timer Mode. Incremented every rising APB bus clock edge.
1528 * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
1529 * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
1530 * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
1531 */
1532#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
1533#define CTIMER_CTCR_CINSEL_MASK (0xCU)
1534#define CTIMER_CTCR_CINSEL_SHIFT (2U)
1535/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
1536 * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
1537 * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
1538 * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
1539 * same timer.
1540 * 0b00..Channel 0. CAPn.0 for CTIMERn
1541 * 0b01..Channel 1. CAPn.1 for CTIMERn
1542 * 0b10..Channel 2. CAPn.2 for CTIMERn
1543 * 0b11..Channel 3. CAPn.3 for CTIMERn
1544 */
1545#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
1546#define CTIMER_CTCR_ENCC_MASK (0x10U)
1547#define CTIMER_CTCR_ENCC_SHIFT (4U)
1548/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
1549 * capture-edge event specified in bits 7:5 occurs.
1550 */
1551#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
1552#define CTIMER_CTCR_SELCC_MASK (0xE0U)
1553#define CTIMER_CTCR_SELCC_SHIFT (5U)
1554/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
1555 * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
1556 * 0x3 and 0x6 to 0x7 are reserved.
1557 * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
1558 * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
1559 * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
1560 * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
1561 * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
1562 * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
1563 */
1564#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
1565/*! @} */
1566
1567/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
1568/*! @{ */
1569#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
1570#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
1571/*! PWMEN0 - PWM mode enable for channel0.
1572 * 0b0..Match. CTIMERn_MAT0 is controlled by EM0.
1573 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
1574 */
1575#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
1576#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
1577#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
1578/*! PWMEN1 - PWM mode enable for channel1.
1579 * 0b0..Match. CTIMERn_MAT01 is controlled by EM1.
1580 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
1581 */
1582#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
1583#define CTIMER_PWMC_PWMEN2_MASK (0x4U)
1584#define CTIMER_PWMC_PWMEN2_SHIFT (2U)
1585/*! PWMEN2 - PWM mode enable for channel2.
1586 * 0b0..Match. CTIMERn_MAT2 is controlled by EM2.
1587 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
1588 */
1589#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
1590#define CTIMER_PWMC_PWMEN3_MASK (0x8U)
1591#define CTIMER_PWMC_PWMEN3_SHIFT (3U)
1592/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
1593 * 0b0..Match. CTIMERn_MAT3 is controlled by EM3.
1594 * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
1595 */
1596#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
1597/*! @} */
1598
1599/*! @name MSR - Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero. */
1600/*! @{ */
1601#define CTIMER_MSR_MATCH_SHADOW_MASK (0xFFFFFFFFU)
1602#define CTIMER_MSR_MATCH_SHADOW_SHIFT (0U)
1603/*! MATCH_SHADOW - Timer counter match value.
1604 */
1605#define CTIMER_MSR_MATCH_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK)
1606/*! @} */
1607
1608/* The count of CTIMER_MSR */
1609#define CTIMER_MSR_COUNT (4U)
1610
1611
1612/*!
1613 * @}
1614 */ /* end of group CTIMER_Register_Masks */
1615
1616
1617/* CTIMER - Peripheral instance base addresses */
1618/** Peripheral CTIMER0 base address */
1619#define CTIMER0_BASE (0x40038000u)
1620/** Peripheral CTIMER0 base pointer */
1621#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
1622/** Array initializer of CTIMER peripheral base addresses */
1623#define CTIMER_BASE_ADDRS { CTIMER0_BASE }
1624/** Array initializer of CTIMER peripheral base pointers */
1625#define CTIMER_BASE_PTRS { CTIMER0 }
1626/** Interrupt vectors for the CTIMER peripheral type */
1627#define CTIMER_IRQS { CTIMER0_IRQn }
1628
1629/*!
1630 * @}
1631 */ /* end of group CTIMER_Peripheral_Access_Layer */
1632
1633
1634/* ----------------------------------------------------------------------------
1635 -- GPIO Peripheral Access Layer
1636 ---------------------------------------------------------------------------- */
1637
1638/*!
1639 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
1640 * @{
1641 */
1642
1643/** GPIO - Register Layout Typedef */
1644typedef struct {
1645 __IO uint8_t B[2][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
1646 uint8_t RESERVED_0[4032];
1647 __IO uint32_t W[2][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
1648 uint8_t RESERVED_1[3840];
1649 __IO uint32_t DIR[1]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */
1650 uint8_t RESERVED_2[124];
1651 __IO uint32_t MASK[1]; /**< Mask register, array offset: 0x2080, array step: 0x4 */
1652 uint8_t RESERVED_3[124];
1653 __IO uint32_t PIN[1]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */
1654 uint8_t RESERVED_4[124];
1655 __IO uint32_t MPIN[1]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */
1656 uint8_t RESERVED_5[124];
1657 __IO uint32_t SET[1]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
1658 uint8_t RESERVED_6[124];
1659 __O uint32_t CLR[1]; /**< Clear port, array offset: 0x2280, array step: 0x4 */
1660 uint8_t RESERVED_7[124];
1661 __O uint32_t NOT[1]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */
1662 uint8_t RESERVED_8[124];
1663 __O uint32_t DIRSET[1]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
1664 uint8_t RESERVED_9[124];
1665 __O uint32_t DIRCLR[1]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
1666 uint8_t RESERVED_10[124];
1667 __O uint32_t DIRNOT[1]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
1668} GPIO_Type;
1669
1670/* ----------------------------------------------------------------------------
1671 -- GPIO Register Masks
1672 ---------------------------------------------------------------------------- */
1673
1674/*!
1675 * @addtogroup GPIO_Register_Masks GPIO Register Masks
1676 * @{
1677 */
1678
1679/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
1680/*! @{ */
1681#define GPIO_B_PBYTE_MASK (0x1U)
1682#define GPIO_B_PBYTE_SHIFT (0U)
1683/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function,
1684 * except that pins configured as analog I/O always read as 0. One register for each port pin.
1685 * Supported pins depends on the specific device and package. Write: loads the pin's output bit.
1686 * One register for each port pin. Supported pins depends on the specific device and package.
1687 */
1688#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
1689/*! @} */
1690
1691/* The count of GPIO_B */
1692#define GPIO_B_COUNT (2U)
1693
1694/* The count of GPIO_B */
1695#define GPIO_B_COUNT2 (32U)
1696
1697/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
1698/*! @{ */
1699#define GPIO_W_PWORD_MASK (0x3FFFFU)
1700#define GPIO_W_PWORD_SHIFT (0U)
1701/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is
1702 * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be
1703 * read. Writing any value other than 0 will set the output bit. One register for each port pin.
1704 * Supported pins depends on the specific device and package.
1705 */
1706#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
1707/*! @} */
1708
1709/* The count of GPIO_W */
1710#define GPIO_W_COUNT (2U)
1711
1712/* The count of GPIO_W */
1713#define GPIO_W_COUNT2 (32U)
1714
1715/*! @name DIR - Direction registers */
1716/*! @{ */
1717#define GPIO_DIR_DIRP_MASK (0x3FFFFU)
1718#define GPIO_DIR_DIRP_SHIFT (0U)
1719/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
1720 * pins depends on the specific device and package. 0 = input. 1 = output.
1721 */
1722#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
1723/*! @} */
1724
1725/* The count of GPIO_DIR */
1726#define GPIO_DIR_COUNT (1U)
1727
1728/*! @name MASK - Mask register */
1729/*! @{ */
1730#define GPIO_MASK_MASKP_MASK (0x3FFFFU)
1731#define GPIO_MASK_MASKP_SHIFT (0U)
1732/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 =
1733 * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 =
1734 * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit
1735 * not affected.
1736 */
1737#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
1738/*! @} */
1739
1740/* The count of GPIO_MASK */
1741#define GPIO_MASK_COUNT (1U)
1742
1743/*! @name PIN - Port pin register */
1744/*! @{ */
1745#define GPIO_PIN_PORT_MASK (0x3FFFFU)
1746#define GPIO_PIN_PORT_SHIFT (0U)
1747/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
1748 * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit.
1749 * 1 = Read: pin is high; write: set output bit.
1750 */
1751#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
1752/*! @} */
1753
1754/* The count of GPIO_PIN */
1755#define GPIO_PIN_COUNT (1U)
1756
1757/*! @name MPIN - Masked port register */
1758/*! @{ */
1759#define GPIO_MPIN_MPORTP_MASK (0x3FFFFU)
1760#define GPIO_MPIN_MPORTP_SHIFT (0U)
1761/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
1762 * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK
1763 * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1
1764 * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit
1765 * if the corresponding bit in the MASK register is 0.
1766 */
1767#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
1768/*! @} */
1769
1770/* The count of GPIO_MPIN */
1771#define GPIO_MPIN_COUNT (1U)
1772
1773/*! @name SET - Write: Set register for port Read: output bits for port */
1774/*! @{ */
1775#define GPIO_SET_SETP_MASK (0x3FFFFU)
1776#define GPIO_SET_SETP_SHIFT (0U)
1777/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
1778 * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output
1779 * bit; write: set output bit.
1780 */
1781#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
1782/*! @} */
1783
1784/* The count of GPIO_SET */
1785#define GPIO_SET_COUNT (1U)
1786
1787/*! @name CLR - Clear port */
1788/*! @{ */
1789#define GPIO_CLR_CLRP_MASK (0x3FFFFU)
1790#define GPIO_CLR_CLRP_SHIFT (0U)
1791/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
1792 * specific device and package. 0 = No operation. 1 = Clear output bit.
1793 */
1794#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
1795/*! @} */
1796
1797/* The count of GPIO_CLR */
1798#define GPIO_CLR_COUNT (1U)
1799
1800/*! @name NOT - Toggle port */
1801/*! @{ */
1802#define GPIO_NOT_NOTP_MASK (0x3FFFFU)
1803#define GPIO_NOT_NOTP_SHIFT (0U)
1804/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
1805 * specific device and package. 0 = no operation. 1 = Toggle output bit.
1806 */
1807#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
1808/*! @} */
1809
1810/* The count of GPIO_NOT */
1811#define GPIO_NOT_COUNT (1U)
1812
1813/*! @name DIRSET - Set pin direction bits for port */
1814/*! @{ */
1815#define GPIO_DIRSET_DIRSETP_MASK (0x3FFFFU)
1816#define GPIO_DIRSET_DIRSETP_SHIFT (0U)
1817/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
1818 * the specific device and package. 0 = No operation. 1 = Set direction bit.
1819 */
1820#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
1821/*! @} */
1822
1823/* The count of GPIO_DIRSET */
1824#define GPIO_DIRSET_COUNT (1U)
1825
1826/*! @name DIRCLR - Clear pin direction bits for port */
1827/*! @{ */
1828#define GPIO_DIRCLR_DIRCLRP_MASK (0x3FFFFU)
1829#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U)
1830/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
1831 * the specific device and package. 0 = No operation. 1 = Clear direction bit.
1832 */
1833#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
1834/*! @} */
1835
1836/* The count of GPIO_DIRCLR */
1837#define GPIO_DIRCLR_COUNT (1U)
1838
1839/*! @name DIRNOT - Toggle pin direction bits for port */
1840/*! @{ */
1841#define GPIO_DIRNOT_DIRNOTP_MASK (0x3FFFFU)
1842#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U)
1843/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends
1844 * on the specific device and package. 0 = no operation. 1 = Toggle direction bit.
1845 */
1846#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
1847/*! @} */
1848
1849/* The count of GPIO_DIRNOT */
1850#define GPIO_DIRNOT_COUNT (1U)
1851
1852
1853/*!
1854 * @}
1855 */ /* end of group GPIO_Register_Masks */
1856
1857
1858/* GPIO - Peripheral instance base addresses */
1859/** Peripheral GPIO base address */
1860#define GPIO_BASE (0xA0000000u)
1861/** Peripheral GPIO base pointer */
1862#define GPIO ((GPIO_Type *)GPIO_BASE)
1863/** Array initializer of GPIO peripheral base addresses */
1864#define GPIO_BASE_ADDRS { GPIO_BASE }
1865/** Array initializer of GPIO peripheral base pointers */
1866#define GPIO_BASE_PTRS { GPIO }
1867
1868/*!
1869 * @}
1870 */ /* end of group GPIO_Peripheral_Access_Layer */
1871
1872
1873/* ----------------------------------------------------------------------------
1874 -- I2C Peripheral Access Layer
1875 ---------------------------------------------------------------------------- */
1876
1877/*!
1878 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
1879 * @{
1880 */
1881
1882/** I2C - Register Layout Typedef */
1883typedef struct {
1884 __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x0 */
1885 __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x4 */
1886 __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x8 */
1887 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0xC */
1888 __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x10 */
1889 __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x14 */
1890 __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x18 */
1891 uint8_t RESERVED_0[4];
1892 __IO uint32_t MSTCTL; /**< Master control register., offset: 0x20 */
1893 __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x24 */
1894 __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x28 */
1895 uint8_t RESERVED_1[20];
1896 __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x40 */
1897 __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x44 */
1898 __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x48, array step: 0x4 */
1899 __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x58 */
1900 uint8_t RESERVED_2[36];
1901 __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x80 */
1902} I2C_Type;
1903
1904/* ----------------------------------------------------------------------------
1905 -- I2C Register Masks
1906 ---------------------------------------------------------------------------- */
1907
1908/*!
1909 * @addtogroup I2C_Register_Masks I2C Register Masks
1910 * @{
1911 */
1912
1913/*! @name CFG - Configuration for shared functions. */
1914/*! @{ */
1915#define I2C_CFG_MSTEN_MASK (0x1U)
1916#define I2C_CFG_MSTEN_SHIFT (0U)
1917/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not
1918 * changed, but the Master function is internally reset.
1919 * 0b0..Disabled. The I2C Master function is disabled.
1920 * 0b1..Enabled. The I2C Master function is enabled.
1921 */
1922#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
1923#define I2C_CFG_SLVEN_MASK (0x2U)
1924#define I2C_CFG_SLVEN_SHIFT (1U)
1925/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not
1926 * changed, but the Slave function is internally reset.
1927 * 0b0..Disabled. The I2C slave function is disabled.
1928 * 0b1..Enabled. The I2C slave function is enabled.
1929 */
1930#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
1931#define I2C_CFG_MONEN_MASK (0x4U)
1932#define I2C_CFG_MONEN_SHIFT (2U)
1933/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not
1934 * changed, but the Monitor function is internally reset.
1935 * 0b0..Disabled. The I2C Monitor function is disabled.
1936 * 0b1..Enabled. The I2C Monitor function is enabled.
1937 */
1938#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
1939#define I2C_CFG_TIMEOUTEN_MASK (0x8U)
1940#define I2C_CFG_TIMEOUTEN_SHIFT (3U)
1941/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
1942 * 0b0..Disabled. Time-out function is disabled.
1943 * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause
1944 * interrupts if they are enabled. Typically, only one time-out will be used in a system.
1945 */
1946#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
1947#define I2C_CFG_MONCLKSTR_MASK (0x10U)
1948#define I2C_CFG_MONCLKSTR_SHIFT (4U)
1949/*! MONCLKSTR - Monitor function Clock Stretching.
1950 * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able
1951 * to read data provided by the Monitor function before it is overwritten. This mode may be used when
1952 * non-invasive monitoring is critical.
1953 * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can
1954 * read all incoming data supplied by the Monitor function.
1955 */
1956#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
1957/*! @} */
1958
1959/*! @name STAT - Status register for Master, Slave, and Monitor functions. */
1960/*! @{ */
1961#define I2C_STAT_MSTPENDING_MASK (0x1U)
1962#define I2C_STAT_MSTPENDING_SHIFT (0U)
1963/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on
1964 * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what
1965 * type of software service if any the master expects. This flag will cause an interrupt when set
1966 * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling
1967 * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle
1968 * state, and no communication is needed, mask this interrupt.
1969 * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
1970 * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the
1971 * idle state, it is waiting to receive or transmit data or the NACK bit.
1972 */
1973#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
1974#define I2C_STAT_MSTSTATE_MASK (0xEU)
1975#define I2C_STAT_MSTSTATE_SHIFT (1U)
1976/*! MSTSTATE - Master State code. The master state code reflects the master state when the
1977 * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field
1978 * indicates a specific required service for the Master function. All other values are reserved. See
1979 * Table 400 for details of state values and appropriate responses.
1980 * 0b000..Idle. The Master function is available to be used for a new transaction.
1981 * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
1982 * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
1983 * 0b011..NACK Address. Slave NACKed address.
1984 * 0b100..NACK Data. Slave NACKed transmitted data.
1985 */
1986#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
1987#define I2C_STAT_MSTARBLOSS_MASK (0x10U)
1988#define I2C_STAT_MSTARBLOSS_SHIFT (4U)
1989/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to
1990 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
1991 * 0b0..No Arbitration Loss has occurred.
1992 * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master
1993 * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing,
1994 * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
1995 */
1996#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
1997#define I2C_STAT_MSTSTSTPERR_MASK (0x40U)
1998#define I2C_STAT_MSTSTSTPERR_SHIFT (6U)
1999/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to
2000 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
2001 * 0b0..No Start/Stop Error has occurred.
2002 * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is
2003 * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an
2004 * idle state, no action is required. A request for a Start could be made, or software could attempt to insure
2005 * that the bus has not stalled.
2006 */
2007#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
2008#define I2C_STAT_SLVPENDING_MASK (0x100U)
2009#define I2C_STAT_SLVPENDING_SHIFT (8U)
2010/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue
2011 * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if
2012 * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the
2013 * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is
2014 * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time
2015 * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section
2016 * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are
2017 * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must
2018 * also be detected automatically, since the address must be acknowledged before the clock can be
2019 * stretched.
2020 * 0b0..In progress. The Slave function does not currently need service.
2021 * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
2022 */
2023#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
2024#define I2C_STAT_SLVSTATE_MASK (0x600U)
2025#define I2C_STAT_SLVSTATE_SHIFT (9U)
2026/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for
2027 * the Slave function. All other values are reserved. See Table 401 for state values and actions.
2028 * note that the occurrence of some states and how they are handled are affected by DMA mode and
2029 * Automatic Operation modes.
2030 * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
2031 * 0b01..Slave receive. Received data is available (Slave Receiver mode).
2032 * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode).
2033 */
2034#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
2035#define I2C_STAT_SLVNOTSTR_MASK (0x800U)
2036#define I2C_STAT_SLVNOTSTR_SHIFT (11U)
2037/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock.
2038 * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave
2039 * operation. This read-only flag reflects the slave function status in real time.
2040 * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
2041 * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or
2042 * Power-down mode could be entered at this time.
2043 */
2044#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
2045#define I2C_STAT_SLVIDX_MASK (0x3000U)
2046#define I2C_STAT_SLVIDX_SHIFT (12U)
2047/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been
2048 * selected by receiving an address that matches one of the slave addresses defined by any enabled
2049 * slave address registers, and provides an identification of the address that was matched. It is
2050 * possible that more than one address could be matched, but only one match can be reported here.
2051 * 0b00..Address 0. Slave address 0 was matched.
2052 * 0b01..Address 1. Slave address 1 was matched.
2053 * 0b10..Address 2. Slave address 2 was matched.
2054 * 0b11..Address 3. Slave address 3 was matched.
2055 */
2056#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
2057#define I2C_STAT_SLVSEL_MASK (0x4000U)
2058#define I2C_STAT_SLVSEL_SHIFT (14U)
2059/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave
2060 * function to acknowledge the address, or when the address has been automatically acknowledged.
2061 * It is cleared when another address cycle presents an address that does not match an enabled
2062 * address on the Slave function, when slave software decides to NACK a matched address, when
2063 * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of
2064 * Automatic Operation. SLVSEL is not cleared if software NACKs data.
2065 * 0b0..Not selected. The Slave function is not currently selected.
2066 * 0b1..Selected. The Slave function is currently selected.
2067 */
2068#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
2069#define I2C_STAT_SLVDESEL_MASK (0x8000U)
2070#define I2C_STAT_SLVDESEL_SHIFT (15U)
2071/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via
2072 * INTENSET. This flag can be cleared by writing a 1 to this bit.
2073 * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently
2074 * selected. That information can be found in the SLVSEL flag.
2075 * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag
2076 * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
2077 */
2078#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
2079#define I2C_STAT_MONRDY_MASK (0x10000U)
2080#define I2C_STAT_MONRDY_SHIFT (16U)
2081/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read.
2082 * 0b0..No data. The Monitor function does not currently have data available.
2083 * 0b1..Data waiting. The Monitor function has data waiting to be read.
2084 */
2085#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
2086#define I2C_STAT_MONOV_MASK (0x20000U)
2087#define I2C_STAT_MONOV_SHIFT (17U)
2088/*! MONOV - Monitor Overflow flag.
2089 * 0b0..No overrun. Monitor data has not overrun.
2090 * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not
2091 * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
2092 */
2093#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
2094#define I2C_STAT_MONACTIVE_MASK (0x40000U)
2095#define I2C_STAT_MONACTIVE_SHIFT (18U)
2096/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to
2097 * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred
2098 * more recently than a bus Stop.
2099 * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive.
2100 * 0b1..Active. The Monitor function considers the I2C bus to be active.
2101 */
2102#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
2103#define I2C_STAT_MONIDLE_MASK (0x80000U)
2104#define I2C_STAT_MONIDLE_SHIFT (19U)
2105/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change
2106 * from active to inactive. This can be used by software to decide when to process data
2107 * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the
2108 * INTENSET register. The flag can be cleared by writing a 1 to this bit.
2109 * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software.
2110 * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
2111 */
2112#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
2113#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U)
2114#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U)
2115/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been
2116 * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock
2117 * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus
2118 * is idle.
2119 * 0b0..No time-out. I2C bus events have not caused a time-out.
2120 * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
2121 */
2122#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
2123#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U)
2124#define I2C_STAT_SCLTIMEOUT_SHIFT (25U)
2125/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the
2126 * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
2127 * 0b0..No time-out. SCL low time has not caused a time-out.
2128 * 0b1..Time-out. SCL low time has caused a time-out.
2129 */
2130#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
2131/*! @} */
2132
2133/*! @name INTENSET - Interrupt Enable Set and read register. */
2134/*! @{ */
2135#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U)
2136#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U)
2137/*! MSTPENDINGEN - Master Pending interrupt Enable.
2138 * 0b0..Disabled. The MstPending interrupt is disabled.
2139 * 0b1..Enabled. The MstPending interrupt is enabled.
2140 */
2141#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
2142#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U)
2143#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U)
2144/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable.
2145 * 0b0..Disabled. The MstArbLoss interrupt is disabled.
2146 * 0b1..Enabled. The MstArbLoss interrupt is enabled.
2147 */
2148#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
2149#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U)
2150#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U)
2151/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable.
2152 * 0b0..Disabled. The MstStStpErr interrupt is disabled.
2153 * 0b1..Enabled. The MstStStpErr interrupt is enabled.
2154 */
2155#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
2156#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U)
2157#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U)
2158/*! SLVPENDINGEN - Slave Pending interrupt Enable.
2159 * 0b0..Disabled. The SlvPending interrupt is disabled.
2160 * 0b1..Enabled. The SlvPending interrupt is enabled.
2161 */
2162#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
2163#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U)
2164#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U)
2165/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable.
2166 * 0b0..Disabled. The SlvNotStr interrupt is disabled.
2167 * 0b1..Enabled. The SlvNotStr interrupt is enabled.
2168 */
2169#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
2170#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U)
2171#define I2C_INTENSET_SLVDESELEN_SHIFT (15U)
2172/*! SLVDESELEN - Slave Deselect interrupt Enable.
2173 * 0b0..Disabled. The SlvDeSel interrupt is disabled.
2174 * 0b1..Enabled. The SlvDeSel interrupt is enabled.
2175 */
2176#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
2177#define I2C_INTENSET_MONRDYEN_MASK (0x10000U)
2178#define I2C_INTENSET_MONRDYEN_SHIFT (16U)
2179/*! MONRDYEN - Monitor data Ready interrupt Enable.
2180 * 0b0..Disabled. The MonRdy interrupt is disabled.
2181 * 0b1..Enabled. The MonRdy interrupt is enabled.
2182 */
2183#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
2184#define I2C_INTENSET_MONOVEN_MASK (0x20000U)
2185#define I2C_INTENSET_MONOVEN_SHIFT (17U)
2186/*! MONOVEN - Monitor Overrun interrupt Enable.
2187 * 0b0..Disabled. The MonOv interrupt is disabled.
2188 * 0b1..Enabled. The MonOv interrupt is enabled.
2189 */
2190#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
2191#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U)
2192#define I2C_INTENSET_MONIDLEEN_SHIFT (19U)
2193/*! MONIDLEEN - Monitor Idle interrupt Enable.
2194 * 0b0..Disabled. The MonIdle interrupt is disabled.
2195 * 0b1..Enabled. The MonIdle interrupt is enabled.
2196 */
2197#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
2198#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U)
2199#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U)
2200/*! EVENTTIMEOUTEN - Event time-out interrupt Enable.
2201 * 0b0..Disabled. The Event time-out interrupt is disabled.
2202 * 0b1..Enabled. The Event time-out interrupt is enabled.
2203 */
2204#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
2205#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U)
2206#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U)
2207/*! SCLTIMEOUTEN - SCL time-out interrupt Enable.
2208 * 0b0..Disabled. The SCL time-out interrupt is disabled.
2209 * 0b1..Enabled. The SCL time-out interrupt is enabled.
2210 */
2211#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
2212/*! @} */
2213
2214/*! @name INTENCLR - Interrupt Enable Clear register. */
2215/*! @{ */
2216#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U)
2217#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U)
2218/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding
2219 * bit in the INTENSET register if implemented.
2220 */
2221#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
2222#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U)
2223#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U)
2224/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear.
2225 */
2226#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
2227#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U)
2228#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U)
2229/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear.
2230 */
2231#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
2232#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U)
2233#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U)
2234/*! SLVPENDINGCLR - Slave Pending interrupt clear.
2235 */
2236#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
2237#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U)
2238#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U)
2239/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear.
2240 */
2241#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
2242#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U)
2243#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U)
2244/*! SLVDESELCLR - Slave Deselect interrupt clear.
2245 */
2246#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
2247#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U)
2248#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U)
2249/*! MONRDYCLR - Monitor data Ready interrupt clear.
2250 */
2251#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
2252#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U)
2253#define I2C_INTENCLR_MONOVCLR_SHIFT (17U)
2254/*! MONOVCLR - Monitor Overrun interrupt clear.
2255 */
2256#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
2257#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U)
2258#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U)
2259/*! MONIDLECLR - Monitor Idle interrupt clear.
2260 */
2261#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
2262#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U)
2263#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U)
2264/*! EVENTTIMEOUTCLR - Event time-out interrupt clear.
2265 */
2266#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
2267#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U)
2268#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U)
2269/*! SCLTIMEOUTCLR - SCL time-out interrupt clear.
2270 */
2271#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
2272/*! @} */
2273
2274/*! @name TIMEOUT - Time-out value register. */
2275/*! @{ */
2276#define I2C_TIMEOUT_TOMIN_MASK (0xFU)
2277#define I2C_TIMEOUT_TOMIN_SHIFT (0U)
2278/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum
2279 * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
2280 */
2281#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
2282#define I2C_TIMEOUT_TO_MASK (0xFFF0U)
2283#define I2C_TIMEOUT_TO_SHIFT (4U)
2284/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C
2285 * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation,
2286 * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A
2287 * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after
2288 * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the
2289 * I2C function clock.
2290 */
2291#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
2292/*! @} */
2293
2294/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */
2295/*! @{ */
2296#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU)
2297#define I2C_CLKDIV_DIVVAL_SHIFT (0U)
2298/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that
2299 * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 =
2300 * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is
2301 * divided by 65,536 before use.
2302 */
2303#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
2304/*! @} */
2305
2306/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
2307/*! @{ */
2308#define I2C_INTSTAT_MSTPENDING_MASK (0x1U)
2309#define I2C_INTSTAT_MSTPENDING_SHIFT (0U)
2310/*! MSTPENDING - Master Pending.
2311 */
2312#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
2313#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U)
2314#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U)
2315/*! MSTARBLOSS - Master Arbitration Loss flag.
2316 */
2317#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
2318#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U)
2319#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U)
2320/*! MSTSTSTPERR - Master Start/Stop Error flag.
2321 */
2322#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
2323#define I2C_INTSTAT_SLVPENDING_MASK (0x100U)
2324#define I2C_INTSTAT_SLVPENDING_SHIFT (8U)
2325/*! SLVPENDING - Slave Pending.
2326 */
2327#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
2328#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U)
2329#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U)
2330/*! SLVNOTSTR - Slave Not Stretching status.
2331 */
2332#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
2333#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U)
2334#define I2C_INTSTAT_SLVDESEL_SHIFT (15U)
2335/*! SLVDESEL - Slave Deselected flag.
2336 */
2337#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
2338#define I2C_INTSTAT_MONRDY_MASK (0x10000U)
2339#define I2C_INTSTAT_MONRDY_SHIFT (16U)
2340/*! MONRDY - Monitor Ready.
2341 */
2342#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
2343#define I2C_INTSTAT_MONOV_MASK (0x20000U)
2344#define I2C_INTSTAT_MONOV_SHIFT (17U)
2345/*! MONOV - Monitor Overflow flag.
2346 */
2347#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
2348#define I2C_INTSTAT_MONIDLE_MASK (0x80000U)
2349#define I2C_INTSTAT_MONIDLE_SHIFT (19U)
2350/*! MONIDLE - Monitor Idle flag.
2351 */
2352#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
2353#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U)
2354#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U)
2355/*! EVENTTIMEOUT - Event time-out Interrupt flag.
2356 */
2357#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
2358#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U)
2359#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U)
2360/*! SCLTIMEOUT - SCL time-out Interrupt flag.
2361 */
2362#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
2363/*! @} */
2364
2365/*! @name MSTCTL - Master control register. */
2366/*! @{ */
2367#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U)
2368#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U)
2369/*! MSTCONTINUE - Master Continue. This bit is write-only.
2370 * 0b0..No effect.
2371 * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing
2372 * transmit data, reading received data, or any other housekeeping related to the next bus operation.
2373 */
2374#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
2375#define I2C_MSTCTL_MSTSTART_MASK (0x2U)
2376#define I2C_MSTCTL_MSTSTART_SHIFT (1U)
2377/*! MSTSTART - Master Start control.
2378 * 0b0..No effect.
2379 * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time.
2380 */
2381#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
2382#define I2C_MSTCTL_MSTSTOP_MASK (0x4U)
2383#define I2C_MSTCTL_MSTSTOP_SHIFT (2U)
2384/*! MSTSTOP - Master Stop control.
2385 * 0b0..No effect.
2386 * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave
2387 * if the master is receiving data from the slave (Master Receiver mode).
2388 */
2389#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
2390/*! @} */
2391
2392/*! @name MSTTIME - Master timing configuration. */
2393/*! @{ */
2394#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U)
2395#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U)
2396/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this
2397 * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This
2398 * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters
2399 * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.
2400 * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
2401 * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
2402 * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
2403 * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
2404 * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
2405 * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
2406 * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
2407 * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
2408 */
2409#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
2410#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U)
2411#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U)
2412/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this
2413 * master on SCL. Other masters in a multi-master system could shorten this time. This
2414 * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters
2415 * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.
2416 * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
2417 * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
2418 * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
2419 * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
2420 * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
2421 * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
2422 * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
2423 * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
2424 */
2425#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
2426/*! @} */
2427
2428/*! @name MSTDAT - Combined Master receiver and transmitter data register. */
2429/*! @{ */
2430#define I2C_MSTDAT_DATA_MASK (0xFFU)
2431#define I2C_MSTDAT_DATA_SHIFT (0U)
2432/*! DATA - Master function data register. Read: read the most recently received data for the Master
2433 * function. Write: transmit data using the Master function.
2434 */
2435#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
2436/*! @} */
2437
2438/*! @name SLVCTL - Slave control register. */
2439/*! @{ */
2440#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U)
2441#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U)
2442/*! SLVCONTINUE - Slave Continue.
2443 * 0b0..No effect.
2444 * 0b1..Continue. Informs the Slave function to continue to the next operation. This must done after writing
2445 * transmit data, reading received data, or any other housekeeping related to the next bus operation.
2446 */
2447#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
2448#define I2C_SLVCTL_SLVNACK_MASK (0x2U)
2449#define I2C_SLVCTL_SLVNACK_SHIFT (1U)
2450/*! SLVNACK - Slave NACK.
2451 * 0b0..No effect.
2452 * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).
2453 */
2454#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
2455/*! @} */
2456
2457/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */
2458/*! @{ */
2459#define I2C_SLVDAT_DATA_MASK (0xFFU)
2460#define I2C_SLVDAT_DATA_SHIFT (0U)
2461/*! DATA - Slave function data register. Read: read the most recently received data for the Slave
2462 * function. Write: transmit data using the Slave function.
2463 */
2464#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
2465/*! @} */
2466
2467/*! @name SLVADR - Slave address register. */
2468/*! @{ */
2469#define I2C_SLVADR_SADISABLE_MASK (0x1U)
2470#define I2C_SLVADR_SADISABLE_SHIFT (0U)
2471/*! SADISABLE - Slave Address n Disable.
2472 * 0b0..Enabled. Slave Address n is enabled.
2473 * 0b1..Ignored Slave Address n is ignored.
2474 */
2475#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
2476#define I2C_SLVADR_SLVADR_MASK (0xFEU)
2477#define I2C_SLVADR_SLVADR_SHIFT (1U)
2478/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled.
2479 */
2480#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
2481/*! @} */
2482
2483/* The count of I2C_SLVADR */
2484#define I2C_SLVADR_COUNT (4U)
2485
2486/*! @name SLVQUAL0 - Slave Qualification for address 0. */
2487/*! @{ */
2488#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U)
2489#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U)
2490/*! QUALMODE0 - Qualify mode for slave address 0.
2491 * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
2492 * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
2493 */
2494#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
2495#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU)
2496#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U)
2497/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to
2498 * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is
2499 * set to 1 will cause an automatic match of the corresponding bit of the received address when it
2500 * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for
2501 * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0
2502 * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).
2503 */
2504#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
2505/*! @} */
2506
2507/*! @name MONRXDAT - Monitor receiver data register. */
2508/*! @{ */
2509#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU)
2510#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U)
2511/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.
2512 */
2513#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
2514#define I2C_MONRXDAT_MONSTART_MASK (0x100U)
2515#define I2C_MONRXDAT_MONSTART_SHIFT (8U)
2516/*! MONSTART - Monitor Received Start.
2517 * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus.
2518 * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus.
2519 */
2520#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
2521#define I2C_MONRXDAT_MONRESTART_MASK (0x200U)
2522#define I2C_MONRXDAT_MONRESTART_SHIFT (9U)
2523/*! MONRESTART - Monitor Received Repeated Start.
2524 * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
2525 * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
2526 */
2527#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
2528#define I2C_MONRXDAT_MONNACK_MASK (0x400U)
2529#define I2C_MONRXDAT_MONNACK_SHIFT (10U)
2530/*! MONNACK - Monitor Received NACK.
2531 * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
2532 * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
2533 */
2534#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
2535/*! @} */
2536
2537
2538/*!
2539 * @}
2540 */ /* end of group I2C_Register_Masks */
2541
2542
2543/* I2C - Peripheral instance base addresses */
2544/** Peripheral I2C0 base address */
2545#define I2C0_BASE (0x40050000u)
2546/** Peripheral I2C0 base pointer */
2547#define I2C0 ((I2C_Type *)I2C0_BASE)
2548/** Array initializer of I2C peripheral base addresses */
2549#define I2C_BASE_ADDRS { I2C0_BASE }
2550/** Array initializer of I2C peripheral base pointers */
2551#define I2C_BASE_PTRS { I2C0 }
2552/** Interrupt vectors for the I2C peripheral type */
2553#define I2C_IRQS { I2C0_IRQn }
2554
2555/*!
2556 * @}
2557 */ /* end of group I2C_Peripheral_Access_Layer */
2558
2559
2560/* ----------------------------------------------------------------------------
2561 -- IOCON Peripheral Access Layer
2562 ---------------------------------------------------------------------------- */
2563
2564/*!
2565 * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer
2566 * @{
2567 */
2568
2569/** IOCON - Register Layout Typedef */
2570typedef struct {
2571 __IO uint32_t PIO[19]; /**< Digital I/O control for pins PIO0_17..Digital I/O control for pins PIO0_14, array offset: 0x0, array step: 0x4 */
2572} IOCON_Type;
2573
2574/* ----------------------------------------------------------------------------
2575 -- IOCON Register Masks
2576 ---------------------------------------------------------------------------- */
2577
2578/*!
2579 * @addtogroup IOCON_Register_Masks IOCON Register Masks
2580 * @{
2581 */
2582
2583/*! @name PIO - Digital I/O control for pins PIO0_17..Digital I/O control for pins PIO0_14 */
2584/*! @{ */
2585#define IOCON_PIO_MODE_MASK (0x18U)
2586#define IOCON_PIO_MODE_SHIFT (3U)
2587/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control).
2588 * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled).
2589 * 0b01..Pull-down. Pull-down resistor enabled.
2590 * 0b10..Pull-up. Pull-up resistor enabled.
2591 * 0b11..Repeater. Repeater mode.
2592 */
2593#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
2594#define IOCON_PIO_HYS_MASK (0x20U)
2595#define IOCON_PIO_HYS_SHIFT (5U)
2596/*! HYS - Hysteresis.
2597 * 0b0..Disable
2598 * 0b1..Enable
2599 */
2600#define IOCON_PIO_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_HYS_SHIFT)) & IOCON_PIO_HYS_MASK)
2601#define IOCON_PIO_INV_MASK (0x40U)
2602#define IOCON_PIO_INV_SHIFT (6U)
2603/*! INV - Invert input
2604 * 0b0..Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
2605 * 0b1..Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
2606 */
2607#define IOCON_PIO_INV(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INV_SHIFT)) & IOCON_PIO_INV_MASK)
2608#define IOCON_PIO_OD_MASK (0x400U)
2609#define IOCON_PIO_OD_SHIFT (10U)
2610/*! OD - Open-drain mode.
2611 * 0b0..Disable.
2612 * 0b1..Open-drain mode enabled. Remark: This is not a true open-drain mode.
2613 */
2614#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
2615/*! @} */
2616
2617/* The count of IOCON_PIO */
2618#define IOCON_PIO_COUNT (19U)
2619
2620
2621/*!
2622 * @}
2623 */ /* end of group IOCON_Register_Masks */
2624
2625
2626/* IOCON - Peripheral instance base addresses */
2627/** Peripheral IOCON base address */
2628#define IOCON_BASE (0x40044000u)
2629/** Peripheral IOCON base pointer */
2630#define IOCON ((IOCON_Type *)IOCON_BASE)
2631/** Array initializer of IOCON peripheral base addresses */
2632#define IOCON_BASE_ADDRS { IOCON_BASE }
2633/** Array initializer of IOCON peripheral base pointers */
2634#define IOCON_BASE_PTRS { IOCON }
2635
2636#define IOCON_INDEX_PIO0_17 ( 0)
2637#define IOCON_INDEX_PIO0_13 ( 1)
2638#define IOCON_INDEX_PIO0_12 ( 2)
2639#define IOCON_INDEX_PIO0_5 ( 3)
2640#define IOCON_INDEX_PIO0_4 ( 4)
2641#define IOCON_INDEX_PIO0_3 ( 5)
2642#define IOCON_INDEX_PIO0_2 ( 6)
2643#define IOCON_INDEX_PIO0_11 ( 7)
2644#define IOCON_INDEX_PIO0_10 ( 8)
2645#define IOCON_INDEX_PIO0_16 ( 9)
2646#define IOCON_INDEX_PIO0_15 (10)
2647#define IOCON_INDEX_PIO0_1 (11)
2648#define IOCON_INDEX_PIO0_9 (13)
2649#define IOCON_INDEX_PIO0_8 (14)
2650#define IOCON_INDEX_PIO0_7 (15)
2651#define IOCON_INDEX_PIO0_0 (17)
2652#define IOCON_INDEX_PIO0_14 (18)
2653
2654
2655/*!
2656 * @}
2657 */ /* end of group IOCON_Peripheral_Access_Layer */
2658
2659
2660/* ----------------------------------------------------------------------------
2661 -- MRT Peripheral Access Layer
2662 ---------------------------------------------------------------------------- */
2663
2664/*!
2665 * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
2666 * @{
2667 */
2668
2669/** MRT - Register Layout Typedef */
2670typedef struct {
2671 struct { /* offset: 0x0, array step: 0x10 */
2672 __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */
2673 __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */
2674 __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */
2675 __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */
2676 } CHANNEL[2];
2677 uint8_t RESERVED_0[208];
2678 __I uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance., offset: 0xF0 */
2679 __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */
2680 __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */
2681} MRT_Type;
2682
2683/* ----------------------------------------------------------------------------
2684 -- MRT Register Masks
2685 ---------------------------------------------------------------------------- */
2686
2687/*!
2688 * @addtogroup MRT_Register_Masks MRT Register Masks
2689 * @{
2690 */
2691
2692/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */
2693/*! @{ */
2694#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0x7FFFFFFFU)
2695#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U)
2696/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT
2697 * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to
2698 * this bit field starts the timer immediately. If the timer is running, writing a zero to this
2699 * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer
2700 * stops at the end of the time interval.
2701 */
2702#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
2703#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U)
2704#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U)
2705/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register.
2706 * This bit is write-only. Reading this bit always returns 0.
2707 * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the
2708 * time interval if the repeat mode is selected.
2709 * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
2710 */
2711#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
2712/*! @} */
2713
2714/* The count of MRT_CHANNEL_INTVAL */
2715#define MRT_CHANNEL_INTVAL_COUNT (2U)
2716
2717/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */
2718/*! @{ */
2719#define MRT_CHANNEL_TIMER_VALUE_MASK (0x7FFFFFFFU)
2720#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U)
2721/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn
2722 * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval
2723 * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn
2724 * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields
2725 * returns -1 (0x00FF FFFF).
2726 */
2727#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
2728/*! @} */
2729
2730/* The count of MRT_CHANNEL_TIMER */
2731#define MRT_CHANNEL_TIMER_COUNT (2U)
2732
2733/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */
2734/*! @{ */
2735#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U)
2736#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U)
2737/*! INTEN - Enable the TIMERn interrupt.
2738 * 0b0..Disabled. TIMERn interrupt is disabled.
2739 * 0b1..Enabled. TIMERn interrupt is enabled.
2740 */
2741#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
2742#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U)
2743#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U)
2744/*! MODE - Selects timer mode.
2745 * 0b00..Repeat interrupt mode.
2746 * 0b01..One-shot interrupt mode.
2747 * 0b10..One-shot stall mode.
2748 * 0b11..Reserved.
2749 */
2750#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
2751/*! @} */
2752
2753/* The count of MRT_CHANNEL_CTRL */
2754#define MRT_CHANNEL_CTRL_COUNT (2U)
2755
2756/*! @name CHANNEL_STAT - MRT Status register. */
2757/*! @{ */
2758#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U)
2759#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U)
2760/*! INTFLAG - Monitors the interrupt flag.
2761 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
2762 * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If
2763 * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt
2764 * are raised. Writing a 1 to this bit clears the interrupt request.
2765 */
2766#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
2767#define MRT_CHANNEL_STAT_RUN_MASK (0x2U)
2768#define MRT_CHANNEL_STAT_RUN_SHIFT (1U)
2769/*! RUN - Indicates the state of TIMERn. This bit is read-only.
2770 * 0b0..Idle state. TIMERn is stopped.
2771 * 0b1..Running. TIMERn is running.
2772 */
2773#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
2774/*! @} */
2775
2776/* The count of MRT_CHANNEL_STAT */
2777#define MRT_CHANNEL_STAT_COUNT (2U)
2778
2779/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance. */
2780/*! @{ */
2781#define MRT_MODCFG_NOC_MASK (0xFU)
2782#define MRT_MODCFG_NOC_SHIFT (0U)
2783/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.)
2784 */
2785#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
2786#define MRT_MODCFG_NOB_MASK (0x1F0U)
2787#define MRT_MODCFG_NOB_SHIFT (4U)
2788/*! NOB - Identifies the number of timer bits in this MRT. (31 bits wide on this device.)
2789 */
2790#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
2791/*! @} */
2792
2793/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */
2794/*! @{ */
2795#define MRT_IDLE_CH_CHAN_MASK (0xF0U)
2796#define MRT_IDLE_CH_CHAN_SHIFT (4U)
2797/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is
2798 * positioned such that it can be used as an offset from the MRT base address in order to access
2799 * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See
2800 * text above for more details.
2801 */
2802#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
2803/*! @} */
2804
2805/*! @name IRQ_FLAG - Global interrupt flag register */
2806/*! @{ */
2807#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U)
2808#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U)
2809/*! GFLAG0 - Monitors the interrupt flag of TIMER0.
2810 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
2811 * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If
2812 * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global
2813 * interrupt are raised. Writing a 1 to this bit clears the interrupt request.
2814 */
2815#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
2816#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U)
2817#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U)
2818/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0.
2819 */
2820#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
2821/*! @} */
2822
2823
2824/*!
2825 * @}
2826 */ /* end of group MRT_Register_Masks */
2827
2828
2829/* MRT - Peripheral instance base addresses */
2830/** Peripheral MRT0 base address */
2831#define MRT0_BASE (0x40004000u)
2832/** Peripheral MRT0 base pointer */
2833#define MRT0 ((MRT_Type *)MRT0_BASE)
2834/** Array initializer of MRT peripheral base addresses */
2835#define MRT_BASE_ADDRS { MRT0_BASE }
2836/** Array initializer of MRT peripheral base pointers */
2837#define MRT_BASE_PTRS { MRT0 }
2838/** Interrupt vectors for the MRT peripheral type */
2839#define MRT_IRQS { MRT0_IRQn }
2840
2841/*!
2842 * @}
2843 */ /* end of group MRT_Peripheral_Access_Layer */
2844
2845
2846/* ----------------------------------------------------------------------------
2847 -- PINT Peripheral Access Layer
2848 ---------------------------------------------------------------------------- */
2849
2850/*!
2851 * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
2852 * @{
2853 */
2854
2855/** PINT - Register Layout Typedef */
2856typedef struct {
2857 __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */
2858 __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */
2859 __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */
2860 __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */
2861 __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */
2862 __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */
2863 __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */
2864 __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */
2865 __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */
2866 __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */
2867 __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */
2868 __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */
2869 __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */
2870} PINT_Type;
2871
2872/* ----------------------------------------------------------------------------
2873 -- PINT Register Masks
2874 ---------------------------------------------------------------------------- */
2875
2876/*!
2877 * @addtogroup PINT_Register_Masks PINT Register Masks
2878 * @{
2879 */
2880
2881/*! @name ISEL - Pin Interrupt Mode register */
2882/*! @{ */
2883#define PINT_ISEL_PMODE_MASK (0xFFU)
2884#define PINT_ISEL_PMODE_SHIFT (0U)
2885/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt
2886 * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive
2887 */
2888#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
2889/*! @} */
2890
2891/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */
2892/*! @{ */
2893#define PINT_IENR_ENRL_MASK (0xFFU)
2894#define PINT_IENR_ENRL_SHIFT (0U)
2895/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the
2896 * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable
2897 * rising edge or level interrupt.
2898 */
2899#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
2900/*! @} */
2901
2902/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */
2903/*! @{ */
2904#define PINT_SIENR_SETENRL_MASK (0xFFU)
2905#define PINT_SIENR_SETENRL_SHIFT (0U)
2906/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n
2907 * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.
2908 */
2909#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
2910/*! @} */
2911
2912/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */
2913/*! @{ */
2914#define PINT_CIENR_CENRL_MASK (0xFFU)
2915#define PINT_CIENR_CENRL_SHIFT (0U)
2916/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit
2917 * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level
2918 * interrupt.
2919 */
2920#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
2921/*! @} */
2922
2923/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */
2924/*! @{ */
2925#define PINT_IENF_ENAF_MASK (0xFFU)
2926#define PINT_IENF_ENAF_SHIFT (0U)
2927/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt.
2928 * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt
2929 * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active
2930 * interrupt level HIGH.
2931 */
2932#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
2933/*! @} */
2934
2935/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */
2936/*! @{ */
2937#define PINT_SIENF_SETENAF_MASK (0xFFU)
2938#define PINT_SIENF_SETENAF_SHIFT (0U)
2939/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n
2940 * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable
2941 * falling edge interrupt.
2942 */
2943#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
2944/*! @} */
2945
2946/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */
2947/*! @{ */
2948#define PINT_CIENF_CENAF_MASK (0xFFU)
2949#define PINT_CIENF_CENAF_SHIFT (0U)
2950/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n
2951 * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or
2952 * falling edge interrupt disabled.
2953 */
2954#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
2955/*! @} */
2956
2957/*! @name RISE - Pin interrupt rising edge register */
2958/*! @{ */
2959#define PINT_RISE_RDET_MASK (0xFFU)
2960#define PINT_RISE_RDET_SHIFT (0U)
2961/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read
2962 * 0: No rising edge has been detected on this pin since Reset or the last time a one was written
2963 * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the
2964 * last time a one was written to this bit. Write 1: clear rising edge detection for this pin.
2965 */
2966#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
2967/*! @} */
2968
2969/*! @name FALL - Pin interrupt falling edge register */
2970/*! @{ */
2971#define PINT_FALL_FDET_MASK (0xFFU)
2972#define PINT_FALL_FDET_SHIFT (0U)
2973/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read
2974 * 0: No falling edge has been detected on this pin since Reset or the last time a one was
2975 * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or
2976 * the last time a one was written to this bit. Write 1: clear falling edge detection for this
2977 * pin.
2978 */
2979#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
2980/*! @} */
2981
2982/*! @name IST - Pin interrupt status register */
2983/*! @{ */
2984#define PINT_IST_PSTAT_MASK (0xFFU)
2985#define PINT_IST_PSTAT_SHIFT (0U)
2986/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts
2987 * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for
2988 * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this
2989 * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin.
2990 * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).
2991 */
2992#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
2993/*! @} */
2994
2995/*! @name PMCTRL - Pattern match interrupt control register */
2996/*! @{ */
2997#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U)
2998#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U)
2999/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.
3000 * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.
3001 * 0b1..Pattern match. Interrupts are driven in response to pattern matches.
3002 */
3003#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
3004#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U)
3005#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U)
3006/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.
3007 * 0b0..Disabled. RXEV output to the CPU is disabled.
3008 * 0b1..Enabled. RXEV output to the CPU is enabled.
3009 */
3010#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
3011#define PINT_PMCTRL_PMAT_MASK (0xFF000000U)
3012#define PINT_PMCTRL_PMAT_SHIFT (24U)
3013/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field
3014 * indicates that the corresponding product term is matched by the current state of the appropriate
3015 * inputs.
3016 */
3017#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
3018/*! @} */
3019
3020/*! @name PMSRC - Pattern match interrupt bit-slice source register */
3021/*! @{ */
3022#define PINT_PMSRC_SRC0_MASK (0x700U)
3023#define PINT_PMSRC_SRC0_SHIFT (8U)
3024/*! SRC0 - Selects the input source for bit slice 0
3025 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.
3026 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0.
3027 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0.
3028 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0.
3029 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0.
3030 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0.
3031 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0.
3032 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0.
3033 */
3034#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
3035#define PINT_PMSRC_SRC1_MASK (0x3800U)
3036#define PINT_PMSRC_SRC1_SHIFT (11U)
3037/*! SRC1 - Selects the input source for bit slice 1
3038 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.
3039 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1.
3040 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1.
3041 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1.
3042 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1.
3043 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1.
3044 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1.
3045 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1.
3046 */
3047#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
3048#define PINT_PMSRC_SRC2_MASK (0x1C000U)
3049#define PINT_PMSRC_SRC2_SHIFT (14U)
3050/*! SRC2 - Selects the input source for bit slice 2
3051 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.
3052 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2.
3053 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2.
3054 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2.
3055 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2.
3056 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2.
3057 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2.
3058 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2.
3059 */
3060#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
3061#define PINT_PMSRC_SRC3_MASK (0xE0000U)
3062#define PINT_PMSRC_SRC3_SHIFT (17U)
3063/*! SRC3 - Selects the input source for bit slice 3
3064 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3.
3065 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3.
3066 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3.
3067 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3.
3068 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3.
3069 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3.
3070 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3.
3071 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3.
3072 */
3073#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
3074#define PINT_PMSRC_SRC4_MASK (0x700000U)
3075#define PINT_PMSRC_SRC4_SHIFT (20U)
3076/*! SRC4 - Selects the input source for bit slice 4
3077 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.
3078 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4.
3079 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4.
3080 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4.
3081 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4.
3082 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4.
3083 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4.
3084 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4.
3085 */
3086#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
3087#define PINT_PMSRC_SRC5_MASK (0x3800000U)
3088#define PINT_PMSRC_SRC5_SHIFT (23U)
3089/*! SRC5 - Selects the input source for bit slice 5
3090 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.
3091 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5.
3092 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5.
3093 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5.
3094 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5.
3095 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5.
3096 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5.
3097 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5.
3098 */
3099#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
3100#define PINT_PMSRC_SRC6_MASK (0x1C000000U)
3101#define PINT_PMSRC_SRC6_SHIFT (26U)
3102/*! SRC6 - Selects the input source for bit slice 6
3103 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.
3104 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6.
3105 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6.
3106 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6.
3107 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6.
3108 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6.
3109 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6.
3110 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6.
3111 */
3112#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
3113#define PINT_PMSRC_SRC7_MASK (0xE0000000U)
3114#define PINT_PMSRC_SRC7_SHIFT (29U)
3115/*! SRC7 - Selects the input source for bit slice 7
3116 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7.
3117 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7.
3118 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7.
3119 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7.
3120 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7.
3121 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7.
3122 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7.
3123 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7.
3124 */
3125#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
3126/*! @} */
3127
3128/*! @name PMCFG - Pattern match interrupt bit slice configuration register */
3129/*! @{ */
3130#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U)
3131#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U)
3132/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint.
3133 * 0b0..No effect. Slice 0 is not an endpoint.
3134 * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.
3135 */
3136#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
3137#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U)
3138#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U)
3139/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint.
3140 * 0b0..No effect. Slice 1 is not an endpoint.
3141 * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.
3142 */
3143#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
3144#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U)
3145#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U)
3146/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint.
3147 * 0b0..No effect. Slice 2 is not an endpoint.
3148 * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.
3149 */
3150#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
3151#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U)
3152#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U)
3153/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint.
3154 * 0b0..No effect. Slice 3 is not an endpoint.
3155 * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.
3156 */
3157#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
3158#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U)
3159#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U)
3160/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint.
3161 * 0b0..No effect. Slice 4 is not an endpoint.
3162 * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.
3163 */
3164#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
3165#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U)
3166#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U)
3167/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint.
3168 * 0b0..No effect. Slice 5 is not an endpoint.
3169 * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.
3170 */
3171#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
3172#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U)
3173#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U)
3174/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint.
3175 * 0b0..No effect. Slice 6 is not an endpoint.
3176 * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.
3177 */
3178#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
3179#define PINT_PMCFG_CFG0_MASK (0x700U)
3180#define PINT_PMCFG_CFG0_SHIFT (8U)
3181/*! CFG0 - Specifies the match contribution condition for bit slice 0.
3182 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
3183 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
3184 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3185 * PMSRC registers are written to.
3186 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
3187 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3188 * PMSRC registers are written to.
3189 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
3190 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
3191 * cleared when the PMCFG or the PMSRC registers are written to.
3192 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
3193 * 0b101..Low level. Match occurs when there is a low level on the specified input.
3194 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
3195 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
3196 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
3197 * is cleared after one clock cycle.
3198 */
3199#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
3200#define PINT_PMCFG_CFG1_MASK (0x3800U)
3201#define PINT_PMCFG_CFG1_SHIFT (11U)
3202/*! CFG1 - Specifies the match contribution condition for bit slice 1.
3203 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
3204 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
3205 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3206 * PMSRC registers are written to.
3207 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
3208 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3209 * PMSRC registers are written to.
3210 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
3211 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
3212 * cleared when the PMCFG or the PMSRC registers are written to.
3213 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
3214 * 0b101..Low level. Match occurs when there is a low level on the specified input.
3215 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
3216 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
3217 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
3218 * is cleared after one clock cycle.
3219 */
3220#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
3221#define PINT_PMCFG_CFG2_MASK (0x1C000U)
3222#define PINT_PMCFG_CFG2_SHIFT (14U)
3223/*! CFG2 - Specifies the match contribution condition for bit slice 2.
3224 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
3225 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
3226 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3227 * PMSRC registers are written to.
3228 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
3229 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3230 * PMSRC registers are written to.
3231 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
3232 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
3233 * cleared when the PMCFG or the PMSRC registers are written to.
3234 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
3235 * 0b101..Low level. Match occurs when there is a low level on the specified input.
3236 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
3237 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
3238 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
3239 * is cleared after one clock cycle.
3240 */
3241#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
3242#define PINT_PMCFG_CFG3_MASK (0xE0000U)
3243#define PINT_PMCFG_CFG3_SHIFT (17U)
3244/*! CFG3 - Specifies the match contribution condition for bit slice 3.
3245 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
3246 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
3247 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3248 * PMSRC registers are written to.
3249 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
3250 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3251 * PMSRC registers are written to.
3252 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
3253 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
3254 * cleared when the PMCFG or the PMSRC registers are written to.
3255 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
3256 * 0b101..Low level. Match occurs when there is a low level on the specified input.
3257 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
3258 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
3259 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
3260 * is cleared after one clock cycle.
3261 */
3262#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
3263#define PINT_PMCFG_CFG4_MASK (0x700000U)
3264#define PINT_PMCFG_CFG4_SHIFT (20U)
3265/*! CFG4 - Specifies the match contribution condition for bit slice 4.
3266 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
3267 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
3268 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3269 * PMSRC registers are written to.
3270 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
3271 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3272 * PMSRC registers are written to.
3273 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
3274 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
3275 * cleared when the PMCFG or the PMSRC registers are written to.
3276 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
3277 * 0b101..Low level. Match occurs when there is a low level on the specified input.
3278 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
3279 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
3280 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
3281 * is cleared after one clock cycle.
3282 */
3283#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
3284#define PINT_PMCFG_CFG5_MASK (0x3800000U)
3285#define PINT_PMCFG_CFG5_SHIFT (23U)
3286/*! CFG5 - Specifies the match contribution condition for bit slice 5.
3287 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
3288 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
3289 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3290 * PMSRC registers are written to.
3291 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
3292 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3293 * PMSRC registers are written to.
3294 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
3295 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
3296 * cleared when the PMCFG or the PMSRC registers are written to.
3297 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
3298 * 0b101..Low level. Match occurs when there is a low level on the specified input.
3299 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
3300 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
3301 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
3302 * is cleared after one clock cycle.
3303 */
3304#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
3305#define PINT_PMCFG_CFG6_MASK (0x1C000000U)
3306#define PINT_PMCFG_CFG6_SHIFT (26U)
3307/*! CFG6 - Specifies the match contribution condition for bit slice 6.
3308 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
3309 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
3310 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3311 * PMSRC registers are written to.
3312 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
3313 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3314 * PMSRC registers are written to.
3315 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
3316 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
3317 * cleared when the PMCFG or the PMSRC registers are written to.
3318 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
3319 * 0b101..Low level. Match occurs when there is a low level on the specified input.
3320 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
3321 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
3322 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
3323 * is cleared after one clock cycle.
3324 */
3325#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
3326#define PINT_PMCFG_CFG7_MASK (0xE0000000U)
3327#define PINT_PMCFG_CFG7_SHIFT (29U)
3328/*! CFG7 - Specifies the match contribution condition for bit slice 7.
3329 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
3330 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
3331 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3332 * PMSRC registers are written to.
3333 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
3334 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3335 * PMSRC registers are written to.
3336 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
3337 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
3338 * cleared when the PMCFG or the PMSRC registers are written to.
3339 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
3340 * 0b101..Low level. Match occurs when there is a low level on the specified input.
3341 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
3342 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
3343 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
3344 * is cleared after one clock cycle.
3345 */
3346#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
3347/*! @} */
3348
3349
3350/*!
3351 * @}
3352 */ /* end of group PINT_Register_Masks */
3353
3354
3355/* PINT - Peripheral instance base addresses */
3356/** Peripheral PINT base address */
3357#define PINT_BASE (0xA0004000u)
3358/** Peripheral PINT base pointer */
3359#define PINT ((PINT_Type *)PINT_BASE)
3360/** Array initializer of PINT peripheral base addresses */
3361#define PINT_BASE_ADDRS { PINT_BASE }
3362/** Array initializer of PINT peripheral base pointers */
3363#define PINT_BASE_PTRS { PINT }
3364/** Interrupt vectors for the PINT peripheral type */
3365#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }
3366
3367/*!
3368 * @}
3369 */ /* end of group PINT_Peripheral_Access_Layer */
3370
3371
3372/* ----------------------------------------------------------------------------
3373 -- PMU Peripheral Access Layer
3374 ---------------------------------------------------------------------------- */
3375
3376/*!
3377 * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer
3378 * @{
3379 */
3380
3381/** PMU - Register Layout Typedef */
3382typedef struct {
3383 __IO uint32_t PCON; /**< Power control register, offset: 0x0 */
3384 __IO uint32_t GPREG[5]; /**< General purpose register N, array offset: 0x4, array step: 0x4 */
3385 uint8_t RESERVED_0[8];
3386 __IO uint32_t WUSRCREG; /**< Pin wake-up source register, offset: 0x20 */
3387 __IO uint32_t WUENAREG; /**< Pin wake-up enable register, offset: 0x24 */
3388} PMU_Type;
3389
3390/* ----------------------------------------------------------------------------
3391 -- PMU Register Masks
3392 ---------------------------------------------------------------------------- */
3393
3394/*!
3395 * @addtogroup PMU_Register_Masks PMU Register Masks
3396 * @{
3397 */
3398
3399/*! @name PCON - Power control register */
3400/*! @{ */
3401#define PMU_PCON_PM_MASK (0x7U)
3402#define PMU_PCON_PM_SHIFT (0U)
3403/*! PM - Power mode
3404 * 0b000..Default. The part is in active or sleep mode.
3405 * 0b001..Deep-sleep mode. ARM WFI will enter Deep-sleep mode.
3406 * 0b010..Power-down mode. ARM WFI will enter Power-down mode.
3407 * 0b011..Deep power-down mode. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down).
3408 */
3409#define PMU_PCON_PM(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_PM_SHIFT)) & PMU_PCON_PM_MASK)
3410#define PMU_PCON_NODPD_MASK (0x8U)
3411#define PMU_PCON_NODPD_SHIFT (3U)
3412/*! NODPD - A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM
3413 * field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by
3414 * power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode
3415 * is blocked.
3416 */
3417#define PMU_PCON_NODPD(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_NODPD_SHIFT)) & PMU_PCON_NODPD_MASK)
3418#define PMU_PCON_SLEEPFLAG_MASK (0x100U)
3419#define PMU_PCON_SLEEPFLAG_SHIFT (8U)
3420/*! SLEEPFLAG - Sleep mode flag
3421 * 0b0..Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect.
3422 * 0b1..Low power mode. Read: Sleep, Deep-sleep or Power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0.
3423 */
3424#define PMU_PCON_SLEEPFLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_SLEEPFLAG_SHIFT)) & PMU_PCON_SLEEPFLAG_MASK)
3425#define PMU_PCON_DPDFLAG_MASK (0x800U)
3426#define PMU_PCON_DPDFLAG_SHIFT (11U)
3427/*! DPDFLAG - Deep power-down flag
3428 * 0b0..Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect.
3429 * 0b1..Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag.
3430 */
3431#define PMU_PCON_DPDFLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_DPDFLAG_SHIFT)) & PMU_PCON_DPDFLAG_MASK)
3432/*! @} */
3433
3434/*! @name GPREG - General purpose register N */
3435/*! @{ */
3436#define PMU_GPREG_GPDATA_MASK (0xFFFFFFFFU)
3437#define PMU_GPREG_GPDATA_SHIFT (0U)
3438/*! GPDATA - Data retained during Deep power-down mode.
3439 */
3440#define PMU_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPREG_GPDATA_SHIFT)) & PMU_GPREG_GPDATA_MASK)
3441/*! @} */
3442
3443/* The count of PMU_GPREG */
3444#define PMU_GPREG_COUNT (5U)
3445
3446/*! @name WUSRCREG - Pin wake-up source register */
3447/*! @{ */
3448#define PMU_WUSRCREG_WUSRCREG_MASK (0xFFU)
3449#define PMU_WUSRCREG_WUSRCREG_SHIFT (0U)
3450/*! WUSRCREG - Pin wake-up source
3451 */
3452#define PMU_WUSRCREG_WUSRCREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_WUSRCREG_WUSRCREG_SHIFT)) & PMU_WUSRCREG_WUSRCREG_MASK)
3453/*! @} */
3454
3455/*! @name WUENAREG - Pin wake-up enable register */
3456/*! @{ */
3457#define PMU_WUENAREG_WUENAREG_MASK (0xFFU)
3458#define PMU_WUENAREG_WUENAREG_SHIFT (0U)
3459/*! WUENAREG - Pin wake-up enable
3460 */
3461#define PMU_WUENAREG_WUENAREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_WUENAREG_WUENAREG_SHIFT)) & PMU_WUENAREG_WUENAREG_MASK)
3462/*! @} */
3463
3464
3465/*!
3466 * @}
3467 */ /* end of group PMU_Register_Masks */
3468
3469
3470/* PMU - Peripheral instance base addresses */
3471/** Peripheral PMU base address */
3472#define PMU_BASE (0x40020000u)
3473/** Peripheral PMU base pointer */
3474#define PMU ((PMU_Type *)PMU_BASE)
3475/** Array initializer of PMU peripheral base addresses */
3476#define PMU_BASE_ADDRS { PMU_BASE }
3477/** Array initializer of PMU peripheral base pointers */
3478#define PMU_BASE_PTRS { PMU }
3479
3480/*!
3481 * @}
3482 */ /* end of group PMU_Peripheral_Access_Layer */
3483
3484
3485/* ----------------------------------------------------------------------------
3486 -- SPI Peripheral Access Layer
3487 ---------------------------------------------------------------------------- */
3488
3489/*!
3490 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
3491 * @{
3492 */
3493
3494/** SPI - Register Layout Typedef */
3495typedef struct {
3496 __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x0 */
3497 __IO uint32_t DLY; /**< SPI Delay register, offset: 0x4 */
3498 __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position, offset: 0x8 */
3499 __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */
3500 __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x10 */
3501 __I uint32_t RXDAT; /**< SPI Receive Data, offset: 0x14 */
3502 __IO uint32_t TXDATCTL; /**< SPI Transmit Data with Control, offset: 0x18 */
3503 __IO uint32_t TXDAT; /**< SPI Transmit Data., offset: 0x1C */
3504 __IO uint32_t TXCTL; /**< SPI Transmit Control, offset: 0x20 */
3505 __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x24 */
3506 __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x28 */
3507} SPI_Type;
3508
3509/* ----------------------------------------------------------------------------
3510 -- SPI Register Masks
3511 ---------------------------------------------------------------------------- */
3512
3513/*!
3514 * @addtogroup SPI_Register_Masks SPI Register Masks
3515 * @{
3516 */
3517
3518/*! @name CFG - SPI Configuration register */
3519/*! @{ */
3520#define SPI_CFG_ENABLE_MASK (0x1U)
3521#define SPI_CFG_ENABLE_SHIFT (0U)
3522/*! ENABLE - SPI enable.
3523 * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset.
3524 * 0b1..Enabled. The SPI is enabled for operation.
3525 */
3526#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
3527#define SPI_CFG_MASTER_MASK (0x4U)
3528#define SPI_CFG_MASTER_SHIFT (2U)
3529/*! MASTER - Master mode select.
3530 * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
3531 * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
3532 */
3533#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
3534#define SPI_CFG_LSBF_MASK (0x8U)
3535#define SPI_CFG_LSBF_SHIFT (3U)
3536/*! LSBF - LSB First mode enable.
3537 * 0b0..Standard. Data is transmitted and received in standard MSB first order.
3538 * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first).
3539 */
3540#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
3541#define SPI_CFG_CPHA_MASK (0x10U)
3542#define SPI_CFG_CPHA_SHIFT (4U)
3543/*! CPHA - Clock Phase select.
3544 * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock
3545 * changes away from the rest state). Data is changed on the following edge.
3546 * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock
3547 * changes away from the rest state). Data is captured on the following edge.
3548 */
3549#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
3550#define SPI_CFG_CPOL_MASK (0x20U)
3551#define SPI_CFG_CPOL_SHIFT (5U)
3552/*! CPOL - Clock Polarity select.
3553 * 0b0..Low. The rest state of the clock (between transfers) is low.
3554 * 0b1..High. The rest state of the clock (between transfers) is high.
3555 */
3556#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
3557#define SPI_CFG_LOOP_MASK (0x80U)
3558#define SPI_CFG_LOOP_SHIFT (7U)
3559/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit
3560 * and receive data connected together to allow simple software testing.
3561 * 0b0..Disabled.
3562 * 0b1..Enabled.
3563 */
3564#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
3565#define SPI_CFG_SPOL0_MASK (0x100U)
3566#define SPI_CFG_SPOL0_SHIFT (8U)
3567/*! SPOL0 - SSEL0 Polarity select.
3568 * 0b0..Low. The SSEL0 pin is active low.
3569 * 0b1..High. The SSEL0 pin is active high.
3570 */
3571#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
3572#define SPI_CFG_SPOL1_MASK (0x200U)
3573#define SPI_CFG_SPOL1_SHIFT (9U)
3574/*! SPOL1 - SSEL1 Polarity select.
3575 * 0b0..Low. The SSEL1 pin is active low.
3576 * 0b1..High. The SSEL1 pin is active high.
3577 */
3578#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
3579/*! @} */
3580
3581/*! @name DLY - SPI Delay register */
3582/*! @{ */
3583#define SPI_DLY_PRE_DELAY_MASK (0xFU)
3584#define SPI_DLY_PRE_DELAY_SHIFT (0U)
3585/*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data
3586 * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This
3587 * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI
3588 * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are
3589 * inserted.
3590 */
3591#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
3592#define SPI_DLY_POST_DELAY_MASK (0xF0U)
3593#define SPI_DLY_POST_DELAY_SHIFT (4U)
3594/*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL
3595 * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock
3596 * times are inserted. 0xF = 15 SPI clock times are inserted.
3597 */
3598#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
3599#define SPI_DLY_FRAME_DELAY_MASK (0xF00U)
3600#define SPI_DLY_FRAME_DELAY_SHIFT (8U)
3601/*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current
3602 * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1
3603 * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock
3604 * times are inserted.
3605 */
3606#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
3607#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U)
3608#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U)
3609/*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between
3610 * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1
3611 * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that
3612 * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16
3613 * SPI clock times.
3614 */
3615#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
3616/*! @} */
3617
3618/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position */
3619/*! @{ */
3620#define SPI_STAT_RXRDY_MASK (0x1U)
3621#define SPI_STAT_RXRDY_SHIFT (0U)
3622/*! RXRDY - Receiver Ready flag. When 1, indicates that data is available to be read from the
3623 * receiver buffer. Cleared after a read of the RXDAT register.
3624 */
3625#define SPI_STAT_RXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_RXRDY_SHIFT)) & SPI_STAT_RXRDY_MASK)
3626#define SPI_STAT_TXRDY_MASK (0x2U)
3627#define SPI_STAT_TXRDY_SHIFT (1U)
3628/*! TXRDY - Transmitter Ready flag. When 1, this bit indicates that data may be written to the
3629 * transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data
3630 * is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register.
3631 */
3632#define SPI_STAT_TXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_TXRDY_SHIFT)) & SPI_STAT_TXRDY_MASK)
3633#define SPI_STAT_RXOV_MASK (0x4U)
3634#define SPI_STAT_RXOV_SHIFT (2U)
3635/*! RXOV - Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This
3636 * flag is set when the beginning of a received character is detected while the receiver buffer
3637 * is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming
3638 * data is lost. Data received by the SPI should be considered undefined if RxOv is set.
3639 */
3640#define SPI_STAT_RXOV(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_RXOV_SHIFT)) & SPI_STAT_RXOV_MASK)
3641#define SPI_STAT_TXUR_MASK (0x8U)
3642#define SPI_STAT_TXUR_SHIFT (3U)
3643/*! TXUR - Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0).
3644 * In this case, the transmitter must begin sending new data on the next input clock if the
3645 * transmitter is idle. If that data is not available in the transmitter holding register at that
3646 * point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be
3647 * considered undefined if TXUR is set.
3648 */
3649#define SPI_STAT_TXUR(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_TXUR_SHIFT)) & SPI_STAT_TXUR_MASK)
3650#define SPI_STAT_SSA_MASK (0x10U)
3651#define SPI_STAT_SSA_SHIFT (4U)
3652/*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from
3653 * deasserted to asserted, in both master and slave modes. This allows determining when the SPI
3654 * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a
3655 * slave mode access begins. This flag is cleared by software.
3656 */
3657#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
3658#define SPI_STAT_SSD_MASK (0x20U)
3659#define SPI_STAT_SSD_SHIFT (5U)
3660/*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to
3661 * deasserted, in both master and slave modes. This allows determining when the SPI
3662 * transmit/receive functions become idle. This flag is cleared by software.
3663 */
3664#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
3665#define SPI_STAT_STALLED_MASK (0x40U)
3666#define SPI_STAT_STALLED_SHIFT (6U)
3667/*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition.
3668 */
3669#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
3670#define SPI_STAT_ENDTRANSFER_MASK (0x80U)
3671#define SPI_STAT_ENDTRANSFER_SHIFT (7U)
3672/*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current
3673 * transfer when the transmitter finishes any activity already in progress, as if the EOT flag
3674 * had been set prior to the last transmission. This capability is included to support cases where
3675 * it is not known when transmit data is written that it will be the end of a transfer. The bit
3676 * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end
3677 * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
3678 */
3679#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
3680#define SPI_STAT_MSTIDLE_MASK (0x100U)
3681#define SPI_STAT_MSTIDLE_SHIFT (8U)
3682/*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle.
3683 * This means that the transmit holding register is empty and the transmitter is not in the
3684 * process of sending data.
3685 */
3686#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
3687/*! @} */
3688
3689/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
3690/*! @{ */
3691#define SPI_INTENSET_RXRDYEN_MASK (0x1U)
3692#define SPI_INTENSET_RXRDYEN_SHIFT (0U)
3693/*! RXRDYEN - Determines whether an interrupt occurs when receiver data is available.
3694 * 0b0..No interrupt will be generated when receiver data is available.
3695 * 0b1..An interrupt will be generated when receiver data is available in the RXDAT register.
3696 */
3697#define SPI_INTENSET_RXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_RXRDYEN_SHIFT)) & SPI_INTENSET_RXRDYEN_MASK)
3698#define SPI_INTENSET_TXRDYEN_MASK (0x2U)
3699#define SPI_INTENSET_TXRDYEN_SHIFT (1U)
3700/*! TXRDYEN - Determines whether an interrupt occurs when the transmitter holding register is available.
3701 * 0b0..No interrupt will be generated when the transmitter holding register is available.
3702 * 0b1..An interrupt will be generated when data may be written to TXDAT.
3703 */
3704#define SPI_INTENSET_TXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_TXRDYEN_SHIFT)) & SPI_INTENSET_TXRDYEN_MASK)
3705#define SPI_INTENSET_RXOVEN_MASK (0x4U)
3706#define SPI_INTENSET_RXOVEN_SHIFT (2U)
3707/*! RXOVEN - Determines whether an interrupt occurs when a receiver overrun occurs. This happens in
3708 * slave mode when there is a need for the receiver to move newly received data to the RXDAT
3709 * register when it is already in use. The interface prevents receiver overrun in Master mode by not
3710 * allowing a new transmission to begin when a receiver overrun would otherwise occur.
3711 * 0b0..No interrupt will be generated when a receiver overrun occurs.
3712 * 0b1..An interrupt will be generated if a receiver overrun occurs.
3713 */
3714#define SPI_INTENSET_RXOVEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_RXOVEN_SHIFT)) & SPI_INTENSET_RXOVEN_MASK)
3715#define SPI_INTENSET_TXUREN_MASK (0x8U)
3716#define SPI_INTENSET_TXUREN_SHIFT (3U)
3717/*! TXUREN - Determines whether an interrupt occurs when a transmitter underrun occurs. This happens
3718 * in slave mode when there is a need to transmit data when none is available.
3719 * 0b0..No interrupt will be generated when the transmitter underruns.
3720 * 0b1..An interrupt will be generated if the transmitter underruns.
3721 */
3722#define SPI_INTENSET_TXUREN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_TXUREN_SHIFT)) & SPI_INTENSET_TXUREN_MASK)
3723#define SPI_INTENSET_SSAEN_MASK (0x10U)
3724#define SPI_INTENSET_SSAEN_SHIFT (4U)
3725/*! SSAEN - Determines whether an interrupt occurs when the Slave Select is asserted.
3726 * 0b0..No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
3727 * 0b1..An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
3728 */
3729#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
3730#define SPI_INTENSET_SSDEN_MASK (0x20U)
3731#define SPI_INTENSET_SSDEN_SHIFT (5U)
3732/*! SSDEN - Determines whether an interrupt occurs when the Slave Select is deasserted.
3733 * 0b0..No interrupt will be generated when all asserted Slave Selects transition to deasserted.
3734 * 0b1..An interrupt will be generated when all asserted Slave Selects transition to deasserted.
3735 */
3736#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
3737#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U)
3738#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U)
3739/*! MSTIDLEEN - Determines whether an interrupt occurs when the MSTIDLE enable
3740 * 0b0..No interrupt will be generated when MSTIDLE enabled.
3741 * 0b1..An interrupt will be generated when MSTIDLE enabled.
3742 */
3743#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
3744/*! @} */
3745
3746/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */
3747/*! @{ */
3748#define SPI_INTENCLR_RXRDYEN_MASK (0x1U)
3749#define SPI_INTENCLR_RXRDYEN_SHIFT (0U)
3750/*! RXRDYEN - Writing 1 clears the corresponding bits in the INTENSET register.
3751 */
3752#define SPI_INTENCLR_RXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_RXRDYEN_SHIFT)) & SPI_INTENCLR_RXRDYEN_MASK)
3753#define SPI_INTENCLR_TXRDYEN_MASK (0x2U)
3754#define SPI_INTENCLR_TXRDYEN_SHIFT (1U)
3755/*! TXRDYEN - Writing 1 clears the corresponding bits in the INTENSET register.
3756 */
3757#define SPI_INTENCLR_TXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_TXRDYEN_SHIFT)) & SPI_INTENCLR_TXRDYEN_MASK)
3758#define SPI_INTENCLR_RXOVEN_MASK (0x4U)
3759#define SPI_INTENCLR_RXOVEN_SHIFT (2U)
3760/*! RXOVEN - Writing 1 clears the corresponding bits in the INTENSET register.
3761 */
3762#define SPI_INTENCLR_RXOVEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_RXOVEN_SHIFT)) & SPI_INTENCLR_RXOVEN_MASK)
3763#define SPI_INTENCLR_TXUREN_MASK (0x8U)
3764#define SPI_INTENCLR_TXUREN_SHIFT (3U)
3765/*! TXUREN - Writing 1 clears the corresponding bits in the INTENSET register.
3766 */
3767#define SPI_INTENCLR_TXUREN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_TXUREN_SHIFT)) & SPI_INTENCLR_TXUREN_MASK)
3768#define SPI_INTENCLR_SSAEN_MASK (0x10U)
3769#define SPI_INTENCLR_SSAEN_SHIFT (4U)
3770/*! SSAEN - Writing 1 clears the corresponding bits in the INTENSET register.
3771 */
3772#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
3773#define SPI_INTENCLR_SSDEN_MASK (0x20U)
3774#define SPI_INTENCLR_SSDEN_SHIFT (5U)
3775/*! SSDEN - Writing 1 clears the corresponding bits in the INTENSET register.
3776 */
3777#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
3778#define SPI_INTENCLR_MSTIDLE_MASK (0x100U)
3779#define SPI_INTENCLR_MSTIDLE_SHIFT (8U)
3780/*! MSTIDLE - Writing 1 clears the corresponding bits in the INTENSET register.
3781 */
3782#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
3783/*! @} */
3784
3785/*! @name RXDAT - SPI Receive Data */
3786/*! @{ */
3787#define SPI_RXDAT_RXDAT_MASK (0xFFFFU)
3788#define SPI_RXDAT_RXDAT_SHIFT (0U)
3789/*! RXDAT - Receiver Data. This contains the next piece of received data. The number of bits that
3790 * are used depends on the LEN setting in TXCTL / TXDATCTL.
3791 */
3792#define SPI_RXDAT_RXDAT(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXDAT_SHIFT)) & SPI_RXDAT_RXDAT_MASK)
3793#define SPI_RXDAT_RXSSEL0_N_MASK (0x10000U)
3794#define SPI_RXDAT_RXSSEL0_N_SHIFT (16U)
3795/*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved
3796 * along with received data. The value will reflect the SSEL0 pin for both master and slave
3797 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
3798 * pin is configured by the related SPOL bit in CFG.
3799 */
3800#define SPI_RXDAT_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXSSEL0_N_SHIFT)) & SPI_RXDAT_RXSSEL0_N_MASK)
3801#define SPI_RXDAT_RXSSEL1_N_MASK (0x20000U)
3802#define SPI_RXDAT_RXSSEL1_N_SHIFT (17U)
3803/*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved
3804 * along with received data. The value will reflect the SSEL1 pin for both master and slave
3805 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
3806 * pin is configured by the related SPOL bit in CFG.
3807 */
3808#define SPI_RXDAT_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXSSEL1_N_SHIFT)) & SPI_RXDAT_RXSSEL1_N_MASK)
3809#define SPI_RXDAT_RXSSEL2_N_MASK (0x40000U)
3810#define SPI_RXDAT_RXSSEL2_N_SHIFT (18U)
3811/*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved
3812 * along with received data. The value will reflect the SSEL2 pin for both master and slave
3813 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
3814 * pin is configured by the related SPOL bit in CFG.
3815 */
3816#define SPI_RXDAT_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXSSEL2_N_SHIFT)) & SPI_RXDAT_RXSSEL2_N_MASK)
3817#define SPI_RXDAT_RXSSEL3_N_MASK (0x80000U)
3818#define SPI_RXDAT_RXSSEL3_N_SHIFT (19U)
3819/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved
3820 * along with received data. The value will reflect the SSEL3 pin for both master and slave
3821 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
3822 * pin is configured by the related SPOL bit in CFG.
3823 */
3824#define SPI_RXDAT_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXSSEL3_N_SHIFT)) & SPI_RXDAT_RXSSEL3_N_MASK)
3825#define SPI_RXDAT_SOT_MASK (0x100000U)
3826#define SPI_RXDAT_SOT_SHIFT (20U)
3827/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went
3828 * from deasserted to asserted (i.e., any previous transfer has ended). This information can be
3829 * used to identify the first piece of data in cases where the transfer length is greater than 16
3830 * bit.
3831 */
3832#define SPI_RXDAT_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_SOT_SHIFT)) & SPI_RXDAT_SOT_MASK)
3833/*! @} */
3834
3835/*! @name TXDATCTL - SPI Transmit Data with Control */
3836/*! @{ */
3837#define SPI_TXDATCTL_TXDAT_MASK (0xFFFFU)
3838#define SPI_TXDATCTL_TXDAT_SHIFT (0U)
3839/*! TXDAT - Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.
3840 */
3841#define SPI_TXDATCTL_TXDAT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_TXDAT_SHIFT)) & SPI_TXDATCTL_TXDAT_MASK)
3842#define SPI_TXDATCTL_TXSSEL0_N_MASK (0x10000U)
3843#define SPI_TXDATCTL_TXSSEL0_N_SHIFT (16U)
3844/*! TXSSEL0_N - Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the
3845 * pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in
3846 * the CFG register.
3847 * 0b0..SSEL0 asserted.
3848 * 0b1..SSEL0 not asserted.
3849 */
3850#define SPI_TXDATCTL_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_TXSSEL0_N_SHIFT)) & SPI_TXDATCTL_TXSSEL0_N_MASK)
3851#define SPI_TXDATCTL_TXSSEL1_N_MASK (0x20000U)
3852#define SPI_TXDATCTL_TXSSEL1_N_SHIFT (17U)
3853/*! TXSSEL1_N - Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the
3854 * pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in
3855 * the CFG register.
3856 * 0b0..SSEL1 asserted.
3857 * 0b1..SSEL1 not asserted.
3858 */
3859#define SPI_TXDATCTL_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_TXSSEL1_N_SHIFT)) & SPI_TXDATCTL_TXSSEL1_N_MASK)
3860#define SPI_TXDATCTL_EOT_MASK (0x100000U)
3861#define SPI_TXDATCTL_EOT_SHIFT (20U)
3862/*! EOT - End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain
3863 * so for at least the time specified by the Transfer_delay value in the DLY register.
3864 * 0b0..This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
3865 * 0b1..This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
3866 */
3867#define SPI_TXDATCTL_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_EOT_SHIFT)) & SPI_TXDATCTL_EOT_MASK)
3868#define SPI_TXDATCTL_EOF_MASK (0x200000U)
3869#define SPI_TXDATCTL_EOF_SHIFT (21U)
3870/*! EOF - End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value
3871 * in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY
3872 * value = 0. This control can be used as part of the support for frame lengths greater than 16
3873 * bits.
3874 * 0b0..This piece of data transmitted is not treated as the end of a frame.
3875 * 0b1..This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted.
3876 */
3877#define SPI_TXDATCTL_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_EOF_SHIFT)) & SPI_TXDATCTL_EOF_MASK)
3878#define SPI_TXDATCTL_RXIGNORE_MASK (0x400000U)
3879#define SPI_TXDATCTL_RXIGNORE_SHIFT (22U)
3880/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to
3881 * read unneeded data from the receiver.Setting this bit simplifies the transmit process and can
3882 * be used with the DMA.
3883 * 0b0..Received data must be read in order to allow transmission to progress. In slave mode, an overrun error
3884 * will occur if received data is not read before new data is received.
3885 * 0b1..Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
3886 */
3887#define SPI_TXDATCTL_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_RXIGNORE_SHIFT)) & SPI_TXDATCTL_RXIGNORE_MASK)
3888#define SPI_TXDATCTL_LEN_MASK (0xF000000U)
3889#define SPI_TXDATCTL_LEN_SHIFT (24U)
3890/*! LEN - Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths
3891 * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data
3892 * transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits
3893 * in length. ... 0xF = Data transfer is 16 bits in length.
3894 * 0b0000..
3895 * 0b0001..Data transfer is 1 bit in length.
3896 * 0b0010..Data transfer is 2 bit in length.
3897 * 0b0011..Data transfer is 3 bit in length.
3898 * 0b0100..Data transfer is 4 bit in length.
3899 * 0b0101..Data transfer is 5 bit in length.
3900 * 0b0110..Data transfer is 6 bit in length.
3901 * 0b0111..Data transfer is 7 bit in length.
3902 * 0b1000..Data transfer is 8 bit in length.
3903 * 0b1001..Data transfer is 9 bit in length.
3904 * 0b1010..Data transfer is 10 bit in length.
3905 * 0b1011..Data transfer is 11 bit in length.
3906 * 0b1100..Data transfer is 12 bit in length.
3907 * 0b1101..Data transfer is 13 bit in length.
3908 * 0b1110..Data transfer is 14 bit in length.
3909 * 0b1111..Data transfer is 15 bit in length.
3910 */
3911#define SPI_TXDATCTL_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_LEN_SHIFT)) & SPI_TXDATCTL_LEN_MASK)
3912/*! @} */
3913
3914/*! @name TXDAT - SPI Transmit Data. */
3915/*! @{ */
3916#define SPI_TXDAT_DATA_MASK (0xFFFFU)
3917#define SPI_TXDAT_DATA_SHIFT (0U)
3918/*! DATA - Transmit Data. This field provides from 4 to 16 bits of data to be transmitted.
3919 */
3920#define SPI_TXDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDAT_DATA_SHIFT)) & SPI_TXDAT_DATA_MASK)
3921/*! @} */
3922
3923/*! @name TXCTL - SPI Transmit Control */
3924/*! @{ */
3925#define SPI_TXCTL_TXSSEL0_N_MASK (0x10000U)
3926#define SPI_TXCTL_TXSSEL0_N_SHIFT (16U)
3927/*! TXSSEL0_N - Transmit Slave Select 0.
3928 */
3929#define SPI_TXCTL_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_TXSSEL0_N_SHIFT)) & SPI_TXCTL_TXSSEL0_N_MASK)
3930#define SPI_TXCTL_TXSSEL1_N_MASK (0x20000U)
3931#define SPI_TXCTL_TXSSEL1_N_SHIFT (17U)
3932/*! TXSSEL1_N - Transmit Slave Select 1.
3933 */
3934#define SPI_TXCTL_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_TXSSEL1_N_SHIFT)) & SPI_TXCTL_TXSSEL1_N_MASK)
3935#define SPI_TXCTL_EOT_MASK (0x100000U)
3936#define SPI_TXCTL_EOT_SHIFT (20U)
3937/*! EOT - End of Transfer.
3938 */
3939#define SPI_TXCTL_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_EOT_SHIFT)) & SPI_TXCTL_EOT_MASK)
3940#define SPI_TXCTL_EOF_MASK (0x200000U)
3941#define SPI_TXCTL_EOF_SHIFT (21U)
3942/*! EOF - End of Frame.
3943 */
3944#define SPI_TXCTL_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_EOF_SHIFT)) & SPI_TXCTL_EOF_MASK)
3945#define SPI_TXCTL_RXIGNORE_MASK (0x400000U)
3946#define SPI_TXCTL_RXIGNORE_SHIFT (22U)
3947/*! RXIGNORE - Receive Ignore.
3948 */
3949#define SPI_TXCTL_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_RXIGNORE_SHIFT)) & SPI_TXCTL_RXIGNORE_MASK)
3950#define SPI_TXCTL_LEN_MASK (0xF000000U)
3951#define SPI_TXCTL_LEN_SHIFT (24U)
3952/*! LEN - Data transfer Length.
3953 */
3954#define SPI_TXCTL_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_LEN_SHIFT)) & SPI_TXCTL_LEN_MASK)
3955/*! @} */
3956
3957/*! @name DIV - SPI clock Divider */
3958/*! @{ */
3959#define SPI_DIV_DIVVAL_MASK (0xFFFFU)
3960#define SPI_DIV_DIVVAL_SHIFT (0U)
3961/*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the
3962 * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1,
3963 * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results
3964 * in FCLK/65536.
3965 */
3966#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
3967/*! @} */
3968
3969/*! @name INTSTAT - SPI Interrupt Status */
3970/*! @{ */
3971#define SPI_INTSTAT_RXRDY_MASK (0x1U)
3972#define SPI_INTSTAT_RXRDY_SHIFT (0U)
3973/*! RXRDY - Receiver Ready flag.
3974 */
3975#define SPI_INTSTAT_RXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_RXRDY_SHIFT)) & SPI_INTSTAT_RXRDY_MASK)
3976#define SPI_INTSTAT_TXRDY_MASK (0x2U)
3977#define SPI_INTSTAT_TXRDY_SHIFT (1U)
3978/*! TXRDY - Transmitter Ready flag.
3979 */
3980#define SPI_INTSTAT_TXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_TXRDY_SHIFT)) & SPI_INTSTAT_TXRDY_MASK)
3981#define SPI_INTSTAT_RXOV_MASK (0x4U)
3982#define SPI_INTSTAT_RXOV_SHIFT (2U)
3983/*! RXOV - Receiver Overrun interrupt flag.
3984 */
3985#define SPI_INTSTAT_RXOV(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_RXOV_SHIFT)) & SPI_INTSTAT_RXOV_MASK)
3986#define SPI_INTSTAT_TXUR_MASK (0x8U)
3987#define SPI_INTSTAT_TXUR_SHIFT (3U)
3988/*! TXUR - Transmitter Underrun interrupt flag.
3989 */
3990#define SPI_INTSTAT_TXUR(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_TXUR_SHIFT)) & SPI_INTSTAT_TXUR_MASK)
3991#define SPI_INTSTAT_SSA_MASK (0x10U)
3992#define SPI_INTSTAT_SSA_SHIFT (4U)
3993/*! SSA - Slave Select Assert.
3994 */
3995#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
3996#define SPI_INTSTAT_SSD_MASK (0x20U)
3997#define SPI_INTSTAT_SSD_SHIFT (5U)
3998/*! SSD - Slave Select Deassert.
3999 */
4000#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
4001#define SPI_INTSTAT_MSTIDLE_MASK (0x100U)
4002#define SPI_INTSTAT_MSTIDLE_SHIFT (8U)
4003/*! MSTIDLE - Master Idle status flag.
4004 */
4005#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
4006/*! @} */
4007
4008
4009/*!
4010 * @}
4011 */ /* end of group SPI_Register_Masks */
4012
4013
4014/* SPI - Peripheral instance base addresses */
4015/** Peripheral SPI0 base address */
4016#define SPI0_BASE (0x40058000u)
4017/** Peripheral SPI0 base pointer */
4018#define SPI0 ((SPI_Type *)SPI0_BASE)
4019/** Array initializer of SPI peripheral base addresses */
4020#define SPI_BASE_ADDRS { SPI0_BASE }
4021/** Array initializer of SPI peripheral base pointers */
4022#define SPI_BASE_PTRS { SPI0 }
4023/** Interrupt vectors for the SPI peripheral type */
4024#define SPI_IRQS { SPI0_IRQn }
4025
4026/*!
4027 * @}
4028 */ /* end of group SPI_Peripheral_Access_Layer */
4029
4030
4031/* ----------------------------------------------------------------------------
4032 -- SWM Peripheral Access Layer
4033 ---------------------------------------------------------------------------- */
4034
4035/*!
4036 * @addtogroup SWM_Peripheral_Access_Layer SWM Peripheral Access Layer
4037 * @{
4038 */
4039
4040/** SWM - Register Layout Typedef */
4041typedef struct {
4042 union { /* offset: 0x0 */
4043 struct { /* offset: 0x0 */
4044 __IO uint32_t PINASSIGN0; /**< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS., offset: 0x0 */
4045 __IO uint32_t PINASSIGN1; /**< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_SCLK., offset: 0x4 */
4046 __IO uint32_t PINASSIGN2; /**< Pin assign register 2. Assign movable functions SPI0_SCK, SPI0_MOSI, SPI0_MISO, SPI0_SSEL0., offset: 0x8 */
4047 __IO uint32_t PINASSIGN3; /**< Pin assign register 3. Assign movable function SPI0_SSEL1, T0_CAP0, T0_CAP1, T0_CAP2., offset: 0xC */
4048 __IO uint32_t PINASSIGN4; /**< Pin assign register 4. Assign movable functions T0_MAT0, T0_MAT1, T0_MAT2,T0_MAT3., offset: 0x10 */
4049 __IO uint32_t PINASSIGN5; /**< Pin assign register 5. Assign movable functions I2C0_SDA, I2C0_SCL, COMP0_OUT, CLKOUT, offset: 0x14 */
4050 __IO uint32_t PINASSIGN6; /**< Pin assign register 6. Assign movable functions GPIO_INT_BMAT, LVLSHFT_IN0, LVLSHFT_IN1, LVLSHFT_OUT0., offset: 0x18 */
4051 __IO uint32_t PINASSIGN7; /**< Pin assign register 7. Assign movable functions LVLSHFT_OUT1., offset: 0x1C */
4052 } PINASSIGN;
4053 __IO uint32_t PINASSIGN_DATA[8]; /**< Pin assign register, array offset: 0x0, array step: 0x4 */
4054 };
4055 uint8_t RESERVED_0[416];
4056 __IO uint32_t PINENABLE0; /**< Pin enable register 0. Enables fixed-pin functions ACMP_I1, ACMP_I2, ACMP_I3,ACMP_I4, SWCLK, SWDIO, RESET, CLKIN, WKCLK_IN, VDDCMP, ADC_0 - ADC_11., offset: 0x1C0 */
4057} SWM_Type;
4058
4059/* ----------------------------------------------------------------------------
4060 -- SWM Register Masks
4061 ---------------------------------------------------------------------------- */
4062
4063/*!
4064 * @addtogroup SWM_Register_Masks SWM Register Masks
4065 * @{
4066 */
4067
4068/*! @name PINASSIGN0 - Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS. */
4069/*! @{ */
4070#define SWM_PINASSIGN0_U0_TXD_O_MASK (0xFFU)
4071#define SWM_PINASSIGN0_U0_TXD_O_SHIFT (0U)
4072/*! U0_TXD_O - U0_TXD function assignment. The value is the pin number to be assigned to this
4073 * function. The following pins are available: PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from
4074 * PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
4075 */
4076#define SWM_PINASSIGN0_U0_TXD_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_TXD_O_SHIFT)) & SWM_PINASSIGN0_U0_TXD_O_MASK)
4077#define SWM_PINASSIGN0_U0_RXD_I_MASK (0xFF00U)
4078#define SWM_PINASSIGN0_U0_RXD_I_SHIFT (8U)
4079/*! U0_RXD_I - U0_RXD function assignment. The value is the pin number to be assigned to this
4080 * function. The following pins are available: PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from
4081 * PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
4082 */
4083#define SWM_PINASSIGN0_U0_RXD_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_RXD_I_SHIFT)) & SWM_PINASSIGN0_U0_RXD_I_MASK)
4084#define SWM_PINASSIGN0_U0_RTS_O_MASK (0xFF0000U)
4085#define SWM_PINASSIGN0_U0_RTS_O_SHIFT (16U)
4086/*! U0_RTS_O - U0_RTS function assignment. The value is the pin number to be assigned to this
4087 * function. The following pins are available: PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from
4088 * PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
4089 */
4090#define SWM_PINASSIGN0_U0_RTS_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_RTS_O_SHIFT)) & SWM_PINASSIGN0_U0_RTS_O_MASK)
4091#define SWM_PINASSIGN0_U0_CTS_I_MASK (0xFF000000U)
4092#define SWM_PINASSIGN0_U0_CTS_I_SHIFT (24U)
4093/*! U0_CTS_I - U0_CTS function assignment. The value is the pin number to be assigned to this
4094 * function. The following pins are available: PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from
4095 * PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
4096 */
4097#define SWM_PINASSIGN0_U0_CTS_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_CTS_I_SHIFT)) & SWM_PINASSIGN0_U0_CTS_I_MASK)
4098/*! @} */
4099
4100/*! @name PINASSIGN1 - Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_SCLK. */
4101/*! @{ */
4102#define SWM_PINASSIGN1_U0_SCLK_IO_MASK (0xFFU)
4103#define SWM_PINASSIGN1_U0_SCLK_IO_SHIFT (0U)
4104/*! U0_SCLK_IO - U0_SCLK function assignment. The value is the pin number to be assigned to this
4105 * function. The following pins are available: PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and
4106 * from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
4107 */
4108#define SWM_PINASSIGN1_U0_SCLK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U0_SCLK_IO_SHIFT)) & SWM_PINASSIGN1_U0_SCLK_IO_MASK)
4109#define SWM_PINASSIGN1_U1_TXD_O_MASK (0xFF00U)
4110#define SWM_PINASSIGN1_U1_TXD_O_SHIFT (8U)
4111/*! U1_TXD_O - U1_TXD function assignment. The value is the pin number to be assigned to this
4112 * function. The following pins are available: PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from
4113 * PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
4114 */
4115#define SWM_PINASSIGN1_U1_TXD_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U1_TXD_O_SHIFT)) & SWM_PINASSIGN1_U1_TXD_O_MASK)
4116#define SWM_PINASSIGN1_U1_RXD_I_MASK (0xFF0000U)
4117#define SWM_PINASSIGN1_U1_RXD_I_SHIFT (16U)
4118/*! U1_RXD_I - U1_RXD function assignment. The value is the pin number to be assigned to this
4119 * function. The following pins are available: PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from
4120 * PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
4121 */
4122#define SWM_PINASSIGN1_U1_RXD_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U1_RXD_I_SHIFT)) & SWM_PINASSIGN1_U1_RXD_I_MASK)
4123#define SWM_PINASSIGN1_U1_SCLK_IO_MASK (0xFF000000U)
4124#define SWM_PINASSIGN1_U1_SCLK_IO_SHIFT (24U)
4125/*! U1_SCLK_IO - U1_SCLK function assignment. The value is the pin number to be assigned to this
4126 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
4127 * 0x7) to PIO0_17 (= 0x11).
4128 */
4129#define SWM_PINASSIGN1_U1_SCLK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U1_SCLK_IO_SHIFT)) & SWM_PINASSIGN1_U1_SCLK_IO_MASK)
4130/*! @} */
4131
4132/*! @name PINASSIGN2 - Pin assign register 2. Assign movable functions SPI0_SCK, SPI0_MOSI, SPI0_MISO, SPI0_SSEL0. */
4133/*! @{ */
4134#define SWM_PINASSIGN2_SPI0_SCK_IO_MASK (0xFFU)
4135#define SWM_PINASSIGN2_SPI0_SCK_IO_SHIFT (0U)
4136/*! SPI0_SCK_IO - SPI0_SCK function assignment. The value is the pin number to be assigned to this
4137 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
4138 * 0x7) to PIO0_17 (= 0x11).
4139 */
4140#define SWM_PINASSIGN2_SPI0_SCK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_SPI0_SCK_IO_SHIFT)) & SWM_PINASSIGN2_SPI0_SCK_IO_MASK)
4141#define SWM_PINASSIGN2_SPI0_MOSI_IO_MASK (0xFF00U)
4142#define SWM_PINASSIGN2_SPI0_MOSI_IO_SHIFT (8U)
4143/*! SPI0_MOSI_IO - SPI0_MOSI function assignment. The value is the pin number to be assigned to this
4144 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
4145 * 0x7) to PIO0_17 (= 0x11).
4146 */
4147#define SWM_PINASSIGN2_SPI0_MOSI_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_SPI0_MOSI_IO_SHIFT)) & SWM_PINASSIGN2_SPI0_MOSI_IO_MASK)
4148#define SWM_PINASSIGN2_SPI0_MISO_IO_MASK (0xFF0000U)
4149#define SWM_PINASSIGN2_SPI0_MISO_IO_SHIFT (16U)
4150/*! SPI0_MISO_IO - SPI0_MISO function assignment. The value is the pin number to be assigned to this
4151 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
4152 * 0x7) to PIO0_17 (= 0x11).
4153 */
4154#define SWM_PINASSIGN2_SPI0_MISO_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_SPI0_MISO_IO_SHIFT)) & SWM_PINASSIGN2_SPI0_MISO_IO_MASK)
4155#define SWM_PINASSIGN2_SPI0_SSEL0_IO_MASK (0xFF000000U)
4156#define SWM_PINASSIGN2_SPI0_SSEL0_IO_SHIFT (24U)
4157/*! SPI0_SSEL0_IO - SPI0_SSEL0 function assignment. The value is the pin number to be assigned to
4158 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7
4159 * (= 0x7) to PIO0_17 (= 0x11).
4160 */
4161#define SWM_PINASSIGN2_SPI0_SSEL0_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_SPI0_SSEL0_IO_SHIFT)) & SWM_PINASSIGN2_SPI0_SSEL0_IO_MASK)
4162/*! @} */
4163
4164/*! @name PINASSIGN3 - Pin assign register 3. Assign movable function SPI0_SSEL1, T0_CAP0, T0_CAP1, T0_CAP2. */
4165/*! @{ */
4166#define SWM_PINASSIGN3_SPI0_SSEL1_IO_MASK (0xFFU)
4167#define SWM_PINASSIGN3_SPI0_SSEL1_IO_SHIFT (0U)
4168/*! SPI0_SSEL1_IO - SPI0_SSEL1 function assignment. The value is the pin number to be assigned to
4169 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7
4170 * (= 0x7) to PIO0_17 (= 0x11).
4171 */
4172#define SWM_PINASSIGN3_SPI0_SSEL1_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_SPI0_SSEL1_IO_SHIFT)) & SWM_PINASSIGN3_SPI0_SSEL1_IO_MASK)
4173#define SWM_PINASSIGN3_T0_CAP0_MASK (0xFF00U)
4174#define SWM_PINASSIGN3_T0_CAP0_SHIFT (8U)
4175/*! T0_CAP0 - T0_CAP0 function assignment. The value is the pin number to be assigned to this
4176 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7)
4177 * to PIO0_17 (= 0x11).
4178 */
4179#define SWM_PINASSIGN3_T0_CAP0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_T0_CAP0_SHIFT)) & SWM_PINASSIGN3_T0_CAP0_MASK)
4180#define SWM_PINASSIGN3_T0_CAP1_MASK (0xFF0000U)
4181#define SWM_PINASSIGN3_T0_CAP1_SHIFT (16U)
4182/*! T0_CAP1 - T0_CAP1 function assignment. The value is the pin number to be assigned to this
4183 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7)
4184 * to PIO0_17 (= 0x11).
4185 */
4186#define SWM_PINASSIGN3_T0_CAP1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_T0_CAP1_SHIFT)) & SWM_PINASSIGN3_T0_CAP1_MASK)
4187#define SWM_PINASSIGN3_T0_CAP2_MASK (0xFF000000U)
4188#define SWM_PINASSIGN3_T0_CAP2_SHIFT (24U)
4189/*! T0_CAP2 - T0_CAP2 function assignment. The value is the pin number to be assigned to this
4190 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7)
4191 * to PIO0_17 (= 0x11).
4192 */
4193#define SWM_PINASSIGN3_T0_CAP2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_T0_CAP2_SHIFT)) & SWM_PINASSIGN3_T0_CAP2_MASK)
4194/*! @} */
4195
4196/*! @name PINASSIGN4 - Pin assign register 4. Assign movable functions T0_MAT0, T0_MAT1, T0_MAT2,T0_MAT3. */
4197/*! @{ */
4198#define SWM_PINASSIGN4_T0_MAT0_MASK (0xFFU)
4199#define SWM_PINASSIGN4_T0_MAT0_SHIFT (0U)
4200/*! T0_MAT0 - T0_MAT0 function assignment. The value is the pin number to be assigned to this
4201 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7)
4202 * to PIO0_17 (= 0x11).
4203 */
4204#define SWM_PINASSIGN4_T0_MAT0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_T0_MAT0_SHIFT)) & SWM_PINASSIGN4_T0_MAT0_MASK)
4205#define SWM_PINASSIGN4_T0_MAT1_MASK (0xFF00U)
4206#define SWM_PINASSIGN4_T0_MAT1_SHIFT (8U)
4207/*! T0_MAT1 - T0_MAT1 function assignment. The value is the pin number to be assigned to this
4208 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7)
4209 * to PIO0_17 (= 0x11).
4210 */
4211#define SWM_PINASSIGN4_T0_MAT1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_T0_MAT1_SHIFT)) & SWM_PINASSIGN4_T0_MAT1_MASK)
4212#define SWM_PINASSIGN4_T0_MAT2_MASK (0xFF0000U)
4213#define SWM_PINASSIGN4_T0_MAT2_SHIFT (16U)
4214/*! T0_MAT2 - T0_MAT2 function assignment. The value is the pin number to be assigned to this
4215 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7)
4216 * to PIO0_17 (= 0x11).
4217 */
4218#define SWM_PINASSIGN4_T0_MAT2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_T0_MAT2_SHIFT)) & SWM_PINASSIGN4_T0_MAT2_MASK)
4219#define SWM_PINASSIGN4_T0_MAT3_MASK (0xFF000000U)
4220#define SWM_PINASSIGN4_T0_MAT3_SHIFT (24U)
4221/*! T0_MAT3 - T0_MAT3 function assignment. The value is the pin number to be assigned to this
4222 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7)
4223 * to PIO0_17 (= 0x11).
4224 */
4225#define SWM_PINASSIGN4_T0_MAT3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_T0_MAT3_SHIFT)) & SWM_PINASSIGN4_T0_MAT3_MASK)
4226/*! @} */
4227
4228/*! @name PINASSIGN5 - Pin assign register 5. Assign movable functions I2C0_SDA, I2C0_SCL, COMP0_OUT, CLKOUT */
4229/*! @{ */
4230#define SWM_PINASSIGN5_I2C0_SDA_IO_MASK (0xFFU)
4231#define SWM_PINASSIGN5_I2C0_SDA_IO_SHIFT (0U)
4232/*! I2C0_SDA_IO - I2C0_SDA function assignment. The value is the pin number to be assigned to this
4233 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
4234 * 0x7) to PIO0_17 (= 0x11).
4235 */
4236#define SWM_PINASSIGN5_I2C0_SDA_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_I2C0_SDA_IO_SHIFT)) & SWM_PINASSIGN5_I2C0_SDA_IO_MASK)
4237#define SWM_PINASSIGN5_I2C0_SCL_IO_MASK (0xFF00U)
4238#define SWM_PINASSIGN5_I2C0_SCL_IO_SHIFT (8U)
4239/*! I2C0_SCL_IO - I2C0_SCL function assignment. The value is the pin number to be assigned to this
4240 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
4241 * 0x7) to PIO0_17 (= 0x11).
4242 */
4243#define SWM_PINASSIGN5_I2C0_SCL_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_I2C0_SCL_IO_SHIFT)) & SWM_PINASSIGN5_I2C0_SCL_IO_MASK)
4244#define SWM_PINASSIGN5_COMP0_OUT_O_MASK (0xFF0000U)
4245#define SWM_PINASSIGN5_COMP0_OUT_O_SHIFT (16U)
4246/*! COMP0_OUT_O - COMP0_OUT function assignment. The value is the pin number to be assigned to this
4247 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
4248 * 0x7) to PIO0_17 (= 0x11).
4249 */
4250#define SWM_PINASSIGN5_COMP0_OUT_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_COMP0_OUT_O_SHIFT)) & SWM_PINASSIGN5_COMP0_OUT_O_MASK)
4251#define SWM_PINASSIGN5_CLKOUT_O_MASK (0xFF000000U)
4252#define SWM_PINASSIGN5_CLKOUT_O_SHIFT (24U)
4253/*! CLKOUT_O - CLKOUT function assignment. The value is the pin number to be assigned to this
4254 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7)
4255 * to PIO0_17 (= 0x11).
4256 */
4257#define SWM_PINASSIGN5_CLKOUT_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_CLKOUT_O_SHIFT)) & SWM_PINASSIGN5_CLKOUT_O_MASK)
4258/*! @} */
4259
4260/*! @name PINASSIGN6 - Pin assign register 6. Assign movable functions GPIO_INT_BMAT, LVLSHFT_IN0, LVLSHFT_IN1, LVLSHFT_OUT0. */
4261/*! @{ */
4262#define SWM_PINASSIGN6_GPIO_INT_BMAT_O_MASK (0xFFU)
4263#define SWM_PINASSIGN6_GPIO_INT_BMAT_O_SHIFT (0U)
4264/*! GPIO_INT_BMAT_O - GPIO_INT_BMAT function assignment. The value is the pin number to be assigned
4265 * to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from
4266 * PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
4267 */
4268#define SWM_PINASSIGN6_GPIO_INT_BMAT_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_GPIO_INT_BMAT_O_SHIFT)) & SWM_PINASSIGN6_GPIO_INT_BMAT_O_MASK)
4269#define SWM_PINASSIGN6_LVLSHFT_IN0_MASK (0xFF00U)
4270#define SWM_PINASSIGN6_LVLSHFT_IN0_SHIFT (8U)
4271/*! LVLSHFT_IN0 - LVLSHFT_IN0 function assignment. The value is the pin number to be assigned to
4272 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7
4273 * (= 0x7) to PIO0_17 (= 0x11).
4274 */
4275#define SWM_PINASSIGN6_LVLSHFT_IN0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_LVLSHFT_IN0_SHIFT)) & SWM_PINASSIGN6_LVLSHFT_IN0_MASK)
4276#define SWM_PINASSIGN6_LVLSHFT_IN1_MASK (0xFF0000U)
4277#define SWM_PINASSIGN6_LVLSHFT_IN1_SHIFT (16U)
4278/*! LVLSHFT_IN1 - LVLSHFT_IN1 function assignment. The value is the pin number to be assigned to
4279 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7
4280 * (= 0x7) to PIO0_17 (= 0x11).
4281 */
4282#define SWM_PINASSIGN6_LVLSHFT_IN1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_LVLSHFT_IN1_SHIFT)) & SWM_PINASSIGN6_LVLSHFT_IN1_MASK)
4283#define SWM_PINASSIGN6_LVLSHFT_OUT0_MASK (0xFF000000U)
4284#define SWM_PINASSIGN6_LVLSHFT_OUT0_SHIFT (24U)
4285/*! LVLSHFT_OUT0 - LVLSHFT_OUT0 function assignment. The value is the pin number to be assigned to
4286 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7
4287 * (= 0x7) to PIO0_17 (= 0x11).
4288 */
4289#define SWM_PINASSIGN6_LVLSHFT_OUT0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_LVLSHFT_OUT0_SHIFT)) & SWM_PINASSIGN6_LVLSHFT_OUT0_MASK)
4290/*! @} */
4291
4292/*! @name PINASSIGN7 - Pin assign register 7. Assign movable functions LVLSHFT_OUT1. */
4293/*! @{ */
4294#define SWM_PINASSIGN7_LVLSHFT_OUT1_MASK (0xFFU)
4295#define SWM_PINASSIGN7_LVLSHFT_OUT1_SHIFT (0U)
4296/*! LVLSHFT_OUT1 - LVLSHFT_OUT1 function assignment. The value is the pin number to be assigned to
4297 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7
4298 * (= 0x7) to PIO0_17 (= 0x11).
4299 */
4300#define SWM_PINASSIGN7_LVLSHFT_OUT1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN7_LVLSHFT_OUT1_SHIFT)) & SWM_PINASSIGN7_LVLSHFT_OUT1_MASK)
4301/*! @} */
4302
4303/*! @name PINASSIGN_DATA - Pin assign register */
4304/*! @{ */
4305#define SWM_PINASSIGN_DATA_DATA0_MASK (0xFFU)
4306#define SWM_PINASSIGN_DATA_DATA0_SHIFT (0U)
4307/*! DATA0 - T0_MAT3 function assignment. The value is the pin number to be assigned to this
4308 * function. The following pins are available: PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from
4309 * PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
4310 */
4311#define SWM_PINASSIGN_DATA_DATA0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_DATA0_SHIFT)) & SWM_PINASSIGN_DATA_DATA0_MASK)
4312#define SWM_PINASSIGN_DATA_DATA1_MASK (0xFF00U)
4313#define SWM_PINASSIGN_DATA_DATA1_SHIFT (8U)
4314/*! DATA1 - T0_CAP0 function assignment. The value is the pin number to be assigned to this
4315 * function. The following pins are available: PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from
4316 * PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
4317 */
4318#define SWM_PINASSIGN_DATA_DATA1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_DATA1_SHIFT)) & SWM_PINASSIGN_DATA_DATA1_MASK)
4319#define SWM_PINASSIGN_DATA_DATA2_MASK (0xFF0000U)
4320#define SWM_PINASSIGN_DATA_DATA2_SHIFT (16U)
4321/*! DATA2 - T0_CAP1 function assignment. The value is the pin number to be assigned to this
4322 * function. The following pins are available: PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from
4323 * PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
4324 */
4325#define SWM_PINASSIGN_DATA_DATA2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_DATA2_SHIFT)) & SWM_PINASSIGN_DATA_DATA2_MASK)
4326#define SWM_PINASSIGN_DATA_DATA3_MASK (0xFF000000U)
4327#define SWM_PINASSIGN_DATA_DATA3_SHIFT (24U)
4328/*! DATA3 - T0_CAP2 function assignment. The value is the pin number to be assigned to this
4329 * function. The following pins are available: PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from
4330 * PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
4331 */
4332#define SWM_PINASSIGN_DATA_DATA3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_DATA3_SHIFT)) & SWM_PINASSIGN_DATA_DATA3_MASK)
4333/*! @} */
4334
4335/* The count of SWM_PINASSIGN_DATA */
4336#define SWM_PINASSIGN_DATA_COUNT (8U)
4337
4338/*! @name PINENABLE0 - Pin enable register 0. Enables fixed-pin functions ACMP_I1, ACMP_I2, ACMP_I3,ACMP_I4, SWCLK, SWDIO, RESET, CLKIN, WKCLK_IN, VDDCMP, ADC_0 - ADC_11. */
4339/*! @{ */
4340#define SWM_PINENABLE0_ACMP_I1_MASK (0x1U)
4341#define SWM_PINENABLE0_ACMP_I1_SHIFT (0U)
4342/*! ACMP_I1 - ACMP_I1 function select.
4343 * 0b0..ACMP_I1 enabled on pin PIO0_00.
4344 * 0b1..ACMP_I1 disabled.
4345 */
4346#define SWM_PINENABLE0_ACMP_I1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I1_SHIFT)) & SWM_PINENABLE0_ACMP_I1_MASK)
4347#define SWM_PINENABLE0_ACMP_I2_MASK (0x2U)
4348#define SWM_PINENABLE0_ACMP_I2_SHIFT (1U)
4349/*! ACMP_I2 - ACMP_I2 function select.
4350 * 0b0..ACMP_I2 enabled on pin PIO0_1.
4351 * 0b1..ACMP_I2 disabled.
4352 */
4353#define SWM_PINENABLE0_ACMP_I2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I2_SHIFT)) & SWM_PINENABLE0_ACMP_I2_MASK)
4354#define SWM_PINENABLE0_ACMP_I3_MASK (0x4U)
4355#define SWM_PINENABLE0_ACMP_I3_SHIFT (2U)
4356/*! ACMP_I3 - ACMP_I3 function select.
4357 * 0b0..ACMP_I3 enabled on pin PIO0_14.
4358 * 0b1..ACMP_I3 disabled.
4359 */
4360#define SWM_PINENABLE0_ACMP_I3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I3_SHIFT)) & SWM_PINENABLE0_ACMP_I3_MASK)
4361#define SWM_PINENABLE0_ACMP_I4_MASK (0x8U)
4362#define SWM_PINENABLE0_ACMP_I4_SHIFT (3U)
4363/*! ACMP_I4 - ACMP_I4 function select.
4364 * 0b0..ACMP_I4 enabled on pin PIO0_16.
4365 * 0b1..ACMP_I4 disabled.
4366 */
4367#define SWM_PINENABLE0_ACMP_I4(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I4_SHIFT)) & SWM_PINENABLE0_ACMP_I4_MASK)
4368#define SWM_PINENABLE0_SWCLK_MASK (0x10U)
4369#define SWM_PINENABLE0_SWCLK_SHIFT (4U)
4370/*! SWCLK - SWCLK function select.
4371 * 0b0..SWCLK enabled on pin PIO0_3.
4372 * 0b1..SWCLK disabled.
4373 */
4374#define SWM_PINENABLE0_SWCLK(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_SWCLK_SHIFT)) & SWM_PINENABLE0_SWCLK_MASK)
4375#define SWM_PINENABLE0_SWDIO_MASK (0x20U)
4376#define SWM_PINENABLE0_SWDIO_SHIFT (5U)
4377/*! SWDIO - SWDIO function select.
4378 * 0b0..SWDIO enabled on pin PIO0_2.
4379 * 0b1..SWDIO disabled.
4380 */
4381#define SWM_PINENABLE0_SWDIO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_SWDIO_SHIFT)) & SWM_PINENABLE0_SWDIO_MASK)
4382#define SWM_PINENABLE0_RESETN_MASK (0x40U)
4383#define SWM_PINENABLE0_RESETN_SHIFT (6U)
4384/*! RESETN - RESETN function select.
4385 * 0b0..RESETN enabled on pin PIO0_5.
4386 * 0b1..RESETN disabled.
4387 */
4388#define SWM_PINENABLE0_RESETN(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_RESETN_SHIFT)) & SWM_PINENABLE0_RESETN_MASK)
4389#define SWM_PINENABLE0_CLKIN_MASK (0x80U)
4390#define SWM_PINENABLE0_CLKIN_SHIFT (7U)
4391/*! CLKIN - CLKIN function select.
4392 * 0b0..CLKIN enabled on pin PIO0_1.
4393 * 0b1..CLKIN disabled.
4394 */
4395#define SWM_PINENABLE0_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_CLKIN_SHIFT)) & SWM_PINENABLE0_CLKIN_MASK)
4396#define SWM_PINENABLE0_WKCLKIN_MASK (0x100U)
4397#define SWM_PINENABLE0_WKCLKIN_SHIFT (8U)
4398/*! WKCLKIN - WKCLK_IN function select.
4399 * 0b0..WKCLK_IN enabled on pin PIO0_11.
4400 * 0b1..WKCLK_IN disabled.
4401 */
4402#define SWM_PINENABLE0_WKCLKIN(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_WKCLKIN_SHIFT)) & SWM_PINENABLE0_WKCLKIN_MASK)
4403#define SWM_PINENABLE0_VDDCMP_MASK (0x200U)
4404#define SWM_PINENABLE0_VDDCMP_SHIFT (9U)
4405/*! VDDCMP - VDDCMP function select.
4406 * 0b0..VDDCMP enabled on pin PIO0_6.
4407 * 0b1..VDDCMP disabled.
4408 */
4409#define SWM_PINENABLE0_VDDCMP(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_VDDCMP_SHIFT)) & SWM_PINENABLE0_VDDCMP_MASK)
4410#define SWM_PINENABLE0_ADC_0_MASK (0x400U)
4411#define SWM_PINENABLE0_ADC_0_SHIFT (10U)
4412/*! ADC_0 - ADC_0 function select.
4413 * 0b0..ADC_0 enabled on pin PIO0_1.
4414 * 0b1..ADC_0 disabled.
4415 */
4416#define SWM_PINENABLE0_ADC_0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_0_SHIFT)) & SWM_PINENABLE0_ADC_0_MASK)
4417#define SWM_PINENABLE0_ADC_1_MASK (0x800U)
4418#define SWM_PINENABLE0_ADC_1_SHIFT (11U)
4419/*! ADC_1 - ADC_1 function select.
4420 * 0b0..ADC_1 enabled on pin PIO0_7.
4421 * 0b1..ADC_1 disabled.
4422 */
4423#define SWM_PINENABLE0_ADC_1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_1_SHIFT)) & SWM_PINENABLE0_ADC_1_MASK)
4424#define SWM_PINENABLE0_ADC_2_MASK (0x1000U)
4425#define SWM_PINENABLE0_ADC_2_SHIFT (12U)
4426/*! ADC_2 - ADC_2 function select.
4427 * 0b0..ADC_2 enabled on pin PIO0_14.
4428 * 0b1..ADC_2 disabled.
4429 */
4430#define SWM_PINENABLE0_ADC_2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_2_SHIFT)) & SWM_PINENABLE0_ADC_2_MASK)
4431#define SWM_PINENABLE0_ADC_3_MASK (0x2000U)
4432#define SWM_PINENABLE0_ADC_3_SHIFT (13U)
4433/*! ADC_3 - ADC_3 function select.
4434 * 0b0..ADC_3 enabled on pin PIO0_16.
4435 * 0b1..ADC_3 disabled.
4436 */
4437#define SWM_PINENABLE0_ADC_3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_3_SHIFT)) & SWM_PINENABLE0_ADC_3_MASK)
4438#define SWM_PINENABLE0_ADC_4_MASK (0x4000U)
4439#define SWM_PINENABLE0_ADC_4_SHIFT (14U)
4440/*! ADC_4 - ADC_4 function select.
4441 * 0b0..ADC_4 enabled on pin PIO0_9.
4442 * 0b1..ADC_4 disabled.
4443 */
4444#define SWM_PINENABLE0_ADC_4(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_4_SHIFT)) & SWM_PINENABLE0_ADC_4_MASK)
4445#define SWM_PINENABLE0_ADC_5_MASK (0x8000U)
4446#define SWM_PINENABLE0_ADC_5_SHIFT (15U)
4447/*! ADC_5 - ADC_5 function select.
4448 * 0b0..ADC_5 enabled on pin PIO0_8.
4449 * 0b1..ADC_5 disabled.
4450 */
4451#define SWM_PINENABLE0_ADC_5(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_5_SHIFT)) & SWM_PINENABLE0_ADC_5_MASK)
4452#define SWM_PINENABLE0_ADC_6_MASK (0x10000U)
4453#define SWM_PINENABLE0_ADC_6_SHIFT (16U)
4454/*! ADC_6 - ADC_6 function select.
4455 * 0b0..ADC_6 enabled on pin PIO0_11.
4456 * 0b1..ADC_6 disabled.
4457 */
4458#define SWM_PINENABLE0_ADC_6(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_6_SHIFT)) & SWM_PINENABLE0_ADC_6_MASK)
4459#define SWM_PINENABLE0_ADC_7_MASK (0x20000U)
4460#define SWM_PINENABLE0_ADC_7_SHIFT (17U)
4461/*! ADC_7 - ADC_7 function select.
4462 * 0b0..ADC_7 enabled on pin PIO0_10.
4463 * 0b1..ADC_7 disabled.
4464 */
4465#define SWM_PINENABLE0_ADC_7(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_7_SHIFT)) & SWM_PINENABLE0_ADC_7_MASK)
4466#define SWM_PINENABLE0_ADC_8_MASK (0x40000U)
4467#define SWM_PINENABLE0_ADC_8_SHIFT (18U)
4468/*! ADC_8 - ADC_8 function select.
4469 * 0b0..ADC_8 enabled on pin PIO0_15.
4470 * 0b1..ADC_8 disabled.
4471 */
4472#define SWM_PINENABLE0_ADC_8(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_8_SHIFT)) & SWM_PINENABLE0_ADC_8_MASK)
4473#define SWM_PINENABLE0_ADC_9_MASK (0x80000U)
4474#define SWM_PINENABLE0_ADC_9_SHIFT (19U)
4475/*! ADC_9 - ADC_9 function select.
4476 * 0b0..ADC_9 enabled on pin PIO0_17.
4477 * 0b1..ADC_9 disabled.
4478 */
4479#define SWM_PINENABLE0_ADC_9(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_9_SHIFT)) & SWM_PINENABLE0_ADC_9_MASK)
4480#define SWM_PINENABLE0_ADC_10_MASK (0x100000U)
4481#define SWM_PINENABLE0_ADC_10_SHIFT (20U)
4482/*! ADC_10 - ADC_10 function select.
4483 * 0b0..ADC_10 enabled on pin PIO0_13.
4484 * 0b1..ADC_10 disabled.
4485 */
4486#define SWM_PINENABLE0_ADC_10(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_10_SHIFT)) & SWM_PINENABLE0_ADC_10_MASK)
4487#define SWM_PINENABLE0_ADC_11_MASK (0x200000U)
4488#define SWM_PINENABLE0_ADC_11_SHIFT (21U)
4489/*! ADC_11 - ADC_11 function select.
4490 * 0b0..ADC_11 enabled on pin PIO0_4.
4491 * 0b1..ADC_11 disabled.
4492 */
4493#define SWM_PINENABLE0_ADC_11(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_11_SHIFT)) & SWM_PINENABLE0_ADC_11_MASK)
4494/*! @} */
4495
4496
4497/*!
4498 * @}
4499 */ /* end of group SWM_Register_Masks */
4500
4501
4502/* SWM - Peripheral instance base addresses */
4503/** Peripheral SWM0 base address */
4504#define SWM0_BASE (0x4000C000u)
4505/** Peripheral SWM0 base pointer */
4506#define SWM0 ((SWM_Type *)SWM0_BASE)
4507/** Array initializer of SWM peripheral base addresses */
4508#define SWM_BASE_ADDRS { SWM0_BASE }
4509/** Array initializer of SWM peripheral base pointers */
4510#define SWM_BASE_PTRS { SWM0 }
4511
4512/*!
4513 * @}
4514 */ /* end of group SWM_Peripheral_Access_Layer */
4515
4516
4517/* ----------------------------------------------------------------------------
4518 -- SYSCON Peripheral Access Layer
4519 ---------------------------------------------------------------------------- */
4520
4521/*!
4522 * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
4523 * @{
4524 */
4525
4526/** SYSCON - Register Layout Typedef */
4527typedef struct {
4528 __IO uint32_t SYSMEMREMAP; /**< System Remap register, offset: 0x0 */
4529 uint8_t RESERVED_0[52];
4530 __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x38 */
4531 uint8_t RESERVED_1[20];
4532 __IO uint32_t MAINCLKSEL; /**< Main clock source select register, offset: 0x50 */
4533 __IO uint32_t MAINCLKUEN; /**< Main clock source update enable register, offset: 0x54 */
4534 __IO uint32_t SYSAHBCLKDIV; /**< System clock divider register, offset: 0x58 */
4535 uint8_t RESERVED_2[8];
4536 __IO uint32_t ADCCLKSEL; /**< ADC clock source select register, offset: 0x64 */
4537 __IO uint32_t ADCCLKDIV; /**< ADC clock divider register, offset: 0x68 */
4538 uint8_t RESERVED_3[16];
4539 __IO uint32_t LPOSCCLKEN; /**< External clock source select register, offset: 0x7C */
4540 __IO uint32_t SYSAHBCLKCTRL0; /**< System clock group 0 control register, offset: 0x80 */
4541 uint8_t RESERVED_4[4];
4542 __IO uint32_t PRESETCTRL0; /**< Peripheral reset group 0 control register, offset: 0x88 */
4543 __IO uint32_t PRESETCTRL1; /**< Peripheral reset group 1 control register, offset: 0x8C */
4544 __IO uint32_t UART0CLKSEL; /**< UART0 clock source, offset: 0x90 */
4545 __IO uint32_t UART1CLKSEL; /**< UART1 clock source, offset: 0x94 */
4546 uint8_t RESERVED_5[12];
4547 __IO uint32_t I2C0CLKSEL; /**< I2C0 clock source, offset: 0xA4 */
4548 uint8_t RESERVED_6[12];
4549 __IO uint32_t SPI0CLKSEL; /**< SPI0 clock source, offset: 0xB4 */
4550 uint8_t RESERVED_7[24];
4551 struct { /* offset: 0xD0, array step: 0xC */
4552 __IO uint32_t FRGDIV; /**< fractional generator N divider value register, array offset: 0xD0, array step: 0xC */
4553 __IO uint32_t FRGMULT; /**< fractional generator N multiplier value register, array offset: 0xD4, array step: 0xC */
4554 __IO uint32_t FRGCLKSEL; /**< FRG N clock source select register, array offset: 0xD8, array step: 0xC */
4555 } FRG[1];
4556 uint8_t RESERVED_8[20];
4557 __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select register, offset: 0xF0 */
4558 __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider registers, offset: 0xF4 */
4559 uint8_t RESERVED_9[8];
4560 __I uint32_t PIOPORCAP[1]; /**< POR captured PIO N status register(PIO0 has 32 PIOs, PIO1 has 22 PIOs), array offset: 0x100, array step: 0x4 */
4561 uint8_t RESERVED_10[76];
4562 __IO uint32_t BODCTRL; /**< BOD control register, offset: 0x150 */
4563 __IO uint32_t SYSTCKCAL; /**< System tick timer calibration register, offset: 0x154 */
4564 uint8_t RESERVED_11[24];
4565 __IO uint32_t IRQLATENCY; /**< IRQ latency register, offset: 0x170 */
4566 __IO uint32_t NMISRC; /**< NMI source selection register, offset: 0x174 */
4567 __IO uint32_t PINTSEL[8]; /**< Pin interrupt select registers N, array offset: 0x178, array step: 0x4 */
4568 uint8_t RESERVED_12[108];
4569 __IO uint32_t STARTERP0; /**< Start logic 0 pin wake-up enable register 0, offset: 0x204 */
4570 uint8_t RESERVED_13[12];
4571 __IO uint32_t STARTERP1; /**< Start logic 0 pin wake-up enable register 1, offset: 0x214 */
4572 uint8_t RESERVED_14[24];
4573 __IO uint32_t PDSLEEPCFG; /**< Deep-sleep configuration register, offset: 0x230 */
4574 __IO uint32_t PDAWAKECFG; /**< Wake-up configuration register, offset: 0x234 */
4575 __IO uint32_t PDRUNCFG; /**< Power configuration register, offset: 0x238 */
4576 uint8_t RESERVED_15[444];
4577 __I uint32_t DEVICE_ID; /**< Part ID register, offset: 0x3F8 */
4578} SYSCON_Type;
4579
4580/* ----------------------------------------------------------------------------
4581 -- SYSCON Register Masks
4582 ---------------------------------------------------------------------------- */
4583
4584/*!
4585 * @addtogroup SYSCON_Register_Masks SYSCON Register Masks
4586 * @{
4587 */
4588
4589/*! @name SYSMEMREMAP - System Remap register */
4590/*! @{ */
4591#define SYSCON_SYSMEMREMAP_MAP_MASK (0x3U)
4592#define SYSCON_SYSMEMREMAP_MAP_SHIFT (0U)
4593/*! MAP - System memory remap. Value 0x3 is reserved.
4594 * 0b00..Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
4595 * 0b01..User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
4596 * 0b10..User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
4597 */
4598#define SYSCON_SYSMEMREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSMEMREMAP_MAP_SHIFT)) & SYSCON_SYSMEMREMAP_MAP_MASK)
4599/*! @} */
4600
4601/*! @name SYSRSTSTAT - System reset status register */
4602/*! @{ */
4603#define SYSCON_SYSRSTSTAT_POR_BOD_MASK (0x1U)
4604#define SYSCON_SYSRSTSTAT_POR_BOD_SHIFT (0U)
4605/*! POR_BOD - POR reset status
4606 * 0b0..No POR detected
4607 * 0b1..POR detected. Writing a one clears this reset.
4608 */
4609#define SYSCON_SYSRSTSTAT_POR_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_POR_BOD_MASK)
4610#define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U)
4611#define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U)
4612/*! EXTRST - Status of the external RESET pin. External reset status.
4613 * 0b0..No reset event detected.
4614 * 0b1..Reset detected. Writing a one clears this reset.
4615 */
4616#define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK)
4617#define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U)
4618#define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U)
4619/*! WDT - Status of the Watchdog reset
4620 * 0b0..No WDT reset detected
4621 * 0b1..WDT reset detected. Writing a one clears this reset.
4622 */
4623#define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK)
4624#define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U)
4625#define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U)
4626/*! SYSRST - Status of the software system reset
4627 * 0b0..No System reset detected
4628 * 0b1..System reset detected. Writing a one clears this reset.
4629 */
4630#define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK)
4631/*! @} */
4632
4633/*! @name MAINCLKSEL - Main clock source select register */
4634/*! @{ */
4635#define SYSCON_MAINCLKSEL_SEL_MASK (0x3U)
4636#define SYSCON_MAINCLKSEL_SEL_SHIFT (0U)
4637/*! SEL - Main clock source
4638 * 0b00..FRO
4639 * 0b01..External clock
4640 * 0b10..LowPower Oscillator
4641 * 0b11..FRO_DIV
4642 */
4643#define SYSCON_MAINCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSEL_SEL_SHIFT)) & SYSCON_MAINCLKSEL_SEL_MASK)
4644/*! @} */
4645
4646/*! @name MAINCLKUEN - Main clock source update enable register */
4647/*! @{ */
4648#define SYSCON_MAINCLKUEN_ENA_MASK (0x1U)
4649#define SYSCON_MAINCLKUEN_ENA_SHIFT (0U)
4650/*! ENA - Enable main clock source update
4651 * 0b0..no change
4652 * 0b1..update clock source
4653 */
4654#define SYSCON_MAINCLKUEN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKUEN_ENA_SHIFT)) & SYSCON_MAINCLKUEN_ENA_MASK)
4655/*! @} */
4656
4657/*! @name SYSAHBCLKDIV - System clock divider register */
4658/*! @{ */
4659#define SYSCON_SYSAHBCLKDIV_DIV_MASK (0xFFU)
4660#define SYSCON_SYSAHBCLKDIV_DIV_SHIFT (0U)
4661/*! DIV - System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.
4662 */
4663#define SYSCON_SYSAHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKDIV_DIV_SHIFT)) & SYSCON_SYSAHBCLKDIV_DIV_MASK)
4664/*! @} */
4665
4666/*! @name ADCCLKSEL - ADC clock source select register */
4667/*! @{ */
4668#define SYSCON_ADCCLKSEL_SEL_MASK (0x3U)
4669#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U)
4670/*! SEL - Clock source for ADC clock
4671 * 0b00..FRO
4672 * 0b01..clk_in
4673 * 0b10..none
4674 * 0b11..none
4675 */
4676#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK)
4677/*! @} */
4678
4679/*! @name ADCCLKDIV - ADC clock divider register */
4680/*! @{ */
4681#define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU)
4682#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U)
4683/*! DIV - ADC clock divider values 0: ADC clock disabled. 1: Divide by 1. to 255: Divide by 255.
4684 */
4685#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK)
4686/*! @} */
4687
4688/*! @name LPOSCCLKEN - External clock source select register */
4689/*! @{ */
4690#define SYSCON_LPOSCCLKEN_WDT_MASK (0x1U)
4691#define SYSCON_LPOSCCLKEN_WDT_SHIFT (0U)
4692/*! WDT - Enables clock for WDT
4693 * 0b0..System oscillator
4694 * 0b1..Clk_in
4695 */
4696#define SYSCON_LPOSCCLKEN_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPOSCCLKEN_WDT_SHIFT)) & SYSCON_LPOSCCLKEN_WDT_MASK)
4697#define SYSCON_LPOSCCLKEN_WKT_MASK (0x2U)
4698#define SYSCON_LPOSCCLKEN_WKT_SHIFT (1U)
4699/*! WKT - Enables clock for Wake Timer
4700 */
4701#define SYSCON_LPOSCCLKEN_WKT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPOSCCLKEN_WKT_SHIFT)) & SYSCON_LPOSCCLKEN_WKT_MASK)
4702/*! @} */
4703
4704/*! @name SYSAHBCLKCTRL0 - System clock group 0 control register */
4705/*! @{ */
4706#define SYSCON_SYSAHBCLKCTRL0_SYS_MASK (0x1U)
4707#define SYSCON_SYSAHBCLKCTRL0_SYS_SHIFT (0U)
4708/*! SYS - Enables the clock for the AHB, the APB bridge, the Cortex-M0+ core clocks, SYSCON, and the
4709 * PMU. This bit is read only and always reads as 1.
4710 */
4711#define SYSCON_SYSAHBCLKCTRL0_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_SYS_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_SYS_MASK)
4712#define SYSCON_SYSAHBCLKCTRL0_ROM_MASK (0x2U)
4713#define SYSCON_SYSAHBCLKCTRL0_ROM_SHIFT (1U)
4714/*! ROM - Enables clock for ROM.
4715 * 0b0..disable
4716 * 0b1..enable
4717 */
4718#define SYSCON_SYSAHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_ROM_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_ROM_MASK)
4719#define SYSCON_SYSAHBCLKCTRL0_RAM0_MASK (0x4U)
4720#define SYSCON_SYSAHBCLKCTRL0_RAM0_SHIFT (2U)
4721/*! RAM0 - Enables clock for SRAM0
4722 * 0b0..disable
4723 * 0b1..enable
4724 */
4725#define SYSCON_SYSAHBCLKCTRL0_RAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_RAM0_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_RAM0_MASK)