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Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/LPC810/LPC810_features.h')
-rw-r--r-- | lib/chibios-contrib/ext/mcux-sdk/devices/LPC810/LPC810_features.h | 173 |
1 files changed, 173 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC810/LPC810_features.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC810/LPC810_features.h new file mode 100644 index 000000000..a0b3b0f74 --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC810/LPC810_features.h | |||
@@ -0,0 +1,173 @@ | |||
1 | /* | ||
2 | ** ################################################################### | ||
3 | ** Version: rev. 1.2, 2017-06-08 | ||
4 | ** Build: b190506 | ||
5 | ** | ||
6 | ** Abstract: | ||
7 | ** Chip specific module features. | ||
8 | ** | ||
9 | ** Copyright 2016 Freescale Semiconductor, Inc. | ||
10 | ** Copyright 2016-2019 NXP | ||
11 | ** All rights reserved. | ||
12 | ** | ||
13 | ** SPDX-License-Identifier: BSD-3-Clause | ||
14 | ** | ||
15 | ** http: www.nxp.com | ||
16 | ** mail: [email protected] | ||
17 | ** | ||
18 | ** Revisions: | ||
19 | ** - rev. 1.0 (2016-08-12) | ||
20 | ** Initial version. | ||
21 | ** - rev. 1.1 (2016-11-25) | ||
22 | ** Update CANFD and Classic CAN register. | ||
23 | ** Add MAC TIMERSTAMP registers. | ||
24 | ** - rev. 1.2 (2017-06-08) | ||
25 | ** Remove RTC_CTRL_RTC_OSC_BYPASS. | ||
26 | ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. | ||
27 | ** Remove RESET and HALT from SYSCON_AHBCLKDIV. | ||
28 | ** | ||
29 | ** ################################################################### | ||
30 | */ | ||
31 | |||
32 | #ifndef _LPC810_FEATURES_H_ | ||
33 | #define _LPC810_FEATURES_H_ | ||
34 | |||
35 | /* SOC module features */ | ||
36 | |||
37 | /* @brief CRC availability on the SoC. */ | ||
38 | #define FSL_FEATURE_SOC_CRC_COUNT (1) | ||
39 | /* @brief GPIO availability on the SoC. */ | ||
40 | #define FSL_FEATURE_SOC_GPIO_COUNT (1) | ||
41 | /* @brief I2C availability on the SoC. */ | ||
42 | #define FSL_FEATURE_SOC_I2C_COUNT (1) | ||
43 | /* @brief IOCON availability on the SoC. */ | ||
44 | #define FSL_FEATURE_SOC_IOCON_COUNT (1) | ||
45 | /* @brief MRT availability on the SoC. */ | ||
46 | #define FSL_FEATURE_SOC_MRT_COUNT (1) | ||
47 | /* @brief MTB availability on the SoC. */ | ||
48 | #define FSL_FEATURE_SOC_MTB_COUNT (1) | ||
49 | /* @brief PINT availability on the SoC. */ | ||
50 | #define FSL_FEATURE_SOC_PINT_COUNT (1) | ||
51 | /* @brief PMU availability on the SoC. */ | ||
52 | #define FSL_FEATURE_SOC_PMU_COUNT (1) | ||
53 | /* @brief SCT availability on the SoC. */ | ||
54 | #define FSL_FEATURE_SOC_SCT_COUNT (1) | ||
55 | /* @brief SPI availability on the SoC. */ | ||
56 | #define FSL_FEATURE_SOC_SPI_COUNT (1) | ||
57 | /* @brief SWM availability on the SoC. */ | ||
58 | #define FSL_FEATURE_SOC_SWM_COUNT (1) | ||
59 | /* @brief SYSCON availability on the SoC. */ | ||
60 | #define FSL_FEATURE_SOC_SYSCON_COUNT (1) | ||
61 | /* @brief USART availability on the SoC. */ | ||
62 | #define FSL_FEATURE_SOC_USART_COUNT (2) | ||
63 | /* @brief WWDT availability on the SoC. */ | ||
64 | #define FSL_FEATURE_SOC_WWDT_COUNT (1) | ||
65 | |||
66 | /* ACOMP module features */ | ||
67 | |||
68 | /* @brief Has INTENA bitfile in CTRL reigster. */ | ||
69 | #define FSL_FEATURE_ACOMP_HAS_CTRL_INTENA (0) | ||
70 | |||
71 | /* CLOCK module features */ | ||
72 | |||
73 | /* @brief GPIOINT clock source. */ | ||
74 | #define FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE (0) | ||
75 | |||
76 | /* IOCON module features */ | ||
77 | |||
78 | /* No feature definitions */ | ||
79 | |||
80 | /* MRT module features */ | ||
81 | |||
82 | /* @brief Writing a zero asserts the MRT reset. */ | ||
83 | #define FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET (1) | ||
84 | /* @brief Has no MULTITASK bitfile in MODCFG reigster. */ | ||
85 | #define FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK (1) | ||
86 | /* @brief Has no INUSE bitfile in STAT reigster. */ | ||
87 | #define FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE (1) | ||
88 | /* @brief number of channels. */ | ||
89 | #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) | ||
90 | |||
91 | /* NVIC module features */ | ||
92 | |||
93 | /* @brief Number of connected outputs. */ | ||
94 | #define FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER (1) | ||
95 | |||
96 | /* PINT module features */ | ||
97 | |||
98 | /* @brief Number of connected outputs */ | ||
99 | #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) | ||
100 | |||
101 | /* SCT module features */ | ||
102 | |||
103 | /* @brief Number of events */ | ||
104 | #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (6) | ||
105 | /* @brief Number of states */ | ||
106 | #define FSL_FEATURE_SCT_NUMBER_OF_STATES (2) | ||
107 | /* @brief Number of match capture */ | ||
108 | #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (5) | ||
109 | /* @brief Writing a zero asserts the SCT reset. */ | ||
110 | #define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (1) | ||
111 | /* @brief Do not has DMA request register (register DMAREQ0). */ | ||
112 | #define FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST (1) | ||
113 | /* @brief Number of outputs */ | ||
114 | #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (4) | ||
115 | |||
116 | /* SPI module features */ | ||
117 | |||
118 | /* @brief Has SPOL0 bitfile in CFG reigster. */ | ||
119 | #define FSL_FEATURE_SPI_HAS_SSEL0 (1) | ||
120 | /* @brief Has SPOL1 bitfile in CFG reigster. */ | ||
121 | #define FSL_FEATURE_SPI_HAS_SSEL1 (0) | ||
122 | /* @brief Has SPOL2 bitfile in CFG reigster. */ | ||
123 | #define FSL_FEATURE_SPI_HAS_SSEL2 (0) | ||
124 | /* @brief Has SPOL3 bitfile in CFG reigster. */ | ||
125 | #define FSL_FEATURE_SPI_HAS_SSEL3 (0) | ||
126 | |||
127 | /* SWM module features */ | ||
128 | |||
129 | /* @brief Has SWM PINENABLE0 ACMP I3. */ | ||
130 | #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I3 (0) | ||
131 | /* @brief Has SWM PINENABLE0 ACMP I4. */ | ||
132 | #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I4 (0) | ||
133 | /* @brief Has SWM PINENABLE0 ACMP I5. */ | ||
134 | #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I5 (0) | ||
135 | |||
136 | /* SYSCON module features */ | ||
137 | |||
138 | /* @brief Pointer to ROM IAP entry functions */ | ||
139 | #define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x1fff1ff1) | ||
140 | /* @brief Flash page size in bytes */ | ||
141 | #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (64) | ||
142 | /* @brief Flash sector size in bytes */ | ||
143 | #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (1024) | ||
144 | /* @brief Flash size in bytes */ | ||
145 | #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (4096) | ||
146 | /* @brief IAP has Flash read & write function */ | ||
147 | #define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1) | ||
148 | /* @brief Starter register discontinuous. */ | ||
149 | #define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) | ||
150 | /* @brief Has PINTSEL register. */ | ||
151 | #define FSL_FEATURE_SYSCON_HAS_PINT_SEL_REGISTER (1) | ||
152 | |||
153 | /* USART module features */ | ||
154 | |||
155 | /* @brief Has OSR (register OSR). */ | ||
156 | #define FSL_FEATURE_USART_HAS_OSR_REGISTER (0) | ||
157 | /* @brief Has TXIDLEEN bitfile in INTENSET reigster. */ | ||
158 | #define FSL_FEATURE_USART_HAS_INTENSET_TXIDLEEN (0) | ||
159 | /* @brief Has ABERREN bitfile in INTENSET reigster. */ | ||
160 | #define FSL_FEATURE_USART_HAS_ABERR_CHECK (0) | ||
161 | |||
162 | /* WKT module features */ | ||
163 | |||
164 | /* @brief Has SEL_EXTCLK bitfile in CTRL reigster. */ | ||
165 | #define FSL_FEATURE_WKT_HAS_CTRL_SEL_EXTCLK (0) | ||
166 | |||
167 | /* WWDT module features */ | ||
168 | |||
169 | /* @brief Has no RESET register. */ | ||
170 | #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) | ||
171 | |||
172 | #endif /* _LPC810_FEATURES_H_ */ | ||
173 | |||