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1/*
2** ###################################################################
3** Processor: LPC811M001JDH16
4** Compilers: GNU C Compiler
5** IAR ANSI C/C++ Compiler for ARM
6** Keil ARM C/C++ Compiler
7** MCUXpresso Compiler
8**
9** Reference manual: LPC81x User manual Rev.1.6 2 April 2014
10** Version: rev. 1.2, 2017-06-08
11** Build: b200513
12**
13** Abstract:
14** CMSIS Peripheral Access Layer for LPC811
15**
16** Copyright 1997-2016 Freescale Semiconductor, Inc.
17** Copyright 2016-2020 NXP
18** All rights reserved.
19**
20** SPDX-License-Identifier: BSD-3-Clause
21**
22** http: www.nxp.com
23** mail: [email protected]
24**
25** Revisions:
26** - rev. 1.0 (2016-08-12)
27** Initial version.
28** - rev. 1.1 (2016-11-25)
29** Update CANFD and Classic CAN register.
30** Add MAC TIMERSTAMP registers.
31** - rev. 1.2 (2017-06-08)
32** Remove RTC_CTRL_RTC_OSC_BYPASS.
33** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
34** Remove RESET and HALT from SYSCON_AHBCLKDIV.
35**
36** ###################################################################
37*/
38
39/*!
40 * @file LPC811.h
41 * @version 1.2
42 * @date 2017-06-08
43 * @brief CMSIS Peripheral Access Layer for LPC811
44 *
45 * CMSIS Peripheral Access Layer for LPC811
46 */
47
48#ifndef _LPC811_H_
49#define _LPC811_H_ /**< Symbol preventing repeated inclusion */
50
51/** Memory map major version (memory maps with equal major version number are
52 * compatible) */
53#define MCU_MEM_MAP_VERSION 0x0100U
54/** Memory map minor version */
55#define MCU_MEM_MAP_VERSION_MINOR 0x0002U
56
57
58/* ----------------------------------------------------------------------------
59 -- Interrupt vector numbers
60 ---------------------------------------------------------------------------- */
61
62/*!
63 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
64 * @{
65 */
66
67/** Interrupt Number Definitions */
68#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
69
70typedef enum IRQn {
71 /* Auxiliary constants */
72 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
73
74 /* Core interrupts */
75 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
76 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
77 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
78 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
79 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
80
81 /* Device specific interrupts */
82 SPI0_IRQn = 0, /**< SPI0 interrupt */
83 SPI1_IRQn = 1, /**< SPI1 interrupt */
84 Reserved18_IRQn = 2, /**< Reserved interrupt */
85 USART0_IRQn = 3, /**< USART0 interrupt */
86 USART1_IRQn = 4, /**< USART1 interrupt */
87 USART2_IRQn = 5, /**< USART2 interrupt */
88 Reserved22_IRQn = 6, /**< Reserved interrupt */
89 Reserved23_IRQn = 7, /**< Reserved interrupt */
90 I2C0_IRQn = 8, /**< I2C0 interrupt */
91 SCT0_IRQn = 9, /**< State configurable timer interrupt */
92 MRT0_IRQn = 10, /**< Multi-rate timer interrupt */
93 CMP_IRQn = 11, /**< Analog comparator interrupt or Capacitive Touch interrupt */
94 WDT_IRQn = 12, /**< Windowed watchdog timer interrupt */
95 BOD_IRQn = 13, /**< BOD interrupts */
96 Reserved30_IRQn = 14, /**< Reserved interrupt */
97 WKT_IRQn = 15, /**< Self-wake-up timer interrupt */
98 Reserved32_IRQn = 16, /**< Reserved interrupt */
99 Reserved33_IRQn = 17, /**< Reserved interrupt */
100 Reserved34_IRQn = 18, /**< Reserved interrupt */
101 Reserved35_IRQn = 19, /**< Reserved interrupt */
102 Reserved36_IRQn = 20, /**< Reserved interrupt */
103 Reserved37_IRQn = 21, /**< Reserved interrupt */
104 Reserved38_IRQn = 22, /**< Reserved interrupt */
105 Reserved39_IRQn = 23, /**< Reserved interrupt */
106 PIN_INT0_IRQn = 24, /**< Pin interrupt 0 or pattern match engine slice 0 interrupt */
107 PIN_INT1_IRQn = 25, /**< Pin interrupt 1 or pattern match engine slice 1 interrupt */
108 PIN_INT2_IRQn = 26, /**< Pin interrupt 2 or pattern match engine slice 2 interrupt */
109 PIN_INT3_IRQn = 27, /**< Pin interrupt 3 or pattern match engine slice 3 interrupt */
110 PIN_INT4_IRQn = 28, /**< Pin interrupt 4 or pattern match engine slice 4 interrupt */
111 PIN_INT5_IRQn = 29, /**< Pin interrupt 5 or pattern match engine slice 5 interrupt */
112 PIN_INT6_IRQn = 30, /**< Pin interrupt 6 or pattern match engine slice 6 interrupt */
113 PIN_INT7_IRQn = 31 /**< Pin interrupt 7 or pattern match engine slice 7 interrupt */
114} IRQn_Type;
115
116/*!
117 * @}
118 */ /* end of group Interrupt_vector_numbers */
119
120
121/* ----------------------------------------------------------------------------
122 -- Cortex M0 Core Configuration
123 ---------------------------------------------------------------------------- */
124
125/*!
126 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
127 * @{
128 */
129
130#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
131#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
132#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */
133#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
134#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
135
136#include "core_cm0plus.h" /* Core Peripheral Access Layer */
137#include "system_LPC811.h" /* Device specific configuration file */
138
139/*!
140 * @}
141 */ /* end of group Cortex_Core_Configuration */
142
143
144/* ----------------------------------------------------------------------------
145 -- Device Peripheral Access Layer
146 ---------------------------------------------------------------------------- */
147
148/*!
149 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
150 * @{
151 */
152
153
154/*
155** Start of section using anonymous unions
156*/
157
158#if defined(__ARMCC_VERSION)
159 #if (__ARMCC_VERSION >= 6010050)
160 #pragma clang diagnostic push
161 #else
162 #pragma push
163 #pragma anon_unions
164 #endif
165#elif defined(__GNUC__)
166 /* anonymous unions are enabled by default */
167#elif defined(__IAR_SYSTEMS_ICC__)
168 #pragma language=extended
169#else
170 #error Not supported compiler type
171#endif
172
173/* ----------------------------------------------------------------------------
174 -- ACOMP Peripheral Access Layer
175 ---------------------------------------------------------------------------- */
176
177/*!
178 * @addtogroup ACOMP_Peripheral_Access_Layer ACOMP Peripheral Access Layer
179 * @{
180 */
181
182/** ACOMP - Register Layout Typedef */
183typedef struct {
184 __IO uint32_t CTRL; /**< Comparator control register, offset: 0x0 */
185 __IO uint32_t LAD; /**< Voltage ladder register, offset: 0x4 */
186} ACOMP_Type;
187
188/* ----------------------------------------------------------------------------
189 -- ACOMP Register Masks
190 ---------------------------------------------------------------------------- */
191
192/*!
193 * @addtogroup ACOMP_Register_Masks ACOMP Register Masks
194 * @{
195 */
196
197/*! @name CTRL - Comparator control register */
198/*! @{ */
199#define ACOMP_CTRL_EDGESEL_MASK (0x18U)
200#define ACOMP_CTRL_EDGESEL_SHIFT (3U)
201/*! EDGESEL - This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below):
202 * 0b00..Falling edges
203 * 0b01..Rising edges
204 * 0b10..Both edges
205 * 0b11..Both edges
206 */
207#define ACOMP_CTRL_EDGESEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_EDGESEL_SHIFT)) & ACOMP_CTRL_EDGESEL_MASK)
208#define ACOMP_CTRL_COMPSA_MASK (0x40U)
209#define ACOMP_CTRL_COMPSA_SHIFT (6U)
210/*! COMPSA - Comparator output control
211 * 0b0..Comparator output is used directly.
212 * 0b1..Comparator output is synchronized to the bus clock for output to other modules.
213 */
214#define ACOMP_CTRL_COMPSA(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPSA_SHIFT)) & ACOMP_CTRL_COMPSA_MASK)
215#define ACOMP_CTRL_COMP_VP_SEL_MASK (0x700U)
216#define ACOMP_CTRL_COMP_VP_SEL_SHIFT (8U)
217/*! COMP_VP_SEL - Selects positive voltage input
218 * 0b000..VOLTAGE_LADDER_OUTPUT
219 * 0b001..ACMP_I1
220 * 0b010..ACMP_I2
221 * 0b011..ACMP_I3
222 * 0b100..ACMP_I4
223 * 0b101..ACMP_I5
224 * 0b110..Band gap. Internal reference voltage.
225 * 0b111..DAC0 output
226 */
227#define ACOMP_CTRL_COMP_VP_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMP_VP_SEL_SHIFT)) & ACOMP_CTRL_COMP_VP_SEL_MASK)
228#define ACOMP_CTRL_COMP_VM_SEL_MASK (0x3800U)
229#define ACOMP_CTRL_COMP_VM_SEL_SHIFT (11U)
230/*! COMP_VM_SEL - Selects negative voltage input
231 * 0b000..VOLTAGE_LADDER_OUTPUT
232 * 0b001..ACMP_I1
233 * 0b010..ACMP_I2
234 * 0b011..ACMP_I3
235 * 0b100..ACMP_I4
236 * 0b101..ACMP_I5
237 * 0b110..Band gap. Internal reference voltage.
238 * 0b111..DAC0 output
239 */
240#define ACOMP_CTRL_COMP_VM_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMP_VM_SEL_SHIFT)) & ACOMP_CTRL_COMP_VM_SEL_MASK)
241#define ACOMP_CTRL_EDGECLR_MASK (0x100000U)
242#define ACOMP_CTRL_EDGECLR_SHIFT (20U)
243/*! EDGECLR - Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request,
244 * toggle the EDGECLR bit by first writing a 1 and then a 0.
245 */
246#define ACOMP_CTRL_EDGECLR(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_EDGECLR_SHIFT)) & ACOMP_CTRL_EDGECLR_MASK)
247#define ACOMP_CTRL_COMPSTAT_MASK (0x200000U)
248#define ACOMP_CTRL_COMPSTAT_SHIFT (21U)
249/*! COMPSTAT - Comparator status. This bit reflects the state of the comparator output.
250 */
251#define ACOMP_CTRL_COMPSTAT(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPSTAT_SHIFT)) & ACOMP_CTRL_COMPSTAT_MASK)
252#define ACOMP_CTRL_COMPEDGE_MASK (0x800000U)
253#define ACOMP_CTRL_COMPEDGE_SHIFT (23U)
254/*! COMPEDGE - Comparator edge-detect status.
255 */
256#define ACOMP_CTRL_COMPEDGE(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPEDGE_SHIFT)) & ACOMP_CTRL_COMPEDGE_MASK)
257#define ACOMP_CTRL_HYS_MASK (0x6000000U)
258#define ACOMP_CTRL_HYS_SHIFT (25U)
259/*! HYS - Controls the hysteresis of the comparator. When the comparator is outputting a certain
260 * state, this is the difference between the selected signals, in the opposite direction from the
261 * state being output, that will switch the output.
262 * 0b00..None (the output will switch as the voltages cross)
263 * 0b01..5 mv
264 * 0b10..10 mv
265 * 0b11..20 mv
266 */
267#define ACOMP_CTRL_HYS(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_HYS_SHIFT)) & ACOMP_CTRL_HYS_MASK)
268/*! @} */
269
270/*! @name LAD - Voltage ladder register */
271/*! @{ */
272#define ACOMP_LAD_LADEN_MASK (0x1U)
273#define ACOMP_LAD_LADEN_SHIFT (0U)
274/*! LADEN - Voltage ladder enable
275 */
276#define ACOMP_LAD_LADEN(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADEN_SHIFT)) & ACOMP_LAD_LADEN_MASK)
277#define ACOMP_LAD_LADSEL_MASK (0x3EU)
278#define ACOMP_LAD_LADSEL_SHIFT (1U)
279/*! LADSEL - Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000
280 * = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref
281 */
282#define ACOMP_LAD_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADSEL_SHIFT)) & ACOMP_LAD_LADSEL_MASK)
283#define ACOMP_LAD_LADREF_MASK (0x40U)
284#define ACOMP_LAD_LADREF_SHIFT (6U)
285/*! LADREF - Selects the reference voltage Vref for the voltage ladder.
286 * 0b0..Supply pin VDD
287 * 0b1..VDDCMP pin
288 */
289#define ACOMP_LAD_LADREF(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADREF_SHIFT)) & ACOMP_LAD_LADREF_MASK)
290/*! @} */
291
292
293/*!
294 * @}
295 */ /* end of group ACOMP_Register_Masks */
296
297
298/* ACOMP - Peripheral instance base addresses */
299/** Peripheral ACOMP base address */
300#define ACOMP_BASE (0x40024000u)
301/** Peripheral ACOMP base pointer */
302#define ACOMP ((ACOMP_Type *)ACOMP_BASE)
303/** Array initializer of ACOMP peripheral base addresses */
304#define ACOMP_BASE_ADDRS { ACOMP_BASE }
305/** Array initializer of ACOMP peripheral base pointers */
306#define ACOMP_BASE_PTRS { ACOMP }
307
308/*!
309 * @}
310 */ /* end of group ACOMP_Peripheral_Access_Layer */
311
312
313/* ----------------------------------------------------------------------------
314 -- CRC Peripheral Access Layer
315 ---------------------------------------------------------------------------- */
316
317/*!
318 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
319 * @{
320 */
321
322/** CRC - Register Layout Typedef */
323typedef struct {
324 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
325 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
326 union { /* offset: 0x8 */
327 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
328 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
329 };
330} CRC_Type;
331
332/* ----------------------------------------------------------------------------
333 -- CRC Register Masks
334 ---------------------------------------------------------------------------- */
335
336/*!
337 * @addtogroup CRC_Register_Masks CRC Register Masks
338 * @{
339 */
340
341/*! @name MODE - CRC mode register */
342/*! @{ */
343#define CRC_MODE_CRC_POLY_MASK (0x3U)
344#define CRC_MODE_CRC_POLY_SHIFT (0U)
345/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
346 */
347#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
348#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
349#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
350/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
351 */
352#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
353#define CRC_MODE_CMPL_WR_MASK (0x8U)
354#define CRC_MODE_CMPL_WR_SHIFT (3U)
355/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
356 */
357#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
358#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
359#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
360/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
361 */
362#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
363#define CRC_MODE_CMPL_SUM_MASK (0x20U)
364#define CRC_MODE_CMPL_SUM_SHIFT (5U)
365/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
366 */
367#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
368/*! @} */
369
370/*! @name SEED - CRC seed register */
371/*! @{ */
372#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
373#define CRC_SEED_CRC_SEED_SHIFT (0U)
374/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
375 * selected bit order and 1's complement pre-processes. A write access to this register will
376 * overrule the CRC calculation in progresses.
377 */
378#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
379/*! @} */
380
381/*! @name SUM - CRC checksum register */
382/*! @{ */
383#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
384#define CRC_SUM_CRC_SUM_SHIFT (0U)
385/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
386 */
387#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
388/*! @} */
389
390/*! @name WR_DATA - CRC data register */
391/*! @{ */
392#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
393#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
394/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
395 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
396 * accept back-to-back transactions.
397 */
398#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
399/*! @} */
400
401
402/*!
403 * @}
404 */ /* end of group CRC_Register_Masks */
405
406
407/* CRC - Peripheral instance base addresses */
408/** Peripheral CRC base address */
409#define CRC_BASE (0x50000000u)
410/** Peripheral CRC base pointer */
411#define CRC ((CRC_Type *)CRC_BASE)
412/** Array initializer of CRC peripheral base addresses */
413#define CRC_BASE_ADDRS { CRC_BASE }
414/** Array initializer of CRC peripheral base pointers */
415#define CRC_BASE_PTRS { CRC }
416
417/*!
418 * @}
419 */ /* end of group CRC_Peripheral_Access_Layer */
420
421
422/* ----------------------------------------------------------------------------
423 -- FLASH_CTRL Peripheral Access Layer
424 ---------------------------------------------------------------------------- */
425
426/*!
427 * @addtogroup FLASH_CTRL_Peripheral_Access_Layer FLASH_CTRL Peripheral Access Layer
428 * @{
429 */
430
431/** FLASH_CTRL - Register Layout Typedef */
432typedef struct {
433 uint8_t RESERVED_0[16];
434 __IO uint32_t FLASHCFG; /**< Flash configuration register, offset: 0x10 */
435 uint8_t RESERVED_1[12];
436 __IO uint32_t FMSSTART; /**< Flash signature start address register, offset: 0x20 */
437 __IO uint32_t FMSSTOP; /**< Flash signaure stop address register, offset: 0x24 */
438 uint8_t RESERVED_2[4];
439 __I uint32_t FMSW0; /**< Flash signature generation result register returns the flash signature produced by the embedded signature generator.., offset: 0x2C */
440} FLASH_CTRL_Type;
441
442/* ----------------------------------------------------------------------------
443 -- FLASH_CTRL Register Masks
444 ---------------------------------------------------------------------------- */
445
446/*!
447 * @addtogroup FLASH_CTRL_Register_Masks FLASH_CTRL Register Masks
448 * @{
449 */
450
451/*! @name FLASHCFG - Flash configuration register */
452/*! @{ */
453#define FLASH_CTRL_FLASHCFG_FLASHTIM_MASK (0x3U)
454#define FLASH_CTRL_FLASHCFG_FLASHTIM_SHIFT (0U)
455/*! FLASHTIM - Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
456 * 0b00..1 system clock flash access time.
457 * 0b01..2 system clock flash access time.
458 * 0b10..3 system clock flash access time.
459 * 0b11..Reserved.
460 */
461#define FLASH_CTRL_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FLASHCFG_FLASHTIM_SHIFT)) & FLASH_CTRL_FLASHCFG_FLASHTIM_MASK)
462/*! @} */
463
464/*! @name FMSSTART - Flash signature start address register */
465/*! @{ */
466#define FLASH_CTRL_FMSSTART_START_MASK (0x1FFFFU)
467#define FLASH_CTRL_FMSSTART_START_SHIFT (0U)
468/*! START - Signature generation start address (corresponds to AHB byte address bits[18:2]).
469 */
470#define FLASH_CTRL_FMSSTART_START(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTART_START_SHIFT)) & FLASH_CTRL_FMSSTART_START_MASK)
471/*! @} */
472
473/*! @name FMSSTOP - Flash signaure stop address register */
474/*! @{ */
475#define FLASH_CTRL_FMSSTOP_STOPA_MASK (0x1FFFFU)
476#define FLASH_CTRL_FMSSTOP_STOPA_SHIFT (0U)
477/*! STOPA - Stop address for signature generation (the word specified by STOP is included in the
478 * address range). The address is in units of memory words, not bytes.
479 */
480#define FLASH_CTRL_FMSSTOP_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTOP_STOPA_SHIFT)) & FLASH_CTRL_FMSSTOP_STOPA_MASK)
481#define FLASH_CTRL_FMSSTOP_STRTBIST_MASK (0x80000000U)
482#define FLASH_CTRL_FMSSTOP_STRTBIST_SHIFT (31U)
483/*! STRTBIST - When this bit is written to 1, signature generation starts. At the end of signature
484 * generation, this bit is automatically cleared.
485 */
486#define FLASH_CTRL_FMSSTOP_STRTBIST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTOP_STRTBIST_SHIFT)) & FLASH_CTRL_FMSSTOP_STRTBIST_MASK)
487/*! @} */
488
489/*! @name FMSW0 - Flash signature generation result register returns the flash signature produced by the embedded signature generator.. */
490/*! @{ */
491#define FLASH_CTRL_FMSW0_SIG_MASK (0xFFFFFFFFU)
492#define FLASH_CTRL_FMSW0_SIG_SHIFT (0U)
493/*! SIG - 32-bit signature.
494 */
495#define FLASH_CTRL_FMSW0_SIG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSW0_SIG_SHIFT)) & FLASH_CTRL_FMSW0_SIG_MASK)
496/*! @} */
497
498
499/*!
500 * @}
501 */ /* end of group FLASH_CTRL_Register_Masks */
502
503
504/* FLASH_CTRL - Peripheral instance base addresses */
505/** Peripheral FLASH_CTRL base address */
506#define FLASH_CTRL_BASE (0x40040000u)
507/** Peripheral FLASH_CTRL base pointer */
508#define FLASH_CTRL ((FLASH_CTRL_Type *)FLASH_CTRL_BASE)
509/** Array initializer of FLASH_CTRL peripheral base addresses */
510#define FLASH_CTRL_BASE_ADDRS { FLASH_CTRL_BASE }
511/** Array initializer of FLASH_CTRL peripheral base pointers */
512#define FLASH_CTRL_BASE_PTRS { FLASH_CTRL }
513
514/*!
515 * @}
516 */ /* end of group FLASH_CTRL_Peripheral_Access_Layer */
517
518
519/* ----------------------------------------------------------------------------
520 -- GPIO Peripheral Access Layer
521 ---------------------------------------------------------------------------- */
522
523/*!
524 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
525 * @{
526 */
527
528/** GPIO - Register Layout Typedef */
529typedef struct {
530 __IO uint8_t B[1][18]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x12, index2*0x1 */
531 uint8_t RESERVED_0[4078];
532 __IO uint32_t W[1][18]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x48, index2*0x4 */
533 uint8_t RESERVED_1[4024];
534 __IO uint32_t DIR[1]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */
535 uint8_t RESERVED_2[124];
536 __IO uint32_t MASK[1]; /**< Mask register, array offset: 0x2080, array step: 0x4 */
537 uint8_t RESERVED_3[124];
538 __IO uint32_t PIN[1]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */
539 uint8_t RESERVED_4[124];
540 __IO uint32_t MPIN[1]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */
541 uint8_t RESERVED_5[124];
542 __IO uint32_t SET[1]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
543 uint8_t RESERVED_6[124];
544 __O uint32_t CLR[1]; /**< Clear port, array offset: 0x2280, array step: 0x4 */
545 uint8_t RESERVED_7[124];
546 __O uint32_t NOT[1]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */
547} GPIO_Type;
548
549/* ----------------------------------------------------------------------------
550 -- GPIO Register Masks
551 ---------------------------------------------------------------------------- */
552
553/*!
554 * @addtogroup GPIO_Register_Masks GPIO Register Masks
555 * @{
556 */
557
558/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
559/*! @{ */
560#define GPIO_B_PBYTE_MASK (0x1U)
561#define GPIO_B_PBYTE_SHIFT (0U)
562/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function,
563 * except that pins configured as analog I/O always read as 0. One register for each port pin.
564 * Supported pins depends on the specific device and package. Write: loads the pin's output bit.
565 * One register for each port pin. Supported pins depends on the specific device and package.
566 */
567#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
568/*! @} */
569
570/* The count of GPIO_B */
571#define GPIO_B_COUNT (1U)
572
573/* The count of GPIO_B */
574#define GPIO_B_COUNT2 (18U)
575
576/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
577/*! @{ */
578#define GPIO_W_PWORD_MASK (0xFFFFFFFFU)
579#define GPIO_W_PWORD_SHIFT (0U)
580/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is
581 * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be
582 * read. Writing any value other than 0 will set the output bit. One register for each port pin.
583 * Supported pins depends on the specific device and package.
584 */
585#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
586/*! @} */
587
588/* The count of GPIO_W */
589#define GPIO_W_COUNT (1U)
590
591/* The count of GPIO_W */
592#define GPIO_W_COUNT2 (18U)
593
594/*! @name DIR - Direction registers */
595/*! @{ */
596#define GPIO_DIR_DIRP_MASK (0x3FFFFU)
597#define GPIO_DIR_DIRP_SHIFT (0U)
598/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
599 * pins depends on the specific device and package. 0 = input. 1 = output.
600 */
601#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
602/*! @} */
603
604/* The count of GPIO_DIR */
605#define GPIO_DIR_COUNT (1U)
606
607/*! @name MASK - Mask register */
608/*! @{ */
609#define GPIO_MASK_MASKP_MASK (0x3FFFFU)
610#define GPIO_MASK_MASKP_SHIFT (0U)
611/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 =
612 * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 =
613 * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit
614 * not affected.
615 */
616#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
617/*! @} */
618
619/* The count of GPIO_MASK */
620#define GPIO_MASK_COUNT (1U)
621
622/*! @name PIN - Port pin register */
623/*! @{ */
624#define GPIO_PIN_PORT_MASK (0x3FFFFU)
625#define GPIO_PIN_PORT_SHIFT (0U)
626/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
627 * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit.
628 * 1 = Read: pin is high; write: set output bit.
629 */
630#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
631/*! @} */
632
633/* The count of GPIO_PIN */
634#define GPIO_PIN_COUNT (1U)
635
636/*! @name MPIN - Masked port register */
637/*! @{ */
638#define GPIO_MPIN_MPORTP_MASK (0x3FFFFU)
639#define GPIO_MPIN_MPORTP_SHIFT (0U)
640/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
641 * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK
642 * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1
643 * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit
644 * if the corresponding bit in the MASK register is 0.
645 */
646#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
647/*! @} */
648
649/* The count of GPIO_MPIN */
650#define GPIO_MPIN_COUNT (1U)
651
652/*! @name SET - Write: Set register for port Read: output bits for port */
653/*! @{ */
654#define GPIO_SET_SETP_MASK (0x3FFFFU)
655#define GPIO_SET_SETP_SHIFT (0U)
656/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
657 * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output
658 * bit; write: set output bit.
659 */
660#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
661/*! @} */
662
663/* The count of GPIO_SET */
664#define GPIO_SET_COUNT (1U)
665
666/*! @name CLR - Clear port */
667/*! @{ */
668#define GPIO_CLR_CLRP_MASK (0x3FFFFU)
669#define GPIO_CLR_CLRP_SHIFT (0U)
670/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
671 * specific device and package. 0 = No operation. 1 = Clear output bit.
672 */
673#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
674/*! @} */
675
676/* The count of GPIO_CLR */
677#define GPIO_CLR_COUNT (1U)
678
679/*! @name NOT - Toggle port */
680/*! @{ */
681#define GPIO_NOT_NOTP_MASK (0x3FFFFU)
682#define GPIO_NOT_NOTP_SHIFT (0U)
683/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
684 * specific device and package. 0 = no operation. 1 = Toggle output bit.
685 */
686#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
687/*! @} */
688
689/* The count of GPIO_NOT */
690#define GPIO_NOT_COUNT (1U)
691
692
693/*!
694 * @}
695 */ /* end of group GPIO_Register_Masks */
696
697
698/* GPIO - Peripheral instance base addresses */
699/** Peripheral GPIO base address */
700#define GPIO_BASE (0xA0000000u)
701/** Peripheral GPIO base pointer */
702#define GPIO ((GPIO_Type *)GPIO_BASE)
703/** Array initializer of GPIO peripheral base addresses */
704#define GPIO_BASE_ADDRS { GPIO_BASE }
705/** Array initializer of GPIO peripheral base pointers */
706#define GPIO_BASE_PTRS { GPIO }
707
708/*!
709 * @}
710 */ /* end of group GPIO_Peripheral_Access_Layer */
711
712
713/* ----------------------------------------------------------------------------
714 -- I2C Peripheral Access Layer
715 ---------------------------------------------------------------------------- */
716
717/*!
718 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
719 * @{
720 */
721
722/** I2C - Register Layout Typedef */
723typedef struct {
724 __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x0 */
725 __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x4 */
726 __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x8 */
727 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0xC */
728 __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x10 */
729 __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x14 */
730 __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x18 */
731 uint8_t RESERVED_0[4];
732 __IO uint32_t MSTCTL; /**< Master control register., offset: 0x20 */
733 __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x24 */
734 __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x28 */
735 uint8_t RESERVED_1[20];
736 __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x40 */
737 __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x44 */
738 __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x48, array step: 0x4 */
739 __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x58 */
740 uint8_t RESERVED_2[36];
741 __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x80 */
742} I2C_Type;
743
744/* ----------------------------------------------------------------------------
745 -- I2C Register Masks
746 ---------------------------------------------------------------------------- */
747
748/*!
749 * @addtogroup I2C_Register_Masks I2C Register Masks
750 * @{
751 */
752
753/*! @name CFG - Configuration for shared functions. */
754/*! @{ */
755#define I2C_CFG_MSTEN_MASK (0x1U)
756#define I2C_CFG_MSTEN_SHIFT (0U)
757/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not
758 * changed, but the Master function is internally reset.
759 * 0b0..Disabled. The I2C Master function is disabled.
760 * 0b1..Enabled. The I2C Master function is enabled.
761 */
762#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
763#define I2C_CFG_SLVEN_MASK (0x2U)
764#define I2C_CFG_SLVEN_SHIFT (1U)
765/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not
766 * changed, but the Slave function is internally reset.
767 * 0b0..Disabled. The I2C slave function is disabled.
768 * 0b1..Enabled. The I2C slave function is enabled.
769 */
770#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
771#define I2C_CFG_MONEN_MASK (0x4U)
772#define I2C_CFG_MONEN_SHIFT (2U)
773/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not
774 * changed, but the Monitor function is internally reset.
775 * 0b0..Disabled. The I2C Monitor function is disabled.
776 * 0b1..Enabled. The I2C Monitor function is enabled.
777 */
778#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
779#define I2C_CFG_TIMEOUTEN_MASK (0x8U)
780#define I2C_CFG_TIMEOUTEN_SHIFT (3U)
781/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
782 * 0b0..Disabled. Time-out function is disabled.
783 * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause
784 * interrupts if they are enabled. Typically, only one time-out will be used in a system.
785 */
786#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
787#define I2C_CFG_MONCLKSTR_MASK (0x10U)
788#define I2C_CFG_MONCLKSTR_SHIFT (4U)
789/*! MONCLKSTR - Monitor function Clock Stretching.
790 * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able
791 * to read data provided by the Monitor function before it is overwritten. This mode may be used when
792 * non-invasive monitoring is critical.
793 * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can
794 * read all incoming data supplied by the Monitor function.
795 */
796#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
797/*! @} */
798
799/*! @name STAT - Status register for Master, Slave, and Monitor functions. */
800/*! @{ */
801#define I2C_STAT_MSTPENDING_MASK (0x1U)
802#define I2C_STAT_MSTPENDING_SHIFT (0U)
803/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on
804 * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what
805 * type of software service if any the master expects. This flag will cause an interrupt when set
806 * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling
807 * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle
808 * state, and no communication is needed, mask this interrupt.
809 * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
810 * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the
811 * idle state, it is waiting to receive or transmit data or the NACK bit.
812 */
813#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
814#define I2C_STAT_MSTSTATE_MASK (0xEU)
815#define I2C_STAT_MSTSTATE_SHIFT (1U)
816/*! MSTSTATE - Master State code. The master state code reflects the master state when the
817 * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field
818 * indicates a specific required service for the Master function. All other values are reserved. See
819 * Table 400 for details of state values and appropriate responses.
820 * 0b000..Idle. The Master function is available to be used for a new transaction.
821 * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
822 * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
823 * 0b011..NACK Address. Slave NACKed address.
824 * 0b100..NACK Data. Slave NACKed transmitted data.
825 */
826#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
827#define I2C_STAT_MSTARBLOSS_MASK (0x10U)
828#define I2C_STAT_MSTARBLOSS_SHIFT (4U)
829/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to
830 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
831 * 0b0..No Arbitration Loss has occurred.
832 * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master
833 * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing,
834 * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
835 */
836#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
837#define I2C_STAT_MSTSTSTPERR_MASK (0x40U)
838#define I2C_STAT_MSTSTSTPERR_SHIFT (6U)
839/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to
840 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
841 * 0b0..No Start/Stop Error has occurred.
842 * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is
843 * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an
844 * idle state, no action is required. A request for a Start could be made, or software could attempt to insure
845 * that the bus has not stalled.
846 */
847#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
848#define I2C_STAT_SLVPENDING_MASK (0x100U)
849#define I2C_STAT_SLVPENDING_SHIFT (8U)
850/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue
851 * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if
852 * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the
853 * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is
854 * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time
855 * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section
856 * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are
857 * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must
858 * also be detected automatically, since the address must be acknowledged before the clock can be
859 * stretched.
860 * 0b0..In progress. The Slave function does not currently need service.
861 * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
862 */
863#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
864#define I2C_STAT_SLVSTATE_MASK (0x600U)
865#define I2C_STAT_SLVSTATE_SHIFT (9U)
866/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for
867 * the Slave function. All other values are reserved. See Table 401 for state values and actions.
868 * note that the occurrence of some states and how they are handled are affected by DMA mode and
869 * Automatic Operation modes.
870 * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
871 * 0b01..Slave receive. Received data is available (Slave Receiver mode).
872 * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode).
873 */
874#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
875#define I2C_STAT_SLVNOTSTR_MASK (0x800U)
876#define I2C_STAT_SLVNOTSTR_SHIFT (11U)
877/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock.
878 * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave
879 * operation. This read-only flag reflects the slave function status in real time.
880 * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
881 * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or
882 * Power-down mode could be entered at this time.
883 */
884#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
885#define I2C_STAT_SLVIDX_MASK (0x3000U)
886#define I2C_STAT_SLVIDX_SHIFT (12U)
887/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been
888 * selected by receiving an address that matches one of the slave addresses defined by any enabled
889 * slave address registers, and provides an identification of the address that was matched. It is
890 * possible that more than one address could be matched, but only one match can be reported here.
891 * 0b00..Address 0. Slave address 0 was matched.
892 * 0b01..Address 1. Slave address 1 was matched.
893 * 0b10..Address 2. Slave address 2 was matched.
894 * 0b11..Address 3. Slave address 3 was matched.
895 */
896#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
897#define I2C_STAT_SLVSEL_MASK (0x4000U)
898#define I2C_STAT_SLVSEL_SHIFT (14U)
899/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave
900 * function to acknowledge the address, or when the address has been automatically acknowledged.
901 * It is cleared when another address cycle presents an address that does not match an enabled
902 * address on the Slave function, when slave software decides to NACK a matched address, when
903 * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of
904 * Automatic Operation. SLVSEL is not cleared if software NACKs data.
905 * 0b0..Not selected. The Slave function is not currently selected.
906 * 0b1..Selected. The Slave function is currently selected.
907 */
908#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
909#define I2C_STAT_SLVDESEL_MASK (0x8000U)
910#define I2C_STAT_SLVDESEL_SHIFT (15U)
911/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via
912 * INTENSET. This flag can be cleared by writing a 1 to this bit.
913 * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently
914 * selected. That information can be found in the SLVSEL flag.
915 * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag
916 * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
917 */
918#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
919#define I2C_STAT_MONRDY_MASK (0x10000U)
920#define I2C_STAT_MONRDY_SHIFT (16U)
921/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read.
922 * 0b0..No data. The Monitor function does not currently have data available.
923 * 0b1..Data waiting. The Monitor function has data waiting to be read.
924 */
925#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
926#define I2C_STAT_MONOV_MASK (0x20000U)
927#define I2C_STAT_MONOV_SHIFT (17U)
928/*! MONOV - Monitor Overflow flag.
929 * 0b0..No overrun. Monitor data has not overrun.
930 * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not
931 * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
932 */
933#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
934#define I2C_STAT_MONACTIVE_MASK (0x40000U)
935#define I2C_STAT_MONACTIVE_SHIFT (18U)
936/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to
937 * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred
938 * more recently than a bus Stop.
939 * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive.
940 * 0b1..Active. The Monitor function considers the I2C bus to be active.
941 */
942#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
943#define I2C_STAT_MONIDLE_MASK (0x80000U)
944#define I2C_STAT_MONIDLE_SHIFT (19U)
945/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change
946 * from active to inactive. This can be used by software to decide when to process data
947 * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the
948 * INTENSET register. The flag can be cleared by writing a 1 to this bit.
949 * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software.
950 * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
951 */
952#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
953#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U)
954#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U)
955/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been
956 * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock
957 * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus
958 * is idle.
959 * 0b0..No time-out. I2C bus events have not caused a time-out.
960 * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
961 */
962#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
963#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U)
964#define I2C_STAT_SCLTIMEOUT_SHIFT (25U)
965/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the
966 * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
967 * 0b0..No time-out. SCL low time has not caused a time-out.
968 * 0b1..Time-out. SCL low time has caused a time-out.
969 */
970#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
971/*! @} */
972
973/*! @name INTENSET - Interrupt Enable Set and read register. */
974/*! @{ */
975#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U)
976#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U)
977/*! MSTPENDINGEN - Master Pending interrupt Enable.
978 * 0b0..Disabled. The MstPending interrupt is disabled.
979 * 0b1..Enabled. The MstPending interrupt is enabled.
980 */
981#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
982#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U)
983#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U)
984/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable.
985 * 0b0..Disabled. The MstArbLoss interrupt is disabled.
986 * 0b1..Enabled. The MstArbLoss interrupt is enabled.
987 */
988#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
989#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U)
990#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U)
991/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable.
992 * 0b0..Disabled. The MstStStpErr interrupt is disabled.
993 * 0b1..Enabled. The MstStStpErr interrupt is enabled.
994 */
995#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
996#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U)
997#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U)
998/*! SLVPENDINGEN - Slave Pending interrupt Enable.
999 * 0b0..Disabled. The SlvPending interrupt is disabled.
1000 * 0b1..Enabled. The SlvPending interrupt is enabled.
1001 */
1002#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
1003#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U)
1004#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U)
1005/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable.
1006 * 0b0..Disabled. The SlvNotStr interrupt is disabled.
1007 * 0b1..Enabled. The SlvNotStr interrupt is enabled.
1008 */
1009#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
1010#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U)
1011#define I2C_INTENSET_SLVDESELEN_SHIFT (15U)
1012/*! SLVDESELEN - Slave Deselect interrupt Enable.
1013 * 0b0..Disabled. The SlvDeSel interrupt is disabled.
1014 * 0b1..Enabled. The SlvDeSel interrupt is enabled.
1015 */
1016#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
1017#define I2C_INTENSET_MONRDYEN_MASK (0x10000U)
1018#define I2C_INTENSET_MONRDYEN_SHIFT (16U)
1019/*! MONRDYEN - Monitor data Ready interrupt Enable.
1020 * 0b0..Disabled. The MonRdy interrupt is disabled.
1021 * 0b1..Enabled. The MonRdy interrupt is enabled.
1022 */
1023#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
1024#define I2C_INTENSET_MONOVEN_MASK (0x20000U)
1025#define I2C_INTENSET_MONOVEN_SHIFT (17U)
1026/*! MONOVEN - Monitor Overrun interrupt Enable.
1027 * 0b0..Disabled. The MonOv interrupt is disabled.
1028 * 0b1..Enabled. The MonOv interrupt is enabled.
1029 */
1030#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
1031#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U)
1032#define I2C_INTENSET_MONIDLEEN_SHIFT (19U)
1033/*! MONIDLEEN - Monitor Idle interrupt Enable.
1034 * 0b0..Disabled. The MonIdle interrupt is disabled.
1035 * 0b1..Enabled. The MonIdle interrupt is enabled.
1036 */
1037#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
1038#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U)
1039#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U)
1040/*! EVENTTIMEOUTEN - Event time-out interrupt Enable.
1041 * 0b0..Disabled. The Event time-out interrupt is disabled.
1042 * 0b1..Enabled. The Event time-out interrupt is enabled.
1043 */
1044#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
1045#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U)
1046#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U)
1047/*! SCLTIMEOUTEN - SCL time-out interrupt Enable.
1048 * 0b0..Disabled. The SCL time-out interrupt is disabled.
1049 * 0b1..Enabled. The SCL time-out interrupt is enabled.
1050 */
1051#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
1052/*! @} */
1053
1054/*! @name INTENCLR - Interrupt Enable Clear register. */
1055/*! @{ */
1056#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U)
1057#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U)
1058/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding
1059 * bit in the INTENSET register if implemented.
1060 */
1061#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
1062#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U)
1063#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U)
1064/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear.
1065 */
1066#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
1067#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U)
1068#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U)
1069/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear.
1070 */
1071#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
1072#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U)
1073#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U)
1074/*! SLVPENDINGCLR - Slave Pending interrupt clear.
1075 */
1076#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
1077#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U)
1078#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U)
1079/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear.
1080 */
1081#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
1082#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U)
1083#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U)
1084/*! SLVDESELCLR - Slave Deselect interrupt clear.
1085 */
1086#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
1087#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U)
1088#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U)
1089/*! MONRDYCLR - Monitor data Ready interrupt clear.
1090 */
1091#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
1092#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U)
1093#define I2C_INTENCLR_MONOVCLR_SHIFT (17U)
1094/*! MONOVCLR - Monitor Overrun interrupt clear.
1095 */
1096#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
1097#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U)
1098#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U)
1099/*! MONIDLECLR - Monitor Idle interrupt clear.
1100 */
1101#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
1102#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U)
1103#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U)
1104/*! EVENTTIMEOUTCLR - Event time-out interrupt clear.
1105 */
1106#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
1107#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U)
1108#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U)
1109/*! SCLTIMEOUTCLR - SCL time-out interrupt clear.
1110 */
1111#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
1112/*! @} */
1113
1114/*! @name TIMEOUT - Time-out value register. */
1115/*! @{ */
1116#define I2C_TIMEOUT_TOMIN_MASK (0xFU)
1117#define I2C_TIMEOUT_TOMIN_SHIFT (0U)
1118/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum
1119 * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
1120 */
1121#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
1122#define I2C_TIMEOUT_TO_MASK (0xFFF0U)
1123#define I2C_TIMEOUT_TO_SHIFT (4U)
1124/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C
1125 * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation,
1126 * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A
1127 * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after
1128 * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the
1129 * I2C function clock.
1130 */
1131#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
1132/*! @} */
1133
1134/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */
1135/*! @{ */
1136#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU)
1137#define I2C_CLKDIV_DIVVAL_SHIFT (0U)
1138/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that
1139 * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 =
1140 * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is
1141 * divided by 65,536 before use.
1142 */
1143#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
1144/*! @} */
1145
1146/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
1147/*! @{ */
1148#define I2C_INTSTAT_MSTPENDING_MASK (0x1U)
1149#define I2C_INTSTAT_MSTPENDING_SHIFT (0U)
1150/*! MSTPENDING - Master Pending.
1151 */
1152#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
1153#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U)
1154#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U)
1155/*! MSTARBLOSS - Master Arbitration Loss flag.
1156 */
1157#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
1158#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U)
1159#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U)
1160/*! MSTSTSTPERR - Master Start/Stop Error flag.
1161 */
1162#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
1163#define I2C_INTSTAT_SLVPENDING_MASK (0x100U)
1164#define I2C_INTSTAT_SLVPENDING_SHIFT (8U)
1165/*! SLVPENDING - Slave Pending.
1166 */
1167#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
1168#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U)
1169#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U)
1170/*! SLVNOTSTR - Slave Not Stretching status.
1171 */
1172#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
1173#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U)
1174#define I2C_INTSTAT_SLVDESEL_SHIFT (15U)
1175/*! SLVDESEL - Slave Deselected flag.
1176 */
1177#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
1178#define I2C_INTSTAT_MONRDY_MASK (0x10000U)
1179#define I2C_INTSTAT_MONRDY_SHIFT (16U)
1180/*! MONRDY - Monitor Ready.
1181 */
1182#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
1183#define I2C_INTSTAT_MONOV_MASK (0x20000U)
1184#define I2C_INTSTAT_MONOV_SHIFT (17U)
1185/*! MONOV - Monitor Overflow flag.
1186 */
1187#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
1188#define I2C_INTSTAT_MONIDLE_MASK (0x80000U)
1189#define I2C_INTSTAT_MONIDLE_SHIFT (19U)
1190/*! MONIDLE - Monitor Idle flag.
1191 */
1192#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
1193#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U)
1194#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U)
1195/*! EVENTTIMEOUT - Event time-out Interrupt flag.
1196 */
1197#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
1198#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U)
1199#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U)
1200/*! SCLTIMEOUT - SCL time-out Interrupt flag.
1201 */
1202#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
1203/*! @} */
1204
1205/*! @name MSTCTL - Master control register. */
1206/*! @{ */
1207#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U)
1208#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U)
1209/*! MSTCONTINUE - Master Continue.
1210 * 0b0..No effect.
1211 * 0b1..Informs the Master function to continue to the next operation.
1212 */
1213#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
1214#define I2C_MSTCTL_MSTSTART_MASK (0x2U)
1215#define I2C_MSTCTL_MSTSTART_SHIFT (1U)
1216/*! MSTSTART - Master Start control.
1217 * 0b0..No effect.
1218 * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time.
1219 */
1220#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
1221#define I2C_MSTCTL_MSTSTOP_MASK (0x4U)
1222#define I2C_MSTCTL_MSTSTOP_SHIFT (2U)
1223/*! MSTSTOP - Master Stop control.
1224 * 0b0..No effect.
1225 * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave
1226 * if the master is receiving data from the slave (Master Receiver mode).
1227 */
1228#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
1229/*! @} */
1230
1231/*! @name MSTTIME - Master timing configuration. */
1232/*! @{ */
1233#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U)
1234#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U)
1235/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this
1236 * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This
1237 * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters
1238 * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.
1239 * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
1240 * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
1241 * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
1242 * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
1243 * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
1244 * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
1245 * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
1246 * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
1247 */
1248#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
1249#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U)
1250#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U)
1251/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this
1252 * master on SCL. Other masters in a multi-master system could shorten this time. This
1253 * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters
1254 * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.
1255 * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
1256 * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
1257 * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
1258 * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
1259 * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
1260 * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
1261 * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
1262 * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
1263 */
1264#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
1265/*! @} */
1266
1267/*! @name MSTDAT - Combined Master receiver and transmitter data register. */
1268/*! @{ */
1269#define I2C_MSTDAT_DATA_MASK (0xFFU)
1270#define I2C_MSTDAT_DATA_SHIFT (0U)
1271/*! DATA - Master function data register. Read: read the most recently received data for the Master
1272 * function. Write: transmit data using the Master function.
1273 */
1274#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
1275/*! @} */
1276
1277/*! @name SLVCTL - Slave control register. */
1278/*! @{ */
1279#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U)
1280#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U)
1281/*! SLVCONTINUE - Slave Continue.
1282 * 0b0..No effect.
1283 * 0b1..Continue. Informs the Slave function to continue to the next operation. This must done after writing
1284 * transmit data, reading received data, or any other housekeeping related to the next bus operation.
1285 */
1286#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
1287#define I2C_SLVCTL_SLVNACK_MASK (0x2U)
1288#define I2C_SLVCTL_SLVNACK_SHIFT (1U)
1289/*! SLVNACK - Slave NACK.
1290 * 0b0..No effect.
1291 * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).
1292 */
1293#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
1294/*! @} */
1295
1296/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */
1297/*! @{ */
1298#define I2C_SLVDAT_DATA_MASK (0xFFU)
1299#define I2C_SLVDAT_DATA_SHIFT (0U)
1300/*! DATA - Slave function data register. Read: read the most recently received data for the Slave
1301 * function. Write: transmit data using the Slave function.
1302 */
1303#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
1304/*! @} */
1305
1306/*! @name SLVADR - Slave address register. */
1307/*! @{ */
1308#define I2C_SLVADR_SADISABLE_MASK (0x1U)
1309#define I2C_SLVADR_SADISABLE_SHIFT (0U)
1310/*! SADISABLE - Slave Address n Disable.
1311 * 0b0..Enabled. Slave Address n is enabled.
1312 * 0b1..Ignored Slave Address n is ignored.
1313 */
1314#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
1315#define I2C_SLVADR_SLVADR_MASK (0xFEU)
1316#define I2C_SLVADR_SLVADR_SHIFT (1U)
1317/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1318 */
1319#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
1320/*! @} */
1321
1322/* The count of I2C_SLVADR */
1323#define I2C_SLVADR_COUNT (4U)
1324
1325/*! @name SLVQUAL0 - Slave Qualification for address 0. */
1326/*! @{ */
1327#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U)
1328#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U)
1329/*! QUALMODE0 - Qualify mode for slave address 0.
1330 * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
1331 * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
1332 */
1333#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
1334#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU)
1335#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U)
1336/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to
1337 * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is
1338 * set to 1 will cause an automatic match of the corresponding bit of the received address when it
1339 * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for
1340 * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0
1341 * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).
1342 */
1343#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
1344/*! @} */
1345
1346/*! @name MONRXDAT - Monitor receiver data register. */
1347/*! @{ */
1348#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU)
1349#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U)
1350/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.
1351 */
1352#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
1353#define I2C_MONRXDAT_MONSTART_MASK (0x100U)
1354#define I2C_MONRXDAT_MONSTART_SHIFT (8U)
1355/*! MONSTART - Monitor Received Start.
1356 * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus.
1357 * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus.
1358 */
1359#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
1360#define I2C_MONRXDAT_MONRESTART_MASK (0x200U)
1361#define I2C_MONRXDAT_MONRESTART_SHIFT (9U)
1362/*! MONRESTART - Monitor Received Repeated Start.
1363 * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
1364 * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
1365 */
1366#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
1367#define I2C_MONRXDAT_MONNACK_MASK (0x400U)
1368#define I2C_MONRXDAT_MONNACK_SHIFT (10U)
1369/*! MONNACK - Monitor Received NACK.
1370 * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
1371 * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
1372 */
1373#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
1374/*! @} */
1375
1376
1377/*!
1378 * @}
1379 */ /* end of group I2C_Register_Masks */
1380
1381
1382/* I2C - Peripheral instance base addresses */
1383/** Peripheral I2C0 base address */
1384#define I2C0_BASE (0x40050000u)
1385/** Peripheral I2C0 base pointer */
1386#define I2C0 ((I2C_Type *)I2C0_BASE)
1387/** Array initializer of I2C peripheral base addresses */
1388#define I2C_BASE_ADDRS { I2C0_BASE }
1389/** Array initializer of I2C peripheral base pointers */
1390#define I2C_BASE_PTRS { I2C0 }
1391/** Interrupt vectors for the I2C peripheral type */
1392#define I2C_IRQS { I2C0_IRQn }
1393
1394/*!
1395 * @}
1396 */ /* end of group I2C_Peripheral_Access_Layer */
1397
1398
1399/* ----------------------------------------------------------------------------
1400 -- IOCON Peripheral Access Layer
1401 ---------------------------------------------------------------------------- */
1402
1403/*!
1404 * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer
1405 * @{
1406 */
1407
1408/** IOCON - Register Layout Typedef */
1409typedef struct {
1410 __IO uint32_t PIO[19]; /**< Digital I/O control for pins PIO0_17..Digital I/O control for pins PIO0_14, array offset: 0x0, array step: 0x4 */
1411} IOCON_Type;
1412
1413/* ----------------------------------------------------------------------------
1414 -- IOCON Register Masks
1415 ---------------------------------------------------------------------------- */
1416
1417/*!
1418 * @addtogroup IOCON_Register_Masks IOCON Register Masks
1419 * @{
1420 */
1421
1422/*! @name PIO - Digital I/O control for pins PIO0_17..Digital I/O control for pins PIO0_14 */
1423/*! @{ */
1424#define IOCON_PIO_MODE_MASK (0x18U)
1425#define IOCON_PIO_MODE_SHIFT (3U)
1426/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control).
1427 * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled).
1428 * 0b01..Pull-down. Pull-down resistor enabled.
1429 * 0b10..Pull-up. Pull-up resistor enabled.
1430 * 0b11..Repeater. Repeater mode.
1431 */
1432#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
1433#define IOCON_PIO_HYS_MASK (0x20U)
1434#define IOCON_PIO_HYS_SHIFT (5U)
1435/*! HYS - Hysteresis.
1436 * 0b0..Disable
1437 * 0b1..Enable
1438 */
1439#define IOCON_PIO_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_HYS_SHIFT)) & IOCON_PIO_HYS_MASK)
1440#define IOCON_PIO_INV_MASK (0x40U)
1441#define IOCON_PIO_INV_SHIFT (6U)
1442/*! INV - Invert input
1443 * 0b0..Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
1444 * 0b1..Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
1445 */
1446#define IOCON_PIO_INV(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INV_SHIFT)) & IOCON_PIO_INV_MASK)
1447#define IOCON_PIO_I2CMODE_MASK (0x300U)
1448#define IOCON_PIO_I2CMODE_SHIFT (8U)
1449/*! I2CMODE - Selects I2C mode.
1450 * 0b00..Standard mode/ Fast-mode I2C.
1451 * 0b01..Standard GPIO functionality. Requires external pull-up for GPIO output function.
1452 * 0b10..Fast-mode Plus I2C
1453 * 0b11..Reserved
1454 */
1455#define IOCON_PIO_I2CMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CMODE_SHIFT)) & IOCON_PIO_I2CMODE_MASK)
1456#define IOCON_PIO_OD_MASK (0x400U)
1457#define IOCON_PIO_OD_SHIFT (10U)
1458/*! OD - Open-drain mode.
1459 * 0b0..Disable.
1460 * 0b1..Open-drain mode enabled. Remark: This is not a true open-drain mode.
1461 */
1462#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
1463#define IOCON_PIO_S_MODE_MASK (0x1800U)
1464#define IOCON_PIO_S_MODE_SHIFT (11U)
1465/*! S_MODE - Digital filter sample mode.
1466 * 0b00..Bypass input filter.
1467 * 0b01..1 clock cycle. Input pulses shorter than one filter clock are rejected.
1468 * 0b10..2 clock cycles. Input pulses shorter than two filter clocks are rejected.
1469 * 0b11..3 clock cycles. Input pulses shorter than three filter clocks are rejected.
1470 */
1471#define IOCON_PIO_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_S_MODE_SHIFT)) & IOCON_PIO_S_MODE_MASK)
1472#define IOCON_PIO_CLK_DIV_MASK (0xE000U)
1473#define IOCON_PIO_CLK_DIV_SHIFT (13U)
1474/*! CLK_DIV - Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
1475 * 0b000..IOCONCLKDIV0
1476 * 0b001..IOCONCLKDIV1
1477 * 0b010..IOCONCLKDIV2
1478 * 0b011..IOCONCLKDIV3
1479 * 0b100..IOCONCLKDIV4
1480 * 0b101..IOCONCLKDIV5
1481 * 0b110..IOCONCLKDIV6
1482 */
1483#define IOCON_PIO_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_CLK_DIV_SHIFT)) & IOCON_PIO_CLK_DIV_MASK)
1484/*! @} */
1485
1486/* The count of IOCON_PIO */
1487#define IOCON_PIO_COUNT (19U)
1488
1489
1490/*!
1491 * @}
1492 */ /* end of group IOCON_Register_Masks */
1493
1494
1495/* IOCON - Peripheral instance base addresses */
1496/** Peripheral IOCON base address */
1497#define IOCON_BASE (0x40044000u)
1498/** Peripheral IOCON base pointer */
1499#define IOCON ((IOCON_Type *)IOCON_BASE)
1500/** Array initializer of IOCON peripheral base addresses */
1501#define IOCON_BASE_ADDRS { IOCON_BASE }
1502/** Array initializer of IOCON peripheral base pointers */
1503#define IOCON_BASE_PTRS { IOCON }
1504
1505#define IOCON_INDEX_PIO0_17 (0 )
1506#define IOCON_INDEX_PIO0_13 (1 )
1507#define IOCON_INDEX_PIO0_12 (2 )
1508#define IOCON_INDEX_PIO0_5 (3 )
1509#define IOCON_INDEX_PIO0_4 (4 )
1510#define IOCON_INDEX_PIO0_3 (5 )
1511#define IOCON_INDEX_PIO0_2 (6 )
1512#define IOCON_INDEX_PIO0_11 (7 )
1513#define IOCON_INDEX_PIO0_10 (8 )
1514#define IOCON_INDEX_PIO0_16 (9 )
1515#define IOCON_INDEX_PIO0_15 (10)
1516#define IOCON_INDEX_PIO0_1 (11)
1517#define IOCON_INDEX_PIO0_9 (13)
1518#define IOCON_INDEX_PIO0_8 (14)
1519#define IOCON_INDEX_PIO0_7 (15)
1520#define IOCON_INDEX_PIO0_6 (16)
1521#define IOCON_INDEX_PIO0_0 (17)
1522#define IOCON_INDEX_PIO0_14 (18)
1523
1524
1525/*!
1526 * @}
1527 */ /* end of group IOCON_Peripheral_Access_Layer */
1528
1529
1530/* ----------------------------------------------------------------------------
1531 -- MRT Peripheral Access Layer
1532 ---------------------------------------------------------------------------- */
1533
1534/*!
1535 * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
1536 * @{
1537 */
1538
1539/** MRT - Register Layout Typedef */
1540typedef struct {
1541 struct { /* offset: 0x0, array step: 0x10 */
1542 __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */
1543 __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */
1544 __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */
1545 __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */
1546 } CHANNEL[4];
1547 uint8_t RESERVED_0[176];
1548 __I uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance., offset: 0xF0 */
1549 __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */
1550 __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */
1551} MRT_Type;
1552
1553/* ----------------------------------------------------------------------------
1554 -- MRT Register Masks
1555 ---------------------------------------------------------------------------- */
1556
1557/*!
1558 * @addtogroup MRT_Register_Masks MRT Register Masks
1559 * @{
1560 */
1561
1562/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */
1563/*! @{ */
1564#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0x7FFFFFFFU)
1565#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U)
1566/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT
1567 * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to
1568 * this bit field starts the timer immediately. If the timer is running, writing a zero to this
1569 * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer
1570 * stops at the end of the time interval.
1571 */
1572#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
1573#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U)
1574#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U)
1575/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register.
1576 * This bit is write-only. Reading this bit always returns 0.
1577 * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the
1578 * time interval if the repeat mode is selected.
1579 * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
1580 */
1581#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
1582/*! @} */
1583
1584/* The count of MRT_CHANNEL_INTVAL */
1585#define MRT_CHANNEL_INTVAL_COUNT (4U)
1586
1587/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */
1588/*! @{ */
1589#define MRT_CHANNEL_TIMER_VALUE_MASK (0x7FFFFFFFU)
1590#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U)
1591/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn
1592 * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval
1593 * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn
1594 * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields
1595 * returns -1 (0x00FF FFFF).
1596 */
1597#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
1598/*! @} */
1599
1600/* The count of MRT_CHANNEL_TIMER */
1601#define MRT_CHANNEL_TIMER_COUNT (4U)
1602
1603/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */
1604/*! @{ */
1605#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U)
1606#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U)
1607/*! INTEN - Enable the TIMERn interrupt.
1608 * 0b0..Disabled. TIMERn interrupt is disabled.
1609 * 0b1..Enabled. TIMERn interrupt is enabled.
1610 */
1611#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
1612#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U)
1613#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U)
1614/*! MODE - Selects timer mode.
1615 * 0b00..Repeat interrupt mode.
1616 * 0b01..One-shot interrupt mode.
1617 * 0b10..One-shot stall mode.
1618 * 0b11..Reserved.
1619 */
1620#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
1621/*! @} */
1622
1623/* The count of MRT_CHANNEL_CTRL */
1624#define MRT_CHANNEL_CTRL_COUNT (4U)
1625
1626/*! @name CHANNEL_STAT - MRT Status register. */
1627/*! @{ */
1628#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U)
1629#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U)
1630/*! INTFLAG - Monitors the interrupt flag.
1631 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
1632 * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If
1633 * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt
1634 * are raised. Writing a 1 to this bit clears the interrupt request.
1635 */
1636#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
1637#define MRT_CHANNEL_STAT_RUN_MASK (0x2U)
1638#define MRT_CHANNEL_STAT_RUN_SHIFT (1U)
1639/*! RUN - Indicates the state of TIMERn. This bit is read-only.
1640 * 0b0..Idle state. TIMERn is stopped.
1641 * 0b1..Running. TIMERn is running.
1642 */
1643#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
1644/*! @} */
1645
1646/* The count of MRT_CHANNEL_STAT */
1647#define MRT_CHANNEL_STAT_COUNT (4U)
1648
1649/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance. */
1650/*! @{ */
1651#define MRT_MODCFG_NOC_MASK (0xFU)
1652#define MRT_MODCFG_NOC_SHIFT (0U)
1653/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.)
1654 */
1655#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
1656#define MRT_MODCFG_NOB_MASK (0x1F0U)
1657#define MRT_MODCFG_NOB_SHIFT (4U)
1658/*! NOB - Identifies the number of timer bits in this MRT. (31 bits wide on this device.)
1659 */
1660#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
1661/*! @} */
1662
1663/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */
1664/*! @{ */
1665#define MRT_IDLE_CH_CHAN_MASK (0xF0U)
1666#define MRT_IDLE_CH_CHAN_SHIFT (4U)
1667/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is
1668 * positioned such that it can be used as an offset from the MRT base address in order to access
1669 * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See
1670 * text above for more details.
1671 */
1672#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
1673/*! @} */
1674
1675/*! @name IRQ_FLAG - Global interrupt flag register */
1676/*! @{ */
1677#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U)
1678#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U)
1679/*! GFLAG0 - Monitors the interrupt flag of TIMER0.
1680 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
1681 * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If
1682 * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global
1683 * interrupt are raised. Writing a 1 to this bit clears the interrupt request.
1684 */
1685#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
1686#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U)
1687#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U)
1688/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0.
1689 */
1690#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
1691#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U)
1692#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U)
1693/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0.
1694 */
1695#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
1696#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U)
1697#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U)
1698/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0.
1699 */
1700#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
1701/*! @} */
1702
1703
1704/*!
1705 * @}
1706 */ /* end of group MRT_Register_Masks */
1707
1708
1709/* MRT - Peripheral instance base addresses */
1710/** Peripheral MRT0 base address */
1711#define MRT0_BASE (0x40004000u)
1712/** Peripheral MRT0 base pointer */
1713#define MRT0 ((MRT_Type *)MRT0_BASE)
1714/** Array initializer of MRT peripheral base addresses */
1715#define MRT_BASE_ADDRS { MRT0_BASE }
1716/** Array initializer of MRT peripheral base pointers */
1717#define MRT_BASE_PTRS { MRT0 }
1718/** Interrupt vectors for the MRT peripheral type */
1719#define MRT_IRQS { MRT0_IRQn }
1720
1721/*!
1722 * @}
1723 */ /* end of group MRT_Peripheral_Access_Layer */
1724
1725
1726/* ----------------------------------------------------------------------------
1727 -- MTB Peripheral Access Layer
1728 ---------------------------------------------------------------------------- */
1729
1730/*!
1731 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
1732 * @{
1733 */
1734
1735/** MTB - Register Layout Typedef */
1736typedef struct {
1737 __IO uint32_t POSITION; /**< POSITION Register, offset: 0x0 */
1738 __IO uint32_t MASTER; /**< MASTER Register, offset: 0x4 */
1739 __IO uint32_t FLOW; /**< FLOW Register, offset: 0x8 */
1740 __I uint32_t BASE; /**< Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB SRAM location, by a debug agent., offset: 0xC */
1741} MTB_Type;
1742
1743/* ----------------------------------------------------------------------------
1744 -- MTB Register Masks
1745 ---------------------------------------------------------------------------- */
1746
1747/*!
1748 * @addtogroup MTB_Register_Masks MTB Register Masks
1749 * @{
1750 */
1751
1752/*! @name POSITION - POSITION Register */
1753/*! @{ */
1754#define MTB_POSITION_WRAP_MASK (0x4U)
1755#define MTB_POSITION_WRAP_SHIFT (2U)
1756/*! WRAP - This bit is set to 1 automatically when the POINTER value wraps as determined by the
1757 * MASTER.MASK field in the MASTER Trace Control Register.
1758 */
1759#define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
1760#define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U)
1761#define MTB_POSITION_POINTER_SHIFT (3U)
1762/*! POINTER - Trace packet location pointer. Because a packet consists of two words, the POINTER
1763 * field is the location of the first word of a packet. This field contains bits [31:3] of the
1764 * address, in the SRAM, where the next trace packet will be written. The field points to an unused
1765 * location and is automatically incremented. A debug agent can calculate the system address, on
1766 * the AHB-Lite bus, of the SRAM location pointed to by the POSITION register using the following
1767 * equation: system address = BASE + ((P + (2AWIDTH - (BASE MOD 2AWIDTH))) MOD 2AWIDTH). Where P =
1768 * POSITION AND 0xFFFF_FFF8. Where BASE is the BASE register value
1769 */
1770#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
1771/*! @} */
1772
1773/*! @name MASTER - MASTER Register */
1774/*! @{ */
1775#define MTB_MASTER_MASK_MASK (0x1FU)
1776#define MTB_MASTER_MASK_SHIFT (0U)
1777/*! MASK - This value determines the maximum size of the trace buffer in SRAM. It specifies the
1778 * most-significant bit of the POSITION.POINTER field that can be updated by automatic increment. If
1779 * the trace tries to advance past this power of two, the POSITION.WRAP bit is set to 1, the
1780 * POSITION.POINTER[MASK:0] bits are set to zero, and the POSITION.POINTER[AWIDTH-4:MASK+1] bits
1781 * remain unchanged. This field causes the trace packet information to be stored in a circular buffer
1782 * of size 2(MASK+4) bytes, that can be positioned in memory at multiples of this size. Valid
1783 * values of this field are zero to AWIDTH-4. Values greater than the maximum have the same effect
1784 * as the maximum.
1785 */
1786#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
1787#define MTB_MASTER_TSTARTEN_MASK (0x20U)
1788#define MTB_MASTER_TSTARTEN_SHIFT (5U)
1789/*! TSTARTEN - Trace start input enable. If this bit is 1 and the TSTART signal is HIGH, then the EN
1790 * bit is set to 1. Tracing continues until a stop condition occurs.
1791 */
1792#define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
1793#define MTB_MASTER_TSTOPEN_MASK (0x40U)
1794#define MTB_MASTER_TSTOPEN_SHIFT (6U)
1795/*! TSTOPEN - Trace stop input enable. If this bit is 1 and the TSTOP signal is HIGH, then the EN
1796 * bit is set to 0. If a trace packet is being written to memory, the write is completed before
1797 * tracing is stopped.
1798 */
1799#define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
1800#define MTB_MASTER_SFRWPRIV_MASK (0x80U)
1801#define MTB_MASTER_SFRWPRIV_SHIFT (7U)
1802/*! SFRWPRIV - Special Function Register Write Privilege bit. If this bit is 0, then User or
1803 * Privileged AHB-Lite read and write accesses to the Special Function Registers are permitted. If this
1804 * bit is 1, then only Privileged write accesses are permitted and User write accesses are
1805 * ignored. The HPROT[1] signal determines if an access is User or Privileged.
1806 */
1807#define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
1808#define MTB_MASTER_RAMPRIV_MASK (0x100U)
1809#define MTB_MASTER_RAMPRIV_SHIFT (8U)
1810/*! RAMPRIV - SRAM Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write
1811 * accesses to the SRAM are permitted. If this bit is 1, then only Privileged AHB-Lite read and
1812 * write accesses to the SRAM are permitted and User accesses are RAZ/WI. The HPROT[1] signal
1813 * determines if an access is User or Privileged.
1814 */
1815#define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
1816#define MTB_MASTER_HALTREQ_MASK (0x200U)
1817#define MTB_MASTER_HALTREQ_SHIFT (9U)
1818/*! HALTREQ - Halt request bit. This bit is connected to the halt request signal of the trace logic,
1819 * EDBGRQ. When HALTREQ is set to 1, EDBGRQ is asserted if DBGEN is also HIGH. The HALTREQ bit
1820 * can be automatically set to 1 using the FLOW.WATERMARK field.
1821 */
1822#define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
1823#define MTB_MASTER_EN_MASK (0x80000000U)
1824#define MTB_MASTER_EN_SHIFT (31U)
1825/*! EN - Main trace enable bit. When this bit is 1 trace data is written into the SRAM memory
1826 * location addressed by POSITION.POINTER. The POSITION.POINTER value auto increments after the trace
1827 * data packet is written. The EN bit can be automatically set to 0 using the FLOW.WATERMARK field
1828 * and the FLOW.AUTOSTOP bit. The EN bit is automatically set to 1 if the TSTARTEN bit is 1 and
1829 * the TSTART signal is HIGH. The EN bit is automatically set to 0 if TSTOPEN bit is 1 and the
1830 * TSTOP signal is HIGH.
1831 */
1832#define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
1833/*! @} */
1834
1835/*! @name FLOW - FLOW Register */
1836/*! @{ */
1837#define MTB_FLOW_AUTOSTOP_MASK (0x1U)
1838#define MTB_FLOW_AUTOSTOP_SHIFT (0U)
1839/*! AUTOSTOP - If this bit is 1 and WATERMARK is equal to POSITION.POINTER, then the MASTER.EN bit
1840 * is automatically set to 0. This stops tracing.
1841 */
1842#define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
1843#define MTB_FLOW_AUTOHALT_MASK (0x2U)
1844#define MTB_FLOW_AUTOHALT_SHIFT (1U)
1845/*! AUTOHALT - If this bit is 1 and WATERMARK is equal to POSITION.POINTER, then the MASTER.HALTREQ
1846 * bit is automatically set to 1. If the DBGEN signal is HIGH, the MTB asserts this halt request
1847 * to the Cortex-M0+ processor by asserting the EDBGRQ signal.
1848 */
1849#define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
1850#define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U)
1851#define MTB_FLOW_WATERMARK_SHIFT (3U)
1852/*! WATERMARK - WATERMARK value. This field contains an address in the same format as the
1853 * POSITION.POINTER field. When the POSITION.POINTER matches the WATERMARK field value, actions defined by
1854 * the AUTOHALT and AUTOSTOP bits are performed.
1855 */
1856#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
1857/*! @} */
1858
1859/*! @name BASE - Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB SRAM location, by a debug agent. */
1860/*! @{ */
1861#define MTB_BASE_BASE_MASK (0xFFFFFFFFU)
1862#define MTB_BASE_BASE_SHIFT (0U)
1863/*! BASE - The value provided is the value of the SRAMBASEADDR[31:0] signal.
1864 */
1865#define MTB_BASE_BASE(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASE_SHIFT)) & MTB_BASE_BASE_MASK)
1866/*! @} */
1867
1868
1869/*!
1870 * @}
1871 */ /* end of group MTB_Register_Masks */
1872
1873
1874/* MTB - Peripheral instance base addresses */
1875/** Peripheral MTB base address */
1876#define MTB_BASE (0x14000000u)
1877/** Peripheral MTB base pointer */
1878#define MTB ((MTB_Type *)MTB_BASE)
1879/** Array initializer of MTB peripheral base addresses */
1880#define MTB_BASE_ADDRS { MTB_BASE }
1881/** Array initializer of MTB peripheral base pointers */
1882#define MTB_BASE_PTRS { MTB }
1883
1884/*!
1885 * @}
1886 */ /* end of group MTB_Peripheral_Access_Layer */
1887
1888
1889/* ----------------------------------------------------------------------------
1890 -- PINT Peripheral Access Layer
1891 ---------------------------------------------------------------------------- */
1892
1893/*!
1894 * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
1895 * @{
1896 */
1897
1898/** PINT - Register Layout Typedef */
1899typedef struct {
1900 __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */
1901 __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */
1902 __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */
1903 __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */
1904 __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */
1905 __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */
1906 __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */
1907 __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */
1908 __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */
1909 __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */
1910 __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */
1911 __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */
1912 __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */
1913} PINT_Type;
1914
1915/* ----------------------------------------------------------------------------
1916 -- PINT Register Masks
1917 ---------------------------------------------------------------------------- */
1918
1919/*!
1920 * @addtogroup PINT_Register_Masks PINT Register Masks
1921 * @{
1922 */
1923
1924/*! @name ISEL - Pin Interrupt Mode register */
1925/*! @{ */
1926#define PINT_ISEL_PMODE_MASK (0xFFU)
1927#define PINT_ISEL_PMODE_SHIFT (0U)
1928/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt
1929 * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive
1930 */
1931#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
1932/*! @} */
1933
1934/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */
1935/*! @{ */
1936#define PINT_IENR_ENRL_MASK (0xFFU)
1937#define PINT_IENR_ENRL_SHIFT (0U)
1938/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the
1939 * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable
1940 * rising edge or level interrupt.
1941 */
1942#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
1943/*! @} */
1944
1945/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */
1946/*! @{ */
1947#define PINT_SIENR_SETENRL_MASK (0xFFU)
1948#define PINT_SIENR_SETENRL_SHIFT (0U)
1949/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n
1950 * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.
1951 */
1952#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
1953/*! @} */
1954
1955/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */
1956/*! @{ */
1957#define PINT_CIENR_CENRL_MASK (0xFFU)
1958#define PINT_CIENR_CENRL_SHIFT (0U)
1959/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit
1960 * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level
1961 * interrupt.
1962 */
1963#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
1964/*! @} */
1965
1966/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */
1967/*! @{ */
1968#define PINT_IENF_ENAF_MASK (0xFFU)
1969#define PINT_IENF_ENAF_SHIFT (0U)
1970/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt.
1971 * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt
1972 * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active
1973 * interrupt level HIGH.
1974 */
1975#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
1976/*! @} */
1977
1978/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */
1979/*! @{ */
1980#define PINT_SIENF_SETENAF_MASK (0xFFU)
1981#define PINT_SIENF_SETENAF_SHIFT (0U)
1982/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n
1983 * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable
1984 * falling edge interrupt.
1985 */
1986#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
1987/*! @} */
1988
1989/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */
1990/*! @{ */
1991#define PINT_CIENF_CENAF_MASK (0xFFU)
1992#define PINT_CIENF_CENAF_SHIFT (0U)
1993/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n
1994 * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or
1995 * falling edge interrupt disabled.
1996 */
1997#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
1998/*! @} */
1999
2000/*! @name RISE - Pin interrupt rising edge register */
2001/*! @{ */
2002#define PINT_RISE_RDET_MASK (0xFFU)
2003#define PINT_RISE_RDET_SHIFT (0U)
2004/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read
2005 * 0: No rising edge has been detected on this pin since Reset or the last time a one was written
2006 * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the
2007 * last time a one was written to this bit. Write 1: clear rising edge detection for this pin.
2008 */
2009#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
2010/*! @} */
2011
2012/*! @name FALL - Pin interrupt falling edge register */
2013/*! @{ */
2014#define PINT_FALL_FDET_MASK (0xFFU)
2015#define PINT_FALL_FDET_SHIFT (0U)
2016/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read
2017 * 0: No falling edge has been detected on this pin since Reset or the last time a one was
2018 * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or
2019 * the last time a one was written to this bit. Write 1: clear falling edge detection for this
2020 * pin.
2021 */
2022#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
2023/*! @} */
2024
2025/*! @name IST - Pin interrupt status register */
2026/*! @{ */
2027#define PINT_IST_PSTAT_MASK (0xFFU)
2028#define PINT_IST_PSTAT_SHIFT (0U)
2029/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts
2030 * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for
2031 * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this
2032 * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin.
2033 * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).
2034 */
2035#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
2036/*! @} */
2037
2038/*! @name PMCTRL - Pattern match interrupt control register */
2039/*! @{ */
2040#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U)
2041#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U)
2042/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.
2043 * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.
2044 * 0b1..Pattern match. Interrupts are driven in response to pattern matches.
2045 */
2046#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
2047#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U)
2048#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U)
2049/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.
2050 * 0b0..Disabled. RXEV output to the CPU is disabled.
2051 * 0b1..Enabled. RXEV output to the CPU is enabled.
2052 */
2053#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
2054#define PINT_PMCTRL_PMAT_MASK (0xFF000000U)
2055#define PINT_PMCTRL_PMAT_SHIFT (24U)
2056/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field
2057 * indicates that the corresponding product term is matched by the current state of the appropriate
2058 * inputs.
2059 */
2060#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
2061/*! @} */
2062
2063/*! @name PMSRC - Pattern match interrupt bit-slice source register */
2064/*! @{ */
2065#define PINT_PMSRC_SRC0_MASK (0x700U)
2066#define PINT_PMSRC_SRC0_SHIFT (8U)
2067/*! SRC0 - Selects the input source for bit slice 0
2068 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.
2069 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0.
2070 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0.
2071 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0.
2072 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0.
2073 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0.
2074 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0.
2075 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0.
2076 */
2077#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
2078#define PINT_PMSRC_SRC1_MASK (0x3800U)
2079#define PINT_PMSRC_SRC1_SHIFT (11U)
2080/*! SRC1 - Selects the input source for bit slice 1
2081 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.
2082 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1.
2083 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1.
2084 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1.
2085 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1.
2086 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1.
2087 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1.
2088 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1.
2089 */
2090#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
2091#define PINT_PMSRC_SRC2_MASK (0x1C000U)
2092#define PINT_PMSRC_SRC2_SHIFT (14U)
2093/*! SRC2 - Selects the input source for bit slice 2
2094 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.
2095 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2.
2096 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2.
2097 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2.
2098 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2.
2099 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2.
2100 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2.
2101 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2.
2102 */
2103#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
2104#define PINT_PMSRC_SRC3_MASK (0xE0000U)
2105#define PINT_PMSRC_SRC3_SHIFT (17U)
2106/*! SRC3 - Selects the input source for bit slice 3
2107 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3.
2108 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3.
2109 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3.
2110 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3.
2111 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3.
2112 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3.
2113 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3.
2114 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3.
2115 */
2116#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
2117#define PINT_PMSRC_SRC4_MASK (0x700000U)
2118#define PINT_PMSRC_SRC4_SHIFT (20U)
2119/*! SRC4 - Selects the input source for bit slice 4
2120 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.
2121 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4.
2122 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4.
2123 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4.
2124 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4.
2125 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4.
2126 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4.
2127 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4.
2128 */
2129#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
2130#define PINT_PMSRC_SRC5_MASK (0x3800000U)
2131#define PINT_PMSRC_SRC5_SHIFT (23U)
2132/*! SRC5 - Selects the input source for bit slice 5
2133 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.
2134 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5.
2135 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5.
2136 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5.
2137 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5.
2138 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5.
2139 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5.
2140 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5.
2141 */
2142#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
2143#define PINT_PMSRC_SRC6_MASK (0x1C000000U)
2144#define PINT_PMSRC_SRC6_SHIFT (26U)
2145/*! SRC6 - Selects the input source for bit slice 6
2146 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.
2147 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6.
2148 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6.
2149 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6.
2150 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6.
2151 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6.
2152 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6.
2153 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6.
2154 */
2155#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
2156#define PINT_PMSRC_SRC7_MASK (0xE0000000U)
2157#define PINT_PMSRC_SRC7_SHIFT (29U)
2158/*! SRC7 - Selects the input source for bit slice 7
2159 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7.
2160 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7.
2161 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7.
2162 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7.
2163 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7.
2164 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7.
2165 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7.
2166 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7.
2167 */
2168#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
2169/*! @} */
2170
2171/*! @name PMCFG - Pattern match interrupt bit slice configuration register */
2172/*! @{ */
2173#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U)
2174#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U)
2175/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint.
2176 * 0b0..No effect. Slice 0 is not an endpoint.
2177 * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.
2178 */
2179#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
2180#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U)
2181#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U)
2182/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint.
2183 * 0b0..No effect. Slice 1 is not an endpoint.
2184 * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.
2185 */
2186#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
2187#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U)
2188#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U)
2189/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint.
2190 * 0b0..No effect. Slice 2 is not an endpoint.
2191 * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.
2192 */
2193#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
2194#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U)
2195#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U)
2196/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint.
2197 * 0b0..No effect. Slice 3 is not an endpoint.
2198 * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.
2199 */
2200#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
2201#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U)
2202#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U)
2203/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint.
2204 * 0b0..No effect. Slice 4 is not an endpoint.
2205 * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.
2206 */
2207#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
2208#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U)
2209#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U)
2210/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint.
2211 * 0b0..No effect. Slice 5 is not an endpoint.
2212 * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.
2213 */
2214#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
2215#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U)
2216#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U)
2217/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint.
2218 * 0b0..No effect. Slice 6 is not an endpoint.
2219 * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.
2220 */
2221#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
2222#define PINT_PMCFG_CFG0_MASK (0x700U)
2223#define PINT_PMCFG_CFG0_SHIFT (8U)
2224/*! CFG0 - Specifies the match contribution condition for bit slice 0.
2225 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
2226 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
2227 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2228 * PMSRC registers are written to.
2229 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
2230 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2231 * PMSRC registers are written to.
2232 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
2233 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
2234 * cleared when the PMCFG or the PMSRC registers are written to.
2235 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
2236 * 0b101..Low level. Match occurs when there is a low level on the specified input.
2237 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
2238 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
2239 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
2240 * is cleared after one clock cycle.
2241 */
2242#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
2243#define PINT_PMCFG_CFG1_MASK (0x3800U)
2244#define PINT_PMCFG_CFG1_SHIFT (11U)
2245/*! CFG1 - Specifies the match contribution condition for bit slice 1.
2246 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
2247 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
2248 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2249 * PMSRC registers are written to.
2250 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
2251 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2252 * PMSRC registers are written to.
2253 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
2254 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
2255 * cleared when the PMCFG or the PMSRC registers are written to.
2256 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
2257 * 0b101..Low level. Match occurs when there is a low level on the specified input.
2258 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
2259 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
2260 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
2261 * is cleared after one clock cycle.
2262 */
2263#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
2264#define PINT_PMCFG_CFG2_MASK (0x1C000U)
2265#define PINT_PMCFG_CFG2_SHIFT (14U)
2266/*! CFG2 - Specifies the match contribution condition for bit slice 2.
2267 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
2268 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
2269 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2270 * PMSRC registers are written to.
2271 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
2272 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2273 * PMSRC registers are written to.
2274 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
2275 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
2276 * cleared when the PMCFG or the PMSRC registers are written to.
2277 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
2278 * 0b101..Low level. Match occurs when there is a low level on the specified input.
2279 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
2280 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
2281 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
2282 * is cleared after one clock cycle.
2283 */
2284#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
2285#define PINT_PMCFG_CFG3_MASK (0xE0000U)
2286#define PINT_PMCFG_CFG3_SHIFT (17U)
2287/*! CFG3 - Specifies the match contribution condition for bit slice 3.
2288 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
2289 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
2290 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2291 * PMSRC registers are written to.
2292 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
2293 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2294 * PMSRC registers are written to.
2295 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
2296 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
2297 * cleared when the PMCFG or the PMSRC registers are written to.
2298 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
2299 * 0b101..Low level. Match occurs when there is a low level on the specified input.
2300 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
2301 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
2302 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
2303 * is cleared after one clock cycle.
2304 */
2305#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
2306#define PINT_PMCFG_CFG4_MASK (0x700000U)
2307#define PINT_PMCFG_CFG4_SHIFT (20U)
2308/*! CFG4 - Specifies the match contribution condition for bit slice 4.
2309 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
2310 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
2311 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2312 * PMSRC registers are written to.
2313 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
2314 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2315 * PMSRC registers are written to.
2316 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
2317 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
2318 * cleared when the PMCFG or the PMSRC registers are written to.
2319 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
2320 * 0b101..Low level. Match occurs when there is a low level on the specified input.
2321 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
2322 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
2323 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
2324 * is cleared after one clock cycle.
2325 */
2326#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
2327#define PINT_PMCFG_CFG5_MASK (0x3800000U)
2328#define PINT_PMCFG_CFG5_SHIFT (23U)
2329/*! CFG5 - Specifies the match contribution condition for bit slice 5.
2330 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
2331 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
2332 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2333 * PMSRC registers are written to.
2334 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
2335 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2336 * PMSRC registers are written to.
2337 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
2338 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
2339 * cleared when the PMCFG or the PMSRC registers are written to.
2340 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
2341 * 0b101..Low level. Match occurs when there is a low level on the specified input.
2342 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
2343 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
2344 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
2345 * is cleared after one clock cycle.
2346 */
2347#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
2348#define PINT_PMCFG_CFG6_MASK (0x1C000000U)
2349#define PINT_PMCFG_CFG6_SHIFT (26U)
2350/*! CFG6 - Specifies the match contribution condition for bit slice 6.
2351 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
2352 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
2353 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2354 * PMSRC registers are written to.
2355 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
2356 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2357 * PMSRC registers are written to.
2358 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
2359 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
2360 * cleared when the PMCFG or the PMSRC registers are written to.
2361 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
2362 * 0b101..Low level. Match occurs when there is a low level on the specified input.
2363 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
2364 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
2365 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
2366 * is cleared after one clock cycle.
2367 */
2368#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
2369#define PINT_PMCFG_CFG7_MASK (0xE0000000U)
2370#define PINT_PMCFG_CFG7_SHIFT (29U)
2371/*! CFG7 - Specifies the match contribution condition for bit slice 7.
2372 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
2373 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
2374 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2375 * PMSRC registers are written to.
2376 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
2377 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2378 * PMSRC registers are written to.
2379 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
2380 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
2381 * cleared when the PMCFG or the PMSRC registers are written to.
2382 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
2383 * 0b101..Low level. Match occurs when there is a low level on the specified input.
2384 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
2385 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
2386 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
2387 * is cleared after one clock cycle.
2388 */
2389#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
2390/*! @} */
2391
2392
2393/*!
2394 * @}
2395 */ /* end of group PINT_Register_Masks */
2396
2397
2398/* PINT - Peripheral instance base addresses */
2399/** Peripheral PINT base address */
2400#define PINT_BASE (0xA0004000u)
2401/** Peripheral PINT base pointer */
2402#define PINT ((PINT_Type *)PINT_BASE)
2403/** Array initializer of PINT peripheral base addresses */
2404#define PINT_BASE_ADDRS { PINT_BASE }
2405/** Array initializer of PINT peripheral base pointers */
2406#define PINT_BASE_PTRS { PINT }
2407/** Interrupt vectors for the PINT peripheral type */
2408#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }
2409
2410/*!
2411 * @}
2412 */ /* end of group PINT_Peripheral_Access_Layer */
2413
2414
2415/* ----------------------------------------------------------------------------
2416 -- PMU Peripheral Access Layer
2417 ---------------------------------------------------------------------------- */
2418
2419/*!
2420 * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer
2421 * @{
2422 */
2423
2424/** PMU - Register Layout Typedef */
2425typedef struct {
2426 __IO uint32_t PCON; /**< Power control register, offset: 0x0 */
2427 __IO uint32_t GPREG[4]; /**< General purpose register N, array offset: 0x4, array step: 0x4 */
2428 __IO uint32_t DPDCTRL; /**< Deep power-down control register. Also includes bits for general purpose storage., offset: 0x14 */
2429} PMU_Type;
2430
2431/* ----------------------------------------------------------------------------
2432 -- PMU Register Masks
2433 ---------------------------------------------------------------------------- */
2434
2435/*!
2436 * @addtogroup PMU_Register_Masks PMU Register Masks
2437 * @{
2438 */
2439
2440/*! @name PCON - Power control register */
2441/*! @{ */
2442#define PMU_PCON_PM_MASK (0x7U)
2443#define PMU_PCON_PM_SHIFT (0U)
2444/*! PM - Power mode
2445 * 0b000..Default. The part is in active or sleep mode.
2446 * 0b001..Deep-sleep mode. ARM WFI will enter Deep-sleep mode.
2447 * 0b010..Power-down mode. ARM WFI will enter Power-down mode.
2448 * 0b011..Deep power-down mode. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down).
2449 */
2450#define PMU_PCON_PM(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_PM_SHIFT)) & PMU_PCON_PM_MASK)
2451#define PMU_PCON_NODPD_MASK (0x8U)
2452#define PMU_PCON_NODPD_SHIFT (3U)
2453/*! NODPD - A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM
2454 * field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by
2455 * power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode
2456 * is blocked.
2457 */
2458#define PMU_PCON_NODPD(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_NODPD_SHIFT)) & PMU_PCON_NODPD_MASK)
2459#define PMU_PCON_SLEEPFLAG_MASK (0x100U)
2460#define PMU_PCON_SLEEPFLAG_SHIFT (8U)
2461/*! SLEEPFLAG - Sleep mode flag
2462 * 0b0..Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect.
2463 * 0b1..Low power mode. Read: Sleep, Deep-sleep or Power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0.
2464 */
2465#define PMU_PCON_SLEEPFLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_SLEEPFLAG_SHIFT)) & PMU_PCON_SLEEPFLAG_MASK)
2466#define PMU_PCON_DPDFLAG_MASK (0x800U)
2467#define PMU_PCON_DPDFLAG_SHIFT (11U)
2468/*! DPDFLAG - Deep power-down flag
2469 * 0b0..Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect.
2470 * 0b1..Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag.
2471 */
2472#define PMU_PCON_DPDFLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_DPDFLAG_SHIFT)) & PMU_PCON_DPDFLAG_MASK)
2473/*! @} */
2474
2475/*! @name GPREG - General purpose register N */
2476/*! @{ */
2477#define PMU_GPREG_GPDATA_MASK (0xFFFFFFFFU)
2478#define PMU_GPREG_GPDATA_SHIFT (0U)
2479/*! GPDATA - Data retained during Deep power-down mode.
2480 */
2481#define PMU_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPREG_GPDATA_SHIFT)) & PMU_GPREG_GPDATA_MASK)
2482/*! @} */
2483
2484/* The count of PMU_GPREG */
2485#define PMU_GPREG_COUNT (4U)
2486
2487/*! @name DPDCTRL - Deep power-down control register. Also includes bits for general purpose storage. */
2488/*! @{ */
2489#define PMU_DPDCTRL_WAKEUPHYS_MASK (0x1U)
2490#define PMU_DPDCTRL_WAKEUPHYS_SHIFT (0U)
2491/*! WAKEUPHYS - WAKEUP pin hysteresis enable
2492 * 0b0..Disabled. Hysteresis for WAKEUP pin disabled.
2493 * 0b1..Enabled. Hysteresis for WAKEUP pin enabled.
2494 */
2495#define PMU_DPDCTRL_WAKEUPHYS(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_WAKEUPHYS_SHIFT)) & PMU_DPDCTRL_WAKEUPHYS_MASK)
2496#define PMU_DPDCTRL_WAKEPAD_DISABLE_MASK (0x2U)
2497#define PMU_DPDCTRL_WAKEPAD_DISABLE_SHIFT (1U)
2498/*! WAKEPAD_DISABLE - WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be
2499 * used for other purposes. Remark: Never set this bit if you intend to use a pin to wake up the
2500 * part from Deep power-down mode. You can only disable the wake-up pin if the self wake-up timer
2501 * is enabled and configured. Remark: Setting this bit is not necessary if Deep power-down mode is
2502 * not used.
2503 * 0b0..Enabled. The wake-up function is enabled on pin PIO0_4.
2504 * 0b1..Disabled. Setting this bit disables the wake-up function on pin PIO0_4.
2505 */
2506#define PMU_DPDCTRL_WAKEPAD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_WAKEPAD_DISABLE_SHIFT)) & PMU_DPDCTRL_WAKEPAD_DISABLE_MASK)
2507#define PMU_DPDCTRL_LPOSCEN_MASK (0x4U)
2508#define PMU_DPDCTRL_LPOSCEN_SHIFT (2U)
2509/*! LPOSCEN - Enable the low-power oscillator for use with the 10 kHz self wake-up timer clock. You
2510 * must set this bit if the CLKSEL bit in the self wake-up timer CTRL bit is set. Do not enable
2511 * the low-power oscillator if the self wake-up timer is clocked by the divided IRC or the
2512 * external clock input.
2513 * 0b0..Disabled.
2514 * 0b1..Enabled.
2515 */
2516#define PMU_DPDCTRL_LPOSCEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_LPOSCEN_SHIFT)) & PMU_DPDCTRL_LPOSCEN_MASK)
2517#define PMU_DPDCTRL_LPOSCDPDEN_MASK (0x8U)
2518#define PMU_DPDCTRL_LPOSCDPDEN_SHIFT (3U)
2519/*! LPOSCDPDEN - causes the low-power oscillator to remain running during Deep power-down mode
2520 * provided that bit 2 in this register is set as well. You must set this bit for the self wake-up
2521 * timer to be able to wake up the part from Deep power-down mode. Remark: Do not set this bit
2522 * unless you use the self wake-up timer with the low-power oscillator clock source to wake up from
2523 * Deep power-down mode.
2524 * 0b0..Disabled.
2525 * 0b1..Enabled.
2526 */
2527#define PMU_DPDCTRL_LPOSCDPDEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_LPOSCDPDEN_SHIFT)) & PMU_DPDCTRL_LPOSCDPDEN_MASK)
2528#define PMU_DPDCTRL_GPDATA_MASK (0xFFFFFFF0U)
2529#define PMU_DPDCTRL_GPDATA_SHIFT (4U)
2530/*! GPDATA - Data retained during Deep power-down mode.
2531 */
2532#define PMU_DPDCTRL_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_GPDATA_SHIFT)) & PMU_DPDCTRL_GPDATA_MASK)
2533/*! @} */
2534
2535
2536/*!
2537 * @}
2538 */ /* end of group PMU_Register_Masks */
2539
2540
2541/* PMU - Peripheral instance base addresses */
2542/** Peripheral PMU base address */
2543#define PMU_BASE (0x40020000u)
2544/** Peripheral PMU base pointer */
2545#define PMU ((PMU_Type *)PMU_BASE)
2546/** Array initializer of PMU peripheral base addresses */
2547#define PMU_BASE_ADDRS { PMU_BASE }
2548/** Array initializer of PMU peripheral base pointers */
2549#define PMU_BASE_PTRS { PMU }
2550
2551/*!
2552 * @}
2553 */ /* end of group PMU_Peripheral_Access_Layer */
2554
2555
2556/* ----------------------------------------------------------------------------
2557 -- SCT Peripheral Access Layer
2558 ---------------------------------------------------------------------------- */
2559
2560/*!
2561 * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
2562 * @{
2563 */
2564
2565/** SCT - Register Layout Typedef */
2566typedef struct {
2567 __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */
2568 union { /* offset: 0x4 */
2569 struct { /* offset: 0x4 */
2570 __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */
2571 __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */
2572 } CTRL_ACCESS16BIT;
2573 __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */
2574 };
2575 union { /* offset: 0x8 */
2576 struct { /* offset: 0x8 */
2577 __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */
2578 __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */
2579 } LIMIT_ACCESS16BIT;
2580 __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */
2581 };
2582 union { /* offset: 0xC */
2583 struct { /* offset: 0xC */
2584 __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */
2585 __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */
2586 } HALT_ACCESS16BIT;
2587 __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */
2588 };
2589 union { /* offset: 0x10 */
2590 struct { /* offset: 0x10 */
2591 __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */
2592 __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */
2593 } STOP_ACCESS16BIT;
2594 __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */
2595 };
2596 union { /* offset: 0x14 */
2597 struct { /* offset: 0x14 */
2598 __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */
2599 __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */
2600 } START_ACCESS16BIT;
2601 __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */
2602 };
2603 uint8_t RESERVED_0[40];
2604 union { /* offset: 0x40 */
2605 struct { /* offset: 0x40 */
2606 __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */
2607 __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */
2608 } COUNT_ACCESS16BIT;
2609 __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */
2610 };
2611 union { /* offset: 0x44 */
2612 struct { /* offset: 0x44 */
2613 __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */
2614 __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */
2615 } STATE_ACCESS16BIT;
2616 __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */
2617 };
2618 __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */
2619 union { /* offset: 0x4C */
2620 struct { /* offset: 0x4C */
2621 __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */
2622 __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */
2623 } REGMODE_ACCESS16BIT;
2624 __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */
2625 };
2626 __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */
2627 __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */
2628 __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */
2629 uint8_t RESERVED_1[148];
2630 __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */
2631 __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */
2632 __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */
2633 __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */
2634 union { /* offset: 0x100 */
2635 union { /* offset: 0x100, array step: 0x4 */
2636 struct { /* offset: 0x100, array step: 0x4 */
2637 __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */
2638 __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */
2639 } CAP_ACCESS16BIT[5];
2640 __IO uint32_t CAP[5]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */
2641 };
2642 union { /* offset: 0x100, array step: 0x4 */
2643 struct { /* offset: 0x100, array step: 0x4 */
2644 __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */
2645 __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */
2646 } MATCH_ACCESS16BIT[5];
2647 __IO uint32_t MATCH[5]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */
2648 };
2649 };
2650 uint8_t RESERVED_2[236];
2651 union { /* offset: 0x200 */
2652 union { /* offset: 0x200, array step: 0x4 */
2653 struct { /* offset: 0x200, array step: 0x4 */
2654 __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */
2655 __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */
2656 } CAPCTRL_ACCESS16BIT[5];
2657 __IO uint32_t CAPCTRL[5]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */
2658 };
2659 union { /* offset: 0x200, array step: 0x4 */
2660 struct { /* offset: 0x200, array step: 0x4 */
2661 __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */
2662 __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */
2663 } MATCHREL_ACCESS16BIT[5];
2664 __IO uint32_t MATCHREL[5]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */
2665 };
2666 };
2667 uint8_t RESERVED_3[236];
2668 struct { /* offset: 0x300, array step: 0x8 */
2669 __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */
2670 __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */
2671 } EV[6];
2672 uint8_t RESERVED_4[464];
2673 struct { /* offset: 0x500, array step: 0x8 */
2674 __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */
2675 __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */
2676 } OUT[4];
2677} SCT_Type;
2678
2679/* ----------------------------------------------------------------------------
2680 -- SCT Register Masks
2681 ---------------------------------------------------------------------------- */
2682
2683/*!
2684 * @addtogroup SCT_Register_Masks SCT Register Masks
2685 * @{
2686 */
2687
2688/*! @name CONFIG - SCT configuration register */
2689/*! @{ */
2690#define SCT_CONFIG_UNIFY_MASK (0x1U)
2691#define SCT_CONFIG_UNIFY_SHIFT (0U)
2692/*! UNIFY - SCT operation
2693 * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.
2694 * 0b1..The SCT operates as a unified 32-bit counter.
2695 */
2696#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
2697#define SCT_CONFIG_CLKMODE_MASK (0x6U)
2698#define SCT_CONFIG_CLKMODE_SHIFT (1U)
2699/*! CLKMODE - SCT clock mode
2700 * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers.
2701 * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are
2702 * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The
2703 * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the
2704 * high-performance, sampled-clock mode.
2705 * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the
2706 * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the
2707 * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.
2708 * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL
2709 * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system
2710 * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than
2711 * the system clock.
2712 */
2713#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
2714#define SCT_CONFIG_CKSEL_MASK (0x78U)
2715#define SCT_CONFIG_CKSEL_SHIFT (3U)
2716/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent
2717 * on the CLKMODE bit selection in this register.
2718 * 0b0000..Rising edges on input 0.
2719 * 0b0001..Falling edges on input 0.
2720 * 0b0010..Rising edges on input 1.
2721 * 0b0011..Falling edges on input 1.
2722 * 0b0100..Rising edges on input 2.
2723 * 0b0101..Falling edges on input 2.
2724 * 0b0110..Rising edges on input 3.
2725 * 0b0111..Falling edges on input 3.
2726 */
2727#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
2728#define SCT_CONFIG_NORELOAD_L_MASK (0x80U)
2729#define SCT_CONFIG_NORELOAD_L_SHIFT (7U)
2730/*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their
2731 * respective reload registers. Setting this bit eliminates the need to write to the reload
2732 * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any
2733 * time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
2734 */
2735#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK)
2736#define SCT_CONFIG_NORELOAD_H_MASK (0x100U)
2737#define SCT_CONFIG_NORELOAD_H_SHIFT (8U)
2738/*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their
2739 * respective reload registers. Setting this bit eliminates the need to write to the reload
2740 * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at
2741 * any time. This bit is not used when the UNIFY bit is set.
2742 */
2743#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
2744#define SCT_CONFIG_INSYNC_MASK (0x1FE00U)
2745#define SCT_CONFIG_INSYNC_SHIFT (9U)
2746/*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all
2747 * other bits are reserved. A 1 in one of these bits subjects the corresponding input to
2748 * synchronization to the SCT clock, before it is used to create an event. If an input is known to
2749 * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note:
2750 * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input
2751 * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation.
2752 * It does not apply to the clock input specified in the CKSEL field.
2753 */
2754#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
2755#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U)
2756#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U)
2757/*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto
2758 * LIMIT condition without the need to define an associated event. As with any LIMIT event, this
2759 * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change
2760 * the direction of count in bi-directional mode. Software can write to set or clear this bit at
2761 * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
2762 */
2763#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
2764#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U)
2765#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U)
2766/*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a
2767 * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event,
2768 * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to
2769 * change the direction of count in bi-directional mode. Software can write to set or clear this bit
2770 * at any time. This bit is not used when the UNIFY bit is set.
2771 */
2772#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
2773/*! @} */
2774
2775/*! @name CTRLL - SCT_CTRLL register */
2776/*! @{ */
2777#define SCT_CTRLL_DOWN_L_MASK (0x1U)
2778#define SCT_CTRLL_DOWN_L_SHIFT (0U)
2779/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit
2780 * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit
2781 * when the counter is counting down and a limit condition occurs or when the counter reaches 0.
2782 */
2783#define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK)
2784#define SCT_CTRLL_STOP_L_MASK (0x2U)
2785#define SCT_CTRLL_STOP_L_SHIFT (1U)
2786/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events
2787 * related to the counter can occur. If a designated start event occurs, this bit is cleared and
2788 * counting resumes.
2789 */
2790#define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK)
2791#define SCT_CTRLL_HALT_L_MASK (0x4U)
2792#define SCT_CTRLL_HALT_L_SHIFT (2U)
2793/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A
2794 * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to
2795 * remove the halt condition while keeping the SCT in the stop condition (not running) with a
2796 * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set,
2797 * only software can clear this bit to restore counter operation. This bit is set on reset.
2798 */
2799#define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK)
2800#define SCT_CTRLL_CLRCTR_L_MASK (0x8U)
2801#define SCT_CTRLL_CLRCTR_L_SHIFT (3U)
2802/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
2803 */
2804#define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK)
2805#define SCT_CTRLL_BIDIR_L_MASK (0x10U)
2806#define SCT_CTRLL_BIDIR_L_SHIFT (4U)
2807/*! BIDIR_L - L or unified counter direction select
2808 * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
2809 * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
2810 */
2811#define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK)
2812#define SCT_CTRLL_PRE_L_MASK (0x1FE0U)
2813#define SCT_CTRLL_PRE_L_SHIFT (5U)
2814/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified
2815 * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1.
2816 * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
2817 */
2818#define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK)
2819/*! @} */
2820
2821/*! @name CTRLH - SCT_CTRLH register */
2822/*! @{ */
2823#define SCT_CTRLH_DOWN_H_MASK (0x1U)
2824#define SCT_CTRLH_DOWN_H_SHIFT (0U)
2825/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the
2826 * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit
2827 * when the counter is counting down and a limit condition occurs or when the counter reaches 0.
2828 */
2829#define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK)
2830#define SCT_CTRLH_STOP_H_MASK (0x2U)
2831#define SCT_CTRLH_STOP_H_SHIFT (1U)
2832/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to
2833 * the counter can occur. If such an event matches the mask in the Start register, this bit is
2834 * cleared and counting resumes.
2835 */
2836#define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK)
2837#define SCT_CTRLH_HALT_H_MASK (0x4U)
2838#define SCT_CTRLH_HALT_H_SHIFT (2U)
2839/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets
2840 * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the
2841 * halt condition while keeping the SCT in the stop condition (not running) with a single write to
2842 * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit
2843 * can only be cleared by software to restore counter operation. This bit is set on reset.
2844 */
2845#define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK)
2846#define SCT_CTRLH_CLRCTR_H_MASK (0x8U)
2847#define SCT_CTRLH_CLRCTR_H_SHIFT (3U)
2848/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0.
2849 */
2850#define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK)
2851#define SCT_CTRLH_BIDIR_H_MASK (0x10U)
2852#define SCT_CTRLH_BIDIR_H_SHIFT (4U)
2853/*! BIDIR_H - Direction select
2854 * 0b0..The H counter counts up to its limit condition, then is cleared to zero.
2855 * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0.
2856 */
2857#define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK)
2858#define SCT_CTRLH_PRE_H_MASK (0x1FE0U)
2859#define SCT_CTRLH_PRE_H_SHIFT (5U)
2860/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock.
2861 * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the
2862 * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
2863 */
2864#define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK)
2865/*! @} */
2866
2867/*! @name CTRL - SCT control register */
2868/*! @{ */
2869#define SCT_CTRL_DOWN_L_MASK (0x1U)
2870#define SCT_CTRL_DOWN_L_SHIFT (0U)
2871/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit
2872 * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit
2873 * when the counter is counting down and a limit condition occurs or when the counter reaches 0.
2874 */
2875#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
2876#define SCT_CTRL_STOP_L_MASK (0x2U)
2877#define SCT_CTRL_STOP_L_SHIFT (1U)
2878/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events
2879 * related to the counter can occur. If a designated start event occurs, this bit is cleared and
2880 * counting resumes.
2881 */
2882#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
2883#define SCT_CTRL_HALT_L_MASK (0x4U)
2884#define SCT_CTRL_HALT_L_SHIFT (2U)
2885/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A
2886 * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to
2887 * remove the halt condition while keeping the SCT in the stop condition (not running) with a
2888 * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set,
2889 * only software can clear this bit to restore counter operation. This bit is set on reset.
2890 */
2891#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
2892#define SCT_CTRL_CLRCTR_L_MASK (0x8U)
2893#define SCT_CTRL_CLRCTR_L_SHIFT (3U)
2894/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
2895 */
2896#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
2897#define SCT_CTRL_BIDIR_L_MASK (0x10U)
2898#define SCT_CTRL_BIDIR_L_SHIFT (4U)
2899/*! BIDIR_L - L or unified counter direction select
2900 * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
2901 * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
2902 */
2903#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
2904#define SCT_CTRL_PRE_L_MASK (0x1FE0U)
2905#define SCT_CTRL_PRE_L_SHIFT (5U)
2906/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified
2907 * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1.
2908 * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
2909 */
2910#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
2911#define SCT_CTRL_DOWN_H_MASK (0x10000U)
2912#define SCT_CTRL_DOWN_H_SHIFT (16U)
2913/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the
2914 * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit
2915 * when the counter is counting down and a limit condition occurs or when the counter reaches 0.
2916 */
2917#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
2918#define SCT_CTRL_STOP_H_MASK (0x20000U)
2919#define SCT_CTRL_STOP_H_SHIFT (17U)
2920/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to
2921 * the counter can occur. If such an event matches the mask in the Start register, this bit is
2922 * cleared and counting resumes.
2923 */
2924#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
2925#define SCT_CTRL_HALT_H_MASK (0x40000U)
2926#define SCT_CTRL_HALT_H_SHIFT (18U)
2927/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets
2928 * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the
2929 * halt condition while keeping the SCT in the stop condition (not running) with a single write to
2930 * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit
2931 * can only be cleared by software to restore counter operation. This bit is set on reset.
2932 */
2933#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
2934#define SCT_CTRL_CLRCTR_H_MASK (0x80000U)
2935#define SCT_CTRL_CLRCTR_H_SHIFT (19U)
2936/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0.
2937 */
2938#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
2939#define SCT_CTRL_BIDIR_H_MASK (0x100000U)
2940#define SCT_CTRL_BIDIR_H_SHIFT (20U)
2941/*! BIDIR_H - Direction select
2942 * 0b0..The H counter counts up to its limit condition, then is cleared to zero.
2943 * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0.
2944 */
2945#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
2946#define SCT_CTRL_PRE_H_MASK (0x1FE00000U)
2947#define SCT_CTRL_PRE_H_SHIFT (21U)
2948/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock.
2949 * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the
2950 * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
2951 */
2952#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
2953/*! @} */
2954
2955/*! @name LIMITL - SCT_LIMITL register */
2956/*! @{ */
2957#define SCT_LIMITL_LIMITL_MASK (0xFFFFU)
2958#define SCT_LIMITL_LIMITL_SHIFT (0U)
2959#define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK)
2960/*! @} */
2961
2962/*! @name LIMITH - SCT_LIMITH register */
2963/*! @{ */
2964#define SCT_LIMITH_LIMITH_MASK (0xFFFFU)
2965#define SCT_LIMITH_LIMITH_SHIFT (0U)
2966#define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK)
2967/*! @} */
2968
2969/*! @name LIMIT - SCT limit event select register */
2970/*! @{ */
2971#define SCT_LIMIT_LIMMSK_L_MASK (0x3FU)
2972#define SCT_LIMIT_LIMMSK_L_SHIFT (0U)
2973/*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter
2974 * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
2975 */
2976#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
2977#define SCT_LIMIT_LIMMSK_H_MASK (0x3F0000U)
2978#define SCT_LIMIT_LIMMSK_H_SHIFT (16U)
2979/*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit
2980 * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
2981 */
2982#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
2983/*! @} */
2984
2985/*! @name HALTL - SCT_HALTL register */
2986/*! @{ */
2987#define SCT_HALTL_HALTL_MASK (0xFFFFU)
2988#define SCT_HALTL_HALTL_SHIFT (0U)
2989#define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK)
2990/*! @} */
2991
2992/*! @name HALTH - SCT_HALTH register */
2993/*! @{ */
2994#define SCT_HALTH_HALTH_MASK (0xFFFFU)
2995#define SCT_HALTH_HALTH_SHIFT (0U)
2996#define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK)
2997/*! @} */
2998
2999/*! @name HALT - SCT halt event select register */
3000/*! @{ */
3001#define SCT_HALT_HALTMSK_L_MASK (0x3FU)
3002#define SCT_HALT_HALTMSK_L_SHIFT (0U)
3003/*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0,
3004 * event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
3005 */
3006#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
3007#define SCT_HALT_HALTMSK_H_MASK (0x3F0000U)
3008#define SCT_HALT_HALTMSK_H_SHIFT (16U)
3009/*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16,
3010 * event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
3011 */
3012#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
3013/*! @} */
3014
3015/*! @name STOPL - SCT_STOPL register */
3016/*! @{ */
3017#define SCT_STOPL_STOPL_MASK (0xFFFFU)
3018#define SCT_STOPL_STOPL_SHIFT (0U)
3019#define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK)
3020/*! @} */
3021
3022/*! @name STOPH - SCT_STOPH register */
3023/*! @{ */
3024#define SCT_STOPH_STOPH_MASK (0xFFFFU)
3025#define SCT_STOPH_STOPH_SHIFT (0U)
3026#define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK)
3027/*! @} */
3028
3029/*! @name STOP - SCT stop event select register */
3030/*! @{ */
3031#define SCT_STOP_STOPMSK_L_MASK (0x3FU)
3032#define SCT_STOP_STOPMSK_L_SHIFT (0U)
3033/*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0,
3034 * event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
3035 */
3036#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
3037#define SCT_STOP_STOPMSK_H_MASK (0x3F0000U)
3038#define SCT_STOP_STOPMSK_H_SHIFT (16U)
3039/*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16,
3040 * event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
3041 */
3042#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
3043/*! @} */
3044
3045/*! @name STARTL - SCT_STARTL register */
3046/*! @{ */
3047#define SCT_STARTL_STARTL_MASK (0xFFFFU)
3048#define SCT_STARTL_STARTL_SHIFT (0U)
3049#define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK)
3050/*! @} */
3051
3052/*! @name STARTH - SCT_STARTH register */
3053/*! @{ */
3054#define SCT_STARTH_STARTH_MASK (0xFFFFU)
3055#define SCT_STARTH_STARTH_SHIFT (0U)
3056#define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK)
3057/*! @} */
3058
3059/*! @name START - SCT start event select register */
3060/*! @{ */
3061#define SCT_START_STARTMSK_L_MASK (0x3FU)
3062#define SCT_START_STARTMSK_L_SHIFT (0U)
3063/*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit
3064 * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
3065 */
3066#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
3067#define SCT_START_STARTMSK_H_MASK (0x3F0000U)
3068#define SCT_START_STARTMSK_H_SHIFT (16U)
3069/*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit
3070 * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
3071 */
3072#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
3073/*! @} */
3074
3075/*! @name COUNTL - SCT_COUNTL register */
3076/*! @{ */
3077#define SCT_COUNTL_COUNTL_MASK (0xFFFFU)
3078#define SCT_COUNTL_COUNTL_SHIFT (0U)
3079#define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK)
3080/*! @} */
3081
3082/*! @name COUNTH - SCT_COUNTH register */
3083/*! @{ */
3084#define SCT_COUNTH_COUNTH_MASK (0xFFFFU)
3085#define SCT_COUNTH_COUNTH_SHIFT (0U)
3086#define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK)
3087/*! @} */
3088
3089/*! @name COUNT - SCT counter register */
3090/*! @{ */
3091#define SCT_COUNT_CTR_L_MASK (0xFFFFU)
3092#define SCT_COUNT_CTR_L_SHIFT (0U)
3093/*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write
3094 * the lower 16 bits of the 32-bit unified counter.
3095 */
3096#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
3097#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U)
3098#define SCT_COUNT_CTR_H_SHIFT (16U)
3099/*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write
3100 * the upper 16 bits of the 32-bit unified counter.
3101 */
3102#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
3103/*! @} */
3104
3105/*! @name STATEL - SCT_STATEL register */
3106/*! @{ */
3107#define SCT_STATEL_STATEL_MASK (0xFFFFU)
3108#define SCT_STATEL_STATEL_SHIFT (0U)
3109#define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK)
3110/*! @} */
3111
3112/*! @name STATEH - SCT_STATEH register */
3113/*! @{ */
3114#define SCT_STATEH_STATEH_MASK (0xFFFFU)
3115#define SCT_STATEH_STATEH_SHIFT (0U)
3116#define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK)
3117/*! @} */
3118
3119/*! @name STATE - SCT state register */
3120/*! @{ */
3121#define SCT_STATE_STATE_L_MASK (0x1FU)
3122#define SCT_STATE_STATE_L_SHIFT (0U)
3123/*! STATE_L - State variable.
3124 */
3125#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
3126#define SCT_STATE_STATE_H_MASK (0x1F0000U)
3127#define SCT_STATE_STATE_H_SHIFT (16U)
3128/*! STATE_H - State variable.
3129 */
3130#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
3131/*! @} */
3132
3133/*! @name INPUT - SCT input register */
3134/*! @{ */
3135#define SCT_INPUT_AIN0_MASK (0x1U)
3136#define SCT_INPUT_AIN0_SHIFT (0U)
3137/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge.
3138 */
3139#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
3140#define SCT_INPUT_AIN1_MASK (0x2U)
3141#define SCT_INPUT_AIN1_SHIFT (1U)
3142/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge.
3143 */
3144#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
3145#define SCT_INPUT_AIN2_MASK (0x4U)
3146#define SCT_INPUT_AIN2_SHIFT (2U)
3147/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge.
3148 */
3149#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
3150#define SCT_INPUT_AIN3_MASK (0x8U)
3151#define SCT_INPUT_AIN3_SHIFT (3U)
3152/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge.
3153 */
3154#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
3155#define SCT_INPUT_SIN0_MASK (0x10000U)
3156#define SCT_INPUT_SIN0_SHIFT (16U)
3157/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC.
3158 */
3159#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
3160#define SCT_INPUT_SIN1_MASK (0x20000U)
3161#define SCT_INPUT_SIN1_SHIFT (17U)
3162/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC.
3163 */
3164#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
3165#define SCT_INPUT_SIN2_MASK (0x40000U)
3166#define SCT_INPUT_SIN2_SHIFT (18U)
3167/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC.
3168 */
3169#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
3170#define SCT_INPUT_SIN3_MASK (0x80000U)
3171#define SCT_INPUT_SIN3_SHIFT (19U)
3172/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC.
3173 */
3174#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
3175/*! @} */
3176
3177/*! @name REGMODEL - SCT_REGMODEL register */
3178/*! @{ */
3179#define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU)
3180#define SCT_REGMODEL_REGMODEL_SHIFT (0U)
3181#define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK)
3182/*! @} */
3183
3184/*! @name REGMODEH - SCT_REGMODEH register */
3185/*! @{ */
3186#define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU)
3187#define SCT_REGMODEH_REGMODEH_SHIFT (0U)
3188#define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK)
3189/*! @} */
3190
3191/*! @name REGMODE - SCT match/capture mode register */
3192/*! @{ */
3193#define SCT_REGMODE_REGMOD_L_MASK (0x1FU)
3194#define SCT_REGMODE_REGMOD_L_SHIFT (0U)
3195/*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1,
3196 * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as
3197 * match register. 1 = register operates as capture register.
3198 */
3199#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
3200#define SCT_REGMODE_REGMOD_H_MASK (0x1F0000U)
3201#define SCT_REGMODE_REGMOD_H_SHIFT (16U)
3202/*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit
3203 * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as
3204 * match registers. 1 = register operates as capture registers.
3205 */
3206#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
3207/*! @} */
3208
3209/*! @name OUTPUT - SCT output register */
3210/*! @{ */
3211#define SCT_OUTPUT_OUT_MASK (0xFU)
3212#define SCT_OUTPUT_OUT_SHIFT (0U)
3213/*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the
3214 * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of
3215 * outputs in this SCT.
3216 */
3217#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)
3218/*! @} */
3219
3220/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */
3221/*! @{ */
3222#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U)
3223#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U)
3224/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
3225 * 0b00..Set and clear do not depend on the direction of any counter.
3226 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
3227 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
3228 */
3229#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
3230#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU)
3231#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U)
3232/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.
3233 * 0b00..Set and clear do not depend on the direction of any counter.
3234 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
3235 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
3236 */
3237#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
3238#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U)
3239#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U)
3240/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.
3241 * 0b00..Set and clear do not depend on the direction of any counter.
3242 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
3243 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
3244 */
3245#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
3246#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U)
3247#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U)
3248/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.
3249 * 0b00..Set and clear do not depend on the direction of any counter.
3250 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
3251 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
3252 */
3253#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
3254/*! @} */
3255
3256/*! @name RES - SCT conflict resolution register */
3257/*! @{ */
3258#define SCT_RES_O0RES_MASK (0x3U)
3259#define SCT_RES_O0RES_SHIFT (0U)
3260/*! O0RES - Effect of simultaneous set and clear on output 0.
3261 * 0b00..No change.
3262 * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register).
3263 * 0b10..Clear output (or set based on the SETCLR0 field).
3264 * 0b11..Toggle output.
3265 */
3266#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
3267#define SCT_RES_O1RES_MASK (0xCU)
3268#define SCT_RES_O1RES_SHIFT (2U)
3269/*! O1RES - Effect of simultaneous set and clear on output 1.
3270 * 0b00..No change.
3271 * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register).
3272 * 0b10..Clear output (or set based on the SETCLR1 field).
3273 * 0b11..Toggle output.
3274 */
3275#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
3276#define SCT_RES_O2RES_MASK (0x30U)
3277#define SCT_RES_O2RES_SHIFT (4U)
3278/*! O2RES - Effect of simultaneous set and clear on output 2.
3279 * 0b00..No change.
3280 * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register).
3281 * 0b10..Clear output n (or set based on the SETCLR2 field).
3282 * 0b11..Toggle output.
3283 */
3284#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
3285#define SCT_RES_O3RES_MASK (0xC0U)
3286#define SCT_RES_O3RES_SHIFT (6U)
3287/*! O3RES - Effect of simultaneous set and clear on output 3.
3288 * 0b00..No change.
3289 * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register).
3290 * 0b10..Clear output (or set based on the SETCLR3 field).
3291 * 0b11..Toggle output.
3292 */
3293#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
3294/*! @} */
3295
3296/*! @name EVEN - SCT event interrupt enable register */
3297/*! @{ */
3298#define SCT_EVEN_IEN_MASK (0x3FU)
3299#define SCT_EVEN_IEN_SHIFT (0U)
3300/*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are
3301 * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in
3302 * this SCT.
3303 */
3304#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)
3305/*! @} */
3306
3307/*! @name EVFLAG - SCT event flag register */
3308/*! @{ */
3309#define SCT_EVFLAG_FLAG_MASK (0x3FU)
3310#define SCT_EVFLAG_FLAG_SHIFT (0U)
3311/*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit
3312 * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
3313 */
3314#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)
3315/*! @} */
3316
3317/*! @name CONEN - SCT conflict interrupt enable register */
3318/*! @{ */
3319#define SCT_CONEN_NCEN_MASK (0xFU)
3320#define SCT_CONEN_NCEN_SHIFT (0U)
3321/*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag
3322 * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of
3323 * outputs in this SCT.
3324 */
3325#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)
3326/*! @} */
3327
3328/*! @name CONFLAG - SCT conflict flag register */
3329/*! @{ */
3330#define SCT_CONFLAG_NCFLAG_MASK (0xFU)
3331#define SCT_CONFLAG_NCFLAG_SHIFT (0U)
3332/*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was
3333 * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits =
3334 * number of outputs in this SCT.
3335 */
3336#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)
3337#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U)
3338#define SCT_CONFLAG_BUSERRL_SHIFT (30U)
3339/*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE
3340 * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write
3341 * to certain L and H registers can be half successful and half unsuccessful.
3342 */
3343#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
3344#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U)
3345#define SCT_CONFLAG_BUSERRH_SHIFT (31U)
3346/*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or
3347 * the Output register when the H counter was not halted.
3348 */
3349#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
3350/*! @} */
3351
3352/*! @name CAPL - SCT_CAPL register */
3353/*! @{ */
3354#define SCT_CAPL_CAPL_MASK (0xFFFFU)
3355#define SCT_CAPL_CAPL_SHIFT (0U)
3356#define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK)
3357/*! @} */
3358
3359/* The count of SCT_CAPL */
3360#define SCT_CAPL_COUNT (5U)
3361
3362/*! @name CAPH - SCT_CAPH register */
3363/*! @{ */
3364#define SCT_CAPH_CAPH_MASK (0xFFFFU)
3365#define SCT_CAPH_CAPH_SHIFT (0U)
3366#define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK)
3367/*! @} */
3368
3369/* The count of SCT_CAPH */
3370#define SCT_CAPH_COUNT (5U)
3371
3372/*! @name CAP - SCT capture register of capture channel */
3373/*! @{ */
3374#define SCT_CAP_CAPn_L_MASK (0xFFFFU)
3375#define SCT_CAP_CAPn_L_SHIFT (0U)
3376/*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured.
3377 * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last
3378 * captured.
3379 */
3380#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK)
3381#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U)
3382#define SCT_CAP_CAPn_H_SHIFT (16U)
3383/*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured.
3384 * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last
3385 * captured.
3386 */
3387#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK)
3388/*! @} */
3389
3390/* The count of SCT_CAP */
3391#define SCT_CAP_COUNT (5U)
3392
3393/*! @name MATCHL - SCT_MATCHL register */
3394/*! @{ */
3395#define SCT_MATCHL_MATCHL_MASK (0xFFFFU)
3396#define SCT_MATCHL_MATCHL_SHIFT (0U)
3397#define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK)
3398/*! @} */
3399
3400/* The count of SCT_MATCHL */
3401#define SCT_MATCHL_COUNT (5U)
3402
3403/*! @name MATCHH - SCT_MATCHH register */
3404/*! @{ */
3405#define SCT_MATCHH_MATCHH_MASK (0xFFFFU)
3406#define SCT_MATCHH_MATCHH_SHIFT (0U)
3407#define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK)
3408/*! @} */
3409
3410/* The count of SCT_MATCHH */
3411#define SCT_MATCHH_COUNT (5U)
3412
3413/*! @name MATCH - SCT match value register of match channels */
3414/*! @{ */
3415#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU)
3416#define SCT_MATCH_MATCHn_L_SHIFT (0U)
3417/*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When
3418 * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified
3419 * counter.
3420 */
3421#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK)
3422#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U)
3423#define SCT_MATCH_MATCHn_H_SHIFT (16U)
3424/*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When
3425 * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified
3426 * counter.
3427 */
3428#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK)
3429/*! @} */
3430
3431/* The count of SCT_MATCH */
3432#define SCT_MATCH_COUNT (5U)
3433
3434/*! @name CAPCTRLL - SCT_CAPCTRLL register */
3435/*! @{ */
3436#define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU)
3437#define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U)
3438#define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK)
3439/*! @} */
3440
3441/* The count of SCT_CAPCTRLL */
3442#define SCT_CAPCTRLL_COUNT (5U)
3443
3444/*! @name CAPCTRLH - SCT_CAPCTRLH register */
3445/*! @{ */
3446#define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU)
3447#define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U)
3448#define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK)
3449/*! @} */
3450
3451/* The count of SCT_CAPCTRLH */
3452#define SCT_CAPCTRLH_COUNT (5U)
3453
3454/*! @name CAPCTRL - SCT capture control register */
3455/*! @{ */
3456#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU)
3457#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U)
3458/*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1)
3459 * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of
3460 * match/captures in this SCT.
3461 */
3462#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK)
3463#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U)
3464#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U)
3465/*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event
3466 * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
3467 */
3468#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK)
3469/*! @} */
3470
3471/* The count of SCT_CAPCTRL */
3472#define SCT_CAPCTRL_COUNT (5U)
3473
3474/*! @name MATCHRELL - SCT_MATCHRELL register */
3475/*! @{ */
3476#define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU)
3477#define SCT_MATCHRELL_MATCHRELL_SHIFT (0U)
3478#define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK)
3479/*! @} */
3480
3481/* The count of SCT_MATCHRELL */
3482#define SCT_MATCHRELL_COUNT (5U)
3483
3484/*! @name MATCHRELH - SCT_MATCHRELH register */
3485/*! @{ */
3486#define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU)
3487#define SCT_MATCHRELH_MATCHRELH_SHIFT (0U)
3488#define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK)
3489/*! @} */
3490
3491/* The count of SCT_MATCHRELH */
3492#define SCT_MATCHRELH_COUNT (5U)
3493
3494/*! @name MATCHREL - SCT match reload value register */
3495/*! @{ */
3496#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU)
3497#define SCT_MATCHREL_RELOADn_L_SHIFT (0U)
3498/*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register.
3499 * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn
3500 * register.
3501 */
3502#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK)
3503#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U)
3504#define SCT_MATCHREL_RELOADn_H_SHIFT (16U)
3505/*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When
3506 * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn
3507 * register.
3508 */
3509#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK)
3510/*! @} */
3511
3512/* The count of SCT_MATCHREL */
3513#define SCT_MATCHREL_COUNT (5U)
3514
3515/*! @name EV_STATE - SCT event state register 0 */
3516/*! @{ */
3517#define SCT_EV_STATE_STATEMSK0_MASK (0x1U)
3518#define SCT_EV_STATE_STATEMSK0_SHIFT (0U)
3519/*! STATEMSK0 - If bit m is one, event n happens in state m of the counter selected by the HEVENT
3520 * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of
3521 * bits = number of states in this SCT.
3522 */
3523#define SCT_EV_STATE_STATEMSK0(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSK0_SHIFT)) & SCT_EV_STATE_STATEMSK0_MASK)
3524#define SCT_EV_STATE_STATEMSK1_MASK (0x2U)
3525#define SCT_EV_STATE_STATEMSK1_SHIFT (1U)
3526/*! STATEMSK1 - If bit m is one, event n happens in state m of the counter selected by the HEVENT
3527 * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of
3528 * bits = number of states in this SCT.
3529 */
3530#define SCT_EV_STATE_STATEMSK1(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSK1_SHIFT)) & SCT_EV_STATE_STATEMSK1_MASK)
3531/*! @} */
3532
3533/* The count of SCT_EV_STATE */
3534#define SCT_EV_STATE_COUNT (6U)
3535
3536/*! @name EV_CTRL - SCT event control register 0 */
3537/*! @{ */
3538#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU)
3539#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U)
3540/*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur
3541 * only when the counter selected by the HEVENT bit is running.
3542 */
3543#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK)
3544#define SCT_EV_CTRL_HEVENT_MASK (0x10U)
3545#define SCT_EV_CTRL_HEVENT_SHIFT (4U)
3546/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1.
3547 * 0b0..Selects the L state and the L match register selected by MATCHSEL.
3548 * 0b1..Selects the H state and the H match register selected by MATCHSEL.
3549 */
3550#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK)
3551#define SCT_EV_CTRL_OUTSEL_MASK (0x20U)
3552#define SCT_EV_CTRL_OUTSEL_SHIFT (5U)
3553/*! OUTSEL - Input/output select
3554 * 0b0..Selects the inputs selected by IOSEL.
3555 * 0b1..Selects the outputs selected by IOSEL.
3556 */
3557#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK)
3558#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U)
3559#define SCT_EV_CTRL_IOSEL_SHIFT (6U)
3560/*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not
3561 * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit
3562 * ingredient of every event.
3563 */