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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/driver_reset.cmake14
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_clock.c439
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_clock.h562
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_power.c167
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_power.h372
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_reset.c92
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_reset.h140
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_swm_connections.h125
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_syscon_connections.h62
9 files changed, 1973 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/driver_reset.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/driver_reset.cmake
new file mode 100644
index 000000000..989530f6f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/driver_reset.cmake
@@ -0,0 +1,14 @@
1if(NOT DRIVER_RESET_INCLUDED)
2
3 set(DRIVER_RESET_INCLUDED true CACHE BOOL "driver_reset component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 )
7
8 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
9 ${CMAKE_CURRENT_LIST_DIR}/.
10 )
11
12
13
14endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_clock.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_clock.c
new file mode 100644
index 000000000..fe306b624
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_clock.c
@@ -0,0 +1,439 @@
1/*
2 * Copyright 2017-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_clock.h"
9/*******************************************************************************
10 * Definitions
11 ******************************************************************************/
12/* Component ID definition, used by tools. */
13#ifndef FSL_COMPONENT_ID
14#define FSL_COMPONENT_ID "platform.drivers.clock"
15#endif
16#define SYSPLL_MIN_INPUT_FREQ_HZ (10000000U) /*!< Minimum PLL input rate */
17#define SYSPLL_MAX_INPUT_FREQ_HZ (25000000U) /*!< Maximum PLL input rate */
18#define SYSPLL_MAX_OUTPUT_FREQ_HZ (100000000U) /*!< Maximum PLL output rate */
19#define SYSPLL_MIN_FCCO_FREQ_HZ (156000000U) /*!< Maximum FCCO output rate */
20#define SYSPLL_MAX_FCCO_FREQ_HZ (320000000U) /*!< Maximum FCCO output rate */
21#define SYSOSC_BOUNDARY_FREQ_HZ (15000000U) /*!< boundary frequency value */
22
23/* External clock rate.
24 * Either external clk in rate or system oscillator frequency.
25 */
26uint32_t g_Ext_Clk_Freq = 0U;
27uint32_t g_Wdt_Osc_Freq = 0U;
28
29/*
30 * Sys pll freq.
31 */
32uint32_t g_Sys_Pll_Freq = 0U;
33/*******************************************************************************
34 * Variables
35 ******************************************************************************/
36
37/*******************************************************************************
38 * Prototypes
39 ******************************************************************************/
40/*
41 * @brief select post divider for system pll according to the target frequency.
42 * @param outFreq: Value to be output
43 * @return post divider
44 */
45static uint32_t findSyestemPllPsel(uint32_t outFreq);
46
47/*
48 * @brief Update clock source.
49 * @param base clock register base address.
50 * @param mask clock source update enable bit mask value.
51 */
52static void CLOCK_UpdateClkSrc(volatile uint32_t *base, uint32_t mask);
53
54/*******************************************************************************
55 * Code
56 ******************************************************************************/
57static void CLOCK_UpdateClkSrc(volatile uint32_t *base, uint32_t mask)
58{
59 assert(base);
60
61 *base &= ~mask;
62 *base |= mask;
63 while ((*base & mask) == 0U)
64 {
65 }
66}
67
68/*! brief Return Frequency of IRC
69 * return Frequency of IRC
70 */
71uint32_t CLOCK_GetIrcFreq(void)
72{
73 return 12000000U;
74}
75
76/*! brief Return Frequency of SYSOSC
77 * return Frequency of SYSOSC
78 */
79uint32_t CLOCK_GetSysOscFreq(void)
80{
81 uint32_t freq = 0U;
82 if ((SYSCON->PDRUNCFG & SYSCON_PDRUNCFG_SYSOSC_PD_MASK) == 0UL)
83 {
84 freq = CLOCK_GetExtClkFreq();
85 }
86 return freq;
87}
88
89/*! brief Return Frequency of Main Clock.
90 * return Frequency of Main Clock.
91 */
92uint32_t CLOCK_GetMainClkFreq(void)
93{
94 uint32_t freq = 0U;
95
96 switch (SYSCON->MAINCLKSEL)
97 {
98 case 0U:
99 freq = CLOCK_GetIrcFreq();
100 break;
101
102 case 1U:
103 freq = CLOCK_GetSystemPLLInClockRate();
104 break;
105
106 case 2U:
107 freq = CLOCK_GetWdtOscFreq();
108 break;
109
110 case 3U:
111 freq = CLOCK_GetSystemPLLFreq();
112 break;
113 default:
114 assert(false);
115 break;
116 }
117
118 return freq;
119}
120
121/*! brief Return Frequency of ClockOut
122 * return Frequency of ClockOut
123 */
124uint32_t CLOCK_GetClockOutClkFreq(void)
125{
126 uint32_t div = SYSCON->CLKOUTDIV & 0xffU, freq = 0U;
127
128 switch (SYSCON->CLKOUTSEL)
129 {
130 case 0U:
131 freq = CLOCK_GetIrcFreq();
132 break;
133
134 case 1U:
135 freq = CLOCK_GetSysOscFreq();
136 break;
137
138 case 2U:
139 freq = CLOCK_GetWdtOscFreq();
140 break;
141
142 case 3U:
143 freq = CLOCK_GetMainClkFreq();
144 break;
145
146 default:
147 assert(false);
148 break;
149 }
150
151 return div == 0U ? 0U : (freq / div);
152}
153
154/*! brief Return Frequency of UART
155 * return Frequency of UART
156 */
157uint32_t CLOCK_GetUartClkFreq(void)
158{
159 uint32_t freq = CLOCK_GetMainClkFreq();
160 uint32_t uartDiv = SYSCON->UARTCLKDIV & 0xffU;
161
162 return uartDiv == 0U ? 0U :
163 (uint32_t)((uint64_t)(freq << 8U) /
164 (uartDiv * (256U + ((SYSCON->UARTFRGMULT) & SYSCON_UARTFRGMULT_MULT_MASK))));
165}
166
167/*! brief Return Frequency of UART0
168 * return Frequency of UART0
169 */
170uint32_t CLOCK_GetUart0ClkFreq(void)
171{
172 return CLOCK_GetUartClkFreq();
173}
174
175/*! brief Return Frequency of UART1
176 * return Frequency of UART1
177 */
178uint32_t CLOCK_GetUart1ClkFreq(void)
179{
180 return CLOCK_GetUartClkFreq();
181}
182
183/*! brief Return Frequency of UART2
184 * return Frequency of UART2
185 */
186uint32_t CLOCK_GetUart2ClkFreq(void)
187{
188 return CLOCK_GetUartClkFreq();
189}
190
191/*! brief Return Frequency of selected clock
192 * return Frequency of selected clock
193 */
194uint32_t CLOCK_GetFreq(clock_name_t clockName)
195{
196 uint32_t freq;
197
198 switch (clockName)
199 {
200 case kCLOCK_CoreSysClk:
201 freq = CLOCK_GetCoreSysClkFreq();
202 break;
203 case kCLOCK_MainClk:
204 freq = CLOCK_GetMainClkFreq();
205 break;
206 case kCLOCK_Irc:
207 freq = CLOCK_GetIrcFreq();
208 break;
209 case kCLOCK_ExtClk:
210 freq = CLOCK_GetExtClkFreq();
211 break;
212 case kCLOCK_WdtOsc:
213 freq = CLOCK_GetWdtOscFreq();
214 break;
215 case kCLOCK_PllOut:
216 freq = CLOCK_GetSystemPLLFreq();
217 break;
218
219 default:
220 freq = 0U;
221 break;
222 }
223
224 return freq;
225}
226
227/*! brief Return System PLL input clock rate
228 * return System PLL input clock rate
229 */
230uint32_t CLOCK_GetSystemPLLInClockRate(void)
231{
232 uint32_t freq = 0U;
233
234 switch ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK))
235 {
236 /* source from external clock in */
237 case 0x00U:
238 freq = CLOCK_GetIrcFreq();
239 break;
240 /* source from the IRC clock */
241 case 0x01U:
242 freq = CLOCK_GetSysOscFreq();
243 break;
244 /* source from external clock clock */
245 case 0x03U:
246 freq = CLOCK_GetExtClkFreq();
247 break;
248
249 default:
250 assert(false);
251 break;
252 }
253
254 return freq;
255}
256
257static uint32_t findSyestemPllPsel(uint32_t outFreq)
258{
259 uint32_t pSel = 0U;
260
261 if (outFreq > (SYSPLL_MIN_FCCO_FREQ_HZ >> 1U))
262 {
263 pSel = 0U;
264 }
265 else if (outFreq > (SYSPLL_MIN_FCCO_FREQ_HZ >> 2U))
266 {
267 pSel = 1U;
268 }
269 else if (outFreq > (SYSPLL_MIN_FCCO_FREQ_HZ >> 3U))
270 {
271 pSel = 2U;
272 }
273 else
274 {
275 pSel = 3U;
276 }
277
278 return pSel;
279}
280
281/*! brief System PLL initialize.
282 * param config System PLL configurations.
283 */
284void CLOCK_InitSystemPll(const clock_sys_pll_t *config)
285{
286 assert(config->targetFreq <= SYSPLL_MAX_OUTPUT_FREQ_HZ);
287
288 uint32_t mSel = 0U, pSel = 0U, inputFreq = 0U;
289 uint32_t syspllclkseltmp;
290 /* Power off PLL during setup changes */
291 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSPLL_PD_MASK;
292
293 /*set system pll clock source select register */
294 syspllclkseltmp = (SYSCON->SYSPLLCLKSEL & (~SYSCON_SYSPLLCLKSEL_SEL_MASK)) | (uint32_t)config->src;
295 SYSCON->SYSPLLCLKSEL |= syspllclkseltmp;
296 /* system pll clock source update */
297 CLOCK_UpdateClkSrc((volatile uint32_t *)(&(SYSCON->SYSPLLCLKUEN)), SYSCON_SYSPLLCLKSEL_SEL_MASK);
298
299 inputFreq = CLOCK_GetSystemPLLInClockRate();
300 assert(inputFreq != 0U);
301
302 /* calucate the feedback divider value and post divider value*/
303 mSel = config->targetFreq / inputFreq;
304 pSel = findSyestemPllPsel(config->targetFreq);
305
306 /* configure PSEL and MSEL */
307 SYSCON->SYSPLLCTRL = (SYSCON->SYSPLLCTRL & (~(SYSCON_SYSPLLCTRL_MSEL_MASK | SYSCON_SYSPLLCTRL_PSEL_MASK))) |
308 SYSCON_SYSPLLCTRL_MSEL(mSel == 0U ? 0U : (mSel - 1U)) | SYSCON_SYSPLLCTRL_PSEL(pSel);
309
310 /* Power up PLL after setup changes */
311 SYSCON->PDRUNCFG &= ~SYSCON_PDRUNCFG_SYSPLL_PD_MASK;
312
313 /* wait pll lock */
314 while ((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) == 0U)
315 {
316 }
317
318 g_Sys_Pll_Freq = inputFreq * mSel;
319}
320
321/*! brief Init external CLK IN, select the CLKIN as the external clock source.
322 * param clkInFreq external clock in frequency.
323 */
324void CLOCK_InitExtClkin(uint32_t clkInFreq)
325{
326 /* remove the pull up and pull down resistors in the IOCON */
327 IOCON->PIO[IOCON_INDEX_PIO0_1] &= ~IOCON_PIO_MODE_MASK;
328 /* enable the 1 bit functions for CLKIN */
329 SWM0->PINENABLE0 &= ~SWM_PINENABLE0_CLKIN_MASK;
330 /* bypass system oscillator */
331 SYSCON->SYSOSCCTRL |= SYSCON_SYSOSCCTRL_BYPASS_MASK;
332 /* record the external clock rate */
333 g_Ext_Clk_Freq = clkInFreq;
334}
335
336/*! brief Init SYS OSC
337 * param oscFreq oscillator frequency value.
338 */
339void CLOCK_InitSysOsc(uint32_t oscFreq)
340{
341 uint32_t sysoscctrltmp;
342 /* remove the pull up and pull down resistors in the IOCON */
343 IOCON->PIO[IOCON_INDEX_PIO0_9] &= ~IOCON_PIO_MODE_MASK;
344 IOCON->PIO[IOCON_INDEX_PIO0_8] &= ~IOCON_PIO_MODE_MASK;
345 /* enable the 1 bit functions for XTALIN and XTALOUT */
346 SWM0->PINENABLE0 &= ~(SWM_PINENABLE0_XTALIN_MASK | SWM_PINENABLE0_XTALOUT_MASK);
347
348 /* system osc configure */
349 sysoscctrltmp = (SYSCON->SYSOSCCTRL & (~(SYSCON_SYSOSCCTRL_BYPASS_MASK | SYSCON_SYSOSCCTRL_FREQRANGE_MASK))) |
350 (oscFreq > SYSOSC_BOUNDARY_FREQ_HZ ? SYSCON_SYSOSCCTRL_FREQRANGE_MASK : 0U);
351 SYSCON->SYSOSCCTRL |= sysoscctrltmp;
352
353 /* enable system osc power first */
354 SYSCON->PDRUNCFG &= ~SYSCON_PDRUNCFG_SYSOSC_PD_MASK;
355
356 /* software delay 500USs */
357 SDK_DelayAtLeastUs(500U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
358
359 /* record the external clock rate */
360 g_Ext_Clk_Freq = oscFreq;
361}
362
363/*! brief Init watch dog OSC
364 * Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the
365 * listed frequency value. The watchdog oscillator is the clock source with the lowest power
366 * consumption. If accurate timing is required, use the FRO or system oscillator.
367 * The frequency of the watchdog oscillator is undefined after reset. The watchdog
368 * oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
369 * using the watchdog oscillator.
370 * Watchdog osc output frequency = wdtOscFreq / wdtOscDiv, should in range 9.3KHZ to 2.3MHZ.
371 * param wdtOscFreq watch dog analog part output frequency, reference _wdt_analog_output_freq.
372 * param wdtOscDiv watch dog analog part output frequency divider, shoule be a value >= 2U and multiple of 2
373 */
374void CLOCK_InitWdtOsc(clock_wdt_analog_freq_t wdtOscFreq, uint32_t wdtOscDiv)
375{
376 assert(wdtOscDiv >= 2U);
377
378 uint32_t wdtOscCtrl = SYSCON->WDTOSCCTRL;
379
380 wdtOscCtrl &= ~(SYSCON_WDTOSCCTRL_DIVSEL_MASK | SYSCON_WDTOSCCTRL_FREQSEL_MASK);
381
382 wdtOscCtrl |=
383 SYSCON_WDTOSCCTRL_DIVSEL((wdtOscDiv >> 1U) - 1U) | SYSCON_WDTOSCCTRL_FREQSEL(CLK_WDT_OSC_GET_REG(wdtOscFreq));
384
385 SYSCON->WDTOSCCTRL = wdtOscCtrl;
386
387 /* power up watchdog oscillator */
388 SYSCON->PDRUNCFG &= ~SYSCON_PDRUNCFG_WDTOSC_PD_MASK;
389 /* update watch dog oscillator value */
390 g_Wdt_Osc_Freq = CLK_WDT_OSC_GET_FREQ(wdtOscFreq) / wdtOscDiv;
391}
392
393/*! brief Set main clock reference source.
394 * param src, reference clock_main_clk_src_t to set the main clock source.
395 */
396void CLOCK_SetMainClkSrc(clock_main_clk_src_t src)
397{
398 uint32_t mainMux = CLK_MAIN_CLK_MUX_GET_MUX(src), mainPreMux = CLK_MAIN_CLK_MUX_GET_PRE_MUX(src);
399
400 if (((SYSCON->MAINCLKSEL & SYSCON_MAINCLKSEL_SEL_MASK) != mainPreMux) && (mainMux == 0U))
401 {
402 SYSCON->MAINCLKSEL = (SYSCON->MAINCLKSEL & (~SYSCON_MAINCLKSEL_SEL_MASK)) | SYSCON_MAINCLKSEL_SEL(mainPreMux);
403 CLOCK_UpdateClkSrc((volatile uint32_t *)(&(SYSCON->MAINCLKUEN)), SYSCON_MAINCLKUEN_ENA_MASK);
404 }
405}
406
407/*! brief Set UARTFRG
408 * param target UART clock src.
409 */
410bool CLOCK_SetUARTFRGClkFreq(uint32_t freq)
411{
412 uint32_t input = CLOCK_GetMainClkFreq();
413 uint32_t mul;
414
415 freq *= SYSCON->UARTCLKDIV;
416
417 /* The given frequency should not be 0. */
418 assert(0UL != freq);
419
420 if ((freq > input) || (input / freq >= 2U))
421 {
422 return false;
423 }
424
425 mul = (uint32_t)(((uint64_t)((uint64_t)input - freq) << 8U) / ((uint64_t)freq));
426
427 SYSCON->UARTFRGDIV = SYSCON_UARTFRGDIV_DIV_MASK;
428 SYSCON->UARTFRGMULT = SYSCON_UARTFRGMULT_MULT(mul);
429
430 return true;
431}
432
433/*! brief Update CLKOUT src
434 * param none.
435 */
436void CLOCK_UpdateClkOUTsrc(void)
437{
438 CLOCK_UpdateClkSrc((volatile uint32_t *)(&(SYSCON->CLKOUTUEN)), SYSCON_CLKOUTUEN_ENA_MASK);
439}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_clock.h
new file mode 100644
index 000000000..683574c8f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_clock.h
@@ -0,0 +1,562 @@
1/*
2 * Copyright 2017-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_common.h"
12
13/*! @addtogroup clock */
14/*! @{ */
15
16/*! @file */
17
18/*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22/*! @name Driver version */
23/*@{*/
24/*! @brief CLOCK driver version 2.4.2. */
25#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 2))
26/*@}*/
27
28/* Definition for delay API in clock driver, users can redefine it to the real application. */
29#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
30#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (30000000UL)
31#endif
32
33/*! @brief watchdog oscilltor clock frequency.
34 *
35 * This variable is used to store the watchdog oscillator frequency which is
36 * set by CLOCK_InitWdtOsc, and it is returned by CLOCK_GetWdtOscFreq.
37 */
38extern uint32_t g_Wdt_Osc_Freq;
39
40/*! @brief external clock frequency.
41 *
42 * This variable is used to store the external clock frequency which is include
43 * external oscillator clock and external clk in clock frequency value, it is
44 * set by CLOCK_InitExtClkin when CLK IN is used as external clock or by CLOCK_InitSysOsc
45 * when external oscillator is used as external clock ,and it is returned by
46 * CLOCK_GetExtClkFreq.
47 */
48extern uint32_t g_Ext_Clk_Freq;
49
50extern uint32_t g_Sys_Pll_Freq;
51
52/*! @brief Clock ip name array for ADC. */
53#define ADC_CLOCKS \
54 { \
55 kCLOCK_Adc, \
56 }
57/*! @brief Clock ip name array for ACMP. */
58#define ACMP_CLOCKS \
59 { \
60 kCLOCK_Acmp, \
61 }
62/*! @brief Clock ip name array for SWM. */
63#define SWM_CLOCKS \
64 { \
65 kCLOCK_Swm, \
66 }
67/*! @brief Clock ip name array for ROM. */
68#define ROM_CLOCKS \
69 { \
70 kCLOCK_Rom, \
71 }
72/*! @brief Clock ip name array for SRAM. */
73#define SRAM_CLOCKS \
74 { \
75 kCLOCK_Ram0_1, \
76 }
77/*! @brief Clock ip name array for IOCON. */
78#define IOCON_CLOCKS \
79 { \
80 kCLOCK_Iocon, \
81 }
82/*! @brief Clock ip name array for GPIO. */
83#define GPIO_CLOCKS \
84 { \
85 kCLOCK_Gpio0, \
86 }
87/*! @brief Clock ip name array for GPIO_INT. */
88#define GPIO_INT_CLOCKS \
89 { \
90 kCLOCK_GpioInt, \
91 }
92/*! @brief Clock ip name array for DMA. */
93#define DMA_CLOCKS \
94 { \
95 kCLOCK_Dma, \
96 }
97/*! @brief Clock ip name array for CRC. */
98#define CRC_CLOCKS \
99 { \
100 kCLOCK_Crc, \
101 }
102/*! @brief Clock ip name array for WWDT. */
103#define WWDT_CLOCKS \
104 { \
105 kCLOCK_Wwdt, \
106 }
107/*! @brief Clock ip name array for SCT0. */
108#define SCT_CLOCKS \
109 { \
110 kCLOCK_Sct, \
111 }
112/*! @brief Clock ip name array for I2C. */
113#define I2C_CLOCKS \
114 { \
115 kCLOCK_I2c0, \
116 }
117/*! @brief Clock ip name array for I2C. */
118#define USART_CLOCKS \
119 { \
120 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, \
121 }
122/*! @brief Clock ip name array for SPI. */
123#define SPI_CLOCKS \
124 { \
125 kCLOCK_Spi0, kCLOCK_Spi1, \
126 }
127/*! @brief Clock ip name array for MTB. */
128#define MTB_CLOCKS \
129 { \
130 kCLOCK_Mtb, \
131 }
132/*! @brief Clock ip name array for MRT. */
133#define MRT_CLOCKS \
134 { \
135 kCLOCK_Mrt, \
136 }
137/*! @brief Clock ip name array for WKT. */
138#define WKT_CLOCKS \
139 { \
140 kCLOCK_Wkt, \
141 }
142
143/*! @brief Internal used Clock definition only. */
144#define CLK_GATE_DEFINE(reg, bit) ((((reg)&0xFFU) << 8U) | ((bit)&0xFFU))
145#define CLK_GATE_GET_REG(x) (((x) >> 8U) & 0xFFU)
146#define CLK_GATE_GET_BITS_SHIFT(x) ((uint32_t)(x)&0xFFU)
147/* clock mux register definition */
148#define CLK_MUX_DEFINE(reg, mux) (((offsetof(SYSCON_Type, reg) & 0xFFU) << 8U) | ((mux)&0xFFU))
149#define CLK_MUX_GET_REG(x) ((volatile uint32_t *)(((uint32_t)(SYSCON)) + (((uint32_t)(x) >> 8U) & 0xFFU)))
150#define CLK_MUX_GET_MUX(x) ((uint32_t)(x)&0xFFU)
151#define CLK_MAIN_CLK_MUX_DEFINE(preMux, mux) ((preMux) << 8U | (mux))
152#define CLK_MAIN_CLK_MUX_GET_PRE_MUX(x) (((uint32_t)(x) >> 8U) & 0xFFU)
153#define CLK_MAIN_CLK_MUX_GET_MUX(x) ((uint32_t)(x)&0xFFU)
154/* clock divider register definition */
155#define CLK_DIV_DEFINE(reg) (((uint32_t)offsetof(SYSCON_Type, reg)) & 0xFFFU)
156#define CLK_DIV_GET_REG(x) *((volatile uint32_t *)(((uint32_t)(SYSCON)) + ((uint32_t)(x)&0xFFFU)))
157/* watch dog oscillator definition */
158#define CLK_WDT_OSC_DEFINE(freq, regValue) (((freq)&0xFFFFFFU) | (((regValue)&0xFFU) << 24U))
159#define CLK_WDT_OSC_GET_FREQ(x) ((uint32_t)(x)&0xFFFFFFU)
160#define CLK_WDT_OSC_GET_REG(x) (((uint32_t)(x) >> 24U) & 0xFFU)
161/* register offset */
162#define SYS_AHB_CLK_CTRL (0U)
163/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
164typedef enum _clock_ip_name
165{
166 kCLOCK_Sys = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 0U),
167 kCLOCK_Rom = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 1U),
168 kCLOCK_Ram0_1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 2U),
169 kCLOCK_Flashreg = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 3U),
170 kCLOCK_Flash = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 4U),
171 kCLOCK_I2c0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 5U),
172 kCLOCK_Gpio0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 6U),
173 kCLOCK_Swm = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 7U),
174 kCLOCK_Sct = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 8U),
175 kCLOCK_Wkt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 9U),
176 kCLOCK_Mrt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 10U),
177 kCLOCK_Spi0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 11U),
178 kCLOCK_Spi1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 12U),
179 kCLOCK_Crc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 13U),
180 kCLOCK_Uart0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 14U),
181 kCLOCK_Uart1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 15U),
182 kCLOCK_Uart2 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 16U),
183 kCLOCK_Wwdt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 17U),
184 kCLOCK_Iocon = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 18U),
185 kCLOCK_Acmp = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 19U),
186} clock_ip_name_t;
187
188/*! @brief Clock name used to get clock frequency. */
189typedef enum _clock_name
190{
191 kCLOCK_CoreSysClk, /*!< Cpu/AHB/AHB matrix/Memories,etc */
192 kCLOCK_MainClk, /*!< Main clock */
193 kCLOCK_SysOsc, /*!< Crystal Oscillator */
194 kCLOCK_Irc, /*!< IRC12M */
195 kCLOCK_ExtClk, /*!< External Clock */
196 kCLOCK_PllOut, /*!< PLL Output */
197 kCLOCK_Pllin, /*!< PLL Input */
198 kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
199} clock_name_t;
200
201/*! @brief Clock Mux Switches
202 *CLK_MUX_DEFINE(reg, mux)
203 *reg is used to define the mux register
204 *mux is used to define the mux value
205 *
206 */
207typedef enum _clock_select
208{
209
210 kSYSPLL_From_Irc = CLK_MUX_DEFINE(SYSPLLCLKSEL, 0U),
211 kSYSPLL_From_SysOsc = CLK_MUX_DEFINE(SYSPLLCLKSEL, 1U),
212 kSYSPLL_From_ExtClk = CLK_MUX_DEFINE(SYSPLLCLKSEL, 3U),
213
214 kMAINCLK_From_Irc = CLK_MUX_DEFINE(MAINCLKSEL, 0U),
215 kMAINCLK_From_SysPllIn = CLK_MUX_DEFINE(MAINCLKSEL, 1U),
216 kMAINCLK_From_WdtOsc = CLK_MUX_DEFINE(MAINCLKSEL, 2U),
217 kMAINCLK_From_SysPll = CLK_MUX_DEFINE(MAINCLKSEL, 3U),
218
219 kCLKOUT_From_Irc = CLK_MUX_DEFINE(CLKOUTSEL, 0U),
220 kCLKOUT_From_SysOsc = CLK_MUX_DEFINE(CLKOUTSEL, 1U),
221 kCLKOUT_From_WdtOsc = CLK_MUX_DEFINE(CLKOUTSEL, 2U),
222 kCLKOUT_From_MainClk = CLK_MUX_DEFINE(CLKOUTSEL, 3U)
223} clock_select_t;
224
225/*! @brief Clock divider
226 */
227typedef enum _clock_divider
228{
229
230 kCLOCK_DivUsartClk = CLK_DIV_DEFINE(UARTCLKDIV),
231 kCLOCK_DivClkOut = CLK_DIV_DEFINE(CLKOUTDIV),
232 kCLOCK_DivUartFrg = CLK_DIV_DEFINE(UARTFRGDIV),
233
234 kCLOCK_IOCONCLKDiv6 = CLK_DIV_DEFINE(IOCONCLKDIV6),
235 kCLOCK_IOCONCLKDiv5 = CLK_DIV_DEFINE(IOCONCLKDIV5),
236 kCLOCK_IOCONCLKDiv4 = CLK_DIV_DEFINE(IOCONCLKDIV4),
237 kCLOCK_IOCONCLKDiv3 = CLK_DIV_DEFINE(IOCONCLKDIV3),
238 kCLOCK_IOCONCLKDiv2 = CLK_DIV_DEFINE(IOCONCLKDIV2),
239 kCLOCK_IOCONCLKDiv1 = CLK_DIV_DEFINE(IOCONCLKDIV1),
240 kCLOCK_IOCONCLKDiv0 = CLK_DIV_DEFINE(IOCONCLKDIV0),
241
242} clock_divider_t;
243
244/*! @brief watch dog analog output frequency */
245typedef enum _clock_wdt_analog_freq
246{
247 kCLOCK_WdtAnaFreq0HZ = CLK_WDT_OSC_DEFINE(0U, 0U),
248 kCLOCK_WdtAnaFreq600KHZ = CLK_WDT_OSC_DEFINE(600000U, 1U),
249 kCLOCK_WdtAnaFreq1050KHZ = CLK_WDT_OSC_DEFINE(1050000U, 2u),
250 kCLOCK_WdtAnaFreq1400KHZ = CLK_WDT_OSC_DEFINE(1400000U, 3U),
251 kCLOCK_WdtAnaFreq1750KHZ = CLK_WDT_OSC_DEFINE(1750000U, 4U),
252 kCLOCK_WdtAnaFreq2100KHZ = CLK_WDT_OSC_DEFINE(2100000U, 5U),
253 kCLOCK_WdtAnaFreq2400KHZ = CLK_WDT_OSC_DEFINE(2400000U, 6U),
254 kCLOCK_WdtAnaFreq2700KHZ = CLK_WDT_OSC_DEFINE(2700000U, 7U),
255 kCLOCK_WdtAnaFreq3000KHZ = CLK_WDT_OSC_DEFINE(3000000U, 8U),
256 kCLOCK_WdtAnaFreq3250KHZ = CLK_WDT_OSC_DEFINE(3250000U, 9U),
257 kCLOCK_WdtAnaFreq3500KHZ = CLK_WDT_OSC_DEFINE(3500000U, 10U),
258 kCLOCK_WdtAnaFreq3750KHZ = CLK_WDT_OSC_DEFINE(3750000U, 11U),
259 kCLOCK_WdtAnaFreq4000KHZ = CLK_WDT_OSC_DEFINE(4000000U, 12U),
260 kCLOCK_WdtAnaFreq4200KHZ = CLK_WDT_OSC_DEFINE(4200000U, 13U),
261 kCLOCK_WdtAnaFreq4400KHZ = CLK_WDT_OSC_DEFINE(4400000U, 14U),
262 kCLOCK_WdtAnaFreq4600KHZ = CLK_WDT_OSC_DEFINE(4600000U, 15U),
263} clock_wdt_analog_freq_t;
264
265/*! @brief PLL clock definition.*/
266typedef enum _clock_sys_pll_src
267{
268 kCLOCK_SysPllSrcIrc = 0U, /*!< system pll source from FRO */
269 kCLOCK_SysPllSrcSysosc = 1U, /*!< system pll source from system osc */
270 kCLOCK_SysPllSrcExtClk = 3U, /*!< system pll source from ext clkin */
271} clock_sys_pll_src;
272
273/*!< Main clock source definition */
274typedef enum _clock_main_clk_src
275{
276 kCLOCK_MainClkSrcIrc = CLK_MAIN_CLK_MUX_DEFINE(0U, 0U), /*!< main clock source from FRO */
277 kCLOCK_MainClkSrcSysPllin = CLK_MAIN_CLK_MUX_DEFINE(1U, 0U), /*!< main clock source from pll input */
278 kCLOCK_MainClkSrcWdtOsc = CLK_MAIN_CLK_MUX_DEFINE(2U, 0U), /*!< main clock source from watchdog oscillator */
279 kCLOCK_MainClkSrcSysPll = CLK_MAIN_CLK_MUX_DEFINE(3U, 0U), /*!< main clock source from system pll */
280} clock_main_clk_src_t;
281
282/*! @brief PLL configuration structure */
283typedef struct _clock_sys_pll
284{
285 uint32_t targetFreq; /*!< System pll fclk output frequency, the output frequency should be lower than 100MHZ*/
286 clock_sys_pll_src src; /*!< System pll clock source */
287} clock_sys_pll_t;
288
289/*******************************************************************************
290 * API
291 ******************************************************************************/
292
293#if defined(__cplusplus)
294extern "C" {
295#endif /* __cplusplus */
296
297/*!
298 * @name Clock gate, mux, and divider.
299 * @{
300 */
301
302/*
303 *! @brief enable ip clock.
304 *
305 * @param clk clock ip definition.
306 */
307static inline void CLOCK_EnableClock(clock_ip_name_t clk)
308{
309 SYSCON->SYSAHBCLKCTRL |= 1UL << CLK_GATE_GET_BITS_SHIFT(clk);
310}
311
312/*
313 *!@brief disable ip clock.
314 *
315 * @param clk clock ip definition.
316 */
317static inline void CLOCK_DisableClock(clock_ip_name_t clk)
318{
319 SYSCON->SYSAHBCLKCTRL &= ~(1UL << CLK_GATE_GET_BITS_SHIFT(clk));
320}
321
322/*
323 *! @brief Configure the clock selection muxes.
324 * @param mux : Clock to be configured.
325 * @return Nothing
326 */
327static inline void CLOCK_Select(clock_select_t sel)
328{
329 *(CLK_MUX_GET_REG(sel)) = CLK_MUX_GET_MUX(sel);
330}
331
332/*
333 *! @brief Setup peripheral clock dividers.
334 * @param name : Clock divider name
335 * @param value: Value to be divided
336 * @return Nothing
337 */
338static inline void CLOCK_SetClkDivider(clock_divider_t name, uint32_t value)
339{
340 CLK_DIV_GET_REG(name) = value & 0xFFU;
341}
342
343/*
344 *! @brief Get peripheral clock dividers.
345 * @param name : Clock divider name
346 * @return clock divider value
347 */
348static inline uint32_t CLOCK_GetClkDivider(clock_divider_t name)
349{
350 return CLK_DIV_GET_REG(name) & 0xFFU;
351}
352
353/*
354 *! @brief Setup Core clock dividers.
355 * Be careful about the core divider value, due to core/system frequency should be lower than 30MHZ.
356 * @param value: Value to be divided
357 * @return Nothing
358 */
359static inline void CLOCK_SetCoreSysClkDiv(uint32_t value)
360{
361 assert(value != 0U);
362
363 SYSCON->SYSAHBCLKDIV = (SYSCON->SYSAHBCLKDIV & (~SYSCON_SYSAHBCLKDIV_DIV_MASK)) | SYSCON_SYSAHBCLKDIV_DIV(value);
364}
365
366/*! @brief Set main clock reference source.
367 * @param src, reference clock_main_clk_src_t to set the main clock source.
368 */
369void CLOCK_SetMainClkSrc(clock_main_clk_src_t src);
370
371/*
372 *! @brief Set Fractional generator 0 multiplier value.
373 * @param mul : FRG0 multiplier value.
374 * @return Nothing
375 */
376static inline void CLOCK_SetFRGClkMul(uint32_t mul)
377{
378 SYSCON->UARTFRGDIV = SYSCON_UARTFRGDIV_DIV_MASK;
379 SYSCON->UARTFRGMULT = SYSCON_UARTFRGMULT_MULT(mul);
380}
381/* @} */
382
383/*!
384 * @name Get frequency
385 * @{
386 */
387
388/*! @brief Return Frequency of Main Clock.
389 * @return Frequency of Main Clock.
390 */
391uint32_t CLOCK_GetMainClkFreq(void);
392
393/*! @brief Return Frequency of core.
394 * @return Frequency of core.
395 */
396static inline uint32_t CLOCK_GetCoreSysClkFreq(void)
397{
398 return CLOCK_GetMainClkFreq() / (SYSCON->SYSAHBCLKDIV & 0xffU);
399}
400
401/*! @brief Return Frequency of ClockOut
402 * @return Frequency of ClockOut
403 */
404uint32_t CLOCK_GetClockOutClkFreq(void);
405
406/*! @brief Return Frequency of IRC
407 * @return Frequency of IRC
408 */
409uint32_t CLOCK_GetIrcFreq(void);
410
411/*! @brief Return Frequency of SYSOSC
412 * @return Frequency of SYSOSC
413 */
414uint32_t CLOCK_GetSysOscFreq(void);
415
416/*! @brief Get UART0 frequency
417 * @retval UART0 frequency value.
418 */
419uint32_t CLOCK_GetUartClkFreq(void);
420
421/*! @brief Get UART0 frequency
422 * @retval UART0 frequency value.
423 */
424uint32_t CLOCK_GetUart0ClkFreq(void);
425
426/*! @brief Get UART1 frequency
427 * @retval UART1 frequency value.
428 */
429uint32_t CLOCK_GetUart1ClkFreq(void);
430
431/*! @brief Get UART2 frequency
432 * @retval UART2 frequency value.
433 */
434uint32_t CLOCK_GetUart2ClkFreq(void);
435
436/*! @brief Return Frequency of selected clock
437 * @return Frequency of selected clock
438 */
439uint32_t CLOCK_GetFreq(clock_name_t clockName);
440
441/*! @brief Return System PLL input clock rate
442 * @return System PLL input clock rate
443 */
444uint32_t CLOCK_GetSystemPLLInClockRate(void);
445
446/*! @brief Return Frequency of System PLL
447 * @return Frequency of PLL
448 */
449static inline uint32_t CLOCK_GetSystemPLLFreq(void)
450{
451 return CLOCK_GetSystemPLLInClockRate() * ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK) + 1U);
452}
453
454/*! @brief Get watch dog OSC frequency
455 * @retval watch dog OSC frequency value.
456 */
457static inline uint32_t CLOCK_GetWdtOscFreq(void)
458{
459 return g_Wdt_Osc_Freq;
460}
461
462/*! @brief Get external clock frequency
463 * @retval external clock frequency value.
464 */
465static inline uint32_t CLOCK_GetExtClkFreq(void)
466{
467 return g_Ext_Clk_Freq;
468}
469/* @} */
470
471/*!
472 * @name PLL operations
473 * @{
474 */
475
476/*! @brief System PLL initialize.
477 * @param config System PLL configurations.
478 */
479void CLOCK_InitSystemPll(const clock_sys_pll_t *config);
480
481/*! @brief System PLL Deinitialize.*/
482static inline void CLOCK_DenitSystemPll(void)
483{
484 /* Power off PLL */
485 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSPLL_PD_MASK;
486}
487
488/* @} */
489
490/*!
491 * @name External/internal oscillator clock operations
492 * @{
493 */
494
495/*! @brief Init external CLK IN, select the CLKIN as the external clock source.
496 * @param clkInFreq external clock in frequency.
497 */
498void CLOCK_InitExtClkin(uint32_t clkInFreq);
499
500/*! @brief Init SYS OSC
501 * @param oscFreq oscillator frequency value.
502 */
503void CLOCK_InitSysOsc(uint32_t oscFreq);
504
505/*! @brief Deinit SYS OSC
506 * @param config oscillator configuration.
507 */
508static inline void CLOCK_DeinitSysOsc(void)
509{
510 /* Deinit system osc power */
511 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSOSC_PD_MASK;
512}
513
514/*! @brief Init watch dog OSC
515 * Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the
516 * listed frequency value. The watchdog oscillator is the clock source with the lowest power
517 * consumption. If accurate timing is required, use the FRO or system oscillator.
518 * The frequency of the watchdog oscillator is undefined after reset. The watchdog
519 * oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
520 * using the watchdog oscillator.
521 * Watchdog osc output frequency = wdtOscFreq / wdtOscDiv, should in range 9.3KHZ to 2.3MHZ.
522 * @param wdtOscFreq watch dog analog part output frequency, reference _wdt_analog_output_freq.
523 * @param wdtOscDiv watch dog analog part output frequency divider, shoule be a value >= 2U and multiple of 2
524 */
525void CLOCK_InitWdtOsc(clock_wdt_analog_freq_t wdtOscFreq, uint32_t wdtOscDiv);
526
527/*! @brief Deinit watch dog OSC
528 * @param config oscillator configuration.
529 */
530static inline void CLOCK_DeinitWdtOsc(void)
531{
532 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_WDTOSC_PD_MASK;
533}
534
535/*! @brief Set UARTFRG
536 * @param target UART clock src.
537 */
538bool CLOCK_SetUARTFRGClkFreq(uint32_t freq);
539
540/*! @brief Set UARTFRGMULT
541 * @deprecated Do not use this function. Refer to CLOCK_SetFRGClkMul().
542 * @param UARTFRGMULT.
543 */
544static inline void CLOCK_SetUARTFRGMULT(uint32_t mul)
545{
546 SYSCON->UARTFRGMULT = SYSCON_UARTFRGMULT_MULT(mul);
547}
548
549/*! @brief Update CLKOUT src
550 * @param none.
551 */
552void CLOCK_UpdateClkOUTsrc(void);
553
554/* @} */
555
556#if defined(__cplusplus)
557}
558#endif /* __cplusplus */
559
560/*! @} */
561
562#endif /* _FSL_CLOCK_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_power.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_power.c
new file mode 100644
index 000000000..9ed77304b
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_power.c
@@ -0,0 +1,167 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2018, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8#include "fsl_power.h"
9/* Component ID definition, used by tools. */
10#ifndef FSL_COMPONENT_ID
11#define FSL_COMPONENT_ID "platform.drivers.power_no_lib"
12#endif
13/*******************************************************************************
14 * Definitions
15 ******************************************************************************/
16
17/*******************************************************************************
18 * Code
19 ******************************************************************************/
20/*!
21 * brief API to enter sleep power mode.
22 *
23 * return none
24 */
25void POWER_EnterSleep(void)
26{
27 uint32_t pmsk;
28
29 pmsk = __get_PRIMASK();
30 __disable_irq();
31
32 /* sleep mode */
33 PMU->PCON &= ~PMU_PCON_PM_MASK;
34 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
35 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
36
37 /* Enter powerdown mode */
38 __WFI();
39
40 __set_PRIMASK(pmsk);
41
42}
43
44/*!
45 * brief API to enter deep sleep power mode.
46 *
47 * param activePart: should be a single or combine value of _power_deep_sleep_active .
48 * return none
49 */
50void POWER_EnterDeepSleep(uint32_t activePart)
51{
52 assert((SYSCON->MAINCLKSEL & SYSCON_MAINCLKSEL_SEL_MASK) == 0U);
53
54 uint32_t pmsk;
55
56 pmsk = __get_PRIMASK();
57 __disable_irq();
58
59 PMU->PCON = (PMU->PCON & (~PMU_PCON_PM_MASK)) | PMU_PCON_PM(kPmu_Deep_Sleep);
60
61 /* remain active during power down mode */
62 SYSCON->PDSLEEPCFG &= ~activePart;
63
64 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
65 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
66
67 /* Enter powerdown mode */
68 __WFI();
69
70 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
71 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
72 __set_PRIMASK(pmsk);
73}
74
75/*!
76 * brief API to enter power down mode.
77 *
78 * param activePart: should be a single or combine value of _power_deep_sleep_active .
79 * return none
80 */
81void POWER_EnterPowerDown(uint32_t activePart)
82{
83 assert((SYSCON->MAINCLKSEL & SYSCON_MAINCLKSEL_SEL_MASK) == 0U);
84
85 uint32_t pmsk;
86
87 pmsk = __get_PRIMASK();
88 __disable_irq();
89
90 PMU->PCON = (PMU->PCON & (~PMU_PCON_PM_MASK)) | PMU_PCON_PM(kPmu_PowerDown);
91
92 /* remain active during power down mode */
93 SYSCON->PDSLEEPCFG &= ~activePart;
94
95 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
96 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
97
98 /* Enter powerdown mode */
99 __WFI();
100
101 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
102 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
103 __set_PRIMASK(pmsk);
104}
105
106/*!
107 * brief API to enter deep power down mode.
108 *
109 * return none
110 */
111void POWER_EnterDeepPowerDownMode(void)
112{
113 uint32_t pmsk;
114
115 pmsk = __get_PRIMASK();
116 __disable_irq();
117
118 /* make sure NODPD is cleared */
119 PMU->PCON = (PMU->PCON & (~(PMU_PCON_PM_MASK | PMU_PCON_NODPD_MASK))) | PMU_PCON_PM(kPmu_Deep_PowerDown);
120
121 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
122 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
123
124 /* Enter powerdown mode */
125 __WFI();
126
127 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
128 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
129 __set_PRIMASK(pmsk);
130}
131
132void EnableDeepSleepIRQ(IRQn_Type interrupt)
133{
134 uint32_t intNumber = (uint32_t)interrupt;
135
136 if(intNumber >= 24u)
137 {
138 /* enable pin interrupt wake up in the STARTERP0 register */
139 SYSCON->STARTERP0 |= 1UL << (intNumber - 24u);
140 }
141 else
142 {
143 /* enable interrupt wake up in the STARTERP1 register */
144 SYSCON->STARTERP1 |= 1UL << intNumber;
145 }
146 /* also enable interrupt at NVIC */
147 (void)EnableIRQ(interrupt);
148}
149
150void DisableDeepSleepIRQ(IRQn_Type interrupt)
151{
152 uint32_t intNumber = (uint32_t)interrupt;
153
154 /* also disable interrupt at NVIC */
155 (void)DisableIRQ(interrupt);
156
157 if(intNumber >= 24u)
158 {
159 /* disable pin interrupt wake up in the STARTERP0 register */
160 SYSCON->STARTERP0 &= ~(1UL << (intNumber - 24u));
161 }
162 else
163 {
164 /* disable interrupt wake up in the STARTERP1 register */
165 SYSCON->STARTERP1 &= ~(1UL << intNumber);
166 }
167}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_power.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_power.h
new file mode 100644
index 000000000..53de59a2d
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_power.h
@@ -0,0 +1,372 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2018, 2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8#ifndef _FSL_POWER_H_
9#define _FSL_POWER_H_
10
11#include "fsl_common.h"
12
13/*******************************************************************************
14 * Definitions
15 ******************************************************************************/
16
17/*!
18 * @addtogroup power
19 * @{
20 */
21
22/*! @name Driver version */
23/*@{*/
24/*! @brief power driver version 2.0.4. */
25#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
26/*@}*/
27
28/*! @brief PMU PCON reserved mask, used to clear reserved field which should not write 1*/
29#define PMUC_PCON_RESERVED_MASK ((0xf << 4) | (0x6 << 8) | 0xfffff000u)
30
31#define POWER_EnbaleLPO POWER_EnableLPO
32#define POWER_EnbaleLPOInDeepPowerDownMode POWER_EnableLPOInDeepPowerDownMode
33
34typedef enum pd_bits
35{
36 kPDRUNCFG_PD_IRC_OUT = SYSCON_PDRUNCFG_IRCOUT_PD_MASK,
37 kPDRUNCFG_PD_IRC = SYSCON_PDRUNCFG_IRC_PD_MASK,
38 kPDRUNCFG_PD_FLASH = SYSCON_PDRUNCFG_FLASH_PD_MASK,
39 kPDRUNCFG_PD_BOD = SYSCON_PDRUNCFG_BOD_PD_MASK,
40 kPDRUNCFG_PD_SYSOSC = SYSCON_PDRUNCFG_SYSOSC_PD_MASK,
41 kPDRUNCFG_PD_WDT_OSC = SYSCON_PDRUNCFG_WDTOSC_PD_MASK,
42 kPDRUNCFG_PD_SYSPLL = SYSCON_PDRUNCFG_SYSPLL_PD_MASK,
43 kPDRUNCFG_PD_ACMP = SYSCON_PDRUNCFG_ACMP_MASK,
44
45 /*
46 This enum member has no practical meaning,it is used to avoid MISRA issue,
47 user should not trying to use it.
48 */
49 kPDRUNCFG_ForceUnsigned = (int)0x80000000U,
50} pd_bit_t;
51
52/*! @brief Deep sleep and power down mode wake up configurations */
53enum _power_wakeup
54{
55 kPDAWAKECFG_Wakeup_IRC_OUT = SYSCON_PDAWAKECFG_IRCOUT_PD_MASK,
56 kPDAWAKECFG_Wakeup_IRC = SYSCON_PDAWAKECFG_IRC_PD_MASK,
57 kPDAWAKECFG_Wakeup_FLASH = SYSCON_PDAWAKECFG_FLASH_PD_MASK,
58 kPDAWAKECFG_Wakeup_BOD = SYSCON_PDAWAKECFG_BOD_PD_MASK,
59 kPDAWAKECFG_Wakeup_SYSOSC = SYSCON_PDAWAKECFG_SYSOSC_PD_MASK,
60 kPDAWAKECFG_Wakeup_WDT_OSC = SYSCON_PDAWAKECFG_WDTOSC_PD_MASK,
61 kPDAWAKECFG_Wakeup_SYSPLL = SYSCON_PDAWAKECFG_SYSPLL_PD_MASK,
62 kPDAWAKECFG_Wakeup_ACMP = SYSCON_PDAWAKECFG_ACMP_MASK,
63};
64
65/*! @brief Deep sleep/power down mode active part */
66enum _power_deep_sleep_active
67{
68 kPDSLEEPCFG_DeepSleepBODActive = SYSCON_PDSLEEPCFG_BOD_PD_MASK,
69 kPDSLEEPCFG_DeepSleepWDTOscActive = SYSCON_PDSLEEPCFG_WDTOSC_PD_MASK,
70};
71
72/*! @brief pmu general purpose register index */
73typedef enum _power_gen_reg
74{
75 kPmu_GenReg0 = 0U, /*!< general purpose register0 */
76 kPmu_GenReg1 = 1U, /*!< general purpose register1 */
77 kPmu_GenReg2 = 2U, /*!< general purpose register2 */
78 kPmu_GenReg3 = 3U, /*!< general purpose register3 */
79 kPmu_GenReg4 = 4U, /*!< DPDCTRL bit 31-4 */
80} power_gen_reg_t;
81
82/* Power mode configuration API parameter */
83typedef enum _power_mode_config
84{
85 kPmu_Sleep = 0U,
86 kPmu_Deep_Sleep = 1U,
87 kPmu_PowerDown = 2U,
88 kPmu_Deep_PowerDown = 3U,
89} power_mode_cfg_t;
90
91/*******************************************************************************
92 * API
93 ******************************************************************************/
94
95#ifdef __cplusplus
96extern "C" {
97#endif
98
99/*!
100 * @name SYSCON Power Configuration
101 * @{
102 */
103
104/*!
105 * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
106 *
107 * @param en peripheral for which to enable the PDRUNCFG bit
108 * @return none
109 */
110static inline void POWER_EnablePD(pd_bit_t en)
111{
112 SYSCON->PDRUNCFG |= (uint32_t)en;
113}
114
115/*!
116 * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
117 *
118 * @param en peripheral for which to disable the PDRUNCFG bit
119 * @return none
120 */
121static inline void POWER_DisablePD(pd_bit_t en)
122{
123 SYSCON->PDRUNCFG &= ~(uint32_t)en;
124}
125
126/*!
127 * @brief API to config wakeup configurations for deep sleep mode and power down mode.
128 *
129 * @param mask: wake up configurations for deep sleep mode and power down mode, reference _power_wakeup.
130 * @param powerDown: true is power down the mask part, false is powered part.
131 */
132static inline void POWER_WakeUpConfig(uint32_t mask, bool powerDown)
133{
134 if (powerDown)
135 {
136 SYSCON->PDAWAKECFG |= mask;
137 }
138 else
139 {
140 SYSCON->PDAWAKECFG &= ~mask;
141 }
142}
143
144/*!
145 * @brief API to config active part for deep sleep mode and power down mode.
146 *
147 * @param mask: active part configurations for deep sleep mode and power down mode, reference _power_deep_sleep_active.
148 * @param powerDown: true is power down the mask part, false is powered part.
149 */
150static inline void POWER_DeepSleepConfig(uint32_t mask, bool powerDown)
151{
152 if (powerDown)
153 {
154 SYSCON->PDSLEEPCFG |= mask;
155 }
156 else
157 {
158 SYSCON->PDSLEEPCFG &= ~mask;
159 }
160}
161
162/* @} */
163
164/*!
165 * @name ARM core Power Configuration
166 * @{
167 */
168
169/*!
170 * @brief API to enable deep sleep bit in the ARM Core.
171 *
172 * @return none
173 */
174static inline void POWER_EnableDeepSleep(void)
175{
176 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
177}
178
179/*!
180 * @brief API to disable deep sleep bit in the ARM Core.
181 *
182 * @return none
183 */
184static inline void POWER_DisableDeepSleep(void)
185{
186 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
187}
188
189/* @} */
190
191/*!
192 * @name PMU functionality
193 * @{
194 */
195
196/*!
197 * @brief API to enter sleep power mode.
198 *
199 * @return none
200 */
201void POWER_EnterSleep(void);
202
203/*!
204 * @brief API to enter deep sleep power mode.
205 *
206 * @param activePart: should be a single or combine value of _power_deep_sleep_active .
207 * @return none
208 */
209void POWER_EnterDeepSleep(uint32_t activePart);
210
211/*!
212 * @brief API to enter power down mode.
213 *
214 * @param activePart: should be a single or combine value of _power_deep_sleep_active .
215 * @return none
216 */
217void POWER_EnterPowerDown(uint32_t activePart);
218
219/*!
220 * @brief API to enter deep power down mode.
221 *
222 * @return none
223 */
224void POWER_EnterDeepPowerDownMode(void);
225
226/*!
227 * @brief API to get sleep mode flag.
228 *
229 * @return sleep mode flag: 0 is active mode, 1 is sleep mode entered.
230 */
231static inline uint32_t POWER_GetSleepModeFlag(void)
232{
233 return (PMU->PCON & PMU_PCON_SLEEPFLAG_MASK) >> PMU_PCON_SLEEPFLAG_SHIFT;
234}
235
236/*!
237 * @brief API to clear sleep mode flag.
238 *
239 */
240static inline void POWER_ClrSleepModeFlag(void)
241{
242 PMU->PCON |= PMU_PCON_SLEEPFLAG_MASK;
243}
244
245/*!
246 * @brief API to get deep power down mode flag.
247 *
248 * @return sleep mode flag: 0 not deep power down, 1 is deep power down mode entered.
249 */
250static inline uint32_t POWER_GetDeepPowerDownModeFlag(void)
251{
252 return (PMU->PCON & PMU_PCON_DPDFLAG_MASK) >> PMU_PCON_DPDFLAG_SHIFT;
253}
254
255/*!
256 * @brief API to clear deep power down mode flag.
257 *
258 */
259static inline void POWER_ClrDeepPowerDownModeFlag(void)
260{
261 PMU->PCON |= PMU_PCON_DPDFLAG_MASK;
262}
263
264/*!
265 * @brief API to enable non deep power down mode.
266 *
267 * @param enable: true is enable non deep power down, otherwise disable.
268 */
269static inline void POWER_EnableNonDpd(bool enable)
270{
271 if (enable)
272 {
273 PMU->PCON |= PMU_PCON_NODPD_MASK;
274 }
275 else
276 {
277 PMU->PCON &= ~PMU_PCON_NODPD_MASK;
278 }
279}
280
281/*!
282 * @brief API to enable LPO.
283 *
284 * @param enable: true to enable LPO, false to disable LPO.
285 */
286static inline void POWER_EnableLPO(bool enable)
287{
288 if (enable)
289 {
290 PMU->DPDCTRL |= PMU_DPDCTRL_LPOSCEN_MASK;
291 }
292 else
293 {
294 PMU->DPDCTRL &= ~PMU_DPDCTRL_LPOSCEN_MASK;
295 }
296}
297
298/*!
299 * @brief API to enable LPO in deep power down mode.
300 *
301 * @param enable: true to enable LPO, false to disable LPO.
302 */
303static inline void POWER_EnableLPOInDeepPowerDownMode(bool enable)
304{
305 if (enable)
306 {
307 PMU->DPDCTRL |= PMU_DPDCTRL_LPOSCDPDEN_MASK;
308 }
309 else
310 {
311 PMU->DPDCTRL &= ~PMU_DPDCTRL_LPOSCDPDEN_MASK;
312 }
313}
314
315/*!
316 * @brief API to retore data to general purpose register which can be retain during deep power down mode.
317 * Note the kPMU_GenReg4 can retore 3 byte data only, so the general purpose register can store 19bytes data.
318 * @param index: general purpose data register index.
319 * @param data: data to restore.
320 */
321static inline void POWER_SetRetainData(power_gen_reg_t index, uint32_t data)
322{
323 if (index <= kPmu_GenReg3)
324 {
325 PMU->GPREG[index] = data;
326 }
327 else
328 {
329 /* only 28 bits can store in GPDATA field */
330 PMU->DPDCTRL = (PMU->DPDCTRL & (~PMU_DPDCTRL_GPDATA_MASK)) | PMU_DPDCTRL_GPDATA(data);
331 }
332}
333
334/*!
335 * @brief API to get data from general purpose register which retain during deep power down mode.
336 * Note the kPMU_GenReg4 can retore 3 byte data only, so the general purpose register can store 19bytes data.
337 * @param index: general purpose data register index.
338 * @return data stored in the general purpose register.
339 */
340static inline uint32_t POWER_GetRetainData(power_gen_reg_t index)
341{
342 if (index == kPmu_GenReg4)
343 {
344 return (PMU->DPDCTRL & PMU_DPDCTRL_GPDATA_MASK) >> PMU_DPDCTRL_GPDATA_SHIFT;
345 }
346
347 return PMU->GPREG[index];
348}
349
350/*!
351 * @brief API to enable wake up pin for deep power down mode.
352 *
353 * @param enable: true is enable, otherwise disable.
354 * @param enHysteresis: true is enable Hysteresis for the pin, otherwise disable.
355 */
356static inline void POWER_EnableWakeupPinForDeepPowerDown(bool enable, bool enHysteresis)
357{
358 PMU->DPDCTRL = (PMU->DPDCTRL & (~(PMU_DPDCTRL_WAKEUPHYS_MASK | PMU_DPDCTRL_WAKEPAD_DISABLE_MASK))) |
359 PMU_DPDCTRL_WAKEPAD_DISABLE(!enable) | PMU_DPDCTRL_WAKEUPHYS(enHysteresis);
360}
361
362/* @} */
363
364#ifdef __cplusplus
365}
366#endif
367
368/*!
369 * @}
370 */
371
372#endif /* _FSL_POWER_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_reset.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_reset.c
new file mode 100644
index 000000000..e081cbe08
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_reset.c
@@ -0,0 +1,92 @@
1/*
2 * Copyright 2017, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "fsl_reset.h"
10
11/*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14/* Component ID definition, used by tools. */
15#ifndef FSL_COMPONENT_ID
16#define FSL_COMPONENT_ID "platform.drivers.reset"
17#endif
18
19/*******************************************************************************
20 * Variables
21 ******************************************************************************/
22
23/*******************************************************************************
24 * Prototypes
25 ******************************************************************************/
26
27/*!
28* @brief Assert reset to peripheral.
29*
30* Asserts reset signal to specified peripheral module.
31*
32* @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
33* and reset bit position in the reset register.
34*/
35static void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
36
37/*!
38 * @brief Clear reset to peripheral.
39 *
40 * Clears reset signal to specified peripheral module, allows it to operate.
41 *
42 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
43 * and reset bit position in the reset register.
44 */
45static void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
46
47/*******************************************************************************
48 * Code
49 ******************************************************************************/
50
51#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
52 (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
53
54static void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
55{
56 const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
57 const uint32_t bitMask = 1UL << bitPos;
58
59 assert(bitPos < 32UL);
60
61 /* reset register is in SYSCON */
62 /* set bit */
63 SYSCON->PRESETCTRL &= ~bitMask;
64}
65
66static void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
67{
68 const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
69 const uint32_t bitMask = 1UL << bitPos;
70
71 assert(bitPos < 32UL);
72
73 /* reset register is in SYSCON */
74 /* clear bit */
75 SYSCON->PRESETCTRL |= bitMask;
76}
77
78/*!
79 * brief Reset peripheral module.
80 *
81 * Reset peripheral module.
82 *
83 * param peripheral Peripheral to reset. The enum argument contains encoding of reset register
84 * and reset bit position in the reset register.
85 */
86void RESET_PeripheralReset(reset_ip_name_t peripheral)
87{
88 RESET_SetPeripheralReset(peripheral);
89 RESET_ClearPeripheralReset(peripheral);
90}
91
92#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_reset.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_reset.h
new file mode 100644
index 000000000..d92863d9d
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_reset.h
@@ -0,0 +1,140 @@
1/*
2 * Copyright 2017, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_RESET_H_
9#define _FSL_RESET_H_
10
11#include <assert.h>
12#include <stdbool.h>
13#include <stdint.h>
14#include <string.h>
15#include "fsl_device_registers.h"
16
17/*!
18 * @addtogroup reset
19 * @{
20 */
21
22/*******************************************************************************
23 * Definitions
24 ******************************************************************************/
25
26/*! @name Driver version */
27/*@{*/
28/*! @brief reset driver version 2.0.2. */
29#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
30/*@}*/
31
32/*!
33 * @brief Enumeration for peripheral reset control bits
34 *
35 * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
36 */
37typedef enum _SYSCON_RSTn
38{
39 kSPI0_RST_N_SHIFT_RSTn = 0 | 0U, /**< SPI0 reset control. */
40 kSPI1_RST_N_SHIFT_RSTn = 0 | 1U, /**< SPI1 reset control */
41 kUARTFRG_RST_N_SHIFT_RSTn = 0 | 2U, /**< UARTFRG reset control */
42 kUART0_RST_N_SHIFT_RSTn = 0 | 3U, /**< UART0 reset control */
43 kUART1_RST_N_SHIFT_RSTn = 0 | 4U, /**< UART1 reset control */
44 kUART2_RST_N_SHIFT_RSTn = 0 | 5U, /**< UART2 reset control */
45 kI2C0_RST_N_SHIFT_RSTn = 0 | 6U, /**< I2C0 reset control */
46 kMRT_RST_N_SHIFT_RSTn = 0 | 7U, /**< Multi-rate timer(MRT) reset control */
47 kSCT_RST_N_SHIFT_RSTn = 0 | 8U, /**< SCT reset control */
48 kWKT_RST_N_SHIFT_RSTn = 0 | 9U, /**< Self-wake-up timer(WKT) reset control */
49 kGPIO0_RST_N_SHIFT_RSTn = 0 | 10U, /**< GPIO0 reset control */
50 kFLASH_RST_N_SHIFT_RSTn = 0 | 11U, /**< Flash controller reset control */
51 kACMP_RST_N_SHIFT_RSTn = 0 | 12U, /**< Analog comparator reset control */
52 kCRC_RST_SHIFT_RSTn = 0 | 13U, /**< CRC reset control */
53 kI2C1_RST_N_SHIFT_RSTn = 0 | 14U, /**< I2C1 reset control */
54 kI2C2_RST_N_SHIFT_RSTn = 0 | 15U, /**< I2C2 reset control */
55 kI2C3_RST_N_SHIFT_RSTn = 0 | 16U, /**< I2C3 reset control */
56 kADC_RST_N_SHIFT_RSTn = 0 | 24U, /**< ADC reset control */
57 kDMA_RST_N_SHIFT_RSTn = 0 | 29U, /**< DMA reset control */
58
59} SYSCON_RSTn_t;
60
61/** Array initializers with peripheral reset bits **/
62#define FLASH_RSTS_N \
63 { \
64 kFLASH_RST_N_SHIFT_RSTn \
65 } /* Reset bits for Flash peripheral */
66#define I2C_RSTS_N \
67 { \
68 kI2C0_RST_N_SHIFT_RSTn, kI2C1_RST_N_SHIFT_RSTn, kI2C2_RST_N_SHIFT_RSTn, kI2C3_RST_N_SHIFT_RSTn \
69 } /* Reset bits for I2C peripheral */
70#define GPIO_RSTS_N \
71 { \
72 kGPIO0_RST_N_SHIFT_RSTn \
73 } /* Reset bits for GPIO peripheral */
74#define SWM_RSTS_N \
75 { \
76 kSWM_RST_N_SHIFT_RSTn \
77 } /* Reset bits for SWM peripheral */
78#define SCT_RSTS_N \
79 { \
80 kSCT_RST_N_SHIFT_RSTn \
81 } /* Reset bits for SCT peripheral */
82#define WKT_RSTS_N \
83 { \
84 kWKT_RST_N_SHIFT_RSTn \
85 } /* Reset bits for WKT peripheral */
86#define MRT_RSTS_N \
87 { \
88 kMRT_RST_N_SHIFT_RSTn \
89 } /* Reset bits for MRT peripheral */
90#define SPI_RSTS_N \
91 { \
92 kSPI0_RST_N_SHIFT_RSTn, kSPI1_RST_N_SHIFT_RSTn \
93 } /* Reset bits for SPI peripheral */
94#define UART_RSTS_N \
95 { \
96 kUART0_RST_N_SHIFT_RSTn, kUART1_RST_N_SHIFT_RSTn, kUART2_RST_N_SHIFT_RSTn \
97 } /* Reset bits for UART peripheral */
98#define ACMP_RSTS_N \
99 { \
100 kACMP_RST_N_SHIFT_RSTn \
101 } /* Reset bits for ACMP peripheral */
102#define ADC_RSTS_N \
103 { \
104 kADC_RST_N_SHIFT_RSTn \
105 } /* Reset bits for ADC peripheral */
106#define DAC_RSTS_N \
107 { \
108 kDAC0_RST_N_SHIFT_RSTn, kDAC1_RST_N_SHIFT_RSTn \
109 } /* Reset bits for DAC peripheral */
110#define DMA_RSTS_N \
111 { \
112 kDMA_RST_N_SHIFT_RSTn \
113 } /* Reset bits for DMA peripheral */
114
115typedef SYSCON_RSTn_t reset_ip_name_t;
116
117/*******************************************************************************
118 * API
119 ******************************************************************************/
120#if defined(__cplusplus)
121extern "C" {
122#endif
123
124/*!
125 * @brief Reset peripheral module.
126 *
127 * Reset peripheral module.
128 *
129 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
130 * and reset bit position in the reset register.
131 */
132void RESET_PeripheralReset(reset_ip_name_t peripheral);
133
134#if defined(__cplusplus)
135}
136#endif
137
138/*! @} */
139
140#endif /* _FSL_RESET_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_swm_connections.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_swm_connections.h
new file mode 100644
index 000000000..db9360cb4
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_swm_connections.h
@@ -0,0 +1,125 @@
1/*
2 * Copyright 2017 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_SWM_CONNECTIONS_
10#define _FSL_SWM_CONNECTIONS_
11
12#include "fsl_common.h"
13
14/*******************************************************************************
15 * Definitions
16 ******************************************************************************/
17/* Component ID definition, used by tools. */
18#ifndef FSL_COMPONENT_ID
19#define FSL_COMPONENT_ID "platform.drivers.swm_connections"
20#endif
21
22/*!
23 * @addtogroup swm
24 * @{
25 */
26
27/*!
28 * @name swm connections
29 * @{
30 */
31
32/*! @brief SWM port_pin number */
33typedef enum _swm_port_pin_type_t
34{
35 kSWM_PortPin_P0_0 = 0U, /*!< port_pin number P0_0. */
36 kSWM_PortPin_P0_1 = 1U, /*!< port_pin number P0_1. */
37 kSWM_PortPin_P0_2 = 2U, /*!< port_pin number P0_2. */
38 kSWM_PortPin_P0_3 = 3U, /*!< port_pin number P0_3. */
39 kSWM_PortPin_P0_4 = 4U, /*!< port_pin number P0_4. */
40 kSWM_PortPin_P0_5 = 5U, /*!< port_pin number P0_5. */
41 kSWM_PortPin_P0_6 = 6U, /*!< port_pin number P0_6. */
42 kSWM_PortPin_P0_7 = 7U, /*!< port_pin number P0_7. */
43 kSWM_PortPin_P0_8 = 8U, /*!< port_pin number P0_8. */
44 kSWM_PortPin_P0_9 = 9U, /*!< port_pin number P0_9. */
45 kSWM_PortPin_P0_10 = 10U, /*!< port_pin number P0_10. */
46 kSWM_PortPin_P0_11 = 11U, /*!< port_pin number P0_11. */
47 kSWM_PortPin_P0_12 = 12U, /*!< port_pin number P0_12. */
48 kSWM_PortPin_P0_13 = 13U, /*!< port_pin number P0_13. */
49 kSWM_PortPin_P0_14 = 14U, /*!< port_pin number P0_14. */
50 kSWM_PortPin_P0_15 = 15U, /*!< port_pin number P0_15. */
51 kSWM_PortPin_P0_16 = 16U, /*!< port_pin number P0_16. */
52 kSWM_PortPin_P0_17 = 17U, /*!< port_pin number P0_17. */
53 kSWM_PortPin_Reset = 0xffU /*!< port_pin reset number. */
54} swm_port_pin_type_t;
55
56/*! @brief SWM movable selection */
57typedef enum _swm_select_movable_t
58{
59 kSWM_USART0_TXD = 0U, /*!< Movable function as USART0_TXD. */
60 kSWM_USART0_RXD = 1U, /*!< Movable function as USART0_RXD. */
61 kSWM_USART0_RTS = 2U, /*!< Movable function as USART0_RTS. */
62 kSWM_USART0_CTS = 3U, /*!< Movable function as USART0_CTS. */
63
64 kSWM_USART0_SCLK = 4U, /*!< Movable function as USART0_SCLK. */
65 kSWM_USART1_TXD = 5U, /*!< Movable function as USART1_TXD. */
66 kSWM_USART1_RXD = 6U, /*!< Movable function as USART1_RXD. */
67 kSWM_USART1_RTS = 7U, /*!< Movable function as USART1_RTS. */
68
69 kSWM_USART1_CTS = 8U, /*!< Movable function as USART1_CTS. */
70 kSWM_USART1_SCLK = 9U, /*!< Movable function as USART1_SCLK. */
71 kSWM_USART2_TXD = 10U, /*!< Movable function as USART2_TXD. */
72 kSWM_USART2_RXD = 11U, /*!< Movable function as USART2_RXD. */
73
74 kSWM_USART2_RTS = 12U, /*!< Movable function as USART2_RTS. */
75 kSWM_USART2_CTS = 13U, /*!< Movable function as USART2_CTS. */
76 kSWM_USART2_SCLK = 14U, /*!< Movable function as USART2_SCLK. */
77 kSWM_SPI0_SCK = 15U, /*!< Movable function as SPI0_SCK. */
78
79 kSWM_SPI0_MOSI = 16U, /*!< Movable function as SPI0_MOSI. */
80 kSWM_SPI0_MISO = 17U, /*!< Movable function as SPI0_MISO. */
81 kSWM_SPI0_SSEL = 18U, /*!< Movable function as SPI0_SSEL0. */
82 kSWM_SPI1_SCK = 19U, /*!< Movable function as SPI1_SCK. */
83
84 kSWM_SPI1_MOSI = 20U, /*!< Movable function as SPI1_MOSI. */
85 kSWM_SPI1_MISO = 21U, /*!< Movable function as SPI1_MISO. */
86 kSWM_SPI1_SSEL = 22U, /*!< Movable function as SPI1_SSEL0. */
87 kSWM_CTIN_0 = 23U, /*!< Movable function as CTIN_0. */
88
89 kSWM_CTIN_1 = 24U, /*!< Movable function as CTIN_1. */
90 kSWM_CTIN_2 = 25U, /*!< Movable function as CTIN_2. */
91 kSWM_CTIN_3 = 26U, /*!< Movable function as CTIN_3. */
92 kSWM_CTOUT_0 = 27U, /*!< Movable function as CTOUT_0. */
93
94 kSWM_CTOUT_1 = 28U, /*!< Movable function as CTOUT_1. */
95 kSWM_CTOUT_2 = 29U, /*!< Movable function as CTOUT_2. */
96 kSWM_CTOUT_3 = 30U, /*!< Movable function as CTOUT_3. */
97 kSWM_I2C_SDA = 31U, /*!< Movable function as I2C_SDA. */
98
99 kSWM_I2C_SCL = 32U, /*!< Movable function as I2C_SCL. */
100 kSWM_ACMP_OUT = 33U, /*!< Movable function as ACMP_OUT. */
101 kSWM_CLKOUT = 34U, /*!< Movable function as CLKOUT. */
102 kSWM_GPIO_INT_BMAT = 35U, /*!< Movable function as GPIO_INT_BMAT. */
103
104 kSWM_MOVABLE_NUM_FUNCS = 36U, /*!< Movable function number. */
105} swm_select_movable_t;
106
107/*! @brief SWM fixed pin selection */
108typedef enum _swm_select_fixed_pin_t
109{
110 kSWM_ACMP_INPUT1 = SWM_PINENABLE0_ACMP_I1_MASK, /*!< Fixed-pin function as ACMP_INPUT1. */
111 kSWM_ACMP_INPUT2 = SWM_PINENABLE0_ACMP_I2_MASK, /*!< Fixed-pin function as ACMP_INPUT2. */
112 kSWM_SWCLK = SWM_PINENABLE0_SWCLK_MASK, /*!< Fixed-pin function as SWCLK. */
113 kSWM_SWDIO = SWM_PINENABLE0_SWDIO_MASK, /*!< Fixed-pin function as SWDIO. */
114 kSWM_XTALIN = SWM_PINENABLE0_XTALIN_MASK, /*!< Fixed-pin function as XTALIN. */
115 kSWM_XTALOUT = SWM_PINENABLE0_XTALOUT_MASK, /*!< Fixed-pin function as XTALOUT. */
116 kSWM_RESETN = SWM_PINENABLE0_RESETN_MASK, /*!< Fixed-pin function as RESETN. */
117 kSWM_CLKIN = SWM_PINENABLE0_CLKIN_MASK, /*!< Fixed-pin function as CLKIN. */
118 kSWM_VDDCMP = SWM_PINENABLE0_VDDCMP_MASK, /*!< Fixed-pin function as VDDCMP. */
119
120 kSWM_FIXEDPIN_NUM_FUNCS = (int)0x80000101U, /*!< Fixed-pin function number. */
121} swm_select_fixed_pin_t;
122
123/*@}*/
124
125#endif /* _FSL_INPUTMUX_CONNECTIONS_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_syscon_connections.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_syscon_connections.h
new file mode 100644
index 000000000..e066585bf
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC811/drivers/fsl_syscon_connections.h
@@ -0,0 +1,62 @@
1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_SYSCON_CONNECTIONS_
10#define _FSL_SYSCON_CONNECTIONS_
11
12#include "fsl_common.h"
13
14/*******************************************************************************
15 * Definitions
16 ******************************************************************************/
17/* Component ID definition, used by tools. */
18#ifndef FSL_COMPONENT_ID
19#define FSL_COMPONENT_ID "platform.drivers.syscon_connections"
20#endif
21
22/*!
23 * @addtogroup syscon
24 * @{
25 */
26
27/*!
28 * @name Syscon multiplexing connections
29 * @{
30 */
31
32/*! @brief Periphinmux IDs */
33#define PINTSEL_ID 0x178U
34#define SYSCON_SHIFT 20U
35
36/*! @brief SYSCON connections type */
37typedef enum _syscon_connection_t
38{
39 /*!< Pin Interrupt. */
40 kSYSCON_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_ID << SYSCON_SHIFT),
41 kSYSCON_GpioPort0Pin1ToPintsel = 1U + (PINTSEL_ID << SYSCON_SHIFT),
42 kSYSCON_GpioPort0Pin2ToPintsel = 2U + (PINTSEL_ID << SYSCON_SHIFT),
43 kSYSCON_GpioPort0Pin3ToPintsel = 3U + (PINTSEL_ID << SYSCON_SHIFT),
44 kSYSCON_GpioPort0Pin4ToPintsel = 4U + (PINTSEL_ID << SYSCON_SHIFT),
45 kSYSCON_GpioPort0Pin5ToPintsel = 5U + (PINTSEL_ID << SYSCON_SHIFT),
46 kSYSCON_GpioPort0Pin6ToPintsel = 6U + (PINTSEL_ID << SYSCON_SHIFT),
47 kSYSCON_GpioPort0Pin7ToPintsel = 7U + (PINTSEL_ID << SYSCON_SHIFT),
48 kSYSCON_GpioPort0Pin8ToPintsel = 8U + (PINTSEL_ID << SYSCON_SHIFT),
49 kSYSCON_GpioPort0Pin9ToPintsel = 9U + (PINTSEL_ID << SYSCON_SHIFT),
50 kSYSCON_GpioPort0Pin10ToPintsel = 10U + (PINTSEL_ID << SYSCON_SHIFT),
51 kSYSCON_GpioPort0Pin11ToPintsel = 11U + (PINTSEL_ID << SYSCON_SHIFT),
52 kSYSCON_GpioPort0Pin12ToPintsel = 12U + (PINTSEL_ID << SYSCON_SHIFT),
53 kSYSCON_GpioPort0Pin13ToPintsel = 13U + (PINTSEL_ID << SYSCON_SHIFT),
54 kSYSCON_GpioPort0Pin14ToPintsel = 14U + (PINTSEL_ID << SYSCON_SHIFT),
55 kSYSCON_GpioPort0Pin15ToPintsel = 15U + (PINTSEL_ID << SYSCON_SHIFT),
56 kSYSCON_GpioPort0Pin16ToPintsel = 16U + (PINTSEL_ID << SYSCON_SHIFT),
57 kSYSCON_GpioPort0Pin17ToPintsel = 17U + (PINTSEL_ID << SYSCON_SHIFT),
58} syscon_connection_t;
59
60/*@}*/
61
62#endif /* _FSL_SYSCON_CONNECTIONS_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 20:26:09 +0100