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1/*
2** ###################################################################
3** Processors: LPC812M101JD20
4** LPC812M101JDH16
5** LPC812M101JDH20
6** LPC812M101JTB16
7**
8** Compilers: GNU C Compiler
9** IAR ANSI C/C++ Compiler for ARM
10** Keil ARM C/C++ Compiler
11** MCUXpresso Compiler
12**
13** Reference manual: LPC81x User manual Rev.1.6 2 April 2014
14** Version: rev. 1.2, 2017-06-08
15** Build: b200513
16**
17** Abstract:
18** CMSIS Peripheral Access Layer for LPC812
19**
20** Copyright 1997-2016 Freescale Semiconductor, Inc.
21** Copyright 2016-2020 NXP
22** All rights reserved.
23**
24** SPDX-License-Identifier: BSD-3-Clause
25**
26** http: www.nxp.com
27** mail: [email protected]
28**
29** Revisions:
30** - rev. 1.0 (2016-08-12)
31** Initial version.
32** - rev. 1.1 (2016-11-25)
33** Update CANFD and Classic CAN register.
34** Add MAC TIMERSTAMP registers.
35** - rev. 1.2 (2017-06-08)
36** Remove RTC_CTRL_RTC_OSC_BYPASS.
37** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
38** Remove RESET and HALT from SYSCON_AHBCLKDIV.
39**
40** ###################################################################
41*/
42
43/*!
44 * @file LPC812.h
45 * @version 1.2
46 * @date 2017-06-08
47 * @brief CMSIS Peripheral Access Layer for LPC812
48 *
49 * CMSIS Peripheral Access Layer for LPC812
50 */
51
52#ifndef _LPC812_H_
53#define _LPC812_H_ /**< Symbol preventing repeated inclusion */
54
55/** Memory map major version (memory maps with equal major version number are
56 * compatible) */
57#define MCU_MEM_MAP_VERSION 0x0100U
58/** Memory map minor version */
59#define MCU_MEM_MAP_VERSION_MINOR 0x0002U
60
61
62/* ----------------------------------------------------------------------------
63 -- Interrupt vector numbers
64 ---------------------------------------------------------------------------- */
65
66/*!
67 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
68 * @{
69 */
70
71/** Interrupt Number Definitions */
72#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
73
74typedef enum IRQn {
75 /* Auxiliary constants */
76 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
77
78 /* Core interrupts */
79 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
80 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
81 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
82 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
83 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
84
85 /* Device specific interrupts */
86 SPI0_IRQn = 0, /**< SPI0 interrupt */
87 SPI1_IRQn = 1, /**< SPI1 interrupt */
88 Reserved18_IRQn = 2, /**< Reserved interrupt */
89 USART0_IRQn = 3, /**< USART0 interrupt */
90 USART1_IRQn = 4, /**< USART1 interrupt */
91 USART2_IRQn = 5, /**< USART2 interrupt */
92 Reserved22_IRQn = 6, /**< Reserved interrupt */
93 Reserved23_IRQn = 7, /**< Reserved interrupt */
94 I2C0_IRQn = 8, /**< I2C0 interrupt */
95 SCT0_IRQn = 9, /**< State configurable timer interrupt */
96 MRT0_IRQn = 10, /**< Multi-rate timer interrupt */
97 CMP_IRQn = 11, /**< Analog comparator interrupt or Capacitive Touch interrupt */
98 WDT_IRQn = 12, /**< Windowed watchdog timer interrupt */
99 BOD_IRQn = 13, /**< BOD interrupts */
100 Reserved30_IRQn = 14, /**< Reserved interrupt */
101 WKT_IRQn = 15, /**< Self-wake-up timer interrupt */
102 Reserved32_IRQn = 16, /**< Reserved interrupt */
103 Reserved33_IRQn = 17, /**< Reserved interrupt */
104 Reserved34_IRQn = 18, /**< Reserved interrupt */
105 Reserved35_IRQn = 19, /**< Reserved interrupt */
106 Reserved36_IRQn = 20, /**< Reserved interrupt */
107 Reserved37_IRQn = 21, /**< Reserved interrupt */
108 Reserved38_IRQn = 22, /**< Reserved interrupt */
109 Reserved39_IRQn = 23, /**< Reserved interrupt */
110 PIN_INT0_IRQn = 24, /**< Pin interrupt 0 or pattern match engine slice 0 interrupt */
111 PIN_INT1_IRQn = 25, /**< Pin interrupt 1 or pattern match engine slice 1 interrupt */
112 PIN_INT2_IRQn = 26, /**< Pin interrupt 2 or pattern match engine slice 2 interrupt */
113 PIN_INT3_IRQn = 27, /**< Pin interrupt 3 or pattern match engine slice 3 interrupt */
114 PIN_INT4_IRQn = 28, /**< Pin interrupt 4 or pattern match engine slice 4 interrupt */
115 PIN_INT5_IRQn = 29, /**< Pin interrupt 5 or pattern match engine slice 5 interrupt */
116 PIN_INT6_IRQn = 30, /**< Pin interrupt 6 or pattern match engine slice 6 interrupt */
117 PIN_INT7_IRQn = 31 /**< Pin interrupt 7 or pattern match engine slice 7 interrupt */
118} IRQn_Type;
119
120/*!
121 * @}
122 */ /* end of group Interrupt_vector_numbers */
123
124
125/* ----------------------------------------------------------------------------
126 -- Cortex M0 Core Configuration
127 ---------------------------------------------------------------------------- */
128
129/*!
130 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
131 * @{
132 */
133
134#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
135#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
136#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */
137#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
138#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
139
140#include "core_cm0plus.h" /* Core Peripheral Access Layer */
141#include "system_LPC812.h" /* Device specific configuration file */
142
143/*!
144 * @}
145 */ /* end of group Cortex_Core_Configuration */
146
147
148/* ----------------------------------------------------------------------------
149 -- Device Peripheral Access Layer
150 ---------------------------------------------------------------------------- */
151
152/*!
153 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
154 * @{
155 */
156
157
158/*
159** Start of section using anonymous unions
160*/
161
162#if defined(__ARMCC_VERSION)
163 #if (__ARMCC_VERSION >= 6010050)
164 #pragma clang diagnostic push
165 #else
166 #pragma push
167 #pragma anon_unions
168 #endif
169#elif defined(__GNUC__)
170 /* anonymous unions are enabled by default */
171#elif defined(__IAR_SYSTEMS_ICC__)
172 #pragma language=extended
173#else
174 #error Not supported compiler type
175#endif
176
177/* ----------------------------------------------------------------------------
178 -- ACOMP Peripheral Access Layer
179 ---------------------------------------------------------------------------- */
180
181/*!
182 * @addtogroup ACOMP_Peripheral_Access_Layer ACOMP Peripheral Access Layer
183 * @{
184 */
185
186/** ACOMP - Register Layout Typedef */
187typedef struct {
188 __IO uint32_t CTRL; /**< Comparator control register, offset: 0x0 */
189 __IO uint32_t LAD; /**< Voltage ladder register, offset: 0x4 */
190} ACOMP_Type;
191
192/* ----------------------------------------------------------------------------
193 -- ACOMP Register Masks
194 ---------------------------------------------------------------------------- */
195
196/*!
197 * @addtogroup ACOMP_Register_Masks ACOMP Register Masks
198 * @{
199 */
200
201/*! @name CTRL - Comparator control register */
202/*! @{ */
203#define ACOMP_CTRL_EDGESEL_MASK (0x18U)
204#define ACOMP_CTRL_EDGESEL_SHIFT (3U)
205/*! EDGESEL - This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below):
206 * 0b00..Falling edges
207 * 0b01..Rising edges
208 * 0b10..Both edges
209 * 0b11..Both edges
210 */
211#define ACOMP_CTRL_EDGESEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_EDGESEL_SHIFT)) & ACOMP_CTRL_EDGESEL_MASK)
212#define ACOMP_CTRL_COMPSA_MASK (0x40U)
213#define ACOMP_CTRL_COMPSA_SHIFT (6U)
214/*! COMPSA - Comparator output control
215 * 0b0..Comparator output is used directly.
216 * 0b1..Comparator output is synchronized to the bus clock for output to other modules.
217 */
218#define ACOMP_CTRL_COMPSA(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPSA_SHIFT)) & ACOMP_CTRL_COMPSA_MASK)
219#define ACOMP_CTRL_COMP_VP_SEL_MASK (0x700U)
220#define ACOMP_CTRL_COMP_VP_SEL_SHIFT (8U)
221/*! COMP_VP_SEL - Selects positive voltage input
222 * 0b000..VOLTAGE_LADDER_OUTPUT
223 * 0b001..ACMP_I1
224 * 0b010..ACMP_I2
225 * 0b011..ACMP_I3
226 * 0b100..ACMP_I4
227 * 0b101..ACMP_I5
228 * 0b110..Band gap. Internal reference voltage.
229 * 0b111..DAC0 output
230 */
231#define ACOMP_CTRL_COMP_VP_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMP_VP_SEL_SHIFT)) & ACOMP_CTRL_COMP_VP_SEL_MASK)
232#define ACOMP_CTRL_COMP_VM_SEL_MASK (0x3800U)
233#define ACOMP_CTRL_COMP_VM_SEL_SHIFT (11U)
234/*! COMP_VM_SEL - Selects negative voltage input
235 * 0b000..VOLTAGE_LADDER_OUTPUT
236 * 0b001..ACMP_I1
237 * 0b010..ACMP_I2
238 * 0b011..ACMP_I3
239 * 0b100..ACMP_I4
240 * 0b101..ACMP_I5
241 * 0b110..Band gap. Internal reference voltage.
242 * 0b111..DAC0 output
243 */
244#define ACOMP_CTRL_COMP_VM_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMP_VM_SEL_SHIFT)) & ACOMP_CTRL_COMP_VM_SEL_MASK)
245#define ACOMP_CTRL_EDGECLR_MASK (0x100000U)
246#define ACOMP_CTRL_EDGECLR_SHIFT (20U)
247/*! EDGECLR - Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request,
248 * toggle the EDGECLR bit by first writing a 1 and then a 0.
249 */
250#define ACOMP_CTRL_EDGECLR(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_EDGECLR_SHIFT)) & ACOMP_CTRL_EDGECLR_MASK)
251#define ACOMP_CTRL_COMPSTAT_MASK (0x200000U)
252#define ACOMP_CTRL_COMPSTAT_SHIFT (21U)
253/*! COMPSTAT - Comparator status. This bit reflects the state of the comparator output.
254 */
255#define ACOMP_CTRL_COMPSTAT(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPSTAT_SHIFT)) & ACOMP_CTRL_COMPSTAT_MASK)
256#define ACOMP_CTRL_COMPEDGE_MASK (0x800000U)
257#define ACOMP_CTRL_COMPEDGE_SHIFT (23U)
258/*! COMPEDGE - Comparator edge-detect status.
259 */
260#define ACOMP_CTRL_COMPEDGE(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPEDGE_SHIFT)) & ACOMP_CTRL_COMPEDGE_MASK)
261#define ACOMP_CTRL_HYS_MASK (0x6000000U)
262#define ACOMP_CTRL_HYS_SHIFT (25U)
263/*! HYS - Controls the hysteresis of the comparator. When the comparator is outputting a certain
264 * state, this is the difference between the selected signals, in the opposite direction from the
265 * state being output, that will switch the output.
266 * 0b00..None (the output will switch as the voltages cross)
267 * 0b01..5 mv
268 * 0b10..10 mv
269 * 0b11..20 mv
270 */
271#define ACOMP_CTRL_HYS(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_HYS_SHIFT)) & ACOMP_CTRL_HYS_MASK)
272/*! @} */
273
274/*! @name LAD - Voltage ladder register */
275/*! @{ */
276#define ACOMP_LAD_LADEN_MASK (0x1U)
277#define ACOMP_LAD_LADEN_SHIFT (0U)
278/*! LADEN - Voltage ladder enable
279 */
280#define ACOMP_LAD_LADEN(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADEN_SHIFT)) & ACOMP_LAD_LADEN_MASK)
281#define ACOMP_LAD_LADSEL_MASK (0x3EU)
282#define ACOMP_LAD_LADSEL_SHIFT (1U)
283/*! LADSEL - Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000
284 * = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref
285 */
286#define ACOMP_LAD_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADSEL_SHIFT)) & ACOMP_LAD_LADSEL_MASK)
287#define ACOMP_LAD_LADREF_MASK (0x40U)
288#define ACOMP_LAD_LADREF_SHIFT (6U)
289/*! LADREF - Selects the reference voltage Vref for the voltage ladder.
290 * 0b0..Supply pin VDD
291 * 0b1..VDDCMP pin
292 */
293#define ACOMP_LAD_LADREF(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADREF_SHIFT)) & ACOMP_LAD_LADREF_MASK)
294/*! @} */
295
296
297/*!
298 * @}
299 */ /* end of group ACOMP_Register_Masks */
300
301
302/* ACOMP - Peripheral instance base addresses */
303/** Peripheral ACOMP base address */
304#define ACOMP_BASE (0x40024000u)
305/** Peripheral ACOMP base pointer */
306#define ACOMP ((ACOMP_Type *)ACOMP_BASE)
307/** Array initializer of ACOMP peripheral base addresses */
308#define ACOMP_BASE_ADDRS { ACOMP_BASE }
309/** Array initializer of ACOMP peripheral base pointers */
310#define ACOMP_BASE_PTRS { ACOMP }
311
312/*!
313 * @}
314 */ /* end of group ACOMP_Peripheral_Access_Layer */
315
316
317/* ----------------------------------------------------------------------------
318 -- CRC Peripheral Access Layer
319 ---------------------------------------------------------------------------- */
320
321/*!
322 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
323 * @{
324 */
325
326/** CRC - Register Layout Typedef */
327typedef struct {
328 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
329 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
330 union { /* offset: 0x8 */
331 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
332 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
333 };
334} CRC_Type;
335
336/* ----------------------------------------------------------------------------
337 -- CRC Register Masks
338 ---------------------------------------------------------------------------- */
339
340/*!
341 * @addtogroup CRC_Register_Masks CRC Register Masks
342 * @{
343 */
344
345/*! @name MODE - CRC mode register */
346/*! @{ */
347#define CRC_MODE_CRC_POLY_MASK (0x3U)
348#define CRC_MODE_CRC_POLY_SHIFT (0U)
349/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
350 */
351#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
352#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
353#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
354/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
355 */
356#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
357#define CRC_MODE_CMPL_WR_MASK (0x8U)
358#define CRC_MODE_CMPL_WR_SHIFT (3U)
359/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
360 */
361#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
362#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
363#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
364/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
365 */
366#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
367#define CRC_MODE_CMPL_SUM_MASK (0x20U)
368#define CRC_MODE_CMPL_SUM_SHIFT (5U)
369/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
370 */
371#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
372/*! @} */
373
374/*! @name SEED - CRC seed register */
375/*! @{ */
376#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
377#define CRC_SEED_CRC_SEED_SHIFT (0U)
378/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
379 * selected bit order and 1's complement pre-processes. A write access to this register will
380 * overrule the CRC calculation in progresses.
381 */
382#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
383/*! @} */
384
385/*! @name SUM - CRC checksum register */
386/*! @{ */
387#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
388#define CRC_SUM_CRC_SUM_SHIFT (0U)
389/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
390 */
391#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
392/*! @} */
393
394/*! @name WR_DATA - CRC data register */
395/*! @{ */
396#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
397#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
398/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
399 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
400 * accept back-to-back transactions.
401 */
402#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
403/*! @} */
404
405
406/*!
407 * @}
408 */ /* end of group CRC_Register_Masks */
409
410
411/* CRC - Peripheral instance base addresses */
412/** Peripheral CRC base address */
413#define CRC_BASE (0x50000000u)
414/** Peripheral CRC base pointer */
415#define CRC ((CRC_Type *)CRC_BASE)
416/** Array initializer of CRC peripheral base addresses */
417#define CRC_BASE_ADDRS { CRC_BASE }
418/** Array initializer of CRC peripheral base pointers */
419#define CRC_BASE_PTRS { CRC }
420
421/*!
422 * @}
423 */ /* end of group CRC_Peripheral_Access_Layer */
424
425
426/* ----------------------------------------------------------------------------
427 -- FLASH_CTRL Peripheral Access Layer
428 ---------------------------------------------------------------------------- */
429
430/*!
431 * @addtogroup FLASH_CTRL_Peripheral_Access_Layer FLASH_CTRL Peripheral Access Layer
432 * @{
433 */
434
435/** FLASH_CTRL - Register Layout Typedef */
436typedef struct {
437 uint8_t RESERVED_0[16];
438 __IO uint32_t FLASHCFG; /**< Flash configuration register, offset: 0x10 */
439 uint8_t RESERVED_1[12];
440 __IO uint32_t FMSSTART; /**< Flash signature start address register, offset: 0x20 */
441 __IO uint32_t FMSSTOP; /**< Flash signaure stop address register, offset: 0x24 */
442 uint8_t RESERVED_2[4];
443 __I uint32_t FMSW0; /**< Flash signature generation result register returns the flash signature produced by the embedded signature generator.., offset: 0x2C */
444} FLASH_CTRL_Type;
445
446/* ----------------------------------------------------------------------------
447 -- FLASH_CTRL Register Masks
448 ---------------------------------------------------------------------------- */
449
450/*!
451 * @addtogroup FLASH_CTRL_Register_Masks FLASH_CTRL Register Masks
452 * @{
453 */
454
455/*! @name FLASHCFG - Flash configuration register */
456/*! @{ */
457#define FLASH_CTRL_FLASHCFG_FLASHTIM_MASK (0x3U)
458#define FLASH_CTRL_FLASHCFG_FLASHTIM_SHIFT (0U)
459/*! FLASHTIM - Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
460 * 0b00..1 system clock flash access time.
461 * 0b01..2 system clock flash access time.
462 * 0b10..3 system clock flash access time.
463 * 0b11..Reserved.
464 */
465#define FLASH_CTRL_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FLASHCFG_FLASHTIM_SHIFT)) & FLASH_CTRL_FLASHCFG_FLASHTIM_MASK)
466/*! @} */
467
468/*! @name FMSSTART - Flash signature start address register */
469/*! @{ */
470#define FLASH_CTRL_FMSSTART_START_MASK (0x1FFFFU)
471#define FLASH_CTRL_FMSSTART_START_SHIFT (0U)
472/*! START - Signature generation start address (corresponds to AHB byte address bits[18:2]).
473 */
474#define FLASH_CTRL_FMSSTART_START(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTART_START_SHIFT)) & FLASH_CTRL_FMSSTART_START_MASK)
475/*! @} */
476
477/*! @name FMSSTOP - Flash signaure stop address register */
478/*! @{ */
479#define FLASH_CTRL_FMSSTOP_STOPA_MASK (0x1FFFFU)
480#define FLASH_CTRL_FMSSTOP_STOPA_SHIFT (0U)
481/*! STOPA - Stop address for signature generation (the word specified by STOP is included in the
482 * address range). The address is in units of memory words, not bytes.
483 */
484#define FLASH_CTRL_FMSSTOP_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTOP_STOPA_SHIFT)) & FLASH_CTRL_FMSSTOP_STOPA_MASK)
485#define FLASH_CTRL_FMSSTOP_STRTBIST_MASK (0x80000000U)
486#define FLASH_CTRL_FMSSTOP_STRTBIST_SHIFT (31U)
487/*! STRTBIST - When this bit is written to 1, signature generation starts. At the end of signature
488 * generation, this bit is automatically cleared.
489 */
490#define FLASH_CTRL_FMSSTOP_STRTBIST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTOP_STRTBIST_SHIFT)) & FLASH_CTRL_FMSSTOP_STRTBIST_MASK)
491/*! @} */
492
493/*! @name FMSW0 - Flash signature generation result register returns the flash signature produced by the embedded signature generator.. */
494/*! @{ */
495#define FLASH_CTRL_FMSW0_SIG_MASK (0xFFFFFFFFU)
496#define FLASH_CTRL_FMSW0_SIG_SHIFT (0U)
497/*! SIG - 32-bit signature.
498 */
499#define FLASH_CTRL_FMSW0_SIG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSW0_SIG_SHIFT)) & FLASH_CTRL_FMSW0_SIG_MASK)
500/*! @} */
501
502
503/*!
504 * @}
505 */ /* end of group FLASH_CTRL_Register_Masks */
506
507
508/* FLASH_CTRL - Peripheral instance base addresses */
509/** Peripheral FLASH_CTRL base address */
510#define FLASH_CTRL_BASE (0x40040000u)
511/** Peripheral FLASH_CTRL base pointer */
512#define FLASH_CTRL ((FLASH_CTRL_Type *)FLASH_CTRL_BASE)
513/** Array initializer of FLASH_CTRL peripheral base addresses */
514#define FLASH_CTRL_BASE_ADDRS { FLASH_CTRL_BASE }
515/** Array initializer of FLASH_CTRL peripheral base pointers */
516#define FLASH_CTRL_BASE_PTRS { FLASH_CTRL }
517
518/*!
519 * @}
520 */ /* end of group FLASH_CTRL_Peripheral_Access_Layer */
521
522
523/* ----------------------------------------------------------------------------
524 -- GPIO Peripheral Access Layer
525 ---------------------------------------------------------------------------- */
526
527/*!
528 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
529 * @{
530 */
531
532/** GPIO - Register Layout Typedef */
533typedef struct {
534 __IO uint8_t B[1][18]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x12, index2*0x1 */
535 uint8_t RESERVED_0[4078];
536 __IO uint32_t W[1][18]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x48, index2*0x4 */
537 uint8_t RESERVED_1[4024];
538 __IO uint32_t DIR[1]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */
539 uint8_t RESERVED_2[124];
540 __IO uint32_t MASK[1]; /**< Mask register, array offset: 0x2080, array step: 0x4 */
541 uint8_t RESERVED_3[124];
542 __IO uint32_t PIN[1]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */
543 uint8_t RESERVED_4[124];
544 __IO uint32_t MPIN[1]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */
545 uint8_t RESERVED_5[124];
546 __IO uint32_t SET[1]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
547 uint8_t RESERVED_6[124];
548 __O uint32_t CLR[1]; /**< Clear port, array offset: 0x2280, array step: 0x4 */
549 uint8_t RESERVED_7[124];
550 __O uint32_t NOT[1]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */
551} GPIO_Type;
552
553/* ----------------------------------------------------------------------------
554 -- GPIO Register Masks
555 ---------------------------------------------------------------------------- */
556
557/*!
558 * @addtogroup GPIO_Register_Masks GPIO Register Masks
559 * @{
560 */
561
562/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
563/*! @{ */
564#define GPIO_B_PBYTE_MASK (0x1U)
565#define GPIO_B_PBYTE_SHIFT (0U)
566/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function,
567 * except that pins configured as analog I/O always read as 0. One register for each port pin.
568 * Supported pins depends on the specific device and package. Write: loads the pin's output bit.
569 * One register for each port pin. Supported pins depends on the specific device and package.
570 */
571#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
572/*! @} */
573
574/* The count of GPIO_B */
575#define GPIO_B_COUNT (1U)
576
577/* The count of GPIO_B */
578#define GPIO_B_COUNT2 (18U)
579
580/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
581/*! @{ */
582#define GPIO_W_PWORD_MASK (0xFFFFFFFFU)
583#define GPIO_W_PWORD_SHIFT (0U)
584/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is
585 * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be
586 * read. Writing any value other than 0 will set the output bit. One register for each port pin.
587 * Supported pins depends on the specific device and package.
588 */
589#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
590/*! @} */
591
592/* The count of GPIO_W */
593#define GPIO_W_COUNT (1U)
594
595/* The count of GPIO_W */
596#define GPIO_W_COUNT2 (18U)
597
598/*! @name DIR - Direction registers */
599/*! @{ */
600#define GPIO_DIR_DIRP_MASK (0x3FFFFU)
601#define GPIO_DIR_DIRP_SHIFT (0U)
602/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
603 * pins depends on the specific device and package. 0 = input. 1 = output.
604 */
605#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
606/*! @} */
607
608/* The count of GPIO_DIR */
609#define GPIO_DIR_COUNT (1U)
610
611/*! @name MASK - Mask register */
612/*! @{ */
613#define GPIO_MASK_MASKP_MASK (0x3FFFFU)
614#define GPIO_MASK_MASKP_SHIFT (0U)
615/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 =
616 * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 =
617 * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit
618 * not affected.
619 */
620#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
621/*! @} */
622
623/* The count of GPIO_MASK */
624#define GPIO_MASK_COUNT (1U)
625
626/*! @name PIN - Port pin register */
627/*! @{ */
628#define GPIO_PIN_PORT_MASK (0x3FFFFU)
629#define GPIO_PIN_PORT_SHIFT (0U)
630/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
631 * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit.
632 * 1 = Read: pin is high; write: set output bit.
633 */
634#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
635/*! @} */
636
637/* The count of GPIO_PIN */
638#define GPIO_PIN_COUNT (1U)
639
640/*! @name MPIN - Masked port register */
641/*! @{ */
642#define GPIO_MPIN_MPORTP_MASK (0x3FFFFU)
643#define GPIO_MPIN_MPORTP_SHIFT (0U)
644/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
645 * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK
646 * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1
647 * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit
648 * if the corresponding bit in the MASK register is 0.
649 */
650#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
651/*! @} */
652
653/* The count of GPIO_MPIN */
654#define GPIO_MPIN_COUNT (1U)
655
656/*! @name SET - Write: Set register for port Read: output bits for port */
657/*! @{ */
658#define GPIO_SET_SETP_MASK (0x3FFFFU)
659#define GPIO_SET_SETP_SHIFT (0U)
660/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
661 * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output
662 * bit; write: set output bit.
663 */
664#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
665/*! @} */
666
667/* The count of GPIO_SET */
668#define GPIO_SET_COUNT (1U)
669
670/*! @name CLR - Clear port */
671/*! @{ */
672#define GPIO_CLR_CLRP_MASK (0x3FFFFU)
673#define GPIO_CLR_CLRP_SHIFT (0U)
674/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
675 * specific device and package. 0 = No operation. 1 = Clear output bit.
676 */
677#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
678/*! @} */
679
680/* The count of GPIO_CLR */
681#define GPIO_CLR_COUNT (1U)
682
683/*! @name NOT - Toggle port */
684/*! @{ */
685#define GPIO_NOT_NOTP_MASK (0x3FFFFU)
686#define GPIO_NOT_NOTP_SHIFT (0U)
687/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
688 * specific device and package. 0 = no operation. 1 = Toggle output bit.
689 */
690#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
691/*! @} */
692
693/* The count of GPIO_NOT */
694#define GPIO_NOT_COUNT (1U)
695
696
697/*!
698 * @}
699 */ /* end of group GPIO_Register_Masks */
700
701
702/* GPIO - Peripheral instance base addresses */
703/** Peripheral GPIO base address */
704#define GPIO_BASE (0xA0000000u)
705/** Peripheral GPIO base pointer */
706#define GPIO ((GPIO_Type *)GPIO_BASE)
707/** Array initializer of GPIO peripheral base addresses */
708#define GPIO_BASE_ADDRS { GPIO_BASE }
709/** Array initializer of GPIO peripheral base pointers */
710#define GPIO_BASE_PTRS { GPIO }
711
712/*!
713 * @}
714 */ /* end of group GPIO_Peripheral_Access_Layer */
715
716
717/* ----------------------------------------------------------------------------
718 -- I2C Peripheral Access Layer
719 ---------------------------------------------------------------------------- */
720
721/*!
722 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
723 * @{
724 */
725
726/** I2C - Register Layout Typedef */
727typedef struct {
728 __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x0 */
729 __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x4 */
730 __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x8 */
731 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0xC */
732 __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x10 */
733 __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x14 */
734 __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x18 */
735 uint8_t RESERVED_0[4];
736 __IO uint32_t MSTCTL; /**< Master control register., offset: 0x20 */
737 __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x24 */
738 __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x28 */
739 uint8_t RESERVED_1[20];
740 __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x40 */
741 __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x44 */
742 __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x48, array step: 0x4 */
743 __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x58 */
744 uint8_t RESERVED_2[36];
745 __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x80 */
746} I2C_Type;
747
748/* ----------------------------------------------------------------------------
749 -- I2C Register Masks
750 ---------------------------------------------------------------------------- */
751
752/*!
753 * @addtogroup I2C_Register_Masks I2C Register Masks
754 * @{
755 */
756
757/*! @name CFG - Configuration for shared functions. */
758/*! @{ */
759#define I2C_CFG_MSTEN_MASK (0x1U)
760#define I2C_CFG_MSTEN_SHIFT (0U)
761/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not
762 * changed, but the Master function is internally reset.
763 * 0b0..Disabled. The I2C Master function is disabled.
764 * 0b1..Enabled. The I2C Master function is enabled.
765 */
766#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
767#define I2C_CFG_SLVEN_MASK (0x2U)
768#define I2C_CFG_SLVEN_SHIFT (1U)
769/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not
770 * changed, but the Slave function is internally reset.
771 * 0b0..Disabled. The I2C slave function is disabled.
772 * 0b1..Enabled. The I2C slave function is enabled.
773 */
774#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
775#define I2C_CFG_MONEN_MASK (0x4U)
776#define I2C_CFG_MONEN_SHIFT (2U)
777/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not
778 * changed, but the Monitor function is internally reset.
779 * 0b0..Disabled. The I2C Monitor function is disabled.
780 * 0b1..Enabled. The I2C Monitor function is enabled.
781 */
782#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
783#define I2C_CFG_TIMEOUTEN_MASK (0x8U)
784#define I2C_CFG_TIMEOUTEN_SHIFT (3U)
785/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
786 * 0b0..Disabled. Time-out function is disabled.
787 * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause
788 * interrupts if they are enabled. Typically, only one time-out will be used in a system.
789 */
790#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
791#define I2C_CFG_MONCLKSTR_MASK (0x10U)
792#define I2C_CFG_MONCLKSTR_SHIFT (4U)
793/*! MONCLKSTR - Monitor function Clock Stretching.
794 * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able
795 * to read data provided by the Monitor function before it is overwritten. This mode may be used when
796 * non-invasive monitoring is critical.
797 * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can
798 * read all incoming data supplied by the Monitor function.
799 */
800#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
801/*! @} */
802
803/*! @name STAT - Status register for Master, Slave, and Monitor functions. */
804/*! @{ */
805#define I2C_STAT_MSTPENDING_MASK (0x1U)
806#define I2C_STAT_MSTPENDING_SHIFT (0U)
807/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on
808 * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what
809 * type of software service if any the master expects. This flag will cause an interrupt when set
810 * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling
811 * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle
812 * state, and no communication is needed, mask this interrupt.
813 * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
814 * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the
815 * idle state, it is waiting to receive or transmit data or the NACK bit.
816 */
817#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
818#define I2C_STAT_MSTSTATE_MASK (0xEU)
819#define I2C_STAT_MSTSTATE_SHIFT (1U)
820/*! MSTSTATE - Master State code. The master state code reflects the master state when the
821 * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field
822 * indicates a specific required service for the Master function. All other values are reserved. See
823 * Table 400 for details of state values and appropriate responses.
824 * 0b000..Idle. The Master function is available to be used for a new transaction.
825 * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
826 * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
827 * 0b011..NACK Address. Slave NACKed address.
828 * 0b100..NACK Data. Slave NACKed transmitted data.
829 */
830#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
831#define I2C_STAT_MSTARBLOSS_MASK (0x10U)
832#define I2C_STAT_MSTARBLOSS_SHIFT (4U)
833/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to
834 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
835 * 0b0..No Arbitration Loss has occurred.
836 * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master
837 * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing,
838 * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
839 */
840#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
841#define I2C_STAT_MSTSTSTPERR_MASK (0x40U)
842#define I2C_STAT_MSTSTSTPERR_SHIFT (6U)
843/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to
844 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
845 * 0b0..No Start/Stop Error has occurred.
846 * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is
847 * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an
848 * idle state, no action is required. A request for a Start could be made, or software could attempt to insure
849 * that the bus has not stalled.
850 */
851#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
852#define I2C_STAT_SLVPENDING_MASK (0x100U)
853#define I2C_STAT_SLVPENDING_SHIFT (8U)
854/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue
855 * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if
856 * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the
857 * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is
858 * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time
859 * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section
860 * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are
861 * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must
862 * also be detected automatically, since the address must be acknowledged before the clock can be
863 * stretched.
864 * 0b0..In progress. The Slave function does not currently need service.
865 * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
866 */
867#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
868#define I2C_STAT_SLVSTATE_MASK (0x600U)
869#define I2C_STAT_SLVSTATE_SHIFT (9U)
870/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for
871 * the Slave function. All other values are reserved. See Table 401 for state values and actions.
872 * note that the occurrence of some states and how they are handled are affected by DMA mode and
873 * Automatic Operation modes.
874 * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
875 * 0b01..Slave receive. Received data is available (Slave Receiver mode).
876 * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode).
877 */
878#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
879#define I2C_STAT_SLVNOTSTR_MASK (0x800U)
880#define I2C_STAT_SLVNOTSTR_SHIFT (11U)
881/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock.
882 * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave
883 * operation. This read-only flag reflects the slave function status in real time.
884 * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
885 * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or
886 * Power-down mode could be entered at this time.
887 */
888#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
889#define I2C_STAT_SLVIDX_MASK (0x3000U)
890#define I2C_STAT_SLVIDX_SHIFT (12U)
891/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been
892 * selected by receiving an address that matches one of the slave addresses defined by any enabled
893 * slave address registers, and provides an identification of the address that was matched. It is
894 * possible that more than one address could be matched, but only one match can be reported here.
895 * 0b00..Address 0. Slave address 0 was matched.
896 * 0b01..Address 1. Slave address 1 was matched.
897 * 0b10..Address 2. Slave address 2 was matched.
898 * 0b11..Address 3. Slave address 3 was matched.
899 */
900#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
901#define I2C_STAT_SLVSEL_MASK (0x4000U)
902#define I2C_STAT_SLVSEL_SHIFT (14U)
903/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave
904 * function to acknowledge the address, or when the address has been automatically acknowledged.
905 * It is cleared when another address cycle presents an address that does not match an enabled
906 * address on the Slave function, when slave software decides to NACK a matched address, when
907 * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of
908 * Automatic Operation. SLVSEL is not cleared if software NACKs data.
909 * 0b0..Not selected. The Slave function is not currently selected.
910 * 0b1..Selected. The Slave function is currently selected.
911 */
912#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
913#define I2C_STAT_SLVDESEL_MASK (0x8000U)
914#define I2C_STAT_SLVDESEL_SHIFT (15U)
915/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via
916 * INTENSET. This flag can be cleared by writing a 1 to this bit.
917 * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently
918 * selected. That information can be found in the SLVSEL flag.
919 * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag
920 * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
921 */
922#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
923#define I2C_STAT_MONRDY_MASK (0x10000U)
924#define I2C_STAT_MONRDY_SHIFT (16U)
925/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read.
926 * 0b0..No data. The Monitor function does not currently have data available.
927 * 0b1..Data waiting. The Monitor function has data waiting to be read.
928 */
929#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
930#define I2C_STAT_MONOV_MASK (0x20000U)
931#define I2C_STAT_MONOV_SHIFT (17U)
932/*! MONOV - Monitor Overflow flag.
933 * 0b0..No overrun. Monitor data has not overrun.
934 * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not
935 * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
936 */
937#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
938#define I2C_STAT_MONACTIVE_MASK (0x40000U)
939#define I2C_STAT_MONACTIVE_SHIFT (18U)
940/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to
941 * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred
942 * more recently than a bus Stop.
943 * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive.
944 * 0b1..Active. The Monitor function considers the I2C bus to be active.
945 */
946#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
947#define I2C_STAT_MONIDLE_MASK (0x80000U)
948#define I2C_STAT_MONIDLE_SHIFT (19U)
949/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change
950 * from active to inactive. This can be used by software to decide when to process data
951 * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the
952 * INTENSET register. The flag can be cleared by writing a 1 to this bit.
953 * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software.
954 * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
955 */
956#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
957#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U)
958#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U)
959/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been
960 * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock
961 * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus
962 * is idle.
963 * 0b0..No time-out. I2C bus events have not caused a time-out.
964 * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
965 */
966#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
967#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U)
968#define I2C_STAT_SCLTIMEOUT_SHIFT (25U)
969/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the
970 * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
971 * 0b0..No time-out. SCL low time has not caused a time-out.
972 * 0b1..Time-out. SCL low time has caused a time-out.
973 */
974#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
975/*! @} */
976
977/*! @name INTENSET - Interrupt Enable Set and read register. */
978/*! @{ */
979#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U)
980#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U)
981/*! MSTPENDINGEN - Master Pending interrupt Enable.
982 * 0b0..Disabled. The MstPending interrupt is disabled.
983 * 0b1..Enabled. The MstPending interrupt is enabled.
984 */
985#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
986#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U)
987#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U)
988/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable.
989 * 0b0..Disabled. The MstArbLoss interrupt is disabled.
990 * 0b1..Enabled. The MstArbLoss interrupt is enabled.
991 */
992#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
993#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U)
994#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U)
995/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable.
996 * 0b0..Disabled. The MstStStpErr interrupt is disabled.
997 * 0b1..Enabled. The MstStStpErr interrupt is enabled.
998 */
999#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
1000#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U)
1001#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U)
1002/*! SLVPENDINGEN - Slave Pending interrupt Enable.
1003 * 0b0..Disabled. The SlvPending interrupt is disabled.
1004 * 0b1..Enabled. The SlvPending interrupt is enabled.
1005 */
1006#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
1007#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U)
1008#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U)
1009/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable.
1010 * 0b0..Disabled. The SlvNotStr interrupt is disabled.
1011 * 0b1..Enabled. The SlvNotStr interrupt is enabled.
1012 */
1013#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
1014#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U)
1015#define I2C_INTENSET_SLVDESELEN_SHIFT (15U)
1016/*! SLVDESELEN - Slave Deselect interrupt Enable.
1017 * 0b0..Disabled. The SlvDeSel interrupt is disabled.
1018 * 0b1..Enabled. The SlvDeSel interrupt is enabled.
1019 */
1020#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
1021#define I2C_INTENSET_MONRDYEN_MASK (0x10000U)
1022#define I2C_INTENSET_MONRDYEN_SHIFT (16U)
1023/*! MONRDYEN - Monitor data Ready interrupt Enable.
1024 * 0b0..Disabled. The MonRdy interrupt is disabled.
1025 * 0b1..Enabled. The MonRdy interrupt is enabled.
1026 */
1027#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
1028#define I2C_INTENSET_MONOVEN_MASK (0x20000U)
1029#define I2C_INTENSET_MONOVEN_SHIFT (17U)
1030/*! MONOVEN - Monitor Overrun interrupt Enable.
1031 * 0b0..Disabled. The MonOv interrupt is disabled.
1032 * 0b1..Enabled. The MonOv interrupt is enabled.
1033 */
1034#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
1035#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U)
1036#define I2C_INTENSET_MONIDLEEN_SHIFT (19U)
1037/*! MONIDLEEN - Monitor Idle interrupt Enable.
1038 * 0b0..Disabled. The MonIdle interrupt is disabled.
1039 * 0b1..Enabled. The MonIdle interrupt is enabled.
1040 */
1041#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
1042#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U)
1043#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U)
1044/*! EVENTTIMEOUTEN - Event time-out interrupt Enable.
1045 * 0b0..Disabled. The Event time-out interrupt is disabled.
1046 * 0b1..Enabled. The Event time-out interrupt is enabled.
1047 */
1048#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
1049#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U)
1050#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U)
1051/*! SCLTIMEOUTEN - SCL time-out interrupt Enable.
1052 * 0b0..Disabled. The SCL time-out interrupt is disabled.
1053 * 0b1..Enabled. The SCL time-out interrupt is enabled.
1054 */
1055#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
1056/*! @} */
1057
1058/*! @name INTENCLR - Interrupt Enable Clear register. */
1059/*! @{ */
1060#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U)
1061#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U)
1062/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding
1063 * bit in the INTENSET register if implemented.
1064 */
1065#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
1066#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U)
1067#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U)
1068/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear.
1069 */
1070#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
1071#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U)
1072#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U)
1073/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear.
1074 */
1075#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
1076#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U)
1077#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U)
1078/*! SLVPENDINGCLR - Slave Pending interrupt clear.
1079 */
1080#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
1081#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U)
1082#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U)
1083/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear.
1084 */
1085#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
1086#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U)
1087#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U)
1088/*! SLVDESELCLR - Slave Deselect interrupt clear.
1089 */
1090#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
1091#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U)
1092#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U)
1093/*! MONRDYCLR - Monitor data Ready interrupt clear.
1094 */
1095#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
1096#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U)
1097#define I2C_INTENCLR_MONOVCLR_SHIFT (17U)
1098/*! MONOVCLR - Monitor Overrun interrupt clear.
1099 */
1100#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
1101#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U)
1102#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U)
1103/*! MONIDLECLR - Monitor Idle interrupt clear.
1104 */
1105#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
1106#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U)
1107#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U)
1108/*! EVENTTIMEOUTCLR - Event time-out interrupt clear.
1109 */
1110#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
1111#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U)
1112#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U)
1113/*! SCLTIMEOUTCLR - SCL time-out interrupt clear.
1114 */
1115#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
1116/*! @} */
1117
1118/*! @name TIMEOUT - Time-out value register. */
1119/*! @{ */
1120#define I2C_TIMEOUT_TOMIN_MASK (0xFU)
1121#define I2C_TIMEOUT_TOMIN_SHIFT (0U)
1122/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum
1123 * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
1124 */
1125#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
1126#define I2C_TIMEOUT_TO_MASK (0xFFF0U)
1127#define I2C_TIMEOUT_TO_SHIFT (4U)
1128/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C
1129 * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation,
1130 * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A
1131 * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after
1132 * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the
1133 * I2C function clock.
1134 */
1135#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
1136/*! @} */
1137
1138/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */
1139/*! @{ */
1140#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU)
1141#define I2C_CLKDIV_DIVVAL_SHIFT (0U)
1142/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that
1143 * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 =
1144 * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is
1145 * divided by 65,536 before use.
1146 */
1147#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
1148/*! @} */
1149
1150/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
1151/*! @{ */
1152#define I2C_INTSTAT_MSTPENDING_MASK (0x1U)
1153#define I2C_INTSTAT_MSTPENDING_SHIFT (0U)
1154/*! MSTPENDING - Master Pending.
1155 */
1156#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
1157#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U)
1158#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U)
1159/*! MSTARBLOSS - Master Arbitration Loss flag.
1160 */
1161#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
1162#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U)
1163#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U)
1164/*! MSTSTSTPERR - Master Start/Stop Error flag.
1165 */
1166#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
1167#define I2C_INTSTAT_SLVPENDING_MASK (0x100U)
1168#define I2C_INTSTAT_SLVPENDING_SHIFT (8U)
1169/*! SLVPENDING - Slave Pending.
1170 */
1171#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
1172#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U)
1173#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U)
1174/*! SLVNOTSTR - Slave Not Stretching status.
1175 */
1176#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
1177#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U)
1178#define I2C_INTSTAT_SLVDESEL_SHIFT (15U)
1179/*! SLVDESEL - Slave Deselected flag.
1180 */
1181#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
1182#define I2C_INTSTAT_MONRDY_MASK (0x10000U)
1183#define I2C_INTSTAT_MONRDY_SHIFT (16U)
1184/*! MONRDY - Monitor Ready.
1185 */
1186#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
1187#define I2C_INTSTAT_MONOV_MASK (0x20000U)
1188#define I2C_INTSTAT_MONOV_SHIFT (17U)
1189/*! MONOV - Monitor Overflow flag.
1190 */
1191#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
1192#define I2C_INTSTAT_MONIDLE_MASK (0x80000U)
1193#define I2C_INTSTAT_MONIDLE_SHIFT (19U)
1194/*! MONIDLE - Monitor Idle flag.
1195 */
1196#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
1197#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U)
1198#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U)
1199/*! EVENTTIMEOUT - Event time-out Interrupt flag.
1200 */
1201#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
1202#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U)
1203#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U)
1204/*! SCLTIMEOUT - SCL time-out Interrupt flag.
1205 */
1206#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
1207/*! @} */
1208
1209/*! @name MSTCTL - Master control register. */
1210/*! @{ */
1211#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U)
1212#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U)
1213/*! MSTCONTINUE - Master Continue.
1214 * 0b0..No effect.
1215 * 0b1..Informs the Master function to continue to the next operation.
1216 */
1217#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
1218#define I2C_MSTCTL_MSTSTART_MASK (0x2U)
1219#define I2C_MSTCTL_MSTSTART_SHIFT (1U)
1220/*! MSTSTART - Master Start control.
1221 * 0b0..No effect.
1222 * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time.
1223 */
1224#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
1225#define I2C_MSTCTL_MSTSTOP_MASK (0x4U)
1226#define I2C_MSTCTL_MSTSTOP_SHIFT (2U)
1227/*! MSTSTOP - Master Stop control.
1228 * 0b0..No effect.
1229 * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave
1230 * if the master is receiving data from the slave (Master Receiver mode).
1231 */
1232#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
1233/*! @} */
1234
1235/*! @name MSTTIME - Master timing configuration. */
1236/*! @{ */
1237#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U)
1238#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U)
1239/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this
1240 * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This
1241 * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters
1242 * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.
1243 * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
1244 * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
1245 * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
1246 * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
1247 * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
1248 * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
1249 * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
1250 * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
1251 */
1252#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
1253#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U)
1254#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U)
1255/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this
1256 * master on SCL. Other masters in a multi-master system could shorten this time. This
1257 * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters
1258 * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.
1259 * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
1260 * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
1261 * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
1262 * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
1263 * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
1264 * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
1265 * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
1266 * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
1267 */
1268#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
1269/*! @} */
1270
1271/*! @name MSTDAT - Combined Master receiver and transmitter data register. */
1272/*! @{ */
1273#define I2C_MSTDAT_DATA_MASK (0xFFU)
1274#define I2C_MSTDAT_DATA_SHIFT (0U)
1275/*! DATA - Master function data register. Read: read the most recently received data for the Master
1276 * function. Write: transmit data using the Master function.
1277 */
1278#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
1279/*! @} */
1280
1281/*! @name SLVCTL - Slave control register. */
1282/*! @{ */
1283#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U)
1284#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U)
1285/*! SLVCONTINUE - Slave Continue.
1286 * 0b0..No effect.
1287 * 0b1..Continue. Informs the Slave function to continue to the next operation. This must done after writing
1288 * transmit data, reading received data, or any other housekeeping related to the next bus operation.
1289 */
1290#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
1291#define I2C_SLVCTL_SLVNACK_MASK (0x2U)
1292#define I2C_SLVCTL_SLVNACK_SHIFT (1U)
1293/*! SLVNACK - Slave NACK.
1294 * 0b0..No effect.
1295 * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).
1296 */
1297#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
1298/*! @} */
1299
1300/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */
1301/*! @{ */
1302#define I2C_SLVDAT_DATA_MASK (0xFFU)
1303#define I2C_SLVDAT_DATA_SHIFT (0U)
1304/*! DATA - Slave function data register. Read: read the most recently received data for the Slave
1305 * function. Write: transmit data using the Slave function.
1306 */
1307#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
1308/*! @} */
1309
1310/*! @name SLVADR - Slave address register. */
1311/*! @{ */
1312#define I2C_SLVADR_SADISABLE_MASK (0x1U)
1313#define I2C_SLVADR_SADISABLE_SHIFT (0U)
1314/*! SADISABLE - Slave Address n Disable.
1315 * 0b0..Enabled. Slave Address n is enabled.
1316 * 0b1..Ignored Slave Address n is ignored.
1317 */
1318#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
1319#define I2C_SLVADR_SLVADR_MASK (0xFEU)
1320#define I2C_SLVADR_SLVADR_SHIFT (1U)
1321/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1322 */
1323#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
1324/*! @} */
1325
1326/* The count of I2C_SLVADR */
1327#define I2C_SLVADR_COUNT (4U)
1328
1329/*! @name SLVQUAL0 - Slave Qualification for address 0. */
1330/*! @{ */
1331#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U)
1332#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U)
1333/*! QUALMODE0 - Qualify mode for slave address 0.
1334 * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
1335 * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
1336 */
1337#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
1338#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU)
1339#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U)
1340/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to
1341 * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is
1342 * set to 1 will cause an automatic match of the corresponding bit of the received address when it
1343 * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for
1344 * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0
1345 * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).
1346 */
1347#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
1348/*! @} */
1349
1350/*! @name MONRXDAT - Monitor receiver data register. */
1351/*! @{ */
1352#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU)
1353#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U)
1354/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.
1355 */
1356#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
1357#define I2C_MONRXDAT_MONSTART_MASK (0x100U)
1358#define I2C_MONRXDAT_MONSTART_SHIFT (8U)
1359/*! MONSTART - Monitor Received Start.
1360 * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus.
1361 * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus.
1362 */
1363#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
1364#define I2C_MONRXDAT_MONRESTART_MASK (0x200U)
1365#define I2C_MONRXDAT_MONRESTART_SHIFT (9U)
1366/*! MONRESTART - Monitor Received Repeated Start.
1367 * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
1368 * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
1369 */
1370#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
1371#define I2C_MONRXDAT_MONNACK_MASK (0x400U)
1372#define I2C_MONRXDAT_MONNACK_SHIFT (10U)
1373/*! MONNACK - Monitor Received NACK.
1374 * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
1375 * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
1376 */
1377#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
1378/*! @} */
1379
1380
1381/*!
1382 * @}
1383 */ /* end of group I2C_Register_Masks */
1384
1385
1386/* I2C - Peripheral instance base addresses */
1387/** Peripheral I2C0 base address */
1388#define I2C0_BASE (0x40050000u)
1389/** Peripheral I2C0 base pointer */
1390#define I2C0 ((I2C_Type *)I2C0_BASE)
1391/** Array initializer of I2C peripheral base addresses */
1392#define I2C_BASE_ADDRS { I2C0_BASE }
1393/** Array initializer of I2C peripheral base pointers */
1394#define I2C_BASE_PTRS { I2C0 }
1395/** Interrupt vectors for the I2C peripheral type */
1396#define I2C_IRQS { I2C0_IRQn }
1397
1398/*!
1399 * @}
1400 */ /* end of group I2C_Peripheral_Access_Layer */
1401
1402
1403/* ----------------------------------------------------------------------------
1404 -- IOCON Peripheral Access Layer
1405 ---------------------------------------------------------------------------- */
1406
1407/*!
1408 * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer
1409 * @{
1410 */
1411
1412/** IOCON - Register Layout Typedef */
1413typedef struct {
1414 __IO uint32_t PIO[19]; /**< Digital I/O control for pins PIO0_17..Digital I/O control for pins PIO0_14, array offset: 0x0, array step: 0x4 */
1415} IOCON_Type;
1416
1417/* ----------------------------------------------------------------------------
1418 -- IOCON Register Masks
1419 ---------------------------------------------------------------------------- */
1420
1421/*!
1422 * @addtogroup IOCON_Register_Masks IOCON Register Masks
1423 * @{
1424 */
1425
1426/*! @name PIO - Digital I/O control for pins PIO0_17..Digital I/O control for pins PIO0_14 */
1427/*! @{ */
1428#define IOCON_PIO_MODE_MASK (0x18U)
1429#define IOCON_PIO_MODE_SHIFT (3U)
1430/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control).
1431 * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled).
1432 * 0b01..Pull-down. Pull-down resistor enabled.
1433 * 0b10..Pull-up. Pull-up resistor enabled.
1434 * 0b11..Repeater. Repeater mode.
1435 */
1436#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
1437#define IOCON_PIO_HYS_MASK (0x20U)
1438#define IOCON_PIO_HYS_SHIFT (5U)
1439/*! HYS - Hysteresis.
1440 * 0b0..Disable
1441 * 0b1..Enable
1442 */
1443#define IOCON_PIO_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_HYS_SHIFT)) & IOCON_PIO_HYS_MASK)
1444#define IOCON_PIO_INV_MASK (0x40U)
1445#define IOCON_PIO_INV_SHIFT (6U)
1446/*! INV - Invert input
1447 * 0b0..Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
1448 * 0b1..Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
1449 */
1450#define IOCON_PIO_INV(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INV_SHIFT)) & IOCON_PIO_INV_MASK)
1451#define IOCON_PIO_I2CMODE_MASK (0x300U)
1452#define IOCON_PIO_I2CMODE_SHIFT (8U)
1453/*! I2CMODE - Selects I2C mode.
1454 * 0b00..Standard mode/ Fast-mode I2C.
1455 * 0b01..Standard GPIO functionality. Requires external pull-up for GPIO output function.
1456 * 0b10..Fast-mode Plus I2C
1457 * 0b11..Reserved
1458 */
1459#define IOCON_PIO_I2CMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CMODE_SHIFT)) & IOCON_PIO_I2CMODE_MASK)
1460#define IOCON_PIO_OD_MASK (0x400U)
1461#define IOCON_PIO_OD_SHIFT (10U)
1462/*! OD - Open-drain mode.
1463 * 0b0..Disable.
1464 * 0b1..Open-drain mode enabled. Remark: This is not a true open-drain mode.
1465 */
1466#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
1467#define IOCON_PIO_S_MODE_MASK (0x1800U)
1468#define IOCON_PIO_S_MODE_SHIFT (11U)
1469/*! S_MODE - Digital filter sample mode.
1470 * 0b00..Bypass input filter.
1471 * 0b01..1 clock cycle. Input pulses shorter than one filter clock are rejected.
1472 * 0b10..2 clock cycles. Input pulses shorter than two filter clocks are rejected.
1473 * 0b11..3 clock cycles. Input pulses shorter than three filter clocks are rejected.
1474 */
1475#define IOCON_PIO_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_S_MODE_SHIFT)) & IOCON_PIO_S_MODE_MASK)
1476#define IOCON_PIO_CLK_DIV_MASK (0xE000U)
1477#define IOCON_PIO_CLK_DIV_SHIFT (13U)
1478/*! CLK_DIV - Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
1479 * 0b000..IOCONCLKDIV0
1480 * 0b001..IOCONCLKDIV1
1481 * 0b010..IOCONCLKDIV2
1482 * 0b011..IOCONCLKDIV3
1483 * 0b100..IOCONCLKDIV4
1484 * 0b101..IOCONCLKDIV5
1485 * 0b110..IOCONCLKDIV6
1486 */
1487#define IOCON_PIO_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_CLK_DIV_SHIFT)) & IOCON_PIO_CLK_DIV_MASK)
1488/*! @} */
1489
1490/* The count of IOCON_PIO */
1491#define IOCON_PIO_COUNT (19U)
1492
1493
1494/*!
1495 * @}
1496 */ /* end of group IOCON_Register_Masks */
1497
1498
1499/* IOCON - Peripheral instance base addresses */
1500/** Peripheral IOCON base address */
1501#define IOCON_BASE (0x40044000u)
1502/** Peripheral IOCON base pointer */
1503#define IOCON ((IOCON_Type *)IOCON_BASE)
1504/** Array initializer of IOCON peripheral base addresses */
1505#define IOCON_BASE_ADDRS { IOCON_BASE }
1506/** Array initializer of IOCON peripheral base pointers */
1507#define IOCON_BASE_PTRS { IOCON }
1508
1509#define IOCON_INDEX_PIO0_17 (0 )
1510#define IOCON_INDEX_PIO0_13 (1 )
1511#define IOCON_INDEX_PIO0_12 (2 )
1512#define IOCON_INDEX_PIO0_5 (3 )
1513#define IOCON_INDEX_PIO0_4 (4 )
1514#define IOCON_INDEX_PIO0_3 (5 )
1515#define IOCON_INDEX_PIO0_2 (6 )
1516#define IOCON_INDEX_PIO0_11 (7 )
1517#define IOCON_INDEX_PIO0_10 (8 )
1518#define IOCON_INDEX_PIO0_16 (9 )
1519#define IOCON_INDEX_PIO0_15 (10)
1520#define IOCON_INDEX_PIO0_1 (11)
1521#define IOCON_INDEX_PIO0_9 (13)
1522#define IOCON_INDEX_PIO0_8 (14)
1523#define IOCON_INDEX_PIO0_7 (15)
1524#define IOCON_INDEX_PIO0_6 (16)
1525#define IOCON_INDEX_PIO0_0 (17)
1526#define IOCON_INDEX_PIO0_14 (18)
1527
1528
1529/*!
1530 * @}
1531 */ /* end of group IOCON_Peripheral_Access_Layer */
1532
1533
1534/* ----------------------------------------------------------------------------
1535 -- MRT Peripheral Access Layer
1536 ---------------------------------------------------------------------------- */
1537
1538/*!
1539 * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
1540 * @{
1541 */
1542
1543/** MRT - Register Layout Typedef */
1544typedef struct {
1545 struct { /* offset: 0x0, array step: 0x10 */
1546 __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */
1547 __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */
1548 __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */
1549 __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */
1550 } CHANNEL[4];
1551 uint8_t RESERVED_0[176];
1552 __I uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance., offset: 0xF0 */
1553 __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */
1554 __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */
1555} MRT_Type;
1556
1557/* ----------------------------------------------------------------------------
1558 -- MRT Register Masks
1559 ---------------------------------------------------------------------------- */
1560
1561/*!
1562 * @addtogroup MRT_Register_Masks MRT Register Masks
1563 * @{
1564 */
1565
1566/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */
1567/*! @{ */
1568#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0x7FFFFFFFU)
1569#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U)
1570/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT
1571 * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to
1572 * this bit field starts the timer immediately. If the timer is running, writing a zero to this
1573 * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer
1574 * stops at the end of the time interval.
1575 */
1576#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
1577#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U)
1578#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U)
1579/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register.
1580 * This bit is write-only. Reading this bit always returns 0.
1581 * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the
1582 * time interval if the repeat mode is selected.
1583 * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
1584 */
1585#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
1586/*! @} */
1587
1588/* The count of MRT_CHANNEL_INTVAL */
1589#define MRT_CHANNEL_INTVAL_COUNT (4U)
1590
1591/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */
1592/*! @{ */
1593#define MRT_CHANNEL_TIMER_VALUE_MASK (0x7FFFFFFFU)
1594#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U)
1595/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn
1596 * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval
1597 * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn
1598 * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields
1599 * returns -1 (0x00FF FFFF).
1600 */
1601#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
1602/*! @} */
1603
1604/* The count of MRT_CHANNEL_TIMER */
1605#define MRT_CHANNEL_TIMER_COUNT (4U)
1606
1607/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */
1608/*! @{ */
1609#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U)
1610#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U)
1611/*! INTEN - Enable the TIMERn interrupt.
1612 * 0b0..Disabled. TIMERn interrupt is disabled.
1613 * 0b1..Enabled. TIMERn interrupt is enabled.
1614 */
1615#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
1616#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U)
1617#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U)
1618/*! MODE - Selects timer mode.
1619 * 0b00..Repeat interrupt mode.
1620 * 0b01..One-shot interrupt mode.
1621 * 0b10..One-shot stall mode.
1622 * 0b11..Reserved.
1623 */
1624#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
1625/*! @} */
1626
1627/* The count of MRT_CHANNEL_CTRL */
1628#define MRT_CHANNEL_CTRL_COUNT (4U)
1629
1630/*! @name CHANNEL_STAT - MRT Status register. */
1631/*! @{ */
1632#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U)
1633#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U)
1634/*! INTFLAG - Monitors the interrupt flag.
1635 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
1636 * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If
1637 * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt
1638 * are raised. Writing a 1 to this bit clears the interrupt request.
1639 */
1640#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
1641#define MRT_CHANNEL_STAT_RUN_MASK (0x2U)
1642#define MRT_CHANNEL_STAT_RUN_SHIFT (1U)
1643/*! RUN - Indicates the state of TIMERn. This bit is read-only.
1644 * 0b0..Idle state. TIMERn is stopped.
1645 * 0b1..Running. TIMERn is running.
1646 */
1647#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
1648/*! @} */
1649
1650/* The count of MRT_CHANNEL_STAT */
1651#define MRT_CHANNEL_STAT_COUNT (4U)
1652
1653/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance. */
1654/*! @{ */
1655#define MRT_MODCFG_NOC_MASK (0xFU)
1656#define MRT_MODCFG_NOC_SHIFT (0U)
1657/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.)
1658 */
1659#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
1660#define MRT_MODCFG_NOB_MASK (0x1F0U)
1661#define MRT_MODCFG_NOB_SHIFT (4U)
1662/*! NOB - Identifies the number of timer bits in this MRT. (31 bits wide on this device.)
1663 */
1664#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
1665/*! @} */
1666
1667/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */
1668/*! @{ */
1669#define MRT_IDLE_CH_CHAN_MASK (0xF0U)
1670#define MRT_IDLE_CH_CHAN_SHIFT (4U)
1671/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is
1672 * positioned such that it can be used as an offset from the MRT base address in order to access
1673 * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See
1674 * text above for more details.
1675 */
1676#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
1677/*! @} */
1678
1679/*! @name IRQ_FLAG - Global interrupt flag register */
1680/*! @{ */
1681#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U)
1682#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U)
1683/*! GFLAG0 - Monitors the interrupt flag of TIMER0.
1684 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
1685 * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If
1686 * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global
1687 * interrupt are raised. Writing a 1 to this bit clears the interrupt request.
1688 */
1689#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
1690#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U)
1691#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U)
1692/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0.
1693 */
1694#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
1695#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U)
1696#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U)
1697/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0.
1698 */
1699#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
1700#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U)
1701#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U)
1702/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0.
1703 */
1704#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
1705/*! @} */
1706
1707
1708/*!
1709 * @}
1710 */ /* end of group MRT_Register_Masks */
1711
1712
1713/* MRT - Peripheral instance base addresses */
1714/** Peripheral MRT0 base address */
1715#define MRT0_BASE (0x40004000u)
1716/** Peripheral MRT0 base pointer */
1717#define MRT0 ((MRT_Type *)MRT0_BASE)
1718/** Array initializer of MRT peripheral base addresses */
1719#define MRT_BASE_ADDRS { MRT0_BASE }
1720/** Array initializer of MRT peripheral base pointers */
1721#define MRT_BASE_PTRS { MRT0 }
1722/** Interrupt vectors for the MRT peripheral type */
1723#define MRT_IRQS { MRT0_IRQn }
1724
1725/*!
1726 * @}
1727 */ /* end of group MRT_Peripheral_Access_Layer */
1728
1729
1730/* ----------------------------------------------------------------------------
1731 -- MTB Peripheral Access Layer
1732 ---------------------------------------------------------------------------- */
1733
1734/*!
1735 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
1736 * @{
1737 */
1738
1739/** MTB - Register Layout Typedef */
1740typedef struct {
1741 __IO uint32_t POSITION; /**< POSITION Register, offset: 0x0 */
1742 __IO uint32_t MASTER; /**< MASTER Register, offset: 0x4 */
1743 __IO uint32_t FLOW; /**< FLOW Register, offset: 0x8 */
1744 __I uint32_t BASE; /**< Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB SRAM location, by a debug agent., offset: 0xC */
1745} MTB_Type;
1746
1747/* ----------------------------------------------------------------------------
1748 -- MTB Register Masks
1749 ---------------------------------------------------------------------------- */
1750
1751/*!
1752 * @addtogroup MTB_Register_Masks MTB Register Masks
1753 * @{
1754 */
1755
1756/*! @name POSITION - POSITION Register */
1757/*! @{ */
1758#define MTB_POSITION_WRAP_MASK (0x4U)
1759#define MTB_POSITION_WRAP_SHIFT (2U)
1760/*! WRAP - This bit is set to 1 automatically when the POINTER value wraps as determined by the
1761 * MASTER.MASK field in the MASTER Trace Control Register.
1762 */
1763#define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
1764#define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U)
1765#define MTB_POSITION_POINTER_SHIFT (3U)
1766/*! POINTER - Trace packet location pointer. Because a packet consists of two words, the POINTER
1767 * field is the location of the first word of a packet. This field contains bits [31:3] of the
1768 * address, in the SRAM, where the next trace packet will be written. The field points to an unused
1769 * location and is automatically incremented. A debug agent can calculate the system address, on
1770 * the AHB-Lite bus, of the SRAM location pointed to by the POSITION register using the following
1771 * equation: system address = BASE + ((P + (2AWIDTH - (BASE MOD 2AWIDTH))) MOD 2AWIDTH). Where P =
1772 * POSITION AND 0xFFFF_FFF8. Where BASE is the BASE register value
1773 */
1774#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
1775/*! @} */
1776
1777/*! @name MASTER - MASTER Register */
1778/*! @{ */
1779#define MTB_MASTER_MASK_MASK (0x1FU)
1780#define MTB_MASTER_MASK_SHIFT (0U)
1781/*! MASK - This value determines the maximum size of the trace buffer in SRAM. It specifies the
1782 * most-significant bit of the POSITION.POINTER field that can be updated by automatic increment. If
1783 * the trace tries to advance past this power of two, the POSITION.WRAP bit is set to 1, the
1784 * POSITION.POINTER[MASK:0] bits are set to zero, and the POSITION.POINTER[AWIDTH-4:MASK+1] bits
1785 * remain unchanged. This field causes the trace packet information to be stored in a circular buffer
1786 * of size 2(MASK+4) bytes, that can be positioned in memory at multiples of this size. Valid
1787 * values of this field are zero to AWIDTH-4. Values greater than the maximum have the same effect
1788 * as the maximum.
1789 */
1790#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
1791#define MTB_MASTER_TSTARTEN_MASK (0x20U)
1792#define MTB_MASTER_TSTARTEN_SHIFT (5U)
1793/*! TSTARTEN - Trace start input enable. If this bit is 1 and the TSTART signal is HIGH, then the EN
1794 * bit is set to 1. Tracing continues until a stop condition occurs.
1795 */
1796#define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
1797#define MTB_MASTER_TSTOPEN_MASK (0x40U)
1798#define MTB_MASTER_TSTOPEN_SHIFT (6U)
1799/*! TSTOPEN - Trace stop input enable. If this bit is 1 and the TSTOP signal is HIGH, then the EN
1800 * bit is set to 0. If a trace packet is being written to memory, the write is completed before
1801 * tracing is stopped.
1802 */
1803#define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
1804#define MTB_MASTER_SFRWPRIV_MASK (0x80U)
1805#define MTB_MASTER_SFRWPRIV_SHIFT (7U)
1806/*! SFRWPRIV - Special Function Register Write Privilege bit. If this bit is 0, then User or
1807 * Privileged AHB-Lite read and write accesses to the Special Function Registers are permitted. If this
1808 * bit is 1, then only Privileged write accesses are permitted and User write accesses are
1809 * ignored. The HPROT[1] signal determines if an access is User or Privileged.
1810 */
1811#define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
1812#define MTB_MASTER_RAMPRIV_MASK (0x100U)
1813#define MTB_MASTER_RAMPRIV_SHIFT (8U)
1814/*! RAMPRIV - SRAM Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write
1815 * accesses to the SRAM are permitted. If this bit is 1, then only Privileged AHB-Lite read and
1816 * write accesses to the SRAM are permitted and User accesses are RAZ/WI. The HPROT[1] signal
1817 * determines if an access is User or Privileged.
1818 */
1819#define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
1820#define MTB_MASTER_HALTREQ_MASK (0x200U)
1821#define MTB_MASTER_HALTREQ_SHIFT (9U)
1822/*! HALTREQ - Halt request bit. This bit is connected to the halt request signal of the trace logic,
1823 * EDBGRQ. When HALTREQ is set to 1, EDBGRQ is asserted if DBGEN is also HIGH. The HALTREQ bit
1824 * can be automatically set to 1 using the FLOW.WATERMARK field.
1825 */
1826#define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
1827#define MTB_MASTER_EN_MASK (0x80000000U)
1828#define MTB_MASTER_EN_SHIFT (31U)
1829/*! EN - Main trace enable bit. When this bit is 1 trace data is written into the SRAM memory
1830 * location addressed by POSITION.POINTER. The POSITION.POINTER value auto increments after the trace
1831 * data packet is written. The EN bit can be automatically set to 0 using the FLOW.WATERMARK field
1832 * and the FLOW.AUTOSTOP bit. The EN bit is automatically set to 1 if the TSTARTEN bit is 1 and
1833 * the TSTART signal is HIGH. The EN bit is automatically set to 0 if TSTOPEN bit is 1 and the
1834 * TSTOP signal is HIGH.
1835 */
1836#define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
1837/*! @} */
1838
1839/*! @name FLOW - FLOW Register */
1840/*! @{ */
1841#define MTB_FLOW_AUTOSTOP_MASK (0x1U)
1842#define MTB_FLOW_AUTOSTOP_SHIFT (0U)
1843/*! AUTOSTOP - If this bit is 1 and WATERMARK is equal to POSITION.POINTER, then the MASTER.EN bit
1844 * is automatically set to 0. This stops tracing.
1845 */
1846#define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
1847#define MTB_FLOW_AUTOHALT_MASK (0x2U)
1848#define MTB_FLOW_AUTOHALT_SHIFT (1U)
1849/*! AUTOHALT - If this bit is 1 and WATERMARK is equal to POSITION.POINTER, then the MASTER.HALTREQ
1850 * bit is automatically set to 1. If the DBGEN signal is HIGH, the MTB asserts this halt request
1851 * to the Cortex-M0+ processor by asserting the EDBGRQ signal.
1852 */
1853#define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
1854#define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U)
1855#define MTB_FLOW_WATERMARK_SHIFT (3U)
1856/*! WATERMARK - WATERMARK value. This field contains an address in the same format as the
1857 * POSITION.POINTER field. When the POSITION.POINTER matches the WATERMARK field value, actions defined by
1858 * the AUTOHALT and AUTOSTOP bits are performed.
1859 */
1860#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
1861/*! @} */
1862
1863/*! @name BASE - Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB SRAM location, by a debug agent. */
1864/*! @{ */
1865#define MTB_BASE_BASE_MASK (0xFFFFFFFFU)
1866#define MTB_BASE_BASE_SHIFT (0U)
1867/*! BASE - The value provided is the value of the SRAMBASEADDR[31:0] signal.
1868 */
1869#define MTB_BASE_BASE(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASE_SHIFT)) & MTB_BASE_BASE_MASK)
1870/*! @} */
1871
1872
1873/*!
1874 * @}
1875 */ /* end of group MTB_Register_Masks */
1876
1877
1878/* MTB - Peripheral instance base addresses */
1879/** Peripheral MTB base address */
1880#define MTB_BASE (0x14000000u)
1881/** Peripheral MTB base pointer */
1882#define MTB ((MTB_Type *)MTB_BASE)
1883/** Array initializer of MTB peripheral base addresses */
1884#define MTB_BASE_ADDRS { MTB_BASE }
1885/** Array initializer of MTB peripheral base pointers */
1886#define MTB_BASE_PTRS { MTB }
1887
1888/*!
1889 * @}
1890 */ /* end of group MTB_Peripheral_Access_Layer */
1891
1892
1893/* ----------------------------------------------------------------------------
1894 -- PINT Peripheral Access Layer
1895 ---------------------------------------------------------------------------- */
1896
1897/*!
1898 * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
1899 * @{
1900 */
1901
1902/** PINT - Register Layout Typedef */
1903typedef struct {
1904 __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */
1905 __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */
1906 __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */
1907 __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */
1908 __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */
1909 __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */
1910 __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */
1911 __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */
1912 __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */
1913 __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */
1914 __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */
1915 __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */
1916 __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */
1917} PINT_Type;
1918
1919/* ----------------------------------------------------------------------------
1920 -- PINT Register Masks
1921 ---------------------------------------------------------------------------- */
1922
1923/*!
1924 * @addtogroup PINT_Register_Masks PINT Register Masks
1925 * @{
1926 */
1927
1928/*! @name ISEL - Pin Interrupt Mode register */
1929/*! @{ */
1930#define PINT_ISEL_PMODE_MASK (0xFFU)
1931#define PINT_ISEL_PMODE_SHIFT (0U)
1932/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt
1933 * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive
1934 */
1935#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
1936/*! @} */
1937
1938/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */
1939/*! @{ */
1940#define PINT_IENR_ENRL_MASK (0xFFU)
1941#define PINT_IENR_ENRL_SHIFT (0U)
1942/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the
1943 * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable
1944 * rising edge or level interrupt.
1945 */
1946#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
1947/*! @} */
1948
1949/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */
1950/*! @{ */
1951#define PINT_SIENR_SETENRL_MASK (0xFFU)
1952#define PINT_SIENR_SETENRL_SHIFT (0U)
1953/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n
1954 * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.
1955 */
1956#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
1957/*! @} */
1958
1959/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */
1960/*! @{ */
1961#define PINT_CIENR_CENRL_MASK (0xFFU)
1962#define PINT_CIENR_CENRL_SHIFT (0U)
1963/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit
1964 * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level
1965 * interrupt.
1966 */
1967#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
1968/*! @} */
1969
1970/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */
1971/*! @{ */
1972#define PINT_IENF_ENAF_MASK (0xFFU)
1973#define PINT_IENF_ENAF_SHIFT (0U)
1974/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt.
1975 * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt
1976 * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active
1977 * interrupt level HIGH.
1978 */
1979#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
1980/*! @} */
1981
1982/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */
1983/*! @{ */
1984#define PINT_SIENF_SETENAF_MASK (0xFFU)
1985#define PINT_SIENF_SETENAF_SHIFT (0U)
1986/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n
1987 * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable
1988 * falling edge interrupt.
1989 */
1990#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
1991/*! @} */
1992
1993/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */
1994/*! @{ */
1995#define PINT_CIENF_CENAF_MASK (0xFFU)
1996#define PINT_CIENF_CENAF_SHIFT (0U)
1997/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n
1998 * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or
1999 * falling edge interrupt disabled.
2000 */
2001#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
2002/*! @} */
2003
2004/*! @name RISE - Pin interrupt rising edge register */
2005/*! @{ */
2006#define PINT_RISE_RDET_MASK (0xFFU)
2007#define PINT_RISE_RDET_SHIFT (0U)
2008/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read
2009 * 0: No rising edge has been detected on this pin since Reset or the last time a one was written
2010 * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the
2011 * last time a one was written to this bit. Write 1: clear rising edge detection for this pin.
2012 */
2013#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
2014/*! @} */
2015
2016/*! @name FALL - Pin interrupt falling edge register */
2017/*! @{ */
2018#define PINT_FALL_FDET_MASK (0xFFU)
2019#define PINT_FALL_FDET_SHIFT (0U)
2020/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read
2021 * 0: No falling edge has been detected on this pin since Reset or the last time a one was
2022 * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or
2023 * the last time a one was written to this bit. Write 1: clear falling edge detection for this
2024 * pin.
2025 */
2026#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
2027/*! @} */
2028
2029/*! @name IST - Pin interrupt status register */
2030/*! @{ */
2031#define PINT_IST_PSTAT_MASK (0xFFU)
2032#define PINT_IST_PSTAT_SHIFT (0U)
2033/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts
2034 * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for
2035 * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this
2036 * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin.
2037 * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).
2038 */
2039#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
2040/*! @} */
2041
2042/*! @name PMCTRL - Pattern match interrupt control register */
2043/*! @{ */
2044#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U)
2045#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U)
2046/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.
2047 * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.
2048 * 0b1..Pattern match. Interrupts are driven in response to pattern matches.
2049 */
2050#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
2051#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U)
2052#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U)
2053/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.
2054 * 0b0..Disabled. RXEV output to the CPU is disabled.
2055 * 0b1..Enabled. RXEV output to the CPU is enabled.
2056 */
2057#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
2058#define PINT_PMCTRL_PMAT_MASK (0xFF000000U)
2059#define PINT_PMCTRL_PMAT_SHIFT (24U)
2060/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field
2061 * indicates that the corresponding product term is matched by the current state of the appropriate
2062 * inputs.
2063 */
2064#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
2065/*! @} */
2066
2067/*! @name PMSRC - Pattern match interrupt bit-slice source register */
2068/*! @{ */
2069#define PINT_PMSRC_SRC0_MASK (0x700U)
2070#define PINT_PMSRC_SRC0_SHIFT (8U)
2071/*! SRC0 - Selects the input source for bit slice 0
2072 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.
2073 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0.
2074 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0.
2075 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0.
2076 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0.
2077 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0.
2078 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0.
2079 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0.
2080 */
2081#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
2082#define PINT_PMSRC_SRC1_MASK (0x3800U)
2083#define PINT_PMSRC_SRC1_SHIFT (11U)
2084/*! SRC1 - Selects the input source for bit slice 1
2085 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.
2086 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1.
2087 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1.
2088 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1.
2089 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1.
2090 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1.
2091 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1.
2092 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1.
2093 */
2094#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
2095#define PINT_PMSRC_SRC2_MASK (0x1C000U)
2096#define PINT_PMSRC_SRC2_SHIFT (14U)
2097/*! SRC2 - Selects the input source for bit slice 2
2098 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.
2099 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2.
2100 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2.
2101 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2.
2102 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2.
2103 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2.
2104 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2.
2105 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2.
2106 */
2107#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
2108#define PINT_PMSRC_SRC3_MASK (0xE0000U)
2109#define PINT_PMSRC_SRC3_SHIFT (17U)
2110/*! SRC3 - Selects the input source for bit slice 3
2111 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3.
2112 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3.
2113 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3.
2114 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3.
2115 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3.
2116 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3.
2117 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3.
2118 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3.
2119 */
2120#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
2121#define PINT_PMSRC_SRC4_MASK (0x700000U)
2122#define PINT_PMSRC_SRC4_SHIFT (20U)
2123/*! SRC4 - Selects the input source for bit slice 4
2124 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.
2125 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4.
2126 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4.
2127 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4.
2128 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4.
2129 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4.
2130 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4.
2131 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4.
2132 */
2133#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
2134#define PINT_PMSRC_SRC5_MASK (0x3800000U)
2135#define PINT_PMSRC_SRC5_SHIFT (23U)
2136/*! SRC5 - Selects the input source for bit slice 5
2137 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.
2138 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5.
2139 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5.
2140 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5.
2141 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5.
2142 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5.
2143 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5.
2144 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5.
2145 */
2146#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
2147#define PINT_PMSRC_SRC6_MASK (0x1C000000U)
2148#define PINT_PMSRC_SRC6_SHIFT (26U)
2149/*! SRC6 - Selects the input source for bit slice 6
2150 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.
2151 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6.
2152 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6.
2153 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6.
2154 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6.
2155 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6.
2156 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6.
2157 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6.
2158 */
2159#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
2160#define PINT_PMSRC_SRC7_MASK (0xE0000000U)
2161#define PINT_PMSRC_SRC7_SHIFT (29U)
2162/*! SRC7 - Selects the input source for bit slice 7
2163 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7.
2164 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7.
2165 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7.
2166 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7.
2167 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7.
2168 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7.
2169 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7.
2170 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7.
2171 */
2172#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
2173/*! @} */
2174
2175/*! @name PMCFG - Pattern match interrupt bit slice configuration register */
2176/*! @{ */
2177#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U)
2178#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U)
2179/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint.
2180 * 0b0..No effect. Slice 0 is not an endpoint.
2181 * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.
2182 */
2183#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
2184#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U)
2185#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U)
2186/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint.
2187 * 0b0..No effect. Slice 1 is not an endpoint.
2188 * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.
2189 */
2190#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
2191#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U)
2192#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U)
2193/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint.
2194 * 0b0..No effect. Slice 2 is not an endpoint.
2195 * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.
2196 */
2197#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
2198#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U)
2199#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U)
2200/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint.
2201 * 0b0..No effect. Slice 3 is not an endpoint.
2202 * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.
2203 */
2204#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
2205#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U)
2206#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U)
2207/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint.
2208 * 0b0..No effect. Slice 4 is not an endpoint.
2209 * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.
2210 */
2211#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
2212#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U)
2213#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U)
2214/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint.
2215 * 0b0..No effect. Slice 5 is not an endpoint.
2216 * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.
2217 */
2218#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
2219#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U)
2220#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U)
2221/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint.
2222 * 0b0..No effect. Slice 6 is not an endpoint.
2223 * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.
2224 */
2225#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
2226#define PINT_PMCFG_CFG0_MASK (0x700U)
2227#define PINT_PMCFG_CFG0_SHIFT (8U)
2228/*! CFG0 - Specifies the match contribution condition for bit slice 0.
2229 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
2230 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
2231 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2232 * PMSRC registers are written to.
2233 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
2234 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2235 * PMSRC registers are written to.
2236 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
2237 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
2238 * cleared when the PMCFG or the PMSRC registers are written to.
2239 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
2240 * 0b101..Low level. Match occurs when there is a low level on the specified input.
2241 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
2242 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
2243 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
2244 * is cleared after one clock cycle.
2245 */
2246#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
2247#define PINT_PMCFG_CFG1_MASK (0x3800U)
2248#define PINT_PMCFG_CFG1_SHIFT (11U)
2249/*! CFG1 - Specifies the match contribution condition for bit slice 1.
2250 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
2251 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
2252 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2253 * PMSRC registers are written to.
2254 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
2255 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2256 * PMSRC registers are written to.
2257 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
2258 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
2259 * cleared when the PMCFG or the PMSRC registers are written to.
2260 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
2261 * 0b101..Low level. Match occurs when there is a low level on the specified input.
2262 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
2263 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
2264 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
2265 * is cleared after one clock cycle.
2266 */
2267#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
2268#define PINT_PMCFG_CFG2_MASK (0x1C000U)
2269#define PINT_PMCFG_CFG2_SHIFT (14U)
2270/*! CFG2 - Specifies the match contribution condition for bit slice 2.
2271 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
2272 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
2273 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2274 * PMSRC registers are written to.
2275 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
2276 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2277 * PMSRC registers are written to.
2278 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
2279 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
2280 * cleared when the PMCFG or the PMSRC registers are written to.
2281 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
2282 * 0b101..Low level. Match occurs when there is a low level on the specified input.
2283 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
2284 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
2285 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
2286 * is cleared after one clock cycle.
2287 */
2288#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
2289#define PINT_PMCFG_CFG3_MASK (0xE0000U)
2290#define PINT_PMCFG_CFG3_SHIFT (17U)
2291/*! CFG3 - Specifies the match contribution condition for bit slice 3.
2292 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
2293 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
2294 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2295 * PMSRC registers are written to.
2296 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
2297 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2298 * PMSRC registers are written to.
2299 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
2300 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
2301 * cleared when the PMCFG or the PMSRC registers are written to.
2302 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
2303 * 0b101..Low level. Match occurs when there is a low level on the specified input.
2304 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
2305 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
2306 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
2307 * is cleared after one clock cycle.
2308 */
2309#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
2310#define PINT_PMCFG_CFG4_MASK (0x700000U)
2311#define PINT_PMCFG_CFG4_SHIFT (20U)
2312/*! CFG4 - Specifies the match contribution condition for bit slice 4.
2313 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
2314 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
2315 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2316 * PMSRC registers are written to.
2317 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
2318 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2319 * PMSRC registers are written to.
2320 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
2321 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
2322 * cleared when the PMCFG or the PMSRC registers are written to.
2323 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
2324 * 0b101..Low level. Match occurs when there is a low level on the specified input.
2325 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
2326 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
2327 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
2328 * is cleared after one clock cycle.
2329 */
2330#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
2331#define PINT_PMCFG_CFG5_MASK (0x3800000U)
2332#define PINT_PMCFG_CFG5_SHIFT (23U)
2333/*! CFG5 - Specifies the match contribution condition for bit slice 5.
2334 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
2335 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
2336 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2337 * PMSRC registers are written to.
2338 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
2339 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2340 * PMSRC registers are written to.
2341 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
2342 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
2343 * cleared when the PMCFG or the PMSRC registers are written to.
2344 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
2345 * 0b101..Low level. Match occurs when there is a low level on the specified input.
2346 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
2347 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
2348 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
2349 * is cleared after one clock cycle.
2350 */
2351#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
2352#define PINT_PMCFG_CFG6_MASK (0x1C000000U)
2353#define PINT_PMCFG_CFG6_SHIFT (26U)
2354/*! CFG6 - Specifies the match contribution condition for bit slice 6.
2355 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
2356 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
2357 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2358 * PMSRC registers are written to.
2359 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
2360 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2361 * PMSRC registers are written to.
2362 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
2363 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
2364 * cleared when the PMCFG or the PMSRC registers are written to.
2365 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
2366 * 0b101..Low level. Match occurs when there is a low level on the specified input.
2367 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
2368 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
2369 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
2370 * is cleared after one clock cycle.
2371 */
2372#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
2373#define PINT_PMCFG_CFG7_MASK (0xE0000000U)
2374#define PINT_PMCFG_CFG7_SHIFT (29U)
2375/*! CFG7 - Specifies the match contribution condition for bit slice 7.
2376 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
2377 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
2378 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2379 * PMSRC registers are written to.
2380 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
2381 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
2382 * PMSRC registers are written to.
2383 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
2384 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
2385 * cleared when the PMCFG or the PMSRC registers are written to.
2386 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
2387 * 0b101..Low level. Match occurs when there is a low level on the specified input.
2388 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
2389 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
2390 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
2391 * is cleared after one clock cycle.
2392 */
2393#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
2394/*! @} */
2395
2396
2397/*!
2398 * @}
2399 */ /* end of group PINT_Register_Masks */
2400
2401
2402/* PINT - Peripheral instance base addresses */
2403/** Peripheral PINT base address */
2404#define PINT_BASE (0xA0004000u)
2405/** Peripheral PINT base pointer */
2406#define PINT ((PINT_Type *)PINT_BASE)
2407/** Array initializer of PINT peripheral base addresses */
2408#define PINT_BASE_ADDRS { PINT_BASE }
2409/** Array initializer of PINT peripheral base pointers */
2410#define PINT_BASE_PTRS { PINT }
2411/** Interrupt vectors for the PINT peripheral type */
2412#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }
2413
2414/*!
2415 * @}
2416 */ /* end of group PINT_Peripheral_Access_Layer */
2417
2418
2419/* ----------------------------------------------------------------------------
2420 -- PMU Peripheral Access Layer
2421 ---------------------------------------------------------------------------- */
2422
2423/*!
2424 * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer
2425 * @{
2426 */
2427
2428/** PMU - Register Layout Typedef */
2429typedef struct {
2430 __IO uint32_t PCON; /**< Power control register, offset: 0x0 */
2431 __IO uint32_t GPREG[4]; /**< General purpose register N, array offset: 0x4, array step: 0x4 */
2432 __IO uint32_t DPDCTRL; /**< Deep power-down control register. Also includes bits for general purpose storage., offset: 0x14 */
2433} PMU_Type;
2434
2435/* ----------------------------------------------------------------------------
2436 -- PMU Register Masks
2437 ---------------------------------------------------------------------------- */
2438
2439/*!
2440 * @addtogroup PMU_Register_Masks PMU Register Masks
2441 * @{
2442 */
2443
2444/*! @name PCON - Power control register */
2445/*! @{ */
2446#define PMU_PCON_PM_MASK (0x7U)
2447#define PMU_PCON_PM_SHIFT (0U)
2448/*! PM - Power mode
2449 * 0b000..Default. The part is in active or sleep mode.
2450 * 0b001..Deep-sleep mode. ARM WFI will enter Deep-sleep mode.
2451 * 0b010..Power-down mode. ARM WFI will enter Power-down mode.
2452 * 0b011..Deep power-down mode. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down).
2453 */
2454#define PMU_PCON_PM(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_PM_SHIFT)) & PMU_PCON_PM_MASK)
2455#define PMU_PCON_NODPD_MASK (0x8U)
2456#define PMU_PCON_NODPD_SHIFT (3U)
2457/*! NODPD - A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM
2458 * field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by
2459 * power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode
2460 * is blocked.
2461 */
2462#define PMU_PCON_NODPD(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_NODPD_SHIFT)) & PMU_PCON_NODPD_MASK)
2463#define PMU_PCON_SLEEPFLAG_MASK (0x100U)
2464#define PMU_PCON_SLEEPFLAG_SHIFT (8U)
2465/*! SLEEPFLAG - Sleep mode flag
2466 * 0b0..Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect.
2467 * 0b1..Low power mode. Read: Sleep, Deep-sleep or Power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0.
2468 */
2469#define PMU_PCON_SLEEPFLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_SLEEPFLAG_SHIFT)) & PMU_PCON_SLEEPFLAG_MASK)
2470#define PMU_PCON_DPDFLAG_MASK (0x800U)
2471#define PMU_PCON_DPDFLAG_SHIFT (11U)
2472/*! DPDFLAG - Deep power-down flag
2473 * 0b0..Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect.
2474 * 0b1..Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag.
2475 */
2476#define PMU_PCON_DPDFLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_DPDFLAG_SHIFT)) & PMU_PCON_DPDFLAG_MASK)
2477/*! @} */
2478
2479/*! @name GPREG - General purpose register N */
2480/*! @{ */
2481#define PMU_GPREG_GPDATA_MASK (0xFFFFFFFFU)
2482#define PMU_GPREG_GPDATA_SHIFT (0U)
2483/*! GPDATA - Data retained during Deep power-down mode.
2484 */
2485#define PMU_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPREG_GPDATA_SHIFT)) & PMU_GPREG_GPDATA_MASK)
2486/*! @} */
2487
2488/* The count of PMU_GPREG */
2489#define PMU_GPREG_COUNT (4U)
2490
2491/*! @name DPDCTRL - Deep power-down control register. Also includes bits for general purpose storage. */
2492/*! @{ */
2493#define PMU_DPDCTRL_WAKEUPHYS_MASK (0x1U)
2494#define PMU_DPDCTRL_WAKEUPHYS_SHIFT (0U)
2495/*! WAKEUPHYS - WAKEUP pin hysteresis enable
2496 * 0b0..Disabled. Hysteresis for WAKEUP pin disabled.
2497 * 0b1..Enabled. Hysteresis for WAKEUP pin enabled.
2498 */
2499#define PMU_DPDCTRL_WAKEUPHYS(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_WAKEUPHYS_SHIFT)) & PMU_DPDCTRL_WAKEUPHYS_MASK)
2500#define PMU_DPDCTRL_WAKEPAD_DISABLE_MASK (0x2U)
2501#define PMU_DPDCTRL_WAKEPAD_DISABLE_SHIFT (1U)
2502/*! WAKEPAD_DISABLE - WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be
2503 * used for other purposes. Remark: Never set this bit if you intend to use a pin to wake up the
2504 * part from Deep power-down mode. You can only disable the wake-up pin if the self wake-up timer
2505 * is enabled and configured. Remark: Setting this bit is not necessary if Deep power-down mode is
2506 * not used.
2507 * 0b0..Enabled. The wake-up function is enabled on pin PIO0_4.
2508 * 0b1..Disabled. Setting this bit disables the wake-up function on pin PIO0_4.
2509 */
2510#define PMU_DPDCTRL_WAKEPAD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_WAKEPAD_DISABLE_SHIFT)) & PMU_DPDCTRL_WAKEPAD_DISABLE_MASK)
2511#define PMU_DPDCTRL_LPOSCEN_MASK (0x4U)
2512#define PMU_DPDCTRL_LPOSCEN_SHIFT (2U)
2513/*! LPOSCEN - Enable the low-power oscillator for use with the 10 kHz self wake-up timer clock. You
2514 * must set this bit if the CLKSEL bit in the self wake-up timer CTRL bit is set. Do not enable
2515 * the low-power oscillator if the self wake-up timer is clocked by the divided IRC or the
2516 * external clock input.
2517 * 0b0..Disabled.
2518 * 0b1..Enabled.
2519 */
2520#define PMU_DPDCTRL_LPOSCEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_LPOSCEN_SHIFT)) & PMU_DPDCTRL_LPOSCEN_MASK)
2521#define PMU_DPDCTRL_LPOSCDPDEN_MASK (0x8U)
2522#define PMU_DPDCTRL_LPOSCDPDEN_SHIFT (3U)
2523/*! LPOSCDPDEN - causes the low-power oscillator to remain running during Deep power-down mode
2524 * provided that bit 2 in this register is set as well. You must set this bit for the self wake-up
2525 * timer to be able to wake up the part from Deep power-down mode. Remark: Do not set this bit
2526 * unless you use the self wake-up timer with the low-power oscillator clock source to wake up from
2527 * Deep power-down mode.
2528 * 0b0..Disabled.
2529 * 0b1..Enabled.
2530 */
2531#define PMU_DPDCTRL_LPOSCDPDEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_LPOSCDPDEN_SHIFT)) & PMU_DPDCTRL_LPOSCDPDEN_MASK)
2532#define PMU_DPDCTRL_GPDATA_MASK (0xFFFFFFF0U)
2533#define PMU_DPDCTRL_GPDATA_SHIFT (4U)
2534/*! GPDATA - Data retained during Deep power-down mode.
2535 */
2536#define PMU_DPDCTRL_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_GPDATA_SHIFT)) & PMU_DPDCTRL_GPDATA_MASK)
2537/*! @} */
2538
2539
2540/*!
2541 * @}
2542 */ /* end of group PMU_Register_Masks */
2543
2544
2545/* PMU - Peripheral instance base addresses */
2546/** Peripheral PMU base address */
2547#define PMU_BASE (0x40020000u)
2548/** Peripheral PMU base pointer */
2549#define PMU ((PMU_Type *)PMU_BASE)
2550/** Array initializer of PMU peripheral base addresses */
2551#define PMU_BASE_ADDRS { PMU_BASE }
2552/** Array initializer of PMU peripheral base pointers */
2553#define PMU_BASE_PTRS { PMU }
2554
2555/*!
2556 * @}
2557 */ /* end of group PMU_Peripheral_Access_Layer */
2558
2559
2560/* ----------------------------------------------------------------------------
2561 -- SCT Peripheral Access Layer
2562 ---------------------------------------------------------------------------- */
2563
2564/*!
2565 * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
2566 * @{
2567 */
2568
2569/** SCT - Register Layout Typedef */
2570typedef struct {
2571 __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */
2572 union { /* offset: 0x4 */
2573 struct { /* offset: 0x4 */
2574 __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */
2575 __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */
2576 } CTRL_ACCESS16BIT;
2577 __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */
2578 };
2579 union { /* offset: 0x8 */
2580 struct { /* offset: 0x8 */
2581 __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */
2582 __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */
2583 } LIMIT_ACCESS16BIT;
2584 __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */
2585 };
2586 union { /* offset: 0xC */
2587 struct { /* offset: 0xC */
2588 __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */
2589 __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */
2590 } HALT_ACCESS16BIT;
2591 __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */
2592 };
2593 union { /* offset: 0x10 */
2594 struct { /* offset: 0x10 */
2595 __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */
2596 __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */
2597 } STOP_ACCESS16BIT;
2598 __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */
2599 };
2600 union { /* offset: 0x14 */
2601 struct { /* offset: 0x14 */
2602 __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */
2603 __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */
2604 } START_ACCESS16BIT;
2605 __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */
2606 };
2607 uint8_t RESERVED_0[40];
2608 union { /* offset: 0x40 */
2609 struct { /* offset: 0x40 */
2610 __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */
2611 __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */
2612 } COUNT_ACCESS16BIT;
2613 __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */
2614 };
2615 union { /* offset: 0x44 */
2616 struct { /* offset: 0x44 */
2617 __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */
2618 __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */
2619 } STATE_ACCESS16BIT;
2620 __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */
2621 };
2622 __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */
2623 union { /* offset: 0x4C */
2624 struct { /* offset: 0x4C */
2625 __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */
2626 __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */
2627 } REGMODE_ACCESS16BIT;
2628 __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */
2629 };
2630 __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */
2631 __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */
2632 __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */
2633 uint8_t RESERVED_1[148];
2634 __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */
2635 __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */
2636 __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */
2637 __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */
2638 union { /* offset: 0x100 */
2639 union { /* offset: 0x100, array step: 0x4 */
2640 struct { /* offset: 0x100, array step: 0x4 */
2641 __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */
2642 __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */
2643 } CAP_ACCESS16BIT[5];
2644 __IO uint32_t CAP[5]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */
2645 };
2646 union { /* offset: 0x100, array step: 0x4 */
2647 struct { /* offset: 0x100, array step: 0x4 */
2648 __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */
2649 __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */
2650 } MATCH_ACCESS16BIT[5];
2651 __IO uint32_t MATCH[5]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */
2652 };
2653 };
2654 uint8_t RESERVED_2[236];
2655 union { /* offset: 0x200 */
2656 union { /* offset: 0x200, array step: 0x4 */
2657 struct { /* offset: 0x200, array step: 0x4 */
2658 __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */
2659 __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */
2660 } CAPCTRL_ACCESS16BIT[5];
2661 __IO uint32_t CAPCTRL[5]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */
2662 };
2663 union { /* offset: 0x200, array step: 0x4 */
2664 struct { /* offset: 0x200, array step: 0x4 */
2665 __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */
2666 __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */
2667 } MATCHREL_ACCESS16BIT[5];
2668 __IO uint32_t MATCHREL[5]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */
2669 };
2670 };
2671 uint8_t RESERVED_3[236];
2672 struct { /* offset: 0x300, array step: 0x8 */
2673 __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */
2674 __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */
2675 } EV[6];
2676 uint8_t RESERVED_4[464];
2677 struct { /* offset: 0x500, array step: 0x8 */
2678 __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */
2679 __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */
2680 } OUT[4];
2681} SCT_Type;
2682
2683/* ----------------------------------------------------------------------------
2684 -- SCT Register Masks
2685 ---------------------------------------------------------------------------- */
2686
2687/*!
2688 * @addtogroup SCT_Register_Masks SCT Register Masks
2689 * @{
2690 */
2691
2692/*! @name CONFIG - SCT configuration register */
2693/*! @{ */
2694#define SCT_CONFIG_UNIFY_MASK (0x1U)
2695#define SCT_CONFIG_UNIFY_SHIFT (0U)
2696/*! UNIFY - SCT operation
2697 * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.
2698 * 0b1..The SCT operates as a unified 32-bit counter.
2699 */
2700#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
2701#define SCT_CONFIG_CLKMODE_MASK (0x6U)
2702#define SCT_CONFIG_CLKMODE_SHIFT (1U)
2703/*! CLKMODE - SCT clock mode
2704 * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers.
2705 * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are
2706 * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The
2707 * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the
2708 * high-performance, sampled-clock mode.
2709 * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the
2710 * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the
2711 * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.
2712 * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL
2713 * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system
2714 * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than
2715 * the system clock.
2716 */
2717#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
2718#define SCT_CONFIG_CKSEL_MASK (0x78U)
2719#define SCT_CONFIG_CKSEL_SHIFT (3U)
2720/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent
2721 * on the CLKMODE bit selection in this register.
2722 * 0b0000..Rising edges on input 0.
2723 * 0b0001..Falling edges on input 0.
2724 * 0b0010..Rising edges on input 1.
2725 * 0b0011..Falling edges on input 1.
2726 * 0b0100..Rising edges on input 2.
2727 * 0b0101..Falling edges on input 2.
2728 * 0b0110..Rising edges on input 3.
2729 * 0b0111..Falling edges on input 3.
2730 */
2731#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
2732#define SCT_CONFIG_NORELOAD_L_MASK (0x80U)
2733#define SCT_CONFIG_NORELOAD_L_SHIFT (7U)
2734/*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their
2735 * respective reload registers. Setting this bit eliminates the need to write to the reload
2736 * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any
2737 * time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
2738 */
2739#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK)
2740#define SCT_CONFIG_NORELOAD_H_MASK (0x100U)
2741#define SCT_CONFIG_NORELOAD_H_SHIFT (8U)
2742/*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their
2743 * respective reload registers. Setting this bit eliminates the need to write to the reload
2744 * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at
2745 * any time. This bit is not used when the UNIFY bit is set.
2746 */
2747#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
2748#define SCT_CONFIG_INSYNC_MASK (0x1FE00U)
2749#define SCT_CONFIG_INSYNC_SHIFT (9U)
2750/*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all
2751 * other bits are reserved. A 1 in one of these bits subjects the corresponding input to
2752 * synchronization to the SCT clock, before it is used to create an event. If an input is known to
2753 * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note:
2754 * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input
2755 * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation.
2756 * It does not apply to the clock input specified in the CKSEL field.
2757 */
2758#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
2759#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U)
2760#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U)
2761/*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto
2762 * LIMIT condition without the need to define an associated event. As with any LIMIT event, this
2763 * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change
2764 * the direction of count in bi-directional mode. Software can write to set or clear this bit at
2765 * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
2766 */
2767#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
2768#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U)
2769#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U)
2770/*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a
2771 * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event,
2772 * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to
2773 * change the direction of count in bi-directional mode. Software can write to set or clear this bit
2774 * at any time. This bit is not used when the UNIFY bit is set.
2775 */
2776#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
2777/*! @} */
2778
2779/*! @name CTRLL - SCT_CTRLL register */
2780/*! @{ */
2781#define SCT_CTRLL_DOWN_L_MASK (0x1U)
2782#define SCT_CTRLL_DOWN_L_SHIFT (0U)
2783/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit
2784 * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit
2785 * when the counter is counting down and a limit condition occurs or when the counter reaches 0.
2786 */
2787#define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK)
2788#define SCT_CTRLL_STOP_L_MASK (0x2U)
2789#define SCT_CTRLL_STOP_L_SHIFT (1U)
2790/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events
2791 * related to the counter can occur. If a designated start event occurs, this bit is cleared and
2792 * counting resumes.
2793 */
2794#define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK)
2795#define SCT_CTRLL_HALT_L_MASK (0x4U)
2796#define SCT_CTRLL_HALT_L_SHIFT (2U)
2797/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A
2798 * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to
2799 * remove the halt condition while keeping the SCT in the stop condition (not running) with a
2800 * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set,
2801 * only software can clear this bit to restore counter operation. This bit is set on reset.
2802 */
2803#define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK)
2804#define SCT_CTRLL_CLRCTR_L_MASK (0x8U)
2805#define SCT_CTRLL_CLRCTR_L_SHIFT (3U)
2806/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
2807 */
2808#define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK)
2809#define SCT_CTRLL_BIDIR_L_MASK (0x10U)
2810#define SCT_CTRLL_BIDIR_L_SHIFT (4U)
2811/*! BIDIR_L - L or unified counter direction select
2812 * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
2813 * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
2814 */
2815#define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK)
2816#define SCT_CTRLL_PRE_L_MASK (0x1FE0U)
2817#define SCT_CTRLL_PRE_L_SHIFT (5U)
2818/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified
2819 * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1.
2820 * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
2821 */
2822#define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK)
2823/*! @} */
2824
2825/*! @name CTRLH - SCT_CTRLH register */
2826/*! @{ */
2827#define SCT_CTRLH_DOWN_H_MASK (0x1U)
2828#define SCT_CTRLH_DOWN_H_SHIFT (0U)
2829/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the
2830 * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit
2831 * when the counter is counting down and a limit condition occurs or when the counter reaches 0.
2832 */
2833#define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK)
2834#define SCT_CTRLH_STOP_H_MASK (0x2U)
2835#define SCT_CTRLH_STOP_H_SHIFT (1U)
2836/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to
2837 * the counter can occur. If such an event matches the mask in the Start register, this bit is
2838 * cleared and counting resumes.
2839 */
2840#define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK)
2841#define SCT_CTRLH_HALT_H_MASK (0x4U)
2842#define SCT_CTRLH_HALT_H_SHIFT (2U)
2843/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets
2844 * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the
2845 * halt condition while keeping the SCT in the stop condition (not running) with a single write to
2846 * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit
2847 * can only be cleared by software to restore counter operation. This bit is set on reset.
2848 */
2849#define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK)
2850#define SCT_CTRLH_CLRCTR_H_MASK (0x8U)
2851#define SCT_CTRLH_CLRCTR_H_SHIFT (3U)
2852/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0.
2853 */
2854#define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK)
2855#define SCT_CTRLH_BIDIR_H_MASK (0x10U)
2856#define SCT_CTRLH_BIDIR_H_SHIFT (4U)
2857/*! BIDIR_H - Direction select
2858 * 0b0..The H counter counts up to its limit condition, then is cleared to zero.
2859 * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0.
2860 */
2861#define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK)
2862#define SCT_CTRLH_PRE_H_MASK (0x1FE0U)
2863#define SCT_CTRLH_PRE_H_SHIFT (5U)
2864/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock.
2865 * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the
2866 * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
2867 */
2868#define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK)
2869/*! @} */
2870
2871/*! @name CTRL - SCT control register */
2872/*! @{ */
2873#define SCT_CTRL_DOWN_L_MASK (0x1U)
2874#define SCT_CTRL_DOWN_L_SHIFT (0U)
2875/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit
2876 * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit
2877 * when the counter is counting down and a limit condition occurs or when the counter reaches 0.
2878 */
2879#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
2880#define SCT_CTRL_STOP_L_MASK (0x2U)
2881#define SCT_CTRL_STOP_L_SHIFT (1U)
2882/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events
2883 * related to the counter can occur. If a designated start event occurs, this bit is cleared and
2884 * counting resumes.
2885 */
2886#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
2887#define SCT_CTRL_HALT_L_MASK (0x4U)
2888#define SCT_CTRL_HALT_L_SHIFT (2U)
2889/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A
2890 * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to
2891 * remove the halt condition while keeping the SCT in the stop condition (not running) with a
2892 * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set,
2893 * only software can clear this bit to restore counter operation. This bit is set on reset.
2894 */
2895#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
2896#define SCT_CTRL_CLRCTR_L_MASK (0x8U)
2897#define SCT_CTRL_CLRCTR_L_SHIFT (3U)
2898/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
2899 */
2900#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
2901#define SCT_CTRL_BIDIR_L_MASK (0x10U)
2902#define SCT_CTRL_BIDIR_L_SHIFT (4U)
2903/*! BIDIR_L - L or unified counter direction select
2904 * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
2905 * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
2906 */
2907#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
2908#define SCT_CTRL_PRE_L_MASK (0x1FE0U)
2909#define SCT_CTRL_PRE_L_SHIFT (5U)
2910/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified
2911 * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1.
2912 * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
2913 */
2914#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
2915#define SCT_CTRL_DOWN_H_MASK (0x10000U)
2916#define SCT_CTRL_DOWN_H_SHIFT (16U)
2917/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the
2918 * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit
2919 * when the counter is counting down and a limit condition occurs or when the counter reaches 0.
2920 */
2921#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
2922#define SCT_CTRL_STOP_H_MASK (0x20000U)
2923#define SCT_CTRL_STOP_H_SHIFT (17U)
2924/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to
2925 * the counter can occur. If such an event matches the mask in the Start register, this bit is
2926 * cleared and counting resumes.
2927 */
2928#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
2929#define SCT_CTRL_HALT_H_MASK (0x40000U)
2930#define SCT_CTRL_HALT_H_SHIFT (18U)
2931/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets
2932 * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the
2933 * halt condition while keeping the SCT in the stop condition (not running) with a single write to
2934 * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit
2935 * can only be cleared by software to restore counter operation. This bit is set on reset.
2936 */
2937#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
2938#define SCT_CTRL_CLRCTR_H_MASK (0x80000U)
2939#define SCT_CTRL_CLRCTR_H_SHIFT (19U)
2940/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0.
2941 */
2942#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
2943#define SCT_CTRL_BIDIR_H_MASK (0x100000U)
2944#define SCT_CTRL_BIDIR_H_SHIFT (20U)
2945/*! BIDIR_H - Direction select
2946 * 0b0..The H counter counts up to its limit condition, then is cleared to zero.
2947 * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0.
2948 */
2949#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
2950#define SCT_CTRL_PRE_H_MASK (0x1FE00000U)
2951#define SCT_CTRL_PRE_H_SHIFT (21U)
2952/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock.
2953 * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the
2954 * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
2955 */
2956#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
2957/*! @} */
2958
2959/*! @name LIMITL - SCT_LIMITL register */
2960/*! @{ */
2961#define SCT_LIMITL_LIMITL_MASK (0xFFFFU)
2962#define SCT_LIMITL_LIMITL_SHIFT (0U)
2963#define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK)
2964/*! @} */
2965
2966/*! @name LIMITH - SCT_LIMITH register */
2967/*! @{ */
2968#define SCT_LIMITH_LIMITH_MASK (0xFFFFU)
2969#define SCT_LIMITH_LIMITH_SHIFT (0U)
2970#define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK)
2971/*! @} */
2972
2973/*! @name LIMIT - SCT limit event select register */
2974/*! @{ */
2975#define SCT_LIMIT_LIMMSK_L_MASK (0x3FU)
2976#define SCT_LIMIT_LIMMSK_L_SHIFT (0U)
2977/*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter
2978 * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
2979 */
2980#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
2981#define SCT_LIMIT_LIMMSK_H_MASK (0x3F0000U)
2982#define SCT_LIMIT_LIMMSK_H_SHIFT (16U)
2983/*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit
2984 * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
2985 */
2986#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
2987/*! @} */
2988
2989/*! @name HALTL - SCT_HALTL register */
2990/*! @{ */
2991#define SCT_HALTL_HALTL_MASK (0xFFFFU)
2992#define SCT_HALTL_HALTL_SHIFT (0U)
2993#define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK)
2994/*! @} */
2995
2996/*! @name HALTH - SCT_HALTH register */
2997/*! @{ */
2998#define SCT_HALTH_HALTH_MASK (0xFFFFU)
2999#define SCT_HALTH_HALTH_SHIFT (0U)
3000#define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK)
3001/*! @} */
3002
3003/*! @name HALT - SCT halt event select register */
3004/*! @{ */
3005#define SCT_HALT_HALTMSK_L_MASK (0x3FU)
3006#define SCT_HALT_HALTMSK_L_SHIFT (0U)
3007/*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0,
3008 * event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
3009 */
3010#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
3011#define SCT_HALT_HALTMSK_H_MASK (0x3F0000U)
3012#define SCT_HALT_HALTMSK_H_SHIFT (16U)
3013/*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16,
3014 * event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
3015 */
3016#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
3017/*! @} */
3018
3019/*! @name STOPL - SCT_STOPL register */
3020/*! @{ */
3021#define SCT_STOPL_STOPL_MASK (0xFFFFU)
3022#define SCT_STOPL_STOPL_SHIFT (0U)
3023#define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK)
3024/*! @} */
3025
3026/*! @name STOPH - SCT_STOPH register */
3027/*! @{ */
3028#define SCT_STOPH_STOPH_MASK (0xFFFFU)
3029#define SCT_STOPH_STOPH_SHIFT (0U)
3030#define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK)
3031/*! @} */
3032
3033/*! @name STOP - SCT stop event select register */
3034/*! @{ */
3035#define SCT_STOP_STOPMSK_L_MASK (0x3FU)
3036#define SCT_STOP_STOPMSK_L_SHIFT (0U)
3037/*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0,
3038 * event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
3039 */
3040#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
3041#define SCT_STOP_STOPMSK_H_MASK (0x3F0000U)
3042#define SCT_STOP_STOPMSK_H_SHIFT (16U)
3043/*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16,
3044 * event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
3045 */
3046#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
3047/*! @} */
3048
3049/*! @name STARTL - SCT_STARTL register */
3050/*! @{ */
3051#define SCT_STARTL_STARTL_MASK (0xFFFFU)
3052#define SCT_STARTL_STARTL_SHIFT (0U)
3053#define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK)
3054/*! @} */
3055
3056/*! @name STARTH - SCT_STARTH register */
3057/*! @{ */
3058#define SCT_STARTH_STARTH_MASK (0xFFFFU)
3059#define SCT_STARTH_STARTH_SHIFT (0U)
3060#define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK)
3061/*! @} */
3062
3063/*! @name START - SCT start event select register */
3064/*! @{ */
3065#define SCT_START_STARTMSK_L_MASK (0x3FU)
3066#define SCT_START_STARTMSK_L_SHIFT (0U)
3067/*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit
3068 * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
3069 */
3070#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
3071#define SCT_START_STARTMSK_H_MASK (0x3F0000U)
3072#define SCT_START_STARTMSK_H_SHIFT (16U)
3073/*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit
3074 * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
3075 */
3076#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
3077/*! @} */
3078
3079/*! @name COUNTL - SCT_COUNTL register */
3080/*! @{ */
3081#define SCT_COUNTL_COUNTL_MASK (0xFFFFU)
3082#define SCT_COUNTL_COUNTL_SHIFT (0U)
3083#define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK)
3084/*! @} */
3085
3086/*! @name COUNTH - SCT_COUNTH register */
3087/*! @{ */
3088#define SCT_COUNTH_COUNTH_MASK (0xFFFFU)
3089#define SCT_COUNTH_COUNTH_SHIFT (0U)
3090#define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK)
3091/*! @} */
3092
3093/*! @name COUNT - SCT counter register */
3094/*! @{ */
3095#define SCT_COUNT_CTR_L_MASK (0xFFFFU)
3096#define SCT_COUNT_CTR_L_SHIFT (0U)
3097/*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write
3098 * the lower 16 bits of the 32-bit unified counter.
3099 */
3100#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
3101#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U)
3102#define SCT_COUNT_CTR_H_SHIFT (16U)
3103/*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write
3104 * the upper 16 bits of the 32-bit unified counter.
3105 */
3106#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
3107/*! @} */
3108
3109/*! @name STATEL - SCT_STATEL register */
3110/*! @{ */
3111#define SCT_STATEL_STATEL_MASK (0xFFFFU)
3112#define SCT_STATEL_STATEL_SHIFT (0U)
3113#define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK)
3114/*! @} */
3115
3116/*! @name STATEH - SCT_STATEH register */
3117/*! @{ */
3118#define SCT_STATEH_STATEH_MASK (0xFFFFU)
3119#define SCT_STATEH_STATEH_SHIFT (0U)
3120#define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK)
3121/*! @} */
3122
3123/*! @name STATE - SCT state register */
3124/*! @{ */
3125#define SCT_STATE_STATE_L_MASK (0x1FU)
3126#define SCT_STATE_STATE_L_SHIFT (0U)
3127/*! STATE_L - State variable.
3128 */
3129#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
3130#define SCT_STATE_STATE_H_MASK (0x1F0000U)
3131#define SCT_STATE_STATE_H_SHIFT (16U)
3132/*! STATE_H - State variable.
3133 */
3134#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
3135/*! @} */
3136
3137/*! @name INPUT - SCT input register */
3138/*! @{ */
3139#define SCT_INPUT_AIN0_MASK (0x1U)
3140#define SCT_INPUT_AIN0_SHIFT (0U)
3141/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge.
3142 */
3143#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
3144#define SCT_INPUT_AIN1_MASK (0x2U)
3145#define SCT_INPUT_AIN1_SHIFT (1U)
3146/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge.
3147 */
3148#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
3149#define SCT_INPUT_AIN2_MASK (0x4U)
3150#define SCT_INPUT_AIN2_SHIFT (2U)
3151/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge.
3152 */
3153#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
3154#define SCT_INPUT_AIN3_MASK (0x8U)
3155#define SCT_INPUT_AIN3_SHIFT (3U)
3156/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge.
3157 */
3158#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
3159#define SCT_INPUT_SIN0_MASK (0x10000U)
3160#define SCT_INPUT_SIN0_SHIFT (16U)
3161/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC.
3162 */
3163#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
3164#define SCT_INPUT_SIN1_MASK (0x20000U)
3165#define SCT_INPUT_SIN1_SHIFT (17U)
3166/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC.
3167 */
3168#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
3169#define SCT_INPUT_SIN2_MASK (0x40000U)
3170#define SCT_INPUT_SIN2_SHIFT (18U)
3171/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC.
3172 */
3173#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
3174#define SCT_INPUT_SIN3_MASK (0x80000U)
3175#define SCT_INPUT_SIN3_SHIFT (19U)
3176/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC.
3177 */
3178#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
3179/*! @} */
3180
3181/*! @name REGMODEL - SCT_REGMODEL register */
3182/*! @{ */
3183#define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU)
3184#define SCT_REGMODEL_REGMODEL_SHIFT (0U)
3185#define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK)
3186/*! @} */
3187
3188/*! @name REGMODEH - SCT_REGMODEH register */
3189/*! @{ */
3190#define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU)
3191#define SCT_REGMODEH_REGMODEH_SHIFT (0U)
3192#define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK)
3193/*! @} */
3194
3195/*! @name REGMODE - SCT match/capture mode register */
3196/*! @{ */
3197#define SCT_REGMODE_REGMOD_L_MASK (0x1FU)
3198#define SCT_REGMODE_REGMOD_L_SHIFT (0U)
3199/*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1,
3200 * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as
3201 * match register. 1 = register operates as capture register.
3202 */
3203#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
3204#define SCT_REGMODE_REGMOD_H_MASK (0x1F0000U)
3205#define SCT_REGMODE_REGMOD_H_SHIFT (16U)
3206/*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit
3207 * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as
3208 * match registers. 1 = register operates as capture registers.
3209 */
3210#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
3211/*! @} */
3212
3213/*! @name OUTPUT - SCT output register */
3214/*! @{ */
3215#define SCT_OUTPUT_OUT_MASK (0xFU)
3216#define SCT_OUTPUT_OUT_SHIFT (0U)
3217/*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the
3218 * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of
3219 * outputs in this SCT.
3220 */
3221#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)
3222/*! @} */
3223
3224/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */
3225/*! @{ */
3226#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U)
3227#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U)
3228/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
3229 * 0b00..Set and clear do not depend on the direction of any counter.
3230 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
3231 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
3232 */
3233#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
3234#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU)
3235#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U)
3236/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.
3237 * 0b00..Set and clear do not depend on the direction of any counter.
3238 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
3239 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
3240 */
3241#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
3242#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U)
3243#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U)
3244/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.
3245 * 0b00..Set and clear do not depend on the direction of any counter.
3246 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
3247 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
3248 */
3249#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
3250#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U)
3251#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U)
3252/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.
3253 * 0b00..Set and clear do not depend on the direction of any counter.
3254 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
3255 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
3256 */
3257#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
3258/*! @} */
3259
3260/*! @name RES - SCT conflict resolution register */
3261/*! @{ */
3262#define SCT_RES_O0RES_MASK (0x3U)
3263#define SCT_RES_O0RES_SHIFT (0U)
3264/*! O0RES - Effect of simultaneous set and clear on output 0.
3265 * 0b00..No change.
3266 * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register).
3267 * 0b10..Clear output (or set based on the SETCLR0 field).
3268 * 0b11..Toggle output.
3269 */
3270#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
3271#define SCT_RES_O1RES_MASK (0xCU)
3272#define SCT_RES_O1RES_SHIFT (2U)
3273/*! O1RES - Effect of simultaneous set and clear on output 1.
3274 * 0b00..No change.
3275 * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register).
3276 * 0b10..Clear output (or set based on the SETCLR1 field).
3277 * 0b11..Toggle output.
3278 */
3279#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
3280#define SCT_RES_O2RES_MASK (0x30U)
3281#define SCT_RES_O2RES_SHIFT (4U)
3282/*! O2RES - Effect of simultaneous set and clear on output 2.
3283 * 0b00..No change.
3284 * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register).
3285 * 0b10..Clear output n (or set based on the SETCLR2 field).
3286 * 0b11..Toggle output.
3287 */
3288#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
3289#define SCT_RES_O3RES_MASK (0xC0U)
3290#define SCT_RES_O3RES_SHIFT (6U)
3291/*! O3RES - Effect of simultaneous set and clear on output 3.
3292 * 0b00..No change.
3293 * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register).
3294 * 0b10..Clear output (or set based on the SETCLR3 field).
3295 * 0b11..Toggle output.
3296 */
3297#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
3298/*! @} */
3299
3300/*! @name EVEN - SCT event interrupt enable register */
3301/*! @{ */
3302#define SCT_EVEN_IEN_MASK (0x3FU)
3303#define SCT_EVEN_IEN_SHIFT (0U)
3304/*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are
3305 * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in
3306 * this SCT.
3307 */
3308#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)
3309/*! @} */
3310
3311/*! @name EVFLAG - SCT event flag register */
3312/*! @{ */
3313#define SCT_EVFLAG_FLAG_MASK (0x3FU)
3314#define SCT_EVFLAG_FLAG_SHIFT (0U)
3315/*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit
3316 * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
3317 */
3318#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)
3319/*! @} */
3320
3321/*! @name CONEN - SCT conflict interrupt enable register */
3322/*! @{ */
3323#define SCT_CONEN_NCEN_MASK (0xFU)
3324#define SCT_CONEN_NCEN_SHIFT (0U)
3325/*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag
3326 * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of
3327 * outputs in this SCT.
3328 */
3329#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)
3330/*! @} */
3331
3332/*! @name CONFLAG - SCT conflict flag register */
3333/*! @{ */
3334#define SCT_CONFLAG_NCFLAG_MASK (0xFU)
3335#define SCT_CONFLAG_NCFLAG_SHIFT (0U)
3336/*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was
3337 * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits =
3338 * number of outputs in this SCT.
3339 */
3340#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)
3341#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U)
3342#define SCT_CONFLAG_BUSERRL_SHIFT (30U)
3343/*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE
3344 * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write
3345 * to certain L and H registers can be half successful and half unsuccessful.
3346 */
3347#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
3348#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U)
3349#define SCT_CONFLAG_BUSERRH_SHIFT (31U)
3350/*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or
3351 * the Output register when the H counter was not halted.
3352 */
3353#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
3354/*! @} */
3355
3356/*! @name CAPL - SCT_CAPL register */
3357/*! @{ */
3358#define SCT_CAPL_CAPL_MASK (0xFFFFU)
3359#define SCT_CAPL_CAPL_SHIFT (0U)
3360#define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK)
3361/*! @} */
3362
3363/* The count of SCT_CAPL */
3364#define SCT_CAPL_COUNT (5U)
3365
3366/*! @name CAPH - SCT_CAPH register */
3367/*! @{ */
3368#define SCT_CAPH_CAPH_MASK (0xFFFFU)
3369#define SCT_CAPH_CAPH_SHIFT (0U)
3370#define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK)
3371/*! @} */
3372
3373/* The count of SCT_CAPH */
3374#define SCT_CAPH_COUNT (5U)
3375
3376/*! @name CAP - SCT capture register of capture channel */
3377/*! @{ */
3378#define SCT_CAP_CAPn_L_MASK (0xFFFFU)
3379#define SCT_CAP_CAPn_L_SHIFT (0U)
3380/*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured.
3381 * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last
3382 * captured.
3383 */
3384#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK)
3385#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U)
3386#define SCT_CAP_CAPn_H_SHIFT (16U)
3387/*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured.
3388 * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last
3389 * captured.
3390 */
3391#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK)
3392/*! @} */
3393
3394/* The count of SCT_CAP */
3395#define SCT_CAP_COUNT (5U)
3396
3397/*! @name MATCHL - SCT_MATCHL register */
3398/*! @{ */
3399#define SCT_MATCHL_MATCHL_MASK (0xFFFFU)
3400#define SCT_MATCHL_MATCHL_SHIFT (0U)
3401#define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK)
3402/*! @} */
3403
3404/* The count of SCT_MATCHL */
3405#define SCT_MATCHL_COUNT (5U)
3406
3407/*! @name MATCHH - SCT_MATCHH register */
3408/*! @{ */
3409#define SCT_MATCHH_MATCHH_MASK (0xFFFFU)
3410#define SCT_MATCHH_MATCHH_SHIFT (0U)
3411#define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK)
3412/*! @} */
3413
3414/* The count of SCT_MATCHH */
3415#define SCT_MATCHH_COUNT (5U)
3416
3417/*! @name MATCH - SCT match value register of match channels */
3418/*! @{ */
3419#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU)
3420#define SCT_MATCH_MATCHn_L_SHIFT (0U)
3421/*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When
3422 * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified
3423 * counter.
3424 */
3425#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK)
3426#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U)
3427#define SCT_MATCH_MATCHn_H_SHIFT (16U)
3428/*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When
3429 * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified
3430 * counter.
3431 */
3432#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK)
3433/*! @} */
3434
3435/* The count of SCT_MATCH */
3436#define SCT_MATCH_COUNT (5U)
3437
3438/*! @name CAPCTRLL - SCT_CAPCTRLL register */
3439/*! @{ */
3440#define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU)
3441#define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U)
3442#define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK)
3443/*! @} */
3444
3445/* The count of SCT_CAPCTRLL */
3446#define SCT_CAPCTRLL_COUNT (5U)
3447
3448/*! @name CAPCTRLH - SCT_CAPCTRLH register */
3449/*! @{ */
3450#define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU)
3451#define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U)
3452#define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK)
3453/*! @} */
3454
3455/* The count of SCT_CAPCTRLH */
3456#define SCT_CAPCTRLH_COUNT (5U)
3457
3458/*! @name CAPCTRL - SCT capture control register */
3459/*! @{ */
3460#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU)
3461#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U)
3462/*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1)
3463 * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of
3464 * match/captures in this SCT.
3465 */
3466#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK)
3467#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U)
3468#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U)
3469/*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event
3470 * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
3471 */
3472#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK)
3473/*! @} */
3474
3475/* The count of SCT_CAPCTRL */
3476#define SCT_CAPCTRL_COUNT (5U)
3477
3478/*! @name MATCHRELL - SCT_MATCHRELL register */
3479/*! @{ */
3480#define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU)
3481#define SCT_MATCHRELL_MATCHRELL_SHIFT (0U)
3482#define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK)
3483/*! @} */
3484
3485/* The count of SCT_MATCHRELL */
3486#define SCT_MATCHRELL_COUNT (5U)
3487
3488/*! @name MATCHRELH - SCT_MATCHRELH register */
3489/*! @{ */
3490#define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU)
3491#define SCT_MATCHRELH_MATCHRELH_SHIFT (0U)
3492#define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK)
3493/*! @} */
3494
3495/* The count of SCT_MATCHRELH */
3496#define SCT_MATCHRELH_COUNT (5U)
3497
3498/*! @name MATCHREL - SCT match reload value register */
3499/*! @{ */
3500#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU)
3501#define SCT_MATCHREL_RELOADn_L_SHIFT (0U)
3502/*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register.
3503 * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn
3504 * register.
3505 */
3506#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK)
3507#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U)
3508#define SCT_MATCHREL_RELOADn_H_SHIFT (16U)
3509/*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When
3510 * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn
3511 * register.
3512 */
3513#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK)
3514/*! @} */
3515
3516/* The count of SCT_MATCHREL */
3517#define SCT_MATCHREL_COUNT (5U)
3518
3519/*! @name EV_STATE - SCT event state register 0 */
3520/*! @{ */
3521#define SCT_EV_STATE_STATEMSK0_MASK (0x1U)
3522#define SCT_EV_STATE_STATEMSK0_SHIFT (0U)
3523/*! STATEMSK0 - If bit m is one, event n happens in state m of the counter selected by the HEVENT
3524 * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of
3525 * bits = number of states in this SCT.
3526 */
3527#define SCT_EV_STATE_STATEMSK0(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSK0_SHIFT)) & SCT_EV_STATE_STATEMSK0_MASK)
3528#define SCT_EV_STATE_STATEMSK1_MASK (0x2U)
3529#define SCT_EV_STATE_STATEMSK1_SHIFT (1U)
3530/*! STATEMSK1 - If bit m is one, event n happens in state m of the counter selected by the HEVENT
3531 * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of
3532 * bits = number of states in this SCT.
3533 */
3534#define SCT_EV_STATE_STATEMSK1(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSK1_SHIFT)) & SCT_EV_STATE_STATEMSK1_MASK)
3535/*! @} */
3536
3537/* The count of SCT_EV_STATE */
3538#define SCT_EV_STATE_COUNT (6U)
3539
3540/*! @name EV_CTRL - SCT event control register 0 */
3541/*! @{ */
3542#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU)
3543#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U)
3544/*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur
3545 * only when the counter selected by the HEVENT bit is running.
3546 */
3547#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK)
3548#define SCT_EV_CTRL_HEVENT_MASK (0x10U)
3549#define SCT_EV_CTRL_HEVENT_SHIFT (4U)
3550/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1.
3551 * 0b0..Selects the L state and the L match register selected by MATCHSEL.
3552 * 0b1..Selects the H state and the H match register selected by MATCHSEL.
3553 */
3554#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK)
3555#define SCT_EV_CTRL_OUTSEL_MASK (0x20U)
3556#define SCT_EV_CTRL_OUTSEL_SHIFT (5U)
3557/*! OUTSEL - Input/output select
3558 * 0b0..Selects the inputs selected by IOSEL.
3559 * 0b1..Selects the outputs selected by IOSEL.
3560 */
3561#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK)
3562#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U)
3563#define SCT_EV_CTRL_IOSEL_SHIFT (6U)
3564/*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not
3565 * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit
3566 * ingredient of every event.
3567 */
3568#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK)
3569#define SCT_EV_CTRL_IOCOND_MASK (0xC00U)
3570#define SCT_EV_CTRL_IOCOND_SHIFT (10U)
3571/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the
3572 * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state
3573 * detection, an input must have a minimum pulse width of at least one SCT clock period .
3574 * 0b00..LOW
3575 * 0b01..Rise
3576 * 0b10..Fall
3577 * 0b11..HIGH
3578 */
3579#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK)
3580#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U)
3581#define SCT_EV_CTRL_COMBMODE_SHIFT (12U)
3582/*! COMBMODE - Selects how the specified match and I/O condition are used and combined.
3583 * 0b00..OR. The event occurs when either the specified match or I/O condition occurs.
3584 * 0b01..MATCH. Uses the specified match only.
3585 * 0b10..IO. Uses the specified I/O condition only.
3586 * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously.
3587 */
3588#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK)
3589#define SCT_EV_CTRL_STATELD_MASK (0x4000U)
3590#define SCT_EV_CTRL_STATELD_SHIFT (14U)
3591/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this
3592 * event is the highest-numbered event occurring for that state.
3593 * 0b0..STATEV value is added into STATE (the carry-out is ignored).
3594 * 0b1..STATEV value is loaded into STATE.
3595 */
3596#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK)
3597#define SCT_EV_CTRL_STATEV_MASK (0xF8000U)
3598#define SCT_EV_CTRL_STATEV_SHIFT (15U)
3599/*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on
3600 * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and
3601 * STATEV are both zero, there is no change to the STATE value.
3602 */
3603#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK)
3604#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U)
3605#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U)
3606/*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the
3607 * triggering of this event, then a match is considered to be active whenever the counter value is
3608 * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR
3609 * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active
3610 * during the cycle when the counter is equal to the match value.
3611 */
3612#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK)
3613#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U)
3614#define SCT_EV_CTRL_DIRECTION_SHIFT (21U)
3615/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters
3616 * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
3617 * 0b00..Direction independent. This event is triggered regardless of the count direction.
3618 * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1.
3619 * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1.
3620 */
3621#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK)
3622/*! @} */
3623
3624/* The count of SCT_EV_CTRL */
3625#define SCT_EV_CTRL_COUNT (6U)
3626
3627/*! @name OUT_SET - SCT output 0 set register */
3628/*! @{ */
3629#define SCT_OUT_SET_SET_MASK (0x3FU)
3630#define SCT_OUT_SET_SET_SHIFT (0U)
3631/*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output
3632 * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the
3633 * counter is used in bi-directional mode, it is possible to reverse the action specified by the
3634 * output set and clear registers when counting down, See the OUTPUTCTRL register.
3635 */
3636#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
3637/*! @} */
3638
3639/* The count of SCT_OUT_SET */
3640#define SCT_OUT_SET_COUNT (4U)
3641
3642/*! @name OUT_CLR - SCT output 0 clear register */
3643/*! @{ */
3644#define SCT_OUT_CLR_CLR_MASK (0x3FU)
3645#define SCT_OUT_CLR_CLR_SHIFT (0U)
3646/*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0
3647 * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the
3648 * counter is used in bi-directional mode, it is possible to reverse the action specified by the
3649 * output set and clear registers when counting down, See the OUTPUTCTRL register.
3650 */
3651#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
3652/*! @} */
3653
3654/* The count of SCT_OUT_CLR */
3655#define SCT_OUT_CLR_COUNT (4U)
3656
3657
3658/*!
3659 * @}
3660 */ /* end of group SCT_Register_Masks */
3661
3662
3663/* SCT - Peripheral instance base addresses */
3664/** Peripheral SCT0 base address */
3665#define SCT0_BASE (0x50004000u)
3666/** Peripheral SCT0 base pointer */
3667#define SCT0 ((SCT_Type *)SCT0_BASE)
3668/** Array initializer of SCT peripheral base addresses */
3669#define SCT_BASE_ADDRS { SCT0_BASE }
3670/** Array initializer of SCT peripheral base pointers */
3671#define SCT_BASE_PTRS { SCT0 }
3672/** Interrupt vectors for the SCT peripheral type */
3673#define SCT_IRQS { SCT0_IRQn }
3674
3675/*!
3676 * @}
3677 */ /* end of group SCT_Peripheral_Access_Layer */
3678
3679
3680/* ----------------------------------------------------------------------------
3681 -- SPI Peripheral Access Layer
3682 ---------------------------------------------------------------------------- */
3683
3684/*!
3685 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
3686 * @{
3687 */
3688
3689/** SPI - Register Layout Typedef */
3690typedef struct {
3691 __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x0 */
3692 __IO uint32_t DLY; /**< SPI Delay register, offset: 0x4 */
3693 __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position, offset: 0x8 */
3694 __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */
3695 __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x10 */
3696 __I uint32_t RXDAT; /**< SPI Receive Data, offset: 0x14 */
3697 __IO uint32_t TXDATCTL; /**< SPI Transmit Data with Control, offset: 0x18 */
3698 __IO uint32_t TXDAT; /**< SPI Transmit Data., offset: 0x1C */
3699 __IO uint32_t TXCTL; /**< SPI Transmit Control, offset: 0x20 */
3700 __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x24 */
3701 __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x28 */
3702} SPI_Type;
3703
3704/* ----------------------------------------------------------------------------
3705 -- SPI Register Masks
3706 ---------------------------------------------------------------------------- */
3707
3708/*!
3709 * @addtogroup SPI_Register_Masks SPI Register Masks
3710 * @{
3711 */
3712
3713/*! @name CFG - SPI Configuration register */
3714/*! @{ */
3715#define SPI_CFG_ENABLE_MASK (0x1U)
3716#define SPI_CFG_ENABLE_SHIFT (0U)
3717/*! ENABLE - SPI enable.
3718 * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset.
3719 * 0b1..Enabled. The SPI is enabled for operation.
3720 */
3721#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
3722#define SPI_CFG_MASTER_MASK (0x4U)
3723#define SPI_CFG_MASTER_SHIFT (2U)
3724/*! MASTER - Master mode select.
3725 * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
3726 * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
3727 */
3728#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
3729#define SPI_CFG_LSBF_MASK (0x8U)
3730#define SPI_CFG_LSBF_SHIFT (3U)
3731/*! LSBF - LSB First mode enable.
3732 * 0b0..Standard. Data is transmitted and received in standard MSB first order.
3733 * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first).
3734 */
3735#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
3736#define SPI_CFG_CPHA_MASK (0x10U)
3737#define SPI_CFG_CPHA_SHIFT (4U)
3738/*! CPHA - Clock Phase select.
3739 * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock
3740 * changes away from the rest state). Data is changed on the following edge.
3741 * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock
3742 * changes away from the rest state). Data is captured on the following edge.
3743 */
3744#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
3745#define SPI_CFG_CPOL_MASK (0x20U)
3746#define SPI_CFG_CPOL_SHIFT (5U)
3747/*! CPOL - Clock Polarity select.
3748 * 0b0..Low. The rest state of the clock (between transfers) is low.
3749 * 0b1..High. The rest state of the clock (between transfers) is high.
3750 */
3751#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
3752#define SPI_CFG_LOOP_MASK (0x80U)
3753#define SPI_CFG_LOOP_SHIFT (7U)
3754/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit
3755 * and receive data connected together to allow simple software testing.
3756 * 0b0..Disabled.
3757 * 0b1..Enabled.
3758 */
3759#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
3760#define SPI_CFG_SPOL0_MASK (0x100U)
3761#define SPI_CFG_SPOL0_SHIFT (8U)
3762/*! SPOL0 - SSEL0 Polarity select.
3763 * 0b0..Low. The SSEL0 pin is active low.
3764 * 0b1..High. The SSEL0 pin is active high.
3765 */
3766#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
3767/*! @} */
3768
3769/*! @name DLY - SPI Delay register */
3770/*! @{ */
3771#define SPI_DLY_PRE_DELAY_MASK (0xFU)
3772#define SPI_DLY_PRE_DELAY_SHIFT (0U)
3773/*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data
3774 * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This
3775 * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI
3776 * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are
3777 * inserted.
3778 */
3779#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
3780#define SPI_DLY_POST_DELAY_MASK (0xF0U)
3781#define SPI_DLY_POST_DELAY_SHIFT (4U)
3782/*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL
3783 * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock
3784 * times are inserted. 0xF = 15 SPI clock times are inserted.
3785 */
3786#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
3787#define SPI_DLY_FRAME_DELAY_MASK (0xF00U)
3788#define SPI_DLY_FRAME_DELAY_SHIFT (8U)
3789/*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current
3790 * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1
3791 * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock
3792 * times are inserted.
3793 */
3794#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
3795#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U)
3796#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U)
3797/*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between
3798 * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1
3799 * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that
3800 * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16
3801 * SPI clock times.
3802 */
3803#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
3804/*! @} */
3805
3806/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position */
3807/*! @{ */
3808#define SPI_STAT_RXRDY_MASK (0x1U)
3809#define SPI_STAT_RXRDY_SHIFT (0U)
3810/*! RXRDY - Receiver Ready flag. When 1, indicates that data is available to be read from the
3811 * receiver buffer. Cleared after a read of the RXDAT register.
3812 */
3813#define SPI_STAT_RXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_RXRDY_SHIFT)) & SPI_STAT_RXRDY_MASK)
3814#define SPI_STAT_TXRDY_MASK (0x2U)
3815#define SPI_STAT_TXRDY_SHIFT (1U)
3816/*! TXRDY - Transmitter Ready flag. When 1, this bit indicates that data may be written to the
3817 * transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data
3818 * is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register.
3819 */
3820#define SPI_STAT_TXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_TXRDY_SHIFT)) & SPI_STAT_TXRDY_MASK)
3821#define SPI_STAT_RXOV_MASK (0x4U)
3822#define SPI_STAT_RXOV_SHIFT (2U)
3823/*! RXOV - Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This
3824 * flag is set when the beginning of a received character is detected while the receiver buffer
3825 * is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming
3826 * data is lost. Data received by the SPI should be considered undefined if RxOv is set.
3827 */
3828#define SPI_STAT_RXOV(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_RXOV_SHIFT)) & SPI_STAT_RXOV_MASK)
3829#define SPI_STAT_TXUR_MASK (0x8U)
3830#define SPI_STAT_TXUR_SHIFT (3U)
3831/*! TXUR - Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0).
3832 * In this case, the transmitter must begin sending new data on the next input clock if the
3833 * transmitter is idle. If that data is not available in the transmitter holding register at that
3834 * point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be
3835 * considered undefined if TXUR is set.
3836 */
3837#define SPI_STAT_TXUR(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_TXUR_SHIFT)) & SPI_STAT_TXUR_MASK)
3838#define SPI_STAT_SSA_MASK (0x10U)
3839#define SPI_STAT_SSA_SHIFT (4U)
3840/*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from
3841 * deasserted to asserted, in both master and slave modes. This allows determining when the SPI
3842 * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a
3843 * slave mode access begins. This flag is cleared by software.
3844 */
3845#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
3846#define SPI_STAT_SSD_MASK (0x20U)
3847#define SPI_STAT_SSD_SHIFT (5U)
3848/*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to
3849 * deasserted, in both master and slave modes. This allows determining when the SPI
3850 * transmit/receive functions become idle. This flag is cleared by software.
3851 */
3852#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
3853#define SPI_STAT_STALLED_MASK (0x40U)
3854#define SPI_STAT_STALLED_SHIFT (6U)
3855/*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition.
3856 */
3857#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
3858#define SPI_STAT_ENDTRANSFER_MASK (0x80U)
3859#define SPI_STAT_ENDTRANSFER_SHIFT (7U)
3860/*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current
3861 * transfer when the transmitter finishes any activity already in progress, as if the EOT flag
3862 * had been set prior to the last transmission. This capability is included to support cases where
3863 * it is not known when transmit data is written that it will be the end of a transfer. The bit
3864 * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end
3865 * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
3866 */
3867#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
3868#define SPI_STAT_MSTIDLE_MASK (0x100U)
3869#define SPI_STAT_MSTIDLE_SHIFT (8U)
3870/*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle.
3871 * This means that the transmit holding register is empty and the transmitter is not in the
3872 * process of sending data.
3873 */
3874#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
3875/*! @} */
3876
3877/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
3878/*! @{ */
3879#define SPI_INTENSET_RXRDYEN_MASK (0x1U)
3880#define SPI_INTENSET_RXRDYEN_SHIFT (0U)
3881/*! RXRDYEN - Determines whether an interrupt occurs when receiver data is available.
3882 * 0b0..No interrupt will be generated when receiver data is available.
3883 * 0b1..An interrupt will be generated when receiver data is available in the RXDAT register.
3884 */
3885#define SPI_INTENSET_RXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_RXRDYEN_SHIFT)) & SPI_INTENSET_RXRDYEN_MASK)
3886#define SPI_INTENSET_TXRDYEN_MASK (0x2U)
3887#define SPI_INTENSET_TXRDYEN_SHIFT (1U)
3888/*! TXRDYEN - Determines whether an interrupt occurs when the transmitter holding register is available.
3889 * 0b0..No interrupt will be generated when the transmitter holding register is available.
3890 * 0b1..An interrupt will be generated when data may be written to TXDAT.
3891 */
3892#define SPI_INTENSET_TXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_TXRDYEN_SHIFT)) & SPI_INTENSET_TXRDYEN_MASK)
3893#define SPI_INTENSET_RXOVEN_MASK (0x4U)
3894#define SPI_INTENSET_RXOVEN_SHIFT (2U)
3895/*! RXOVEN - Determines whether an interrupt occurs when a receiver overrun occurs. This happens in
3896 * slave mode when there is a need for the receiver to move newly received data to the RXDAT
3897 * register when it is already in use. The interface prevents receiver overrun in Master mode by not
3898 * allowing a new transmission to begin when a receiver overrun would otherwise occur.
3899 * 0b0..No interrupt will be generated when a receiver overrun occurs.
3900 * 0b1..An interrupt will be generated if a receiver overrun occurs.
3901 */
3902#define SPI_INTENSET_RXOVEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_RXOVEN_SHIFT)) & SPI_INTENSET_RXOVEN_MASK)
3903#define SPI_INTENSET_TXUREN_MASK (0x8U)
3904#define SPI_INTENSET_TXUREN_SHIFT (3U)
3905/*! TXUREN - Determines whether an interrupt occurs when a transmitter underrun occurs. This happens
3906 * in slave mode when there is a need to transmit data when none is available.
3907 * 0b0..No interrupt will be generated when the transmitter underruns.
3908 * 0b1..An interrupt will be generated if the transmitter underruns.
3909 */
3910#define SPI_INTENSET_TXUREN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_TXUREN_SHIFT)) & SPI_INTENSET_TXUREN_MASK)
3911#define SPI_INTENSET_SSAEN_MASK (0x10U)
3912#define SPI_INTENSET_SSAEN_SHIFT (4U)
3913/*! SSAEN - Determines whether an interrupt occurs when the Slave Select is asserted.
3914 * 0b0..No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
3915 * 0b1..An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
3916 */
3917#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
3918#define SPI_INTENSET_SSDEN_MASK (0x20U)
3919#define SPI_INTENSET_SSDEN_SHIFT (5U)
3920/*! SSDEN - Determines whether an interrupt occurs when the Slave Select is deasserted.
3921 * 0b0..No interrupt will be generated when all asserted Slave Selects transition to deasserted.
3922 * 0b1..An interrupt will be generated when all asserted Slave Selects transition to deasserted.
3923 */
3924#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
3925/*! @} */
3926
3927/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */
3928/*! @{ */
3929#define SPI_INTENCLR_RXRDYEN_MASK (0x1U)
3930#define SPI_INTENCLR_RXRDYEN_SHIFT (0U)
3931/*! RXRDYEN - Writing 1 clears the corresponding bits in the INTENSET register.
3932 */
3933#define SPI_INTENCLR_RXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_RXRDYEN_SHIFT)) & SPI_INTENCLR_RXRDYEN_MASK)
3934#define SPI_INTENCLR_TXRDYEN_MASK (0x2U)
3935#define SPI_INTENCLR_TXRDYEN_SHIFT (1U)
3936/*! TXRDYEN - Writing 1 clears the corresponding bits in the INTENSET register.
3937 */
3938#define SPI_INTENCLR_TXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_TXRDYEN_SHIFT)) & SPI_INTENCLR_TXRDYEN_MASK)
3939#define SPI_INTENCLR_RXOVEN_MASK (0x4U)
3940#define SPI_INTENCLR_RXOVEN_SHIFT (2U)
3941/*! RXOVEN - Writing 1 clears the corresponding bits in the INTENSET register.
3942 */
3943#define SPI_INTENCLR_RXOVEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_RXOVEN_SHIFT)) & SPI_INTENCLR_RXOVEN_MASK)
3944#define SPI_INTENCLR_TXUREN_MASK (0x8U)
3945#define SPI_INTENCLR_TXUREN_SHIFT (3U)
3946/*! TXUREN - Writing 1 clears the corresponding bits in the INTENSET register.
3947 */
3948#define SPI_INTENCLR_TXUREN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_TXUREN_SHIFT)) & SPI_INTENCLR_TXUREN_MASK)
3949#define SPI_INTENCLR_SSAEN_MASK (0x10U)
3950#define SPI_INTENCLR_SSAEN_SHIFT (4U)
3951/*! SSAEN - Writing 1 clears the corresponding bits in the INTENSET register.
3952 */
3953#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
3954#define SPI_INTENCLR_SSDEN_MASK (0x20U)
3955#define SPI_INTENCLR_SSDEN_SHIFT (5U)
3956/*! SSDEN - Writing 1 clears the corresponding bits in the INTENSET register.
3957 */
3958#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
3959/*! @} */
3960
3961/*! @name RXDAT - SPI Receive Data */
3962/*! @{ */
3963#define SPI_RXDAT_RXDAT_MASK (0xFFFFU)
3964#define SPI_RXDAT_RXDAT_SHIFT (0U)
3965/*! RXDAT - Receiver Data. This contains the next piece of received data. The number of bits that
3966 * are used depends on the LEN setting in TXCTL / TXDATCTL.
3967 */
3968#define SPI_RXDAT_RXDAT(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXDAT_SHIFT)) & SPI_RXDAT_RXDAT_MASK)
3969#define SPI_RXDAT_RXSSEL0_N_MASK (0x10000U)
3970#define SPI_RXDAT_RXSSEL0_N_SHIFT (16U)
3971/*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved
3972 * along with received data. The value will reflect the SSEL0 pin for both master and slave
3973 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
3974 * pin is configured by the related SPOL bit in CFG.
3975 */
3976#define SPI_RXDAT_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXSSEL0_N_SHIFT)) & SPI_RXDAT_RXSSEL0_N_MASK)
3977#define SPI_RXDAT_SOT_MASK (0x100000U)
3978#define SPI_RXDAT_SOT_SHIFT (20U)
3979/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went
3980 * from deasserted to asserted (i.e., any previous transfer has ended). This information can be
3981 * used to identify the first piece of data in cases where the transfer length is greater than 16
3982 * bit.
3983 */
3984#define SPI_RXDAT_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_SOT_SHIFT)) & SPI_RXDAT_SOT_MASK)
3985/*! @} */
3986
3987/*! @name TXDATCTL - SPI Transmit Data with Control */
3988/*! @{ */
3989#define SPI_TXDATCTL_TXDAT_MASK (0xFFFFU)
3990#define SPI_TXDATCTL_TXDAT_SHIFT (0U)
3991/*! TXDAT - Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.
3992 */
3993#define SPI_TXDATCTL_TXDAT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_TXDAT_SHIFT)) & SPI_TXDATCTL_TXDAT_MASK)
3994#define SPI_TXDATCTL_TXSSEL0_N_MASK (0x10000U)
3995#define SPI_TXDATCTL_TXSSEL0_N_SHIFT (16U)
3996/*! TXSSEL0_N - Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the
3997 * pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in
3998 * the CFG register.
3999 * 0b0..SSEL0 asserted.
4000 * 0b1..SSEL0 not asserted.
4001 */
4002#define SPI_TXDATCTL_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_TXSSEL0_N_SHIFT)) & SPI_TXDATCTL_TXSSEL0_N_MASK)
4003#define SPI_TXDATCTL_EOT_MASK (0x100000U)
4004#define SPI_TXDATCTL_EOT_SHIFT (20U)
4005/*! EOT - End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain
4006 * so for at least the time specified by the Transfer_delay value in the DLY register.
4007 * 0b0..This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
4008 * 0b1..This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
4009 */
4010#define SPI_TXDATCTL_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_EOT_SHIFT)) & SPI_TXDATCTL_EOT_MASK)
4011#define SPI_TXDATCTL_EOF_MASK (0x200000U)
4012#define SPI_TXDATCTL_EOF_SHIFT (21U)
4013/*! EOF - End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value
4014 * in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY
4015 * value = 0. This control can be used as part of the support for frame lengths greater than 16
4016 * bits.
4017 * 0b0..This piece of data transmitted is not treated as the end of a frame.
4018 * 0b1..This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted.
4019 */
4020#define SPI_TXDATCTL_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_EOF_SHIFT)) & SPI_TXDATCTL_EOF_MASK)
4021#define SPI_TXDATCTL_RXIGNORE_MASK (0x400000U)
4022#define SPI_TXDATCTL_RXIGNORE_SHIFT (22U)
4023/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to
4024 * read unneeded data from the receiver.Setting this bit simplifies the transmit process and can
4025 * be used with the DMA.
4026 * 0b0..Received data must be read in order to allow transmission to progress. In slave mode, an overrun error
4027 * will occur if received data is not read before new data is received.
4028 * 0b1..Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
4029 */
4030#define SPI_TXDATCTL_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_RXIGNORE_SHIFT)) & SPI_TXDATCTL_RXIGNORE_MASK)
4031#define SPI_TXDATCTL_LEN_MASK (0xF000000U)
4032#define SPI_TXDATCTL_LEN_SHIFT (24U)
4033/*! LEN - Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths
4034 * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data
4035 * transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits
4036 * in length. ... 0xF = Data transfer is 16 bits in length.
4037 * 0b0000..
4038 * 0b0001..Data transfer is 1 bit in length.
4039 * 0b0010..Data transfer is 2 bit in length.
4040 * 0b0011..Data transfer is 3 bit in length.
4041 * 0b0100..Data transfer is 4 bit in length.
4042 * 0b0101..Data transfer is 5 bit in length.
4043 * 0b0110..Data transfer is 6 bit in length.
4044 * 0b0111..Data transfer is 7 bit in length.
4045 * 0b1000..Data transfer is 8 bit in length.
4046 * 0b1001..Data transfer is 9 bit in length.
4047 * 0b1010..Data transfer is 10 bit in length.
4048 * 0b1011..Data transfer is 11 bit in length.
4049 * 0b1100..Data transfer is 12 bit in length.
4050 * 0b1101..Data transfer is 13 bit in length.
4051 * 0b1110..Data transfer is 14 bit in length.
4052 * 0b1111..Data transfer is 15 bit in length.
4053 */
4054#define SPI_TXDATCTL_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_LEN_SHIFT)) & SPI_TXDATCTL_LEN_MASK)
4055/*! @} */
4056
4057/*! @name TXDAT - SPI Transmit Data. */
4058/*! @{ */
4059#define SPI_TXDAT_DATA_MASK (0xFFFFU)
4060#define SPI_TXDAT_DATA_SHIFT (0U)
4061/*! DATA - Transmit Data. This field provides from 4 to 16 bits of data to be transmitted.
4062 */
4063#define SPI_TXDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDAT_DATA_SHIFT)) & SPI_TXDAT_DATA_MASK)
4064/*! @} */
4065
4066/*! @name TXCTL - SPI Transmit Control */
4067/*! @{ */
4068#define SPI_TXCTL_TXSSEL0_N_MASK (0x10000U)
4069#define SPI_TXCTL_TXSSEL0_N_SHIFT (16U)
4070/*! TXSSEL0_N - Transmit Slave Select 0.
4071 */
4072#define SPI_TXCTL_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_TXSSEL0_N_SHIFT)) & SPI_TXCTL_TXSSEL0_N_MASK)
4073#define SPI_TXCTL_EOT_MASK (0x100000U)
4074#define SPI_TXCTL_EOT_SHIFT (20U)
4075/*! EOT - End of Transfer.
4076 */
4077#define SPI_TXCTL_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_EOT_SHIFT)) & SPI_TXCTL_EOT_MASK)
4078#define SPI_TXCTL_EOF_MASK (0x200000U)
4079#define SPI_TXCTL_EOF_SHIFT (21U)
4080/*! EOF - End of Frame.
4081 */
4082#define SPI_TXCTL_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_EOF_SHIFT)) & SPI_TXCTL_EOF_MASK)
4083#define SPI_TXCTL_RXIGNORE_MASK (0x400000U)
4084#define SPI_TXCTL_RXIGNORE_SHIFT (22U)
4085/*! RXIGNORE - Receive Ignore.
4086 */
4087#define SPI_TXCTL_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_RXIGNORE_SHIFT)) & SPI_TXCTL_RXIGNORE_MASK)
4088#define SPI_TXCTL_LEN_MASK (0xF000000U)
4089#define SPI_TXCTL_LEN_SHIFT (24U)
4090/*! LEN - Data transfer Length.
4091 */
4092#define SPI_TXCTL_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_LEN_SHIFT)) & SPI_TXCTL_LEN_MASK)
4093/*! @} */
4094
4095/*! @name DIV - SPI clock Divider */
4096/*! @{ */
4097#define SPI_DIV_DIVVAL_MASK (0xFFFFU)
4098#define SPI_DIV_DIVVAL_SHIFT (0U)
4099/*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the
4100 * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1,
4101 * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results
4102 * in FCLK/65536.
4103 */
4104#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
4105/*! @} */
4106
4107/*! @name INTSTAT - SPI Interrupt Status */
4108/*! @{ */
4109#define SPI_INTSTAT_RXRDY_MASK (0x1U)
4110#define SPI_INTSTAT_RXRDY_SHIFT (0U)
4111/*! RXRDY - Receiver Ready flag.
4112 */
4113#define SPI_INTSTAT_RXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_RXRDY_SHIFT)) & SPI_INTSTAT_RXRDY_MASK)
4114#define SPI_INTSTAT_TXRDY_MASK (0x2U)
4115#define SPI_INTSTAT_TXRDY_SHIFT (1U)
4116/*! TXRDY - Transmitter Ready flag.
4117 */
4118#define SPI_INTSTAT_TXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_TXRDY_SHIFT)) & SPI_INTSTAT_TXRDY_MASK)
4119#define SPI_INTSTAT_RXOV_MASK (0x4U)
4120#define SPI_INTSTAT_RXOV_SHIFT (2U)
4121/*! RXOV - Receiver Overrun interrupt flag.
4122 */
4123#define SPI_INTSTAT_RXOV(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_RXOV_SHIFT)) & SPI_INTSTAT_RXOV_MASK)
4124#define SPI_INTSTAT_TXUR_MASK (0x8U)
4125#define SPI_INTSTAT_TXUR_SHIFT (3U)
4126/*! TXUR - Transmitter Underrun interrupt flag.
4127 */
4128#define SPI_INTSTAT_TXUR(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_TXUR_SHIFT)) & SPI_INTSTAT_TXUR_MASK)
4129#define SPI_INTSTAT_SSA_MASK (0x10U)
4130#define SPI_INTSTAT_SSA_SHIFT (4U)
4131/*! SSA - Slave Select Assert.
4132 */
4133#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
4134#define SPI_INTSTAT_SSD_MASK (0x20U)
4135#define SPI_INTSTAT_SSD_SHIFT (5U)
4136/*! SSD - Slave Select Deassert.
4137 */
4138#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
4139/*! @} */
4140
4141
4142/*!
4143 * @}
4144 */ /* end of group SPI_Register_Masks */
4145
4146
4147/* SPI - Peripheral instance base addresses */
4148/** Peripheral SPI0 base address */
4149#define SPI0_BASE (0x40058000u)
4150/** Peripheral SPI0 base pointer */
4151#define SPI0 ((SPI_Type *)SPI0_BASE)
4152/** Peripheral SPI1 base address */
4153#define SPI1_BASE (0x4005C000u)
4154/** Peripheral SPI1 base pointer */
4155#define SPI1 ((SPI_Type *)SPI1_BASE)
4156/** Array initializer of SPI peripheral base addresses */
4157#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
4158/** Array initializer of SPI peripheral base pointers */
4159#define SPI_BASE_PTRS { SPI0, SPI1 }
4160/** Interrupt vectors for the SPI peripheral type */
4161#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
4162
4163/*!
4164 * @}
4165 */ /* end of group SPI_Peripheral_Access_Layer */
4166
4167
4168/* ----------------------------------------------------------------------------
4169 -- SWM Peripheral Access Layer
4170 ---------------------------------------------------------------------------- */
4171
4172/*!
4173 * @addtogroup SWM_Peripheral_Access_Layer SWM Peripheral Access Layer
4174 * @{
4175 */
4176
4177/** SWM - Register Layout Typedef */
4178typedef struct {
4179 union { /* offset: 0x0 */
4180 struct { /* offset: 0x0 */
4181 __IO uint32_t PINASSIGN0; /**< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS., offset: 0x0 */
4182 __IO uint32_t PINASSIGN1; /**< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_RTS., offset: 0x4 */
4183 __IO uint32_t PINASSIGN2; /**< Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK, U2_TXD, U2_RXD., offset: 0x8 */
4184 __IO uint32_t PINASSIGN3; /**< Pin assign register 3. Assign movable function U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK., offset: 0xC */
4185 __IO uint32_t PINASSIGN4; /**< Pin assign register 4. Assign movable functions SPI0_MOSI, SPI0_MISO,SPI0_SSEL, SPI1_SCK., offset: 0x10 */
4186 __IO uint32_t PINASSIGN5; /**< Pin assign register 5. Assign movable functions SPI1_MOSI, SPI1_MISO,SPI1_SSEL, CTIN_0, offset: 0x14 */
4187 __IO uint32_t PINASSIGN6; /**< Pin assign register 6. Assign movable functions CTIN_1, CTIN_2, CTIN_3,CTOUT_0., offset: 0x18 */
4188 __IO uint32_t PINASSIGN7; /**< Pin assign register 7. Assign movable functions CTOUT_1, CTOUT_2, CTOUT_3,I2C_SDA., offset: 0x1C */
4189 __IO uint32_t PINASSIGN8; /**< Pin assign register 8. Assign movable functions I2C_SCL, ACMP_O, CLKOUT,GPIO_INT_BMAT., offset: 0x20 */
4190 } PINASSIGN;
4191 __IO uint32_t PINASSIGN_DATA[9]; /**< Pin assign register, array offset: 0x0, array step: 0x4 */
4192 };
4193 uint8_t RESERVED_0[412];
4194 __IO uint32_t PINENABLE0; /**< Pin enable register 0. Enables fixed-pin functions ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN, VDDCMP and so on., offset: 0x1C0 */
4195} SWM_Type;
4196
4197/* ----------------------------------------------------------------------------
4198 -- SWM Register Masks
4199 ---------------------------------------------------------------------------- */
4200
4201/*!
4202 * @addtogroup SWM_Register_Masks SWM Register Masks
4203 * @{
4204 */
4205
4206/*! @name PINASSIGN0 - Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS. */
4207/*! @{ */
4208#define SWM_PINASSIGN0_U0_TXD_O_MASK (0xFFU)
4209#define SWM_PINASSIGN0_U0_TXD_O_SHIFT (0U)
4210/*! U0_TXD_O - U0_TXD function assignment. The value is the pin number to be assigned to this
4211 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4212 */
4213#define SWM_PINASSIGN0_U0_TXD_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_TXD_O_SHIFT)) & SWM_PINASSIGN0_U0_TXD_O_MASK)
4214#define SWM_PINASSIGN0_U0_RXD_I_MASK (0xFF00U)
4215#define SWM_PINASSIGN0_U0_RXD_I_SHIFT (8U)
4216/*! U0_RXD_I - U0_RXD function assignment. The value is the pin number to be assigned to this
4217 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4218 */
4219#define SWM_PINASSIGN0_U0_RXD_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_RXD_I_SHIFT)) & SWM_PINASSIGN0_U0_RXD_I_MASK)
4220#define SWM_PINASSIGN0_U0_RTS_O_MASK (0xFF0000U)
4221#define SWM_PINASSIGN0_U0_RTS_O_SHIFT (16U)
4222/*! U0_RTS_O - U0_RTS function assignment. The value is the pin number to be assigned to this
4223 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4224 */
4225#define SWM_PINASSIGN0_U0_RTS_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_RTS_O_SHIFT)) & SWM_PINASSIGN0_U0_RTS_O_MASK)
4226#define SWM_PINASSIGN0_U0_CTS_I_MASK (0xFF000000U)
4227#define SWM_PINASSIGN0_U0_CTS_I_SHIFT (24U)
4228/*! U0_CTS_I - U0_CTS function assignment. The value is the pin number to be assigned to this
4229 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4230 */
4231#define SWM_PINASSIGN0_U0_CTS_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_CTS_I_SHIFT)) & SWM_PINASSIGN0_U0_CTS_I_MASK)
4232/*! @} */
4233
4234/*! @name PINASSIGN1 - Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_RTS. */
4235/*! @{ */
4236#define SWM_PINASSIGN1_U0_SCLK_IO_MASK (0xFFU)
4237#define SWM_PINASSIGN1_U0_SCLK_IO_SHIFT (0U)
4238/*! U0_SCLK_IO - U0_SCLK function assignment. The value is the pin number to be assigned to this
4239 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4240 */
4241#define SWM_PINASSIGN1_U0_SCLK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U0_SCLK_IO_SHIFT)) & SWM_PINASSIGN1_U0_SCLK_IO_MASK)
4242#define SWM_PINASSIGN1_U1_TXD_O_MASK (0xFF00U)
4243#define SWM_PINASSIGN1_U1_TXD_O_SHIFT (8U)
4244/*! U1_TXD_O - U1_TXD function assignment. The value is the pin number to be assigned to this
4245 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4246 */
4247#define SWM_PINASSIGN1_U1_TXD_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U1_TXD_O_SHIFT)) & SWM_PINASSIGN1_U1_TXD_O_MASK)
4248#define SWM_PINASSIGN1_U1_RXD_I_MASK (0xFF0000U)
4249#define SWM_PINASSIGN1_U1_RXD_I_SHIFT (16U)
4250/*! U1_RXD_I - U1_RXD function assignment. The value is the pin number to be assigned to this
4251 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4252 */
4253#define SWM_PINASSIGN1_U1_RXD_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U1_RXD_I_SHIFT)) & SWM_PINASSIGN1_U1_RXD_I_MASK)
4254#define SWM_PINASSIGN1_U1_RTS_O_MASK (0xFF000000U)
4255#define SWM_PINASSIGN1_U1_RTS_O_SHIFT (24U)
4256/*! U1_RTS_O - U1_RTS function assignment. The value is the pin number to be assigned to this
4257 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4258 */
4259#define SWM_PINASSIGN1_U1_RTS_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U1_RTS_O_SHIFT)) & SWM_PINASSIGN1_U1_RTS_O_MASK)
4260/*! @} */
4261
4262/*! @name PINASSIGN2 - Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK, U2_TXD, U2_RXD. */
4263/*! @{ */
4264#define SWM_PINASSIGN2_U1_CTS_I_MASK (0xFFU)
4265#define SWM_PINASSIGN2_U1_CTS_I_SHIFT (0U)
4266/*! U1_CTS_I - U1_CTS function assignment. The value is the pin number to be assigned to this
4267 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4268 */
4269#define SWM_PINASSIGN2_U1_CTS_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_U1_CTS_I_SHIFT)) & SWM_PINASSIGN2_U1_CTS_I_MASK)
4270#define SWM_PINASSIGN2_U1_SCLK_IO_MASK (0xFF00U)
4271#define SWM_PINASSIGN2_U1_SCLK_IO_SHIFT (8U)
4272/*! U1_SCLK_IO - U1_SCLK function assignment. The value is the pin number to be assigned to this
4273 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4274 */
4275#define SWM_PINASSIGN2_U1_SCLK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_U1_SCLK_IO_SHIFT)) & SWM_PINASSIGN2_U1_SCLK_IO_MASK)
4276#define SWM_PINASSIGN2_U2_TXD_O_MASK (0xFF0000U)
4277#define SWM_PINASSIGN2_U2_TXD_O_SHIFT (16U)
4278/*! U2_TXD_O - U2_TXD function assignment. The value is the pin number to be assigned to this
4279 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4280 */
4281#define SWM_PINASSIGN2_U2_TXD_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_U2_TXD_O_SHIFT)) & SWM_PINASSIGN2_U2_TXD_O_MASK)
4282#define SWM_PINASSIGN2_U2_RXD_I_MASK (0xFF000000U)
4283#define SWM_PINASSIGN2_U2_RXD_I_SHIFT (24U)
4284/*! U2_RXD_I - U2_RXD function assignment. The value is the pin number to be assigned to this
4285 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4286 */
4287#define SWM_PINASSIGN2_U2_RXD_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_U2_RXD_I_SHIFT)) & SWM_PINASSIGN2_U2_RXD_I_MASK)
4288/*! @} */
4289
4290/*! @name PINASSIGN3 - Pin assign register 3. Assign movable function U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK. */
4291/*! @{ */
4292#define SWM_PINASSIGN3_U2_RTS_O_MASK (0xFFU)
4293#define SWM_PINASSIGN3_U2_RTS_O_SHIFT (0U)
4294/*! U2_RTS_O - U2_RTS function assignment. The value is the pin number to be assigned to this
4295 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4296 */
4297#define SWM_PINASSIGN3_U2_RTS_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_U2_RTS_O_SHIFT)) & SWM_PINASSIGN3_U2_RTS_O_MASK)
4298#define SWM_PINASSIGN3_U2_CTS_I_MASK (0xFF00U)
4299#define SWM_PINASSIGN3_U2_CTS_I_SHIFT (8U)
4300/*! U2_CTS_I - U2_CTS function assignment. The value is the pin number to be assigned to this
4301 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4302 */
4303#define SWM_PINASSIGN3_U2_CTS_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_U2_CTS_I_SHIFT)) & SWM_PINASSIGN3_U2_CTS_I_MASK)
4304#define SWM_PINASSIGN3_U2_SCLK_IO_MASK (0xFF0000U)
4305#define SWM_PINASSIGN3_U2_SCLK_IO_SHIFT (16U)
4306/*! U2_SCLK_IO - U2_SCLK function assignment. The value is the pin number to be assigned to this
4307 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4308 */
4309#define SWM_PINASSIGN3_U2_SCLK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_U2_SCLK_IO_SHIFT)) & SWM_PINASSIGN3_U2_SCLK_IO_MASK)
4310#define SWM_PINASSIGN3_SPI0_SCK_IO_MASK (0xFF000000U)
4311#define SWM_PINASSIGN3_SPI0_SCK_IO_SHIFT (24U)
4312/*! SPI0_SCK_IO - SPI0_SCK function assignment. The value is the pin number to be assigned to this
4313 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4314 */
4315#define SWM_PINASSIGN3_SPI0_SCK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_SPI0_SCK_IO_SHIFT)) & SWM_PINASSIGN3_SPI0_SCK_IO_MASK)
4316/*! @} */
4317
4318/*! @name PINASSIGN4 - Pin assign register 4. Assign movable functions SPI0_MOSI, SPI0_MISO,SPI0_SSEL, SPI1_SCK. */
4319/*! @{ */
4320#define SWM_PINASSIGN4_SPI0_MOSI_IO_MASK (0xFFU)
4321#define SWM_PINASSIGN4_SPI0_MOSI_IO_SHIFT (0U)
4322/*! SPI0_MOSI_IO - SPI0_MOSI function assignment. The value is the pin number to be assigned to this
4323 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4324 */
4325#define SWM_PINASSIGN4_SPI0_MOSI_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_SPI0_MOSI_IO_SHIFT)) & SWM_PINASSIGN4_SPI0_MOSI_IO_MASK)
4326#define SWM_PINASSIGN4_SPI0_MISO_IO_MASK (0xFF00U)
4327#define SWM_PINASSIGN4_SPI0_MISO_IO_SHIFT (8U)
4328/*! SPI0_MISO_IO - SPI0_MISIO function assignment. The value is the pin number to be assigned to
4329 * this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4330 */
4331#define SWM_PINASSIGN4_SPI0_MISO_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_SPI0_MISO_IO_SHIFT)) & SWM_PINASSIGN4_SPI0_MISO_IO_MASK)
4332#define SWM_PINASSIGN4_SPI0_SSEL_IO_MASK (0xFF0000U)
4333#define SWM_PINASSIGN4_SPI0_SSEL_IO_SHIFT (16U)
4334/*! SPI0_SSEL_IO - SPI0_SSEL function assignment. The value is the pin number to be assigned to this
4335 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4336 */
4337#define SWM_PINASSIGN4_SPI0_SSEL_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_SPI0_SSEL_IO_SHIFT)) & SWM_PINASSIGN4_SPI0_SSEL_IO_MASK)
4338#define SWM_PINASSIGN4_SPI1_SCK_IO_MASK (0xFF000000U)
4339#define SWM_PINASSIGN4_SPI1_SCK_IO_SHIFT (24U)
4340/*! SPI1_SCK_IO - SPI1_SCK function assignment. The value is the pin number to be assigned to this
4341 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4342 */
4343#define SWM_PINASSIGN4_SPI1_SCK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_SPI1_SCK_IO_SHIFT)) & SWM_PINASSIGN4_SPI1_SCK_IO_MASK)
4344/*! @} */
4345
4346/*! @name PINASSIGN5 - Pin assign register 5. Assign movable functions SPI1_MOSI, SPI1_MISO,SPI1_SSEL, CTIN_0 */
4347/*! @{ */
4348#define SWM_PINASSIGN5_SPI1_MOSI_IO_MASK (0xFFU)
4349#define SWM_PINASSIGN5_SPI1_MOSI_IO_SHIFT (0U)
4350/*! SPI1_MOSI_IO - SPI1_MOSI function assignment. The value is the pin number to be assigned to this
4351 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4352 */
4353#define SWM_PINASSIGN5_SPI1_MOSI_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI1_MOSI_IO_SHIFT)) & SWM_PINASSIGN5_SPI1_MOSI_IO_MASK)
4354#define SWM_PINASSIGN5_SPI1_MISO_IO_MASK (0xFF00U)
4355#define SWM_PINASSIGN5_SPI1_MISO_IO_SHIFT (8U)
4356/*! SPI1_MISO_IO - SPI1_MISIO function assignment. The value is the pin number to be assigned to
4357 * this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4358 */
4359#define SWM_PINASSIGN5_SPI1_MISO_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI1_MISO_IO_SHIFT)) & SWM_PINASSIGN5_SPI1_MISO_IO_MASK)
4360#define SWM_PINASSIGN5_SPI1_SSEL_IO_MASK (0xFF0000U)
4361#define SWM_PINASSIGN5_SPI1_SSEL_IO_SHIFT (16U)
4362/*! SPI1_SSEL_IO - SPI1_SSEL function assignment. The value is the pin number to be assigned to this
4363 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4364 */
4365#define SWM_PINASSIGN5_SPI1_SSEL_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI1_SSEL_IO_SHIFT)) & SWM_PINASSIGN5_SPI1_SSEL_IO_MASK)
4366#define SWM_PINASSIGN5_CTIN_0_I_MASK (0xFF000000U)
4367#define SWM_PINASSIGN5_CTIN_0_I_SHIFT (24U)
4368/*! CTIN_0_I - CTIN_0 function assignment. The value is the pin number to be assigned to this
4369 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4370 */
4371#define SWM_PINASSIGN5_CTIN_0_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_CTIN_0_I_SHIFT)) & SWM_PINASSIGN5_CTIN_0_I_MASK)
4372/*! @} */
4373
4374/*! @name PINASSIGN6 - Pin assign register 6. Assign movable functions CTIN_1, CTIN_2, CTIN_3,CTOUT_0. */
4375/*! @{ */
4376#define SWM_PINASSIGN6_CTIN_1_I_MASK (0xFFU)
4377#define SWM_PINASSIGN6_CTIN_1_I_SHIFT (0U)
4378/*! CTIN_1_I - CTIN_1 function assignment. The value is the pin number to be assigned to this
4379 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4380 */
4381#define SWM_PINASSIGN6_CTIN_1_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_CTIN_1_I_SHIFT)) & SWM_PINASSIGN6_CTIN_1_I_MASK)
4382#define SWM_PINASSIGN6_CTIN_2_I_MASK (0xFF00U)
4383#define SWM_PINASSIGN6_CTIN_2_I_SHIFT (8U)
4384/*! CTIN_2_I - CTIN_2 function assignment. The value is the pin number to be assigned to this
4385 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4386 */
4387#define SWM_PINASSIGN6_CTIN_2_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_CTIN_2_I_SHIFT)) & SWM_PINASSIGN6_CTIN_2_I_MASK)
4388#define SWM_PINASSIGN6_CTIN_3_I_MASK (0xFF0000U)
4389#define SWM_PINASSIGN6_CTIN_3_I_SHIFT (16U)
4390/*! CTIN_3_I - CTIN_3 function assignment. The value is the pin number to be assigned to this
4391 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4392 */
4393#define SWM_PINASSIGN6_CTIN_3_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_CTIN_3_I_SHIFT)) & SWM_PINASSIGN6_CTIN_3_I_MASK)
4394#define SWM_PINASSIGN6_CTOUT_0_O_MASK (0xFF000000U)
4395#define SWM_PINASSIGN6_CTOUT_0_O_SHIFT (24U)
4396/*! CTOUT_0_O - CTOUT_0 function assignment. The value is the pin number to be assigned to this
4397 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4398 */
4399#define SWM_PINASSIGN6_CTOUT_0_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_CTOUT_0_O_SHIFT)) & SWM_PINASSIGN6_CTOUT_0_O_MASK)
4400/*! @} */
4401
4402/*! @name PINASSIGN7 - Pin assign register 7. Assign movable functions CTOUT_1, CTOUT_2, CTOUT_3,I2C_SDA. */
4403/*! @{ */
4404#define SWM_PINASSIGN7_CTOUT_1_O_MASK (0xFFU)
4405#define SWM_PINASSIGN7_CTOUT_1_O_SHIFT (0U)
4406/*! CTOUT_1_O - CTOUT_1 function assignment. The value is the pin number to be assigned to this
4407 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4408 */
4409#define SWM_PINASSIGN7_CTOUT_1_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN7_CTOUT_1_O_SHIFT)) & SWM_PINASSIGN7_CTOUT_1_O_MASK)
4410#define SWM_PINASSIGN7_CTOUT_2_O_MASK (0xFF00U)
4411#define SWM_PINASSIGN7_CTOUT_2_O_SHIFT (8U)
4412/*! CTOUT_2_O - CTOUT_2 function assignment. The value is the pin number to be assigned to this
4413 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4414 */
4415#define SWM_PINASSIGN7_CTOUT_2_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN7_CTOUT_2_O_SHIFT)) & SWM_PINASSIGN7_CTOUT_2_O_MASK)
4416#define SWM_PINASSIGN7_CTOUT_3_O_MASK (0xFF0000U)
4417#define SWM_PINASSIGN7_CTOUT_3_O_SHIFT (16U)
4418/*! CTOUT_3_O - CTOUT_3 function assignment. The value is the pin number to be assigned to this
4419 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4420 */
4421#define SWM_PINASSIGN7_CTOUT_3_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN7_CTOUT_3_O_SHIFT)) & SWM_PINASSIGN7_CTOUT_3_O_MASK)
4422#define SWM_PINASSIGN7_I2C_SDA_IO_MASK (0xFF000000U)
4423#define SWM_PINASSIGN7_I2C_SDA_IO_SHIFT (24U)
4424/*! I2C_SDA_IO - I2C_SDA function assignment. The value is the pin number to be assigned to this
4425 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4426 */
4427#define SWM_PINASSIGN7_I2C_SDA_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN7_I2C_SDA_IO_SHIFT)) & SWM_PINASSIGN7_I2C_SDA_IO_MASK)
4428/*! @} */
4429
4430/*! @name PINASSIGN8 - Pin assign register 8. Assign movable functions I2C_SCL, ACMP_O, CLKOUT,GPIO_INT_BMAT. */
4431/*! @{ */
4432#define SWM_PINASSIGN8_I2C_SCL_IO_MASK (0xFFU)
4433#define SWM_PINASSIGN8_I2C_SCL_IO_SHIFT (0U)
4434/*! I2C_SCL_IO - I2C_SCL function assignment. The value is the pin number to be assigned to this
4435 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4436 */
4437#define SWM_PINASSIGN8_I2C_SCL_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN8_I2C_SCL_IO_SHIFT)) & SWM_PINASSIGN8_I2C_SCL_IO_MASK)
4438#define SWM_PINASSIGN8_ACMP_O_O_MASK (0xFF00U)
4439#define SWM_PINASSIGN8_ACMP_O_O_SHIFT (8U)
4440/*! ACMP_O_O - ACMP_O_O function assignment. The value is the pin number to be assigned to this
4441 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4442 */
4443#define SWM_PINASSIGN8_ACMP_O_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN8_ACMP_O_O_SHIFT)) & SWM_PINASSIGN8_ACMP_O_O_MASK)
4444#define SWM_PINASSIGN8_CLKOUT_O_MASK (0xFF0000U)
4445#define SWM_PINASSIGN8_CLKOUT_O_SHIFT (16U)
4446/*! CLKOUT_O - CLKOUT function assignment. The value is the pin number to be assigned to this
4447 * function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4448 */
4449#define SWM_PINASSIGN8_CLKOUT_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN8_CLKOUT_O_SHIFT)) & SWM_PINASSIGN8_CLKOUT_O_MASK)
4450#define SWM_PINASSIGN8_GPIO_INT_BMAT_O_MASK (0xFF000000U)
4451#define SWM_PINASSIGN8_GPIO_INT_BMAT_O_SHIFT (24U)
4452/*! GPIO_INT_BMAT_O - GPIO_INT_BMAT function assignment. The value is the pin number to be assigned
4453 * to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
4454 */
4455#define SWM_PINASSIGN8_GPIO_INT_BMAT_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN8_GPIO_INT_BMAT_O_SHIFT)) & SWM_PINASSIGN8_GPIO_INT_BMAT_O_MASK)
4456/*! @} */
4457
4458/*! @name PINASSIGN_DATA - Pin assign register */
4459/*! @{ */
4460#define SWM_PINASSIGN_DATA_DATA0_MASK (0xFFU)
4461#define SWM_PINASSIGN_DATA_DATA0_SHIFT (0U)
4462/*! DATA0 - T0_MAT3 function assignment. The value is the pin number to be assigned to this
4463 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20)
4464 * to PIO1_21(=0x35).
4465 */
4466#define SWM_PINASSIGN_DATA_DATA0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_DATA0_SHIFT)) & SWM_PINASSIGN_DATA_DATA0_MASK)
4467#define SWM_PINASSIGN_DATA_DATA1_MASK (0xFF00U)
4468#define SWM_PINASSIGN_DATA_DATA1_SHIFT (8U)
4469/*! DATA1 - T0_CAP0 function assignment. The value is the pin number to be assigned to this
4470 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20)
4471 * to PIO1_21(=0x35).
4472 */
4473#define SWM_PINASSIGN_DATA_DATA1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_DATA1_SHIFT)) & SWM_PINASSIGN_DATA_DATA1_MASK)
4474#define SWM_PINASSIGN_DATA_DATA2_MASK (0xFF0000U)
4475#define SWM_PINASSIGN_DATA_DATA2_SHIFT (16U)
4476/*! DATA2 - T0_CAP1 function assignment. The value is the pin number to be assigned to this
4477 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20)
4478 * to PIO1_21(=0x35).
4479 */
4480#define SWM_PINASSIGN_DATA_DATA2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_DATA2_SHIFT)) & SWM_PINASSIGN_DATA_DATA2_MASK)
4481#define SWM_PINASSIGN_DATA_DATA3_MASK (0xFF000000U)
4482#define SWM_PINASSIGN_DATA_DATA3_SHIFT (24U)
4483/*! DATA3 - T0_CAP2 function assignment. The value is the pin number to be assigned to this
4484 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20)
4485 * to PIO1_21(=0x35).
4486 */
4487#define SWM_PINASSIGN_DATA_DATA3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_DATA3_SHIFT)) & SWM_PINASSIGN_DATA_DATA3_MASK)
4488/*! @} */
4489
4490/* The count of SWM_PINASSIGN_DATA */
4491#define SWM_PINASSIGN_DATA_COUNT (9U)
4492
4493/*! @name PINENABLE0 - Pin enable register 0. Enables fixed-pin functions ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN, VDDCMP and so on. */
4494/*! @{ */
4495#define SWM_PINENABLE0_ACMP_I1_MASK (0x1U)
4496#define SWM_PINENABLE0_ACMP_I1_SHIFT (0U)
4497/*! ACMP_I1 - Enables fixed-pin function. Writing a 1 deselects the function and any movable
4498 * function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is
4499 * assigned to this pin.
4500 * 0b0..Enable ACMP_I1. This function is enabled on pin PIO0_0.
4501 * 0b1..Disable ACMP_I1. GPIO function PIO0_0 (default) or any other movable function can be assigned to pin PIO0_0.
4502 */
4503#define SWM_PINENABLE0_ACMP_I1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I1_SHIFT)) & SWM_PINENABLE0_ACMP_I1_MASK)
4504#define SWM_PINENABLE0_ACMP_I2_MASK (0x2U)
4505#define SWM_PINENABLE0_ACMP_I2_SHIFT (1U)
4506/*! ACMP_I2 - Enables fixed-pin function. Writing a 1 deselects the function and any movable
4507 * function can be assigned to this pin. By default the fixed-pin function is deselected and GPIO is
4508 * assigned to this pin. Functions CLKIN and ACMP_I2 are connected to the same pin PIO0_1. To use
4509 * ACMP_I2, disable the CLKIN function in bit 7 of this register and enable ACMP_I2.
4510 * 0b0..Enable ACMP_I2. This function is enabled on pin PIO0_1.
4511 * 0b1..Disable ACMP_I2. GPIO function PIO0_1 (default) or any other movable function can be assigned to pin PIO0_1.
4512 */
4513#define SWM_PINENABLE0_ACMP_I2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I2_SHIFT)) & SWM_PINENABLE0_ACMP_I2_MASK)
4514#define SWM_PINENABLE0_SWCLK_MASK (0x4U)
4515#define SWM_PINENABLE0_SWCLK_SHIFT (2U)
4516/*! SWCLK - Enables fixed-pin function. Writing a 1 deselects the function and any movable function
4517 * can be assigned to this pin. This function is selected by default.
4518 * 0b0..Enable SWCLK. This function is enabled on pin PIO0_3.
4519 * 0b1..Disable SWCLK. GPIO function PIO0_3 is selected on this pin. Any other movable function can be assigned to pin PIO0_3.
4520 */
4521#define SWM_PINENABLE0_SWCLK(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_SWCLK_SHIFT)) & SWM_PINENABLE0_SWCLK_MASK)
4522#define SWM_PINENABLE0_SWDIO_MASK (0x8U)
4523#define SWM_PINENABLE0_SWDIO_SHIFT (3U)
4524/*! SWDIO - Enables fixed-pin function. Writing a 1 deselects the function and any movable function
4525 * can be assigned to this pin. This function is selected by default.
4526 * 0b0..Enable SWDIO. This function is enabled on pin PIO0_2.
4527 * 0b1..Disable SWDIO. GPIO function PIO0_2 is selected on this pin. Any other movable function can be assigned to pin PIO0_2.
4528 */
4529#define SWM_PINENABLE0_SWDIO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_SWDIO_SHIFT)) & SWM_PINENABLE0_SWDIO_MASK)
4530#define SWM_PINENABLE0_XTALIN_MASK (0x10U)
4531#define SWM_PINENABLE0_XTALIN_SHIFT (4U)
4532/*! XTALIN - Enables fixed-pin function. Writing a 1 deselects the function and any movable function
4533 * can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is
4534 * assigned to this pin.
4535 * 0b0..Enable XTALIN. This function is enabled on pin PIO0_8.
4536 * 0b1..Disable XTALIN. GPIO function PIO0_8 (default) or any other movable function can be assigned to pin PIO0_8.
4537 */
4538#define SWM_PINENABLE0_XTALIN(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_XTALIN_SHIFT)) & SWM_PINENABLE0_XTALIN_MASK)
4539#define SWM_PINENABLE0_XTALOUT_MASK (0x20U)
4540#define SWM_PINENABLE0_XTALOUT_SHIFT (5U)
4541/*! XTALOUT - Enables fixed-pin function. Writing a 1 deselects the function and any movable
4542 * function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is
4543 * assigned to this pin.
4544 * 0b0..Enable XTALOUT. This function is enabled on pin PIO0_9.
4545 * 0b1..Disable XTALOUT. GPIO function PIO0_9 (default) or any other movable function can be assigned to pin PIO0_9.
4546 */
4547#define SWM_PINENABLE0_XTALOUT(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_XTALOUT_SHIFT)) & SWM_PINENABLE0_XTALOUT_MASK)
4548#define SWM_PINENABLE0_RESETN_MASK (0x40U)
4549#define SWM_PINENABLE0_RESETN_SHIFT (6U)
4550/*! RESETN - Enables fixed-pin function. Writing a 1 deselects the function and any movable function
4551 * can be assigned to this pin. This function is selected by default.
4552 * 0b0..Enable RESETN. This function is enabled on pin PIO0_5.
4553 * 0b1..Disable RESETN. GPIO function PIO0_5 is selected on this pin. Any other movable function can be assigned to pin PIO0_5.
4554 */
4555#define SWM_PINENABLE0_RESETN(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_RESETN_SHIFT)) & SWM_PINENABLE0_RESETN_MASK)
4556#define SWM_PINENABLE0_CLKIN_MASK (0x80U)
4557#define SWM_PINENABLE0_CLKIN_SHIFT (7U)
4558/*! CLKIN - Enables fixed-pin function. Writing a 1 deselects the function and any movable function
4559 * can be assigned to this pin. By default the fixed-pin function is deselected and GPIO is
4560 * assigned to this pin. Functions CLKIN and ACMP_I2 are connected to the same pin PIO0_1. To use
4561 * CLKIN, disable ACMP_I2 in bit 1 of this register and enable CLKIN.
4562 * 0b0..Enable CLKIN. This function is enabled on pin PIO0_1.
4563 * 0b1..Disable CLKIN. GPIO function PIO0_1 (default) or any other movable function can be assigned to pin CLKIN.
4564 */
4565#define SWM_PINENABLE0_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_CLKIN_SHIFT)) & SWM_PINENABLE0_CLKIN_MASK)
4566#define SWM_PINENABLE0_VDDCMP_MASK (0x100U)
4567#define SWM_PINENABLE0_VDDCMP_SHIFT (8U)
4568/*! VDDCMP - Enables fixed-pin function. Writing a 1 deselects the function and any movable function
4569 * can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is
4570 * assigned to this pin.
4571 * 0b0..Enable VDDCMP. This function is enabled on pin PIO0_6.
4572 * 0b1..Disable VDDCMP. GPIO function PIO0_6 (default) or any other movable function can be assigned to pin PIO0_6.
4573 */
4574#define SWM_PINENABLE0_VDDCMP(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_VDDCMP_SHIFT)) & SWM_PINENABLE0_VDDCMP_MASK)
4575/*! @} */
4576
4577
4578/*!
4579 * @}
4580 */ /* end of group SWM_Register_Masks */
4581
4582
4583/* SWM - Peripheral instance base addresses */
4584/** Peripheral SWM0 base address */
4585#define SWM0_BASE (0x4000C000u)
4586/** Peripheral SWM0 base pointer */
4587#define SWM0 ((SWM_Type *)SWM0_BASE)
4588/** Array initializer of SWM peripheral base addresses */
4589#define SWM_BASE_ADDRS { SWM0_BASE }
4590/** Array initializer of SWM peripheral base pointers */
4591#define SWM_BASE_PTRS { SWM0 }
4592
4593/*!
4594 * @}
4595 */ /* end of group SWM_Peripheral_Access_Layer */
4596
4597
4598/* ----------------------------------------------------------------------------
4599 -- SYSCON Peripheral Access Layer
4600 ---------------------------------------------------------------------------- */
4601
4602/*!
4603 * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
4604 * @{
4605 */
4606
4607/** SYSCON - Register Layout Typedef */
4608typedef struct {
4609 __IO uint32_t SYSMEMREMAP; /**< System Remap register, offset: 0x0 */
4610 __IO uint32_t PRESETCTRL; /**< Peripheral reset control register, offset: 0x4 */
4611 __IO uint32_t SYSPLLCTRL; /**< PLL control, offset: 0x8 */
4612 __I uint32_t SYSPLLSTAT; /**< PLL status, offset: 0xC */
4613 uint8_t RESERVED_0[16];
4614 __IO uint32_t SYSOSCCTRL; /**< system oscillator control, offset: 0x20 */
4615 __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x24 */
4616 uint8_t RESERVED_1[8];
4617 __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x30 */
4618 uint8_t RESERVED_2[12];
4619 __IO uint32_t SYSPLLCLKSEL; /**< System PLL clock source select register, offset: 0x40 */
4620 __IO uint32_t SYSPLLCLKUEN; /**< System PLL clock source update enable register, offset: 0x44 */
4621 uint8_t RESERVED_3[40];
4622 __IO uint32_t MAINCLKSEL; /**< Main clock source select, offset: 0x70 */
4623 __IO uint32_t MAINCLKUEN; /**< Main clock source update enable, offset: 0x74 */
4624 __IO uint32_t SYSAHBCLKDIV; /**< System clock divider, offset: 0x78 */
4625 uint8_t RESERVED_4[4];
4626 __IO uint32_t SYSAHBCLKCTRL; /**< System clock control, offset: 0x80 */
4627 uint8_t RESERVED_5[16];
4628 __IO uint32_t UARTCLKDIV; /**< USART clock divider, offset: 0x94 */
4629 uint8_t RESERVED_6[72];
4630 __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0xE0 */
4631 __IO uint32_t CLKOUTUEN; /**< CLKOUT clock source update enable, offset: 0xE4 */
4632 __IO uint32_t CLKOUTDIV; /**< clock out divider, offset: 0xE8 */
4633 uint8_t RESERVED_7[4];
4634 __IO uint32_t UARTFRGDIV; /**< USART common fractional generator divider value, offset: 0xF0 */
4635 __IO uint32_t UARTFRGMULT; /**< USART common fractional generator divider value, offset: 0xF4 */
4636 uint8_t RESERVED_8[4];
4637 __IO uint32_t EXTTRACECMD; /**< External trace buffer command register, offset: 0xFC */
4638 __I uint32_t PIOPORCAP0; /**< POR captured PIO status 0, offset: 0x100 */
4639 uint8_t RESERVED_9[48];
4640 __IO uint32_t IOCONCLKDIV6; /**< Peripheral clock 6 to the IOCON block for programmable glitch filter, offset: 0x134 */
4641 __IO uint32_t IOCONCLKDIV5; /**< Peripheral clock 6 to the IOCON block for programmable glitch filter, offset: 0x138 */
4642 __IO uint32_t IOCONCLKDIV4; /**< Peripheral clock 4 to the IOCON block for programmable glitch filter, offset: 0x13C */
4643 __IO uint32_t IOCONCLKDIV3; /**< Peripheral clock 3 to the IOCON block for programmable glitch filter, offset: 0x140 */
4644 __IO uint32_t IOCONCLKDIV2; /**< Peripheral clock 2 to the IOCON block for programmable glitch filter, offset: 0x144 */
4645 __IO uint32_t IOCONCLKDIV1; /**< Peripheral clock 1 to the IOCON block for programmable glitch filter, offset: 0x148 */
4646 __IO uint32_t IOCONCLKDIV0; /**< Peripheral clock 0 to the IOCON block for programmable glitch filter, offset: 0x14C */
4647 __IO uint32_t BODCTRL; /**< BOD control register, offset: 0x150 */
4648 __IO uint32_t SYSTCKCAL; /**< System tick timer calibration register, offset: 0x154 */
4649 uint8_t RESERVED_10[24];
4650 __IO uint32_t IRQLATENCY; /**< IRQ latency register, offset: 0x170 */
4651 __IO uint32_t NMISRC; /**< NMI source selection register, offset: 0x174 */
4652 __IO uint32_t PINTSEL[8]; /**< Pin interrupt select registers N, array offset: 0x178, array step: 0x4 */
4653 uint8_t RESERVED_11[108];
4654 __IO uint32_t STARTERP0; /**< Start logic 0 pin wake-up enable register 0, offset: 0x204 */
4655 uint8_t RESERVED_12[12];
4656 __IO uint32_t STARTERP1; /**< Start logic 0 pin wake-up enable register 1, offset: 0x214 */
4657 uint8_t RESERVED_13[24];
4658 __IO uint32_t PDSLEEPCFG; /**< Deep-sleep configuration register, offset: 0x230 */
4659 __IO uint32_t PDAWAKECFG; /**< Wake-up configuration register, offset: 0x234 */
4660 __IO uint32_t PDRUNCFG; /**< Power configuration register, offset: 0x238 */
4661 uint8_t RESERVED_14[444];
4662 __I uint32_t DEVICE_ID; /**< Part ID register, offset: 0x3F8 */
4663} SYSCON_Type;
4664
4665/* ----------------------------------------------------------------------------
4666 -- SYSCON Register Masks
4667 ---------------------------------------------------------------------------- */
4668
4669/*!
4670 * @addtogroup SYSCON_Register_Masks SYSCON Register Masks
4671 * @{
4672 */
4673
4674/*! @name SYSMEMREMAP - System Remap register */
4675/*! @{ */
4676#define SYSCON_SYSMEMREMAP_MAP_MASK (0x3U)
4677#define SYSCON_SYSMEMREMAP_MAP_SHIFT (0U)
4678/*! MAP - System memory remap. Value 0x3 is reserved.
4679 * 0b00..Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
4680 * 0b01..User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
4681 * 0b10..User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
4682 */
4683#define SYSCON_SYSMEMREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSMEMREMAP_MAP_SHIFT)) & SYSCON_SYSMEMREMAP_MAP_MASK)
4684/*! @} */
4685
4686/*! @name PRESETCTRL - Peripheral reset control register */
4687/*! @{ */
4688#define SYSCON_PRESETCTRL_SPI0_RST_N_MASK (0x1U)
4689#define SYSCON_PRESETCTRL_SPI0_RST_N_SHIFT (0U)
4690/*! SPI0_RST_N - SPI0 reset control.
4691 * 0b0..Assert the SPI0 reset.
4692 * 0b1..Clear the SPI0 reset.
4693 */
4694#define SYSCON_PRESETCTRL_SPI0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SPI0_RST_N_SHIFT)) & SYSCON_PRESETCTRL_SPI0_RST_N_MASK)
4695#define SYSCON_PRESETCTRL_SPI1_RST_N_MASK (0x2U)
4696#define SYSCON_PRESETCTRL_SPI1_RST_N_SHIFT (1U)
4697/*! SPI1_RST_N - SPI1 reset control.
4698 * 0b0..Assert the SPI1 reset.
4699 * 0b1..Clear the SPI1 reset.
4700 */
4701#define SYSCON_PRESETCTRL_SPI1_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SPI1_RST_N_SHIFT)) & SYSCON_PRESETCTRL_SPI1_RST_N_MASK)
4702#define SYSCON_PRESETCTRL_UARTFRG_RST_N_MASK (0x4U)
4703#define SYSCON_PRESETCTRL_UARTFRG_RST_N_SHIFT (2U)
4704/*! UARTFRG_RST_N - USART fractional baud rate generator(UARTFRG) reset control.
4705 * 0b0..Assert the UARTFRG reset.
4706 * 0b1..Clear the UARTFRG reset.
4707 */
4708#define SYSCON_PRESETCTRL_UARTFRG_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UARTFRG_RST_N_SHIFT)) & SYSCON_PRESETCTRL_UARTFRG_RST_N_MASK)
4709#define SYSCON_PRESETCTRL_UART0_RST_N_MASK (0x8U)
4710#define SYSCON_PRESETCTRL_UART0_RST_N_SHIFT (3U)
4711/*! UART0_RST_N - USART0 reset control.
4712 * 0b0..Assert the USART0 reset.
4713 * 0b1..Clear the USART0 reset.
4714 */
4715#define SYSCON_PRESETCTRL_UART0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UART0_RST_N_SHIFT)) & SYSCON_PRESETCTRL_UART0_RST_N_MASK)
4716#define SYSCON_PRESETCTRL_UART1_RST_N_MASK (0x10U)
4717#define SYSCON_PRESETCTRL_UART1_RST_N_SHIFT (4U)
4718/*! UART1_RST_N - USART1 reset control.
4719 * 0b0..Assert the USART1 reset.
4720 * 0b1..Clear the USART1 reset.
4721 */
4722#define SYSCON_PRESETCTRL_UART1_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UART1_RST_N_SHIFT)) & SYSCON_PRESETCTRL_UART1_RST_N_MASK)
4723#define SYSCON_PRESETCTRL_UART2_RST_N_MASK (0x20U)
4724#define SYSCON_PRESETCTRL_UART2_RST_N_SHIFT (5U)
4725/*! UART2_RST_N - USART2 reset control.
4726 * 0b0..Assert the USART2 reset.
4727 * 0b1..Clear the USART2 reset.
4728 */
4729#define SYSCON_PRESETCTRL_UART2_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UART2_RST_N_SHIFT)) & SYSCON_PRESETCTRL_UART2_RST_N_MASK)
4730#define SYSCON_PRESETCTRL_I2C0_RST_N_MASK (0x40U)
4731#define SYSCON_PRESETCTRL_I2C0_RST_N_SHIFT (6U)
4732/*! I2C0_RST_N - I2C0 reset control.
4733 * 0b0..Assert the I2C0 reset.
4734 * 0b1..Clear the I2C0 reset.
4735 */
4736#define SYSCON_PRESETCTRL_I2C0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_I2C0_RST_N_SHIFT)) & SYSCON_PRESETCTRL_I2C0_RST_N_MASK)
4737#define SYSCON_PRESETCTRL_MRT_RST_N_MASK (0x80U)
4738#define SYSCON_PRESETCTRL_MRT_RST_N_SHIFT (7U)
4739/*! MRT_RST_N - Multi-rate timer (MRT) reset control.
4740 * 0b0..Assert the MRT reset.
4741 * 0b1..Clear the MRT reset.
4742 */
4743#define SYSCON_PRESETCTRL_MRT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT_RST_N_SHIFT)) & SYSCON_PRESETCTRL_MRT_RST_N_MASK)
4744#define SYSCON_PRESETCTRL_SCT_RST_N_MASK (0x100U)
4745#define SYSCON_PRESETCTRL_SCT_RST_N_SHIFT (8U)
4746/*! SCT_RST_N - SCT reset control.
4747 * 0b0..Assert the SCT reset.
4748 * 0b1..Clear the SCT reset.
4749 */
4750#define SYSCON_PRESETCTRL_SCT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT_RST_N_SHIFT)) & SYSCON_PRESETCTRL_SCT_RST_N_MASK)
4751#define SYSCON_PRESETCTRL_WKT_RST_N_MASK (0x200U)
4752#define SYSCON_PRESETCTRL_WKT_RST_N_SHIFT (9U)
4753/*! WKT_RST_N - Self-wake-up timer (WKT) reset control.
4754 * 0b0..Assert the WKT reset.
4755 * 0b1..Clear the WKT reset.
4756 */
4757#define SYSCON_PRESETCTRL_WKT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WKT_RST_N_SHIFT)) & SYSCON_PRESETCTRL_WKT_RST_N_MASK)
4758#define SYSCON_PRESETCTRL_GPIO_RST_N_MASK (0x400U)
4759#define SYSCON_PRESETCTRL_GPIO_RST_N_SHIFT (10U)
4760/*! GPIO_RST_N - GPIO and GPIO pin interrupt reset control.
4761 * 0b0..Assert the GPIO reset.
4762 * 0b1..Clear the GPIO reset.
4763 */
4764#define SYSCON_PRESETCTRL_GPIO_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO_RST_N_SHIFT)) & SYSCON_PRESETCTRL_GPIO_RST_N_MASK)
4765#define SYSCON_PRESETCTRL_FLASH_RST_N_MASK (0x800U)
4766#define SYSCON_PRESETCTRL_FLASH_RST_N_SHIFT (11U)
4767/*! FLASH_RST_N - Flash controller reset control.
4768 * 0b0..Assert the flash controller reset.
4769 * 0b1..Clear the flash controller reset.
4770 */
4771#define SYSCON_PRESETCTRL_FLASH_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_N_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_N_MASK)
4772#define SYSCON_PRESETCTRL_ACMP_RST_N_MASK (0x1000U)
4773#define SYSCON_PRESETCTRL_ACMP_RST_N_SHIFT (12U)
4774/*! ACMP_RST_N - Analog comparator reset control.
4775 * 0b0..Assert the analog comparator reset.
4776 * 0b1..Clear the analog comparator controller reset.
4777 */
4778#define SYSCON_PRESETCTRL_ACMP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ACMP_RST_N_SHIFT)) & SYSCON_PRESETCTRL_ACMP_RST_N_MASK)
4779/*! @} */
4780
4781/*! @name SYSPLLCTRL - PLL control */
4782/*! @{ */
4783#define SYSCON_SYSPLLCTRL_MSEL_MASK (0x1FU)
4784#define SYSCON_SYSPLLCTRL_MSEL_SHIFT (0U)
4785/*! MSEL - Feedback divider value. The division value M is the programmed MSEL value + 1. 00000:
4786 * Division ratio M = 1 to 11111: Division ratio M = 32
4787 */
4788#define SYSCON_SYSPLLCTRL_MSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_MSEL_SHIFT)) & SYSCON_SYSPLLCTRL_MSEL_MASK)
4789#define SYSCON_SYSPLLCTRL_PSEL_MASK (0x60U)
4790#define SYSCON_SYSPLLCTRL_PSEL_SHIFT (5U)
4791/*! PSEL - Post divider ratio P. The division ratio is 2 x P.
4792 * 0b00..P = 1
4793 * 0b01..P = 2
4794 * 0b10..P = 4
4795 * 0b11..P = 8
4796 */
4797#define SYSCON_SYSPLLCTRL_PSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_PSEL_SHIFT)) & SYSCON_SYSPLLCTRL_PSEL_MASK)
4798/*! @} */
4799
4800/*! @name SYSPLLSTAT - PLL status */
4801/*! @{ */
4802#define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U)
4803#define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U)
4804/*! LOCK - PLL0 lock indicator
4805 */
4806#define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK)
4807/*! @} */
4808
4809/*! @name SYSOSCCTRL - system oscillator control */
4810/*! @{ */
4811#define SYSCON_SYSOSCCTRL_BYPASS_MASK (0x1U)
4812#define SYSCON_SYSOSCCTRL_BYPASS_SHIFT (0U)
4813/*! BYPASS - Bypass system oscillator
4814 */
4815#define SYSCON_SYSOSCCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_BYPASS_SHIFT)) & SYSCON_SYSOSCCTRL_BYPASS_MASK)
4816#define SYSCON_SYSOSCCTRL_FREQRANGE_MASK (0x2U)
4817#define SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT (1U)
4818/*! FREQRANGE - oscillator low / high transconductance selection input (Active High) 1-20MHz '0' : 15-50MHz '1'
4819 */
4820#define SYSCON_SYSOSCCTRL_FREQRANGE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT)) & SYSCON_SYSOSCCTRL_FREQRANGE_MASK)
4821/*! @} */
4822
4823/*! @name WDTOSCCTRL - Watchdog oscillator control */
4824/*! @{ */
4825#define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU)
4826#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U)
4827/*! DIVSEL - Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 +
4828 * DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64
4829 */
4830#define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK)
4831#define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x1E0U)
4832#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U)
4833/*! FREQSEL - Frequency select. Selects the frequency of the oscillator. 0x00 = invalid setting when
4834 * watchdog oscillator is running 0x1 = 0.6 MHz 0x2 = 1.05 MHz 0x3 = 1.4 MHz 0x4 = 1.75 MHz 0x5
4835 * = 2.1 MHz 0x6 = 2.4 MHz 0x7 = 2.7 MHz 0x8 = 3.0 MHz 0x9 = 3.25 MHz 0xA = 3.5 MHz 0xB = 3.75
4836 * MHz 0xC = 4.0 MHz 0xD = 4.2 MHz 0xE = 4.4 MHz 0xF = 4.6 MHz
4837 */
4838#define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK)
4839/*! @} */
4840
4841/*! @name SYSRSTSTAT - System reset status register */
4842/*! @{ */
4843#define SYSCON_SYSRSTSTAT_POR_MASK (0x1U)
4844#define SYSCON_SYSRSTSTAT_POR_SHIFT (0U)
4845/*! POR - POR reset status.
4846 * 0b0..No POR detected.
4847 * 0b1..POR detected. Writing a one cl