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1/*
2** ###################################################################
3** Processors: LPC822M101JDH20
4** LPC822M101JHI33
5**
6** Compilers: GNU C Compiler
7** IAR ANSI C/C++ Compiler for ARM
8** Keil ARM C/C++ Compiler
9** MCUXpresso Compiler
10**
11** Reference manual: LPC82x User manual Rev.1.2 5 October 2016
12** Version: rev. 1.1, 2018-02-25
13** Build: b200509
14**
15** Abstract:
16** CMSIS Peripheral Access Layer for LPC822
17**
18** Copyright 1997-2016 Freescale Semiconductor, Inc.
19** Copyright 2016-2020 NXP
20** All rights reserved.
21**
22** SPDX-License-Identifier: BSD-3-Clause
23**
24** http: www.nxp.com
25** mail: [email protected]
26**
27** Revisions:
28** - rev. 1.0 (2018-02-09)
29** Initial version.
30** - rev. 1.1 (2018-02-25)
31** Update some registers according to UM rev 1.2
32**
33** ###################################################################
34*/
35
36/*!
37 * @file LPC822.h
38 * @version 1.1
39 * @date 2018-02-25
40 * @brief CMSIS Peripheral Access Layer for LPC822
41 *
42 * CMSIS Peripheral Access Layer for LPC822
43 */
44
45#ifndef _LPC822_H_
46#define _LPC822_H_ /**< Symbol preventing repeated inclusion */
47
48/** Memory map major version (memory maps with equal major version number are
49 * compatible) */
50#define MCU_MEM_MAP_VERSION 0x0100U
51/** Memory map minor version */
52#define MCU_MEM_MAP_VERSION_MINOR 0x0001U
53
54
55/* ----------------------------------------------------------------------------
56 -- Interrupt vector numbers
57 ---------------------------------------------------------------------------- */
58
59/*!
60 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
61 * @{
62 */
63
64/** Interrupt Number Definitions */
65#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
66
67typedef enum IRQn {
68 /* Auxiliary constants */
69 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
70
71 /* Core interrupts */
72 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
73 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
74 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
75 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
76 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
77
78 /* Device specific interrupts */
79 SPI0_IRQn = 0, /**< SPI0 interrupt */
80 SPI1_IRQn = 1, /**< SPI1 interrupt */
81 Reserved18_IRQn = 2, /**< Reserved interrupt */
82 USART0_IRQn = 3, /**< USART0 interrupt */
83 USART1_IRQn = 4, /**< USART1 interrupt */
84 USART2_IRQn = 5, /**< USART2 interrupt */
85 Reserved22_IRQn = 6, /**< Reserved interrupt */
86 I2C1_IRQn = 7, /**< I2C1 interrupt */
87 I2C0_IRQn = 8, /**< I2C0 interrupt */
88 SCT0_IRQn = 9, /**< State configurable timer interrupt */
89 MRT0_IRQn = 10, /**< Multi-rate timer interrupt */
90 CMP_IRQn = 11, /**< Analog comparator interrupt */
91 WDT_IRQn = 12, /**< Windowed watchdog timer interrupt */
92 BOD_IRQn = 13, /**< BOD interrupts */
93 FLASH_IRQn = 14, /**< flash interrupt */
94 WKT_IRQn = 15, /**< Self-wake-up timer interrupt */
95 ADC0_SEQA_IRQn = 16, /**< ADC0 sequence A completion. */
96 ADC0_SEQB_IRQn = 17, /**< ADC0 sequence B completion. */
97 ADC0_THCMP_IRQn = 18, /**< ADC0 threshold compare and error. */
98 ADC0_OVR_IRQn = 19, /**< ADC0 overrun */
99 DMA0_IRQn = 20, /**< DMA0 interrupt */
100 I2C2_IRQn = 21, /**< I2C2 interrupt */
101 I2C3_IRQn = 22, /**< I2C3 interrupt */
102 Reserved39_IRQn = 23, /**< Reserved interrupt */
103 PIN_INT0_IRQn = 24, /**< Pin interrupt 0 or pattern match engine slice 0 interrupt */
104 PIN_INT1_IRQn = 25, /**< Pin interrupt 1 or pattern match engine slice 1 interrupt */
105 PIN_INT2_IRQn = 26, /**< Pin interrupt 2 or pattern match engine slice 2 interrupt */
106 PIN_INT3_IRQn = 27, /**< Pin interrupt 3 or pattern match engine slice 3 interrupt */
107 PIN_INT4_IRQn = 28, /**< Pin interrupt 4 or pattern match engine slice 4 interrupt */
108 PIN_INT5_IRQn = 29, /**< Pin interrupt 5 or pattern match engine slice 5 interrupt */
109 PIN_INT6_IRQn = 30, /**< Pin interrupt 6 or pattern match engine slice 6 interrupt */
110 PIN_INT7_IRQn = 31 /**< Pin interrupt 7 or pattern match engine slice 7 interrupt */
111} IRQn_Type;
112
113/*!
114 * @}
115 */ /* end of group Interrupt_vector_numbers */
116
117
118/* ----------------------------------------------------------------------------
119 -- Cortex M0 Core Configuration
120 ---------------------------------------------------------------------------- */
121
122/*!
123 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
124 * @{
125 */
126
127#define __CM0PLUS_REV 0x0000 /**< Core revision r0p1 */
128#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
129#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */
130#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
131#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
132
133#include "core_cm0plus.h" /* Core Peripheral Access Layer */
134#include "system_LPC822.h" /* Device specific configuration file */
135
136/*!
137 * @}
138 */ /* end of group Cortex_Core_Configuration */
139
140
141/* ----------------------------------------------------------------------------
142 -- Mapping Information
143 ---------------------------------------------------------------------------- */
144
145/*!
146 * @addtogroup Mapping_Information Mapping Information
147 * @{
148 */
149
150/** Mapping Information */
151/*!
152 * @addtogroup dma_request
153 * @{
154 */
155
156/*******************************************************************************
157 * Definitions
158 ******************************************************************************/
159
160/*!
161 * @brief Structure for the DMA hardware request
162 *
163 * Defines the structure for the DMA hardware request collections. The user can configure the
164 * hardware request to trigger the DMA transfer accordingly. The index
165 * of the hardware request varies according to the to SoC.
166 */
167typedef enum _dma_request_source
168{
169 kDmaRequestUSART0_RX_DMA = 0U, /**< USART0 RX DMA */
170 kDmaRequestUSART0_TX_DMA = 1U, /**< USART0 TX DMA */
171 kDmaRequestUSART1_RX_DMA = 2U, /**< USART1 RX DMA */
172 kDmaRequestUSART1_TX_DMA = 3U, /**< USART1 TX DMA */
173 kDmaRequestUSART2_RX_DMA = 4U, /**< USART2 RX DMA */
174 kDmaRequestUSART2_TX_DMA = 5U, /**< USART2 TX DMA */
175 kDmaRequestSPI0_RX_DMA = 6U, /**< SPI0 RX DMA */
176 kDmaRequestSPI0_TX_DMA = 7U, /**< SPI0 TX DMA */
177 kDmaRequestSPI1_RX_DMA = 8U, /**< SPI1 RX DMA */
178 kDmaRequestSPI1_TX_DMA = 9U, /**< SPI1 TX DMA */
179 kDmaRequestI2C0_SLV_DMA = 10U, /**< I2C0 SLAVE DMA */
180 kDmaRequestI2C0_MST_DMA = 11U, /**< I2C0 MASTER DMA */
181 kDmaRequestI2C1_SLV_DMA = 12U, /**< I2C1 SLAVE DMA */
182 kDmaRequestI2C1_MST_DMA = 13U, /**< I2C1 MASTER DMA */
183 kDmaRequestI2C2_SLV_DMA = 14U, /**< I2C2 SLAVE DMA */
184 kDmaRequestI2C2_MST_DMA = 15U, /**< I2C2 MASTER DMA */
185 kDmaRequestI2C3_SLV_DMA = 16U, /**< I2C3 SLAVE DMA */
186 kDmaRequestI2C3_MST_DMA = 17U, /**< I2C3 MASTER DMA */
187} dma_request_source_t;
188
189/* @} */
190
191
192/*!
193 * @}
194 */ /* end of group Mapping_Information */
195
196
197/* ----------------------------------------------------------------------------
198 -- Device Peripheral Access Layer
199 ---------------------------------------------------------------------------- */
200
201/*!
202 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
203 * @{
204 */
205
206
207/*
208** Start of section using anonymous unions
209*/
210
211#if defined(__ARMCC_VERSION)
212 #if (__ARMCC_VERSION >= 6010050)
213 #pragma clang diagnostic push
214 #else
215 #pragma push
216 #pragma anon_unions
217 #endif
218#elif defined(__GNUC__)
219 /* anonymous unions are enabled by default */
220#elif defined(__IAR_SYSTEMS_ICC__)
221 #pragma language=extended
222#else
223 #error Not supported compiler type
224#endif
225
226/* ----------------------------------------------------------------------------
227 -- ACOMP Peripheral Access Layer
228 ---------------------------------------------------------------------------- */
229
230/*!
231 * @addtogroup ACOMP_Peripheral_Access_Layer ACOMP Peripheral Access Layer
232 * @{
233 */
234
235/** ACOMP - Register Layout Typedef */
236typedef struct {
237 __IO uint32_t CTRL; /**< Comparator control register, offset: 0x0 */
238 __IO uint32_t LAD; /**< Voltage ladder register, offset: 0x4 */
239} ACOMP_Type;
240
241/* ----------------------------------------------------------------------------
242 -- ACOMP Register Masks
243 ---------------------------------------------------------------------------- */
244
245/*!
246 * @addtogroup ACOMP_Register_Masks ACOMP Register Masks
247 * @{
248 */
249
250/*! @name CTRL - Comparator control register */
251/*! @{ */
252#define ACOMP_CTRL_EDGESEL_MASK (0x18U)
253#define ACOMP_CTRL_EDGESEL_SHIFT (3U)
254/*! EDGESEL - This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below):
255 * 0b00..Falling edges
256 * 0b01..Rising edges
257 * 0b10..Both edges
258 * 0b11..Both edges
259 */
260#define ACOMP_CTRL_EDGESEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_EDGESEL_SHIFT)) & ACOMP_CTRL_EDGESEL_MASK)
261#define ACOMP_CTRL_COMPSA_MASK (0x40U)
262#define ACOMP_CTRL_COMPSA_SHIFT (6U)
263/*! COMPSA - Comparator output control
264 * 0b0..Comparator output is used directly.
265 * 0b1..Comparator output is synchronized to the bus clock for output to other modules.
266 */
267#define ACOMP_CTRL_COMPSA(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPSA_SHIFT)) & ACOMP_CTRL_COMPSA_MASK)
268#define ACOMP_CTRL_COMP_VP_SEL_MASK (0x700U)
269#define ACOMP_CTRL_COMP_VP_SEL_SHIFT (8U)
270/*! COMP_VP_SEL - Selects positive voltage input
271 * 0b000..VOLTAGE_LADDER_OUTPUT
272 * 0b001..ACMP_I1
273 * 0b010..ACMP_I2
274 * 0b011..ACMP_I3
275 * 0b100..ACMP_I4
276 * 0b101..Band gap. Internal reference voltage.
277 * 0b110..ADC channel 0 input
278 * 0b111..Reserved
279 */
280#define ACOMP_CTRL_COMP_VP_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMP_VP_SEL_SHIFT)) & ACOMP_CTRL_COMP_VP_SEL_MASK)
281#define ACOMP_CTRL_COMP_VM_SEL_MASK (0x3800U)
282#define ACOMP_CTRL_COMP_VM_SEL_SHIFT (11U)
283/*! COMP_VM_SEL - Selects negative voltage input
284 * 0b000..VOLTAGE_LADDER_OUTPUT
285 * 0b001..ACMP_I1
286 * 0b010..ACMP_I2
287 * 0b011..ACMP_I3
288 * 0b100..ACMP_I4
289 * 0b101..Band gap. Internal reference voltage.
290 * 0b110..ADC channel 0 input
291 * 0b111..Reserved
292 */
293#define ACOMP_CTRL_COMP_VM_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMP_VM_SEL_SHIFT)) & ACOMP_CTRL_COMP_VM_SEL_MASK)
294#define ACOMP_CTRL_EDGECLR_MASK (0x100000U)
295#define ACOMP_CTRL_EDGECLR_SHIFT (20U)
296/*! EDGECLR - Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request,
297 * toggle the EDGECLR bit by first writing a 1 and then a 0.
298 */
299#define ACOMP_CTRL_EDGECLR(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_EDGECLR_SHIFT)) & ACOMP_CTRL_EDGECLR_MASK)
300#define ACOMP_CTRL_COMPSTAT_MASK (0x200000U)
301#define ACOMP_CTRL_COMPSTAT_SHIFT (21U)
302/*! COMPSTAT - Comparator status. This bit reflects the state of the comparator output.
303 */
304#define ACOMP_CTRL_COMPSTAT(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPSTAT_SHIFT)) & ACOMP_CTRL_COMPSTAT_MASK)
305#define ACOMP_CTRL_COMPEDGE_MASK (0x800000U)
306#define ACOMP_CTRL_COMPEDGE_SHIFT (23U)
307/*! COMPEDGE - Comparator edge-detect status.
308 */
309#define ACOMP_CTRL_COMPEDGE(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPEDGE_SHIFT)) & ACOMP_CTRL_COMPEDGE_MASK)
310#define ACOMP_CTRL_HYS_MASK (0x6000000U)
311#define ACOMP_CTRL_HYS_SHIFT (25U)
312/*! HYS - Controls the hysteresis of the comparator. When the comparator is outputting a certain
313 * state, this is the difference between the selected signals, in the opposite direction from the
314 * state being output, that will switch the output.
315 * 0b00..None (the output will switch as the voltages cross)
316 * 0b01..5 mv
317 * 0b10..10 mv
318 * 0b11..20 mv
319 */
320#define ACOMP_CTRL_HYS(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_HYS_SHIFT)) & ACOMP_CTRL_HYS_MASK)
321/*! @} */
322
323/*! @name LAD - Voltage ladder register */
324/*! @{ */
325#define ACOMP_LAD_LADEN_MASK (0x1U)
326#define ACOMP_LAD_LADEN_SHIFT (0U)
327/*! LADEN - Voltage ladder enable
328 */
329#define ACOMP_LAD_LADEN(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADEN_SHIFT)) & ACOMP_LAD_LADEN_MASK)
330#define ACOMP_LAD_LADSEL_MASK (0x3EU)
331#define ACOMP_LAD_LADSEL_SHIFT (1U)
332/*! LADSEL - Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000
333 * = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref
334 */
335#define ACOMP_LAD_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADSEL_SHIFT)) & ACOMP_LAD_LADSEL_MASK)
336#define ACOMP_LAD_LADREF_MASK (0x40U)
337#define ACOMP_LAD_LADREF_SHIFT (6U)
338/*! LADREF - Selects the reference voltage Vref for the voltage ladder.
339 * 0b0..Supply pin VDD
340 * 0b1..VDDCMP pin
341 */
342#define ACOMP_LAD_LADREF(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADREF_SHIFT)) & ACOMP_LAD_LADREF_MASK)
343/*! @} */
344
345
346/*!
347 * @}
348 */ /* end of group ACOMP_Register_Masks */
349
350
351/* ACOMP - Peripheral instance base addresses */
352/** Peripheral ACOMP base address */
353#define ACOMP_BASE (0x40024000u)
354/** Peripheral ACOMP base pointer */
355#define ACOMP ((ACOMP_Type *)ACOMP_BASE)
356/** Array initializer of ACOMP peripheral base addresses */
357#define ACOMP_BASE_ADDRS { ACOMP_BASE }
358/** Array initializer of ACOMP peripheral base pointers */
359#define ACOMP_BASE_PTRS { ACOMP }
360/** Interrupt vectors for the ACOMP peripheral type */
361#define ACOMP_IRQS { CMP_IRQn }
362
363/*!
364 * @}
365 */ /* end of group ACOMP_Peripheral_Access_Layer */
366
367
368/* ----------------------------------------------------------------------------
369 -- ADC Peripheral Access Layer
370 ---------------------------------------------------------------------------- */
371
372/*!
373 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
374 * @{
375 */
376
377/** ADC - Register Layout Typedef */
378typedef struct {
379 __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
380 uint8_t RESERVED_0[4];
381 __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
382 __IO uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
383 uint8_t RESERVED_1[8];
384 __I uint32_t DAT[12]; /**< ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N., array offset: 0x20, array step: 0x4 */
385 __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
386 __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
387 __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
388 __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
389 __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
390 __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
391 __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
392 __IO uint32_t TRM; /**< ADC Startup register., offset: 0x6C */
393} ADC_Type;
394
395/* ----------------------------------------------------------------------------
396 -- ADC Register Masks
397 ---------------------------------------------------------------------------- */
398
399/*!
400 * @addtogroup ADC_Register_Masks ADC Register Masks
401 * @{
402 */
403
404/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
405/*! @{ */
406#define ADC_CTRL_CLKDIV_MASK (0xFFU)
407#define ADC_CTRL_CLKDIV_SHIFT (0U)
408/*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce
409 * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically,
410 * software should program the smallest value in this field that yields this maximum clock rate or
411 * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may
412 * be desirable. This field is ignored in the asynchronous operating mode.
413 */
414#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
415#define ADC_CTRL_LPWRMODE_MASK (0x400U)
416#define ADC_CTRL_LPWRMODE_SHIFT (10U)
417/*! LPWRMODE - The low-power ADC mode
418 * 0b0..The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested.
419 * 0b1..The low-power ADC mode is enabled. The analog circuitry is automatically powered-down when no conversions
420 * are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is
421 * enabled. After the required start-up time, the requested conversion will be launched. Once the conversion
422 * completes, the analog-circuitry will again be powered-down provided no further conversions are pending.
423 * Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are
424 * required relatively infrequently. The penalty for using this mode is an approximately FIFTEEN ADC CLOCK delay (30
425 * clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger
426 * event occurs until sampling of the A/D input commences. Note: This mode will NOT power-up the A/D if the
427 * ADC_ENA bit is low.
428 */
429#define ADC_CTRL_LPWRMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_LPWRMODE_SHIFT)) & ADC_CTRL_LPWRMODE_MASK)
430#define ADC_CTRL_CALMODE_MASK (0x40000000U)
431#define ADC_CTRL_CALMODE_SHIFT (30U)
432/*! CALMODE - Writing a '1' to this bit will initiate a sef-calibration cycle. This bit will be
433 * automatically cleared by hardware after the calibration cycle is complete. Note: Other bits of
434 * this register may be written to concurrently with setting this bit, however once this bit has
435 * been set no further writes to this register are permitted unitl the full calibration cycle has
436 * ended.
437 */
438#define ADC_CTRL_CALMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALMODE_SHIFT)) & ADC_CTRL_CALMODE_MASK)
439/*! @} */
440
441/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
442/*! @{ */
443#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU)
444#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U)
445/*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this
446 * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be
447 * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1
448 * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via
449 * software command, ADC conversions will be performed on each enabled channel, in sequence,
450 * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31)
451 * is LOW. It is allowed to change this field and set bit 31 in the same write.
452 */
453#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
454#define ADC_SEQ_CTRL_TRIGGER_MASK (0x7000U)
455#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U)
456/*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion
457 * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order
458 * to avoid generating a spurious trigger, it is recommended writing to this field only when
459 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
460 */
461#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
462#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U)
463#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U)
464/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In
465 * order to avoid generating a spurious trigger, it is recommended writing to this field only when
466 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
467 * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
468 * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
469 */
470#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
471#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U)
472#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U)
473/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization
474 * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a
475 * conversion. There are slightly different criteria for whether or not this bit can be set
476 * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0):
477 * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already
478 * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer).
479 * Whether this bit is set or not, a trigger pulse must be maintained for at least one system
480 * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be
481 * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse
482 * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and
483 * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be
484 * maintained for one system clock period.
485 * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled.
486 * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled.
487 */
488#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
489#define ADC_SEQ_CTRL_START_MASK (0x4000000U)
490#define ADC_SEQ_CTRL_START_SHIFT (26U)
491/*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The
492 * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this
493 * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a
494 * conversion sequence. It will consequently always read back as a zero.
495 */
496#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
497#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U)
498#define ADC_SEQ_CTRL_BURST_SHIFT (27U)
499/*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled
500 * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions
501 * can be halted by clearing this bit. The sequence currently in progress will be completed before
502 * conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
503 */
504#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
505#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U)
506#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U)
507/*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a
508 * single conversion on the next channel in the sequence instead of the default response of
509 * launching an entire sequence of conversions. Once all of the channels comprising a sequence have
510 * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled
511 * channel. Interrupt generation will still occur either after each individual conversion or at
512 * the end of the entire sequence, depending on the state of the MODE bit.
513 */
514#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
515#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U)
516#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U)
517/*! LOWPRIO - Set priority for sequence A.
518 * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
519 * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence
520 * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion
521 * currently in progress will be terminated. The A sequence that was interrupted will automatically resume
522 * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the
523 * conversion sequence will resume from that point.
524 */
525#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
526#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U)
527#define ADC_SEQ_CTRL_MODE_SHIFT (30U)
528/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence
529 * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each
530 * conversion, or the individual channel result registers at the end of the entire sequence. Impacts
531 * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which
532 * overrun conditions contribute to an overrun interrupt as described below.
533 * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC
534 * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The
535 * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger
536 * if enabled.
537 * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A
538 * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in
539 * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun
540 * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
541 */
542#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
543#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U)
544#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U)
545/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be
546 * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state
547 * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered
548 * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care
549 * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE
550 * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be
551 * triggered immediately upon being enabled.
552 * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence
553 * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is
554 * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
555 * 0b1..Enabled. Sequence n is enabled.
556 */
557#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
558/*! @} */
559
560/* The count of ADC_SEQ_CTRL */
561#define ADC_SEQ_CTRL_COUNT (2U)
562
563/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
564/*! @{ */
565#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U)
566#define ADC_SEQ_GDAT_RESULT_SHIFT (4U)
567/*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion
568 * performed under conversion sequence associated with this register. The result is a binary
569 * fraction representing the voltage on the currently-selected input channel as it falls within the
570 * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less
571 * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input
572 * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this
573 * result has not yet been read.
574 */
575#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
576#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U)
577#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U)
578/*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or
579 * within the range established by the designated threshold comparison registers (THRn_LOW and
580 * THRn_HIGH).
581 */
582#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
583#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U)
584#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U)
585/*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a
586 * crossing of the threshold level established by the designated LOW threshold comparison register
587 * (THRn_LOW) and, if so, in what direction the crossing occurred.
588 */
589#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
590#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U)
591#define ADC_SEQ_GDAT_CHN_SHIFT (26U)
592/*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000
593 * identifies channel 0, 0001 channel 1, etc.).
594 */
595#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
596#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U)
597#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U)
598/*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a
599 * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along
600 * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun
601 * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set
602 * to '0' (and if the overrun interrupt is enabled).
603 */
604#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
605#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U)
606#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U)
607/*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded
608 * into the RESULT field. It is cleared whenever this register is read. This bit will cause a
609 * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that
610 * sequence is set to 0 (and if the interrupt is enabled).
611 */
612#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
613/*! @} */
614
615/* The count of ADC_SEQ_GDAT */
616#define ADC_SEQ_GDAT_COUNT (2U)
617
618/*! @name DAT - ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. */
619/*! @{ */
620#define ADC_DAT_RESULT_MASK (0xFFF0U)
621#define ADC_DAT_RESULT_SHIFT (4U)
622/*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed
623 * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin,
624 * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on
625 * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that
626 * the voltage on the input was close to, equal to, or greater than that on VREFP.
627 */
628#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
629#define ADC_DAT_THCMPRANGE_MASK (0x30000U)
630#define ADC_DAT_THCMPRANGE_SHIFT (16U)
631/*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion
632 * was greater than or equal to the value programmed into the designated LOW threshold register
633 * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold
634 * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value
635 * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last
636 * completed conversion was greater than the value programmed into the designated HIGH threshold
637 * register (THRn_HIGH). 0x3 = Reserved.
638 */
639#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
640#define ADC_DAT_THCMPCROSS_MASK (0xC0000U)
641#define ADC_DAT_THCMPCROSS_SHIFT (18U)
642/*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The
643 * most recent completed conversion on this channel had the same relationship (above or below) to
644 * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the
645 * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing
646 * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the
647 * previous sample on this channel was above the threshold value established by the designated LOW
648 * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward
649 * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred
650 * - i.e. the previous sample on this channel was below the threshold value established by the
651 * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
652 */
653#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
654#define ADC_DAT_CHANNEL_MASK (0x3C000000U)
655#define ADC_DAT_CHANNEL_SHIFT (26U)
656/*! CHANNEL - This field is hard-coded to contain the channel number that this particular register
657 * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1
658 * register, etc)
659 */
660#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
661#define ADC_DAT_OVERRUN_MASK (0x40000000U)
662#define ADC_DAT_OVERRUN_SHIFT (30U)
663/*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and
664 * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit
665 * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when
666 * the data related to this channel is read from either of the global SEQn_GDAT registers. This
667 * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if
668 * the overrun interrupt is enabled. While it is allowed to include the same channels in both
669 * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the
670 * data registers associated with any of the channels that are shared between the two sequences. Any
671 * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
672 */
673#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
674#define ADC_DAT_DATAVALID_MASK (0x80000000U)
675#define ADC_DAT_DATAVALID_SHIFT (31U)
676/*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is
677 * cleared whenever this register is read or when the data related to this channel is read from
678 * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in
679 * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in
680 * the data registers associated with any of the channels that are shared between the two
681 * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
682 */
683#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
684/*! @} */
685
686/* The count of ADC_DAT */
687#define ADC_DAT_COUNT (12U)
688
689/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
690/*! @{ */
691#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U)
692#define ADC_THR0_LOW_THRLOW_SHIFT (4U)
693/*! THRLOW - Low threshold value against which ADC results will be compared
694 */
695#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
696/*! @} */
697
698/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
699/*! @{ */
700#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U)
701#define ADC_THR1_LOW_THRLOW_SHIFT (4U)
702/*! THRLOW - Low threshold value against which ADC results will be compared
703 */
704#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
705/*! @} */
706
707/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
708/*! @{ */
709#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U)
710#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U)
711/*! THRHIGH - High threshold value against which ADC results will be compared
712 */
713#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
714/*! @} */
715
716/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
717/*! @{ */
718#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U)
719#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U)
720/*! THRHIGH - High threshold value against which ADC results will be compared
721 */
722#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
723/*! @} */
724
725/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
726/*! @{ */
727#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U)
728#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U)
729/*! CH0_THRSEL - Threshold select for channel 0.
730 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
731 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
732 */
733#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
734#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U)
735#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U)
736/*! CH1_THRSEL - Threshold select for channel 1
737 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
738 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
739 */
740#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
741#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U)
742#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U)
743/*! CH2_THRSEL - Threshold select for channel 2.
744 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
745 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
746 */
747#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
748#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U)
749#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U)
750/*! CH3_THRSEL - Threshold select for channel 3.
751 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
752 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
753 */
754#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
755#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U)
756#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U)
757/*! CH4_THRSEL - Threshold select for channel 4.
758 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
759 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
760 */
761#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
762#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U)
763#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U)
764/*! CH5_THRSEL - Threshold select for channel 5.
765 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
766 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
767 */
768#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
769#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U)
770#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U)
771/*! CH6_THRSEL - Threshold select for channel 6.
772 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
773 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
774 */
775#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
776#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U)
777#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U)
778/*! CH7_THRSEL - Threshold select for channel 7.
779 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
780 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
781 */
782#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
783#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U)
784#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U)
785/*! CH8_THRSEL - Threshold select for channel 8.
786 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
787 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
788 */
789#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
790#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U)
791#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U)
792/*! CH9_THRSEL - Threshold select for channel 9.
793 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
794 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
795 */
796#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
797#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U)
798#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U)
799/*! CH10_THRSEL - Threshold select for channel 10.
800 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
801 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
802 */
803#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
804#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U)
805#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U)
806/*! CH11_THRSEL - Threshold select for channel 11.
807 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
808 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
809 */
810#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
811/*! @} */
812
813/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
814/*! @{ */
815#define ADC_INTEN_SEQA_INTEN_MASK (0x1U)
816#define ADC_INTEN_SEQA_INTEN_SHIFT (0U)
817/*! SEQA_INTEN - Sequence A interrupt enable.
818 * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled.
819 * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of
820 * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of
821 * conversions, depending on the MODE bit in the SEQA_CTRL register.
822 */
823#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
824#define ADC_INTEN_SEQB_INTEN_MASK (0x2U)
825#define ADC_INTEN_SEQB_INTEN_SHIFT (1U)
826/*! SEQB_INTEN - Sequence B interrupt enable.
827 * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled.
828 * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of
829 * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of
830 * conversions, depending on the MODE bit in the SEQB_CTRL register.
831 */
832#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
833#define ADC_INTEN_OVR_INTEN_MASK (0x4U)
834#define ADC_INTEN_OVR_INTEN_SHIFT (2U)
835/*! OVR_INTEN - Overrun interrupt enable.
836 * 0b0..Disabled. The overrun interrupt is disabled.
837 * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel
838 * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular
839 * sequence is 0, then an overrun in the global data register for that sequence will also cause this
840 * interrupt/DMA trigger to be asserted.
841 */
842#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
843#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U)
844#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U)
845/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0.
846 * 0b00..Disabled.
847 * 0b01..Outside threshold.
848 * 0b10..Crossing threshold.
849 * 0b11..Reserved
850 */
851#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
852#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U)
853#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U)
854/*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable.
855 * 0b00..Disabled.
856 * 0b01..Outside threshold.
857 * 0b10..Crossing threshold.
858 * 0b11..Reserved
859 */
860#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
861#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U)
862#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U)
863/*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable.
864 * 0b00..Disabled.
865 * 0b01..Outside threshold.
866 * 0b10..Crossing threshold.
867 * 0b11..Reserved
868 */
869#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
870#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U)
871#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U)
872/*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable.
873 * 0b00..Disabled.
874 * 0b01..Outside threshold.
875 * 0b10..Crossing threshold.
876 * 0b11..Reserved
877 */
878#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
879#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U)
880#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U)
881/*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable.
882 * 0b00..Disabled.
883 * 0b01..Outside threshold.
884 * 0b10..Crossing threshold.
885 * 0b11..Reserved
886 */
887#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
888#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U)
889#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U)
890/*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable.
891 * 0b00..Disabled.
892 * 0b01..Outside threshold.
893 * 0b10..Crossing threshold.
894 * 0b11..Reserved
895 */
896#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
897#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U)
898#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U)
899/*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable.
900 * 0b00..Disabled.
901 * 0b01..Outside threshold.
902 * 0b10..Crossing threshold.
903 * 0b11..Reserved
904 */
905#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
906#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U)
907#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U)
908/*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable.
909 * 0b00..Disabled.
910 * 0b01..Outside threshold.
911 * 0b10..Crossing threshold.
912 * 0b11..Reserved
913 */
914#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
915#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U)
916#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U)
917/*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable.
918 * 0b00..Disabled.
919 * 0b01..Outside threshold.
920 * 0b10..Crossing threshold.
921 * 0b11..Reserved
922 */
923#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
924#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U)
925#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U)
926/*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable.
927 * 0b00..Disabled.
928 * 0b01..Outside threshold.
929 * 0b10..Crossing threshold.
930 * 0b11..Reserved
931 */
932#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
933#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U)
934#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U)
935/*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable.
936 * 0b00..Disabled.
937 * 0b01..Outside threshold.
938 * 0b10..Crossing threshold.
939 * 0b11..Reserved
940 */
941#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
942#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U)
943#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U)
944/*! ADCMPINTEN11 - Channel 11 threshold comparison interrupt enable.
945 * 0b00..Disabled.
946 * 0b01..Outside threshold.
947 * 0b10..Crossing threshold.
948 * 0b11..Reserved
949 */
950#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
951/*! @} */
952
953/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
954/*! @{ */
955#define ADC_FLAGS_THCMP0_MASK (0x1U)
956#define ADC_FLAGS_THCMP0_SHIFT (0U)
957/*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or
958 * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by
959 * writing a 1.
960 */
961#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
962#define ADC_FLAGS_THCMP1_MASK (0x2U)
963#define ADC_FLAGS_THCMP1_SHIFT (1U)
964/*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0.
965 */
966#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
967#define ADC_FLAGS_THCMP2_MASK (0x4U)
968#define ADC_FLAGS_THCMP2_SHIFT (2U)
969/*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0.
970 */
971#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
972#define ADC_FLAGS_THCMP3_MASK (0x8U)
973#define ADC_FLAGS_THCMP3_SHIFT (3U)
974/*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0.
975 */
976#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
977#define ADC_FLAGS_THCMP4_MASK (0x10U)
978#define ADC_FLAGS_THCMP4_SHIFT (4U)
979/*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0.
980 */
981#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
982#define ADC_FLAGS_THCMP5_MASK (0x20U)
983#define ADC_FLAGS_THCMP5_SHIFT (5U)
984/*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0.
985 */
986#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
987#define ADC_FLAGS_THCMP6_MASK (0x40U)
988#define ADC_FLAGS_THCMP6_SHIFT (6U)
989/*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0.
990 */
991#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
992#define ADC_FLAGS_THCMP7_MASK (0x80U)
993#define ADC_FLAGS_THCMP7_SHIFT (7U)
994/*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0.
995 */
996#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
997#define ADC_FLAGS_THCMP8_MASK (0x100U)
998#define ADC_FLAGS_THCMP8_SHIFT (8U)
999/*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0.
1000 */
1001#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
1002#define ADC_FLAGS_THCMP9_MASK (0x200U)
1003#define ADC_FLAGS_THCMP9_SHIFT (9U)
1004/*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0.
1005 */
1006#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
1007#define ADC_FLAGS_THCMP10_MASK (0x400U)
1008#define ADC_FLAGS_THCMP10_SHIFT (10U)
1009/*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0.
1010 */
1011#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
1012#define ADC_FLAGS_THCMP11_MASK (0x800U)
1013#define ADC_FLAGS_THCMP11_SHIFT (11U)
1014/*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0.
1015 */
1016#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
1017#define ADC_FLAGS_OVERRUN0_MASK (0x1000U)
1018#define ADC_FLAGS_OVERRUN0_SHIFT (12U)
1019/*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0
1020 */
1021#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
1022#define ADC_FLAGS_OVERRUN1_MASK (0x2000U)
1023#define ADC_FLAGS_OVERRUN1_SHIFT (13U)
1024/*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1
1025 */
1026#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
1027#define ADC_FLAGS_OVERRUN2_MASK (0x4000U)
1028#define ADC_FLAGS_OVERRUN2_SHIFT (14U)
1029/*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2
1030 */
1031#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
1032#define ADC_FLAGS_OVERRUN3_MASK (0x8000U)
1033#define ADC_FLAGS_OVERRUN3_SHIFT (15U)
1034/*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3
1035 */
1036#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
1037#define ADC_FLAGS_OVERRUN4_MASK (0x10000U)
1038#define ADC_FLAGS_OVERRUN4_SHIFT (16U)
1039/*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4
1040 */
1041#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
1042#define ADC_FLAGS_OVERRUN5_MASK (0x20000U)
1043#define ADC_FLAGS_OVERRUN5_SHIFT (17U)
1044/*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5
1045 */
1046#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
1047#define ADC_FLAGS_OVERRUN6_MASK (0x40000U)
1048#define ADC_FLAGS_OVERRUN6_SHIFT (18U)
1049/*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6
1050 */
1051#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
1052#define ADC_FLAGS_OVERRUN7_MASK (0x80000U)
1053#define ADC_FLAGS_OVERRUN7_SHIFT (19U)
1054/*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7
1055 */
1056#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
1057#define ADC_FLAGS_OVERRUN8_MASK (0x100000U)
1058#define ADC_FLAGS_OVERRUN8_SHIFT (20U)
1059/*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8
1060 */
1061#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
1062#define ADC_FLAGS_OVERRUN9_MASK (0x200000U)
1063#define ADC_FLAGS_OVERRUN9_SHIFT (21U)
1064/*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9
1065 */
1066#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
1067#define ADC_FLAGS_OVERRUN10_MASK (0x400000U)
1068#define ADC_FLAGS_OVERRUN10_SHIFT (22U)
1069/*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10
1070 */
1071#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
1072#define ADC_FLAGS_OVERRUN11_MASK (0x800000U)
1073#define ADC_FLAGS_OVERRUN11_SHIFT (23U)
1074/*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11
1075 */
1076#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
1077#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U)
1078#define ADC_FLAGS_SEQA_OVR_SHIFT (24U)
1079/*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register
1080 */
1081#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
1082#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U)
1083#define ADC_FLAGS_SEQB_OVR_SHIFT (25U)
1084/*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register
1085 */
1086#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
1087#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U)
1088#define ADC_FLAGS_SEQA_INT_SHIFT (28U)
1089/*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0,
1090 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which
1091 * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared
1092 * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register
1093 * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be
1094 * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN
1095 * register.
1096 */
1097#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
1098#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U)
1099#define ADC_FLAGS_SEQB_INT_SHIFT (29U)
1100/*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0,
1101 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which
1102 * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared
1103 * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register
1104 * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be
1105 * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN
1106 * register.
1107 */
1108#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
1109#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U)
1110#define ADC_FLAGS_THCMP_INT_SHIFT (30U)
1111/*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in
1112 * the lower bits of this register are set to 1 (due to an enabled out-of-range or
1113 * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be
1114 * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared
1115 * when all of the individual threshold flags are cleared via writing 1s to those bits.
1116 */
1117#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
1118#define ADC_FLAGS_OVR_INT_MASK (0x80000000U)
1119#define ADC_FLAGS_OVR_INT_SHIFT (31U)
1120/*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data
1121 * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers
1122 * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this
1123 * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all
1124 * of the individual overrun bits have been cleared via reading the corresponding data registers.
1125 */
1126#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
1127/*! @} */
1128
1129/*! @name TRM - ADC Startup register. */
1130/*! @{ */
1131#define ADC_TRM_VRANGE_MASK (0x20U)
1132#define ADC_TRM_VRANGE_SHIFT (5U)
1133/*! VRANGE - 2.4V to 3.6V Vdd range: This bit MUST be set to '1' if operation below 2.7V is to be
1134 * used. Failure to set this bit will result in invalid ADC results. Note: This bit will not be
1135 * spec'd on parts that do not support operation below 2.7V
1136 * 0b0..High voltage
1137 * 0b1..Low voltage
1138 */
1139#define ADC_TRM_VRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_TRM_VRANGE_SHIFT)) & ADC_TRM_VRANGE_MASK)
1140/*! @} */
1141
1142
1143/*!
1144 * @}
1145 */ /* end of group ADC_Register_Masks */
1146
1147
1148/* ADC - Peripheral instance base addresses */
1149/** Peripheral ADC0 base address */
1150#define ADC0_BASE (0x4001C000u)
1151/** Peripheral ADC0 base pointer */
1152#define ADC0 ((ADC_Type *)ADC0_BASE)
1153/** Array initializer of ADC peripheral base addresses */
1154#define ADC_BASE_ADDRS { ADC0_BASE }
1155/** Array initializer of ADC peripheral base pointers */
1156#define ADC_BASE_PTRS { ADC0 }
1157/** Interrupt vectors for the ADC peripheral type */
1158#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
1159#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn }
1160
1161/*!
1162 * @}
1163 */ /* end of group ADC_Peripheral_Access_Layer */
1164
1165
1166/* ----------------------------------------------------------------------------
1167 -- CRC Peripheral Access Layer
1168 ---------------------------------------------------------------------------- */
1169
1170/*!
1171 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
1172 * @{
1173 */
1174
1175/** CRC - Register Layout Typedef */
1176typedef struct {
1177 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
1178 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
1179 union { /* offset: 0x8 */
1180 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
1181 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
1182 };
1183} CRC_Type;
1184
1185/* ----------------------------------------------------------------------------
1186 -- CRC Register Masks
1187 ---------------------------------------------------------------------------- */
1188
1189/*!
1190 * @addtogroup CRC_Register_Masks CRC Register Masks
1191 * @{
1192 */
1193
1194/*! @name MODE - CRC mode register */
1195/*! @{ */
1196#define CRC_MODE_CRC_POLY_MASK (0x3U)
1197#define CRC_MODE_CRC_POLY_SHIFT (0U)
1198/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
1199 */
1200#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
1201#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
1202#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
1203/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
1204 */
1205#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
1206#define CRC_MODE_CMPL_WR_MASK (0x8U)
1207#define CRC_MODE_CMPL_WR_SHIFT (3U)
1208/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
1209 */
1210#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
1211#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
1212#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
1213/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
1214 */
1215#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
1216#define CRC_MODE_CMPL_SUM_MASK (0x20U)
1217#define CRC_MODE_CMPL_SUM_SHIFT (5U)
1218/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
1219 */
1220#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
1221/*! @} */
1222
1223/*! @name SEED - CRC seed register */
1224/*! @{ */
1225#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
1226#define CRC_SEED_CRC_SEED_SHIFT (0U)
1227/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
1228 * selected bit order and 1's complement pre-processes. A write access to this register will
1229 * overrule the CRC calculation in progresses.
1230 */
1231#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
1232/*! @} */
1233
1234/*! @name SUM - CRC checksum register */
1235/*! @{ */
1236#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
1237#define CRC_SUM_CRC_SUM_SHIFT (0U)
1238/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
1239 */
1240#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
1241/*! @} */
1242
1243/*! @name WR_DATA - CRC data register */
1244/*! @{ */
1245#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
1246#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
1247/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
1248 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
1249 * accept back-to-back transactions.
1250 */
1251#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
1252/*! @} */
1253
1254
1255/*!
1256 * @}
1257 */ /* end of group CRC_Register_Masks */
1258
1259
1260/* CRC - Peripheral instance base addresses */
1261/** Peripheral CRC base address */
1262#define CRC_BASE (0x50000000u)
1263/** Peripheral CRC base pointer */
1264#define CRC ((CRC_Type *)CRC_BASE)
1265/** Array initializer of CRC peripheral base addresses */
1266#define CRC_BASE_ADDRS { CRC_BASE }
1267/** Array initializer of CRC peripheral base pointers */
1268#define CRC_BASE_PTRS { CRC }
1269
1270/*!
1271 * @}
1272 */ /* end of group CRC_Peripheral_Access_Layer */
1273
1274
1275/* ----------------------------------------------------------------------------
1276 -- DMA Peripheral Access Layer
1277 ---------------------------------------------------------------------------- */
1278
1279/*!
1280 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
1281 * @{
1282 */
1283
1284/** DMA - Register Layout Typedef */
1285typedef struct {
1286 __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
1287 __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
1288 __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
1289 uint8_t RESERVED_0[20];
1290 struct { /* offset: 0x20, array step: 0x5C */
1291 __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
1292 uint8_t RESERVED_0[4];
1293 __IO uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
1294 uint8_t RESERVED_1[4];
1295 __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
1296 uint8_t RESERVED_2[4];
1297 __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
1298 uint8_t RESERVED_3[4];
1299 __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
1300 uint8_t RESERVED_4[4];
1301 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
1302 uint8_t RESERVED_5[4];
1303 __IO uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
1304 uint8_t RESERVED_6[4];
1305 __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
1306 uint8_t RESERVED_7[4];
1307 __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
1308 uint8_t RESERVED_8[4];
1309 __IO uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
1310 uint8_t RESERVED_9[4];
1311 __IO uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
1312 uint8_t RESERVED_10[4];
1313 __IO uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
1314 } COMMON[1];
1315 uint8_t RESERVED_1[900];
1316 struct { /* offset: 0x400, array step: 0x10 */
1317 __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
1318 __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
1319 __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
1320 uint8_t RESERVED_0[4];
1321 } CHANNEL[18];
1322} DMA_Type;
1323
1324/* ----------------------------------------------------------------------------
1325 -- DMA Register Masks
1326 ---------------------------------------------------------------------------- */
1327
1328/*!
1329 * @addtogroup DMA_Register_Masks DMA Register Masks
1330 * @{
1331 */
1332
1333/*! @name CTRL - DMA control. */
1334/*! @{ */
1335#define DMA_CTRL_ENABLE_MASK (0x1U)
1336#define DMA_CTRL_ENABLE_SHIFT (0U)
1337/*! ENABLE - DMA controller master enable.
1338 * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
1339 * disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
1340 * 0b1..Enabled. The DMA controller is enabled.
1341 */
1342#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
1343/*! @} */
1344
1345/*! @name INTSTAT - Interrupt status. */
1346/*! @{ */
1347#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
1348#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
1349/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
1350 * 0b0..Not pending. No enabled interrupts are pending.
1351 * 0b1..Pending. At least one enabled interrupt is pending.
1352 */
1353#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
1354#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
1355#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
1356/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
1357 * 0b0..Not pending. No error interrupts are pending.
1358 * 0b1..Pending. At least one error interrupt is pending.
1359 */
1360#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
1361/*! @} */
1362
1363/*! @name SRAMBASE - SRAM address of the channel configuration table. */
1364/*! @{ */
1365#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
1366#define DMA_SRAMBASE_OFFSET_SHIFT (9U)
1367/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
1368 * table must begin on a 512 byte boundary.
1369 */
1370#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
1371/*! @} */
1372
1373/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
1374/*! @{ */
1375#define DMA_COMMON_ENABLESET_ENA_MASK (0x3FFFFU)
1376#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
1377/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
1378 * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
1379 */
1380#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
1381/*! @} */
1382
1383/* The count of DMA_COMMON_ENABLESET */
1384#define DMA_COMMON_ENABLESET_COUNT (1U)
1385
1386/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
1387/*! @{ */
1388#define DMA_COMMON_ENABLECLR_CLR_MASK (0x3FFFFU)
1389#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
1390/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
1391 * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
1392 * are reserved.
1393 */
1394#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
1395/*! @} */
1396
1397/* The count of DMA_COMMON_ENABLECLR */
1398#define DMA_COMMON_ENABLECLR_COUNT (1U)
1399
1400/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
1401/*! @{ */
1402#define DMA_COMMON_ACTIVE_ACT_MASK (0x3FFFFU)
1403#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
1404/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
1405 * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
1406 */
1407#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
1408/*! @} */
1409
1410/* The count of DMA_COMMON_ACTIVE */
1411#define DMA_COMMON_ACTIVE_COUNT (1U)
1412
1413/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
1414/*! @{ */
1415#define DMA_COMMON_BUSY_BSY_MASK (0x3FFFFU)
1416#define DMA_COMMON_BUSY_BSY_SHIFT (0U)
1417/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
1418 * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
1419 */
1420#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
1421/*! @} */
1422
1423/* The count of DMA_COMMON_BUSY */
1424#define DMA_COMMON_BUSY_COUNT (1U)
1425
1426/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
1427/*! @{ */
1428#define DMA_COMMON_ERRINT_ERR_MASK (0x3FFFFU)
1429#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
1430/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
1431 * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
1432 * not active. 1 = error interrupt is active.
1433 */
1434#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
1435/*! @} */
1436
1437/* The count of DMA_COMMON_ERRINT */
1438#define DMA_COMMON_ERRINT_COUNT (1U)
1439
1440/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
1441/*! @{ */
1442#define DMA_COMMON_INTENSET_INTEN_MASK (0x3FFFFU)
1443#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
1444/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
1445 * number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
1446 * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
1447 */
1448#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
1449/*! @} */
1450
1451/* The count of DMA_COMMON_INTENSET */
1452#define DMA_COMMON_INTENSET_COUNT (1U)
1453
1454/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
1455/*! @{ */
1456#define DMA_COMMON_INTENCLR_CLR_MASK (0x3FFFFU)
1457#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
1458/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
1459 * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
1460 * reserved.
1461 */
1462#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
1463/*! @} */
1464
1465/* The count of DMA_COMMON_INTENCLR */
1466#define DMA_COMMON_INTENCLR_COUNT (1U)
1467
1468/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
1469/*! @{ */
1470#define DMA_COMMON_INTA_IA_MASK (0x3FFFFU)
1471#define DMA_COMMON_INTA_IA_SHIFT (0U)
1472/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
1473 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
1474 * interrupt A is not active. 1 = the DMA channel interrupt A is active.
1475 */
1476#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
1477/*! @} */
1478
1479/* The count of DMA_COMMON_INTA */
1480#define DMA_COMMON_INTA_COUNT (1U)
1481
1482/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
1483/*! @{ */
1484#define DMA_COMMON_INTB_IB_MASK (0x3FFFFU)
1485#define DMA_COMMON_INTB_IB_SHIFT (0U)
1486/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
1487 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
1488 * interrupt B is not active. 1 = the DMA channel interrupt B is active.
1489 */
1490#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
1491/*! @} */
1492
1493/* The count of DMA_COMMON_INTB */
1494#define DMA_COMMON_INTB_COUNT (1U)
1495
1496/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
1497/*! @{ */
1498#define DMA_COMMON_SETVALID_SV_MASK (0x3FFFFU)
1499#define DMA_COMMON_SETVALID_SV_SHIFT (0U)
1500/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
1501 * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
1502 * VALIDPENDING control bit for DMA channel n
1503 */
1504#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
1505/*! @} */
1506
1507/* The count of DMA_COMMON_SETVALID */
1508#define DMA_COMMON_SETVALID_COUNT (1U)
1509
1510/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
1511/*! @{ */
1512#define DMA_COMMON_SETTRIG_TRIG_MASK (0x3FFFFU)
1513#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
1514/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
1515 * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
1516 * sets the TRIG bit for DMA channel n.
1517 */
1518#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
1519/*! @} */
1520
1521/* The count of DMA_COMMON_SETTRIG */
1522#define DMA_COMMON_SETTRIG_COUNT (1U)
1523
1524/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
1525/*! @{ */
1526#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0x3FFFFU)
1527#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
1528/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
1529 * 1 = aborts DMA operations on channel n.
1530 */
1531#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
1532/*! @} */
1533
1534/* The count of DMA_COMMON_ABORT */
1535#define DMA_COMMON_ABORT_COUNT (1U)
1536
1537/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
1538/*! @{ */
1539#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
1540#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
1541/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
1542 * move, any peripheral DMA request associated with that channel can be disabled to prevent any
1543 * interaction between the peripheral and the DMA controller.
1544 * 0b0..Disabled. Peripheral DMA requests are disabled.
1545 * 0b1..Enabled. Peripheral DMA requests are enabled.
1546 */
1547#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
1548#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
1549#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
1550/*! HWTRIGEN - Hardware Triggering Enable for this channel.
1551 * 0b0..Disabled. Hardware triggering is not used.
1552 * 0b1..Enabled. Use hardware triggering.
1553 */
1554#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
1555#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
1556#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
1557/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
1558 * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1559 * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
1560 */
1561#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
1562#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
1563#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
1564/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
1565 * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1566 * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
1567 * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
1568 * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
1569 * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
1570 * current BURSTPOWER length are completed.
1571 */
1572#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
1573#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
1574#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
1575/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
1576 * 0b0..Single transfer. Hardware trigger causes a single transfer.
1577 * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
1578 * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a
1579 * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
1580 * complete.
1581 */
1582#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
1583#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
1584#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
1585/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
1586 * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
1587 * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
1588 * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that
1589 * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:
1590 * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =
1591 * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The
1592 * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
1593 * multiple of the burst size.
1594 */
1595#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
1596#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
1597#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
1598/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
1599 * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this
1600 * could be used to read several sequential registers from a peripheral for each DMA burst,
1601 * reading the same registers again for each burst.
1602 * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
1603 * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
1604 */
1605#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
1606#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
1607#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
1608/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
1609 * 'wrapped', meaning that the destination address range for each burst will be the same. As an
1610 * example, this could be used to write several sequential registers to a peripheral for each DMA
1611 * burst, writing the same registers again for each burst.
1612 * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
1613 * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
1614 */
1615#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
1616#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
1617#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
1618/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority
1619 * levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
1620 */
1621#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
1622/*! @} */
1623
1624/* The count of DMA_CHANNEL_CFG */
1625#define DMA_CHANNEL_CFG_COUNT (18U)
1626
1627/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
1628/*! @{ */
1629#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
1630#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
1631/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the
1632 * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
1633 * 0b0..No effect. No effect on DMA operation.
1634 * 0b1..Valid pending.
1635 */
1636#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
1637#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
1638#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
1639/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is
1640 * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
1641 * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1642 * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
1643 */
1644#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
1645/*! @} */
1646
1647/* The count of DMA_CHANNEL_CTLSTAT */
1648#define DMA_CHANNEL_CTLSTAT_COUNT (18U)
1649
1650/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
1651/*! @{ */
1652#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
1653#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
1654/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor
1655 * is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
1656 * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1657 * 0b1..Valid. The current channel descriptor is considered valid.
1658 */
1659#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
1660#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
1661#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
1662/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current
1663 * descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1664 * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1665 * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.
1666 */
1667#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
1668#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
1669#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
1670/*! SWTRIG - Software Trigger.
1671 * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by
1672 * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1673 * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not
1674 * be used with level triggering when TRIGBURST = 0.
1675 */
1676#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
1677#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)
1678#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)
1679/*! CLRTRIG - Clear Trigger.
1680 * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1681 * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted
1682 */
1683#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
1684#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)
1685#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)
1686/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between
1687 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
1688 * convention, interrupt A may be used when only one interrupt flag is needed.
1689 * 0b0..No effect.
1690 * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
1691 */
1692#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
1693#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)
1694#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)
1695/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between
1696 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
1697 * convention, interrupt A may be used when only one interrupt flag is needed.
1698 * 0b0..No effect.
1699 * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
1700 */
1701#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
1702#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)
1703#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)
1704/*! WIDTH - Transfer width used for this DMA channel.
1705 * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
1706 * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
1707 * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
1708 * 0b11..Reserved. Reserved setting, do not use.
1709 */
1710#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
1711#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)
1712#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)
1713/*! SRCINC - Determines whether the source address is incremented for each DMA transfer.
1714 * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
1715 * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is
1716 * the usual case when the source is memory.
1717 * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
1718 * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
1719 */
1720#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
1721#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)
1722#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)
1723/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer.
1724 * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when
1725 * the destination is a peripheral device.
1726 * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer.
1727 * This is the usual case when the destination is memory.
1728 * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
1729 * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
1730 */
1731#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
1732#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)
1733#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)
1734/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes
1735 * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller
1736 * uses this bit field during transfer to count down. Hence, it cannot be used by software to read
1737 * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1
1738 * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of
1739 * 1,024 transfers will be performed.
1740 */
1741#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
1742/*! @} */
1743
1744/* The count of DMA_CHANNEL_XFERCFG */
1745#define DMA_CHANNEL_XFERCFG_COUNT (18U)
1746
1747
1748/*!
1749 * @}
1750 */ /* end of group DMA_Register_Masks */
1751
1752
1753/* DMA - Peripheral instance base addresses */
1754/** Peripheral DMA0 base address */
1755#define DMA0_BASE (0x50008000u)
1756/** Peripheral DMA0 base pointer */
1757#define DMA0 ((DMA_Type *)DMA0_BASE)
1758/** Array initializer of DMA peripheral base addresses */
1759#define DMA_BASE_ADDRS { DMA0_BASE }
1760/** Array initializer of DMA peripheral base pointers */
1761#define DMA_BASE_PTRS { DMA0 }
1762/** Interrupt vectors for the DMA peripheral type */
1763#define DMA_IRQS { DMA0_IRQn }
1764
1765/*!
1766 * @}
1767 */ /* end of group DMA_Peripheral_Access_Layer */
1768
1769
1770/* ----------------------------------------------------------------------------
1771 -- FLASH_CTRL Peripheral Access Layer
1772 ---------------------------------------------------------------------------- */
1773
1774/*!
1775 * @addtogroup FLASH_CTRL_Peripheral_Access_Layer FLASH_CTRL Peripheral Access Layer
1776 * @{
1777 */
1778
1779/** FLASH_CTRL - Register Layout Typedef */
1780typedef struct {
1781 uint8_t RESERVED_0[16];
1782 __IO uint32_t FLASHCFG; /**< Flash configuration register, offset: 0x10 */
1783 uint8_t RESERVED_1[12];
1784 __IO uint32_t FMSSTART; /**< Flash signature start address register, offset: 0x20 */
1785 __IO uint32_t FMSSTOP; /**< Flash signaure stop address register, offset: 0x24 */
1786 uint8_t RESERVED_2[4];
1787 __I uint32_t FMSW0; /**< Flash signature generation result register returns the flash signature produced by the embedded signature generator.., offset: 0x2C */
1788 uint8_t RESERVED_3[4016];
1789 __I uint32_t FMSTAT; /**< Flash signature generation status bit, offset: 0xFE0 */
1790 uint8_t RESERVED_4[4];
1791 __O uint32_t FMSTATCLR; /**< Clear FLASH signature generation status bit, offset: 0xFE8 */
1792} FLASH_CTRL_Type;
1793
1794/* ----------------------------------------------------------------------------
1795 -- FLASH_CTRL Register Masks
1796 ---------------------------------------------------------------------------- */
1797
1798/*!
1799 * @addtogroup FLASH_CTRL_Register_Masks FLASH_CTRL Register Masks
1800 * @{
1801 */
1802
1803/*! @name FLASHCFG - Flash configuration register */
1804/*! @{ */
1805#define FLASH_CTRL_FLASHCFG_FLASHTIM_MASK (0x3U)
1806#define FLASH_CTRL_FLASHCFG_FLASHTIM_SHIFT (0U)
1807/*! FLASHTIM - Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
1808 * 0b00..1 system clock flash access time.
1809 * 0b01..2 system clock flash access time.
1810 * 0b10-0b11..Reserved.
1811 */
1812#define FLASH_CTRL_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FLASHCFG_FLASHTIM_SHIFT)) & FLASH_CTRL_FLASHCFG_FLASHTIM_MASK)
1813/*! @} */
1814
1815/*! @name FMSSTART - Flash signature start address register */
1816/*! @{ */
1817#define FLASH_CTRL_FMSSTART_START_MASK (0x1FFFFU)
1818#define FLASH_CTRL_FMSSTART_START_SHIFT (0U)
1819/*! START - Signature generation start address (corresponds to AHB byte address bits[18:2]).
1820 */
1821#define FLASH_CTRL_FMSSTART_START(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTART_START_SHIFT)) & FLASH_CTRL_FMSSTART_START_MASK)
1822/*! @} */
1823
1824/*! @name FMSSTOP - Flash signaure stop address register */
1825/*! @{ */
1826#define FLASH_CTRL_FMSSTOP_STOPA_MASK (0x1FFFFU)
1827#define FLASH_CTRL_FMSSTOP_STOPA_SHIFT (0U)
1828/*! STOPA - Stop address for signature generation (the word specified by STOP is included in the
1829 * address range). The address is in units of memory words, not bytes.
1830 */
1831#define FLASH_CTRL_FMSSTOP_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTOP_STOPA_SHIFT)) & FLASH_CTRL_FMSSTOP_STOPA_MASK)
1832#define FLASH_CTRL_FMSSTOP_STRTBIST_MASK (0x80000000U)
1833#define FLASH_CTRL_FMSSTOP_STRTBIST_SHIFT (31U)
1834/*! STRTBIST - When this bit is written to 1, signature generation starts. At the end of signature
1835 * generation, this bit is automatically cleared.
1836 */
1837#define FLASH_CTRL_FMSSTOP_STRTBIST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTOP_STRTBIST_SHIFT)) & FLASH_CTRL_FMSSTOP_STRTBIST_MASK)
1838/*! @} */
1839
1840/*! @name FMSW0 - Flash signature generation result register returns the flash signature produced by the embedded signature generator.. */
1841/*! @{ */
1842#define FLASH_CTRL_FMSW0_SIG_MASK (0xFFFFFFFFU)
1843#define FLASH_CTRL_FMSW0_SIG_SHIFT (0U)
1844/*! SIG - 32-bit signature.
1845 */
1846#define FLASH_CTRL_FMSW0_SIG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSW0_SIG_SHIFT)) & FLASH_CTRL_FMSW0_SIG_MASK)
1847/*! @} */
1848
1849/*! @name FMSTAT - Flash signature generation status bit */
1850/*! @{ */
1851#define FLASH_CTRL_FMSTAT_SIGNATURE_DONE_MASK (0x2U)
1852#define FLASH_CTRL_FMSTAT_SIGNATURE_DONE_SHIFT (1U)
1853/*! SIGNATURE_DONE - This status bit is set at the end of signature computation
1854 */
1855#define FLASH_CTRL_FMSTAT_SIGNATURE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSTAT_SIGNATURE_DONE_SHIFT)) & FLASH_CTRL_FMSTAT_SIGNATURE_DONE_MASK)
1856/*! @} */
1857
1858/*! @name FMSTATCLR - Clear FLASH signature generation status bit */
1859/*! @{ */
1860#define FLASH_CTRL_FMSTATCLR_SIGNATURE_DONE_CLR_MASK (0x2U)
1861#define FLASH_CTRL_FMSTATCLR_SIGNATURE_DONE_CLR_SHIFT (1U)
1862/*! SIGNATURE_DONE_CLR - When the bit is written to 1, the SIGNATURE_DONE bit is cleared.
1863 */
1864#define FLASH_CTRL_FMSTATCLR_SIGNATURE_DONE_CLR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSTATCLR_SIGNATURE_DONE_CLR_SHIFT)) & FLASH_CTRL_FMSTATCLR_SIGNATURE_DONE_CLR_MASK)
1865/*! @} */
1866
1867
1868/*!
1869 * @}
1870 */ /* end of group FLASH_CTRL_Register_Masks */
1871
1872
1873/* FLASH_CTRL - Peripheral instance base addresses */
1874/** Peripheral FLASH_CTRL base address */
1875#define FLASH_CTRL_BASE (0x40040000u)
1876/** Peripheral FLASH_CTRL base pointer */
1877#define FLASH_CTRL ((FLASH_CTRL_Type *)FLASH_CTRL_BASE)
1878/** Array initializer of FLASH_CTRL peripheral base addresses */
1879#define FLASH_CTRL_BASE_ADDRS { FLASH_CTRL_BASE }
1880/** Array initializer of FLASH_CTRL peripheral base pointers */
1881#define FLASH_CTRL_BASE_PTRS { FLASH_CTRL }
1882/** Interrupt vectors for the FLASH_CTRL peripheral type */
1883#define FLASH_CTRL_IRQS { FLASH_IRQn }
1884
1885/*!
1886 * @}
1887 */ /* end of group FLASH_CTRL_Peripheral_Access_Layer */
1888
1889
1890/* ----------------------------------------------------------------------------
1891 -- GPIO Peripheral Access Layer
1892 ---------------------------------------------------------------------------- */
1893
1894/*!
1895 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
1896 * @{
1897 */
1898
1899/** GPIO - Register Layout Typedef */
1900typedef struct {
1901 __IO uint8_t B[1][29]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x1D, index2*0x1 */
1902 uint8_t RESERVED_0[4067];
1903 __IO uint32_t W[1][29]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x74, index2*0x4 */
1904 uint8_t RESERVED_1[3980];
1905 __IO uint32_t DIR[1]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */
1906 uint8_t RESERVED_2[124];
1907 __IO uint32_t MASK[1]; /**< Mask register, array offset: 0x2080, array step: 0x4 */
1908 uint8_t RESERVED_3[124];
1909 __IO uint32_t PIN[1]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */
1910 uint8_t RESERVED_4[124];
1911 __IO uint32_t MPIN[1]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */
1912 uint8_t RESERVED_5[124];
1913 __IO uint32_t SET[1]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
1914 uint8_t RESERVED_6[124];
1915 __O uint32_t CLR[1]; /**< Clear port, array offset: 0x2280, array step: 0x4 */
1916 uint8_t RESERVED_7[124];
1917 __O uint32_t NOT[1]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */
1918 uint8_t RESERVED_8[124];
1919 __O uint32_t DIRSET[1]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
1920 uint8_t RESERVED_9[124];
1921 __O uint32_t DIRCLR[1]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
1922 uint8_t RESERVED_10[124];
1923 __O uint32_t DIRNOT[1]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
1924} GPIO_Type;
1925
1926/* ----------------------------------------------------------------------------
1927 -- GPIO Register Masks
1928 ---------------------------------------------------------------------------- */
1929
1930/*!
1931 * @addtogroup GPIO_Register_Masks GPIO Register Masks
1932 * @{
1933 */
1934
1935/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
1936/*! @{ */
1937#define GPIO_B_PBYTE_MASK (0x1U)
1938#define GPIO_B_PBYTE_SHIFT (0U)
1939/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function,
1940 * except that pins configured as analog I/O always read as 0. One register for each port pin.
1941 * Supported pins depends on the specific device and package. Write: loads the pin's output bit.
1942 * One register for each port pin. Supported pins depends on the specific device and package.
1943 */
1944#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
1945/*! @} */
1946
1947/* The count of GPIO_B */
1948#define GPIO_B_COUNT (1U)
1949
1950/* The count of GPIO_B */
1951#define GPIO_B_COUNT2 (29U)
1952
1953/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
1954/*! @{ */
1955#define GPIO_W_PWORD_MASK (0xFFFFFFFFU)
1956#define GPIO_W_PWORD_SHIFT (0U)
1957/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is
1958 * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be
1959 * read. Writing any value other than 0 will set the output bit. One register for each port pin.
1960 * Supported pins depends on the specific device and package.
1961 */
1962#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
1963/*! @} */
1964
1965/* The count of GPIO_W */
1966#define GPIO_W_COUNT (1U)
1967
1968/* The count of GPIO_W */
1969#define GPIO_W_COUNT2 (29U)
1970
1971/*! @name DIR - Direction registers */
1972/*! @{ */
1973#define GPIO_DIR_DIRP_MASK (0x1FFFFFFFU)
1974#define GPIO_DIR_DIRP_SHIFT (0U)
1975/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
1976 * pins depends on the specific device and package. 0 = input. 1 = output.
1977 */
1978#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
1979/*! @} */
1980
1981/* The count of GPIO_DIR */
1982#define GPIO_DIR_COUNT (1U)
1983
1984/*! @name MASK - Mask register */
1985/*! @{ */
1986#define GPIO_MASK_MASKP_MASK (0x1FFFFFFFU)
1987#define GPIO_MASK_MASKP_SHIFT (0U)
1988/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 =
1989 * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 =
1990 * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit
1991 * not affected.
1992 */
1993#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
1994/*! @} */
1995
1996/* The count of GPIO_MASK */
1997#define GPIO_MASK_COUNT (1U)
1998
1999/*! @name PIN - Port pin register */
2000/*! @{ */
2001#define GPIO_PIN_PORT_MASK (0x1FFFFFFFU)
2002#define GPIO_PIN_PORT_SHIFT (0U)
2003/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
2004 * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit.
2005 * 1 = Read: pin is high; write: set output bit.
2006 */
2007#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
2008/*! @} */
2009
2010/* The count of GPIO_PIN */
2011#define GPIO_PIN_COUNT (1U)
2012
2013/*! @name MPIN - Masked port register */
2014/*! @{ */
2015#define GPIO_MPIN_MPORTP_MASK (0x1FFFFFFFU)
2016#define GPIO_MPIN_MPORTP_SHIFT (0U)
2017/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
2018 * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK
2019 * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1
2020 * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit
2021 * if the corresponding bit in the MASK register is 0.
2022 */
2023#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
2024/*! @} */
2025
2026/* The count of GPIO_MPIN */
2027#define GPIO_MPIN_COUNT (1U)
2028
2029/*! @name SET - Write: Set register for port Read: output bits for port */
2030/*! @{ */
2031#define GPIO_SET_SETP_MASK (0x1FFFFFFFU)
2032#define GPIO_SET_SETP_SHIFT (0U)
2033/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
2034 * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output
2035 * bit; write: set output bit.
2036 */
2037#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
2038/*! @} */
2039
2040/* The count of GPIO_SET */
2041#define GPIO_SET_COUNT (1U)
2042
2043/*! @name CLR - Clear port */
2044/*! @{ */
2045#define GPIO_CLR_CLRP_MASK (0x1FFFFFFFU)
2046#define GPIO_CLR_CLRP_SHIFT (0U)
2047/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
2048 * specific device and package. 0 = No operation. 1 = Clear output bit.
2049 */
2050#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
2051/*! @} */
2052
2053/* The count of GPIO_CLR */
2054#define GPIO_CLR_COUNT (1U)
2055
2056/*! @name NOT - Toggle port */
2057/*! @{ */
2058#define GPIO_NOT_NOTP_MASK (0x1FFFFFFFU)
2059#define GPIO_NOT_NOTP_SHIFT (0U)
2060/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
2061 * specific device and package. 0 = no operation. 1 = Toggle output bit.
2062 */
2063#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
2064/*! @} */
2065
2066/* The count of GPIO_NOT */
2067#define GPIO_NOT_COUNT (1U)
2068
2069/*! @name DIRSET - Set pin direction bits for port */
2070/*! @{ */
2071#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU)
2072#define GPIO_DIRSET_DIRSETP_SHIFT (0U)
2073/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
2074 * the specific device and package. 0 = No operation. 1 = Set direction bit.
2075 */
2076#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
2077/*! @} */
2078
2079/* The count of GPIO_DIRSET */
2080#define GPIO_DIRSET_COUNT (1U)
2081
2082/*! @name DIRCLR - Clear pin direction bits for port */
2083/*! @{ */
2084#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU)
2085#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U)
2086/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
2087 * the specific device and package. 0 = No operation. 1 = Clear direction bit.
2088 */
2089#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
2090/*! @} */
2091
2092/* The count of GPIO_DIRCLR */
2093#define GPIO_DIRCLR_COUNT (1U)
2094
2095/*! @name DIRNOT - Toggle pin direction bits for port */
2096/*! @{ */
2097#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU)
2098#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U)
2099/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends
2100 * on the specific device and package. 0 = no operation. 1 = Toggle direction bit.
2101 */
2102#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
2103/*! @} */
2104
2105/* The count of GPIO_DIRNOT */
2106#define GPIO_DIRNOT_COUNT (1U)
2107
2108
2109/*!
2110 * @}
2111 */ /* end of group GPIO_Register_Masks */
2112
2113
2114/* GPIO - Peripheral instance base addresses */
2115/** Peripheral GPIO base address */
2116#define GPIO_BASE (0xA0000000u)
2117/** Peripheral GPIO base pointer */
2118#define GPIO ((GPIO_Type *)GPIO_BASE)
2119/** Array initializer of GPIO peripheral base addresses */
2120#define GPIO_BASE_ADDRS { GPIO_BASE }
2121/** Array initializer of GPIO peripheral base pointers */
2122#define GPIO_BASE_PTRS { GPIO }
2123
2124/*!
2125 * @}
2126 */ /* end of group GPIO_Peripheral_Access_Layer */
2127
2128
2129/* ----------------------------------------------------------------------------
2130 -- I2C Peripheral Access Layer
2131 ---------------------------------------------------------------------------- */
2132
2133/*!
2134 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
2135 * @{
2136 */
2137
2138/** I2C - Register Layout Typedef */
2139typedef struct {
2140 __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x0 */
2141 __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x4 */
2142 __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x8 */
2143 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0xC */
2144 __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x10 */
2145 __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x14 */
2146 __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x18 */
2147 uint8_t RESERVED_0[4];
2148 __IO uint32_t MSTCTL; /**< Master control register., offset: 0x20 */
2149 __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x24 */
2150 __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x28 */
2151 uint8_t RESERVED_1[20];
2152 __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x40 */
2153 __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x44 */
2154 __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x48, array step: 0x4 */
2155 __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x58 */
2156 uint8_t RESERVED_2[36];
2157 __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x80 */
2158} I2C_Type;
2159
2160/* ----------------------------------------------------------------------------
2161 -- I2C Register Masks
2162 ---------------------------------------------------------------------------- */
2163
2164/*!
2165 * @addtogroup I2C_Register_Masks I2C Register Masks
2166 * @{
2167 */
2168
2169/*! @name CFG - Configuration for shared functions. */
2170/*! @{ */
2171#define I2C_CFG_MSTEN_MASK (0x1U)
2172#define I2C_CFG_MSTEN_SHIFT (0U)
2173/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not
2174 * changed, but the Master function is internally reset.
2175 * 0b0..Disabled. The I2C Master function is disabled.
2176 * 0b1..Enabled. The I2C Master function is enabled.
2177 */
2178#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
2179#define I2C_CFG_SLVEN_MASK (0x2U)
2180#define I2C_CFG_SLVEN_SHIFT (1U)
2181/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not
2182 * changed, but the Slave function is internally reset.
2183 * 0b0..Disabled. The I2C slave function is disabled.
2184 * 0b1..Enabled. The I2C slave function is enabled.
2185 */
2186#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
2187#define I2C_CFG_MONEN_MASK (0x4U)
2188#define I2C_CFG_MONEN_SHIFT (2U)
2189/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not
2190 * changed, but the Monitor function is internally reset.
2191 * 0b0..Disabled. The I2C Monitor function is disabled.
2192 * 0b1..Enabled. The I2C Monitor function is enabled.
2193 */
2194#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
2195#define I2C_CFG_TIMEOUTEN_MASK (0x8U)
2196#define I2C_CFG_TIMEOUTEN_SHIFT (3U)
2197/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
2198 * 0b0..Disabled. Time-out function is disabled.
2199 * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause
2200 * interrupts if they are enabled. Typically, only one time-out will be used in a system.
2201 */
2202#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
2203#define I2C_CFG_MONCLKSTR_MASK (0x10U)
2204#define I2C_CFG_MONCLKSTR_SHIFT (4U)
2205/*! MONCLKSTR - Monitor function Clock Stretching.
2206 * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able
2207 * to read data provided by the Monitor function before it is overwritten. This mode may be used when
2208 * non-invasive monitoring is critical.
2209 * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can
2210 * read all incoming data supplied by the Monitor function.
2211 */
2212#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
2213/*! @} */
2214
2215/*! @name STAT - Status register for Master, Slave, and Monitor functions. */
2216/*! @{ */
2217#define I2C_STAT_MSTPENDING_MASK (0x1U)
2218#define I2C_STAT_MSTPENDING_SHIFT (0U)
2219/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on
2220 * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what
2221 * type of software service if any the master expects. This flag will cause an interrupt when set
2222 * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling
2223 * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle
2224 * state, and no communication is needed, mask this interrupt.
2225 * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
2226 * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the
2227 * idle state, it is waiting to receive or transmit data or the NACK bit.
2228 */
2229#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
2230#define I2C_STAT_MSTSTATE_MASK (0xEU)
2231#define I2C_STAT_MSTSTATE_SHIFT (1U)
2232/*! MSTSTATE - Master State code. The master state code reflects the master state when the
2233 * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field
2234 * indicates a specific required service for the Master function. All other values are reserved. See
2235 * Table 400 for details of state values and appropriate responses.
2236 * 0b000..Idle. The Master function is available to be used for a new transaction.
2237 * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
2238 * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
2239 * 0b011..NACK Address. Slave NACKed address.
2240 * 0b100..NACK Data. Slave NACKed transmitted data.
2241 */
2242#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
2243#define I2C_STAT_MSTARBLOSS_MASK (0x10U)
2244#define I2C_STAT_MSTARBLOSS_SHIFT (4U)
2245/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to
2246 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
2247 * 0b0..No Arbitration Loss has occurred.
2248 * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master
2249 * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing,
2250 * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
2251 */
2252#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
2253#define I2C_STAT_MSTSTSTPERR_MASK (0x40U)
2254#define I2C_STAT_MSTSTSTPERR_SHIFT (6U)
2255/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to
2256 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
2257 * 0b0..No Start/Stop Error has occurred.
2258 * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is
2259 * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an
2260 * idle state, no action is required. A request for a Start could be made, or software could attempt to insure
2261 * that the bus has not stalled.
2262 */
2263#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
2264#define I2C_STAT_SLVPENDING_MASK (0x100U)
2265#define I2C_STAT_SLVPENDING_SHIFT (8U)
2266/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue
2267 * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if
2268 * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the
2269 * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is
2270 * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time
2271 * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section
2272 * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are
2273 * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must
2274 * also be detected automatically, since the address must be acknowledged before the clock can be
2275 * stretched.
2276 * 0b0..In progress. The Slave function does not currently need service.
2277 * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
2278 */
2279#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
2280#define I2C_STAT_SLVSTATE_MASK (0x600U)
2281#define I2C_STAT_SLVSTATE_SHIFT (9U)
2282/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for
2283 * the Slave function. All other values are reserved. See Table 401 for state values and actions.
2284 * note that the occurrence of some states and how they are handled are affected by DMA mode and
2285 * Automatic Operation modes.
2286 * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
2287 * 0b01..Slave receive. Received data is available (Slave Receiver mode).
2288 * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode).
2289 */
2290#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
2291#define I2C_STAT_SLVNOTSTR_MASK (0x800U)
2292#define I2C_STAT_SLVNOTSTR_SHIFT (11U)
2293/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock.
2294 * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave
2295 * operation. This read-only flag reflects the slave function status in real time.
2296 * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
2297 * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or
2298 * Power-down mode could be entered at this time.
2299 */
2300#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
2301#define I2C_STAT_SLVIDX_MASK (0x3000U)
2302#define I2C_STAT_SLVIDX_SHIFT (12U)
2303/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been
2304 * selected by receiving an address that matches one of the slave addresses defined by any enabled
2305 * slave address registers, and provides an identification of the address that was matched. It is
2306 * possible that more than one address could be matched, but only one match can be reported here.
2307 * 0b00..Address 0. Slave address 0 was matched.
2308 * 0b01..Address 1. Slave address 1 was matched.
2309 * 0b10..Address 2. Slave address 2 was matched.
2310 * 0b11..Address 3. Slave address 3 was matched.
2311 */
2312#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
2313#define I2C_STAT_SLVSEL_MASK (0x4000U)
2314#define I2C_STAT_SLVSEL_SHIFT (14U)
2315/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave
2316 * function to acknowledge the address, or when the address has been automatically acknowledged.
2317 * It is cleared when another address cycle presents an address that does not match an enabled
2318 * address on the Slave function, when slave software decides to NACK a matched address, when
2319 * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of
2320 * Automatic Operation. SLVSEL is not cleared if software NACKs data.
2321 * 0b0..Not selected. The Slave function is not currently selected.
2322 * 0b1..Selected. The Slave function is currently selected.
2323 */
2324#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
2325#define I2C_STAT_SLVDESEL_MASK (0x8000U)
2326#define I2C_STAT_SLVDESEL_SHIFT (15U)
2327/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via
2328 * INTENSET. This flag can be cleared by writing a 1 to this bit.
2329 * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently
2330 * selected. That information can be found in the SLVSEL flag.
2331 * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag
2332 * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
2333 */
2334#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
2335#define I2C_STAT_MONRDY_MASK (0x10000U)
2336#define I2C_STAT_MONRDY_SHIFT (16U)
2337/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read.
2338 * 0b0..No data. The Monitor function does not currently have data available.
2339 * 0b1..Data waiting. The Monitor function has data waiting to be read.
2340 */
2341#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
2342#define I2C_STAT_MONOV_MASK (0x20000U)
2343#define I2C_STAT_MONOV_SHIFT (17U)
2344/*! MONOV - Monitor Overflow flag.
2345 * 0b0..No overrun. Monitor data has not overrun.
2346 * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not
2347 * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
2348 */
2349#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
2350#define I2C_STAT_MONACTIVE_MASK (0x40000U)
2351#define I2C_STAT_MONACTIVE_SHIFT (18U)
2352/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to
2353 * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred
2354 * more recently than a bus Stop.
2355 * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive.
2356 * 0b1..Active. The Monitor function considers the I2C bus to be active.
2357 */
2358#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
2359#define I2C_STAT_MONIDLE_MASK (0x80000U)
2360#define I2C_STAT_MONIDLE_SHIFT (19U)
2361/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change
2362 * from active to inactive. This can be used by software to decide when to process data
2363 * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the
2364 * INTENSET register. The flag can be cleared by writing a 1 to this bit.
2365 * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software.
2366 * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
2367 */
2368#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
2369#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U)
2370#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U)
2371/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been
2372 * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock
2373 * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus
2374 * is idle.
2375 * 0b0..No time-out. I2C bus events have not caused a time-out.
2376 * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
2377 */
2378#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
2379#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U)
2380#define I2C_STAT_SCLTIMEOUT_SHIFT (25U)
2381/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the
2382 * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
2383 * 0b0..No time-out. SCL low time has not caused a time-out.
2384 * 0b1..Time-out. SCL low time has caused a time-out.
2385 */
2386#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
2387/*! @} */
2388
2389/*! @name INTENSET - Interrupt Enable Set and read register. */
2390/*! @{ */
2391#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U)
2392#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U)
2393/*! MSTPENDINGEN - Master Pending interrupt Enable.
2394 * 0b0..Disabled. The MstPending interrupt is disabled.
2395 * 0b1..Enabled. The MstPending interrupt is enabled.
2396 */
2397#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
2398#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U)
2399#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U)
2400/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable.
2401 * 0b0..Disabled. The MstArbLoss interrupt is disabled.
2402 * 0b1..Enabled. The MstArbLoss interrupt is enabled.
2403 */
2404#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
2405#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U)
2406#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U)
2407/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable.
2408 * 0b0..Disabled. The MstStStpErr interrupt is disabled.
2409 * 0b1..Enabled. The MstStStpErr interrupt is enabled.
2410 */
2411#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
2412#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U)
2413#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U)
2414/*! SLVPENDINGEN - Slave Pending interrupt Enable.
2415 * 0b0..Disabled. The SlvPending interrupt is disabled.
2416 * 0b1..Enabled. The SlvPending interrupt is enabled.
2417 */
2418#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
2419#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U)
2420#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U)
2421/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable.
2422 * 0b0..Disabled. The SlvNotStr interrupt is disabled.
2423 * 0b1..Enabled. The SlvNotStr interrupt is enabled.
2424 */
2425#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
2426#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U)
2427#define I2C_INTENSET_SLVDESELEN_SHIFT (15U)
2428/*! SLVDESELEN - Slave Deselect interrupt Enable.
2429 * 0b0..Disabled. The SlvDeSel interrupt is disabled.
2430 * 0b1..Enabled. The SlvDeSel interrupt is enabled.
2431 */
2432#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
2433#define I2C_INTENSET_MONRDYEN_MASK (0x10000U)
2434#define I2C_INTENSET_MONRDYEN_SHIFT (16U)
2435/*! MONRDYEN - Monitor data Ready interrupt Enable.
2436 * 0b0..Disabled. The MonRdy interrupt is disabled.
2437 * 0b1..Enabled. The MonRdy interrupt is enabled.
2438 */
2439#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
2440#define I2C_INTENSET_MONOVEN_MASK (0x20000U)
2441#define I2C_INTENSET_MONOVEN_SHIFT (17U)
2442/*! MONOVEN - Monitor Overrun interrupt Enable.
2443 * 0b0..Disabled. The MonOv interrupt is disabled.
2444 * 0b1..Enabled. The MonOv interrupt is enabled.
2445 */
2446#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
2447#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U)
2448#define I2C_INTENSET_MONIDLEEN_SHIFT (19U)
2449/*! MONIDLEEN - Monitor Idle interrupt Enable.
2450 * 0b0..Disabled. The MonIdle interrupt is disabled.
2451 * 0b1..Enabled. The MonIdle interrupt is enabled.
2452 */
2453#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
2454#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U)
2455#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U)
2456/*! EVENTTIMEOUTEN - Event time-out interrupt Enable.
2457 * 0b0..Disabled. The Event time-out interrupt is disabled.
2458 * 0b1..Enabled. The Event time-out interrupt is enabled.
2459 */
2460#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
2461#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U)
2462#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U)
2463/*! SCLTIMEOUTEN - SCL time-out interrupt Enable.
2464 * 0b0..Disabled. The SCL time-out interrupt is disabled.
2465 * 0b1..Enabled. The SCL time-out interrupt is enabled.
2466 */
2467#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
2468/*! @} */
2469
2470/*! @name INTENCLR - Interrupt Enable Clear register. */
2471/*! @{ */
2472#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U)
2473#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U)
2474/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding
2475 * bit in the INTENSET register if implemented.
2476 */
2477#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
2478#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U)
2479#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U)
2480/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear.
2481 */
2482#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
2483#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U)
2484#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U)
2485/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear.
2486 */
2487#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
2488#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U)
2489#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U)
2490/*! SLVPENDINGCLR - Slave Pending interrupt clear.
2491 */
2492#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
2493#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U)
2494#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U)
2495/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear.
2496 */
2497#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
2498#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U)
2499#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U)
2500/*! SLVDESELCLR - Slave Deselect interrupt clear.
2501 */
2502#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
2503#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U)
2504#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U)
2505/*! MONRDYCLR - Monitor data Ready interrupt clear.
2506 */
2507#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
2508#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U)
2509#define I2C_INTENCLR_MONOVCLR_SHIFT (17U)
2510/*! MONOVCLR - Monitor Overrun interrupt clear.
2511 */
2512#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
2513#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U)
2514#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U)
2515/*! MONIDLECLR - Monitor Idle interrupt clear.
2516 */
2517#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
2518#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U)
2519#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U)
2520/*! EVENTTIMEOUTCLR - Event time-out interrupt clear.
2521 */
2522#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
2523#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U)
2524#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U)
2525/*! SCLTIMEOUTCLR - SCL time-out interrupt clear.
2526 */
2527#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
2528/*! @} */
2529
2530/*! @name TIMEOUT - Time-out value register. */
2531/*! @{ */
2532#define I2C_TIMEOUT_TOMIN_MASK (0xFU)
2533#define I2C_TIMEOUT_TOMIN_SHIFT (0U)
2534/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum
2535 * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
2536 */
2537#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
2538#define I2C_TIMEOUT_TO_MASK (0xFFF0U)
2539#define I2C_TIMEOUT_TO_SHIFT (4U)
2540/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C
2541 * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation,
2542 * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A
2543 * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after
2544 * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the
2545 * I2C function clock.
2546 */
2547#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
2548/*! @} */
2549
2550/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */
2551/*! @{ */
2552#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU)
2553#define I2C_CLKDIV_DIVVAL_SHIFT (0U)
2554/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that
2555 * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 =
2556 * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is
2557 * divided by 65,536 before use.
2558 */
2559#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
2560/*! @} */
2561
2562/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
2563/*! @{ */
2564#define I2C_INTSTAT_MSTPENDING_MASK (0x1U)
2565#define I2C_INTSTAT_MSTPENDING_SHIFT (0U)
2566/*! MSTPENDING - Master Pending.
2567 */
2568#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
2569#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U)
2570#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U)
2571/*! MSTARBLOSS - Master Arbitration Loss flag.
2572 */
2573#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
2574#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U)
2575#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U)
2576/*! MSTSTSTPERR - Master Start/Stop Error flag.
2577 */
2578#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
2579#define I2C_INTSTAT_SLVPENDING_MASK (0x100U)
2580#define I2C_INTSTAT_SLVPENDING_SHIFT (8U)
2581/*! SLVPENDING - Slave Pending.
2582 */
2583#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
2584#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U)
2585#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U)
2586/*! SLVNOTSTR - Slave Not Stretching status.
2587 */
2588#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
2589#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U)
2590#define I2C_INTSTAT_SLVDESEL_SHIFT (15U)
2591/*! SLVDESEL - Slave Deselected flag.
2592 */
2593#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
2594#define I2C_INTSTAT_MONRDY_MASK (0x10000U)
2595#define I2C_INTSTAT_MONRDY_SHIFT (16U)
2596/*! MONRDY - Monitor Ready.
2597 */
2598#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
2599#define I2C_INTSTAT_MONOV_MASK (0x20000U)
2600#define I2C_INTSTAT_MONOV_SHIFT (17U)
2601/*! MONOV - Monitor Overflow flag.
2602 */
2603#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
2604#define I2C_INTSTAT_MONIDLE_MASK (0x80000U)
2605#define I2C_INTSTAT_MONIDLE_SHIFT (19U)
2606/*! MONIDLE - Monitor Idle flag.
2607 */
2608#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
2609#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U)
2610#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U)
2611/*! EVENTTIMEOUT - Event time-out Interrupt flag.
2612 */
2613#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
2614#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U)
2615#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U)
2616/*! SCLTIMEOUT - SCL time-out Interrupt flag.
2617 */
2618#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
2619/*! @} */
2620
2621/*! @name MSTCTL - Master control register. */
2622/*! @{ */
2623#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U)
2624#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U)
2625/*! MSTCONTINUE - Master Continue.
2626 * 0b0..No effect.
2627 * 0b1..Informs the Master function to continue to the next operation.
2628 */
2629#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
2630#define I2C_MSTCTL_MSTSTART_MASK (0x2U)
2631#define I2C_MSTCTL_MSTSTART_SHIFT (1U)
2632/*! MSTSTART - Master Start control.
2633 * 0b0..No effect.
2634 * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time.
2635 */
2636#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
2637#define I2C_MSTCTL_MSTSTOP_MASK (0x4U)
2638#define I2C_MSTCTL_MSTSTOP_SHIFT (2U)
2639/*! MSTSTOP - Master Stop control.
2640 * 0b0..No effect.
2641 * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave
2642 * if the master is receiving data from the slave (Master Receiver mode).
2643 */
2644#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
2645#define I2C_MSTCTL_MSTDMA_MASK (0x8U)
2646#define I2C_MSTCTL_MSTDMA_SHIFT (3U)
2647/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type
2648 * operations such as Start, address, Stop, and address match must always be done with software,
2649 * typically via an interrupt. Address acknowledgement must also be done by software except when
2650 * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by
2651 * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA
2652 * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is
2653 * read/write.
2654 * 0b0..Disable. No DMA requests are generated for master operation.
2655 * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating
2656 * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
2657 */
2658#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
2659/*! @} */
2660
2661/*! @name MSTTIME - Master timing configuration. */
2662/*! @{ */
2663#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U)
2664#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U)
2665/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this
2666 * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This
2667 * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters
2668 * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.
2669 * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
2670 * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
2671 * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
2672 * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
2673 * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
2674 * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
2675 * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
2676 * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
2677 */
2678#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
2679#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U)
2680#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U)
2681/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this
2682 * master on SCL. Other masters in a multi-master system could shorten this time. This
2683 * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters
2684 * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.
2685 * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
2686 * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
2687 * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
2688 * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
2689 * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
2690 * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
2691 * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
2692 * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
2693 */
2694#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
2695/*! @} */
2696
2697/*! @name MSTDAT - Combined Master receiver and transmitter data register. */
2698/*! @{ */
2699#define I2C_MSTDAT_DATA_MASK (0xFFU)
2700#define I2C_MSTDAT_DATA_SHIFT (0U)
2701/*! DATA - Master function data register. Read: read the most recently received data for the Master
2702 * function. Write: transmit data using the Master function.
2703 */
2704#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
2705/*! @} */
2706
2707/*! @name SLVCTL - Slave control register. */
2708/*! @{ */
2709#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U)
2710#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U)
2711/*! SLVCONTINUE - Slave Continue.
2712 * 0b0..No effect.
2713 * 0b1..Informs the Slave function to continue to the next operation.
2714 */
2715#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
2716#define I2C_SLVCTL_SLVNACK_MASK (0x2U)
2717#define I2C_SLVCTL_SLVNACK_SHIFT (1U)
2718/*! SLVNACK - Slave NACK.
2719 * 0b0..No effect.
2720 * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).
2721 */
2722#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
2723#define I2C_SLVCTL_SLVDMA_MASK (0x8U)
2724#define I2C_SLVCTL_SLVDMA_SHIFT (3U)
2725/*! SLVDMA - Slave DMA enable.
2726 * 0b0..Disabled. No DMA requests are issued for Slave mode operation.
2727 * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception.
2728 */
2729#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
2730/*! @} */
2731
2732/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */
2733/*! @{ */
2734#define I2C_SLVDAT_DATA_MASK (0xFFU)
2735#define I2C_SLVDAT_DATA_SHIFT (0U)
2736/*! DATA - Slave function data register. Read: read the most recently received data for the Slave
2737 * function. Write: transmit data using the Slave function.
2738 */
2739#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
2740/*! @} */
2741
2742/*! @name SLVADR - Slave address register. */
2743/*! @{ */
2744#define I2C_SLVADR_SADISABLE_MASK (0x1U)
2745#define I2C_SLVADR_SADISABLE_SHIFT (0U)
2746/*! SADISABLE - Slave Address n Disable.
2747 * 0b0..Enabled. Slave Address n is enabled.
2748 * 0b1..Ignored Slave Address n is ignored.
2749 */
2750#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
2751#define I2C_SLVADR_SLVADR_MASK (0xFEU)
2752#define I2C_SLVADR_SLVADR_SHIFT (1U)
2753/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled.
2754 */
2755#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
2756/*! @} */
2757
2758/* The count of I2C_SLVADR */
2759#define I2C_SLVADR_COUNT (4U)
2760
2761/*! @name SLVQUAL0 - Slave Qualification for address 0. */
2762/*! @{ */
2763#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U)
2764#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U)
2765/*! QUALMODE0 - Qualify mode for slave address 0.
2766 * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
2767 * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
2768 */
2769#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
2770#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU)
2771#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U)
2772/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to
2773 * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is
2774 * set to 1 will cause an automatic match of the corresponding bit of the received address when it
2775 * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for
2776 * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0
2777 * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).
2778 */
2779#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
2780/*! @} */
2781
2782/*! @name MONRXDAT - Monitor receiver data register. */
2783/*! @{ */
2784#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU)
2785#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U)
2786/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.
2787 */
2788#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
2789#define I2C_MONRXDAT_MONSTART_MASK (0x100U)
2790#define I2C_MONRXDAT_MONSTART_SHIFT (8U)
2791/*! MONSTART - Monitor Received Start.
2792 * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus.
2793 * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus.
2794 */
2795#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
2796#define I2C_MONRXDAT_MONRESTART_MASK (0x200U)
2797#define I2C_MONRXDAT_MONRESTART_SHIFT (9U)
2798/*! MONRESTART - Monitor Received Repeated Start.
2799 * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
2800 * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
2801 */
2802#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
2803#define I2C_MONRXDAT_MONNACK_MASK (0x400U)
2804#define I2C_MONRXDAT_MONNACK_SHIFT (10U)
2805/*! MONNACK - Monitor Received NACK.
2806 * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
2807 * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
2808 */
2809#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
2810/*! @} */
2811
2812
2813/*!
2814 * @}
2815 */ /* end of group I2C_Register_Masks */
2816
2817
2818/* I2C - Peripheral instance base addresses */
2819/** Peripheral I2C0 base address */
2820#define I2C0_BASE (0x40050000u)
2821/** Peripheral I2C0 base pointer */
2822#define I2C0 ((I2C_Type *)I2C0_BASE)
2823/** Peripheral I2C1 base address */
2824#define I2C1_BASE (0x40054000u)
2825/** Peripheral I2C1 base pointer */
2826#define I2C1 ((I2C_Type *)I2C1_BASE)
2827/** Peripheral I2C2 base address */
2828#define I2C2_BASE (0x40070000u)
2829/** Peripheral I2C2 base pointer */
2830#define I2C2 ((I2C_Type *)I2C2_BASE)
2831/** Peripheral I2C3 base address */
2832#define I2C3_BASE (0x40074000u)
2833/** Peripheral I2C3 base pointer */
2834#define I2C3 ((I2C_Type *)I2C3_BASE)
2835/** Array initializer of I2C peripheral base addresses */
2836#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE }
2837/** Array initializer of I2C peripheral base pointers */
2838#define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3 }
2839/** Interrupt vectors for the I2C peripheral type */
2840#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn }
2841
2842/*!
2843 * @}
2844 */ /* end of group I2C_Peripheral_Access_Layer */
2845
2846
2847/* ----------------------------------------------------------------------------
2848 -- INPUTMUX Peripheral Access Layer
2849 ---------------------------------------------------------------------------- */
2850
2851/*!
2852 * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
2853 * @{
2854 */
2855
2856/** INPUTMUX - Register Layout Typedef */
2857typedef struct {
2858 __IO uint32_t DMA_ITRIG_INMUX[18]; /**< Trigger select register for DMA channel, array offset: 0x0, array step: 0x4 */
2859 uint8_t RESERVED_0[16312];
2860 __IO uint32_t DMA_INMUX_INMUX[2]; /**< DMA output trigger selection to become DMA trigger 7 and DMA trigger 8, array offset: 0x4000, array step: 0x4 */
2861 uint8_t RESERVED_1[24];
2862 __IO uint32_t SCT0_INMUX[4]; /**< input select register for SCT, array offset: 0x4020, array step: 0x4 */
2863} INPUTMUX_Type;
2864
2865/* ----------------------------------------------------------------------------
2866 -- INPUTMUX Register Masks
2867 ---------------------------------------------------------------------------- */
2868
2869/*!
2870 * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
2871 * @{
2872 */
2873
2874/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */
2875/*! @{ */
2876#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0xFU)
2877#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U)
2878/*! INP - Input mux register for trigger inputs 0 to 23 connected to DMA channel 0. Selects from
2879 * ADC, SCT, ACMP, pin interrupts, and DMA requests.
2880 * 0b0000..ADC_SEQA_IRQ
2881 * 0b0001..ADC_SEQB_IRQ
2882 * 0b0010..SCT_DMA0
2883 * 0b0011..SCT_DMA1
2884 * 0b0100..ACMP_O
2885 * 0b0101..PININT0
2886 * 0b0110..PININT1
2887 * 0b0111..DMA trigger mux 0
2888 * 0b1000..DMA trigger mux 1
2889 * 0b1001-0b1111..None
2890 */
2891#define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK)
2892/*! @} */
2893
2894/* The count of INPUTMUX_DMA_ITRIG_INMUX */
2895#define INPUTMUX_DMA_ITRIG_INMUX_COUNT (18U)
2896
2897/*! @name DMA_INMUX_INMUX - DMA output trigger selection to become DMA trigger 7 and DMA trigger 8 */
2898/*! @{ */
2899#define INPUTMUX_DMA_INMUX_INMUX_INP_MASK (0x1FU)
2900#define INPUTMUX_DMA_INMUX_INMUX_INP_SHIFT (0U)
2901/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 17).
2902 */
2903#define INPUTMUX_DMA_INMUX_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_INMUX_INMUX_INP_SHIFT)) & INPUTMUX_DMA_INMUX_INMUX_INP_MASK)
2904/*! @} */
2905
2906/* The count of INPUTMUX_DMA_INMUX_INMUX */
2907#define INPUTMUX_DMA_INMUX_INMUX_COUNT (2U)
2908
2909/*! @name SCT0_INMUX - input select register for SCT */
2910/*! @{ */
2911#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0xFU)
2912#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U)
2913/*! INP_N - Input mux register for SCT input n (n = 0 to 3). 0 = sct input 0 1=sct input 1 2= sct
2914 * input 2 3= sct input 3 4= adc_thcmp_irq 5 = comparator out 6=arm_txev 7=debug_halted
2915 * 0b0000..SCT_PIN0
2916 * 0b0001..SCT_PIN1
2917 * 0b0010..SCT_PIN2
2918 * 0b0011..SCT_PIN3
2919 * 0b0100..ADC_THCMP_IRQ
2920 * 0b0101..ACMP_O
2921 * 0b0110..ARM_TXEV
2922 * 0b0111..DEBUG_HALTED
2923 * 0b1000-0b1111..None
2924 */
2925#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK)
2926/*! @} */
2927
2928/* The count of INPUTMUX_SCT0_INMUX */
2929#define INPUTMUX_SCT0_INMUX_COUNT (4U)
2930
2931
2932/*!
2933 * @}
2934 */ /* end of group INPUTMUX_Register_Masks */
2935
2936
2937/* INPUTMUX - Peripheral instance base addresses */
2938/** Peripheral INPUTMUX base address */
2939#define INPUTMUX_BASE (0x40028000u)
2940/** Peripheral INPUTMUX base pointer */
2941#define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE)
2942/** Array initializer of INPUTMUX peripheral base addresses */
2943#define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE }
2944/** Array initializer of INPUTMUX peripheral base pointers */
2945#define INPUTMUX_BASE_PTRS { INPUTMUX }
2946
2947/*!
2948 * @}
2949 */ /* end of group INPUTMUX_Peripheral_Access_Layer */
2950
2951
2952/* ----------------------------------------------------------------------------
2953 -- IOCON Peripheral Access Layer
2954 ---------------------------------------------------------------------------- */
2955
2956/*!
2957 * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer
2958 * @{
2959 */
2960
2961/** IOCON - Register Layout Typedef */
2962typedef struct {
2963 __IO uint32_t PIO[31]; /**< Digital I/O control for pins PIO0_17..Digital I/O control for pins PIO0_18, array offset: 0x0, array step: 0x4 */
2964} IOCON_Type;
2965
2966/* ----------------------------------------------------------------------------
2967 -- IOCON Register Masks
2968 ---------------------------------------------------------------------------- */
2969
2970/*!
2971 * @addtogroup IOCON_Register_Masks IOCON Register Masks
2972 * @{
2973 */
2974
2975/*! @name PIO - Digital I/O control for pins PIO0_17..Digital I/O control for pins PIO0_18 */
2976/*! @{ */
2977#define IOCON_PIO_MODE_MASK (0x18U)
2978#define IOCON_PIO_MODE_SHIFT (3U)
2979/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control).
2980 * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled).
2981 * 0b01..Pull-down. Pull-down resistor enabled.
2982 * 0b10..Pull-up. Pull-up resistor enabled.
2983 * 0b11..Repeater. Repeater mode.
2984 */
2985#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
2986#define IOCON_PIO_HYS_MASK (0x20U)
2987#define IOCON_PIO_HYS_SHIFT (5U)
2988/*! HYS - Hysteresis.
2989 * 0b0..Disable
2990 * 0b1..Enable
2991 */
2992#define IOCON_PIO_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_HYS_SHIFT)) & IOCON_PIO_HYS_MASK)
2993#define IOCON_PIO_INV_MASK (0x40U)
2994#define IOCON_PIO_INV_SHIFT (6U)
2995/*! INV - Invert input
2996 * 0b0..Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
2997 * 0b1..Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
2998 */
2999#define IOCON_PIO_INV(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INV_SHIFT)) & IOCON_PIO_INV_MASK)
3000#define IOCON_PIO_I2CMODE_MASK (0x300U)
3001#define IOCON_PIO_I2CMODE_SHIFT (8U)
3002/*! I2CMODE - Selects I2C mode.
3003 * 0b00..Standard mode/ Fast-mode I2C.
3004 * 0b01..Standard GPIO functionality. Requires external pull-up for GPIO output function.
3005 * 0b10..Fast-mode Plus I2C
3006 * 0b11..Reserved
3007 */
3008#define IOCON_PIO_I2CMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CMODE_SHIFT)) & IOCON_PIO_I2CMODE_MASK)
3009#define IOCON_PIO_OD_MASK (0x400U)
3010#define IOCON_PIO_OD_SHIFT (10U)
3011/*! OD - Open-drain mode.
3012 * 0b0..Disable.
3013 * 0b1..Open-drain mode enabled. Remark: This is not a true open-drain mode.
3014 */
3015#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
3016#define IOCON_PIO_S_MODE_MASK (0x1800U)
3017#define IOCON_PIO_S_MODE_SHIFT (11U)
3018/*! S_MODE - Digital filter sample mode.
3019 * 0b00..Bypass input filter.
3020 * 0b01..1 clock cycle. Input pulses shorter than one filter clock are rejected.
3021 * 0b10..2 clock cycles. Input pulses shorter than two filter clocks are rejected.
3022 * 0b11..3 clock cycles. Input pulses shorter than three filter clocks are rejected.
3023 */
3024#define IOCON_PIO_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_S_MODE_SHIFT)) & IOCON_PIO_S_MODE_MASK)
3025#define IOCON_PIO_CLK_DIV_MASK (0xE000U)
3026#define IOCON_PIO_CLK_DIV_SHIFT (13U)
3027/*! CLK_DIV - Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
3028 * 0b000..IOCONCLKDIV0
3029 * 0b001..IOCONCLKDIV1
3030 * 0b010..IOCONCLKDIV2
3031 * 0b011..IOCONCLKDIV3
3032 * 0b100..IOCONCLKDIV4
3033 * 0b101..IOCONCLKDIV5
3034 * 0b110..IOCONCLKDIV6
3035 */
3036#define IOCON_PIO_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_CLK_DIV_SHIFT)) & IOCON_PIO_CLK_DIV_MASK)
3037/*! @} */
3038
3039/* The count of IOCON_PIO */
3040#define IOCON_PIO_COUNT (31U)
3041
3042
3043/*!
3044 * @}
3045 */ /* end of group IOCON_Register_Masks */
3046
3047
3048/* IOCON - Peripheral instance base addresses */
3049/** Peripheral IOCON base address */
3050#define IOCON_BASE (0x40044000u)
3051/** Peripheral IOCON base pointer */
3052#define IOCON ((IOCON_Type *)IOCON_BASE)
3053/** Array initializer of IOCON peripheral base addresses */
3054#define IOCON_BASE_ADDRS { IOCON_BASE }
3055/** Array initializer of IOCON peripheral base pointers */
3056#define IOCON_BASE_PTRS { IOCON }
3057
3058#define IOCON_INDEX_PIO0_17 (0 )
3059#define IOCON_INDEX_PIO0_13 (1 )
3060#define IOCON_INDEX_PIO0_12 (2 )
3061#define IOCON_INDEX_PIO0_5 (3 )
3062#define IOCON_INDEX_PIO0_4 (4 )
3063#define IOCON_INDEX_PIO0_3 (5 )
3064#define IOCON_INDEX_PIO0_2 (6 )
3065#define IOCON_INDEX_PIO0_11 (7 )
3066#define IOCON_INDEX_PIO0_10 (8 )
3067#define IOCON_INDEX_PIO0_16 (9 )
3068#define IOCON_INDEX_PIO0_15 (10)
3069#define IOCON_INDEX_PIO0_1 (11)
3070#define IOCON_INDEX_PIO0_9 (13)
3071#define IOCON_INDEX_PIO0_8 (14)
3072#define IOCON_INDEX_PIO0_7 (15)
3073#define IOCON_INDEX_PIO0_6 (16)
3074#define IOCON_INDEX_PIO0_0 (17)
3075#define IOCON_INDEX_PIO0_14 (18)
3076#define IOCON_INDEX_PIO0_28 (20)
3077#define IOCON_INDEX_PIO0_27 (21)
3078#define IOCON_INDEX_PIO0_26 (22)
3079#define IOCON_INDEX_PIO0_25 (23)
3080#define IOCON_INDEX_PIO0_24 (24)
3081#define IOCON_INDEX_PIO0_23 (25)
3082#define IOCON_INDEX_PIO0_22 (26)
3083#define IOCON_INDEX_PIO0_21 (27)
3084#define IOCON_INDEX_PIO0_20 (28)
3085#define IOCON_INDEX_PIO0_19 (29)
3086#define IOCON_INDEX_PIO0_18 (30)
3087
3088
3089/*!
3090 * @}
3091 */ /* end of group IOCON_Peripheral_Access_Layer */
3092
3093
3094/* ----------------------------------------------------------------------------
3095 -- MRT Peripheral Access Layer
3096 ---------------------------------------------------------------------------- */
3097
3098/*!
3099 * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
3100 * @{
3101 */
3102
3103/** MRT - Register Layout Typedef */
3104typedef struct {
3105 struct { /* offset: 0x0, array step: 0x10 */
3106 __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */
3107 __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */
3108 __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */
3109 __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */
3110 } CHANNEL[4];
3111 uint8_t RESERVED_0[176];
3112 __I uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance., offset: 0xF0 */
3113 __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */
3114 __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */
3115} MRT_Type;
3116
3117/* ----------------------------------------------------------------------------
3118 -- MRT Register Masks
3119 ---------------------------------------------------------------------------- */
3120
3121/*!
3122 * @addtogroup MRT_Register_Masks MRT Register Masks
3123 * @{
3124 */
3125
3126/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */
3127/*! @{ */
3128#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0x7FFFFFFFU)
3129#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U)
3130/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT
3131 * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to
3132 * this bit field starts the timer immediately. If the timer is running, writing a zero to this
3133 * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer
3134 * stops at the end of the time interval.
3135 */
3136#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
3137#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U)
3138#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U)
3139/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register.
3140 * This bit is write-only. Reading this bit always returns 0.
3141 * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the
3142 * time interval if the repeat mode is selected.
3143 * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
3144 */
3145#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
3146/*! @} */
3147
3148/* The count of MRT_CHANNEL_INTVAL */
3149#define MRT_CHANNEL_INTVAL_COUNT (4U)
3150
3151/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */
3152/*! @{ */
3153#define MRT_CHANNEL_TIMER_VALUE_MASK (0x7FFFFFFFU)
3154#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U)
3155/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn
3156 * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval
3157 * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn
3158 * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields
3159 * returns -1 (0x00FF FFFF).
3160 */
3161#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
3162/*! @} */
3163
3164/* The count of MRT_CHANNEL_TIMER */
3165#define MRT_CHANNEL_TIMER_COUNT (4U)
3166
3167/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */
3168/*! @{ */
3169#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U)
3170#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U)
3171/*! INTEN - Enable the TIMERn interrupt.
3172 * 0b0..Disabled. TIMERn interrupt is disabled.
3173 * 0b1..Enabled. TIMERn interrupt is enabled.
3174 */
3175#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
3176#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U)
3177#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U)
3178/*! MODE - Selects timer mode.
3179 * 0b00..Repeat interrupt mode.
3180 * 0b01..One-shot interrupt mode.
3181 * 0b10..One-shot stall mode.
3182 * 0b11..Reserved.
3183 */
3184#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
3185/*! @} */
3186
3187/* The count of MRT_CHANNEL_CTRL */
3188#define MRT_CHANNEL_CTRL_COUNT (4U)
3189
3190/*! @name CHANNEL_STAT - MRT Status register. */
3191/*! @{ */
3192#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U)
3193#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U)
3194/*! INTFLAG - Monitors the interrupt flag.
3195 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
3196 * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If
3197 * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt
3198 * are raised. Writing a 1 to this bit clears the interrupt request.
3199 */
3200#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
3201#define MRT_CHANNEL_STAT_RUN_MASK (0x2U)
3202#define MRT_CHANNEL_STAT_RUN_SHIFT (1U)
3203/*! RUN - Indicates the state of TIMERn. This bit is read-only.
3204 * 0b0..Idle state. TIMERn is stopped.
3205 * 0b1..Running. TIMERn is running.
3206 */
3207#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
3208/*! @} */
3209
3210/* The count of MRT_CHANNEL_STAT */
3211#define MRT_CHANNEL_STAT_COUNT (4U)
3212
3213/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance. */
3214/*! @{ */
3215#define MRT_MODCFG_NOC_MASK (0xFU)
3216#define MRT_MODCFG_NOC_SHIFT (0U)
3217/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.)
3218 */
3219#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
3220#define MRT_MODCFG_NOB_MASK (0x1F0U)
3221#define MRT_MODCFG_NOB_SHIFT (4U)
3222/*! NOB - Identifies the number of timer bits in this MRT. (31 bits wide on this device.)
3223 */
3224#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
3225/*! @} */
3226
3227/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */
3228/*! @{ */
3229#define MRT_IDLE_CH_CHAN_MASK (0xF0U)
3230#define MRT_IDLE_CH_CHAN_SHIFT (4U)
3231/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is
3232 * positioned such that it can be used as an offset from the MRT base address in order to access
3233 * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See
3234 * text above for more details.
3235 */
3236#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
3237/*! @} */
3238
3239/*! @name IRQ_FLAG - Global interrupt flag register */
3240/*! @{ */
3241#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U)
3242#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U)
3243/*! GFLAG0 - Monitors the interrupt flag of TIMER0.
3244 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
3245 * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If
3246 * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global
3247 * interrupt are raised. Writing a 1 to this bit clears the interrupt request.
3248 */
3249#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
3250#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U)
3251#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U)
3252/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0.
3253 */
3254#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
3255#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U)
3256#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U)
3257/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0.
3258 */
3259#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
3260#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U)
3261#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U)
3262/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0.
3263 */
3264#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
3265/*! @} */
3266
3267
3268/*!
3269 * @}
3270 */ /* end of group MRT_Register_Masks */
3271
3272
3273/* MRT - Peripheral instance base addresses */
3274/** Peripheral MRT0 base address */
3275#define MRT0_BASE (0x40004000u)
3276/** Peripheral MRT0 base pointer */
3277#define MRT0 ((MRT_Type *)MRT0_BASE)
3278/** Array initializer of MRT peripheral base addresses */
3279#define MRT_BASE_ADDRS { MRT0_BASE }
3280/** Array initializer of MRT peripheral base pointers */
3281#define MRT_BASE_PTRS { MRT0 }
3282/** Interrupt vectors for the MRT peripheral type */
3283#define MRT_IRQS { MRT0_IRQn }
3284
3285/*!
3286 * @}
3287 */ /* end of group MRT_Peripheral_Access_Layer */
3288
3289
3290/* ----------------------------------------------------------------------------
3291 -- MTB Peripheral Access Layer
3292 ---------------------------------------------------------------------------- */
3293
3294/*!
3295 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
3296 * @{
3297 */
3298
3299/** MTB - Register Layout Typedef */
3300typedef struct {
3301 __IO uint32_t POSITION; /**< POSITION Register, offset: 0x0 */
3302 __IO uint32_t MASTER; /**< MASTER Register, offset: 0x4 */
3303 __IO uint32_t FLOW; /**< FLOW Register, offset: 0x8 */
3304 __I uint32_t BASE; /**< Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB SRAM location, by a debug agent., offset: 0xC */
3305} MTB_Type;
3306
3307/* ----------------------------------------------------------------------------
3308 -- MTB Register Masks
3309 ---------------------------------------------------------------------------- */
3310
3311/*!
3312 * @addtogroup MTB_Register_Masks MTB Register Masks
3313 * @{
3314 */
3315
3316/*! @name POSITION - POSITION Register */
3317/*! @{ */
3318#define MTB_POSITION_WRAP_MASK (0x4U)
3319#define MTB_POSITION_WRAP_SHIFT (2U)
3320/*! WRAP - This bit is set to 1 automatically when the POINTER value wraps as determined by the
3321 * MASTER.MASK field in the MASTER Trace Control Register.
3322 */
3323#define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
3324#define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U)
3325#define MTB_POSITION_POINTER_SHIFT (3U)
3326/*! POINTER - Trace packet location pointer. Because a packet consists of two words, the POINTER
3327 * field is the location of the first word of a packet. This field contains bits [31:3] of the
3328 * address, in the SRAM, where the next trace packet will be written. The field points to an unused
3329 * location and is automatically incremented. A debug agent can calculate the system address, on
3330 * the AHB-Lite bus, of the SRAM location pointed to by the POSITION register using the following
3331 * equation: system address = BASE + ((P + (2AWIDTH - (BASE MOD 2AWIDTH))) MOD 2AWIDTH). Where P =
3332 * POSITION AND 0xFFFF_FFF8. Where BASE is the BASE register value
3333 */
3334#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
3335/*! @} */
3336
3337/*! @name MASTER - MASTER Register */
3338/*! @{ */
3339#define MTB_MASTER_MASK_MASK (0x1FU)
3340#define MTB_MASTER_MASK_SHIFT (0U)
3341/*! MASK - This value determines the maximum size of the trace buffer in SRAM. It specifies the
3342 * most-significant bit of the POSITION.POINTER field that can be updated by automatic increment. If
3343 * the trace tries to advance past this power of two, the POSITION.WRAP bit is set to 1, the
3344 * POSITION.POINTER[MASK:0] bits are set to zero, and the POSITION.POINTER[AWIDTH-4:MASK+1] bits
3345 * remain unchanged. This field causes the trace packet information to be stored in a circular buffer
3346 * of size 2(MASK+4) bytes, that can be positioned in memory at multiples of this size. Valid
3347 * values of this field are zero to AWIDTH-4. Values greater than the maximum have the same effect
3348 * as the maximum.
3349 */
3350#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
3351#define MTB_MASTER_TSTARTEN_MASK (0x20U)
3352#define MTB_MASTER_TSTARTEN_SHIFT (5U)
3353/*! TSTARTEN - Trace start input enable. If this bit is 1 and the TSTART signal is HIGH, then the EN
3354 * bit is set to 1. Tracing continues until a stop condition occurs.
3355 */
3356#define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
3357#define MTB_MASTER_TSTOPEN_MASK (0x40U)
3358#define MTB_MASTER_TSTOPEN_SHIFT (6U)
3359/*! TSTOPEN - Trace stop input enable. If this bit is 1 and the TSTOP signal is HIGH, then the EN
3360 * bit is set to 0. If a trace packet is being written to memory, the write is completed before
3361 * tracing is stopped.
3362 */
3363#define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
3364#define MTB_MASTER_SFRWPRIV_MASK (0x80U)
3365#define MTB_MASTER_SFRWPRIV_SHIFT (7U)
3366/*! SFRWPRIV - Special Function Register Write Privilege bit. If this bit is 0, then User or
3367 * Privileged AHB-Lite read and write accesses to the Special Function Registers are permitted. If this
3368 * bit is 1, then only Privileged write accesses are permitted and User write accesses are
3369 * ignored. The HPROT[1] signal determines if an access is User or Privileged.
3370 */
3371#define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
3372#define MTB_MASTER_RAMPRIV_MASK (0x100U)
3373#define MTB_MASTER_RAMPRIV_SHIFT (8U)
3374/*! RAMPRIV - SRAM Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write
3375 * accesses to the SRAM are permitted. If this bit is 1, then only Privileged AHB-Lite read and
3376 * write accesses to the SRAM are permitted and User accesses are RAZ/WI. The HPROT[1] signal
3377 * determines if an access is User or Privileged.
3378 */
3379#define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
3380#define MTB_MASTER_HALTREQ_MASK (0x200U)
3381#define MTB_MASTER_HALTREQ_SHIFT (9U)
3382/*! HALTREQ - Halt request bit. This bit is connected to the halt request signal of the trace logic,
3383 * EDBGRQ. When HALTREQ is set to 1, EDBGRQ is asserted if DBGEN is also HIGH. The HALTREQ bit
3384 * can be automatically set to 1 using the FLOW.WATERMARK field.
3385 */
3386#define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
3387#define MTB_MASTER_EN_MASK (0x80000000U)
3388#define MTB_MASTER_EN_SHIFT (31U)
3389/*! EN - Main trace enable bit. When this bit is 1 trace data is written into the SRAM memory
3390 * location addressed by POSITION.POINTER. The POSITION.POINTER value auto increments after the trace
3391 * data packet is written. The EN bit can be automatically set to 0 using the FLOW.WATERMARK field
3392 * and the FLOW.AUTOSTOP bit. The EN bit is automatically set to 1 if the TSTARTEN bit is 1 and
3393 * the TSTART signal is HIGH. The EN bit is automatically set to 0 if TSTOPEN bit is 1 and the
3394 * TSTOP signal is HIGH.
3395 */
3396#define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
3397/*! @} */
3398
3399/*! @name FLOW - FLOW Register */
3400/*! @{ */
3401#define MTB_FLOW_AUTOSTOP_MASK (0x1U)
3402#define MTB_FLOW_AUTOSTOP_SHIFT (0U)
3403/*! AUTOSTOP - If this bit is 1 and WATERMARK is equal to POSITION.POINTER, then the MASTER.EN bit
3404 * is automatically set to 0. This stops tracing.
3405 */
3406#define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
3407#define MTB_FLOW_AUTOHALT_MASK (0x2U)
3408#define MTB_FLOW_AUTOHALT_SHIFT (1U)
3409/*! AUTOHALT - If this bit is 1 and WATERMARK is equal to POSITION.POINTER, then the MASTER.HALTREQ
3410 * bit is automatically set to 1. If the DBGEN signal is HIGH, the MTB asserts this halt request
3411 * to the Cortex-M0+ processor by asserting the EDBGRQ signal.
3412 */
3413#define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
3414#define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U)
3415#define MTB_FLOW_WATERMARK_SHIFT (3U)
3416/*! WATERMARK - WATERMARK value. This field contains an address in the same format as the
3417 * POSITION.POINTER field. When the POSITION.POINTER matches the WATERMARK field value, actions defined by
3418 * the AUTOHALT and AUTOSTOP bits are performed.
3419 */
3420#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
3421/*! @} */
3422
3423/*! @name BASE - Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB SRAM location, by a debug agent. */
3424/*! @{ */
3425#define MTB_BASE_BASE_MASK (0xFFFFFFFFU)
3426#define MTB_BASE_BASE_SHIFT (0U)
3427/*! BASE - The value provided is the value of the SRAMBASEADDR[31:0] signal.
3428 */
3429#define MTB_BASE_BASE(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASE_SHIFT)) & MTB_BASE_BASE_MASK)
3430/*! @} */
3431
3432
3433/*!
3434 * @}
3435 */ /* end of group MTB_Register_Masks */
3436
3437
3438/* MTB - Peripheral instance base addresses */
3439/** Peripheral MTB_SFR base address */
3440#define MTB_SFR_BASE (0x14000000u)
3441/** Peripheral MTB_SFR base pointer */
3442#define MTB_SFR ((MTB_Type *)MTB_SFR_BASE)
3443/** Array initializer of MTB peripheral base addresses */
3444#define MTB_BASE_ADDRS { MTB_SFR_BASE }
3445/** Array initializer of MTB peripheral base pointers */
3446#define MTB_BASE_PTRS { MTB_SFR }
3447
3448/*!
3449 * @}
3450 */ /* end of group MTB_Peripheral_Access_Layer */
3451
3452
3453/* ----------------------------------------------------------------------------
3454 -- PINT Peripheral Access Layer
3455 ---------------------------------------------------------------------------- */
3456
3457/*!
3458 * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
3459 * @{
3460 */
3461
3462/** PINT - Register Layout Typedef */
3463typedef struct {
3464 __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */
3465 __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */
3466 __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */
3467 __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */
3468 __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */
3469 __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */
3470 __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */
3471 __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */
3472 __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */
3473 __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */
3474 __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */
3475 __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */
3476 __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */
3477} PINT_Type;
3478
3479/* ----------------------------------------------------------------------------
3480 -- PINT Register Masks
3481 ---------------------------------------------------------------------------- */
3482
3483/*!
3484 * @addtogroup PINT_Register_Masks PINT Register Masks
3485 * @{
3486 */
3487
3488/*! @name ISEL - Pin Interrupt Mode register */
3489/*! @{ */
3490#define PINT_ISEL_PMODE_MASK (0xFFU)
3491#define PINT_ISEL_PMODE_SHIFT (0U)
3492/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt
3493 * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive
3494 */
3495#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
3496/*! @} */
3497
3498/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */
3499/*! @{ */
3500#define PINT_IENR_ENRL_MASK (0xFFU)
3501#define PINT_IENR_ENRL_SHIFT (0U)
3502/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the
3503 * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable
3504 * rising edge or level interrupt.
3505 */
3506#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
3507/*! @} */
3508
3509/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */
3510/*! @{ */
3511#define PINT_SIENR_SETENRL_MASK (0xFFU)
3512#define PINT_SIENR_SETENRL_SHIFT (0U)
3513/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n
3514 * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.
3515 */
3516#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
3517/*! @} */
3518
3519/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */
3520/*! @{ */
3521#define PINT_CIENR_CENRL_MASK (0xFFU)
3522#define PINT_CIENR_CENRL_SHIFT (0U)
3523/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit
3524 * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level
3525 * interrupt.
3526 */
3527#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
3528/*! @} */
3529
3530/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */
3531/*! @{ */
3532#define PINT_IENF_ENAF_MASK (0xFFU)
3533#define PINT_IENF_ENAF_SHIFT (0U)
3534/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt.
3535 * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt
3536 * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active
3537 * interrupt level HIGH.
3538 */
3539#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
3540/*! @} */
3541
3542/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */
3543/*! @{ */
3544#define PINT_SIENF_SETENAF_MASK (0xFFU)
3545#define PINT_SIENF_SETENAF_SHIFT (0U)
3546/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n
3547 * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable
3548 * falling edge interrupt.
3549 */
3550#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
3551/*! @} */
3552
3553/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */
3554/*! @{ */
3555#define PINT_CIENF_CENAF_MASK (0xFFU)
3556#define PINT_CIENF_CENAF_SHIFT (0U)
3557/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n
3558 * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or
3559 * falling edge interrupt disabled.
3560 */
3561#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
3562/*! @} */
3563
3564/*! @name RISE - Pin interrupt rising edge register */
3565/*! @{ */
3566#define PINT_RISE_RDET_MASK (0xFFU)
3567#define PINT_RISE_RDET_SHIFT (0U)
3568/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read
3569 * 0: No rising edge has been detected on this pin since Reset or the last time a one was written
3570 * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the
3571 * last time a one was written to this bit. Write 1: clear rising edge detection for this pin.
3572 */
3573#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
3574/*! @} */
3575
3576/*! @name FALL - Pin interrupt falling edge register */
3577/*! @{ */
3578#define PINT_FALL_FDET_MASK (0xFFU)
3579#define PINT_FALL_FDET_SHIFT (0U)
3580/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read
3581 * 0: No falling edge has been detected on this pin since Reset or the last time a one was
3582 * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or
3583 * the last time a one was written to this bit. Write 1: clear falling edge detection for this
3584 * pin.
3585 */
3586#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
3587/*! @} */
3588
3589/*! @name IST - Pin interrupt status register */
3590/*! @{ */
3591#define PINT_IST_PSTAT_MASK (0xFFU)
3592#define PINT_IST_PSTAT_SHIFT (0U)
3593/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts
3594 * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for
3595 * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this
3596 * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin.
3597 * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).
3598 */
3599#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
3600/*! @} */
3601
3602/*! @name PMCTRL - Pattern match interrupt control register */
3603/*! @{ */
3604#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U)
3605#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U)
3606/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.
3607 * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.
3608 * 0b1..Pattern match. Interrupts are driven in response to pattern matches.
3609 */
3610#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
3611#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U)
3612#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U)
3613/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.
3614 * 0b0..Disabled. RXEV output to the CPU is disabled.
3615 * 0b1..Enabled. RXEV output to the CPU is enabled.
3616 */
3617#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
3618#define PINT_PMCTRL_PMAT_MASK (0xFF000000U)
3619#define PINT_PMCTRL_PMAT_SHIFT (24U)
3620/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field
3621 * indicates that the corresponding product term is matched by the current state of the appropriate
3622 * inputs.
3623 */
3624#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
3625/*! @} */
3626
3627/*! @name PMSRC - Pattern match interrupt bit-slice source register */
3628/*! @{ */
3629#define PINT_PMSRC_SRC0_MASK (0x700U)
3630#define PINT_PMSRC_SRC0_SHIFT (8U)
3631/*! SRC0 - Selects the input source for bit slice 0
3632 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.
3633 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0.
3634 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0.
3635 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0.
3636 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0.
3637 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0.
3638 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0.
3639 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0.
3640 */
3641#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
3642#define PINT_PMSRC_SRC1_MASK (0x3800U)
3643#define PINT_PMSRC_SRC1_SHIFT (11U)
3644/*! SRC1 - Selects the input source for bit slice 1
3645 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.
3646 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1.
3647 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1.
3648 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1.
3649 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1.
3650 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1.
3651 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1.
3652 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1.
3653 */
3654#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
3655#define PINT_PMSRC_SRC2_MASK (0x1C000U)
3656#define PINT_PMSRC_SRC2_SHIFT (14U)
3657/*! SRC2 - Selects the input source for bit slice 2
3658 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.
3659 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2.
3660 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2.
3661 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2.
3662 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2.
3663 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2.
3664 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2.
3665 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2.
3666 */
3667#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
3668#define PINT_PMSRC_SRC3_MASK (0xE0000U)
3669#define PINT_PMSRC_SRC3_SHIFT (17U)
3670/*! SRC3 - Selects the input source for bit slice 3
3671 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3.
3672 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3.
3673 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3.
3674 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3.
3675 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3.
3676 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3.
3677 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3.
3678 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3.
3679 */
3680#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
3681#define PINT_PMSRC_SRC4_MASK (0x700000U)
3682#define PINT_PMSRC_SRC4_SHIFT (20U)
3683/*! SRC4 - Selects the input source for bit slice 4
3684 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.
3685 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4.
3686 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4.
3687 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4.
3688 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4.
3689 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4.
3690 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4.
3691 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4.
3692 */
3693#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
3694#define PINT_PMSRC_SRC5_MASK (0x3800000U)
3695#define PINT_PMSRC_SRC5_SHIFT (23U)
3696/*! SRC5 - Selects the input source for bit slice 5
3697 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.
3698 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5.
3699 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5.
3700 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5.
3701 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5.
3702 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5.
3703 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5.
3704 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5.
3705 */
3706#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
3707#define PINT_PMSRC_SRC6_MASK (0x1C000000U)
3708#define PINT_PMSRC_SRC6_SHIFT (26U)
3709/*! SRC6 - Selects the input source for bit slice 6
3710 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.
3711 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6.
3712 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6.
3713 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6.
3714 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6.
3715 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6.
3716 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6.
3717 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6.
3718 */
3719#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
3720#define PINT_PMSRC_SRC7_MASK (0xE0000000U)
3721#define PINT_PMSRC_SRC7_SHIFT (29U)
3722/*! SRC7 - Selects the input source for bit slice 7
3723 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7.
3724 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7.
3725 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7.
3726 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7.
3727 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7.
3728 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7.
3729 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7.
3730 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7.
3731 */
3732#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
3733/*! @} */
3734
3735/*! @name PMCFG - Pattern match interrupt bit slice configuration register */
3736/*! @{ */
3737#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U)
3738#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U)
3739/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint.
3740 * 0b0..No effect. Slice 0 is not an endpoint.
3741 * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.
3742 */
3743#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
3744#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U)
3745#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U)
3746/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint.
3747 * 0b0..No effect. Slice 1 is not an endpoint.
3748 * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.
3749 */
3750#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
3751#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U)
3752#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U)
3753/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint.
3754 * 0b0..No effect. Slice 2 is not an endpoint.
3755 * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.
3756 */
3757#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
3758#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U)
3759#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U)
3760/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint.
3761 * 0b0..No effect. Slice 3 is not an endpoint.
3762 * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.
3763 */
3764#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
3765#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U)
3766#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U)
3767/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint.
3768 * 0b0..No effect. Slice 4 is not an endpoint.
3769 * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.
3770 */
3771#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
3772#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U)
3773#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U)
3774/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint.
3775 * 0b0..No effect. Slice 5 is not an endpoint.
3776 * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.
3777 */
3778#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
3779#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U)
3780#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U)
3781/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint.
3782 * 0b0..No effect. Slice 6 is not an endpoint.
3783 * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.
3784 */
3785#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
3786#define PINT_PMCFG_CFG0_MASK (0x700U)
3787#define PINT_PMCFG_CFG0_SHIFT (8U)
3788/*! CFG0 - Specifies the match contribution condition for bit slice 0.
3789 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
3790 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
3791 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3792 * PMSRC registers are written to.
3793 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
3794 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3795 * PMSRC registers are written to.
3796 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
3797 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
3798 * cleared when the PMCFG or the PMSRC registers are written to.
3799 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
3800 * 0b101..Low level. Match occurs when there is a low level on the specified input.
3801 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
3802 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
3803 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
3804 * is cleared after one clock cycle.
3805 */
3806#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
3807#define PINT_PMCFG_CFG1_MASK (0x3800U)
3808#define PINT_PMCFG_CFG1_SHIFT (11U)
3809/*! CFG1 - Specifies the match contribution condition for bit slice 1.
3810 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
3811 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
3812 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3813 * PMSRC registers are written to.
3814 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
3815 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3816 * PMSRC registers are written to.
3817 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
3818 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
3819 * cleared when the PMCFG or the PMSRC registers are written to.
3820 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
3821 * 0b101..Low level. Match occurs when there is a low level on the specified input.
3822 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
3823 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
3824 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
3825 * is cleared after one clock cycle.
3826 */
3827#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
3828#define PINT_PMCFG_CFG2_MASK (0x1C000U)
3829#define PINT_PMCFG_CFG2_SHIFT (14U)
3830/*! CFG2 - Specifies the match contribution condition for bit slice 2.
3831 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
3832 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
3833 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3834 * PMSRC registers are written to.
3835 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
3836 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3837 * PMSRC registers are written to.
3838 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
3839 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
3840 * cleared when the PMCFG or the PMSRC registers are written to.
3841 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
3842 * 0b101..Low level. Match occurs when there is a low level on the specified input.
3843 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
3844 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
3845 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
3846 * is cleared after one clock cycle.
3847 */
3848#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
3849#define PINT_PMCFG_CFG3_MASK (0xE0000U)
3850#define PINT_PMCFG_CFG3_SHIFT (17U)
3851/*! CFG3 - Specifies the match contribution condition for bit slice 3.
3852 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
3853 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
3854 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3855 * PMSRC registers are written to.
3856 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
3857 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3858 * PMSRC registers are written to.
3859 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
3860 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
3861 * cleared when the PMCFG or the PMSRC registers are written to.
3862 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
3863 * 0b101..Low level. Match occurs when there is a low level on the specified input.
3864 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
3865 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
3866 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
3867 * is cleared after one clock cycle.
3868 */
3869#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
3870#define PINT_PMCFG_CFG4_MASK (0x700000U)
3871#define PINT_PMCFG_CFG4_SHIFT (20U)
3872/*! CFG4 - Specifies the match contribution condition for bit slice 4.
3873 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
3874 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
3875 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3876 * PMSRC registers are written to.
3877 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
3878 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3879 * PMSRC registers are written to.
3880 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
3881 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
3882 * cleared when the PMCFG or the PMSRC registers are written to.
3883 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
3884 * 0b101..Low level. Match occurs when there is a low level on the specified input.
3885 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
3886 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
3887 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
3888 * is cleared after one clock cycle.
3889 */
3890#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
3891#define PINT_PMCFG_CFG5_MASK (0x3800000U)
3892#define PINT_PMCFG_CFG5_SHIFT (23U)
3893/*! CFG5 - Specifies the match contribution condition for bit slice 5.
3894 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
3895 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
3896 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3897 * PMSRC registers are written to.
3898 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
3899 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3900 * PMSRC registers are written to.
3901 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
3902 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
3903 * cleared when the PMCFG or the PMSRC registers are written to.
3904 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
3905 * 0b101..Low level. Match occurs when there is a low level on the specified input.
3906 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
3907 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
3908 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
3909 * is cleared after one clock cycle.
3910 */
3911#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
3912#define PINT_PMCFG_CFG6_MASK (0x1C000000U)
3913#define PINT_PMCFG_CFG6_SHIFT (26U)
3914/*! CFG6 - Specifies the match contribution condition for bit slice 6.
3915 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
3916 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
3917 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3918 * PMSRC registers are written to.
3919 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
3920 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3921 * PMSRC registers are written to.
3922 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
3923 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
3924 * cleared when the PMCFG or the PMSRC registers are written to.
3925 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
3926 * 0b101..Low level. Match occurs when there is a low level on the specified input.
3927 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
3928 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
3929 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
3930 * is cleared after one clock cycle.
3931 */
3932#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
3933#define PINT_PMCFG_CFG7_MASK (0xE0000000U)
3934#define PINT_PMCFG_CFG7_SHIFT (29U)
3935/*! CFG7 - Specifies the match contribution condition for bit slice 7.
3936 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
3937 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
3938 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3939 * PMSRC registers are written to.
3940 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
3941 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
3942 * PMSRC registers are written to.
3943 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
3944 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
3945 * cleared when the PMCFG or the PMSRC registers are written to.
3946 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
3947 * 0b101..Low level. Match occurs when there is a low level on the specified input.
3948 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
3949 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
3950 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
3951 * is cleared after one clock cycle.
3952 */
3953#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
3954/*! @} */
3955
3956
3957/*!
3958 * @}
3959 */ /* end of group PINT_Register_Masks */
3960
3961
3962/* PINT - Peripheral instance base addresses */
3963/** Peripheral PINT base address */
3964#define PINT_BASE (0xA0004000u)
3965/** Peripheral PINT base pointer */
3966#define PINT ((PINT_Type *)PINT_BASE)
3967/** Array initializer of PINT peripheral base addresses */
3968#define PINT_BASE_ADDRS { PINT_BASE }
3969/** Array initializer of PINT peripheral base pointers */
3970#define PINT_BASE_PTRS { PINT }
3971/** Interrupt vectors for the PINT peripheral type */
3972#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }
3973
3974/*!
3975 * @}
3976 */ /* end of group PINT_Peripheral_Access_Layer */
3977
3978
3979/* ----------------------------------------------------------------------------
3980 -- PMU Peripheral Access Layer
3981 ---------------------------------------------------------------------------- */
3982
3983/*!
3984 * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer
3985 * @{
3986 */
3987
3988/** PMU - Register Layout Typedef */
3989typedef struct {
3990 __IO uint32_t PCON; /**< Power control register, offset: 0x0 */
3991 __IO uint32_t GPREG[4]; /**< General purpose register N, array offset: 0x4, array step: 0x4 */
3992 __IO uint32_t DPDCTRL; /**< Deep power-down control register. Also includes bits for general purpose storage., offset: 0x14 */
3993} PMU_Type;
3994
3995/* ----------------------------------------------------------------------------
3996 -- PMU Register Masks
3997 ---------------------------------------------------------------------------- */
3998
3999/*!
4000 * @addtogroup PMU_Register_Masks PMU Register Masks
4001 * @{
4002 */
4003
4004/*! @name PCON - Power control register */
4005/*! @{ */
4006#define PMU_PCON_PM_MASK (0x7U)
4007#define PMU_PCON_PM_SHIFT (0U)
4008/*! PM - Power mode
4009 * 0b000..Default. The part is in active or sleep mode.
4010 * 0b001..Deep-sleep mode. ARM WFI will enter Deep-sleep mode.
4011 * 0b010..Power-down mode. ARM WFI will enter Power-down mode.
4012 * 0b011..Deep power-down mode. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down).
4013 */
4014#define PMU_PCON_PM(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_PM_SHIFT)) & PMU_PCON_PM_MASK)
4015#define PMU_PCON_NODPD_MASK (0x8U)
4016#define PMU_PCON_NODPD_SHIFT (3U)
4017/*! NODPD - A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM
4018 * field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by
4019 * power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode
4020 * is blocked.
4021 */
4022#define PMU_PCON_NODPD(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_NODPD_SHIFT)) & PMU_PCON_NODPD_MASK)
4023#define PMU_PCON_SLEEPFLAG_MASK (0x100U)
4024#define PMU_PCON_SLEEPFLAG_SHIFT (8U)
4025/*! SLEEPFLAG - Sleep mode flag
4026 * 0b0..Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect.
4027 * 0b1..Low power mode. Read: Sleep, Deep-sleep or Power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0.
4028 */
4029#define PMU_PCON_SLEEPFLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_SLEEPFLAG_SHIFT)) & PMU_PCON_SLEEPFLAG_MASK)
4030#define PMU_PCON_DPDFLAG_MASK (0x800U)
4031#define PMU_PCON_DPDFLAG_SHIFT (11U)
4032/*! DPDFLAG - Deep power-down flag
4033 * 0b0..Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect.
4034 * 0b1..Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag.
4035 */
4036#define PMU_PCON_DPDFLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_DPDFLAG_SHIFT)) & PMU_PCON_DPDFLAG_MASK)
4037/*! @} */
4038
4039/*! @name GPREG - General purpose register N */
4040/*! @{ */
4041#define PMU_GPREG_GPDATA_MASK (0xFFFFFFFFU)
4042#define PMU_GPREG_GPDATA_SHIFT (0U)
4043/*! GPDATA - Data retained during Deep power-down mode.
4044 */
4045#define PMU_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPREG_GPDATA_SHIFT)) & PMU_GPREG_GPDATA_MASK)
4046/*! @} */
4047
4048/* The count of PMU_GPREG */
4049#define PMU_GPREG_COUNT (4U)
4050
4051/*! @name DPDCTRL - Deep power-down control register. Also includes bits for general purpose storage. */
4052/*! @{ */
4053#define PMU_DPDCTRL_WAKEUPHYS_MASK (0x1U)
4054#define PMU_DPDCTRL_WAKEUPHYS_SHIFT (0U)
4055/*! WAKEUPHYS - WAKEUP pin hysteresis enable
4056 * 0b0..Disabled. Hysteresis for WAKEUP pin disabled.
4057 * 0b1..Enabled. Hysteresis for WAKEUP pin enabled.
4058 */
4059#define PMU_DPDCTRL_WAKEUPHYS(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_WAKEUPHYS_SHIFT)) & PMU_DPDCTRL_WAKEUPHYS_MASK)
4060#define PMU_DPDCTRL_WAKEPAD_DISABLE_MASK (0x2U)
4061#define PMU_DPDCTRL_WAKEPAD_DISABLE_SHIFT (1U)
4062/*! WAKEPAD_DISABLE - WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be
4063 * used for other purposes. Remark: Never set this bit if you intend to use a pin to wake up the
4064 * part from Deep power-down mode. You can only disable the wake-up pin if the self wake-up timer
4065 * is enabled and configured. Remark: Setting this bit is not necessary if Deep power-down mode is
4066 * not used.
4067 * 0b0..Enabled. The wake-up function is enabled on pin PIO0_4.
4068 * 0b1..Disabled. Setting this bit disables the wake-up function on pin PIO0_4.
4069 */
4070#define PMU_DPDCTRL_WAKEPAD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_WAKEPAD_DISABLE_SHIFT)) & PMU_DPDCTRL_WAKEPAD_DISABLE_MASK)
4071#define PMU_DPDCTRL_LPOSCEN_MASK (0x4U)
4072#define PMU_DPDCTRL_LPOSCEN_SHIFT (2U)
4073/*! LPOSCEN - Enable the low-power oscillator for use with the 10 kHz self wake-up timer clock. You
4074 * must set this bit if the CLKSEL bit in the self wake-up timer CTRL bit is set. Do not enable
4075 * the low-power oscillator if the self wake-up timer is clocked by the divided IRC or the
4076 * external clock input.
4077 * 0b0..Disabled.
4078 * 0b1..Enabled.
4079 */
4080#define PMU_DPDCTRL_LPOSCEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_LPOSCEN_SHIFT)) & PMU_DPDCTRL_LPOSCEN_MASK)
4081#define PMU_DPDCTRL_LPOSCDPDEN_MASK (0x8U)
4082#define PMU_DPDCTRL_LPOSCDPDEN_SHIFT (3U)
4083/*! LPOSCDPDEN - causes the low-power oscillator to remain running during Deep power-down mode
4084 * provided that bit 2 in this register is set as well. You must set this bit for the self wake-up
4085 * timer to be able to wake up the part from Deep power-down mode. Remark: Do not set this bit
4086 * unless you use the self wake-up timer with the low-power oscillator clock source to wake up from
4087 * Deep power-down mode.
4088 * 0b0..Disabled.
4089 * 0b1..Enabled.
4090 */
4091#define PMU_DPDCTRL_LPOSCDPDEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_LPOSCDPDEN_SHIFT)) & PMU_DPDCTRL_LPOSCDPDEN_MASK)
4092#define PMU_DPDCTRL_WAKEUPCLKHYS_MASK (0x10U)
4093#define PMU_DPDCTRL_WAKEUPCLKHYS_SHIFT (4U)
4094/*! WAKEUPCLKHYS - External clock input for the self wake-up timer WKTCLKIN hysteresis enable.
4095 * 0b0..Disabled. Hysteresis for WAKEUP clock pin disabled.
4096 * 0b1..Enabled. Hysteresis for WAKEUP clock pin enabled.
4097 */
4098#define PMU_DPDCTRL_WAKEUPCLKHYS(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_WAKEUPCLKHYS_SHIFT)) & PMU_DPDCTRL_WAKEUPCLKHYS_MASK)
4099#define PMU_DPDCTRL_WAKECLKPAD_DISABLE_MASK (0x20U)
4100#define PMU_DPDCTRL_WAKECLKPAD_DISABLE_SHIFT (5U)
4101/*! WAKECLKPAD_DISABLE - Disable the external clock input for the self wake-up timer. Setting this
4102 * bit enables the self wake-up timer clock pin WKTCLKLIN. To minimize power consumption,
4103 * especially in deep power-down mode, disable this clock input when not using the external clock option
4104 * for the self wake-up timer.
4105 * 0b0..Disabled. Setting this bit disables external clock input on pin PIO0_28.
4106 * 0b1..Enabled. The external clock input for the self wake-up timer is enabled on pin PIO0_28.
4107 */
4108#define PMU_DPDCTRL_WAKECLKPAD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_WAKECLKPAD_DISABLE_SHIFT)) & PMU_DPDCTRL_WAKECLKPAD_DISABLE_MASK)
4109#define PMU_DPDCTRL_GPDATA_MASK (0xFFFFFFC0U)
4110#define PMU_DPDCTRL_GPDATA_SHIFT (6U)
4111/*! GPDATA - Data retained during Deep power-down mode.
4112 */
4113#define PMU_DPDCTRL_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_GPDATA_SHIFT)) & PMU_DPDCTRL_GPDATA_MASK)
4114/*! @} */
4115
4116
4117/*!
4118 * @}
4119 */ /* end of group PMU_Register_Masks */
4120
4121
4122/* PMU - Peripheral instance base addresses */
4123/** Peripheral PMU base address */
4124#define PMU_BASE (0x40020000u)
4125/** Peripheral PMU base pointer */
4126#define PMU ((PMU_Type *)PMU_BASE)
4127/** Array initializer of PMU peripheral base addresses */
4128#define PMU_BASE_ADDRS { PMU_BASE }
4129/** Array initializer of PMU peripheral base pointers */
4130#define PMU_BASE_PTRS { PMU }
4131
4132/*!
4133 * @}
4134 */ /* end of group PMU_Peripheral_Access_Layer */
4135
4136
4137/* ----------------------------------------------------------------------------
4138 -- SCT Peripheral Access Layer
4139 ---------------------------------------------------------------------------- */
4140
4141/*!
4142 * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
4143 * @{
4144 */
4145
4146/** SCT - Register Layout Typedef */
4147typedef struct {
4148 __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */
4149 union { /* offset: 0x4 */
4150 struct { /* offset: 0x4 */
4151 __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */
4152 __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */
4153 } CTRL_ACCESS16BIT;
4154 __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */
4155 };
4156 union { /* offset: 0x8 */
4157 struct { /* offset: 0x8 */
4158 __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */
4159 __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */
4160 } LIMIT_ACCESS16BIT;
4161 __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */
4162 };
4163 union { /* offset: 0xC */
4164 struct { /* offset: 0xC */
4165 __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */
4166 __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */
4167 } HALT_ACCESS16BIT;
4168 __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */
4169 };
4170 union { /* offset: 0x10 */
4171 struct { /* offset: 0x10 */
4172 __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */
4173 __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */
4174 } STOP_ACCESS16BIT;
4175 __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */
4176 };
4177 union { /* offset: 0x14 */
4178 struct { /* offset: 0x14 */
4179 __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */
4180 __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */
4181 } START_ACCESS16BIT;
4182 __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */
4183 };
4184 uint8_t RESERVED_0[40];
4185 union { /* offset: 0x40 */
4186 struct { /* offset: 0x40 */
4187 __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */
4188 __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */
4189 } COUNT_ACCESS16BIT;
4190 __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */
4191 };
4192 union { /* offset: 0x44 */
4193 struct { /* offset: 0x44 */
4194 __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */
4195 __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */
4196 } STATE_ACCESS16BIT;
4197 __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */
4198 };
4199 __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */
4200 union { /* offset: 0x4C */
4201 struct { /* offset: 0x4C */
4202 __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */
4203 __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */
4204 } REGMODE_ACCESS16BIT;
4205 __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */
4206 };
4207 __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */
4208 __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */
4209 __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */
4210 __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */
4211 __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */
4212 uint8_t RESERVED_1[140];
4213 __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */
4214 __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */
4215 __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */
4216 __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */
4217 union { /* offset: 0x100 */
4218 union { /* offset: 0x100, array step: 0x4 */
4219 struct { /* offset: 0x100, array step: 0x4 */
4220 __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */
4221 __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */
4222 } CAP_ACCESS16BIT[8];
4223 __IO uint32_t CAP[8]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */
4224 };
4225 union { /* offset: 0x100, array step: 0x4 */
4226 struct { /* offset: 0x100, array step: 0x4 */
4227 __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */
4228 __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */
4229 } MATCH_ACCESS16BIT[8];
4230 __IO uint32_t MATCH[8]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */
4231 };
4232 };
4233 uint8_t RESERVED_2[224];
4234 union { /* offset: 0x200 */
4235 union { /* offset: 0x200, array step: 0x4 */
4236 struct { /* offset: 0x200, array step: 0x4 */
4237 __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */
4238 __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */
4239 } CAPCTRL_ACCESS16BIT[8];
4240 __IO uint32_t CAPCTRL[8]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */
4241 };
4242 union { /* offset: 0x200, array step: 0x4 */
4243 struct { /* offset: 0x200, array step: 0x4 */
4244 __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */
4245 __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */
4246 } MATCHREL_ACCESS16BIT[8];
4247 __IO uint32_t MATCHREL[8]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */
4248 };
4249 };
4250 uint8_t RESERVED_3[224];
4251 struct { /* offset: 0x300, array step: 0x8 */
4252 __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */
4253 __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */
4254 } EV[8];
4255 uint8_t RESERVED_4[448];
4256 struct { /* offset: 0x500, array step: 0x8 */
4257 __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */
4258 __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */
4259 } OUT[6];
4260} SCT_Type;
4261
4262/* ----------------------------------------------------------------------------
4263 -- SCT Register Masks
4264 ---------------------------------------------------------------------------- */
4265
4266/*!
4267 * @addtogroup SCT_Register_Masks SCT Register Masks
4268 * @{
4269 */
4270
4271/*! @name CONFIG - SCT configuration register */
4272/*! @{ */
4273#define SCT_CONFIG_UNIFY_MASK (0x1U)
4274#define SCT_CONFIG_UNIFY_SHIFT (0U)
4275/*! UNIFY - SCT operation
4276 * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.
4277 * 0b1..The SCT operates as a unified 32-bit counter.
4278 */
4279#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
4280#define SCT_CONFIG_CLKMODE_MASK (0x6U)
4281#define SCT_CONFIG_CLKMODE_SHIFT (1U)
4282/*! CLKMODE - SCT clock mode
4283 * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers.
4284 * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are
4285 * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The
4286 * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the
4287 * high-performance, sampled-clock mode.
4288 * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the
4289 * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the
4290 * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.
4291 * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL
4292 * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system
4293 * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than
4294 * the system clock.
4295 */
4296#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
4297#define SCT_CONFIG_CKSEL_MASK (0x78U)
4298#define SCT_CONFIG_CKSEL_SHIFT (3U)
4299/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent
4300 * on the CLKMODE bit selection in this register.
4301 * 0b0000..Rising edges on input 0.
4302 * 0b0001..Falling edges on input 0.
4303 * 0b0010..Rising edges on input 1.
4304 * 0b0011..Falling edges on input 1.
4305 * 0b0100..Rising edges on input 2.
4306 * 0b0101..Falling edges on input 2.
4307 * 0b0110..Rising edges on input 3.
4308 * 0b0111..Falling edges on input 3.
4309 */
4310#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
4311#define SCT_CONFIG_NORELOAD_L_MASK (0x80U)
4312#define SCT_CONFIG_NORELOAD_L_SHIFT (7U)
4313/*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their
4314 * respective reload registers. Setting this bit eliminates the need to write to the reload
4315 * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any
4316 * time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
4317 */
4318#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK)
4319#define SCT_CONFIG_NORELOAD_H_MASK (0x100U)
4320#define SCT_CONFIG_NORELOAD_H_SHIFT (8U)
4321/*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their
4322 * respective reload registers. Setting this bit eliminates the need to write to the reload
4323 * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at
4324 * any time. This bit is not used when the UNIFY bit is set.
4325 */
4326#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
4327#define SCT_CONFIG_INSYNC_MASK (0x1E00U)
4328#define SCT_CONFIG_INSYNC_SHIFT (9U)
4329/*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all
4330 * other bits are reserved. A 1 in one of these bits subjects the corresponding input to
4331 * synchronization to the SCT clock, before it is used to create an event. If an input is known to
4332 * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note:
4333 * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input
4334 * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation.
4335 * It does not apply to the clock input specified in the CKSEL field.
4336 */
4337#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
4338#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U)
4339#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U)
4340/*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto
4341 * LIMIT condition without the need to define an associated event. As with any LIMIT event, this
4342 * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change
4343 * the direction of count in bi-directional mode. Software can write to set or clear this bit at
4344 * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
4345 */
4346#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
4347#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U)
4348#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U)
4349/*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a
4350 * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event,
4351 * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to
4352 * change the direction of count in bi-directional mode. Software can write to set or clear this bit
4353 * at any time. This bit is not used when the UNIFY bit is set.
4354 */
4355#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
4356/*! @} */
4357
4358/*! @name CTRLL - SCT_CTRLL register */
4359/*! @{ */
4360#define SCT_CTRLL_DOWN_L_MASK (0x1U)
4361#define SCT_CTRLL_DOWN_L_SHIFT (0U)
4362/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit
4363 * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit
4364 * when the counter is counting down and a limit condition occurs or when the counter reaches 0.
4365 */
4366#define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK)
4367#define SCT_CTRLL_STOP_L_MASK (0x2U)
4368#define SCT_CTRLL_STOP_L_SHIFT (1U)
4369/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events
4370 * related to the counter can occur. If a designated start event occurs, this bit is cleared and
4371 * counting resumes.
4372 */
4373#define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK)
4374#define SCT_CTRLL_HALT_L_MASK (0x4U)
4375#define SCT_CTRLL_HALT_L_SHIFT (2U)
4376/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A
4377 * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to
4378 * remove the halt condition while keeping the SCT in the stop condition (not running) with a
4379 * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set,
4380 * only software can clear this bit to restore counter operation. This bit is set on reset.
4381 */
4382#define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK)
4383#define SCT_CTRLL_CLRCTR_L_MASK (0x8U)
4384#define SCT_CTRLL_CLRCTR_L_SHIFT (3U)
4385/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
4386 */
4387#define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK)
4388#define SCT_CTRLL_BIDIR_L_MASK (0x10U)
4389#define SCT_CTRLL_BIDIR_L_SHIFT (4U)
4390/*! BIDIR_L - L or unified counter direction select
4391 * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
4392 * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
4393 */
4394#define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK)
4395#define SCT_CTRLL_PRE_L_MASK (0x1FE0U)
4396#define SCT_CTRLL_PRE_L_SHIFT (5U)
4397/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified
4398 * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1.
4399 * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
4400 */
4401#define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK)
4402/*! @} */
4403
4404/*! @name CTRLH - SCT_CTRLH register */
4405/*! @{ */
4406#define SCT_CTRLH_DOWN_H_MASK (0x1U)
4407#define SCT_CTRLH_DOWN_H_SHIFT (0U)
4408/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the
4409 * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit
4410 * when the counter is counting down and a limit condition occurs or when the counter reaches 0.
4411 */
4412#define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK)
4413#define SCT_CTRLH_STOP_H_MASK (0x2U)
4414#define SCT_CTRLH_STOP_H_SHIFT (1U)
4415/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to
4416 * the counter can occur. If such an event matches the mask in the Start register, this bit is
4417 * cleared and counting resumes.
4418 */
4419#define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK)
4420#define SCT_CTRLH_HALT_H_MASK (0x4U)
4421#define SCT_CTRLH_HALT_H_SHIFT (2U)
4422/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets
4423 * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the
4424 * halt condition while keeping the SCT in the stop condition (not running) with a single write to
4425 * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit
4426 * can only be cleared by software to restore counter operation. This bit is set on reset.
4427 */
4428#define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK)
4429#define SCT_CTRLH_CLRCTR_H_MASK (0x8U)
4430#define SCT_CTRLH_CLRCTR_H_SHIFT (3U)
4431/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0.
4432 */
4433#define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK)
4434#define SCT_CTRLH_BIDIR_H_MASK (0x10U)
4435#define SCT_CTRLH_BIDIR_H_SHIFT (4U)
4436/*! BIDIR_H - Direction select
4437 * 0b0..The H counter counts up to its limit condition, then is cleared to zero.
4438 * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0.
4439 */
4440#define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK)
4441#define SCT_CTRLH_PRE_H_MASK (0x1FE0U)
4442#define SCT_CTRLH_PRE_H_SHIFT (5U)
4443/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock.
4444 * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the
4445 * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
4446 */
4447#define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK)
4448/*! @} */
4449
4450/*! @name CTRL - SCT control register */
4451/*! @{ */
4452#define SCT_CTRL_DOWN_L_MASK (0x1U)
4453#define SCT_CTRL_DOWN_L_SHIFT (0U)
4454/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit
4455 * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit
4456 * when the counter is counting down and a limit condition occurs or when the counter reaches 0.
4457 */
4458#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
4459#define SCT_CTRL_STOP_L_MASK (0x2U)
4460#define SCT_CTRL_STOP_L_SHIFT (1U)
4461/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events
4462 * related to the counter can occur. If a designated start event occurs, this bit is cleared and
4463 * counting resumes.
4464 */
4465#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
4466#define SCT_CTRL_HALT_L_MASK (0x4U)
4467#define SCT_CTRL_HALT_L_SHIFT (2U)
4468/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A
4469 * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to
4470 * remove the halt condition while keeping the SCT in the stop condition (not running) with a
4471 * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set,
4472 * only software can clear this bit to restore counter operation. This bit is set on reset.
4473 */
4474#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
4475#define SCT_CTRL_CLRCTR_L_MASK (0x8U)
4476#define SCT_CTRL_CLRCTR_L_SHIFT (3U)
4477/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
4478 */
4479#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
4480#define SCT_CTRL_BIDIR_L_MASK (0x10U)
4481#define SCT_CTRL_BIDIR_L_SHIFT (4U)
4482/*! BIDIR_L - L or unified counter direction select
4483 * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
4484 * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
4485 */
4486#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
4487#define SCT_CTRL_PRE_L_MASK (0x1FE0U)
4488#define SCT_CTRL_PRE_L_SHIFT (5U)
4489/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified
4490 * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1.
4491 * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
4492 */
4493#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
4494#define SCT_CTRL_DOWN_H_MASK (0x10000U)
4495#define SCT_CTRL_DOWN_H_SHIFT (16U)
4496/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the
4497 * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit
4498 * when the counter is counting down and a limit condition occurs or when the counter reaches 0.
4499 */
4500#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
4501#define SCT_CTRL_STOP_H_MASK (0x20000U)
4502#define SCT_CTRL_STOP_H_SHIFT (17U)
4503/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to
4504 * the counter can occur. If such an event matches the mask in the Start register, this bit is
4505 * cleared and counting resumes.
4506 */
4507#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
4508#define SCT_CTRL_HALT_H_MASK (0x40000U)
4509#define SCT_CTRL_HALT_H_SHIFT (18U)
4510/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets
4511 * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the
4512 * halt condition while keeping the SCT in the stop condition (not running) with a single write to
4513 * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit
4514 * can only be cleared by software to restore counter operation. This bit is set on reset.
4515 */
4516#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
4517#define SCT_CTRL_CLRCTR_H_MASK (0x80000U)
4518#define SCT_CTRL_CLRCTR_H_SHIFT (19U)
4519/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0.
4520 */
4521#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
4522#define SCT_CTRL_BIDIR_H_MASK (0x100000U)
4523#define SCT_CTRL_BIDIR_H_SHIFT (20U)
4524/*! BIDIR_H - Direction select
4525 * 0b0..The H counter counts up to its limit condition, then is cleared to zero.
4526 * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0.
4527 */
4528#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
4529#define SCT_CTRL_PRE_H_MASK (0x1FE00000U)
4530#define SCT_CTRL_PRE_H_SHIFT (21U)
4531/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock.
4532 * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the
4533 * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
4534 */
4535#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
4536/*! @} */
4537
4538/*! @name LIMITL - SCT_LIMITL register */
4539/*! @{ */
4540#define SCT_LIMITL_LIMITL_MASK (0xFFFFU)
4541#define SCT_LIMITL_LIMITL_SHIFT (0U)
4542#define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK)
4543/*! @} */
4544
4545/*! @name LIMITH - SCT_LIMITH register */
4546/*! @{ */
4547#define SCT_LIMITH_LIMITH_MASK (0xFFFFU)
4548#define SCT_LIMITH_LIMITH_SHIFT (0U)
4549#define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK)
4550/*! @} */
4551
4552/*! @name LIMIT - SCT limit event select register */
4553/*! @{ */
4554#define SCT_LIMIT_LIMMSK_L_MASK (0xFFU)
4555#define SCT_LIMIT_LIMMSK_L_SHIFT (0U)
4556/*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter
4557 * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
4558 */
4559#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
4560#define SCT_LIMIT_LIMMSK_H_MASK (0xFF0000U)
4561#define SCT_LIMIT_LIMMSK_H_SHIFT (16U)
4562/*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit
4563 * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
4564 */
4565#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
4566/*! @} */
4567
4568/*! @name HALTL - SCT_HALTL register */
4569/*! @{ */
4570#define SCT_HALTL_HALTL_MASK (0xFFFFU)
4571#define SCT_HALTL_HALTL_SHIFT (0U)
4572#define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK)
4573/*! @} */
4574
4575/*! @name HALTH - SCT_HALTH register */
4576/*! @{ */
4577#define SCT_HALTH_HALTH_MASK (0xFFFFU)
4578#define SCT_HALTH_HALTH_SHIFT (0U)
4579#define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK)
4580/*! @} */
4581
4582/*! @name HALT - SCT halt event select register */
4583/*! @{ */
4584#define SCT_HALT_HALTMSK_L_MASK (0xFFU)
4585#define SCT_HALT_HALTMSK_L_SHIFT (0U)
4586/*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0,
4587 * event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
4588 */
4589#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
4590#define SCT_HALT_HALTMSK_H_MASK (0xFF0000U)
4591#define SCT_HALT_HALTMSK_H_SHIFT (16U)
4592/*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16,
4593 * event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
4594 */
4595#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
4596/*! @} */
4597
4598/*! @name STOPL - SCT_STOPL register */
4599/*! @{ */
4600#define SCT_STOPL_STOPL_MASK (0xFFFFU)
4601#define SCT_STOPL_STOPL_SHIFT (0U)
4602#define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK)
4603/*! @} */
4604
4605/*! @name STOPH - SCT_STOPH register */
4606/*! @{ */
4607#define SCT_STOPH_STOPH_MASK (0xFFFFU)
4608#define SCT_STOPH_STOPH_SHIFT (0U)
4609#define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK)
4610/*! @} */
4611
4612/*! @name STOP - SCT stop event select register */
4613/*! @{ */
4614#define SCT_STOP_STOPMSK_L_MASK (0xFFU)
4615#define SCT_STOP_STOPMSK_L_SHIFT (0U)
4616/*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0,
4617 * event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
4618 */
4619#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
4620#define SCT_STOP_STOPMSK_H_MASK (0xFF0000U)
4621#define SCT_STOP_STOPMSK_H_SHIFT (16U)
4622/*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16,
4623 * event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
4624 */
4625#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
4626/*! @} */
4627
4628/*! @name STARTL - SCT_STARTL register */
4629/*! @{ */
4630#define SCT_STARTL_STARTL_MASK (0xFFFFU)
4631#define SCT_STARTL_STARTL_SHIFT (0U)
4632#define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK)
4633/*! @} */
4634
4635/*! @name STARTH - SCT_STARTH register */
4636/*! @{ */
4637#define SCT_STARTH_STARTH_MASK (0xFFFFU)
4638#define SCT_STARTH_STARTH_SHIFT (0U)
4639#define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK)
4640/*! @} */
4641
4642/*! @name START - SCT start event select register */
4643/*! @{ */
4644#define SCT_START_STARTMSK_L_MASK (0xFFU)
4645#define SCT_START_STARTMSK_L_SHIFT (0U)
4646/*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit
4647 * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
4648 */
4649#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
4650#define SCT_START_STARTMSK_H_MASK (0xFF0000U)
4651#define SCT_START_STARTMSK_H_SHIFT (16U)
4652/*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit
4653 * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
4654 */
4655#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
4656/*! @} */
4657
4658/*! @name COUNTL - SCT_COUNTL register */
4659/*! @{ */
4660#define SCT_COUNTL_COUNTL_MASK (0xFFFFU)
4661#define SCT_COUNTL_COUNTL_SHIFT (0U)
4662#define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK)
4663/*! @} */
4664
4665/*! @name COUNTH - SCT_COUNTH register */
4666/*! @{ */
4667#define SCT_COUNTH_COUNTH_MASK (0xFFFFU)
4668#define SCT_COUNTH_COUNTH_SHIFT (0U)
4669#define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK)
4670/*! @} */
4671
4672/*! @name COUNT - SCT counter register */
4673/*! @{ */
4674#define SCT_COUNT_CTR_L_MASK (0xFFFFU)
4675#define SCT_COUNT_CTR_L_SHIFT (0U)
4676/*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write
4677 * the lower 16 bits of the 32-bit unified counter.
4678 */
4679#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
4680#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U)
4681#define SCT_COUNT_CTR_H_SHIFT (16U)
4682/*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write
4683 * the upper 16 bits of the 32-bit unified counter.
4684 */
4685#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
4686/*! @} */
4687
4688/*! @name STATEL - SCT_STATEL register */
4689/*! @{ */
4690#define SCT_STATEL_STATEL_MASK (0xFFFFU)
4691#define SCT_STATEL_STATEL_SHIFT (0U)
4692#define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK)
4693/*! @} */
4694
4695/*! @name STATEH - SCT_STATEH register */
4696/*! @{ */
4697#define SCT_STATEH_STATEH_MASK (0xFFFFU)
4698#define SCT_STATEH_STATEH_SHIFT (0U)
4699#define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK)
4700/*! @} */
4701
4702/*! @name STATE - SCT state register */
4703/*! @{ */
4704#define SCT_STATE_STATE_L_MASK (0x1FU)
4705#define SCT_STATE_STATE_L_SHIFT (0U)
4706/*! STATE_L - State variable.
4707 */
4708#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
4709#define SCT_STATE_STATE_H_MASK (0x1F0000U)
4710#define SCT_STATE_STATE_H_SHIFT (16U)
4711/*! STATE_H - State variable.
4712 */
4713#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
4714/*! @} */
4715
4716/*! @name INPUT - SCT input register */
4717/*! @{ */
4718#define SCT_INPUT_AIN0_MASK (0x1U)
4719#define SCT_INPUT_AIN0_SHIFT (0U)
4720/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge.
4721 */
4722#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
4723#define SCT_INPUT_AIN1_MASK (0x2U)
4724#define SCT_INPUT_AIN1_SHIFT (1U)
4725/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge.
4726 */
4727#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
4728#define SCT_INPUT_AIN2_MASK (0x4U)
4729#define SCT_INPUT_AIN2_SHIFT (2U)
4730/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge.
4731 */
4732#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
4733#define SCT_INPUT_AIN3_MASK (0x8U)
4734#define SCT_INPUT_AIN3_SHIFT (3U)
4735/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge.
4736 */
4737#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
4738#define SCT_INPUT_SIN0_MASK (0x10000U)
4739#define SCT_INPUT_SIN0_SHIFT (16U)
4740/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC.
4741 */
4742#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
4743#define SCT_INPUT_SIN1_MASK (0x20000U)
4744#define SCT_INPUT_SIN1_SHIFT (17U)
4745/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC.
4746 */
4747#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
4748#define SCT_INPUT_SIN2_MASK (0x40000U)
4749#define SCT_INPUT_SIN2_SHIFT (18U)
4750/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC.
4751 */
4752#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
4753#define SCT_INPUT_SIN3_MASK (0x80000U)
4754#define SCT_INPUT_SIN3_SHIFT (19U)
4755/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC.
4756 */
4757#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
4758/*! @} */
4759
4760/*! @name REGMODEL - SCT_REGMODEL register */
4761/*! @{ */
4762#define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU)
4763#define SCT_REGMODEL_REGMODEL_SHIFT (0U)
4764#define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK)
4765/*! @} */
4766
4767/*! @name REGMODEH - SCT_REGMODEH register */
4768/*! @{ */
4769#define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU)
4770#define SCT_REGMODEH_REGMODEH_SHIFT (0U)
4771#define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK)
4772/*! @} */
4773
4774/*! @name REGMODE - SCT match/capture mode register */
4775/*! @{ */
4776#define SCT_REGMODE_REGMOD_L_MASK (0xFFU)
4777#define SCT_REGMODE_REGMOD_L_SHIFT (0U)
4778/*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1,
4779 * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as
4780 * match register. 1 = register operates as capture register.
4781 */
4782#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
4783#define SCT_REGMODE_REGMOD_H_MASK (0xFF0000U)
4784#define SCT_REGMODE_REGMOD_H_SHIFT (16U)
4785/*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit
4786 * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as
4787 * match registers. 1 = register operates as capture registers.
4788 */
4789#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
4790/*! @} */
4791
4792/*! @name OUTPUT - SCT output register */
4793/*! @{ */
4794#define SCT_OUTPUT_OUT_MASK (0x3FU)
4795#define SCT_OUTPUT_OUT_SHIFT (0U)
4796/*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the
4797 * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of
4798 * outputs in this SCT.
4799 */
4800#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)
4801/*! @} */
4802
4803/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */
4804/*! @{ */
4805#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U)
4806#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U)
4807/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
4808 * 0b00..Set and clear do not depend on the direction of any counter.
4809 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
4810 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
4811 */
4812#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
4813#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU)
4814#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U)
4815/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.
4816 * 0b00..Set and clear do not depend on the direction of any counter.
4817 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
4818 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
4819 */
4820#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
4821#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U)
4822#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U)
4823/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.
4824 * 0b00..Set and clear do not depend on the direction of any counter.
4825 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
4826 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
4827 */
4828#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
4829#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U)
4830#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U)
4831/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.
4832 * 0b00..Set and clear do not depend on the direction of any counter.
4833 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
4834 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
4835 */
4836#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
4837#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U)
4838#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U)
4839/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.
4840 * 0b00..Set and clear do not depend on the direction of any counter.
4841 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
4842 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
4843 */
4844#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
4845#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U)
4846#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U)
4847/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.
4848 * 0b00..Set and clear do not depend on the direction of any counter.
4849 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
4850 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
4851 */
4852#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
4853/*! @} */
4854
4855/*! @name RES - SCT conflict resolution register */
4856/*! @{ */
4857#define SCT_RES_O0RES_MASK (0x3U)
4858#define SCT_RES_O0RES_SHIFT (0U)
4859/*! O0RES - Effect of simultaneous set and clear on output 0.
4860 * 0b00..No change.
4861 * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register).
4862 * 0b10..Clear output (or set based on the SETCLR0 field).
4863 * 0b11..Toggle output.
4864 */
4865#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
4866#define SCT_RES_O1RES_MASK (0xCU)
4867#define SCT_RES_O1RES_SHIFT (2U)
4868/*! O1RES - Effect of simultaneous set and clear on output 1.
4869 * 0b00..No change.
4870 * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register).
4871 * 0b10..Clear output (or set based on the SETCLR1 field).
4872 * 0b11..Toggle output.
4873 */
4874#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
4875#define SCT_RES_O2RES_MASK (0x30U)
4876#define SCT_RES_O2RES_SHIFT (4U)
4877/*! O2RES - Effect of simultaneous set and clear on output 2.
4878 * 0b00..No change.
4879 * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register).
4880 * 0b10..Clear output n (or set based on the SETCLR2 field).
4881 * 0b11..Toggle output.
4882 */
4883#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
4884#define SCT_RES_O3RES_MASK (0xC0U)
4885#define SCT_RES_O3RES_SHIFT (6U)
4886/*! O3RES - Effect of simultaneous set and clear on output 3.
4887 * 0b00..No change.
4888 * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register).
4889 * 0b10..Clear output (or set based on the SETCLR3 field).
4890 * 0b11..Toggle output.
4891 */
4892#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
4893#define SCT_RES_O4RES_MASK (0x300U)
4894#define SCT_RES_O4RES_SHIFT (8U)
4895/*! O4RES - Effect of simultaneous set and clear on output 4.
4896 * 0b00..No change.
4897 * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register).
4898 * 0b10..Clear output (or set based on the SETCLR4 field).
4899 * 0b11..Toggle output.
4900 */
4901#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
4902#define SCT_RES_O5RES_MASK (0xC00U)
4903#define SCT_RES_O5RES_SHIFT (10U)
4904/*! O5RES - Effect of simultaneous set and clear on output 5.
4905 * 0b00..No change.
4906 * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register).
4907 * 0b10..Clear output (or set based on the SETCLR5 field).
4908 * 0b11..Toggle output.
4909 */
4910#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
4911/*! @} */
4912
4913/*! @name DMAREQ0 - SCT DMA request 0 register */
4914/*! @{ */
4915#define SCT_DMAREQ0_DEV_0_MASK (0x3FU)
4916#define SCT_DMAREQ0_DEV_0_SHIFT (0U)
4917/*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1,
4918 * etc.). The number of bits = number of events in this SCT.
4919 */
4920#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK)
4921#define SCT_DMAREQ0_DRL0_MASK (0x40000000U)
4922#define SCT_DMAREQ0_DRL0_SHIFT (30U)
4923/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers.
4924 */
4925#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK)
4926#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U)
4927#define SCT_DMAREQ0_DRQ0_SHIFT (31U)
4928/*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA
4929 * channel is enabled and properly set up, it is unlikely that software will see this flag, it will
4930 * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA
4931 * setup.
4932 */
4933#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK)
4934/*! @} */
4935
4936/*! @name DMAREQ1 - SCT DMA request 1 register */
4937/*! @{ */
4938#define SCT_DMAREQ1_DEV_1_MASK (0x3FU)
4939#define SCT_DMAREQ1_DEV_1_SHIFT (0U)
4940/*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1,
4941 * etc.). The number of bits = number of events in this SCT.
4942 */
4943#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK)
4944#define SCT_DMAREQ1_DRL1_MASK (0x40000000U)
4945#define SCT_DMAREQ1_DRL1_SHIFT (30U)
4946/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
4947 */
4948#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK)
4949#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U)
4950#define SCT_DMAREQ1_DRQ1_SHIFT (31U)
4951/*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA
4952 * channel is enabled and properly set up, it is unlikely that software will see this flag, it will
4953 * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA
4954 * setup.
4955 */
4956#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK)
4957/*! @} */
4958
4959/*! @name EVEN - SCT event interrupt enable register */
4960/*! @{ */
4961#define SCT_EVEN_IEN_MASK (0xFFU)
4962#define SCT_EVEN_IEN_SHIFT (0U)
4963/*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are
4964 * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in
4965 * this SCT.
4966 */
4967#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)
4968/*! @} */
4969
4970/*! @name EVFLAG - SCT event flag register */
4971/*! @{ */
4972#define SCT_EVFLAG_FLAG_MASK (0xFFU)
4973#define SCT_EVFLAG_FLAG_SHIFT (0U)
4974/*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit
4975 * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
4976 */
4977#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)
4978/*! @} */
4979
4980/*! @name CONEN - SCT conflict interrupt enable register */
4981/*! @{ */
4982#define SCT_CONEN_NCEN_MASK (0x3FU)
4983#define SCT_CONEN_NCEN_SHIFT (0U)
4984/*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag
4985 * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of
4986 * outputs in this SCT.
4987 */
4988#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)
4989/*! @} */
4990
4991/*! @name CONFLAG - SCT conflict flag register */
4992/*! @{ */
4993#define SCT_CONFLAG_NCFLAG_MASK (0x3FU)
4994#define SCT_CONFLAG_NCFLAG_SHIFT (0U)
4995/*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was
4996 * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits =
4997 * number of outputs in this SCT.
4998 */
4999#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)
5000#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U)
5001#define SCT_CONFLAG_BUSERRL_SHIFT (30U)
5002/*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE
5003 * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write
5004 * to certain L and H registers can be half successful and half unsuccessful.
5005 */
5006#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
5007#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U)
5008#define SCT_CONFLAG_BUSERRH_SHIFT (31U)
5009/*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or
5010 * the Output register when the H counter was not halted.
5011 */
5012#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
5013/*! @} */
5014
5015/*! @name CAPL - SCT_CAPL register */
5016/*! @{ */
5017#define SCT_CAPL_CAPL_MASK (0xFFFFU)
5018#define SCT_CAPL_CAPL_SHIFT (0U)
5019#define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK)
5020/*! @} */
5021
5022/* The count of SCT_CAPL */
5023#define SCT_CAPL_COUNT (8U)
5024
5025/*! @name CAPH - SCT_CAPH register */
5026/*! @{ */
5027#define SCT_CAPH_CAPH_MASK (0xFFFFU)
5028#define SCT_CAPH_CAPH_SHIFT (0U)
5029#define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK)
5030/*! @} */
5031
5032/* The count of SCT_CAPH */
5033#define SCT_CAPH_COUNT (8U)
5034
5035/*! @name CAP - SCT capture register of capture channel */
5036/*! @{ */
5037#define SCT_CAP_CAPn_L_MASK (0xFFFFU)
5038#define SCT_CAP_CAPn_L_SHIFT (0U)
5039/*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured.
5040 * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last
5041 * captured.
5042 */
5043#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK)
5044#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U)
5045#define SCT_CAP_CAPn_H_SHIFT (16U)
5046/*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured.
5047 * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last
5048 * captured.
5049 */
5050#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK)
5051/*! @} */
5052
5053/* The count of SCT_CAP */
5054#define SCT_CAP_COUNT (8U)
5055
5056/*! @name MATCHL - SCT_MATCHL register */
5057/*! @{ */
5058#define SCT_MATCHL_MATCHL_MASK (0xFFFFU)
5059#define SCT_MATCHL_MATCHL_SHIFT (0U)
5060#define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK)
5061/*! @} */
5062
5063/* The count of SCT_MATCHL */
5064#define SCT_MATCHL_COUNT (8U)
5065
5066/*! @name MATCHH - SCT_MATCHH register */
5067/*! @{ */
5068#define SCT_MATCHH_MATCHH_MASK (0xFFFFU)
5069#define SCT_MATCHH_MATCHH_SHIFT (0U)
5070#define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK)
5071/*! @} */
5072
5073/* The count of SCT_MATCHH */
5074#define SCT_MATCHH_COUNT (8U)
5075
5076/*! @name MATCH - SCT match value register of match channels */
5077/*! @{ */
5078#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU)
5079#define SCT_MATCH_MATCHn_L_SHIFT (0U)
5080/*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When
5081 * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified
5082 * counter.
5083 */
5084#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK)
5085#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U)
5086#define SCT_MATCH_MATCHn_H_SHIFT (16U)
5087/*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When
5088 * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified
5089 * counter.
5090 */
5091#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK)
5092/*! @} */
5093
5094/* The count of SCT_MATCH */
5095#define SCT_MATCH_COUNT (8U)
5096
5097/*! @name CAPCTRLL - SCT_CAPCTRLL register */
5098/*! @{ */
5099#define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU)
5100#define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U)
5101#define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK)
5102/*! @} */
5103
5104/* The count of SCT_CAPCTRLL */
5105#define SCT_CAPCTRLL_COUNT (8U)
5106
5107/*! @name CAPCTRLH - SCT_CAPCTRLH register */
5108/*! @{ */
5109#define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU)
5110#define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U)
5111#define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK)
5112/*! @} */
5113
5114/* The count of SCT_CAPCTRLH */
5115#define SCT_CAPCTRLH_COUNT (8U)
5116
5117/*! @name CAPCTRL - SCT capture control register */
5118/*! @{ */
5119#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFU)
5120#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U)
5121/*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1)
5122 * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of
5123 * match/captures in this SCT.
5124 */
5125#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK)
5126#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFF0000U)
5127#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U)
5128/*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event
5129 * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
5130 */
5131#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK)
5132/*! @} */
5133
5134/* The count of SCT_CAPCTRL */
5135#define SCT_CAPCTRL_COUNT (8U)
5136
5137/*! @name MATCHRELL - SCT_MATCHRELL register */
5138/*! @{ */
5139#define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU)
5140#define SCT_MATCHRELL_MATCHRELL_SHIFT (0U)
5141#define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK)
5142/*! @} */
5143
5144/* The count of SCT_MATCHRELL */
5145#define SCT_MATCHRELL_COUNT (8U)
5146
5147/*! @name MATCHRELH - SCT_MATCHRELH register */
5148/*! @{ */
5149#define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU)
5150#define SCT_MATCHRELH_MATCHRELH_SHIFT (0U)
5151#define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK)
5152/*! @} */
5153
5154/* The count of SCT_MATCHRELH */
5155#define SCT_MATCHRELH_COUNT (8U)
5156
5157/*! @name MATCHREL - SCT match reload value register */
5158/*! @{ */
5159#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU)
5160#define SCT_MATCHREL_RELOADn_L_SHIFT (0U)
5161/*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register.
5162 * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn
5163 * register.
5164 */
5165#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK)
5166#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U)
5167#define SCT_MATCHREL_RELOADn_H_SHIFT (16U)
5168/*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When
5169 * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn
5170 * register.
5171 */
5172#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK)
5173/*! @} */
5174
5175/* The count of SCT_MATCHREL */
5176#define SCT_MATCHREL_COUNT (8U)
5177
5178/*! @name EV_STATE - SCT event state register 0 */
5179/*! @{ */
5180#define SCT_EV_STATE_STATEMSKn_MASK (0xFFU)
5181#define SCT_EV_STATE_STATEMSKn_SHIFT (0U)
5182/*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT
5183 * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of
5184 * bits = number of states in this SCT.
5185 */
5186#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK)
5187/*! @} */
5188
5189/* The count of SCT_EV_STATE */
5190#define SCT_EV_STATE_COUNT (8U)
5191
5192/*! @name EV_CTRL - SCT event control register 0 */
5193/*! @{ */
5194#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU)
5195#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U)
5196/*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur
5197 * only when the counter selected by the HEVENT bit is running.
5198 */
5199#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK)
5200#define SCT_EV_CTRL_HEVENT_MASK (0x10U)
5201#define SCT_EV_CTRL_HEVENT_SHIFT (4U)
5202/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1.
5203 * 0b0..Selects the L state and the L match register selected by MATCHSEL.
5204 * 0b1..Selects the H state and the H match register selected by MATCHSEL.
5205 */
5206#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK)
5207#define SCT_EV_CTRL_OUTSEL_MASK (0x20U)
5208#define SCT_EV_CTRL_OUTSEL_SHIFT (5U)
5209/*! OUTSEL - Input/output select
5210 * 0b0..Selects the inputs selected by IOSEL.
5211 * 0b1..Selects the outputs selected by IOSEL.
5212 */
5213#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK)
5214#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U)
5215#define SCT_EV_CTRL_IOSEL_SHIFT (6U)
5216/*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not
5217 * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit
5218 * ingredient of every event.
5219 */
5220#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK)
5221#define SCT_EV_CTRL_IOCOND_MASK (0xC00U)
5222#define SCT_EV_CTRL_IOCOND_SHIFT (10U)
5223/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the
5224 * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state
5225 * detection, an input must have a minimum pulse width of at least one SCT clock period .
5226 * 0b00..LOW
5227 * 0b01..Rise
5228 * 0b10..Fall
5229 * 0b11..HIGH
5230 */
5231#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK)
5232#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U)
5233#define SCT_EV_CTRL_COMBMODE_SHIFT (12U)
5234/*! COMBMODE - Selects how the specified match and I/O condition are used and combined.
5235 * 0b00..OR. The event occurs when either the specified match or I/O condition occurs.
5236 * 0b01..MATCH. Uses the specified match only.
5237 * 0b10..IO. Uses the specified I/O condition only.
5238 * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously.
5239 */
5240#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK)
5241#define SCT_EV_CTRL_STATELD_MASK (0x4000U)
5242#define SCT_EV_CTRL_STATELD_SHIFT (14U)
5243/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this
5244 * event is the highest-numbered event occurring for that state.
5245 * 0b0..STATEV value is added into STATE (the carry-out is ignored).
5246 * 0b1..STATEV value is loaded into STATE.
5247 */
5248#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK)
5249#define SCT_EV_CTRL_STATEV_MASK (0xF8000U)
5250#define SCT_EV_CTRL_STATEV_SHIFT (15U)
5251/*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on
5252 * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and
5253 * STATEV are both zero, there is no change to the STATE value.
5254 */
5255#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK)
5256#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U)
5257#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U)
5258/*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the
5259 * triggering of this event, then a match is considered to be active whenever the counter value is
5260 * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR
5261 * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active
5262 * during the cycle when the counter is equal to the match value.
5263 */
5264#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK)
5265#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U)
5266#define SCT_EV_CTRL_DIRECTION_SHIFT (21U)
5267/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters
5268 * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
5269 * 0b00..Direction independent. This event is triggered regardless of the count direction.
5270 * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1.
5271 * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1.
5272 */
5273#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK)
5274/*! @} */
5275
5276/* The count of SCT_EV_CTRL */
5277#define SCT_EV_CTRL_COUNT (8U)
5278
5279/*! @name OUT_SET - SCT output 0 set register */
5280/*! @{ */
5281#define SCT_OUT_SET_SET_MASK (0xFFU)
5282#define SCT_OUT_SET_SET_SHIFT (0U)
5283/*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output
5284 * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the
5285 * counter is used in bi-directional mode, it is possible to reverse the action specified by the
5286 * output set and clear registers when counting down, See the OUTPUTCTRL register.
5287 */
5288#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
5289/*! @} */
5290
5291/* The count of SCT_OUT_SET */
5292#define SCT_OUT_SET_COUNT (6U)
5293
5294/*! @name OUT_CLR - SCT output 0 clear register */
5295/*! @{ */
5296#define SCT_OUT_CLR_CLR_MASK (0xFFU)
5297#define SCT_OUT_CLR_CLR_SHIFT (0U)
5298/*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0
5299 * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the
5300 * counter is used in bi-directional mode, it is possible to reverse the action specified by the
5301 * output set and clear registers when counting down, See the OUTPUTCTRL register.
5302 */
5303#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
5304/*! @} */
5305
5306/* The count of SCT_OUT_CLR */
5307#define SCT_OUT_CLR_COUNT (6U)
5308
5309
5310/*!
5311 * @}
5312 */ /* end of group SCT_Register_Masks */
5313
5314
5315/* SCT - Peripheral instance base addresses */
5316/** Peripheral SCT0 base address */
5317#define SCT0_BASE (0x50004000u)
5318/** Peripheral SCT0 base pointer */
5319#define SCT0 ((SCT_Type *)SCT0_BASE)
5320/** Array initializer of SCT peripheral base addresses */
5321#define SCT_BASE_ADDRS { SCT0_BASE }
5322/** Array initializer of SCT peripheral base pointers */
5323#define SCT_BASE_PTRS { SCT0 }
5324/** Interrupt vectors for the SCT peripheral type */
5325#define SCT_IRQS { SCT0_IRQn }
5326
5327/*!
5328 * @}
5329 */ /* end of group SCT_Peripheral_Access_Layer */
5330
5331
5332/* ----------------------------------------------------------------------------
5333 -- SPI Peripheral Access Layer
5334 ---------------------------------------------------------------------------- */
5335
5336/*!
5337 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
5338 * @{
5339 */
5340
5341/** SPI - Register Layout Typedef */
5342typedef struct {
5343 __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x0 */
5344 __IO uint32_t DLY; /**< SPI Delay register, offset: 0x4 */
5345 __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position, offset: 0x8 */
5346 __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */
5347 __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x10 */
5348 __I uint32_t RXDAT; /**< SPI Receive Data, offset: 0x14 */
5349 __IO uint32_t TXDATCTL; /**< SPI Transmit Data with Control, offset: 0x18 */
5350 __IO uint32_t TXDAT; /**< SPI Transmit Data., offset: 0x1C */
5351 __IO uint32_t TXCTL; /**< SPI Transmit Control, offset: 0x20 */
5352 __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x24 */
5353 __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x28 */
5354} SPI_Type;
5355
5356/* ----------------------------------------------------------------------------
5357 -- SPI Register Masks
5358 ---------------------------------------------------------------------------- */
5359
5360/*!
5361 * @addtogroup SPI_Register_Masks SPI Register Masks
5362 * @{
5363 */
5364
5365/*! @name CFG - SPI Configuration register */
5366/*! @{ */
5367#define SPI_CFG_ENABLE_MASK (0x1U)
5368#define SPI_CFG_ENABLE_SHIFT (0U)
5369/*! ENABLE - SPI enable.
5370 * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset.
5371 * 0b1..Enabled. The SPI is enabled for operation.
5372 */
5373#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
5374#define SPI_CFG_MASTER_MASK (0x4U)
5375#define SPI_CFG_MASTER_SHIFT (2U)
5376/*! MASTER - Master mode select.
5377 * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
5378 * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
5379 */
5380#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
5381#define SPI_CFG_LSBF_MASK (0x8U)
5382#define SPI_CFG_LSBF_SHIFT (3U)
5383/*! LSBF - LSB First mode enable.
5384 * 0b0..Standard. Data is transmitted and received in standard MSB first order.
5385 * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first).
5386 */
5387#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
5388#define SPI_CFG_CPHA_MASK (0x10U)
5389#define SPI_CFG_CPHA_SHIFT (4U)
5390/*! CPHA - Clock Phase select.
5391 * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock
5392 * changes away from the rest state). Data is changed on the following edge.
5393 * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock
5394 * changes away from the rest state). Data is captured on the following edge.
5395 */
5396#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
5397#define SPI_CFG_CPOL_MASK (0x20U)
5398#define SPI_CFG_CPOL_SHIFT (5U)
5399/*! CPOL - Clock Polarity select.
5400 * 0b0..Low. The rest state of the clock (between transfers) is low.
5401 * 0b1..High. The rest state of the clock (between transfers) is high.
5402 */
5403#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
5404#define SPI_CFG_LOOP_MASK (0x80U)
5405#define SPI_CFG_LOOP_SHIFT (7U)
5406/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit
5407 * and receive data connected together to allow simple software testing.
5408 * 0b0..Disabled.
5409 * 0b1..Enabled.
5410 */
5411#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
5412#define SPI_CFG_SPOL0_MASK (0x100U)
5413#define SPI_CFG_SPOL0_SHIFT (8U)
5414/*! SPOL0 - SSEL0 Polarity select.
5415 * 0b0..Low. The SSEL0 pin is active low.
5416 * 0b1..High. The SSEL0 pin is active high.
5417 */
5418#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
5419#define SPI_CFG_SPOL1_MASK (0x200U)
5420#define SPI_CFG_SPOL1_SHIFT (9U)
5421/*! SPOL1 - SSEL1 Polarity select.
5422 * 0b0..Low. The SSEL1 pin is active low.
5423 * 0b1..High. The SSEL1 pin is active high.
5424 */
5425#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
5426#define SPI_CFG_SPOL2_MASK (0x400U)
5427#define SPI_CFG_SPOL2_SHIFT (10U)
5428/*! SPOL2 - SSEL2 Polarity select.
5429 * 0b0..Low. The SSEL2 pin is active low.
5430 * 0b1..High. The SSEL2 pin is active high.
5431 */
5432#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
5433#define SPI_CFG_SPOL3_MASK (0x800U)
5434#define SPI_CFG_SPOL3_SHIFT (11U)
5435/*! SPOL3 - SSEL3 Polarity select.
5436 * 0b0..Low. The SSEL3 pin is active low.
5437 * 0b1..High. The SSEL3 pin is active high.
5438 */
5439#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
5440/*! @} */
5441
5442/*! @name DLY - SPI Delay register */
5443/*! @{ */
5444#define SPI_DLY_PRE_DELAY_MASK (0xFU)
5445#define SPI_DLY_PRE_DELAY_SHIFT (0U)
5446/*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data
5447 * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This
5448 * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI
5449 * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are
5450 * inserted.
5451 */
5452#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
5453#define SPI_DLY_POST_DELAY_MASK (0xF0U)
5454#define SPI_DLY_POST_DELAY_SHIFT (4U)
5455/*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL
5456 * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock
5457 * times are inserted. 0xF = 15 SPI clock times are inserted.
5458 */
5459#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
5460#define SPI_DLY_FRAME_DELAY_MASK (0xF00U)
5461#define SPI_DLY_FRAME_DELAY_SHIFT (8U)
5462/*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current
5463 * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1
5464 * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock
5465 * times are inserted.
5466 */
5467#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
5468#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U)
5469#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U)
5470/*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between
5471 * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1
5472 * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that
5473 * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16
5474 * SPI clock times.
5475 */
5476#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
5477/*! @} */
5478
5479/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position */
5480/*! @{ */
5481#define SPI_STAT_RXRDY_MASK (0x1U)
5482#define SPI_STAT_RXRDY_SHIFT (0U)
5483/*! RXRDY - Receiver Ready flag. When 1, indicates that data is available to be read from the
5484 * receiver buffer. Cleared after a read of the RXDAT register.
5485 */
5486#define SPI_STAT_RXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_RXRDY_SHIFT)) & SPI_STAT_RXRDY_MASK)
5487#define SPI_STAT_TXRDY_MASK (0x2U)
5488#define SPI_STAT_TXRDY_SHIFT (1U)
5489/*! TXRDY - Transmitter Ready flag. When 1, this bit indicates that data may be written to the
5490 * transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data
5491 * is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register.
5492 */
5493#define SPI_STAT_TXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_TXRDY_SHIFT)) & SPI_STAT_TXRDY_MASK)
5494#define SPI_STAT_RXOV_MASK (0x4U)
5495#define SPI_STAT_RXOV_SHIFT (2U)
5496/*! RXOV - Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This
5497 * flag is set when the beginning of a received character is detected while the receiver buffer
5498 * is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming
5499 * data is lost. Data received by the SPI should be considered undefined if RxOv is set.
5500 */
5501#define SPI_STAT_RXOV(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_RXOV_SHIFT)) & SPI_STAT_RXOV_MASK)
5502#define SPI_STAT_TXUR_MASK (0x8U)
5503#define SPI_STAT_TXUR_SHIFT (3U)
5504/*! TXUR - Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0).
5505 * In this case, the transmitter must begin sending new data on the next input clock if the
5506 * transmitter is idle. If that data is not available in the transmitter holding register at that
5507 * point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be
5508 * considered undefined if TXUR is set.
5509 */
5510#define SPI_STAT_TXUR(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_TXUR_SHIFT)) & SPI_STAT_TXUR_MASK)
5511#define SPI_STAT_SSA_MASK (0x10U)
5512#define SPI_STAT_SSA_SHIFT (4U)
5513/*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from
5514 * deasserted to asserted, in both master and slave modes. This allows determining when the SPI
5515 * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a
5516 * slave mode access begins. This flag is cleared by software.
5517 */
5518#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
5519#define SPI_STAT_SSD_MASK (0x20U)
5520#define SPI_STAT_SSD_SHIFT (5U)
5521/*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to
5522 * deasserted, in both master and slave modes. This allows determining when the SPI
5523 * transmit/receive functions become idle. This flag is cleared by software.
5524 */
5525#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
5526#define SPI_STAT_STALLED_MASK (0x40U)
5527#define SPI_STAT_STALLED_SHIFT (6U)
5528/*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition.
5529 */
5530#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
5531#define SPI_STAT_ENDTRANSFER_MASK (0x80U)
5532#define SPI_STAT_ENDTRANSFER_SHIFT (7U)
5533/*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current
5534 * transfer when the transmitter finishes any activity already in progress, as if the EOT flag
5535 * had been set prior to the last transmission. This capability is included to support cases where
5536 * it is not known when transmit data is written that it will be the end of a transfer. The bit
5537 * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end
5538 * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
5539 */
5540#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
5541#define SPI_STAT_MSTIDLE_MASK (0x100U)
5542#define SPI_STAT_MSTIDLE_SHIFT (8U)
5543/*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle.
5544 * This means that the transmit holding register is empty and the transmitter is not in the
5545 * process of sending data.
5546 */
5547#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
5548/*! @} */
5549
5550/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
5551/*! @{ */
5552#define SPI_INTENSET_RXRDYEN_MASK (0x1U)
5553#define SPI_INTENSET_RXRDYEN_SHIFT (0U)
5554/*! RXRDYEN - Determines whether an interrupt occurs when receiver data is available.
5555 * 0b0..No interrupt will be generated when receiver data is available.
5556 * 0b1..An interrupt will be generated when receiver data is available in the RXDAT register.
5557 */
5558#define SPI_INTENSET_RXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_RXRDYEN_SHIFT)) & SPI_INTENSET_RXRDYEN_MASK)
5559#define SPI_INTENSET_TXRDYEN_MASK (0x2U)
5560#define SPI_INTENSET_TXRDYEN_SHIFT (1U)
5561/*! TXRDYEN - Determines whether an interrupt occurs when the transmitter holding register is available.
5562 * 0b0..No interrupt will be generated when the transmitter holding register is available.
5563 * 0b1..An interrupt will be generated when data may be written to TXDAT.
5564 */
5565#define SPI_INTENSET_TXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_TXRDYEN_SHIFT)) & SPI_INTENSET_TXRDYEN_MASK)
5566#define SPI_INTENSET_RXOVEN_MASK (0x4U)
5567#define SPI_INTENSET_RXOVEN_SHIFT (2U)
5568/*! RXOVEN - Determines whether an interrupt occurs when a receiver overrun occurs. This happens in
5569 * slave mode when there is a need for the receiver to move newly received data to the RXDAT
5570 * register when it is already in use. The interface prevents receiver overrun in Master mode by not
5571 * allowing a new transmission to begin when a receiver overrun would otherwise occur.
5572 * 0b0..No interrupt will be generated when a receiver overrun occurs.
5573 * 0b1..An interrupt will be generated if a receiver overrun occurs.
5574 */
5575#define SPI_INTENSET_RXOVEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_RXOVEN_SHIFT)) & SPI_INTENSET_RXOVEN_MASK)
5576#define SPI_INTENSET_TXUREN_MASK (0x8U)
5577#define SPI_INTENSET_TXUREN_SHIFT (3U)
5578/*! TXUREN - Determines whether an interrupt occurs when a transmitter underrun occurs. This happens
5579 * in slave mode when there is a need to transmit data when none is available.
5580 * 0b0..No interrupt will be generated when the transmitter underruns.
5581 * 0b1..An interrupt will be generated if the transmitter underruns.
5582 */
5583#define SPI_INTENSET_TXUREN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_TXUREN_SHIFT)) & SPI_INTENSET_TXUREN_MASK)
5584#define SPI_INTENSET_SSAEN_MASK (0x10U)
5585#define SPI_INTENSET_SSAEN_SHIFT (4U)
5586/*! SSAEN - Determines whether an interrupt occurs when the Slave Select is asserted.
5587 * 0b0..No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
5588 * 0b1..An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
5589 */
5590#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
5591#define SPI_INTENSET_SSDEN_MASK (0x20U)
5592#define SPI_INTENSET_SSDEN_SHIFT (5U)
5593/*! SSDEN - Determines whether an interrupt occurs when the Slave Select is deasserted.
5594 * 0b0..No interrupt will be generated when all asserted Slave Selects transition to deasserted.
5595 * 0b1..An interrupt will be generated when all asserted Slave Selects transition to deasserted.
5596 */
5597#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
5598#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U)
5599#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U)
5600/*! MSTIDLEEN - Determines whether an interrupt occurs when the MSTIDLE enable
5601 * 0b0..No interrupt will be generated when MSTIDLE enabled.
5602 * 0b1..An interrupt will be generated when MSTIDLE enabled.
5603 */
5604#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
5605/*! @} */
5606
5607/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */
5608/*! @{ */
5609#define SPI_INTENCLR_RXRDYEN_MASK (0x1U)
5610#define SPI_INTENCLR_RXRDYEN_SHIFT (0U)
5611/*! RXRDYEN - Writing 1 clears the corresponding bits in the INTENSET register.
5612 */
5613#define SPI_INTENCLR_RXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_RXRDYEN_SHIFT)) & SPI_INTENCLR_RXRDYEN_MASK)
5614#define SPI_INTENCLR_TXRDYEN_MASK (0x2U)
5615#define SPI_INTENCLR_TXRDYEN_SHIFT (1U)
5616/*! TXRDYEN - Writing 1 clears the corresponding bits in the INTENSET register.
5617 */
5618#define SPI_INTENCLR_TXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_TXRDYEN_SHIFT)) & SPI_INTENCLR_TXRDYEN_MASK)
5619#define SPI_INTENCLR_RXOVEN_MASK (0x4U)
5620#define SPI_INTENCLR_RXOVEN_SHIFT (2U)
5621/*! RXOVEN - Writing 1 clears the corresponding bits in the INTENSET register.
5622 */
5623#define SPI_INTENCLR_RXOVEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_RXOVEN_SHIFT)) & SPI_INTENCLR_RXOVEN_MASK)
5624#define SPI_INTENCLR_TXUREN_MASK (0x8U)
5625#define SPI_INTENCLR_TXUREN_SHIFT (3U)
5626/*! TXUREN - Writing 1 clears the corresponding bits in the INTENSET register.
5627 */
5628#define SPI_INTENCLR_TXUREN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_TXUREN_SHIFT)) & SPI_INTENCLR_TXUREN_MASK)
5629#define SPI_INTENCLR_SSAEN_MASK (0x10U)
5630#define SPI_INTENCLR_SSAEN_SHIFT (4U)
5631/*! SSAEN - Writing 1 clears the corresponding bits in the INTENSET register.
5632 */
5633#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
5634#define SPI_INTENCLR_SSDEN_MASK (0x20U)
5635#define SPI_INTENCLR_SSDEN_SHIFT (5U)
5636/*! SSDEN - Writing 1 clears the corresponding bits in the INTENSET register.
5637 */
5638#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
5639#define SPI_INTENCLR_MSTIDLE_MASK (0x100U)
5640#define SPI_INTENCLR_MSTIDLE_SHIFT (8U)
5641/*! MSTIDLE - Writing 1 clears the corresponding bits in the INTENSET register.
5642 */
5643#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
5644/*! @} */
5645
5646/*! @name RXDAT - SPI Receive Data */
5647/*! @{ */
5648#define SPI_RXDAT_RXDAT_MASK (0xFFFFU)
5649#define SPI_RXDAT_RXDAT_SHIFT (0U)
5650/*! RXDAT - Receiver Data. This contains the next piece of received data. The number of bits that
5651 * are used depends on the LEN setting in TXCTL / TXDATCTL.
5652 */
5653#define SPI_RXDAT_RXDAT(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXDAT_SHIFT)) & SPI_RXDAT_RXDAT_MASK)
5654#define SPI_RXDAT_RXSSEL0_N_MASK (0x10000U)
5655#define SPI_RXDAT_RXSSEL0_N_SHIFT (16U)
5656/*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved
5657 * along with received data. The value will reflect the SSEL0 pin for both master and slave
5658 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
5659 * pin is configured by the related SPOL bit in CFG.
5660 */
5661#define SPI_RXDAT_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXSSEL0_N_SHIFT)) & SPI_RXDAT_RXSSEL0_N_MASK)
5662#define SPI_RXDAT_RXSSEL1_N_MASK (0x20000U)
5663#define SPI_RXDAT_RXSSEL1_N_SHIFT (17U)
5664/*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved
5665 * along with received data. The value will reflect the SSEL1 pin for both master and slave
5666 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
5667 * pin is configured by the related SPOL bit in CFG.
5668 */
5669#define SPI_RXDAT_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXSSEL1_N_SHIFT)) & SPI_RXDAT_RXSSEL1_N_MASK)
5670#define SPI_RXDAT_RXSSEL2_N_MASK (0x40000U)
5671#define SPI_RXDAT_RXSSEL2_N_SHIFT (18U)
5672/*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved
5673 * along with received data. The value will reflect the SSEL2 pin for both master and slave
5674 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
5675 * pin is configured by the related SPOL bit in CFG.
5676 */
5677#define SPI_RXDAT_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXSSEL2_N_SHIFT)) & SPI_RXDAT_RXSSEL2_N_MASK)
5678#define SPI_RXDAT_RXSSEL3_N_MASK (0x80000U)
5679#define SPI_RXDAT_RXSSEL3_N_SHIFT (19U)
5680/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved
5681 * along with received data. The value will reflect the SSEL3 pin for both master and slave
5682 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
5683 * pin is configured by the related SPOL bit in CFG.
5684 */
5685#define SPI_RXDAT_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXSSEL3_N_SHIFT)) & SPI_RXDAT_RXSSEL3_N_MASK)
5686#define SPI_RXDAT_SOT_MASK (0x100000U)
5687#define SPI_RXDAT_SOT_SHIFT (20U)
5688/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went
5689 * from deasserted to asserted (i.e., any previous transfer has ended). This information can be
5690 * used to identify the first piece of data in cases where the transfer length is greater than 16
5691 * bit.
5692 */
5693#define SPI_RXDAT_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_SOT_SHIFT)) & SPI_RXDAT_SOT_MASK)
5694/*! @} */
5695
5696/*! @name TXDATCTL - SPI Transmit Data with Control */
5697/*! @{ */
5698#define SPI_TXDATCTL_TXDAT_MASK (0xFFFFU)
5699#define SPI_TXDATCTL_TXDAT_SHIFT (0U)
5700/*! TXDAT - Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.
5701 */
5702#define SPI_TXDATCTL_TXDAT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_TXDAT_SHIFT)) & SPI_TXDATCTL_TXDAT_MASK)
5703#define SPI_TXDATCTL_TXSSEL0_N_MASK (0x10000U)
5704#define SPI_TXDATCTL_TXSSEL0_N_SHIFT (16U)
5705/*! TXSSEL0_N - Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the
5706 * pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in
5707 * the CFG register.
5708 * 0b0..SSEL0 asserted.
5709 * 0b1..SSEL0 not asserted.
5710 */
5711#define SPI_TXDATCTL_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_TXSSEL0_N_SHIFT)) & SPI_TXDATCTL_TXSSEL0_N_MASK)
5712#define SPI_TXDATCTL_TXSSEL1_N_MASK (0x20000U)
5713#define SPI_TXDATCTL_TXSSEL1_N_SHIFT (17U)
5714/*! TXSSEL1_N - Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the
5715 * pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in
5716 * the CFG register.
5717 * 0b0..SSEL1 asserted.
5718 * 0b1..SSEL1 not asserted.
5719 */
5720#define SPI_TXDATCTL_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_TXSSEL1_N_SHIFT)) & SPI_TXDATCTL_TXSSEL1_N_MASK)
5721#define SPI_TXDATCTL_TXSSEL2_N_MASK (0x40000U)
5722#define SPI_TXDATCTL_TXSSEL2_N_SHIFT (18U)
5723/*! TXSSEL2_N - Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the
5724 * pin is active LOW by default. Remark: The active state of the SSEL2 pin is configured by bits in
5725 * the CFG register.
5726 * 0b0..SSEL2 asserted.
5727 * 0b1..SSEL2 not asserted.
5728 */
5729#define SPI_TXDATCTL_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_TXSSEL2_N_SHIFT)) & SPI_TXDATCTL_TXSSEL2_N_MASK)
5730#define SPI_TXDATCTL_TXSSEL3_N_MASK (0x80000U)
5731#define SPI_TXDATCTL_TXSSEL3_N_SHIFT (19U)
5732/*! TXSSEL3_N - Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the
5733 * pin is active LOW by default. Remark: The active state of the SSEL3 pin is configured by bits in
5734 * the CFG register.
5735 * 0b0..SSEL3 asserted.
5736 * 0b1..SSEL3 not asserted.
5737 */
5738#define SPI_TXDATCTL_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_TXSSEL3_N_SHIFT)) & SPI_TXDATCTL_TXSSEL3_N_MASK)
5739#define SPI_TXDATCTL_EOT_MASK (0x100000U)
5740#define SPI_TXDATCTL_EOT_SHIFT (20U)
5741/*! EOT - End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain
5742 * so for at least the time specified by the Transfer_delay value in the DLY register.
5743 * 0b0..This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
5744 * 0b1..This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
5745 */
5746#define SPI_TXDATCTL_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_EOT_SHIFT)) & SPI_TXDATCTL_EOT_MASK)
5747#define SPI_TXDATCTL_EOF_MASK (0x200000U)
5748#define SPI_TXDATCTL_EOF_SHIFT (21U)
5749/*! EOF - End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value
5750 * in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY
5751 * value = 0. This control can be used as part of the support for frame lengths greater than 16
5752 * bits.
5753 * 0b0..This piece of data transmitted is not treated as the end of a frame.
5754 * 0b1..This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted.
5755 */
5756#define SPI_TXDATCTL_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_EOF_SHIFT)) & SPI_TXDATCTL_EOF_MASK)
5757#define SPI_TXDATCTL_RXIGNORE_MASK (0x400000U)
5758#define SPI_TXDATCTL_RXIGNORE_SHIFT (22U)
5759/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to
5760 * read unneeded data from the receiver.Setting this bit simplifies the transmit process and can
5761 * be used with the DMA.
5762 * 0b0..Received data must be read in order to allow transmission to progress. In slave mode, an overrun error
5763 * will occur if received data is not read before new data is received.
5764 * 0b1..Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
5765 */
5766#define SPI_TXDATCTL_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_RXIGNORE_SHIFT)) & SPI_TXDATCTL_RXIGNORE_MASK)
5767#define SPI_TXDATCTL_LEN_MASK (0xF000000U)
5768#define SPI_TXDATCTL_LEN_SHIFT (24U)
5769/*! LEN - Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths
5770 * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data
5771 * transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits
5772 * in length. ... 0xF = Data transfer is 16 bits in length.
5773 * 0b0000..
5774 * 0b0001..Data transfer is 1 bit in length.
5775 * 0b0010..Data transfer is 2 bit in length.
5776 * 0b0011..Data transfer is 3 bit in length.
5777 * 0b0100..Data transfer is 4 bit in length.
5778 * 0b0101..Data transfer is 5 bit in length.
5779 * 0b0110..Data transfer is 6 bit in length.
5780 * 0b0111..Data transfer is 7 bit in length.
5781 * 0b1000..Data transfer is 8 bit in length.
5782 * 0b1001..Data transfer is 9 bit in length.
5783 * 0b1010..Data transfer is 10 bit in length.
5784 * 0b1011..Data transfer is 11 bit in length.
5785 * 0b1100..Data transfer is 12 bit in length.
5786 * 0b1101..Data transfer is 13 bit in length.
5787 * 0b1110..Data transfer is 14 bit in length.
5788 * 0b1111..Data transfer is 15 bit in length.
5789 */
5790#define SPI_TXDATCTL_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_LEN_SHIFT)) & SPI_TXDATCTL_LEN_MASK)
5791/*! @} */
5792
5793/*! @name TXDAT - SPI Transmit Data. */
5794/*! @{ */
5795#define SPI_TXDAT_DATA_MASK (0xFFFFU)
5796#define SPI_TXDAT_DATA_SHIFT (0U)
5797/*! DATA - Transmit Data. This field provides from 4 to 16 bits of data to be transmitted.
5798 */
5799#define SPI_TXDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDAT_DATA_SHIFT)) & SPI_TXDAT_DATA_MASK)
5800/*! @} */
5801
5802/*! @name TXCTL - SPI Transmit Control */
5803/*! @{ */
5804#define SPI_TXCTL_TXSSEL0_N_MASK (0x10000U)
5805#define SPI_TXCTL_TXSSEL0_N_SHIFT (16U)
5806/*! TXSSEL0_N - Transmit Slave Select 0.
5807 */
5808#define SPI_TXCTL_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_TXSSEL0_N_SHIFT)) & SPI_TXCTL_TXSSEL0_N_MASK)
5809#define SPI_TXCTL_TXSSEL1_N_MASK (0x20000U)
5810#define SPI_TXCTL_TXSSEL1_N_SHIFT (17U)
5811/*! TXSSEL1_N - Transmit Slave Select 1.
5812 */
5813#define SPI_TXCTL_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_TXSSEL1_N_SHIFT)) & SPI_TXCTL_TXSSEL1_N_MASK)
5814#define SPI_TXCTL_TXSSEL2_N_MASK (0x40000U)
5815#define SPI_TXCTL_TXSSEL2_N_SHIFT (18U)
5816/*! TXSSEL2_N - Transmit Slave Select 2.
5817 */
5818#define SPI_TXCTL_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_TXSSEL2_N_SHIFT)) & SPI_TXCTL_TXSSEL2_N_MASK)
5819#define SPI_TXCTL_TXSSEL3_N_MASK (0x80000U)
5820#define SPI_TXCTL_TXSSEL3_N_SHIFT (19U)
5821/*! TXSSEL3_N - Transmit Slave Select 3.
5822 */
5823#define SPI_TXCTL_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_TXSSEL3_N_SHIFT)) & SPI_TXCTL_TXSSEL3_N_MASK)
5824#define SPI_TXCTL_EOT_MASK (0x100000U)
5825#define SPI_TXCTL_EOT_SHIFT (20U)
5826/*! EOT - End of Transfer.
5827 */
5828#define SPI_TXCTL_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_EOT_SHIFT)) & SPI_TXCTL_EOT_MASK)
5829#define SPI_TXCTL_EOF_MASK (0x200000U)
5830#define SPI_TXCTL_EOF_SHIFT (21U)
5831/*! EOF - End of Frame.
5832 */
5833#define SPI_TXCTL_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_EOF_SHIFT)) & SPI_TXCTL_EOF_MASK)
5834#define SPI_TXCTL_RXIGNORE_MASK (0x400000U)
5835#define SPI_TXCTL_RXIGNORE_SHIFT (22U)
5836/*! RXIGNORE - Receive Ignore.
5837 */
5838#define SPI_TXCTL_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_RXIGNORE_SHIFT)) & SPI_TXCTL_RXIGNORE_MASK)
5839#define SPI_TXCTL_LEN_MASK (0xF000000U)
5840#define SPI_TXCTL_LEN_SHIFT (24U)
5841/*! LEN - Data transfer Length.
5842 */
5843#define SPI_TXCTL_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_LEN_SHIFT)) & SPI_TXCTL_LEN_MASK)
5844/*! @} */
5845
5846/*! @name DIV - SPI clock Divider */
5847/*! @{ */
5848#define SPI_DIV_DIVVAL_MASK (0xFFFFU)
5849#define SPI_DIV_DIVVAL_SHIFT (0U)
5850/*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the
5851 * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1,
5852 * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results
5853 * in FCLK/65536.
5854 */
5855#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
5856/*! @} */
5857
5858/*! @name INTSTAT - SPI Interrupt Status */
5859/*! @{ */
5860#define SPI_INTSTAT_RXRDY_MASK (0x1U)
5861#define SPI_INTSTAT_RXRDY_SHIFT (0U)
5862/*! RXRDY - Receiver Ready flag.
5863 */
5864#define SPI_INTSTAT_RXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_RXRDY_SHIFT)) & SPI_INTSTAT_RXRDY_MASK)
5865#define SPI_INTSTAT_TXRDY_MASK (0x2U)
5866#define SPI_INTSTAT_TXRDY_SHIFT (1U)
5867/*! TXRDY - Transmitter Ready flag.
5868 */
5869#define SPI_INTSTAT_TXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_TXRDY_SHIFT)) & SPI_INTSTAT_TXRDY_MASK)
5870#define SPI_INTSTAT_RXOV_MASK (0x4U)
5871#define SPI_INTSTAT_RXOV_SHIFT (2U)
5872/*! RXOV - Receiver Overrun interrupt flag.
5873 */
5874#define SPI_INTSTAT_RXOV(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_RXOV_SHIFT)) & SPI_INTSTAT_RXOV_MASK)
5875#define SPI_INTSTAT_TXUR_MASK (0x8U)
5876#define SPI_INTSTAT_TXUR_SHIFT (3U)
5877/*! TXUR - Transmitter Underrun interrupt flag.
5878 */
5879#define SPI_INTSTAT_TXUR(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_TXUR_SHIFT)) & SPI_INTSTAT_TXUR_MASK)
5880#define SPI_INTSTAT_SSA_MASK (0x10U)
5881#define SPI_INTSTAT_SSA_SHIFT (4U)
5882/*! SSA - Slave Select Assert.
5883 */
5884#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
5885#define SPI_INTSTAT_SSD_MASK (0x20U)
5886#define SPI_INTSTAT_SSD_SHIFT (5U)
5887/*! SSD - Slave Select Deassert.
5888 */
5889#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
5890#define SPI_INTSTAT_MSTIDLE_MASK (0x100U)
5891#define SPI_INTSTAT_MSTIDLE_SHIFT (8U)
5892/*! MSTIDLE - Master Idle status flag.
5893 */
5894#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
5895/*! @} */
5896
5897
5898/*!
5899 * @}
5900 */ /* end of group SPI_Register_Masks */
5901
5902
5903/* SPI - Peripheral instance base addresses */
5904/** Peripheral SPI0 base address */
5905#define SPI0_BASE (0x40058000u)
5906/** Peripheral SPI0 base pointer */
5907#define SPI0 ((SPI_Type *)SPI0_BASE)
5908/** Peripheral SPI1 base address */
5909#define SPI1_BASE (0x4005C000u)
5910/** Peripheral SPI1 base pointer */
5911#define SPI1 ((SPI_Type *)SPI1_BASE)
5912/** Array initializer of SPI peripheral base addresses */
5913#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
5914/** Array initializer of SPI peripheral base pointers */
5915#define SPI_BASE_PTRS { SPI0, SPI1 }
5916/** Interrupt vectors for the SPI peripheral type */
5917#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
5918
5919/*!
5920 * @}
5921 */ /* end of group SPI_Peripheral_Access_Layer */
5922
5923
5924/* ----------------------------------------------------------------------------
5925 -- SWM Peripheral Access Layer
5926 ---------------------------------------------------------------------------- */
5927
5928/*!
5929 * @addtogroup SWM_Peripheral_Access_Layer SWM Peripheral Access Layer
5930 * @{
5931 */
5932
5933/** SWM - Register Layout Typedef */
5934typedef struct {
5935 union { /* offset: 0x0 */
5936 struct { /* offset: 0x0 */
5937 __IO uint32_t PINASSIGN0; /**< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS., offset: 0x0 */
5938 __IO uint32_t PINASSIGN1; /**< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_RTS., offset: 0x4 */
5939 __IO uint32_t PINASSIGN2; /**< Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK, U2_TXD, U2_RXD., offset: 0x8 */
5940 __IO uint32_t PINASSIGN3; /**< Pin assign register 3. Assign movable function U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK., offset: 0xC */
5941 __IO uint32_t PINASSIGN4; /**< Pin assign register 4. Assign movable functions SPI0_MOSI, SPI0_MISO, SPI0_SSEL0, SPI0_SSEL1., offset: 0x10 */
5942 __IO uint32_t PINASSIGN5; /**< Pin assign register 5. Assign movable functions SPI0_SSEL2, SPI0_SSEL3, SPI1_SCK, SPI1_MOSI, offset: 0x14 */
5943 __IO uint32_t PINASSIGN6; /**< Pin assign register 6. Assign movable functions SPI1_MISO, SPI1_SSEL0, SPI1_SSEL1, SCT0_IN0., offset: 0x18 */
5944 __IO uint32_t PINASSIGN7; /**< Pin assign register 7. Assign movable functions SCT_IN1, SCT_IN2, SCT_IN3, SCT_OUT0., offset: 0x1C */
5945 __IO uint32_t PINASSIGN8; /**< Pin assign register 8. Assign movable functions SCT_OUT1, SCT_OUT2, SCT_OUT3, SCT_OUT4., offset: 0x20 */
5946 __IO uint32_t PINASSIGN9; /**< Pin assign register 9. Assign movable functions SCT_OUT5, I2C1_SDA, I2C1_SCL, I2C2_SDA., offset: 0x24 */
5947 __IO uint32_t PINASSIGN10; /**< Pin assign register 10. Assign movable functions, I2C2_SCL, I2C3_SDA, I2C3_SCL, ADC_PINTRIG0., offset: 0x28 */
5948 __IO uint32_t PINASSIGN11; /**< Pin assign register 11. Assign movable functions ADC_PINTRIG1, ACMP_O, CLKOUT, GPIO_INT_BMAT, offset: 0x2C */
5949 } PINASSIGN;
5950 __IO uint32_t PINASSIGN_DATA[12]; /**< Pin assign register, array offset: 0x0, array step: 0x4 */
5951 };
5952 uint8_t RESERVED_0[400];
5953 __IO uint32_t PINENABLE0; /**< Pin enable register 0. Enables fixed-pin functions ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN, VDDCMP and so on., offset: 0x1C0 */
5954} SWM_Type;
5955
5956/* ----------------------------------------------------------------------------
5957 -- SWM Register Masks
5958 ---------------------------------------------------------------------------- */
5959
5960/*!
5961 * @addtogroup SWM_Register_Masks SWM Register Masks
5962 * @{
5963 */
5964
5965/*! @name PINASSIGN0 - Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS. */
5966/*! @{ */
5967#define SWM_PINASSIGN0_U0_TXD_O_MASK (0xFFU)
5968#define SWM_PINASSIGN0_U0_TXD_O_SHIFT (0U)
5969/*! U0_TXD_O - U0_TXD function assignment. The value is the pin number to be assigned to this
5970 * function. The following pins are available: PIO0_0(= 0) to PIO0_28 (= 0x1C).
5971 */
5972#define SWM_PINASSIGN0_U0_TXD_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_TXD_O_SHIFT)) & SWM_PINASSIGN0_U0_TXD_O_MASK)
5973#define SWM_PINASSIGN0_U0_RXD_I_MASK (0xFF00U)
5974#define SWM_PINASSIGN0_U0_RXD_I_SHIFT (8U)
5975/*! U0_RXD_I - U0_RXD function assignment. The value is the pin number to be assigned to this
5976 * function. The following pins are available: PIO0_0(= 0) to PIO0_28 (= 0x1C).
5977 */
5978#define SWM_PINASSIGN0_U0_RXD_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_RXD_I_SHIFT)) & SWM_PINASSIGN0_U0_RXD_I_MASK)
5979#define SWM_PINASSIGN0_U0_RTS_O_MASK (0xFF0000U)
5980#define SWM_PINASSIGN0_U0_RTS_O_SHIFT (16U)
5981/*! U0_RTS_O - U0_RTS function assignment. The value is the pin number to be assigned to this
5982 * function. The following pins are available: PIO0_0(= 0) to PIO0_28 (= 0x1C).
5983 */
5984#define SWM_PINASSIGN0_U0_RTS_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_RTS_O_SHIFT)) & SWM_PINASSIGN0_U0_RTS_O_MASK)
5985#define SWM_PINASSIGN0_U0_CTS_I_MASK (0xFF000000U)
5986#define SWM_PINASSIGN0_U0_CTS_I_SHIFT (24U)
5987/*! U0_CTS_I - U0_CTS function assignment. The value is the pin number to be assigned to this
5988 * function. The following pins are available: PIO0_0(= 0) to PIO0_28 (= 0x1C).
5989 */
5990#define SWM_PINASSIGN0_U0_CTS_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_CTS_I_SHIFT)) & SWM_PINASSIGN0_U0_CTS_I_MASK)
5991/*! @} */
5992
5993/*! @name PINASSIGN1 - Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_RTS. */
5994/*! @{ */
5995#define SWM_PINASSIGN1_U0_SCLK_IO_MASK (0xFFU)
5996#define SWM_PINASSIGN1_U0_SCLK_IO_SHIFT (0U)
5997/*! U0_SCLK_IO - U0_SCLK function assignment. The value is the pin number to be assigned to this
5998 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
5999 */
6000#define SWM_PINASSIGN1_U0_SCLK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U0_SCLK_IO_SHIFT)) & SWM_PINASSIGN1_U0_SCLK_IO_MASK)
6001#define SWM_PINASSIGN1_U1_TXD_O_MASK (0xFF00U)
6002#define SWM_PINASSIGN1_U1_TXD_O_SHIFT (8U)
6003/*! U1_TXD_O - U1_TXD function assignment. The value is the pin number to be assigned to this
6004 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6005 */
6006#define SWM_PINASSIGN1_U1_TXD_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U1_TXD_O_SHIFT)) & SWM_PINASSIGN1_U1_TXD_O_MASK)
6007#define SWM_PINASSIGN1_U1_RXD_I_MASK (0xFF0000U)
6008#define SWM_PINASSIGN1_U1_RXD_I_SHIFT (16U)
6009/*! U1_RXD_I - U1_RXD function assignment. The value is the pin number to be assigned to this
6010 * function. The following pins are available: PIO0_0(= 0) to PIO0_28 (= 0x1C).
6011 */
6012#define SWM_PINASSIGN1_U1_RXD_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U1_RXD_I_SHIFT)) & SWM_PINASSIGN1_U1_RXD_I_MASK)
6013#define SWM_PINASSIGN1_U1_RTS_O_MASK (0xFF000000U)
6014#define SWM_PINASSIGN1_U1_RTS_O_SHIFT (24U)
6015/*! U1_RTS_O - U1_RTS function assignment. The value is the pin number to be assigned to this
6016 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6017 */
6018#define SWM_PINASSIGN1_U1_RTS_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U1_RTS_O_SHIFT)) & SWM_PINASSIGN1_U1_RTS_O_MASK)
6019/*! @} */
6020
6021/*! @name PINASSIGN2 - Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK, U2_TXD, U2_RXD. */
6022/*! @{ */
6023#define SWM_PINASSIGN2_U1_CTS_I_MASK (0xFFU)
6024#define SWM_PINASSIGN2_U1_CTS_I_SHIFT (0U)
6025/*! U1_CTS_I - U1_CTS function assignment. The value is the pin number to be assigned to this
6026 * function. The following pins are available: PIO0_0(= 0) to PIO0_28 (= 0x1C).
6027 */
6028#define SWM_PINASSIGN2_U1_CTS_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_U1_CTS_I_SHIFT)) & SWM_PINASSIGN2_U1_CTS_I_MASK)
6029#define SWM_PINASSIGN2_U1_SCLK_IO_MASK (0xFF00U)
6030#define SWM_PINASSIGN2_U1_SCLK_IO_SHIFT (8U)
6031/*! U1_SCLK_IO - U1_SCLK function assignment. The value is the pin number to be assigned to this
6032 * function. The following pins are available: PIO0_0(= 0) to PIO0_28 (= 0x1C).
6033 */
6034#define SWM_PINASSIGN2_U1_SCLK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_U1_SCLK_IO_SHIFT)) & SWM_PINASSIGN2_U1_SCLK_IO_MASK)
6035#define SWM_PINASSIGN2_U2_TXD_O_MASK (0xFF0000U)
6036#define SWM_PINASSIGN2_U2_TXD_O_SHIFT (16U)
6037/*! U2_TXD_O - U2_TXD function assignment. The value is the pin number to be assigned to this
6038 * function. The following pins are available: PIO0_0(= 0) to PIO0_28 (= 0x1C).
6039 */
6040#define SWM_PINASSIGN2_U2_TXD_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_U2_TXD_O_SHIFT)) & SWM_PINASSIGN2_U2_TXD_O_MASK)
6041#define SWM_PINASSIGN2_U2_RXD_I_MASK (0xFF000000U)
6042#define SWM_PINASSIGN2_U2_RXD_I_SHIFT (24U)
6043/*! U2_RXD_I - U2_RXD function assignment. The value is the pin number to be assigned to this
6044 * function. The following pins are available: PIO0_0(= 0) to PIO0_28 (= 0x1C).
6045 */
6046#define SWM_PINASSIGN2_U2_RXD_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_U2_RXD_I_SHIFT)) & SWM_PINASSIGN2_U2_RXD_I_MASK)
6047/*! @} */
6048
6049/*! @name PINASSIGN3 - Pin assign register 3. Assign movable function U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK. */
6050/*! @{ */
6051#define SWM_PINASSIGN3_U2_RTS_O_MASK (0xFFU)
6052#define SWM_PINASSIGN3_U2_RTS_O_SHIFT (0U)
6053/*! U2_RTS_O - U2_RTS function assignment. The value is the pin number to be assigned to this
6054 * function. The following pins are available: PIO0_0(= 0) to PIO0_28 (= 0x1C).
6055 */
6056#define SWM_PINASSIGN3_U2_RTS_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_U2_RTS_O_SHIFT)) & SWM_PINASSIGN3_U2_RTS_O_MASK)
6057#define SWM_PINASSIGN3_U2_CTS_I_MASK (0xFF00U)
6058#define SWM_PINASSIGN3_U2_CTS_I_SHIFT (8U)
6059/*! U2_CTS_I - U2_CTS function assignment. The value is the pin number to be assigned to this
6060 * function. The following pins are available: PIO0_0(= 0) to PIO0_28 (= 0x1C).
6061 */
6062#define SWM_PINASSIGN3_U2_CTS_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_U2_CTS_I_SHIFT)) & SWM_PINASSIGN3_U2_CTS_I_MASK)
6063#define SWM_PINASSIGN3_U2_SCLK_IO_MASK (0xFF0000U)
6064#define SWM_PINASSIGN3_U2_SCLK_IO_SHIFT (16U)
6065/*! U2_SCLK_IO - U2_SCLK function assignment. The value is the pin number to be assigned to this
6066 * function. The following pins are available: PIO0_0(= 0) to PIO0_28 (= 0x1C).
6067 */
6068#define SWM_PINASSIGN3_U2_SCLK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_U2_SCLK_IO_SHIFT)) & SWM_PINASSIGN3_U2_SCLK_IO_MASK)
6069#define SWM_PINASSIGN3_SPI0_SCK_IO_MASK (0xFF000000U)
6070#define SWM_PINASSIGN3_SPI0_SCK_IO_SHIFT (24U)
6071/*! SPI0_SCK_IO - SPI0_SCK function assignment. The value is the pin number to be assigned to this
6072 * function. The following pins are available:PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6073 */
6074#define SWM_PINASSIGN3_SPI0_SCK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_SPI0_SCK_IO_SHIFT)) & SWM_PINASSIGN3_SPI0_SCK_IO_MASK)
6075/*! @} */
6076
6077/*! @name PINASSIGN4 - Pin assign register 4. Assign movable functions SPI0_MOSI, SPI0_MISO, SPI0_SSEL0, SPI0_SSEL1. */
6078/*! @{ */
6079#define SWM_PINASSIGN4_SPI0_MOSI_IO_MASK (0xFFU)
6080#define SWM_PINASSIGN4_SPI0_MOSI_IO_SHIFT (0U)
6081/*! SPI0_MOSI_IO - SPI0_MOSI function assignment. The value is the pin number to be assigned to this
6082 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6083 */
6084#define SWM_PINASSIGN4_SPI0_MOSI_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_SPI0_MOSI_IO_SHIFT)) & SWM_PINASSIGN4_SPI0_MOSI_IO_MASK)
6085#define SWM_PINASSIGN4_SPI0_MISO_IO_MASK (0xFF00U)
6086#define SWM_PINASSIGN4_SPI0_MISO_IO_SHIFT (8U)
6087/*! SPI0_MISO_IO - SPI0_MISIO function assignment. The value is the pin number to be assigned to
6088 * this function. The following pins are available:PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6089 */
6090#define SWM_PINASSIGN4_SPI0_MISO_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_SPI0_MISO_IO_SHIFT)) & SWM_PINASSIGN4_SPI0_MISO_IO_MASK)
6091#define SWM_PINASSIGN4_SPI0_SSEL0_IO_MASK (0xFF0000U)
6092#define SWM_PINASSIGN4_SPI0_SSEL0_IO_SHIFT (16U)
6093/*! SPI0_SSEL0_IO - SPI0_SSEL0 function assignment. The value is the pin number to be assigned to
6094 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6095 */
6096#define SWM_PINASSIGN4_SPI0_SSEL0_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_SPI0_SSEL0_IO_SHIFT)) & SWM_PINASSIGN4_SPI0_SSEL0_IO_MASK)
6097#define SWM_PINASSIGN4_SPI0_SSEL1_IO_MASK (0xFF000000U)
6098#define SWM_PINASSIGN4_SPI0_SSEL1_IO_SHIFT (24U)
6099/*! SPI0_SSEL1_IO - SPI0_SSEL1 function assignment. The value is the pin number to be assigned to
6100 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6101 */
6102#define SWM_PINASSIGN4_SPI0_SSEL1_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_SPI0_SSEL1_IO_SHIFT)) & SWM_PINASSIGN4_SPI0_SSEL1_IO_MASK)
6103/*! @} */
6104
6105/*! @name PINASSIGN5 - Pin assign register 5. Assign movable functions SPI0_SSEL2, SPI0_SSEL3, SPI1_SCK, SPI1_MOSI */
6106/*! @{ */
6107#define SWM_PINASSIGN5_SPI0_SSEL2_IO_MASK (0xFFU)
6108#define SWM_PINASSIGN5_SPI0_SSEL2_IO_SHIFT (0U)
6109/*! SPI0_SSEL2_IO - SPI0_SSEL2 function assignment. The value is the pin number to be assigned to
6110 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6111 */
6112#define SWM_PINASSIGN5_SPI0_SSEL2_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI0_SSEL2_IO_SHIFT)) & SWM_PINASSIGN5_SPI0_SSEL2_IO_MASK)
6113#define SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK (0xFF00U)
6114#define SWM_PINASSIGN5_SPI0_SSEL3_IO_SHIFT (8U)
6115/*! SPI0_SSEL3_IO - SPI0_SSEL3 function assignment. The value is the pin number to be assigned to
6116 * this function. The following pins are available:PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6117 */
6118#define SWM_PINASSIGN5_SPI0_SSEL3_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI0_SSEL3_IO_SHIFT)) & SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK)
6119#define SWM_PINASSIGN5_SPI1_SCK_IO_MASK (0xFF0000U)
6120#define SWM_PINASSIGN5_SPI1_SCK_IO_SHIFT (16U)
6121/*! SPI1_SCK_IO - SPI1_SCK function assignment. The value is the pin number to be assigned to this
6122 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6123 */
6124#define SWM_PINASSIGN5_SPI1_SCK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI1_SCK_IO_SHIFT)) & SWM_PINASSIGN5_SPI1_SCK_IO_MASK)
6125#define SWM_PINASSIGN5_SPI1_MOSI_IO_MASK (0xFF000000U)
6126#define SWM_PINASSIGN5_SPI1_MOSI_IO_SHIFT (24U)
6127/*! SPI1_MOSI_IO - SPI1_MOSI function assignment. The value is the pin number to be assigned to this
6128 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6129 */
6130#define SWM_PINASSIGN5_SPI1_MOSI_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI1_MOSI_IO_SHIFT)) & SWM_PINASSIGN5_SPI1_MOSI_IO_MASK)
6131/*! @} */
6132
6133/*! @name PINASSIGN6 - Pin assign register 6. Assign movable functions SPI1_MISO, SPI1_SSEL0, SPI1_SSEL1, SCT0_IN0. */
6134/*! @{ */
6135#define SWM_PINASSIGN6_SPI1_MISO_IO_MASK (0xFFU)
6136#define SWM_PINASSIGN6_SPI1_MISO_IO_SHIFT (0U)
6137/*! SPI1_MISO_IO - SPI1_MISO function assignment. The value is the pin number to be assigned to this
6138 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6139 */
6140#define SWM_PINASSIGN6_SPI1_MISO_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_SPI1_MISO_IO_SHIFT)) & SWM_PINASSIGN6_SPI1_MISO_IO_MASK)
6141#define SWM_PINASSIGN6_SPI1_SSEL0_IO_MASK (0xFF00U)
6142#define SWM_PINASSIGN6_SPI1_SSEL0_IO_SHIFT (8U)
6143/*! SPI1_SSEL0_IO - SPI1_SSEL0 function assignment. The value is the pin number to be assigned to
6144 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6145 */
6146#define SWM_PINASSIGN6_SPI1_SSEL0_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_SPI1_SSEL0_IO_SHIFT)) & SWM_PINASSIGN6_SPI1_SSEL0_IO_MASK)
6147#define SWM_PINASSIGN6_SPI1_SSEL1_IO_MASK (0xFF0000U)
6148#define SWM_PINASSIGN6_SPI1_SSEL1_IO_SHIFT (16U)
6149/*! SPI1_SSEL1_IO - SPI1_SSEL1 function assignment. The value is the pin number to be assigned to
6150 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6151 */
6152#define SWM_PINASSIGN6_SPI1_SSEL1_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_SPI1_SSEL1_IO_SHIFT)) & SWM_PINASSIGN6_SPI1_SSEL1_IO_MASK)
6153#define SWM_PINASSIGN6_SCT_PIN0_I_MASK (0xFF000000U)
6154#define SWM_PINASSIGN6_SCT_PIN0_I_SHIFT (24U)
6155/*! SCT_PIN0_I - SCT_PIN0 function assignment. The value is the pin number to be assigned to this
6156 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6157 */
6158#define SWM_PINASSIGN6_SCT_PIN0_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_SCT_PIN0_I_SHIFT)) & SWM_PINASSIGN6_SCT_PIN0_I_MASK)
6159/*! @} */
6160
6161/*! @name PINASSIGN7 - Pin assign register 7. Assign movable functions SCT_IN1, SCT_IN2, SCT_IN3, SCT_OUT0. */
6162/*! @{ */
6163#define SWM_PINASSIGN7_SCT_PIN1_I_MASK (0xFFU)
6164#define SWM_PINASSIGN7_SCT_PIN1_I_SHIFT (0U)
6165/*! SCT_PIN1_I - SCT_PIN1 function assignment. The value is the pin number to be assigned to this
6166 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6167 */
6168#define SWM_PINASSIGN7_SCT_PIN1_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN7_SCT_PIN1_I_SHIFT)) & SWM_PINASSIGN7_SCT_PIN1_I_MASK)
6169#define SWM_PINASSIGN7_SCT_PIN2_I_MASK (0xFF00U)
6170#define SWM_PINASSIGN7_SCT_PIN2_I_SHIFT (8U)
6171/*! SCT_PIN2_I - SCT_PIN2 function assignment. The value is the pin number to be assigned to this
6172 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6173 */
6174#define SWM_PINASSIGN7_SCT_PIN2_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN7_SCT_PIN2_I_SHIFT)) & SWM_PINASSIGN7_SCT_PIN2_I_MASK)
6175#define SWM_PINASSIGN7_SCT_PIN3_I_MASK (0xFF0000U)
6176#define SWM_PINASSIGN7_SCT_PIN3_I_SHIFT (16U)
6177/*! SCT_PIN3_I - SCT_PIN3 function assignment. The value is the pin number to be assigned to this
6178 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6179 */
6180#define SWM_PINASSIGN7_SCT_PIN3_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN7_SCT_PIN3_I_SHIFT)) & SWM_PINASSIGN7_SCT_PIN3_I_MASK)
6181#define SWM_PINASSIGN7_SCT_OUT0_O_MASK (0xFF000000U)
6182#define SWM_PINASSIGN7_SCT_OUT0_O_SHIFT (24U)
6183/*! SCT_OUT0_O - SCT_OUT0 function assignment. The value is the pin number to be assigned to this
6184 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6185 */
6186#define SWM_PINASSIGN7_SCT_OUT0_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN7_SCT_OUT0_O_SHIFT)) & SWM_PINASSIGN7_SCT_OUT0_O_MASK)
6187/*! @} */
6188
6189/*! @name PINASSIGN8 - Pin assign register 8. Assign movable functions SCT_OUT1, SCT_OUT2, SCT_OUT3, SCT_OUT4. */
6190/*! @{ */
6191#define SWM_PINASSIGN8_SCT_OUT1_O_MASK (0xFFU)
6192#define SWM_PINASSIGN8_SCT_OUT1_O_SHIFT (0U)
6193/*! SCT_OUT1_O - SCT_OUT1 function assignment. The value is the pin number to be assigned to this
6194 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6195 */
6196#define SWM_PINASSIGN8_SCT_OUT1_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN8_SCT_OUT1_O_SHIFT)) & SWM_PINASSIGN8_SCT_OUT1_O_MASK)
6197#define SWM_PINASSIGN8_SCT_OUT2_O_MASK (0xFF00U)
6198#define SWM_PINASSIGN8_SCT_OUT2_O_SHIFT (8U)
6199/*! SCT_OUT2_O - SCT_OUT2 function assignment. The value is the pin number to be assigned to this
6200 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6201 */
6202#define SWM_PINASSIGN8_SCT_OUT2_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN8_SCT_OUT2_O_SHIFT)) & SWM_PINASSIGN8_SCT_OUT2_O_MASK)
6203#define SWM_PINASSIGN8_SCT_OUT3_O_MASK (0xFF0000U)
6204#define SWM_PINASSIGN8_SCT_OUT3_O_SHIFT (16U)
6205/*! SCT_OUT3_O - SCT_OUT3 function assignment. The value is the pin number to be assigned to this
6206 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6207 */
6208#define SWM_PINASSIGN8_SCT_OUT3_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN8_SCT_OUT3_O_SHIFT)) & SWM_PINASSIGN8_SCT_OUT3_O_MASK)
6209#define SWM_PINASSIGN8_SCT_OUT4_O_MASK (0xFF000000U)
6210#define SWM_PINASSIGN8_SCT_OUT4_O_SHIFT (24U)
6211/*! SCT_OUT4_O - SCT_OUT4 function assignment. The value is the pin number to be assigned to this
6212 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6213 */
6214#define SWM_PINASSIGN8_SCT_OUT4_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN8_SCT_OUT4_O_SHIFT)) & SWM_PINASSIGN8_SCT_OUT4_O_MASK)
6215/*! @} */
6216
6217/*! @name PINASSIGN9 - Pin assign register 9. Assign movable functions SCT_OUT5, I2C1_SDA, I2C1_SCL, I2C2_SDA. */
6218/*! @{ */
6219#define SWM_PINASSIGN9_SCT_OUT5_O_MASK (0xFFU)
6220#define SWM_PINASSIGN9_SCT_OUT5_O_SHIFT (0U)
6221/*! SCT_OUT5_O - SCT_OUT5 function assignment. The value is the pin number to be assigned to this
6222 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6223 */
6224#define SWM_PINASSIGN9_SCT_OUT5_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN9_SCT_OUT5_O_SHIFT)) & SWM_PINASSIGN9_SCT_OUT5_O_MASK)
6225#define SWM_PINASSIGN9_I2C1_SDA_IO_MASK (0xFF00U)
6226#define SWM_PINASSIGN9_I2C1_SDA_IO_SHIFT (8U)
6227/*! I2C1_SDA_IO - I2C1_SDA function assignment. The value is the pin number to be assigned to this
6228 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6229 */
6230#define SWM_PINASSIGN9_I2C1_SDA_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN9_I2C1_SDA_IO_SHIFT)) & SWM_PINASSIGN9_I2C1_SDA_IO_MASK)
6231#define SWM_PINASSIGN9_I2C1_SCL_IO_MASK (0xFF0000U)
6232#define SWM_PINASSIGN9_I2C1_SCL_IO_SHIFT (16U)
6233/*! I2C1_SCL_IO - I2C1_SCL function assignment. The value is the pin number to be assigned to this
6234 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6235 */
6236#define SWM_PINASSIGN9_I2C1_SCL_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN9_I2C1_SCL_IO_SHIFT)) & SWM_PINASSIGN9_I2C1_SCL_IO_MASK)
6237#define SWM_PINASSIGN9_I2C2_SDA_IO_MASK (0xFF000000U)
6238#define SWM_PINASSIGN9_I2C2_SDA_IO_SHIFT (24U)
6239/*! I2C2_SDA_IO - I2C1_SDA function assignment. The value is the pin number to be assigned to this
6240 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6241 */
6242#define SWM_PINASSIGN9_I2C2_SDA_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN9_I2C2_SDA_IO_SHIFT)) & SWM_PINASSIGN9_I2C2_SDA_IO_MASK)
6243/*! @} */
6244
6245/*! @name PINASSIGN10 - Pin assign register 10. Assign movable functions, I2C2_SCL, I2C3_SDA, I2C3_SCL, ADC_PINTRIG0. */
6246/*! @{ */
6247#define SWM_PINASSIGN10_I2C2_SCL_IO_MASK (0xFFU)
6248#define SWM_PINASSIGN10_I2C2_SCL_IO_SHIFT (0U)
6249/*! I2C2_SCL_IO - I2C1_SCL function assignment. The value is the pin number to be assigned to this
6250 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6251 */
6252#define SWM_PINASSIGN10_I2C2_SCL_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN10_I2C2_SCL_IO_SHIFT)) & SWM_PINASSIGN10_I2C2_SCL_IO_MASK)
6253#define SWM_PINASSIGN10_I2C3_SDA_IO_MASK (0xFF00U)
6254#define SWM_PINASSIGN10_I2C3_SDA_IO_SHIFT (8U)
6255/*! I2C3_SDA_IO - I2C3_SDA function assignment. The value is the pin number to be assigned to this
6256 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6257 */
6258#define SWM_PINASSIGN10_I2C3_SDA_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN10_I2C3_SDA_IO_SHIFT)) & SWM_PINASSIGN10_I2C3_SDA_IO_MASK)
6259#define SWM_PINASSIGN10_I2C3_SCL_IO_MASK (0xFF0000U)
6260#define SWM_PINASSIGN10_I2C3_SCL_IO_SHIFT (16U)
6261/*! I2C3_SCL_IO - I2C3_SCL function assignment. The value is the pin number to be assigned to this
6262 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6263 */
6264#define SWM_PINASSIGN10_I2C3_SCL_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN10_I2C3_SCL_IO_SHIFT)) & SWM_PINASSIGN10_I2C3_SCL_IO_MASK)
6265#define SWM_PINASSIGN10_ADC_PINTRIG0_I_MASK (0xFF000000U)
6266#define SWM_PINASSIGN10_ADC_PINTRIG0_I_SHIFT (24U)
6267/*! ADC_PINTRIG0_I - ADC_PINTRIG0 function assignment. The value is the pin number to be assigned to
6268 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6269 */
6270#define SWM_PINASSIGN10_ADC_PINTRIG0_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN10_ADC_PINTRIG0_I_SHIFT)) & SWM_PINASSIGN10_ADC_PINTRIG0_I_MASK)
6271/*! @} */
6272
6273/*! @name PINASSIGN11 - Pin assign register 11. Assign movable functions ADC_PINTRIG1, ACMP_O, CLKOUT, GPIO_INT_BMAT */
6274/*! @{ */
6275#define SWM_PINASSIGN11_ADC_PINTRIG1_I_MASK (0xFFU)
6276#define SWM_PINASSIGN11_ADC_PINTRIG1_I_SHIFT (0U)
6277/*! ADC_PINTRIG1_I - ADC_PINTRIG1 function assignment. The value is the pin number to be assigned to
6278 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6279 */
6280#define SWM_PINASSIGN11_ADC_PINTRIG1_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN11_ADC_PINTRIG1_I_SHIFT)) & SWM_PINASSIGN11_ADC_PINTRIG1_I_MASK)
6281#define SWM_PINASSIGN11_ACMP_O_O_MASK (0xFF00U)
6282#define SWM_PINASSIGN11_ACMP_O_O_SHIFT (8U)
6283/*! ACMP_O_O - ACMP_O function assignment. The value is the pin number to be assigned to this
6284 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6285 */
6286#define SWM_PINASSIGN11_ACMP_O_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN11_ACMP_O_O_SHIFT)) & SWM_PINASSIGN11_ACMP_O_O_MASK)
6287#define SWM_PINASSIGN11_CLKOUT_O_MASK (0xFF0000U)
6288#define SWM_PINASSIGN11_CLKOUT_O_SHIFT (16U)
6289/*! CLKOUT_O - CLKOUT function assignment. The value is the pin number to be assigned to this
6290 * function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6291 */
6292#define SWM_PINASSIGN11_CLKOUT_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN11_CLKOUT_O_SHIFT)) & SWM_PINASSIGN11_CLKOUT_O_MASK)
6293#define SWM_PINASSIGN11_GPIO_INT_BMAT_O_MASK (0xFF000000U)
6294#define SWM_PINASSIGN11_GPIO_INT_BMAT_O_SHIFT (24U)
6295/*! GPIO_INT_BMAT_O - GPIO_INT_BMAT function assignment. The value is the pin number to be assigned
6296 * to this function. The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C).
6297 */
6298#define SWM_PINASSIGN11_GPIO_INT_BMAT_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN11_GPIO_INT_BMAT_O_SHIFT)) & SWM_PINASSIGN11_GPIO_INT_BMAT_O_MASK)
6299/*! @} */
6300
6301/*! @name PINASSIGN_DATA - Pin assign register */
6302/*! @{ */
6303#define SWM_PINASSIGN_DATA_T0_MAT3_MASK (0xFFU)
6304#define SWM_PINASSIGN_DATA_T0_MAT3_SHIFT (0U)
6305/*! T0_MAT3 - T0_MAT3 function assignment. The value is the pin number to be assigned to this
6306 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20)
6307 * to PIO1_21(=0x35).
6308 */
6309#define SWM_PINASSIGN_DATA_T0_MAT3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_T0_MAT3_SHIFT)) & SWM_PINASSIGN_DATA_T0_MAT3_MASK)
6310#define SWM_PINASSIGN_DATA_T0_CAP0_MASK (0xFF00U)
6311#define SWM_PINASSIGN_DATA_T0_CAP0_SHIFT (8U)
6312/*! T0_CAP0 - T0_CAP0 function assignment. The value is the pin number to be assigned to this
6313 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20)
6314 * to PIO1_21(=0x35).
6315 */
6316#define SWM_PINASSIGN_DATA_T0_CAP0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_T0_CAP0_SHIFT)) & SWM_PINASSIGN_DATA_T0_CAP0_MASK)
6317#define SWM_PINASSIGN_DATA_T0_CAP1_MASK (0xFF0000U)
6318#define SWM_PINASSIGN_DATA_T0_CAP1_SHIFT (16U)
6319/*! T0_CAP1 - T0_CAP1 function assignment. The value is the pin number to be assigned to this
6320 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20)
6321 * to PIO1_21(=0x35).
6322 */
6323#define SWM_PINASSIGN_DATA_T0_CAP1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_T0_CAP1_SHIFT)) & SWM_PINASSIGN_DATA_T0_CAP1_MASK)
6324#define SWM_PINASSIGN_DATA_T0_CAP2_MASK (0xFF000000U)
6325#define SWM_PINASSIGN_DATA_T0_CAP2_SHIFT (24U)
6326/*! T0_CAP2 - T0_CAP2 function assignment. The value is the pin number to be assigned to this
6327 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20)
6328 * to PIO1_21(=0x35).
6329 */
6330#define SWM_PINASSIGN_DATA_T0_CAP2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_T0_CAP2_SHIFT)) & SWM_PINASSIGN_DATA_T0_CAP2_MASK)
6331/*! @} */
6332
6333/* The count of SWM_PINASSIGN_DATA */
6334#define SWM_PINASSIGN_DATA_COUNT (12U)
6335
6336/*! @name PINENABLE0 - Pin enable register 0. Enables fixed-pin functions ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN, VDDCMP and so on. */
6337/*! @{ */
6338#define SWM_PINENABLE0_ACMP_I1_MASK (0x1U)
6339#define SWM_PINENABLE0_ACMP_I1_SHIFT (0U)
6340/*! ACMP_I1 - ACMP_I1 function select.
6341 * 0b0..ACMP_I1 enabled on pin PIO0_00.
6342 * 0b1..ACMP_I1 disabled.
6343 */
6344#define SWM_PINENABLE0_ACMP_I1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I1_SHIFT)) & SWM_PINENABLE0_ACMP_I1_MASK)
6345#define SWM_PINENABLE0_ACMP_I2_MASK (0x2U)
6346#define SWM_PINENABLE0_ACMP_I2_SHIFT (1U)
6347/*! ACMP_I2 - ACMP_I2 function select.
6348 * 0b0..ACMP_I2 enabled on pin PIO0_1.
6349 * 0b1..ACMP_I2 disabled.
6350 */
6351#define SWM_PINENABLE0_ACMP_I2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I2_SHIFT)) & SWM_PINENABLE0_ACMP_I2_MASK)
6352#define SWM_PINENABLE0_ACMP_I3_MASK (0x4U)
6353#define SWM_PINENABLE0_ACMP_I3_SHIFT (2U)
6354/*! ACMP_I3 - ACMP_I3 function select.
6355 * 0b0..ACMP_I3 enabled on pin PIO0_14.
6356 * 0b1..ACMP_I3 disabled.
6357 */
6358#define SWM_PINENABLE0_ACMP_I3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I3_SHIFT)) & SWM_PINENABLE0_ACMP_I3_MASK)
6359#define SWM_PINENABLE0_ACMP_I4_MASK (0x8U)
6360#define SWM_PINENABLE0_ACMP_I4_SHIFT (3U)
6361/*! ACMP_I4 - ACMP_I4 function select.
6362 * 0b0..ACMP_I4 enabled on pin PIO0_23.
6363 * 0b1..ACMP_I4 disabled.
6364 */
6365#define SWM_PINENABLE0_ACMP_I4(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I4_SHIFT)) & SWM_PINENABLE0_ACMP_I4_MASK)
6366#define SWM_PINENABLE0_SWCLK_MASK (0x10U)
6367#define SWM_PINENABLE0_SWCLK_SHIFT (4U)
6368/*! SWCLK - SWCLK function select.
6369 * 0b0..SWCLK enabled on pin PIO0_3.
6370 * 0b1..SWCLK disabled.
6371 */
6372#define SWM_PINENABLE0_SWCLK(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_SWCLK_SHIFT)) & SWM_PINENABLE0_SWCLK_MASK)
6373#define SWM_PINENABLE0_SWDIO_MASK (0x20U)
6374#define SWM_PINENABLE0_SWDIO_SHIFT (5U)
6375/*! SWDIO - SWDIO function select.
6376 * 0b0..SWDIO enabled on pin PIO0_2.
6377 * 0b1..SWDIO disabled.
6378 */
6379#define SWM_PINENABLE0_SWDIO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_SWDIO_SHIFT)) & SWM_PINENABLE0_SWDIO_MASK)
6380#define SWM_PINENABLE0_XTALIN_MASK (0x40U)
6381#define SWM_PINENABLE0_XTALIN_SHIFT (6U)
6382/*! XTALIN - XTALIN function select.
6383 * 0b0..XTALIN enabled on pin PIO0_8.
6384 * 0b1..XTALIN disabled.
6385 */
6386#define SWM_PINENABLE0_XTALIN(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_XTALIN_SHIFT)) & SWM_PINENABLE0_XTALIN_MASK)
6387#define SWM_PINENABLE0_XTALOUT_MASK (0x80U)
6388#define SWM_PINENABLE0_XTALOUT_SHIFT (7U)
6389/*! XTALOUT - XTALOUT function select.
6390 * 0b0..XTALOUT enabled on pin PIO0_9.
6391 * 0b1..XTALOUT disabled.
6392 */
6393#define SWM_PINENABLE0_XTALOUT(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_XTALOUT_SHIFT)) & SWM_PINENABLE0_XTALOUT_MASK)
6394#define SWM_PINENABLE0_RESETN_MASK (0x100U)
6395#define SWM_PINENABLE0_RESETN_SHIFT (8U)
6396/*! RESETN - RESETN function select.
6397 * 0b0..RESETN enabled on pin PIO0_5.
6398 * 0b1..RESETN disabled.
6399 */
6400#define SWM_PINENABLE0_RESETN(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_RESETN_SHIFT)) & SWM_PINENABLE0_RESETN_MASK)
6401#define SWM_PINENABLE0_CLKIN_MASK (0x200U)
6402#define SWM_PINENABLE0_CLKIN_SHIFT (9U)
6403/*! CLKIN - CLKIN function select.
6404 * 0b0..CLKIN enabled on pin PIO0_1.
6405 * 0b1..CLKIN disabled.
6406 */
6407#define SWM_PINENABLE0_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_CLKIN_SHIFT)) & SWM_PINENABLE0_CLKIN_MASK)
6408#define SWM_PINENABLE0_VDDCMP_MASK (0x400U)
6409#define SWM_PINENABLE0_VDDCMP_SHIFT (10U)
6410/*! VDDCMP - VDDCMP function select.
6411 * 0b0..VDDCMP enabled on pin PIO0_6.
6412 * 0b1..VDDCMP disabled.
6413 */
6414#define SWM_PINENABLE0_VDDCMP(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_VDDCMP_SHIFT)) & SWM_PINENABLE0_VDDCMP_MASK)
6415#define SWM_PINENABLE0_I2C0_SDA_MASK (0x800U)
6416#define SWM_PINENABLE0_I2C0_SDA_SHIFT (11U)
6417/*! I2C0_SDA - I2C0_SDA function select.
6418 * 0b0..I2C0_SDA enabled on pin PIO0_11.
6419 * 0b1..I2C0_SDA disabled.
6420 */
6421#define SWM_PINENABLE0_I2C0_SDA(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_I2C0_SDA_SHIFT)) & SWM_PINENABLE0_I2C0_SDA_MASK)
6422#define SWM_PINENABLE0_I2C0_SCL_MASK (0x1000U)
6423#define SWM_PINENABLE0_I2C0_SCL_SHIFT (12U)
6424/*! I2C0_SCL - I2C0_SCL function select.
6425 * 0b0..I2C0_SCL enabled on pin PIO0_10.
6426 * 0b1..I2C0_SCL disabled.
6427 */
6428#define SWM_PINENABLE0_I2C0_SCL(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_I2C0_SCL_SHIFT)) & SWM_PINENABLE0_I2C0_SCL_MASK)
6429#define SWM_PINENABLE0_ADC_0_MASK (0x2000U)
6430#define SWM_PINENABLE0_ADC_0_SHIFT (13U)
6431/*! ADC_0 - ADC_0 function select.
6432 * 0b0..ADC_0 enabled on pin PIO0_7.
6433 * 0b1..ADC_0 disabled.
6434 */
6435#define SWM_PINENABLE0_ADC_0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_0_SHIFT)) & SWM_PINENABLE0_ADC_0_MASK)
6436#define SWM_PINENABLE0_ADC_1_MASK (0x4000U)
6437#define SWM_PINENABLE0_ADC_1_SHIFT (14U)
6438/*! ADC_1 - ADC_1 function select.
6439 * 0b0..ADC_1 enabled on pin PIO0_6.
6440 * 0b1..ADC_1 disabled.
6441 */
6442#define SWM_PINENABLE0_ADC_1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_1_SHIFT)) & SWM_PINENABLE0_ADC_1_MASK)
6443#define SWM_PINENABLE0_ADC_2_MASK (0x8000U)
6444#define SWM_PINENABLE0_ADC_2_SHIFT (15U)
6445/*! ADC_2 - ADC_2 function select.
6446 * 0b0..ADC_2 enabled on pin PIO0_14.
6447 * 0b1..ADC_2 disabled.
6448 */
6449#define SWM_PINENABLE0_ADC_2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_2_SHIFT)) & SWM_PINENABLE0_ADC_2_MASK)
6450#define SWM_PINENABLE0_ADC_3_MASK (0x10000U)
6451#define SWM_PINENABLE0_ADC_3_SHIFT (16U)
6452/*! ADC_3 - ADC_3 function select.
6453 * 0b0..ADC_3 enabled on pin PIO0_23.
6454 * 0b1..ADC_3 disabled.
6455 */
6456#define SWM_PINENABLE0_ADC_3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_3_SHIFT)) & SWM_PINENABLE0_ADC_3_MASK)
6457#define SWM_PINENABLE0_ADC_4_MASK (0x20000U)
6458#define SWM_PINENABLE0_ADC_4_SHIFT (17U)
6459/*! ADC_4 - ADC_4 function select.
6460 * 0b0..ADC_4 enabled on pin PIO0_22.
6461 * 0b1..ADC_4 disabled.
6462 */
6463#define SWM_PINENABLE0_ADC_4(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_4_SHIFT)) & SWM_PINENABLE0_ADC_4_MASK)
6464#define SWM_PINENABLE0_ADC_5_MASK (0x40000U)
6465#define SWM_PINENABLE0_ADC_5_SHIFT (18U)
6466/*! ADC_5 - ADC_5 function select.
6467 * 0b0..ADC_5 enabled on pin PIO0_21.
6468 * 0b1..ADC_5 disabled.
6469 */
6470#define SWM_PINENABLE0_ADC_5(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_5_SHIFT)) & SWM_PINENABLE0_ADC_5_MASK)
6471#define SWM_PINENABLE0_ADC_6_MASK (0x80000U)
6472#define SWM_PINENABLE0_ADC_6_SHIFT (19U)
6473/*! ADC_6 - ADC_6 function select.
6474 * 0b0..ADC_6 enabled on pin PIO0_20.
6475 * 0b1..ADC_6 disabled.
6476 */
6477#define SWM_PINENABLE0_ADC_6(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_6_SHIFT)) & SWM_PINENABLE0_ADC_6_MASK)
6478#define SWM_PINENABLE0_ADC_7_MASK (0x100000U)
6479#define SWM_PINENABLE0_ADC_7_SHIFT (20U)
6480/*! ADC_7 - ADC_7 function select.
6481 * 0b0..ADC_7 enabled on pin PIO0_19.
6482 * 0b1..ADC_7 disabled.
6483 */
6484#define SWM_PINENABLE0_ADC_7(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_7_SHIFT)) & SWM_PINENABLE0_ADC_7_MASK)
6485#define SWM_PINENABLE0_ADC_8_MASK (0x200000U)
6486#define SWM_PINENABLE0_ADC_8_SHIFT (21U)
6487/*! ADC_8 - ADC_8 function select.
6488 * 0b0..ADC_8 enabled on pin PIO0_18.
6489 * 0b1..ADC_8 disabled.
6490 */
6491#define SWM_PINENABLE0_ADC_8(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_8_SHIFT)) & SWM_PINENABLE0_ADC_8_MASK)
6492#define SWM_PINENABLE0_ADC_9_MASK (0x400000U)
6493#define SWM_PINENABLE0_ADC_9_SHIFT (22U)
6494/*! ADC_9 - ADC_9 function select.
6495 * 0b0..ADC_9 enabled on pin PIO0_17.
6496 * 0b1..ADC_9 disabled.
6497 */
6498#define SWM_PINENABLE0_ADC_9(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_9_SHIFT)) & SWM_PINENABLE0_ADC_9_MASK)
6499#define SWM_PINENABLE0_ADC_10_MASK (0x800000U)
6500#define SWM_PINENABLE0_ADC_10_SHIFT (23U)
6501/*! ADC_10 - ADC_10 function select.
6502 * 0b0..ADC_10 enabled on pin PIO0_13.
6503 * 0b1..ADC_10 disabled.
6504 */
6505#define SWM_PINENABLE0_ADC_10(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_10_SHIFT)) & SWM_PINENABLE0_ADC_10_MASK)
6506#define SWM_PINENABLE0_ADC_11_MASK (0x1000000U)
6507#define SWM_PINENABLE0_ADC_11_SHIFT (24U)
6508/*! ADC_11 - ADC_11 function select.
6509 * 0b0..ADC_11 enabled on pin PIO0_4.
6510 * 0b1..ADC_11 disabled.
6511 */
6512#define SWM_PINENABLE0_ADC_11(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_11_SHIFT)) & SWM_PINENABLE0_ADC_11_MASK)
6513/*! @} */
6514
6515
6516/*!
6517 * @}
6518 */ /* end of group SWM_Register_Masks */
6519
6520
6521/* SWM - Peripheral instance base addresses */
6522/** Peripheral SWM0 base address */
6523#define SWM0_BASE (0x4000C000u)
6524/** Peripheral SWM0 base pointer */
6525#define SWM0 ((SWM_Type *)SWM0_BASE)
6526/** Array initializer of SWM peripheral base addresses */
6527#define SWM_BASE_ADDRS { SWM0_BASE }
6528/** Array initializer of SWM peripheral base pointers */
6529#define SWM_BASE_PTRS { SWM0 }
6530
6531/*!
6532 * @}
6533 */ /* end of group SWM_Peripheral_Access_Layer */
6534
6535
6536/* ----------------------------------------------------------------------------
6537 -- SYSCON Peripheral Access Layer
6538 ---------------------------------------------------------------------------- */
6539
6540/*!
6541 * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
6542 * @{
6543 */
6544
6545/** SYSCON - Register Layout Typedef */
6546typedef struct {
6547 __IO uint32_t SYSMEMREMAP; /**< System Remap register, offset: 0x0 */
6548 __IO uint32_t PRESETCTRL; /**< Peripheral reset control register, offset: 0x4 */
6549 __IO uint32_t SYSPLLCTRL; /**< PLL control, offset: 0x8 */
6550 __I uint32_t SYSPLLSTAT; /**< PLL status, offset: 0xC */
6551 uint8_t RESERVED_0[16];
6552 __IO uint32_t SYSOSCCTRL; /**< system oscillator control, offset: 0x20 */
6553 __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x24 */
6554 __IO uint32_t IRCCTRL; /**< IRC control, offset: 0x28 */
6555 uint8_t RESERVED_1[4];
6556 __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x30 */
6557 uint8_t RESERVED_2[12];
6558 __IO uint32_t SYSPLLCLKSEL; /**< System PLL clock source select register, offset: 0x40 */
6559 __IO uint32_t SYSPLLCLKUEN; /**< System PLL clock source update enable register, offset: 0x44 */
6560 uint8_t RESERVED_3[40];
6561 __IO uint32_t MAINCLKSEL; /**< Main clock source select, offset: 0x70 */
6562 __IO uint32_t MAINCLKUEN; /**< Main clock source update enable, offset: 0x74 */
6563 __IO uint32_t SYSAHBCLKDIV; /**< System clock divider, offset: 0x78 */
6564 uint8_t RESERVED_4[4];
6565 __IO uint32_t SYSAHBCLKCTRL; /**< System clock control, offset: 0x80 */
6566 uint8_t RESERVED_5[16];
6567 __IO uint32_t UARTCLKDIV; /**< USART clock divider, offset: 0x94 */
6568 uint8_t RESERVED_6[72];
6569 __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0xE0 */
6570 __IO uint32_t CLKOUTUEN; /**< CLKOUT clock source update enable, offset: 0xE4 */
6571 __IO uint32_t CLKOUTDIV; /**< PLL control, offset: 0xE8 */
6572 uint8_t RESERVED_7[4];
6573 __IO uint32_t UARTFRGDIV; /**< USART1 to USART4 common fractional generator divider value, offset: 0xF0 */
6574 __IO uint32_t UARTFRGMULT; /**< USART common fractional generator divider value, offset: 0xF4 */
6575 uint8_t RESERVED_8[4];
6576 __IO uint32_t EXTTRACECMD; /**< External trace buffer command register, offset: 0xFC */
6577 __I uint32_t PIOPORCAP0; /**< POR captured PIO status 0, offset: 0x100 */
6578 uint8_t RESERVED_9[48];
6579 __IO uint32_t IOCONCLKDIV6; /**< Peripheral clock 6 to the IOCON block for programmable glitch filter, offset: 0x134 */
6580 __IO uint32_t IOCONCLKDIV5; /**< Peripheral clock 6 to the IOCON block for programmable glitch filter, offset: 0x138 */
6581 __IO uint32_t IOCONCLKDIV4; /**< Peripheral clock 4 to the IOCON block for programmable glitch filter, offset: 0x13C */
6582 __IO uint32_t IOCONCLKDIV3; /**< Peripheral clock 3 to the IOCON block for programmable glitch filter, offset: 0x140 */
6583 __IO uint32_t IOCONCLKDIV2; /**< Peripheral clock 2 to the IOCON block for programmable glitch filter, offset: 0x144 */
6584 __IO uint32_t IOCONCLKDIV1; /**< Peripheral clock 1 to the IOCON block for programmable glitch filter, offset: 0x148 */
6585 __IO uint32_t IOCONCLKDIV0; /**< Peripheral clock 0 to the IOCON block for programmable glitch filter, offset: 0x14C */
6586 __IO uint32_t BODCTRL; /**< BOD control register, offset: 0x150 */
6587 __IO uint32_t SYSTCKCAL; /**< System tick timer calibration register, offset: 0x154 */
6588 uint8_t RESERVED_10[24];
6589 __IO uint32_t IRQLATENCY; /**< IRQ latency register, offset: 0x170 */
6590 __IO uint32_t NMISRC; /**< NMI source selection register, offset: 0x174 */
6591 __IO uint32_t PINTSEL[8]; /**< Pin interrupt select registers N, array offset: 0x178, array step: 0x4 */
6592 uint8_t RESERVED_11[108];
6593 __IO uint32_t STARTERP0; /**< Start logic 0 pin wake-up enable register 0, offset: 0x204 */
6594 uint8_t RESERVED_12[12];
6595 __IO uint32_t STARTERP1; /**< Start logic 1 interrupt wake-up enable register, offset: 0x214 */
6596 uint8_t RESERVED_13[24];
6597 __IO uint32_t PDSLEEPCFG; /**< Deep-sleep configuration register, offset: 0x230 */
6598 __IO uint32_t PDAWAKECFG; /**< Wake-up configuration register, offset: 0x234 */
6599 __IO uint32_t PDRUNCFG; /**< Power configuration register, offset: 0x238 */
6600 uint8_t RESERVED_14[444];
6601 __I uint32_t DEVICE_ID; /**< Part ID register, offset: 0x3F8 */
6602} SYSCON_Type;
6603
6604/* ----------------------------------------------------------------------------
6605 -- SYSCON Register Masks
6606 ---------------------------------------------------------------------------- */
6607
6608/*!
6609 * @addtogroup SYSCON_Register_Masks SYSCON Register Masks
6610 * @{
6611 */
6612
6613/*! @name SYSMEMREMAP - System Remap register */
6614/*! @{ */
6615#define SYSCON_SYSMEMREMAP_MAP_MASK (0x3U)
6616#define SYSCON_SYSMEMREMAP_MAP_SHIFT (0U)
6617/*! MAP - System memory remap. Value 0x3 is reserved.
6618 * 0b00..Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
6619 * 0b01..User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
6620 * 0b10..User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
6621 */
6622#define SYSCON_SYSMEMREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSMEMREMAP_MAP_SHIFT)) & SYSCON_SYSMEMREMAP_MAP_MASK)
6623/*! @} */
6624
6625/*! @name PRESETCTRL - Peripheral reset control register */
6626/*! @{ */
6627#define SYSCON_PRESETCTRL_SPI0_RST_N_MASK (0x1U)
6628#define SYSCON_PRESETCTRL_SPI0_RST_N_SHIFT (0U)
6629/*! SPI0_RST_N - SPI0 reset control.
6630 * 0b0..Assert the SPI0 reset.
6631 * 0b1..Clear the SPI0 reset.
6632 */
6633#define SYSCON_PRESETCTRL_SPI0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SPI0_RST_N_SHIFT)) & SYSCON_PRESETCTRL_SPI0_RST_N_MASK)
6634#define SYSCON_PRESETCTRL_SPI1_RST_N_MASK (0x2U)
6635#define SYSCON_PRESETCTRL_SPI1_RST_N_SHIFT (1U)
6636/*! SPI1_RST_N - SPI1 reset control.
6637 * 0b0..Assert the SPI1 reset.
6638 * 0b1..Clear the SPI1 reset.
6639 */
6640#define SYSCON_PRESETCTRL_SPI1_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SPI1_RST_N_SHIFT)) & SYSCON_PRESETCTRL_SPI1_RST_N_MASK)
6641#define SYSCON_PRESETCTRL_UARTFRG_RST_N_MASK (0x4U)
6642#define SYSCON_PRESETCTRL_UARTFRG_RST_N_SHIFT (2U)
6643/*! UARTFRG_RST_N - USART fractional baud rate generator(UARTFRG) reset control.
6644 * 0b0..Assert the UARTFRG reset.
6645 * 0b1..Clear the UARTFRG reset.
6646 */
6647#define SYSCON_PRESETCTRL_UARTFRG_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UARTFRG_RST_N_SHIFT)) & SYSCON_PRESETCTRL_UARTFRG_RST_N_MASK)
6648#define SYSCON_PRESETCTRL_UART0_RST_N_MASK (0x8U)
6649#define SYSCON_PRESETCTRL_UART0_RST_N_SHIFT (3U)
6650/*! UART0_RST_N - USART0 reset control.
6651 * 0b0..Assert the USART0 reset.
6652 * 0b1..Clear the USART0 reset.
6653 */
6654#define SYSCON_PRESETCTRL_UART0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UART0_RST_N_SHIFT)) & SYSCON_PRESETCTRL_UART0_RST_N_MASK)
6655#define SYSCON_PRESETCTRL_UART1_RST_N_MASK (0x10U)
6656#define SYSCON_PRESETCTRL_UART1_RST_N_SHIFT (4U)
6657/*! UART1_RST_N - USART1 reset control.
6658 * 0b0..Assert the USART1 reset.
6659 * 0b1..Clear the USART1 reset.
6660 */
6661#define SYSCON_PRESETCTRL_UART1_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UART1_RST_N_SHIFT)) & SYSCON_PRESETCTRL_UART1_RST_N_MASK)
6662#define SYSCON_PRESETCTRL_UART2_RST_N_MASK (0x20U)
6663#define SYSCON_PRESETCTRL_UART2_RST_N_SHIFT (5U)
6664/*! UART2_RST_N - USART2 reset control.
6665 * 0b0..Assert the USART2 reset.
6666 * 0b1..Clear the USART2 reset.
6667 */
6668#define SYSCON_PRESETCTRL_UART2_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UART2_RST_N_SHIFT)) & SYSCON_PRESETCTRL_UART2_RST_N_MASK)
6669#define SYSCON_PRESETCTRL_I2C0_RST_N_MASK (0x40U)
6670#define SYSCON_PRESETCTRL_I2C0_RST_N_SHIFT (6U)
6671/*! I2C0_RST_N - I2C0 reset control.
6672 * 0b0..Assert the I2C0 reset.
6673 * 0b1..Clear the I2C0 reset.
6674 */
6675#define SYSCON_PRESETCTRL_I2C0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_I2C0_RST_N_SHIFT)) & SYSCON_PRESETCTRL_I2C0_RST_N_MASK)
6676#define SYSCON_PRESETCTRL_MRT_RST_N_MASK (0x80U)
6677#define SYSCON_PRESETCTRL_MRT_RST_N_SHIFT (7U)
6678/*! MRT_RST_N - Multi-rate timer (MRT) reset control.
6679 * 0b0..Assert the MRT reset.
6680 * 0b1..Clear the MRT reset.
6681 */
6682#define SYSCON_PRESETCTRL_MRT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT_RST_N_SHIFT)) & SYSCON_PRESETCTRL_MRT_RST_N_MASK)
6683#define SYSCON_PRESETCTRL_SCT_RST_N_MASK (0x100U)
6684#define SYSCON_PRESETCTRL_SCT_RST_N_SHIFT (8U)
6685/*! SCT_RST_N - SCT reset control.
6686 * 0b0..Assert the SCT reset.
6687 * 0b1..Clear the SCT reset.
6688 */
6689#define SYSCON_PRESETCTRL_SCT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT_RST_N_SHIFT)) & SYSCON_PRESETCTRL_SCT_RST_N_MASK)
6690#define SYSCON_PRESETCTRL_WKT_RST_N_MASK (0x200U)
6691#define SYSCON_PRESETCTRL_WKT_RST_N_SHIFT (9U)
6692/*! WKT_RST_N - Self-wake-up timer (WKT) reset control.
6693 * 0b0..Assert the WKT reset.
6694 * 0b1..Clear the WKT reset.
6695 */
6696#define SYSCON_PRESETCTRL_WKT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WKT_RST_N_SHIFT)) & SYSCON_PRESETCTRL_WKT_RST_N_MASK)
6697#define SYSCON_PRESETCTRL_GPIO_RST_N_MASK (0x400U)
6698#define SYSCON_PRESETCTRL_GPIO_RST_N_SHIFT (10U)
6699/*! GPIO_RST_N - GPIO and GPIO pin interrupt reset control.
6700 * 0b0..Assert the GPIO reset.
6701 * 0b1..Clear the GPIO reset.
6702 */
6703#define SYSCON_PRESETCTRL_GPIO_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO_RST_N_SHIFT)) & SYSCON_PRESETCTRL_GPIO_RST_N_MASK)
6704#define SYSCON_PRESETCTRL_FLASH_RST_N_MASK (0x800U)
6705#define SYSCON_PRESETCTRL_FLASH_RST_N_SHIFT (11U)
6706/*! FLASH_RST_N - Flash controller reset control.
6707 * 0b0..Assert the flash controller reset.
6708 * 0b1..Clear the flash controller reset.
6709 */
6710#define SYSCON_PRESETCTRL_FLASH_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_N_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_N_MASK)
6711#define SYSCON_PRESETCTRL_ACMP_RST_N_MASK (0x1000U)
6712#define SYSCON_PRESETCTRL_ACMP_RST_N_SHIFT (12U)
6713/*! ACMP_RST_N - Analog comparator reset control.
6714 * 0b0..Assert the analog comparator reset.
6715 * 0b1..Clear the analog comparator controller reset.
6716 */
6717#define SYSCON_PRESETCTRL_ACMP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ACMP_RST_N_SHIFT)) & SYSCON_PRESETCTRL_ACMP_RST_N_MASK)
6718#define SYSCON_PRESETCTRL_I2C1_RST_N_MASK (0x4000U)
6719#define SYSCON_PRESETCTRL_I2C1_RST_N_SHIFT (14U)
6720/*! I2C1_RST_N - I2C1 reset control.
6721 * 0b0..Assert the I2C1 reset.
6722 * 0b1..Clear the I2C1 reset.
6723 */
6724#define SYSCON_PRESETCTRL_I2C1_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_I2C1_RST_N_SHIFT)) & SYSCON_PRESETCTRL_I2C1_RST_N_MASK)
6725#define SYSCON_PRESETCTRL_I2C2_RST_N_MASK (0x8000U)
6726#define SYSCON_PRESETCTRL_I2C2_RST_N_SHIFT (15U)
6727/*! I2C2_RST_N - I2C2 reset control.
6728 * 0b0..Assert the I2C2 reset.
6729 * 0b1..Clear the I2C2 reset.
6730 */
6731#define SYSCON_PRESETCTRL_I2C2_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_I2C2_RST_N_SHIFT)) & SYSCON_PRESETCTRL_I2C2_RST_N_MASK)
6732#define SYSCON_PRESETCTRL_I2C3_RST_N_MASK (0x10000U)
6733#define SYSCON_PRESETCTRL_I2C3_RST_N_SHIFT (16U)
6734/*! I2C3_RST_N - I2C3 reset control.
6735 * 0b0..Assert the I2C3 reset.
6736 * 0b1..Clear the I2C3 reset.
6737 */
6738#define SYSCON_PRESETCTRL_I2C3_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_I2C3_RST_N_SHIFT)) & SYSCON_PRESETCTRL_I2C3_RST_N_MASK)
6739#define SYSCON_PRESETCTRL_ADC_RST_N_MASK (0x1000000U)
6740#define SYSCON_PRESETCTRL_ADC_RST_N_SHIFT (24U)
6741/*! ADC_RST_N - ADC reset control.
6742 * 0b0..Assert the ADC reset.
6743 * 0b1..Clear the ADC reset.
6744 */
6745#define SYSCON_PRESETCTRL_ADC_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC_RST_N_SHIFT)) & SYSCON_PRESETCTRL_ADC_RST_N_MASK)
6746#define SYSCON_PRESETCTRL_DMA_RST_N_MASK (0x20000000U)
6747#define SYSCON_PRESETCTRL_DMA_RST_N_SHIFT (29U)
6748/*! DMA_RST_N - DMA reset control.
6749 * 0b0..Assert the DMA reset.
6750 * 0b1..Clear the DMA reset.
6751 */
6752#define SYSCON_PRESETCTRL_DMA_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA_RST_N_SHIFT)) & SYSCON_PRESETCTRL_DMA_RST_N_MASK)
6753/*! @} */
6754
6755/*! @name SYSPLLCTRL - PLL control */
6756/*! @{ */
6757#define SYSCON_SYSPLLCTRL_MSEL_MASK (0x1FU)
6758#define SYSCON_SYSPLLCTRL_MSEL_SHIFT (0U)
6759/*! MSEL - Feedback divider value. The division value M is the programmed MSEL value + 1. 00000:
6760 * Division ratio M = 1 to 11111: Division ratio M = 32