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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/driver_reset.cmake14
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_clock.c458
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_clock.h574
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_inputmux_connections.h84
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_power.c163
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_power.h386
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_reset.c92
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_reset.h140
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_swm_connections.h134
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_syscon_connections.h73
10 files changed, 2118 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/driver_reset.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/driver_reset.cmake
new file mode 100644
index 000000000..989530f6f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/driver_reset.cmake
@@ -0,0 +1,14 @@
1if(NOT DRIVER_RESET_INCLUDED)
2
3 set(DRIVER_RESET_INCLUDED true CACHE BOOL "driver_reset component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 )
7
8 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
9 ${CMAKE_CURRENT_LIST_DIR}/.
10 )
11
12
13
14endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_clock.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_clock.c
new file mode 100644
index 000000000..9016f71af
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_clock.c
@@ -0,0 +1,458 @@
1/*
2 * Copyright 2017-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_clock.h"
9/*******************************************************************************
10 * Definitions
11 ******************************************************************************/
12/* Component ID definition, used by tools. */
13#ifndef FSL_COMPONENT_ID
14#define FSL_COMPONENT_ID "platform.drivers.clock"
15#endif
16#define SYSPLL_MIN_INPUT_FREQ_HZ (10000000U) /*!< Minimum PLL input rate */
17#define SYSPLL_MAX_INPUT_FREQ_HZ (25000000U) /*!< Maximum PLL input rate */
18#define SYSPLL_MAX_OUTPUT_FREQ_HZ (100000000U) /*!< Maximum PLL output rate */
19#define SYSPLL_MIN_FCCO_FREQ_HZ (156000000U) /*!< Maximum FCCO output rate */
20#define SYSPLL_MAX_FCCO_FREQ_HZ (320000000U) /*!< Maximum FCCO output rate */
21#define SYSOSC_BOUNDARY_FREQ_HZ (15000000U) /*!< boundary frequency value */
22
23/* External clock rate.
24 * Either external clk in rate or system oscillator frequency.
25 */
26uint32_t g_Ext_Clk_Freq = 0U;
27uint32_t g_Wdt_Osc_Freq = 0U;
28
29/** Sys pll freq.*/
30uint32_t g_Sys_Pll_Freq = 0U;
31/*******************************************************************************
32 * Variables
33 ******************************************************************************/
34
35/*******************************************************************************
36 * Prototypes
37 ******************************************************************************/
38/*
39 * @brief select post divider for system pll according to the target frequency.
40 * @param outFreq: Value to be output
41 * @return post divider
42 */
43static uint32_t findSyestemPllPsel(uint32_t outFreq);
44
45/*
46 * @brief Update clock source.
47 * @param base clock register base address.
48 * @param mask clock source update enable bit mask value.
49 */
50static void CLOCK_UpdateClkSrc(volatile uint32_t *base, uint32_t mask);
51
52/*******************************************************************************
53 * Code
54 ******************************************************************************/
55static void CLOCK_UpdateClkSrc(volatile uint32_t *base, uint32_t mask)
56{
57 assert(base);
58
59 *base &= ~mask;
60 *base |= mask;
61 while ((*base & mask) == 0U)
62 {
63 }
64}
65
66/*! brief Return Frequency of IRC
67 * return Frequency of IRC
68 */
69uint32_t CLOCK_GetIrcFreq(void)
70{
71 return 12000000U;
72}
73
74/*! brief Return Frequency of SYSOSC
75 * return Frequency of SYSOSC
76 */
77uint32_t CLOCK_GetSysOscFreq(void)
78{
79 uint32_t freq = 0U;
80 if ((SYSCON->PDRUNCFG & SYSCON_PDRUNCFG_SYSOSC_PD_MASK) == 0U)
81 {
82 freq = CLOCK_GetExtClkFreq();
83 }
84 return freq;
85}
86
87/*! brief Return Frequency of Main Clock.
88 * return Frequency of Main Clock.
89 */
90uint32_t CLOCK_GetMainClkFreq(void)
91{
92 uint32_t freq = 0U;
93
94 switch (SYSCON->MAINCLKSEL)
95 {
96 case 0U:
97 freq = CLOCK_GetIrcFreq();
98 break;
99
100 case 1U:
101 freq = CLOCK_GetSystemPLLInClockRate();
102 break;
103
104 case 2U:
105 freq = CLOCK_GetWdtOscFreq();
106 break;
107
108 case 3U:
109 freq = CLOCK_GetSystemPLLFreq();
110 break;
111 default:
112 assert(false);
113 break;
114 }
115
116 return freq;
117}
118
119/*! brief Return Frequency of ClockOut
120 * return Frequency of ClockOut
121 */
122uint32_t CLOCK_GetClockOutClkFreq(void)
123{
124 uint32_t div = SYSCON->CLKOUTDIV & 0xffU, freq = 0U;
125
126 switch (SYSCON->CLKOUTSEL)
127 {
128 case 0U:
129 freq = CLOCK_GetIrcFreq();
130 break;
131
132 case 1U:
133 freq = CLOCK_GetSysOscFreq();
134 break;
135
136 case 2U:
137 freq = CLOCK_GetWdtOscFreq();
138 break;
139
140 case 3U:
141 freq = CLOCK_GetMainClkFreq();
142 break;
143
144 default:
145 assert(false);
146 break;
147 }
148
149 return div == 0U ? 0U : (freq / div);
150}
151
152/*! brief Return Frequency of UART
153 * return Frequency of UART
154 */
155uint32_t CLOCK_GetUartClkFreq(void)
156{
157 uint32_t freq = CLOCK_GetMainClkFreq();
158 uint32_t uartDiv = SYSCON->UARTCLKDIV & 0xffU;
159
160 return uartDiv == 0U ? 0U :
161 (uint32_t)((uint64_t)(freq << 8U) /
162 (uartDiv * (256U + ((SYSCON->UARTFRGMULT) & SYSCON_UARTFRGMULT_MULT_MASK))));
163}
164
165/*! brief Return Frequency of UART0
166 * return Frequency of UART0
167 */
168uint32_t CLOCK_GetUart0ClkFreq(void)
169{
170 return CLOCK_GetUartClkFreq();
171}
172
173/*! brief Return Frequency of UART1
174 * return Frequency of UART1
175 */
176uint32_t CLOCK_GetUart1ClkFreq(void)
177{
178 return CLOCK_GetUartClkFreq();
179}
180
181/*! brief Return Frequency of UART2
182 * return Frequency of UART2
183 */
184uint32_t CLOCK_GetUart2ClkFreq(void)
185{
186 return CLOCK_GetUartClkFreq();
187}
188
189/*! brief Return Frequency of selected clock
190 * return Frequency of selected clock
191 */
192uint32_t CLOCK_GetFreq(clock_name_t clockName)
193{
194 uint32_t freq;
195
196 switch (clockName)
197 {
198 case kCLOCK_CoreSysClk:
199 freq = CLOCK_GetCoreSysClkFreq();
200 break;
201 case kCLOCK_MainClk:
202 freq = CLOCK_GetMainClkFreq();
203 break;
204 case kCLOCK_Irc:
205 freq = CLOCK_GetIrcFreq();
206 break;
207 case kCLOCK_ExtClk:
208 freq = CLOCK_GetExtClkFreq();
209 break;
210 case kCLOCK_WdtOsc:
211 freq = CLOCK_GetWdtOscFreq();
212 break;
213 case kCLOCK_PllOut:
214 freq = CLOCK_GetSystemPLLFreq();
215 break;
216
217 default:
218 freq = 0U;
219 break;
220 }
221
222 return freq;
223}
224
225/*! brief Return System PLL input clock rate
226 * return System PLL input clock rate
227 */
228uint32_t CLOCK_GetSystemPLLInClockRate(void)
229{
230 uint32_t freq = 0U;
231
232 switch ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK))
233 {
234 /* source from external clock in */
235 case 0x00U:
236 freq = CLOCK_GetIrcFreq();
237 break;
238 /* source from the IRC clock */
239 case 0x01U:
240 freq = CLOCK_GetSysOscFreq();
241 break;
242 /* source from external clock clock */
243 case 0x03U:
244 freq = CLOCK_GetExtClkFreq();
245 break;
246
247 default:
248 assert(false);
249 break;
250 }
251
252 return freq;
253}
254
255static uint32_t findSyestemPllPsel(uint32_t outFreq)
256{
257 uint32_t pSel = 0U;
258
259 if (outFreq > (SYSPLL_MIN_FCCO_FREQ_HZ >> 1U))
260 {
261 pSel = 0U;
262 }
263 else if (outFreq > (SYSPLL_MIN_FCCO_FREQ_HZ >> 2U))
264 {
265 pSel = 1U;
266 }
267 else if (outFreq > (SYSPLL_MIN_FCCO_FREQ_HZ >> 3U))
268 {
269 pSel = 2U;
270 }
271 else
272 {
273 pSel = 3U;
274 }
275
276 return pSel;
277}
278
279/*! brief System PLL initialize.
280 * param config System PLL configurations.
281 */
282void CLOCK_InitSystemPll(const clock_sys_pll_t *config)
283{
284 assert(config->targetFreq <= SYSPLL_MAX_OUTPUT_FREQ_HZ);
285
286 uint32_t mSel = 0U, pSel = 0U, inputFreq = 0U;
287 uint32_t syspllclkseltmp;
288 /* Power off PLL during setup changes */
289 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSPLL_PD_MASK;
290
291 /*set system pll clock source select register */
292 syspllclkseltmp = (SYSCON->SYSPLLCLKSEL & (~SYSCON_SYSPLLCLKSEL_SEL_MASK)) | (uint32_t)config->src;
293 SYSCON->SYSPLLCLKSEL |= syspllclkseltmp;
294 /* system pll clock source update */
295 CLOCK_UpdateClkSrc((volatile uint32_t *)(&(SYSCON->SYSPLLCLKUEN)), SYSCON_SYSPLLCLKSEL_SEL_MASK);
296
297 inputFreq = CLOCK_GetSystemPLLInClockRate();
298 assert(inputFreq != 0U);
299
300 /* calucate the feedback divider value and post divider value*/
301 mSel = config->targetFreq / inputFreq;
302 pSel = findSyestemPllPsel(config->targetFreq);
303
304 /* configure PSEL and MSEL */
305 SYSCON->SYSPLLCTRL = (SYSCON->SYSPLLCTRL & (~(SYSCON_SYSPLLCTRL_MSEL_MASK | SYSCON_SYSPLLCTRL_PSEL_MASK))) |
306 SYSCON_SYSPLLCTRL_MSEL(mSel - 1U) | SYSCON_SYSPLLCTRL_PSEL(pSel);
307
308 /* Power up PLL after setup changes */
309 SYSCON->PDRUNCFG &= ~SYSCON_PDRUNCFG_SYSPLL_PD_MASK;
310
311 /* wait pll lock */
312 while ((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) == 0U)
313 {
314 }
315
316 g_Sys_Pll_Freq = inputFreq * mSel;
317}
318
319/*! brief Init external CLK IN, select the CLKIN as the external clock source.
320 * param clkInFreq external clock in frequency.
321 */
322void CLOCK_InitExtClkin(uint32_t clkInFreq)
323{
324 /* remove the pull up and pull down resistors in the IOCON */
325 IOCON->PIO[IOCON_INDEX_PIO0_1] &= ~IOCON_PIO_MODE_MASK;
326 /* enable the 1 bit functions for CLKIN */
327 SWM0->PINENABLE0 &= ~SWM_PINENABLE0_CLKIN_MASK;
328 /* record the external clock rate */
329 g_Ext_Clk_Freq = clkInFreq;
330}
331
332/*! brief XTALIN init function
333 * system oscillator is bypassed, sys_osc_clk is fed driectly from the XTALIN.
334 * param xtalInFreq XTALIN frequency value
335 * return Frequency of PLL
336 */
337void CLOCK_InitXtalin(uint32_t xtalInFreq)
338{
339 /* remove the pull up and pull down resistors in the IOCON */
340 IOCON->PIO[IOCON_INDEX_PIO0_8] &= ~IOCON_PIO_MODE_MASK;
341 /* enable the 1 bit functions for XTALIN and XTALOUT */
342 SWM0->PINENABLE0 &= ~SWM_PINENABLE0_XTALIN_MASK;
343
344 /* system osc configure */
345 SYSCON->SYSOSCCTRL |= SYSCON_SYSOSCCTRL_BYPASS_MASK;
346 /* enable system osc power first */
347 SYSCON->PDRUNCFG &= ~SYSCON_PDRUNCFG_SYSOSC_PD_MASK;
348
349 /* software delay 500USs */
350 SDK_DelayAtLeastUs(500U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
351
352 /* record the external clock rate */
353 g_Ext_Clk_Freq = xtalInFreq;
354}
355
356/*! brief Init SYS OSC
357 * param oscFreq oscillator frequency value.
358 */
359void CLOCK_InitSysOsc(uint32_t oscFreq)
360{
361 uint32_t sysoscctrltmp;
362 /* remove the pull up and pull down resistors in the IOCON */
363 IOCON->PIO[IOCON_INDEX_PIO0_9] &= ~IOCON_PIO_MODE_MASK;
364 IOCON->PIO[IOCON_INDEX_PIO0_8] &= ~IOCON_PIO_MODE_MASK;
365 /* enable the 1 bit functions for XTALIN and XTALOUT */
366 SWM0->PINENABLE0 &= ~(SWM_PINENABLE0_XTALIN_MASK | SWM_PINENABLE0_XTALOUT_MASK);
367
368 /* system osc configure */
369 sysoscctrltmp = (SYSCON->SYSOSCCTRL & (~(SYSCON_SYSOSCCTRL_BYPASS_MASK | SYSCON_SYSOSCCTRL_FREQ_RANGE_MASK))) |
370 (oscFreq > SYSOSC_BOUNDARY_FREQ_HZ ? SYSCON_SYSOSCCTRL_FREQ_RANGE_MASK : 0U);
371 SYSCON->SYSOSCCTRL |= sysoscctrltmp;
372
373 /* enable system osc power first */
374 SYSCON->PDRUNCFG &= ~SYSCON_PDRUNCFG_SYSOSC_PD_MASK;
375
376 /* software delay 500USs */
377 SDK_DelayAtLeastUs(500U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
378
379 /* record the external clock rate */
380 g_Ext_Clk_Freq = oscFreq;
381}
382
383/*! brief Init watch dog OSC
384 * Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the
385 * listed frequency value. The watchdog oscillator is the clock source with the lowest power
386 * consumption. If accurate timing is required, use the FRO or system oscillator.
387 * The frequency of the watchdog oscillator is undefined after reset. The watchdog
388 * oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
389 * using the watchdog oscillator.
390 * Watchdog osc output frequency = wdtOscFreq / wdtOscDiv, should in range 9.3KHZ to 2.3MHZ.
391 * param wdtOscFreq watch dog analog part output frequency, reference _wdt_analog_output_freq.
392 * param wdtOscDiv watch dog analog part output frequency divider, shoule be a value >= 2U and multiple of 2
393 */
394void CLOCK_InitWdtOsc(clock_wdt_analog_freq_t wdtOscFreq, uint32_t wdtOscDiv)
395{
396 assert(wdtOscDiv >= 2U);
397
398 uint32_t wdtOscCtrl = SYSCON->WDTOSCCTRL;
399
400 wdtOscCtrl &= ~(SYSCON_WDTOSCCTRL_DIVSEL_MASK | SYSCON_WDTOSCCTRL_FREQSEL_MASK);
401
402 wdtOscCtrl |=
403 SYSCON_WDTOSCCTRL_DIVSEL((wdtOscDiv >> 1U) - 1U) | SYSCON_WDTOSCCTRL_FREQSEL(CLK_WDT_OSC_GET_REG(wdtOscFreq));
404
405 SYSCON->WDTOSCCTRL = wdtOscCtrl;
406
407 /* power up watchdog oscillator */
408 SYSCON->PDRUNCFG &= ~SYSCON_PDRUNCFG_WDTOSC_PD_MASK;
409 /* update watch dog oscillator value */
410 g_Wdt_Osc_Freq = CLK_WDT_OSC_GET_FREQ(wdtOscFreq) / wdtOscDiv;
411}
412
413/*! brief Set main clock reference source.
414 * param src, reference clock_main_clk_src_t to set the main clock source.
415 */
416void CLOCK_SetMainClkSrc(clock_main_clk_src_t src)
417{
418 uint32_t mainMux = CLK_MAIN_CLK_MUX_GET_MUX(src), mainPreMux = CLK_MAIN_CLK_MUX_GET_PRE_MUX(src);
419
420 if (((SYSCON->MAINCLKSEL & SYSCON_MAINCLKSEL_SEL_MASK) != mainPreMux) && (mainMux == 0U))
421 {
422 SYSCON->MAINCLKSEL = (SYSCON->MAINCLKSEL & (~SYSCON_MAINCLKSEL_SEL_MASK)) | SYSCON_MAINCLKSEL_SEL(mainPreMux);
423 CLOCK_UpdateClkSrc((volatile uint32_t *)(&(SYSCON->MAINCLKUEN)), SYSCON_MAINCLKUEN_ENA_MASK);
424 }
425}
426
427/*! brief Set UARTFRG
428 * param target UART clock src.
429 */
430bool CLOCK_SetUARTFRGClkFreq(uint32_t freq)
431{
432 uint32_t input = CLOCK_GetMainClkFreq();
433 uint32_t mul;
434
435 freq *= SYSCON->UARTCLKDIV;
436
437 /* The given frequency should not be 0. */
438 assert(0UL != freq);
439
440 if ((freq > input) || (input / freq >= 2U))
441 {
442 return false;
443 }
444
445 mul = (uint32_t)(((uint64_t)((uint64_t)input - freq) << 8U) / ((uint64_t)freq));
446
447 SYSCON->UARTFRGDIV = SYSCON_UARTFRGDIV_DIV_MASK;
448 SYSCON->UARTFRGMULT = SYSCON_UARTFRGMULT_MULT(mul);
449
450 return true;
451}
452
453/*! brief updates the clock source of the CLKOUT
454 */
455void CLOCK_UpdateClkOUTsrc(void)
456{
457 CLOCK_UpdateClkSrc((volatile uint32_t *)(&(SYSCON->CLKOUTUEN)), SYSCON_CLKOUTUEN_ENA_MASK);
458}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_clock.h
new file mode 100644
index 000000000..8533ec7b7
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_clock.h
@@ -0,0 +1,574 @@
1/*
2 * Copyright 2017-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_common.h"
12
13/*! @addtogroup clock */
14/*! @{ */
15
16/*! @file */
17
18/*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22/*! @name Driver version */
23/*@{*/
24/*! @brief CLOCK driver version 2.4.2. */
25#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 2))
26/*@}*/
27
28/* Definition for delay API in clock driver, users can redefine it to the real application. */
29#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
30#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (30000000UL)
31#endif
32
33/*! @brief watchdog oscilltor clock frequency.
34 *
35 * This variable is used to store the watchdog oscillator frequency which is
36 * set by CLOCK_InitWdtOsc, and it is returned by CLOCK_GetWdtOscFreq.
37 */
38extern uint32_t g_Wdt_Osc_Freq;
39
40/*! @brief external clock frequency.
41 *
42 * This variable is used to store the external clock frequency which is include
43 * external oscillator clock and external clk in clock frequency value, it is
44 * set by CLOCK_InitExtClkin when CLK IN is used as external clock or by CLOCK_InitSysOsc
45 * when external oscillator is used as external clock ,and it is returned by
46 * CLOCK_GetExtClkFreq.
47 */
48extern uint32_t g_Ext_Clk_Freq;
49
50extern uint32_t g_Sys_Pll_Freq;
51
52/*! @brief Clock ip name array for ADC. */
53#define ADC_CLOCKS \
54 { \
55 kCLOCK_Adc, \
56 }
57/*! @brief Clock ip name array for ACMP. */
58#define ACMP_CLOCKS \
59 { \
60 kCLOCK_Acmp, \
61 }
62/*! @brief Clock ip name array for SWM. */
63#define SWM_CLOCKS \
64 { \
65 kCLOCK_Swm, \
66 }
67/*! @brief Clock ip name array for ROM. */
68#define ROM_CLOCKS \
69 { \
70 kCLOCK_Rom, \
71 }
72/*! @brief Clock ip name array for SRAM. */
73#define SRAM_CLOCKS \
74 { \
75 kCLOCK_Ram0_1, \
76 }
77/*! @brief Clock ip name array for IOCON. */
78#define IOCON_CLOCKS \
79 { \
80 kCLOCK_Iocon, \
81 }
82/*! @brief Clock ip name array for GPIO. */
83#define GPIO_CLOCKS \
84 { \
85 kCLOCK_Gpio0, \
86 }
87/*! @brief Clock ip name array for GPIO_INT. */
88#define GPIO_INT_CLOCKS \
89 { \
90 kCLOCK_GpioInt, \
91 }
92/*! @brief Clock ip name array for DMA. */
93#define DMA_CLOCKS \
94 { \
95 kCLOCK_Dma, \
96 }
97/*! @brief Clock ip name array for CRC. */
98#define CRC_CLOCKS \
99 { \
100 kCLOCK_Crc, \
101 }
102/*! @brief Clock ip name array for WWDT. */
103#define WWDT_CLOCKS \
104 { \
105 kCLOCK_Wwdt, \
106 }
107/*! @brief Clock ip name array for SCT0. */
108#define SCT_CLOCKS \
109 { \
110 kCLOCK_Sct, \
111 }
112/*! @brief Clock ip name array for I2C. */
113#define I2C_CLOCKS \
114 { \
115 kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, \
116 }
117/*! @brief Clock ip name array for I2C. */
118#define USART_CLOCKS \
119 { \
120 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, \
121 }
122/*! @brief Clock ip name array for SPI. */
123#define SPI_CLOCKS \
124 { \
125 kCLOCK_Spi0, kCLOCK_Spi1, \
126 }
127/*! @brief Clock ip name array for MTB. */
128#define MTB_CLOCKS \
129 { \
130 kCLOCK_Mtb, \
131 }
132/*! @brief Clock ip name array for MRT. */
133#define MRT_CLOCKS \
134 { \
135 kCLOCK_Mrt, \
136 }
137/*! @brief Clock ip name array for WKT. */
138#define WKT_CLOCKS \
139 { \
140 kCLOCK_Wkt, \
141 }
142
143/*! @brief Internal used Clock definition only. */
144#define CLK_GATE_DEFINE(reg, bit) ((((reg)&0xFFU) << 8U) | ((bit)&0xFFU))
145#define CLK_GATE_GET_REG(x) (((x) >> 8U) & 0xFFU)
146#define CLK_GATE_GET_BITS_SHIFT(x) ((uint32_t)(x)&0xFFU)
147/* clock mux register definition */
148#define CLK_MUX_DEFINE(reg, mux) (((offsetof(SYSCON_Type, reg) & 0xFFU) << 8U) | ((mux)&0xFFU))
149#define CLK_MUX_GET_REG(x) ((volatile uint32_t *)(((uint32_t)(SYSCON)) + (((uint32_t)(x) >> 8U) & 0xFFU)))
150#define CLK_MUX_GET_MUX(x) ((uint32_t)(x)&0xFFU)
151#define CLK_MAIN_CLK_MUX_DEFINE(preMux, mux) ((preMux) << 8U | (mux))
152#define CLK_MAIN_CLK_MUX_GET_PRE_MUX(x) ((((uint32_t)(x)) >> 8U) & 0xFFU)
153#define CLK_MAIN_CLK_MUX_GET_MUX(x) (((uint32_t)(x)) & 0xFFU)
154/* clock divider register definition */
155#define CLK_DIV_DEFINE(reg) (((uint32_t)offsetof(SYSCON_Type, reg)) & 0xFFFU)
156#define CLK_DIV_GET_REG(x) *((volatile uint32_t *)(((uint32_t)(SYSCON)) + ((uint32_t)(x)&0xFFFU)))
157/* watch dog oscillator definition */
158#define CLK_WDT_OSC_DEFINE(freq, regValue) (((freq)&0xFFFFFFU) | (((regValue)&0xFFU) << 24U))
159#define CLK_WDT_OSC_GET_FREQ(x) (((uint32_t)(x)) & 0xFFFFFFU)
160#define CLK_WDT_OSC_GET_REG(x) (((uint32_t)(x) >> 24U) & 0xFFU)
161/* register offset */
162#define SYS_AHB_CLK_CTRL (0U)
163/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
164typedef enum _clock_ip_name
165{
166 kCLOCK_Sys = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 0U),
167 kCLOCK_Rom = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 1U),
168 kCLOCK_Ram0_1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 2U),
169 kCLOCK_Flashreg = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 3U),
170 kCLOCK_Flash = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 4U),
171 kCLOCK_I2c0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 5U),
172 kCLOCK_Gpio0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 6U),
173 kCLOCK_Swm = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 7U),
174 kCLOCK_Sct = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 8U),
175 kCLOCK_Wkt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 9U),
176 kCLOCK_Mrt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 10U),
177 kCLOCK_Spi0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 11U),
178 kCLOCK_Spi1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 12U),
179 kCLOCK_Crc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 13U),
180 kCLOCK_Uart0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 14U),
181 kCLOCK_Uart1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 15U),
182 kCLOCK_Uart2 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 16U),
183 kCLOCK_Wwdt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 17U),
184 kCLOCK_Iocon = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 18U),
185 kCLOCK_Acmp = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 19U),
186 kCLOCK_I2c1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 21U),
187 kCLOCK_I2c2 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 22U),
188 kCLOCK_I2c3 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 23U),
189 kCLOCK_Adc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 24U),
190 kCLOCK_Mtb = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 26U),
191 kCLOCK_Dma = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 29U),
192} clock_ip_name_t;
193
194/*! @brief Clock name used to get clock frequency. */
195typedef enum _clock_name
196{
197 kCLOCK_CoreSysClk, /*!< Cpu/AHB/AHB matrix/Memories,etc */
198 kCLOCK_MainClk, /*!< Main clock */
199 kCLOCK_SysOsc, /*!< Crystal Oscillator */
200 kCLOCK_Irc, /*!< IRC12M */
201 kCLOCK_ExtClk, /*!< External Clock */
202 kCLOCK_PllOut, /*!< PLL Output */
203 kCLOCK_Pllin, /*!< PLL Input */
204 kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
205} clock_name_t;
206
207/*! @brief Clock Mux Switches
208 *CLK_MUX_DEFINE(reg, mux)
209 *reg is used to define the mux register
210 *mux is used to define the mux value
211 *
212 */
213typedef enum _clock_select
214{
215
216 kSYSPLL_From_Irc = CLK_MUX_DEFINE(SYSPLLCLKSEL, 0U),
217 kSYSPLL_From_SysOsc = CLK_MUX_DEFINE(SYSPLLCLKSEL, 1U),
218 kSYSPLL_From_ExtClk = CLK_MUX_DEFINE(SYSPLLCLKSEL, 3U),
219
220 kMAINCLK_From_Irc = CLK_MUX_DEFINE(MAINCLKSEL, 0U),
221 kMAINCLK_From_SysPllIn = CLK_MUX_DEFINE(MAINCLKSEL, 1U),
222 kMAINCLK_From_WdtOsc = CLK_MUX_DEFINE(MAINCLKSEL, 2U),
223 kMAINCLK_From_SysPll = CLK_MUX_DEFINE(MAINCLKSEL, 3U),
224
225 kCLKOUT_From_Irc = CLK_MUX_DEFINE(CLKOUTSEL, 0U),
226 kCLKOUT_From_SysOsc = CLK_MUX_DEFINE(CLKOUTSEL, 1U),
227 kCLKOUT_From_WdtOsc = CLK_MUX_DEFINE(CLKOUTSEL, 2U),
228 kCLKOUT_From_MainClk = CLK_MUX_DEFINE(CLKOUTSEL, 3U)
229} clock_select_t;
230
231/*! @brief Clock divider
232 */
233typedef enum _clock_divider
234{
235
236 kCLOCK_DivUsartClk = CLK_DIV_DEFINE(UARTCLKDIV),
237 kCLOCK_DivClkOut = CLK_DIV_DEFINE(CLKOUTDIV),
238 kCLOCK_DivUartFrg = CLK_DIV_DEFINE(UARTFRGDIV),
239
240 kCLOCK_IOCONCLKDiv6 = CLK_DIV_DEFINE(IOCONCLKDIV6),
241 kCLOCK_IOCONCLKDiv5 = CLK_DIV_DEFINE(IOCONCLKDIV5),
242 kCLOCK_IOCONCLKDiv4 = CLK_DIV_DEFINE(IOCONCLKDIV4),
243 kCLOCK_IOCONCLKDiv3 = CLK_DIV_DEFINE(IOCONCLKDIV3),
244 kCLOCK_IOCONCLKDiv2 = CLK_DIV_DEFINE(IOCONCLKDIV2),
245 kCLOCK_IOCONCLKDiv1 = CLK_DIV_DEFINE(IOCONCLKDIV1),
246 kCLOCK_IOCONCLKDiv0 = CLK_DIV_DEFINE(IOCONCLKDIV0),
247
248} clock_divider_t;
249
250/*! @brief watch dog analog output frequency */
251typedef enum _clock_wdt_analog_freq
252{
253 kCLOCK_WdtAnaFreq0HZ = CLK_WDT_OSC_DEFINE(0U, 0U),
254 kCLOCK_WdtAnaFreq600KHZ = CLK_WDT_OSC_DEFINE(600000U, 1U),
255 kCLOCK_WdtAnaFreq1050KHZ = CLK_WDT_OSC_DEFINE(1050000U, 2u),
256 kCLOCK_WdtAnaFreq1400KHZ = CLK_WDT_OSC_DEFINE(1400000U, 3U),
257 kCLOCK_WdtAnaFreq1750KHZ = CLK_WDT_OSC_DEFINE(1750000U, 4U),
258 kCLOCK_WdtAnaFreq2100KHZ = CLK_WDT_OSC_DEFINE(2100000U, 5U),
259 kCLOCK_WdtAnaFreq2400KHZ = CLK_WDT_OSC_DEFINE(2400000U, 6U),
260 kCLOCK_WdtAnaFreq2700KHZ = CLK_WDT_OSC_DEFINE(2700000U, 7U),
261 kCLOCK_WdtAnaFreq3000KHZ = CLK_WDT_OSC_DEFINE(3000000U, 8U),
262 kCLOCK_WdtAnaFreq3250KHZ = CLK_WDT_OSC_DEFINE(3250000U, 9U),
263 kCLOCK_WdtAnaFreq3500KHZ = CLK_WDT_OSC_DEFINE(3500000U, 10U),
264 kCLOCK_WdtAnaFreq3750KHZ = CLK_WDT_OSC_DEFINE(3750000U, 11U),
265 kCLOCK_WdtAnaFreq4000KHZ = CLK_WDT_OSC_DEFINE(4000000U, 12U),
266 kCLOCK_WdtAnaFreq4200KHZ = CLK_WDT_OSC_DEFINE(4200000U, 13U),
267 kCLOCK_WdtAnaFreq4400KHZ = CLK_WDT_OSC_DEFINE(4400000U, 14U),
268 kCLOCK_WdtAnaFreq4600KHZ = CLK_WDT_OSC_DEFINE(4600000U, 15U),
269} clock_wdt_analog_freq_t;
270
271/*! @brief PLL clock definition.*/
272typedef enum _clock_sys_pll_src
273{
274 kCLOCK_SysPllSrcIrc = 0U, /*!< system pll source from FRO */
275 kCLOCK_SysPllSrcSysosc = 1U, /*!< system pll source from system osc */
276 kCLOCK_SysPllSrcExtClk = 3U, /*!< system pll source from ext clkin */
277} clock_sys_pll_src;
278
279/*!< Main clock source definition */
280typedef enum _clock_main_clk_src
281{
282 kCLOCK_MainClkSrcIrc = CLK_MAIN_CLK_MUX_DEFINE(0U, 0U), /*!< main clock source from FRO */
283 kCLOCK_MainClkSrcSysPllin = CLK_MAIN_CLK_MUX_DEFINE(1U, 0U), /*!< main clock source from pll input */
284 kCLOCK_MainClkSrcWdtOsc = CLK_MAIN_CLK_MUX_DEFINE(2U, 0U), /*!< main clock source from watchdog oscillator */
285 kCLOCK_MainClkSrcSysPll = CLK_MAIN_CLK_MUX_DEFINE(3U, 0U), /*!< main clock source from system pll */
286} clock_main_clk_src_t;
287
288/*! @brief PLL configuration structure */
289typedef struct _clock_sys_pll
290{
291 uint32_t targetFreq; /*!< System pll fclk output frequency, the output frequency should be lower than 100MHZ*/
292 clock_sys_pll_src src; /*!< System pll clock source */
293} clock_sys_pll_t;
294
295/*******************************************************************************
296 * API
297 ******************************************************************************/
298
299#if defined(__cplusplus)
300extern "C" {
301#endif /* __cplusplus */
302
303/*!
304 * @name Clock gate, mux, and divider.
305 * @{
306 */
307
308/*
309 *! @brief enable ip clock.
310 *
311 * @param clk clock ip definition.
312 */
313static inline void CLOCK_EnableClock(clock_ip_name_t clk)
314{
315 SYSCON->SYSAHBCLKCTRL |= 1UL << CLK_GATE_GET_BITS_SHIFT(clk);
316}
317
318/*
319 *!@brief disable ip clock.
320 *
321 * @param clk clock ip definition.
322 */
323static inline void CLOCK_DisableClock(clock_ip_name_t clk)
324{
325 SYSCON->SYSAHBCLKCTRL &= ~(1UL << CLK_GATE_GET_BITS_SHIFT(clk));
326}
327
328/*
329 *! @brief Configure the clock selection muxes.
330 * @param mux : Clock to be configured.
331 * @return Nothing
332 */
333static inline void CLOCK_Select(clock_select_t sel)
334{
335 *(CLK_MUX_GET_REG(sel)) = CLK_MUX_GET_MUX(sel);
336}
337
338/*
339 *! @brief Setup peripheral clock dividers.
340 * @param name : Clock divider name
341 * @param value: Value to be divided
342 * @return Nothing
343 */
344static inline void CLOCK_SetClkDivider(clock_divider_t name, uint32_t value)
345{
346 CLK_DIV_GET_REG(name) = value & 0xFFU;
347}
348
349/*
350 *! @brief Get peripheral clock dividers.
351 * @param name : Clock divider name
352 * @return clock divider value
353 */
354static inline uint32_t CLOCK_GetClkDivider(clock_divider_t name)
355{
356 return CLK_DIV_GET_REG(name) & 0xFFU;
357}
358
359/*
360 *! @brief Setup Core clock dividers.
361 * Be careful about the core divider value, due to core/system frequency should be lower than 30MHZ.
362 * @param value: Value to be divided
363 * @return Nothing
364 */
365static inline void CLOCK_SetCoreSysClkDiv(uint32_t value)
366{
367 assert(value != 0U);
368
369 SYSCON->SYSAHBCLKDIV = (SYSCON->SYSAHBCLKDIV & (~SYSCON_SYSAHBCLKDIV_DIV_MASK)) | SYSCON_SYSAHBCLKDIV_DIV(value);
370}
371
372/*! @brief Set main clock reference source.
373 * @param src, reference clock_main_clk_src_t to set the main clock source.
374 */
375void CLOCK_SetMainClkSrc(clock_main_clk_src_t src);
376
377/*
378 *! @brief Set Fractional generator 0 multiplier value.
379 * @param mul : FRG0 multiplier value.
380 * @return Nothing
381 */
382static inline void CLOCK_SetFRGClkMul(uint32_t mul)
383{
384 SYSCON->UARTFRGDIV = SYSCON_UARTFRGDIV_DIV_MASK;
385 SYSCON->UARTFRGMULT = SYSCON_UARTFRGMULT_MULT(mul);
386}
387/* @} */
388
389/*!
390 * @name Get frequency
391 * @{
392 */
393
394/*! @brief Return Frequency of Main Clock.
395 * @return Frequency of Main Clock.
396 */
397uint32_t CLOCK_GetMainClkFreq(void);
398
399/*! @brief Return Frequency of core.
400 * @return Frequency of core.
401 */
402static inline uint32_t CLOCK_GetCoreSysClkFreq(void)
403{
404 return CLOCK_GetMainClkFreq() / (SYSCON->SYSAHBCLKDIV & 0xffU);
405}
406
407/*! @brief Return Frequency of ClockOut
408 * @return Frequency of ClockOut
409 */
410uint32_t CLOCK_GetClockOutClkFreq(void);
411
412/*! @brief Return Frequency of IRC
413 * @return Frequency of IRC
414 */
415uint32_t CLOCK_GetIrcFreq(void);
416
417/*! @brief Return Frequency of SYSOSC
418 * @return Frequency of SYSOSC
419 */
420uint32_t CLOCK_GetSysOscFreq(void);
421
422/*! @brief Get UART0 frequency
423 * @retval UART0 frequency value.
424 */
425uint32_t CLOCK_GetUartClkFreq(void);
426
427/*! @brief Get UART0 frequency
428 * @retval UART0 frequency value.
429 */
430uint32_t CLOCK_GetUart0ClkFreq(void);
431
432/*! @brief Get UART1 frequency
433 * @retval UART1 frequency value.
434 */
435uint32_t CLOCK_GetUart1ClkFreq(void);
436
437/*! @brief Get UART2 frequency
438 * @retval UART2 frequency value.
439 */
440uint32_t CLOCK_GetUart2ClkFreq(void);
441
442/*! @brief Return Frequency of selected clock
443 * @return Frequency of selected clock
444 */
445uint32_t CLOCK_GetFreq(clock_name_t clockName);
446
447/*! @brief Return System PLL input clock rate
448 * @return System PLL input clock rate
449 */
450uint32_t CLOCK_GetSystemPLLInClockRate(void);
451
452/*! @brief Return Frequency of System PLL
453 * @return Frequency of PLL
454 */
455static inline uint32_t CLOCK_GetSystemPLLFreq(void)
456{
457 return CLOCK_GetSystemPLLInClockRate() * ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK) + 1U);
458}
459
460/*! @brief Get watch dog OSC frequency
461 * @retval watch dog OSC frequency value.
462 */
463static inline uint32_t CLOCK_GetWdtOscFreq(void)
464{
465 return g_Wdt_Osc_Freq;
466}
467
468/*! @brief Get external clock frequency
469 * @retval external clock frequency value.
470 */
471static inline uint32_t CLOCK_GetExtClkFreq(void)
472{
473 return g_Ext_Clk_Freq;
474}
475/* @} */
476
477/*!
478 * @name PLL operations
479 * @{
480 */
481
482/*! @brief System PLL initialize.
483 * @param config System PLL configurations.
484 */
485void CLOCK_InitSystemPll(const clock_sys_pll_t *config);
486
487/*! @brief System PLL Deinitialize.*/
488static inline void CLOCK_DenitSystemPll(void)
489{
490 /* Power off PLL */
491 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSPLL_PD_MASK;
492}
493
494/* @} */
495
496/*!
497 * @name External/internal oscillator clock operations
498 * @{
499 */
500
501/*! @brief Init external CLK IN, select the CLKIN as the external clock source.
502 * @param clkInFreq external clock in frequency.
503 */
504void CLOCK_InitExtClkin(uint32_t clkInFreq);
505
506/*! @brief Init SYS OSC
507 * @param oscFreq oscillator frequency value.
508 */
509void CLOCK_InitSysOsc(uint32_t oscFreq);
510
511/*! @brief XTALIN init function
512 * system oscillator is bypassed, sys_osc_clk is fed driectly from the XTALIN.
513 * @param xtalInFreq XTALIN frequency value
514 * @return Frequency of PLL
515 */
516void CLOCK_InitXtalin(uint32_t xtalInFreq);
517
518/*! @brief Deinit SYS OSC
519 * @param config oscillator configuration.
520 */
521static inline void CLOCK_DeinitSysOsc(void)
522{
523 /* Deinit system osc power */
524 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSOSC_PD_MASK;
525}
526
527/*! @brief Init watch dog OSC
528 * Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the
529 * listed frequency value. The watchdog oscillator is the clock source with the lowest power
530 * consumption. If accurate timing is required, use the FRO or system oscillator.
531 * The frequency of the watchdog oscillator is undefined after reset. The watchdog
532 * oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
533 * using the watchdog oscillator.
534 * Watchdog osc output frequency = wdtOscFreq / wdtOscDiv, should in range 9.3KHZ to 2.3MHZ.
535 * @param wdtOscFreq watch dog analog part output frequency, reference _wdt_analog_output_freq.
536 * @param wdtOscDiv watch dog analog part output frequency divider, shoule be a value >= 2U and multiple of 2
537 */
538void CLOCK_InitWdtOsc(clock_wdt_analog_freq_t wdtOscFreq, uint32_t wdtOscDiv);
539
540/*! @brief Deinit watch dog OSC
541 * @param config oscillator configuration.
542 */
543static inline void CLOCK_DeinitWdtOsc(void)
544{
545 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_WDTOSC_PD_MASK;
546}
547
548/*! @brief Set UARTFRG
549 * @param target UART clock src.
550 */
551bool CLOCK_SetUARTFRGClkFreq(uint32_t freq);
552
553/*! @brief updates the clock source of the CLKOUT
554 */
555void CLOCK_UpdateClkOUTsrc(void);
556
557/*! @brief Set UARTFRGMULT
558 * @deprecated Do not use this function. Refer to CLOCK_SetFRGClkMul().
559 * @param UARTFRGMULT.
560 */
561static inline void CLOCK_SetUARTFRGMULT(uint32_t mul)
562{
563 SYSCON->UARTFRGMULT = SYSCON_UARTFRGMULT_MULT(mul);
564}
565
566/* @} */
567
568#if defined(__cplusplus)
569}
570#endif /* __cplusplus */
571
572/*! @} */
573
574#endif /* _FSL_CLOCK_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_inputmux_connections.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_inputmux_connections.h
new file mode 100644
index 000000000..cc8fca8c9
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_inputmux_connections.h
@@ -0,0 +1,84 @@
1/*
2 * Copyright 2017 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_INPUTMUX_CONNECTIONS_
10#define _FSL_INPUTMUX_CONNECTIONS_
11
12/*******************************************************************************
13 * Definitions
14 ******************************************************************************/
15/* Component ID definition, used by tools. */
16#ifndef FSL_COMPONENT_ID
17#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections"
18#endif
19
20/*!
21 * @addtogroup inputmux_driver
22 * @{
23 */
24
25/*!
26 * @name Input multiplexing connections
27 * @{
28 */
29
30/*! @brief Periphinmux IDs */
31#define DMA_ITRIG_INMUX_ID 0x00U
32#define DMA_OTRIG_PMUX_ID 0x4000U
33#define SCT0_INMUX_ID 0x4020U
34#define PMUX_SHIFT 16U
35
36/*! @brief INPUTMUX connections type */
37typedef enum _inputmux_connection_t
38{
39 /*!< DMA ITRIG INMUX. */
40 kINPUTMUX_AdcASeqaIrqToDma = 0U + (DMA_ITRIG_INMUX_ID << PMUX_SHIFT),
41 kINPUTMUX_AdcBSeqbIrqToDma = 1U + (DMA_ITRIG_INMUX_ID << PMUX_SHIFT),
42 kINPUTMUX_SctDma0ToDma = 2U + (DMA_ITRIG_INMUX_ID << PMUX_SHIFT),
43 kINPUTMUX_SctDma1ToDma = 3U + (DMA_ITRIG_INMUX_ID << PMUX_SHIFT),
44 kINPUTMUX_AcmpOToDma = 4U + (DMA_ITRIG_INMUX_ID << PMUX_SHIFT),
45 kINPUTMUX_PinInt0ToDma = 5U + (DMA_ITRIG_INMUX_ID << PMUX_SHIFT),
46 kINPUTMUX_PinInt1ToDma = 6U + (DMA_ITRIG_INMUX_ID << PMUX_SHIFT),
47 kINPUTMUX_DmaTriggerMux0ToDma = 7U + (DMA_ITRIG_INMUX_ID << PMUX_SHIFT),
48 kINPUTMUX_DmaTriggerMux1ToDma = 8U + (DMA_ITRIG_INMUX_ID << PMUX_SHIFT),
49
50 /*!< DMA INMUX. */
51 kINPUTMUX_DmaChannel0TrigoutToTriginChannels = 0U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
52 kINPUTMUX_DmaChannel1TrigoutToTriginChannels = 1U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
53 kINPUTMUX_DmaChannel2TrigoutToTriginChannels = 2U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
54 kINPUTMUX_DmaChannel3TrigoutToTriginChannels = 3U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
55 kINPUTMUX_DmaChannel4TrigoutToTriginChannels = 4U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
56 kINPUTMUX_DmaChannel5TrigoutToTriginChannels = 5U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
57 kINPUTMUX_DmaChannel6TrigoutToTriginChannels = 6U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
58 kINPUTMUX_DmaChannel7TrigoutToTriginChannels = 7U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
59 kINPUTMUX_DmaChannel8TrigoutToTriginChannels = 8U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
60 kINPUTMUX_DmaChannel9TrigoutToTriginChannels = 9U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
61 kINPUTMUX_DmaChannel10TrigoutToTriginChannels = 10U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
62 kINPUTMUX_DmaChannel11TrigoutToTriginChannels = 11U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
63 kINPUTMUX_DmaChannel12TrigoutToTriginChannels = 12U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
64 kINPUTMUX_DmaChannel13TrigoutToTriginChannels = 13U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
65 kINPUTMUX_DmaChannel14TrigoutToTriginChannels = 14U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
66 kINPUTMUX_DmaChannel15TrigoutToTriginChannels = 15U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
67 kINPUTMUX_DmaChannel16TrigoutToTriginChannels = 16U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
68 kINPUTMUX_DmaChannel17TrigoutToTriginChannels = 17U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
69
70 /*!< SCT INMUX. */
71 kINPUTMUX_SctPin0ToSct0 = 0U + (SCT0_INMUX_ID << PMUX_SHIFT),
72 kINPUTMUX_SctPin1ToSct0 = 1U + (SCT0_INMUX_ID << PMUX_SHIFT),
73 kINPUTMUX_SctPin2ToSct0 = 2U + (SCT0_INMUX_ID << PMUX_SHIFT),
74 kINPUTMUX_SctPin3ToSct0 = 3U + (SCT0_INMUX_ID << PMUX_SHIFT),
75 kINPUTMUX_AdcThcmpIrqToSct0 = 4U + (SCT0_INMUX_ID << PMUX_SHIFT),
76 kINPUTMUX_AcmpOToSct0 = 5U + (SCT0_INMUX_ID << PMUX_SHIFT),
77 kINPUTMUX_ArmTxevToSct0 = 6U + (SCT0_INMUX_ID << PMUX_SHIFT),
78 kINPUTMUX_DebugHaltedToSct0 =7U + (SCT0_INMUX_ID << PMUX_SHIFT),
79
80} inputmux_connection_t;
81
82/*@}*/
83
84#endif /* _FSL_INPUTMUX_CONNECTIONS_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_power.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_power.c
new file mode 100644
index 000000000..8a2de409b
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_power.c
@@ -0,0 +1,163 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2018, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8#include "fsl_power.h"
9/* Component ID definition, used by tools. */
10#ifndef FSL_COMPONENT_ID
11#define FSL_COMPONENT_ID "platform.drivers.power_no_lib"
12#endif
13
14/*******************************************************************************
15 * Code
16 ******************************************************************************/
17/*!
18 * brief API to enter sleep power mode.
19 *
20 * return none
21 */
22void POWER_EnterSleep(void)
23{
24 uint32_t pmsk;
25
26 pmsk = __get_PRIMASK();
27 __disable_irq();
28
29 /* sleep mode */
30 PMU->PCON &= ~PMU_PCON_PM_MASK;
31 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
32 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
33
34 /* Enter powerdown mode */
35 __WFI();
36
37 __set_PRIMASK(pmsk);
38}
39
40/*!
41 * brief API to enter deep sleep power mode.
42 *
43 * param activePart: should be a single or combine value of _power_deep_sleep_active .
44 * return none
45 */
46void POWER_EnterDeepSleep(uint32_t activePart)
47{
48 assert((SYSCON->MAINCLKSEL & SYSCON_MAINCLKSEL_SEL_MASK) == 0U);
49
50 uint32_t pmsk;
51
52 pmsk = __get_PRIMASK();
53 __disable_irq();
54
55 PMU->PCON = (PMU->PCON & (~PMU_PCON_PM_MASK)) | PMU_PCON_PM(kPmu_Deep_Sleep);
56
57 /* remain active during power down mode */
58 SYSCON->PDSLEEPCFG &= ~activePart;
59
60 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
61 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
62
63 /* Enter powerdown mode */
64 __WFI();
65
66 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
67 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
68 __set_PRIMASK(pmsk);
69}
70
71/*!
72 * brief API to enter power down mode.
73 *
74 * param activePart: should be a single or combine value of _power_deep_sleep_active .
75 * return none
76 */
77void POWER_EnterPowerDown(uint32_t activePart)
78{
79 assert((SYSCON->MAINCLKSEL & SYSCON_MAINCLKSEL_SEL_MASK) == 0U);
80
81 uint32_t pmsk;
82
83 pmsk = __get_PRIMASK();
84 __disable_irq();
85
86 PMU->PCON = (PMU->PCON & (~PMU_PCON_PM_MASK)) | PMU_PCON_PM(kPmu_PowerDown);
87
88 /* remain active during power down mode */
89 SYSCON->PDSLEEPCFG &= ~activePart;
90
91 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
92 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
93
94 /* Enter powerdown mode */
95 __WFI();
96
97 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
98 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
99 __set_PRIMASK(pmsk);
100}
101
102/*!
103 * brief API to enter deep power down mode.
104 *
105 * return none
106 */
107void POWER_EnterDeepPowerDownMode(void)
108{
109 uint32_t pmsk;
110
111 pmsk = __get_PRIMASK();
112 __disable_irq();
113
114 /* make sure NODPD is cleared */
115 PMU->PCON = (PMU->PCON & (~(PMU_PCON_PM_MASK | PMU_PCON_NODPD_MASK))) | PMU_PCON_PM(kPmu_Deep_PowerDown);
116
117 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
118 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
119
120 /* Enter powerdown mode */
121 __WFI();
122
123 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
124 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
125 __set_PRIMASK(pmsk);
126}
127
128void EnableDeepSleepIRQ(IRQn_Type interrupt)
129{
130 uint32_t intNumber = (uint32_t)interrupt;
131
132 if(intNumber >= 24u)
133 {
134 /* enable pin interrupt wake up in the STARTERP0 register */
135 SYSCON->STARTERP0 |= 1UL << (intNumber - 24u);
136 }
137 else
138 {
139 /* enable interrupt wake up in the STARTERP1 register */
140 SYSCON->STARTERP1 |= 1UL << intNumber;
141 }
142 /* also enable interrupt at NVIC */
143 (void)EnableIRQ(interrupt);
144}
145
146void DisableDeepSleepIRQ(IRQn_Type interrupt)
147{
148 uint32_t intNumber = (uint32_t)interrupt;
149
150 /* also disable interrupt at NVIC */
151 (void)DisableIRQ(interrupt);
152
153 if(intNumber >= 24u)
154 {
155 /* disable pin interrupt wake up in the STARTERP0 register */
156 SYSCON->STARTERP0 &= ~(1UL << (intNumber - 24u));
157 }
158 else
159 {
160 /* disable interrupt wake up in the STARTERP1 register */
161 SYSCON->STARTERP1 &= ~(1UL << intNumber);
162 }
163}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_power.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_power.h
new file mode 100644
index 000000000..1807d5830
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_power.h
@@ -0,0 +1,386 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2018, 2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8#ifndef _FSL_POWER_H_
9#define _FSL_POWER_H_
10
11#include "fsl_common.h"
12
13/*******************************************************************************
14 * Definitions
15 ******************************************************************************/
16
17/*!
18 * @addtogroup power
19 * @{
20 */
21
22/*! @name Driver version */
23/*@{*/
24/*! @brief power driver version 2.0.4. */
25#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
26/*@}*/
27
28/*! @brief PMU PCON reserved mask, used to clear reserved field which should not write 1*/
29#define PMUC_PCON_RESERVED_MASK ((0xf << 4) | (0x6 << 8) | 0xfffff000u)
30
31#define POWER_EnbaleLPO POWER_EnableLPO
32#define POWER_EnbaleLPOInDeepPowerDownMode POWER_EnableLPOInDeepPowerDownMode
33
34typedef enum pd_bits
35{
36 kPDRUNCFG_PD_IRC_OUT = SYSCON_PDRUNCFG_IRCOUT_PD_MASK,
37 kPDRUNCFG_PD_IRC = SYSCON_PDRUNCFG_IRC_PD_MASK,
38 kPDRUNCFG_PD_FLASH = SYSCON_PDRUNCFG_FLASH_PD_MASK,
39 kPDRUNCFG_PD_BOD = SYSCON_PDRUNCFG_BOD_PD_MASK,
40 kPDRUNCFG_PD_ADC0 = SYSCON_PDRUNCFG_ADC_PD_MASK,
41 kPDRUNCFG_PD_SYSOSC = SYSCON_PDRUNCFG_SYSOSC_PD_MASK,
42 kPDRUNCFG_PD_WDT_OSC = SYSCON_PDRUNCFG_WDTOSC_PD_MASK,
43 kPDRUNCFG_PD_SYSPLL = SYSCON_PDRUNCFG_SYSPLL_PD_MASK,
44 kPDRUNCFG_PD_ACMP = SYSCON_PDRUNCFG_ACMP_MASK,
45
46 /*
47 This enum member has no practical meaning,it is used to avoid MISRA issue,
48 user should not trying to use it.
49 */
50 kPDRUNCFG_ForceUnsigned = (int)0x80000000U,
51} pd_bit_t;
52
53/*! @brief Deep sleep and power down mode wake up configurations */
54enum _power_wakeup
55{
56 kPDAWAKECFG_Wakeup_IRC_OUT = SYSCON_PDAWAKECFG_IRCOUT_PD_MASK,
57 kPDAWAKECFG_Wakeup_IRC = SYSCON_PDAWAKECFG_IRC_PD_MASK,
58 kPDAWAKECFG_Wakeup_FLASH = SYSCON_PDAWAKECFG_FLASH_PD_MASK,
59 kPDAWAKECFG_Wakeup_BOD = SYSCON_PDAWAKECFG_BOD_PD_MASK,
60 kPDAWAKECFG_Wakeup_ADC = SYSCON_PDAWAKECFG_ADC_PD_MASK,
61 kPDAWAKECFG_Wakeup_SYSOSC = SYSCON_PDAWAKECFG_SYSOSC_PD_MASK,
62 kPDAWAKECFG_Wakeup_WDT_OSC = SYSCON_PDAWAKECFG_WDTOSC_PD_MASK,
63 kPDAWAKECFG_Wakeup_SYSPLL = SYSCON_PDAWAKECFG_SYSPLL_PD_MASK,
64 kPDAWAKECFG_Wakeup_ACMP = SYSCON_PDAWAKECFG_ACMP_MASK,
65};
66
67/*! @brief Deep sleep/power down mode active part */
68enum _power_deep_sleep_active
69{
70 kPDSLEEPCFG_DeepSleepBODActive = SYSCON_PDSLEEPCFG_BOD_PD_MASK,
71 kPDSLEEPCFG_DeepSleepWDTOscActive = SYSCON_PDSLEEPCFG_WDTOSC_PD_MASK,
72};
73
74/*! @brief pmu general purpose register index */
75typedef enum _power_gen_reg
76{
77 kPmu_GenReg0 = 0U, /*!< general purpose register0 */
78 kPmu_GenReg1 = 1U, /*!< general purpose register1 */
79 kPmu_GenReg2 = 2U, /*!< general purpose register2 */
80 kPmu_GenReg3 = 3U, /*!< general purpose register3 */
81 kPmu_GenReg4 = 4U, /*!< DPDCTRL bit 31-4 */
82} power_gen_reg_t;
83
84/* Power mode configuration API parameter */
85typedef enum _power_mode_config
86{
87 kPmu_Sleep = 0U,
88 kPmu_Deep_Sleep = 1U,
89 kPmu_PowerDown = 2U,
90 kPmu_Deep_PowerDown = 3U,
91} power_mode_cfg_t;
92
93/*******************************************************************************
94 * API
95 ******************************************************************************/
96
97#ifdef __cplusplus
98extern "C" {
99#endif
100
101/*!
102 * @name SYSCON Power Configuration
103 * @{
104 */
105
106/*!
107 * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
108 *
109 * @param en peripheral for which to enable the PDRUNCFG bit
110 * @return none
111 */
112static inline void POWER_EnablePD(pd_bit_t en)
113{
114 SYSCON->PDRUNCFG |= (uint32_t)en;
115}
116
117/*!
118 * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
119 *
120 * @param en peripheral for which to disable the PDRUNCFG bit
121 * @return none
122 */
123static inline void POWER_DisablePD(pd_bit_t en)
124{
125 SYSCON->PDRUNCFG &= ~(uint32_t)en;
126}
127
128/*!
129 * @brief API to config wakeup configurations for deep sleep mode and power down mode.
130 *
131 * @param mask: wake up configurations for deep sleep mode and power down mode, reference _power_wakeup.
132 * @param powerDown: true is power down the mask part, false is powered part.
133 */
134static inline void POWER_WakeUpConfig(uint32_t mask, bool powerDown)
135{
136 if (powerDown)
137 {
138 SYSCON->PDAWAKECFG |= mask;
139 }
140 else
141 {
142 SYSCON->PDAWAKECFG &= ~mask;
143 }
144}
145
146/*!
147 * @brief API to config active part for deep sleep mode and power down mode.
148 *
149 * @param mask: active part configurations for deep sleep mode and power down mode, reference _power_deep_sleep_active.
150 * @param powerDown: true is power down the mask part, false is powered part.
151 */
152static inline void POWER_DeepSleepConfig(uint32_t mask, bool powerDown)
153{
154 if (powerDown)
155 {
156 SYSCON->PDSLEEPCFG |= mask;
157 }
158 else
159 {
160 SYSCON->PDSLEEPCFG &= ~mask;
161 }
162}
163
164/* @} */
165
166/*!
167 * @name ARM core Power Configuration
168 * @{
169 */
170
171/*!
172 * @brief API to enable deep sleep bit in the ARM Core.
173 *
174 * @return none
175 */
176static inline void POWER_EnableDeepSleep(void)
177{
178 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
179}
180
181/*!
182 * @brief API to disable deep sleep bit in the ARM Core.
183 *
184 * @return none
185 */
186static inline void POWER_DisableDeepSleep(void)
187{
188 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
189}
190
191/* @} */
192
193/*!
194 * @name PMU functionality
195 * @{
196 */
197
198/*!
199 * @brief API to enter sleep power mode.
200 *
201 * @return none
202 */
203void POWER_EnterSleep(void);
204
205/*!
206 * @brief API to enter deep sleep power mode.
207 *
208 * @param activePart: should be a single or combine value of _power_deep_sleep_active .
209 * @return none
210 */
211void POWER_EnterDeepSleep(uint32_t activePart);
212
213/*!
214 * @brief API to enter power down mode.
215 *
216 * @param activePart: should be a single or combine value of _power_deep_sleep_active .
217 * @return none
218 */
219void POWER_EnterPowerDown(uint32_t activePart);
220
221/*!
222 * @brief API to enter deep power down mode.
223 *
224 * @return none
225 */
226void POWER_EnterDeepPowerDownMode(void);
227
228/*!
229 * @brief API to get sleep mode flag.
230 *
231 * @return sleep mode flag: 0 is active mode, 1 is sleep mode entered.
232 */
233static inline uint32_t POWER_GetSleepModeFlag(void)
234{
235 return (PMU->PCON & PMU_PCON_SLEEPFLAG_MASK) >> PMU_PCON_SLEEPFLAG_SHIFT;
236}
237
238/*!
239 * @brief API to clear sleep mode flag.
240 *
241 */
242static inline void POWER_ClrSleepModeFlag(void)
243{
244 PMU->PCON |= PMU_PCON_SLEEPFLAG_MASK;
245}
246
247/*!
248 * @brief API to get deep power down mode flag.
249 *
250 * @return sleep mode flag: 0 not deep power down, 1 is deep power down mode entered.
251 */
252static inline uint32_t POWER_GetDeepPowerDownModeFlag(void)
253{
254 return (PMU->PCON & PMU_PCON_DPDFLAG_MASK) >> PMU_PCON_DPDFLAG_SHIFT;
255}
256
257/*!
258 * @brief API to clear deep power down mode flag.
259 *
260 */
261static inline void POWER_ClrDeepPowerDownModeFlag(void)
262{
263 PMU->PCON |= PMU_PCON_DPDFLAG_MASK;
264}
265
266/*!
267 * @brief API to enable non deep power down mode.
268 *
269 * @param enable: true is enable non deep power down, otherwise disable.
270 */
271static inline void POWER_EnableNonDpd(bool enable)
272{
273 if (enable)
274 {
275 PMU->PCON |= PMU_PCON_NODPD_MASK;
276 }
277 else
278 {
279 PMU->PCON &= ~PMU_PCON_NODPD_MASK;
280 }
281}
282
283/*!
284 * @brief API to enable LPO.
285 *
286 * @param enable: true to enable LPO, false to disable LPO.
287 */
288static inline void POWER_EnableLPO(bool enable)
289{
290 if (enable)
291 {
292 PMU->DPDCTRL |= PMU_DPDCTRL_LPOSCEN_MASK;
293 }
294 else
295 {
296 PMU->DPDCTRL &= ~PMU_DPDCTRL_LPOSCEN_MASK;
297 }
298}
299
300/*!
301 * @brief API to enable LPO in deep power down mode.
302 *
303 * @param enable: true to enable LPO, false to disable LPO.
304 */
305static inline void POWER_EnableLPOInDeepPowerDownMode(bool enable)
306{
307 if (enable)
308 {
309 PMU->DPDCTRL |= PMU_DPDCTRL_LPOSCDPDEN_MASK;
310 }
311 else
312 {
313 PMU->DPDCTRL &= ~PMU_DPDCTRL_LPOSCDPDEN_MASK;
314 }
315}
316
317/*!
318 * @brief API to retore data to general purpose register which can be retain during deep power down mode.
319 * Note the kPMU_GenReg4 can retore 3 byte data only, so the general purpose register can store 19bytes data.
320 * @param index: general purpose data register index.
321 * @param data: data to restore.
322 */
323static inline void POWER_SetRetainData(power_gen_reg_t index, uint32_t data)
324{
325 if (index <= kPmu_GenReg3)
326 {
327 PMU->GPREG[index] = data;
328 }
329 else
330 {
331 /* only 26 bits can store in GPDATA field */
332 PMU->DPDCTRL = (PMU->DPDCTRL & (~PMU_DPDCTRL_GPDATA_MASK)) | PMU_DPDCTRL_GPDATA(data);
333 }
334}
335
336/*!
337 * @brief API to get data from general purpose register which retain during deep power down mode.
338 * Note the kPMU_GenReg4 can retore 3 byte data only, so the general purpose register can store 19bytes data.
339 * @param index: general purpose data register index.
340 * @return data stored in the general purpose register.
341 */
342static inline uint32_t POWER_GetRetainData(power_gen_reg_t index)
343{
344 if (index == kPmu_GenReg4)
345 {
346 return (PMU->DPDCTRL & PMU_DPDCTRL_GPDATA_MASK) >> PMU_DPDCTRL_GPDATA_SHIFT;
347 }
348
349 return PMU->GPREG[index];
350}
351
352/*!
353 * @brief API to enable external clock input for self wake up timer.
354 *
355 * @param enable: true is enable external clock input for self-wake-up timer, otherwise disable.
356 * @param enHysteresis: true is enable Hysteresis for the pin, otherwise disable.
357 */
358static inline void POWER_EnableWktClkIn(bool enable, bool enHysteresis)
359{
360 PMU->DPDCTRL = (PMU->DPDCTRL & (~(PMU_DPDCTRL_WAKEUPCLKHYS_MASK | PMU_DPDCTRL_WAKECLKPAD_DISABLE_MASK))) |
361 PMU_DPDCTRL_WAKECLKPAD_DISABLE(enable) | PMU_DPDCTRL_WAKEUPCLKHYS(enHysteresis);
362}
363
364/*!
365 * @brief API to enable wake up pin for deep power down mode.
366 *
367 * @param enable: true is enable, otherwise disable.
368 * @param enHysteresis: true is enable Hysteresis for the pin, otherwise disable.
369 */
370static inline void POWER_EnableWakeupPinForDeepPowerDown(bool enable, bool enHysteresis)
371{
372 PMU->DPDCTRL = (PMU->DPDCTRL & (~(PMU_DPDCTRL_WAKEUPHYS_MASK | PMU_DPDCTRL_WAKEPAD_DISABLE_MASK))) |
373 PMU_DPDCTRL_WAKEPAD_DISABLE(!enable) | PMU_DPDCTRL_WAKEUPHYS(enHysteresis);
374}
375
376/* @} */
377
378#ifdef __cplusplus
379}
380#endif
381
382/*!
383 * @}
384 */
385
386#endif /* _FSL_POWER_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_reset.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_reset.c
new file mode 100644
index 000000000..e081cbe08
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_reset.c
@@ -0,0 +1,92 @@
1/*
2 * Copyright 2017, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "fsl_reset.h"
10
11/*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14/* Component ID definition, used by tools. */
15#ifndef FSL_COMPONENT_ID
16#define FSL_COMPONENT_ID "platform.drivers.reset"
17#endif
18
19/*******************************************************************************
20 * Variables
21 ******************************************************************************/
22
23/*******************************************************************************
24 * Prototypes
25 ******************************************************************************/
26
27/*!
28* @brief Assert reset to peripheral.
29*
30* Asserts reset signal to specified peripheral module.
31*
32* @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
33* and reset bit position in the reset register.
34*/
35static void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
36
37/*!
38 * @brief Clear reset to peripheral.
39 *
40 * Clears reset signal to specified peripheral module, allows it to operate.
41 *
42 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
43 * and reset bit position in the reset register.
44 */
45static void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
46
47/*******************************************************************************
48 * Code
49 ******************************************************************************/
50
51#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
52 (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
53
54static void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
55{
56 const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
57 const uint32_t bitMask = 1UL << bitPos;
58
59 assert(bitPos < 32UL);
60
61 /* reset register is in SYSCON */
62 /* set bit */
63 SYSCON->PRESETCTRL &= ~bitMask;
64}
65
66static void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
67{
68 const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
69 const uint32_t bitMask = 1UL << bitPos;
70
71 assert(bitPos < 32UL);
72
73 /* reset register is in SYSCON */
74 /* clear bit */
75 SYSCON->PRESETCTRL |= bitMask;
76}
77
78/*!
79 * brief Reset peripheral module.
80 *
81 * Reset peripheral module.
82 *
83 * param peripheral Peripheral to reset. The enum argument contains encoding of reset register
84 * and reset bit position in the reset register.
85 */
86void RESET_PeripheralReset(reset_ip_name_t peripheral)
87{
88 RESET_SetPeripheralReset(peripheral);
89 RESET_ClearPeripheralReset(peripheral);
90}
91
92#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_reset.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_reset.h
new file mode 100644
index 000000000..d92863d9d
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_reset.h
@@ -0,0 +1,140 @@
1/*
2 * Copyright 2017, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_RESET_H_
9#define _FSL_RESET_H_
10
11#include <assert.h>
12#include <stdbool.h>
13#include <stdint.h>
14#include <string.h>
15#include "fsl_device_registers.h"
16
17/*!
18 * @addtogroup reset
19 * @{
20 */
21
22/*******************************************************************************
23 * Definitions
24 ******************************************************************************/
25
26/*! @name Driver version */
27/*@{*/
28/*! @brief reset driver version 2.0.2. */
29#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
30/*@}*/
31
32/*!
33 * @brief Enumeration for peripheral reset control bits
34 *
35 * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
36 */
37typedef enum _SYSCON_RSTn
38{
39 kSPI0_RST_N_SHIFT_RSTn = 0 | 0U, /**< SPI0 reset control. */
40 kSPI1_RST_N_SHIFT_RSTn = 0 | 1U, /**< SPI1 reset control */
41 kUARTFRG_RST_N_SHIFT_RSTn = 0 | 2U, /**< UARTFRG reset control */
42 kUART0_RST_N_SHIFT_RSTn = 0 | 3U, /**< UART0 reset control */
43 kUART1_RST_N_SHIFT_RSTn = 0 | 4U, /**< UART1 reset control */
44 kUART2_RST_N_SHIFT_RSTn = 0 | 5U, /**< UART2 reset control */
45 kI2C0_RST_N_SHIFT_RSTn = 0 | 6U, /**< I2C0 reset control */
46 kMRT_RST_N_SHIFT_RSTn = 0 | 7U, /**< Multi-rate timer(MRT) reset control */
47 kSCT_RST_N_SHIFT_RSTn = 0 | 8U, /**< SCT reset control */
48 kWKT_RST_N_SHIFT_RSTn = 0 | 9U, /**< Self-wake-up timer(WKT) reset control */
49 kGPIO0_RST_N_SHIFT_RSTn = 0 | 10U, /**< GPIO0 reset control */
50 kFLASH_RST_N_SHIFT_RSTn = 0 | 11U, /**< Flash controller reset control */
51 kACMP_RST_N_SHIFT_RSTn = 0 | 12U, /**< Analog comparator reset control */
52 kCRC_RST_SHIFT_RSTn = 0 | 13U, /**< CRC reset control */
53 kI2C1_RST_N_SHIFT_RSTn = 0 | 14U, /**< I2C1 reset control */
54 kI2C2_RST_N_SHIFT_RSTn = 0 | 15U, /**< I2C2 reset control */
55 kI2C3_RST_N_SHIFT_RSTn = 0 | 16U, /**< I2C3 reset control */
56 kADC_RST_N_SHIFT_RSTn = 0 | 24U, /**< ADC reset control */
57 kDMA_RST_N_SHIFT_RSTn = 0 | 29U, /**< DMA reset control */
58
59} SYSCON_RSTn_t;
60
61/** Array initializers with peripheral reset bits **/
62#define FLASH_RSTS_N \
63 { \
64 kFLASH_RST_N_SHIFT_RSTn \
65 } /* Reset bits for Flash peripheral */
66#define I2C_RSTS_N \
67 { \
68 kI2C0_RST_N_SHIFT_RSTn, kI2C1_RST_N_SHIFT_RSTn, kI2C2_RST_N_SHIFT_RSTn, kI2C3_RST_N_SHIFT_RSTn \
69 } /* Reset bits for I2C peripheral */
70#define GPIO_RSTS_N \
71 { \
72 kGPIO0_RST_N_SHIFT_RSTn \
73 } /* Reset bits for GPIO peripheral */
74#define SWM_RSTS_N \
75 { \
76 kSWM_RST_N_SHIFT_RSTn \
77 } /* Reset bits for SWM peripheral */
78#define SCT_RSTS_N \
79 { \
80 kSCT_RST_N_SHIFT_RSTn \
81 } /* Reset bits for SCT peripheral */
82#define WKT_RSTS_N \
83 { \
84 kWKT_RST_N_SHIFT_RSTn \
85 } /* Reset bits for WKT peripheral */
86#define MRT_RSTS_N \
87 { \
88 kMRT_RST_N_SHIFT_RSTn \
89 } /* Reset bits for MRT peripheral */
90#define SPI_RSTS_N \
91 { \
92 kSPI0_RST_N_SHIFT_RSTn, kSPI1_RST_N_SHIFT_RSTn \
93 } /* Reset bits for SPI peripheral */
94#define UART_RSTS_N \
95 { \
96 kUART0_RST_N_SHIFT_RSTn, kUART1_RST_N_SHIFT_RSTn, kUART2_RST_N_SHIFT_RSTn \
97 } /* Reset bits for UART peripheral */
98#define ACMP_RSTS_N \
99 { \
100 kACMP_RST_N_SHIFT_RSTn \
101 } /* Reset bits for ACMP peripheral */
102#define ADC_RSTS_N \
103 { \
104 kADC_RST_N_SHIFT_RSTn \
105 } /* Reset bits for ADC peripheral */
106#define DAC_RSTS_N \
107 { \
108 kDAC0_RST_N_SHIFT_RSTn, kDAC1_RST_N_SHIFT_RSTn \
109 } /* Reset bits for DAC peripheral */
110#define DMA_RSTS_N \
111 { \
112 kDMA_RST_N_SHIFT_RSTn \
113 } /* Reset bits for DMA peripheral */
114
115typedef SYSCON_RSTn_t reset_ip_name_t;
116
117/*******************************************************************************
118 * API
119 ******************************************************************************/
120#if defined(__cplusplus)
121extern "C" {
122#endif
123
124/*!
125 * @brief Reset peripheral module.
126 *
127 * Reset peripheral module.
128 *
129 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
130 * and reset bit position in the reset register.
131 */
132void RESET_PeripheralReset(reset_ip_name_t peripheral);
133
134#if defined(__cplusplus)
135}
136#endif
137
138/*! @} */
139
140#endif /* _FSL_RESET_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_swm_connections.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_swm_connections.h
new file mode 100644
index 000000000..4194d45c5
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_swm_connections.h
@@ -0,0 +1,134 @@
1/*
2 * Copyright 2017 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_SWM_CONNECTIONS_
10#define _FSL_SWM_CONNECTIONS_
11
12#include "fsl_common.h"
13
14/*******************************************************************************
15 * Definitions
16 ******************************************************************************/
17/* Component ID definition, used by tools. */
18#ifndef FSL_COMPONENT_ID
19#define FSL_COMPONENT_ID "platform.drivers.swm_connections"
20#endif
21
22/*!
23 * @addtogroup swm
24 * @{
25 */
26
27/*!
28 * @name swm connections
29 * @{
30 */
31
32/*! @brief SWM port_pin number */
33typedef enum _swm_port_pin_type_t
34{
35 kSWM_PortPin_P0_0 = 0U, /*!< port_pin number P0_0. */
36 kSWM_PortPin_P0_1 = 1U, /*!< port_pin number P0_1. */
37 kSWM_PortPin_P0_2 = 2U, /*!< port_pin number P0_2. */
38 kSWM_PortPin_P0_3 = 3U, /*!< port_pin number P0_3. */
39 kSWM_PortPin_P0_4 = 4U, /*!< port_pin number P0_4. */
40 kSWM_PortPin_P0_5 = 5U, /*!< port_pin number P0_5. */
41 kSWM_PortPin_P0_6 = 6U, /*!< port_pin number P0_6. */
42 kSWM_PortPin_P0_7 = 7U, /*!< port_pin number P0_7. */
43 kSWM_PortPin_P0_8 = 8U, /*!< port_pin number P0_8. */
44 kSWM_PortPin_P0_9 = 9U, /*!< port_pin number P0_9. */
45 kSWM_PortPin_P0_10 = 10U, /*!< port_pin number P0_10. */
46 kSWM_PortPin_P0_11 = 11U, /*!< port_pin number P0_11. */
47 kSWM_PortPin_P0_12 = 12U, /*!< port_pin number P0_12. */
48 kSWM_PortPin_P0_13 = 13U, /*!< port_pin number P0_13. */
49 kSWM_PortPin_P0_14 = 14U, /*!< port_pin number P0_14. */
50 kSWM_PortPin_P0_15 = 15U, /*!< port_pin number P0_15. */
51 kSWM_PortPin_P0_16 = 16U, /*!< port_pin number P0_16. */
52 kSWM_PortPin_P0_17 = 17U, /*!< port_pin number P0_17. */
53 kSWM_PortPin_P0_18 = 18U, /*!< port_pin number P0_18. */
54 kSWM_PortPin_P0_19 = 19U, /*!< port_pin number P0_19. */
55 kSWM_PortPin_P0_20 = 20U, /*!< port_pin number P0_20. */
56 kSWM_PortPin_P0_21 = 21U, /*!< port_pin number P0_21. */
57 kSWM_PortPin_P0_22 = 22U, /*!< port_pin number P0_22. */
58 kSWM_PortPin_P0_23 = 23U, /*!< port_pin number P0_23. */
59 kSWM_PortPin_P0_24 = 24U, /*!< port_pin number P0_24. */
60 kSWM_PortPin_P0_25 = 25U, /*!< port_pin number P0_25. */
61 kSWM_PortPin_P0_26 = 26U, /*!< port_pin number P0_26. */
62 kSWM_PortPin_P0_27 = 27U, /*!< port_pin number P0_27. */
63 kSWM_PortPin_P0_28 = 28U, /*!< port_pin number P0_28. */
64 kSWM_PortPin_Reset = 0xffU /*!< port_pin reset number. */
65} swm_port_pin_type_t;
66
67/*! @brief SWM movable selection */
68typedef enum _swm_select_movable_t
69{
70 kSWM_USART0_TXD = 0U, /*!< Movable function as USART0_TXD. */
71 kSWM_USART0_RXD = 1U, /*!< Movable function as USART0_RXD. */
72 kSWM_USART0_RTS = 2U, /*!< Movable function as USART0_RTS. */
73 kSWM_USART0_CTS = 3U, /*!< Movable function as USART0_CTS. */
74 kSWM_USART0_SCLK = 4U, /*!< Movable function as USART0_SCLK. */
75 kSWM_SPI0_SCK = 15U, /*!< Movable function as SPI0_SCK. */
76 kSWM_SPI0_MOSI = 16U, /*!< Movable function as SPI0_MOSI. */
77 kSWM_SPI0_MISO = 17U, /*!< Movable function as SPI0_MISO. */
78 kSWM_SPI0_SSEL0 = 18U, /*!< Movable function as SPI0_SSEL0. */
79 kSWM_SPI0_SSEL1 = 19U, /*!< Movable function as SPI0_SSEL1. */
80 kSWM_SPI0_SSEL2 = 20U, /*!< Movable function as SPI0_SSEL2. */
81 kSWM_SPI0_SSEL3 = 21U, /*!< Movable function as SPI0_SSEL3. */
82 kSWM_SPI1_SCK = 22U, /*!< Movable function as SPI1_SCK. */
83 kSWM_SPI1_MOSI = 23U, /*!< Movable function as SPI1_MOSI. */
84 kSWM_SPI1_MISO = 24U, /*!< Movable function as SPI1_MISO. */
85 kSWM_SPI1_SSEL0 = 25U, /*!< Movable function as SPI1_SSEL0. */
86 kSWM_SPI1_SSEL1 = 26U, /*!< Movable function as SPI1_SSEL1. */
87 kSWM_SCT_PIN0 = 27U, /*!< Movable function as SCT_PIN0. */
88 kSWM_SCT_PIN1 = 28U, /*!< Movable function as SCT_PIN1. */
89 kSWM_SCT_PIN2 = 29U, /*!< Movable function as SCT_PIN2. */
90 kSWM_SCT_PIN3 = 30U, /*!< Movable function as SCT_PIN3. */
91 kSWM_SCT_OUT0 = 31U, /*!< Movable function as SCT_OUT0. */
92 kSWM_SCT_OUT1 = 32U, /*!< Movable function as SCT_OUT1. */
93 kSWM_SCT_OUT2 = 33U, /*!< Movable function as SCT_OUT2. */
94 kSWM_SCT_OUT3 = 34U, /*!< Movable function as SCT_OUT3. */
95 kSWM_SCT_OUT4 = 35U, /*!< Movable function as SCT_OUT4. */
96 kSWM_SCT_OUT5 = 36U, /*!< Movable function as SCT_OUT5. */
97 kSWM_ADC_PINTRIG0 = 43U, /*!< Movable function as PINTRIG0. */
98 kSWM_ADC_PINTRIG1 = 44U, /*!< Movable function as PINTRIG1. */
99 kSWM_CLKOUT = 46U, /*!< Movable function as CLKOUT. */
100 kSWM_GPIO_INT_BMAT = 47U, /*!< Movable function as GPIO_INT_BMAT. */
101
102 kSWM_MOVABLE_NUM_FUNCS = 48U, /*!< Movable function number. */
103} swm_select_movable_t;
104
105/*! @brief SWM fixed pin selection */
106typedef enum _swm_select_fixed_pin_t
107{
108 kSWM_SWCLK = SWM_PINENABLE0_SWCLK_MASK, /*!< Fixed-pin function as SWCLK. */
109 kSWM_SWDIO = SWM_PINENABLE0_SWDIO_MASK, /*!< Fixed-pin function as SWDIO. */
110 kSWM_XTALIN = SWM_PINENABLE0_XTALIN_MASK, /*!< Fixed-pin function as XTALIN. */
111 kSWM_XTALOUT = SWM_PINENABLE0_XTALOUT_MASK, /*!< Fixed-pin function as XTALOUT. */
112 kSWM_RESETN = SWM_PINENABLE0_RESETN_MASK, /*!< Fixed-pin function as RESETN. */
113 kSWM_CLKIN = SWM_PINENABLE0_CLKIN_MASK, /*!< Fixed-pin function as CLKIN. */
114 kSWM_I2C0_SDA = SWM_PINENABLE0_I2C0_SDA_MASK, /*!< Fixed-pin function as I2C0_SDA. */
115 kSWM_I2C0_SCL = SWM_PINENABLE0_I2C0_SCL_MASK, /*!< Fixed-pin function as I2C0_SCL. */
116 kSWM_ADC_CHN0 = SWM_PINENABLE0_ADC_0_MASK, /*!< Fixed-pin function as ADC_CHN0. */
117 kSWM_ADC_CHN1 = SWM_PINENABLE0_ADC_1_MASK, /*!< Fixed-pin function as ADC_CHN1. */
118 kSWM_ADC_CHN2 = SWM_PINENABLE0_ADC_2_MASK, /*!< Fixed-pin function as ADC_CHN2. */
119 kSWM_ADC_CHN3 = SWM_PINENABLE0_ADC_3_MASK, /*!< Fixed-pin function as ADC_CHN3. */
120 kSWM_ADC_CHN4 = SWM_PINENABLE0_ADC_4_MASK, /*!< Fixed-pin function as ADC_CHN4. */
121 kSWM_ADC_CHN5 = SWM_PINENABLE0_ADC_5_MASK, /*!< Fixed-pin function as ADC_CHN5. */
122 kSWM_ADC_CHN6 = SWM_PINENABLE0_ADC_6_MASK, /*!< Fixed-pin function as ADC_CHN6. */
123 kSWM_ADC_CHN7 = SWM_PINENABLE0_ADC_7_MASK, /*!< Fixed-pin function as ADC_CHN7. */
124 kSWM_ADC_CHN8 = SWM_PINENABLE0_ADC_8_MASK, /*!< Fixed-pin function as ADC_CHN8. */
125 kSWM_ADC_CHN9 = SWM_PINENABLE0_ADC_9_MASK, /*!< Fixed-pin function as ADC_CHN9. */
126 kSWM_ADC_CHN10 = SWM_PINENABLE0_ADC_10_MASK, /*!< Fixed-pin function as ADC_CHN10. */
127 kSWM_ADC_CHN11 = SWM_PINENABLE0_ADC_11_MASK, /*!< Fixed-pin function as ADC_CHN11. */
128
129 kSWM_FIXEDPIN_NUM_FUNCS = 0x80000041U, /*!< Fixed-pin function number. */
130} swm_select_fixed_pin_t;
131
132/*@}*/
133
134#endif /* _FSL_INPUTMUX_CONNECTIONS_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_syscon_connections.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_syscon_connections.h
new file mode 100644
index 000000000..85324abf6
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/drivers/fsl_syscon_connections.h
@@ -0,0 +1,73 @@
1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_SYSCON_CONNECTIONS_
10#define _FSL_SYSCON_CONNECTIONS_
11
12#include "fsl_common.h"
13
14/*******************************************************************************
15 * Definitions
16 ******************************************************************************/
17/* Component ID definition, used by tools. */
18#ifndef FSL_COMPONENT_ID
19#define FSL_COMPONENT_ID "platform.drivers.syscon_connections"
20#endif
21
22/*!
23 * @addtogroup syscon
24 * @{
25 */
26
27/*!
28 * @name Syscon multiplexing connections
29 * @{
30 */
31
32/*! @brief Periphinmux IDs */
33#define PINTSEL_ID 0x178U
34#define SYSCON_SHIFT 20U
35
36/*! @brief SYSCON connections type */
37typedef enum _syscon_connection_t
38{
39 /*!< Pin Interrupt. */
40 kSYSCON_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_ID << SYSCON_SHIFT),
41 kSYSCON_GpioPort0Pin1ToPintsel = 1U + (PINTSEL_ID << SYSCON_SHIFT),
42 kSYSCON_GpioPort0Pin2ToPintsel = 2U + (PINTSEL_ID << SYSCON_SHIFT),
43 kSYSCON_GpioPort0Pin3ToPintsel = 3U + (PINTSEL_ID << SYSCON_SHIFT),
44 kSYSCON_GpioPort0Pin4ToPintsel = 4U + (PINTSEL_ID << SYSCON_SHIFT),
45 kSYSCON_GpioPort0Pin5ToPintsel = 5U + (PINTSEL_ID << SYSCON_SHIFT),
46 kSYSCON_GpioPort0Pin6ToPintsel = 6U + (PINTSEL_ID << SYSCON_SHIFT),
47 kSYSCON_GpioPort0Pin7ToPintsel = 7U + (PINTSEL_ID << SYSCON_SHIFT),
48 kSYSCON_GpioPort0Pin8ToPintsel = 8U + (PINTSEL_ID << SYSCON_SHIFT),
49 kSYSCON_GpioPort0Pin9ToPintsel = 9U + (PINTSEL_ID << SYSCON_SHIFT),
50 kSYSCON_GpioPort0Pin10ToPintsel = 10U + (PINTSEL_ID << SYSCON_SHIFT),
51 kSYSCON_GpioPort0Pin11ToPintsel = 11U + (PINTSEL_ID << SYSCON_SHIFT),
52 kSYSCON_GpioPort0Pin12ToPintsel = 12U + (PINTSEL_ID << SYSCON_SHIFT),
53 kSYSCON_GpioPort0Pin13ToPintsel = 13U + (PINTSEL_ID << SYSCON_SHIFT),
54 kSYSCON_GpioPort0Pin14ToPintsel = 14U + (PINTSEL_ID << SYSCON_SHIFT),
55 kSYSCON_GpioPort0Pin15ToPintsel = 15U + (PINTSEL_ID << SYSCON_SHIFT),
56 kSYSCON_GpioPort0Pin16ToPintsel = 16U + (PINTSEL_ID << SYSCON_SHIFT),
57 kSYSCON_GpioPort0Pin17ToPintsel = 17U + (PINTSEL_ID << SYSCON_SHIFT),
58 kSYSCON_GpioPort0Pin18ToPintsel = 18U + (PINTSEL_ID << SYSCON_SHIFT),
59 kSYSCON_GpioPort0Pin19ToPintsel = 19U + (PINTSEL_ID << SYSCON_SHIFT),
60 kSYSCON_GpioPort0Pin20ToPintsel = 20U + (PINTSEL_ID << SYSCON_SHIFT),
61 kSYSCON_GpioPort0Pin21ToPintsel = 21U + (PINTSEL_ID << SYSCON_SHIFT),
62 kSYSCON_GpioPort0Pin22ToPintsel = 22U + (PINTSEL_ID << SYSCON_SHIFT),
63 kSYSCON_GpioPort0Pin23ToPintsel = 23U + (PINTSEL_ID << SYSCON_SHIFT),
64 kSYSCON_GpioPort0Pin24ToPintsel = 24U + (PINTSEL_ID << SYSCON_SHIFT),
65 kSYSCON_GpioPort0Pin25ToPintsel = 25U + (PINTSEL_ID << SYSCON_SHIFT),
66 kSYSCON_GpioPort0Pin26ToPintsel = 26U + (PINTSEL_ID << SYSCON_SHIFT),
67 kSYSCON_GpioPort0Pin27ToPintsel = 27U + (PINTSEL_ID << SYSCON_SHIFT),
68 kSYSCON_GpioPort0Pin28ToPintsel = 28U + (PINTSEL_ID << SYSCON_SHIFT),
69} syscon_connection_t;
70
71/*@}*/
72
73#endif /* _FSL_SYSCON_CONNECTIONS_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 14:16:20 +0100