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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/system_LPC832.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC832/system_LPC832.c
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1/*
2** ###################################################################
3** Processor: LPC832M101FDH20
4** Compilers: GNU C Compiler
5** IAR ANSI C/C++ Compiler for ARM
6** Keil ARM C/C++ Compiler
7** MCUXpresso Compiler
8**
9** Reference manual: LPC83x User manual Rev.1.1 5 October 2016
10** Version: rev. 1.1, 2018-02-25
11** Build: b201015
12**
13** Abstract:
14** Provides a system configuration function and a global variable that
15** contains the system frequency. It configures the device and initializes
16** the oscillator (PLL) that is part of the microcontroller device.
17**
18** Copyright 2016 Freescale Semiconductor, Inc.
19** Copyright 2016-2020 NXP
20** All rights reserved.
21**
22** SPDX-License-Identifier: BSD-3-Clause
23**
24** http: www.nxp.com
25** mail: [email protected]
26**
27** Revisions:
28** - rev. 1.0 (2018-02-09)
29** Initial version.
30** - rev. 1.1 (2018-02-25)
31** Update some registers according to UM rev 1.2
32**
33** ###################################################################
34*/
35
36/*!
37 * @file LPC832
38 * @version 1.1
39 * @date 2018-02-25
40 * @brief Device specific configuration file for LPC832 (implementation file)
41 *
42 * Provides a system configuration function and a global variable that contains
43 * the system frequency. It configures the device and initializes the oscillator
44 * (PLL) that is part of the microcontroller device.
45 */
46
47#include <stdint.h>
48#include "fsl_device_registers.h"
49
50/* get system pll input freq */
51static uint32_t CLOCK_GetSystemPLLInClkRate(void)
52{
53 uint32_t freq = 0U;
54
55 switch ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK))
56 {
57 /* source from external clock in */
58 case 0x00U:
59 freq = CLK_IRC_12MHZ;
60 break;
61 /* source from the IRC clock */
62 case 0x01U:
63 freq = CLK_OSC_IN;
64 break;
65 /* source from external clock clock */
66 case 0x03U:
67 freq = EXT_CLK_IN;
68 break;
69 default:
70 /* default source from the IRC clock */
71 freq = CLK_IRC_12MHZ;
72 break;
73 }
74
75 return freq;
76}
77
78/* get system pll output freq*/
79static uint32_t Clock_GetPLLFreq(uint32_t PLLReg, uint32_t inputRate)
80{
81 uint32_t m_val = ((PLLReg & 0x1FU) + 1U);
82
83 return (inputRate * m_val);
84}
85
86
87
88/* ----------------------------------------------------------------------------
89 -- Core clock
90 ---------------------------------------------------------------------------- */
91
92uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
93
94/* ----------------------------------------------------------------------------
95 -- SystemInit()
96 ---------------------------------------------------------------------------- */
97
98void SystemInit (void) {
99
100#if defined(__MCUXPRESSO)
101 extern void(*const g_pfnVectors[]) (void);
102 SCB->VTOR = (uint32_t) &g_pfnVectors;
103#else
104 extern void *__Vectors;
105 SCB->VTOR = (uint32_t) &__Vectors;
106#endif
107 SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
108 SystemInitHook();
109}
110
111/* ----------------------------------------------------------------------------
112 -- SystemCoreClockUpdate()
113 ---------------------------------------------------------------------------- */
114
115void SystemCoreClockUpdate (void) {
116 uint32_t wdt_osc = 0U;
117 uint32_t irc_clk = 12000000U;
118
119 switch ((SYSCON->WDTOSCCTRL >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) & 0x0FU) {
120 case 0U: wdt_osc = 0U; break;
121 case 1U: wdt_osc = 600000U; break;
122 case 2U: wdt_osc = 1050000U; break;
123 case 3U: wdt_osc = 1400000U; break;
124 case 4U: wdt_osc = 1750000U; break;
125 case 5U: wdt_osc = 2100000U; break;
126 case 6U: wdt_osc = 2400000U; break;
127 case 7U: wdt_osc = 2700000U; break;
128 case 8U: wdt_osc = 3000000U; break;
129 case 9U: wdt_osc = 3250000U; break;
130 case 10U: wdt_osc = 3500000U; break;
131 case 11U: wdt_osc = 3750000U; break;
132 case 12U: wdt_osc = 4000000U; break;
133 case 13U: wdt_osc = 4200000U; break;
134 case 14U: wdt_osc = 4400000U; break;
135 case 15U: wdt_osc = 4600000U; break;
136 default: wdt_osc = 0U; break;
137 }
138 wdt_osc /= (((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1U) << 1U);
139
140 switch (SYSCON->MAINCLKSEL & SYSCON_MAINCLKSEL_SEL_MASK)
141 {
142 case 0U: /* IRC */
143 SystemCoreClock = irc_clk;
144 break;
145 case 1U: /* System PLL input */
146 switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) {
147 case 0U: /* IRC */
148 SystemCoreClock = irc_clk;
149 break;
150 case 1U: /* System oscillator */
151 SystemCoreClock = CLK_OSC_IN;
152 break;
153 case 3U: /* CLKIN */
154 SystemCoreClock = EXT_CLK_IN;
155 break;
156 default:
157 SystemCoreClock = irc_clk; /* default is IRC */
158 break;
159 }
160 break;
161 case 2U: /* watchdog oscillator */
162 SystemCoreClock = wdt_osc;
163 break;
164 case 3U: /* System PLL */
165 SystemCoreClock = Clock_GetPLLFreq((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK), CLOCK_GetSystemPLLInClkRate());
166 break;
167 default:
168 SystemCoreClock = 0U;
169 break;
170 }
171
172 SystemCoreClock /= SYSCON->SYSAHBCLKDIV;
173}
174
175/* ----------------------------------------------------------------------------
176 -- SystemInitHook()
177 ---------------------------------------------------------------------------- */
178
179__attribute__ ((weak)) void SystemInitHook (void) {
180 /* Void implementation of the weak function. */
181}
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