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1/*
2** ###################################################################
3** Processors: LPC845M301JBD48
4** LPC845M301JBD64
5** LPC845M301JHI33
6** LPC845M301JHI48
7**
8** Compilers: GNU C Compiler
9** IAR ANSI C/C++ Compiler for ARM
10** Keil ARM C/C++ Compiler
11** MCUXpresso Compiler
12**
13** Reference manual: LPC84x User manual Rev.1.6 8 Dec 2017
14** Version: rev. 1.2, 2017-06-08
15** Build: b201029
16**
17** Abstract:
18** CMSIS Peripheral Access Layer for LPC845
19**
20** Copyright 1997-2016 Freescale Semiconductor, Inc.
21** Copyright 2016-2020 NXP
22** All rights reserved.
23**
24** SPDX-License-Identifier: BSD-3-Clause
25**
26** http: www.nxp.com
27** mail: [email protected]
28**
29** Revisions:
30** - rev. 1.0 (2016-08-12)
31** Initial version.
32** - rev. 1.1 (2016-11-25)
33** Update CANFD and Classic CAN register.
34** Add MAC TIMERSTAMP registers.
35** - rev. 1.2 (2017-06-08)
36** Remove RTC_CTRL_RTC_OSC_BYPASS.
37** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
38** Remove RESET and HALT from SYSCON_AHBCLKDIV.
39**
40** ###################################################################
41*/
42
43/*!
44 * @file LPC845.h
45 * @version 1.2
46 * @date 2017-06-08
47 * @brief CMSIS Peripheral Access Layer for LPC845
48 *
49 * CMSIS Peripheral Access Layer for LPC845
50 */
51
52#ifndef _LPC845_H_
53#define _LPC845_H_ /**< Symbol preventing repeated inclusion */
54
55/** Memory map major version (memory maps with equal major version number are
56 * compatible) */
57#define MCU_MEM_MAP_VERSION 0x0100U
58/** Memory map minor version */
59#define MCU_MEM_MAP_VERSION_MINOR 0x0002U
60
61
62/* ----------------------------------------------------------------------------
63 -- Interrupt vector numbers
64 ---------------------------------------------------------------------------- */
65
66/*!
67 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
68 * @{
69 */
70
71/** Interrupt Number Definitions */
72#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
73
74typedef enum IRQn {
75 /* Auxiliary constants */
76 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
77
78 /* Core interrupts */
79 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
80 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
81 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
82 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
83 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
84
85 /* Device specific interrupts */
86 SPI0_IRQn = 0, /**< SPI0 interrupt */
87 SPI1_IRQn = 1, /**< SPI1 interrupt */
88 DAC0_IRQn = 2, /**< DAC0 interrupt */
89 USART0_IRQn = 3, /**< USART0 interrupt */
90 USART1_IRQn = 4, /**< USART1 interrupt */
91 USART2_IRQn = 5, /**< USART2 interrupt */
92 Reserved22_IRQn = 6, /**< Reserved interrupt */
93 I2C1_IRQn = 7, /**< I2C1 interrupt */
94 I2C0_IRQn = 8, /**< I2C0 interrupt */
95 SCT0_IRQn = 9, /**< State configurable timer interrupt */
96 MRT0_IRQn = 10, /**< Multi-rate timer interrupt */
97 CMP_CAPT_IRQn = 11, /**< Analog comparator interrupt or Capacitive Touch interrupt */
98 WDT_IRQn = 12, /**< Windowed watchdog timer interrupt */
99 BOD_IRQn = 13, /**< BOD interrupts */
100 FLASH_IRQn = 14, /**< flash interrupt */
101 WKT_IRQn = 15, /**< Self-wake-up timer interrupt */
102 ADC0_SEQA_IRQn = 16, /**< ADC0 sequence A completion. */
103 ADC0_SEQB_IRQn = 17, /**< ADC0 sequence B completion. */
104 ADC0_THCMP_IRQn = 18, /**< ADC0 threshold compare and error. */
105 ADC0_OVR_IRQn = 19, /**< ADC0 overrun */
106 DMA0_IRQn = 20, /**< DMA0 interrupt */
107 I2C2_IRQn = 21, /**< I2C2 interrupt */
108 I2C3_IRQn = 22, /**< I2C3 interrupt */
109 CTIMER0_IRQn = 23, /**< Timer interrupt */
110 PIN_INT0_IRQn = 24, /**< Pin interrupt 0 or pattern match engine slice 0 interrupt */
111 PIN_INT1_IRQn = 25, /**< Pin interrupt 1 or pattern match engine slice 1 interrupt */
112 PIN_INT2_IRQn = 26, /**< Pin interrupt 2 or pattern match engine slice 2 interrupt */
113 PIN_INT3_IRQn = 27, /**< Pin interrupt 3 or pattern match engine slice 3 interrupt */
114 PIN_INT4_IRQn = 28, /**< Pin interrupt 4 or pattern match engine slice 4 interrupt */
115 PIN_INT5_DAC1_IRQn = 29, /**< Pin interrupt 5 or pattern match engine slice 5 interrupt or DAC1 interrupt */
116 PIN_INT6_USART3_IRQn = 30, /**< Pin interrupt 6 or pattern match engine slice 6 interrupt or UART3 interrupt */
117 PIN_INT7_USART4_IRQn = 31 /**< Pin interrupt 7 or pattern match engine slice 7 interrupt or UART4 interrupt */
118} IRQn_Type;
119
120/*!
121 * @}
122 */ /* end of group Interrupt_vector_numbers */
123
124
125/* ----------------------------------------------------------------------------
126 -- Cortex M0 Core Configuration
127 ---------------------------------------------------------------------------- */
128
129/*!
130 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
131 * @{
132 */
133
134#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
135#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
136#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */
137#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
138#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
139
140#include "core_cm0plus.h" /* Core Peripheral Access Layer */
141#include "system_LPC845.h" /* Device specific configuration file */
142
143/*!
144 * @}
145 */ /* end of group Cortex_Core_Configuration */
146
147
148/* ----------------------------------------------------------------------------
149 -- Mapping Information
150 ---------------------------------------------------------------------------- */
151
152/*!
153 * @addtogroup Mapping_Information Mapping Information
154 * @{
155 */
156
157/** Mapping Information */
158/*!
159 * @addtogroup dma_request
160 * @{
161 */
162
163/*******************************************************************************
164 * Definitions
165 ******************************************************************************/
166
167/*!
168 * @brief Structure for the DMA hardware request
169 *
170 * Defines the structure for the DMA hardware request collections. The user can configure the
171 * hardware request to trigger the DMA transfer accordingly. The index
172 * of the hardware request varies according to the to SoC.
173 */
174typedef enum _dma_request_source
175{
176 kDmaRequestUSART0_RX_DMA = 0U, /**< USART0 RX DMA */
177 kDmaRequestUSART0_TX_DMA = 1U, /**< USART0 TX DMA */
178 kDmaRequestUSART1_RX_DMA = 2U, /**< USART1 RX DMA */
179 kDmaRequestUSART1_TX_DMA = 3U, /**< USART1 TX DMA */
180 kDmaRequestUSART2_RX_DMA = 4U, /**< USART2 RX DMA */
181 kDmaRequestUSART2_TX_DMA = 5U, /**< USART2 TX DMA */
182 kDmaRequestUSART3_RX_DMA = 6U, /**< USART3 RX DMA */
183 kDmaRequestUSART3_TX_DMA = 7U, /**< USART3 TX DMA */
184 kDmaRequestUSART4_RX_DMA = 8U, /**< USART4 RX DMA */
185 kDmaRequestUSART4_TX_DMA = 9U, /**< USART4 TX DMA */
186 kDmaRequestSPI0_RX_DMA = 10U, /**< SPI0 RX DMA */
187 kDmaRequestSPI0_TX_DMA = 11U, /**< SPI0 TX DMA */
188 kDmaRequestSPI1_RX_DMA = 12U, /**< SPI1 RX DMA */
189 kDmaRequestSPI1_TX_DMA = 13U, /**< SPI1 TX DMA */
190 kDmaRequestI2C0_SLV_DMA = 14U, /**< I2C0 SLAVE DMA */
191 kDmaRequestI2C0_MST_DMA = 15U, /**< I2C0 MASTER DMA */
192 kDmaRequestI2C1_SLV_DMA = 16U, /**< I2C1 SLAVE DMA */
193 kDmaRequestI2C1_MST_DMA = 17U, /**< I2C1 MASTER DMA */
194 kDmaRequestI2C2_SLV_DMA = 18U, /**< I2C2 SLAVE DMA */
195 kDmaRequestI2C2_MST_DMA = 19U, /**< I2C2 MASTER DMA */
196 kDmaRequestI2C3_SLV_DMA = 20U, /**< I2C3 SLAVE DMA */
197 kDmaRequestI2C3_MST_DMA = 21U, /**< I2C3 MASTER DMA */
198 kDmaRequestDAC0_DMAREQ = 22U, /**< DAC0 DMA REQUEST */
199 kDmaRequestDAC1_DMAREQ = 23U, /**< DAC1 DMA REQUEST */
200 kDmaRequestCAPT_DMA = 24U, /**< CAPT DMA */
201} dma_request_source_t;
202
203/* @} */
204
205
206/*!
207 * @}
208 */ /* end of group Mapping_Information */
209
210
211/* ----------------------------------------------------------------------------
212 -- Device Peripheral Access Layer
213 ---------------------------------------------------------------------------- */
214
215/*!
216 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
217 * @{
218 */
219
220
221/*
222** Start of section using anonymous unions
223*/
224
225#if defined(__ARMCC_VERSION)
226 #if (__ARMCC_VERSION >= 6010050)
227 #pragma clang diagnostic push
228 #else
229 #pragma push
230 #pragma anon_unions
231 #endif
232#elif defined(__GNUC__)
233 /* anonymous unions are enabled by default */
234#elif defined(__IAR_SYSTEMS_ICC__)
235 #pragma language=extended
236#else
237 #error Not supported compiler type
238#endif
239
240/* ----------------------------------------------------------------------------
241 -- ACOMP Peripheral Access Layer
242 ---------------------------------------------------------------------------- */
243
244/*!
245 * @addtogroup ACOMP_Peripheral_Access_Layer ACOMP Peripheral Access Layer
246 * @{
247 */
248
249/** ACOMP - Register Layout Typedef */
250typedef struct {
251 __IO uint32_t CTRL; /**< Comparator control register, offset: 0x0 */
252 __IO uint32_t LAD; /**< Voltage ladder register, offset: 0x4 */
253} ACOMP_Type;
254
255/* ----------------------------------------------------------------------------
256 -- ACOMP Register Masks
257 ---------------------------------------------------------------------------- */
258
259/*!
260 * @addtogroup ACOMP_Register_Masks ACOMP Register Masks
261 * @{
262 */
263
264/*! @name CTRL - Comparator control register */
265/*! @{ */
266#define ACOMP_CTRL_EDGESEL_MASK (0x18U)
267#define ACOMP_CTRL_EDGESEL_SHIFT (3U)
268/*! EDGESEL - This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below):
269 * 0b00..Falling edges
270 * 0b01..Rising edges
271 * 0b10..Both edges
272 * 0b11..Both edges
273 */
274#define ACOMP_CTRL_EDGESEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_EDGESEL_SHIFT)) & ACOMP_CTRL_EDGESEL_MASK)
275#define ACOMP_CTRL_COMPSA_MASK (0x40U)
276#define ACOMP_CTRL_COMPSA_SHIFT (6U)
277/*! COMPSA - Comparator output control
278 * 0b0..Comparator output is used directly.
279 * 0b1..Comparator output is synchronized to the bus clock for output to other modules.
280 */
281#define ACOMP_CTRL_COMPSA(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPSA_SHIFT)) & ACOMP_CTRL_COMPSA_MASK)
282#define ACOMP_CTRL_COMP_VP_SEL_MASK (0x700U)
283#define ACOMP_CTRL_COMP_VP_SEL_SHIFT (8U)
284/*! COMP_VP_SEL - Selects positive voltage input
285 * 0b000..VOLTAGE_LADDER_OUTPUT
286 * 0b001..ACMP_I1
287 * 0b010..ACMP_I2
288 * 0b011..ACMP_I3
289 * 0b100..ACMP_I4
290 * 0b101..ACMP_I5
291 * 0b110..Band gap. Internal reference voltage.
292 * 0b111..DAC0 output
293 */
294#define ACOMP_CTRL_COMP_VP_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMP_VP_SEL_SHIFT)) & ACOMP_CTRL_COMP_VP_SEL_MASK)
295#define ACOMP_CTRL_COMP_VM_SEL_MASK (0x3800U)
296#define ACOMP_CTRL_COMP_VM_SEL_SHIFT (11U)
297/*! COMP_VM_SEL - Selects negative voltage input
298 * 0b000..VOLTAGE_LADDER_OUTPUT
299 * 0b001..ACMP_I1
300 * 0b010..ACMP_I2
301 * 0b011..ACMP_I3
302 * 0b100..ACMP_I4
303 * 0b101..ACMP_I5
304 * 0b110..Band gap. Internal reference voltage.
305 * 0b111..DAC0 output
306 */
307#define ACOMP_CTRL_COMP_VM_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMP_VM_SEL_SHIFT)) & ACOMP_CTRL_COMP_VM_SEL_MASK)
308#define ACOMP_CTRL_EDGECLR_MASK (0x100000U)
309#define ACOMP_CTRL_EDGECLR_SHIFT (20U)
310/*! EDGECLR - Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request,
311 * toggle the EDGECLR bit by first writing a 1 and then a 0.
312 */
313#define ACOMP_CTRL_EDGECLR(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_EDGECLR_SHIFT)) & ACOMP_CTRL_EDGECLR_MASK)
314#define ACOMP_CTRL_COMPSTAT_MASK (0x200000U)
315#define ACOMP_CTRL_COMPSTAT_SHIFT (21U)
316/*! COMPSTAT - Comparator status. This bit reflects the state of the comparator output.
317 */
318#define ACOMP_CTRL_COMPSTAT(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPSTAT_SHIFT)) & ACOMP_CTRL_COMPSTAT_MASK)
319#define ACOMP_CTRL_COMPEDGE_MASK (0x800000U)
320#define ACOMP_CTRL_COMPEDGE_SHIFT (23U)
321/*! COMPEDGE - Comparator edge-detect status.
322 */
323#define ACOMP_CTRL_COMPEDGE(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPEDGE_SHIFT)) & ACOMP_CTRL_COMPEDGE_MASK)
324#define ACOMP_CTRL_INTENA_MASK (0x1000000U)
325#define ACOMP_CTRL_INTENA_SHIFT (24U)
326/*! INTENA - Must be set to generate interrupts.
327 */
328#define ACOMP_CTRL_INTENA(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_INTENA_SHIFT)) & ACOMP_CTRL_INTENA_MASK)
329#define ACOMP_CTRL_HYS_MASK (0x6000000U)
330#define ACOMP_CTRL_HYS_SHIFT (25U)
331/*! HYS - Controls the hysteresis of the comparator. When the comparator is outputting a certain
332 * state, this is the difference between the selected signals, in the opposite direction from the
333 * state being output, that will switch the output.
334 * 0b00..None (the output will switch as the voltages cross)
335 * 0b01..5 mv
336 * 0b10..10 mv
337 * 0b11..20 mv
338 */
339#define ACOMP_CTRL_HYS(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_HYS_SHIFT)) & ACOMP_CTRL_HYS_MASK)
340/*! @} */
341
342/*! @name LAD - Voltage ladder register */
343/*! @{ */
344#define ACOMP_LAD_LADEN_MASK (0x1U)
345#define ACOMP_LAD_LADEN_SHIFT (0U)
346/*! LADEN - Voltage ladder enable
347 */
348#define ACOMP_LAD_LADEN(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADEN_SHIFT)) & ACOMP_LAD_LADEN_MASK)
349#define ACOMP_LAD_LADSEL_MASK (0x3EU)
350#define ACOMP_LAD_LADSEL_SHIFT (1U)
351/*! LADSEL - Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000
352 * = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref
353 */
354#define ACOMP_LAD_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADSEL_SHIFT)) & ACOMP_LAD_LADSEL_MASK)
355#define ACOMP_LAD_LADREF_MASK (0x40U)
356#define ACOMP_LAD_LADREF_SHIFT (6U)
357/*! LADREF - Selects the reference voltage Vref for the voltage ladder.
358 * 0b0..Supply pin VDD
359 * 0b1..VDDCMP pin
360 */
361#define ACOMP_LAD_LADREF(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADREF_SHIFT)) & ACOMP_LAD_LADREF_MASK)
362/*! @} */
363
364
365/*!
366 * @}
367 */ /* end of group ACOMP_Register_Masks */
368
369
370/* ACOMP - Peripheral instance base addresses */
371/** Peripheral ACOMP base address */
372#define ACOMP_BASE (0x40024000u)
373/** Peripheral ACOMP base pointer */
374#define ACOMP ((ACOMP_Type *)ACOMP_BASE)
375/** Array initializer of ACOMP peripheral base addresses */
376#define ACOMP_BASE_ADDRS { ACOMP_BASE }
377/** Array initializer of ACOMP peripheral base pointers */
378#define ACOMP_BASE_PTRS { ACOMP }
379/** Interrupt vectors for the ACOMP peripheral type */
380#define ACOMP_IRQS { CMP_CAPT_IRQn }
381
382/*!
383 * @}
384 */ /* end of group ACOMP_Peripheral_Access_Layer */
385
386
387/* ----------------------------------------------------------------------------
388 -- ADC Peripheral Access Layer
389 ---------------------------------------------------------------------------- */
390
391/*!
392 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
393 * @{
394 */
395
396/** ADC - Register Layout Typedef */
397typedef struct {
398 __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
399 uint8_t RESERVED_0[4];
400 __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
401 __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
402 uint8_t RESERVED_1[8];
403 __I uint32_t DAT[12]; /**< ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N., array offset: 0x20, array step: 0x4 */
404 __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
405 __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
406 __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
407 __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
408 __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
409 __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
410 __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
411 __IO uint32_t TRM; /**< ADC Startup register., offset: 0x6C */
412} ADC_Type;
413
414/* ----------------------------------------------------------------------------
415 -- ADC Register Masks
416 ---------------------------------------------------------------------------- */
417
418/*!
419 * @addtogroup ADC_Register_Masks ADC Register Masks
420 * @{
421 */
422
423/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
424/*! @{ */
425#define ADC_CTRL_CLKDIV_MASK (0xFFU)
426#define ADC_CTRL_CLKDIV_SHIFT (0U)
427/*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce
428 * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically,
429 * software should program the smallest value in this field that yields this maximum clock rate or
430 * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may
431 * be desirable. This field is ignored in the asynchronous operating mode.
432 */
433#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
434#define ADC_CTRL_ASYNMODE_MASK (0x100U)
435#define ADC_CTRL_ASYNMODE_SHIFT (8U)
436/*! ASYNMODE - Select clock mode.
437 * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in
438 * the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to
439 * eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger.
440 * In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC
441 * input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger
442 * pulse.
443 * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
444 */
445#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
446#define ADC_CTRL_LPWRMODE_MASK (0x400U)
447#define ADC_CTRL_LPWRMODE_SHIFT (10U)
448/*! LPWRMODE - The low-power ADC mode
449 * 0b0..The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested.
450 * 0b1..The low-power ADC mode is enabled. The analog circuitry is automatically powered-down when no conversions
451 * are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is
452 * enabled. After the required start-up time, the requested conversion will be launched. Once the conversion
453 * completes, the analog-circuitry will again be powered-down provided no further conversions are pending.
454 * Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are
455 * required relatively infrequently. The penalty for using this mode is an approximately FIFTEEN ADC CLOCK delay (30
456 * clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger
457 * event occurs until sampling of the A/D input commences. Note: This mode will NOT power-up the A/D if the
458 * ADC_ENA bit is low.
459 */
460#define ADC_CTRL_LPWRMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_LPWRMODE_SHIFT)) & ADC_CTRL_LPWRMODE_MASK)
461#define ADC_CTRL_CALMODE_MASK (0x40000000U)
462#define ADC_CTRL_CALMODE_SHIFT (30U)
463/*! CALMODE - Writing a '1' to this bit will initiate a sef-calibration cycle. This bit will be
464 * automatically cleared by hardware after the calibration cycle is complete. Note: Other bits of
465 * this register may be written to concurrently with setting this bit, however once this bit has
466 * been set no further writes to this register are permitted unitl the full calibration cycle has
467 * ended.
468 */
469#define ADC_CTRL_CALMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALMODE_SHIFT)) & ADC_CTRL_CALMODE_MASK)
470/*! @} */
471
472/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
473/*! @{ */
474#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU)
475#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U)
476/*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this
477 * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be
478 * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1
479 * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via
480 * software command, ADC conversions will be performed on each enabled channel, in sequence,
481 * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31)
482 * is LOW. It is allowed to change this field and set bit 31 in the same write.
483 */
484#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
485#define ADC_SEQ_CTRL_TRIGGER_MASK (0x7000U)
486#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U)
487/*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion
488 * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order
489 * to avoid generating a spurious trigger, it is recommended writing to this field only when
490 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
491 */
492#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
493#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U)
494#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U)
495/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In
496 * order to avoid generating a spurious trigger, it is recommended writing to this field only when
497 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
498 * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
499 * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
500 */
501#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
502#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U)
503#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U)
504/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization
505 * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a
506 * conversion. There are slightly different criteria for whether or not this bit can be set
507 * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0):
508 * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already
509 * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer).
510 * Whether this bit is set or not, a trigger pulse must be maintained for at least one system
511 * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be
512 * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse
513 * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and
514 * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be
515 * maintained for one system clock period.
516 * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled.
517 * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled.
518 */
519#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
520#define ADC_SEQ_CTRL_START_MASK (0x4000000U)
521#define ADC_SEQ_CTRL_START_SHIFT (26U)
522/*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The
523 * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this
524 * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a
525 * conversion sequence. It will consequently always read back as a zero.
526 */
527#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
528#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U)
529#define ADC_SEQ_CTRL_BURST_SHIFT (27U)
530/*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled
531 * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions
532 * can be halted by clearing this bit. The sequence currently in progress will be completed before
533 * conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
534 */
535#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
536#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U)
537#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U)
538/*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a
539 * single conversion on the next channel in the sequence instead of the default response of
540 * launching an entire sequence of conversions. Once all of the channels comprising a sequence have
541 * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled
542 * channel. Interrupt generation will still occur either after each individual conversion or at
543 * the end of the entire sequence, depending on the state of the MODE bit.
544 */
545#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
546#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U)
547#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U)
548/*! LOWPRIO - Set priority for sequence A.
549 * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
550 * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence
551 * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion
552 * currently in progress will be terminated. The A sequence that was interrupted will automatically resume
553 * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the
554 * conversion sequence will resume from that point.
555 */
556#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
557#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U)
558#define ADC_SEQ_CTRL_MODE_SHIFT (30U)
559/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence
560 * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each
561 * conversion, or the individual channel result registers at the end of the entire sequence. Impacts
562 * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which
563 * overrun conditions contribute to an overrun interrupt as described below.
564 * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC
565 * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The
566 * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger
567 * if enabled.
568 * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A
569 * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in
570 * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun
571 * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
572 */
573#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
574#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U)
575#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U)
576/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be
577 * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state
578 * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered
579 * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care
580 * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE
581 * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be
582 * triggered immediately upon being enabled.
583 * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence
584 * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is
585 * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
586 * 0b1..Enabled. Sequence n is enabled.
587 */
588#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
589/*! @} */
590
591/* The count of ADC_SEQ_CTRL */
592#define ADC_SEQ_CTRL_COUNT (2U)
593
594/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
595/*! @{ */
596#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U)
597#define ADC_SEQ_GDAT_RESULT_SHIFT (4U)
598/*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion
599 * performed under conversion sequence associated with this register. The result is a binary
600 * fraction representing the voltage on the currently-selected input channel as it falls within the
601 * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less
602 * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input
603 * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this
604 * result has not yet been read.
605 */
606#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
607#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U)
608#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U)
609/*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or
610 * within the range established by the designated threshold comparison registers (THRn_LOW and
611 * THRn_HIGH).
612 */
613#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
614#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U)
615#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U)
616/*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a
617 * crossing of the threshold level established by the designated LOW threshold comparison register
618 * (THRn_LOW) and, if so, in what direction the crossing occurred.
619 */
620#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
621#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U)
622#define ADC_SEQ_GDAT_CHN_SHIFT (26U)
623/*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000
624 * identifies channel 0, 0001 channel 1, etc.).
625 */
626#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
627#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U)
628#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U)
629/*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a
630 * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along
631 * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun
632 * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set
633 * to '0' (and if the overrun interrupt is enabled).
634 */
635#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
636#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U)
637#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U)
638/*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded
639 * into the RESULT field. It is cleared whenever this register is read. This bit will cause a
640 * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that
641 * sequence is set to 0 (and if the interrupt is enabled).
642 */
643#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
644/*! @} */
645
646/* The count of ADC_SEQ_GDAT */
647#define ADC_SEQ_GDAT_COUNT (2U)
648
649/*! @name DAT - ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. */
650/*! @{ */
651#define ADC_DAT_RESULT_MASK (0xFFF0U)
652#define ADC_DAT_RESULT_SHIFT (4U)
653/*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed
654 * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin,
655 * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on
656 * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that
657 * the voltage on the input was close to, equal to, or greater than that on VREFP.
658 */
659#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
660#define ADC_DAT_THCMPRANGE_MASK (0x30000U)
661#define ADC_DAT_THCMPRANGE_SHIFT (16U)
662/*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion
663 * was greater than or equal to the value programmed into the designated LOW threshold register
664 * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold
665 * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value
666 * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last
667 * completed conversion was greater than the value programmed into the designated HIGH threshold
668 * register (THRn_HIGH). 0x3 = Reserved.
669 */
670#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
671#define ADC_DAT_THCMPCROSS_MASK (0xC0000U)
672#define ADC_DAT_THCMPCROSS_SHIFT (18U)
673/*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The
674 * most recent completed conversion on this channel had the same relationship (above or below) to
675 * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the
676 * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing
677 * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the
678 * previous sample on this channel was above the threshold value established by the designated LOW
679 * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward
680 * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred
681 * - i.e. the previous sample on this channel was below the threshold value established by the
682 * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
683 */
684#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
685#define ADC_DAT_CHANNEL_MASK (0x3C000000U)
686#define ADC_DAT_CHANNEL_SHIFT (26U)
687/*! CHANNEL - This field is hard-coded to contain the channel number that this particular register
688 * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1
689 * register, etc)
690 */
691#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
692#define ADC_DAT_OVERRUN_MASK (0x40000000U)
693#define ADC_DAT_OVERRUN_SHIFT (30U)
694/*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and
695 * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit
696 * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when
697 * the data related to this channel is read from either of the global SEQn_GDAT registers. This
698 * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if
699 * the overrun interrupt is enabled. While it is allowed to include the same channels in both
700 * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the
701 * data registers associated with any of the channels that are shared between the two sequences. Any
702 * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
703 */
704#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
705#define ADC_DAT_DATAVALID_MASK (0x80000000U)
706#define ADC_DAT_DATAVALID_SHIFT (31U)
707/*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is
708 * cleared whenever this register is read or when the data related to this channel is read from
709 * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in
710 * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in
711 * the data registers associated with any of the channels that are shared between the two
712 * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
713 */
714#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
715/*! @} */
716
717/* The count of ADC_DAT */
718#define ADC_DAT_COUNT (12U)
719
720/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
721/*! @{ */
722#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U)
723#define ADC_THR0_LOW_THRLOW_SHIFT (4U)
724/*! THRLOW - Low threshold value against which ADC results will be compared
725 */
726#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
727/*! @} */
728
729/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
730/*! @{ */
731#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U)
732#define ADC_THR1_LOW_THRLOW_SHIFT (4U)
733/*! THRLOW - Low threshold value against which ADC results will be compared
734 */
735#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
736/*! @} */
737
738/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
739/*! @{ */
740#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U)
741#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U)
742/*! THRHIGH - High threshold value against which ADC results will be compared
743 */
744#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
745/*! @} */
746
747/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
748/*! @{ */
749#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U)
750#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U)
751/*! THRHIGH - High threshold value against which ADC results will be compared
752 */
753#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
754/*! @} */
755
756/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
757/*! @{ */
758#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U)
759#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U)
760/*! CH0_THRSEL - Threshold select for channel 0.
761 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
762 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
763 */
764#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
765#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U)
766#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U)
767/*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0.
768 */
769#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
770#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U)
771#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U)
772/*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0.
773 */
774#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
775#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U)
776#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U)
777/*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0.
778 */
779#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
780#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U)
781#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U)
782/*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0.
783 */
784#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
785#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U)
786#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U)
787/*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0.
788 */
789#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
790#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U)
791#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U)
792/*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0.
793 */
794#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
795#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U)
796#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U)
797/*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0.
798 */
799#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
800#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U)
801#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U)
802/*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0.
803 */
804#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
805#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U)
806#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U)
807/*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0.
808 */
809#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
810#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U)
811#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U)
812/*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0.
813 */
814#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
815#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U)
816#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U)
817/*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0.
818 */
819#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
820/*! @} */
821
822/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
823/*! @{ */
824#define ADC_INTEN_SEQA_INTEN_MASK (0x1U)
825#define ADC_INTEN_SEQA_INTEN_SHIFT (0U)
826/*! SEQA_INTEN - Sequence A interrupt enable.
827 * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled.
828 * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of
829 * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of
830 * conversions, depending on the MODE bit in the SEQA_CTRL register.
831 */
832#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
833#define ADC_INTEN_SEQB_INTEN_MASK (0x2U)
834#define ADC_INTEN_SEQB_INTEN_SHIFT (1U)
835/*! SEQB_INTEN - Sequence B interrupt enable.
836 * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled.
837 * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of
838 * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of
839 * conversions, depending on the MODE bit in the SEQB_CTRL register.
840 */
841#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
842#define ADC_INTEN_OVR_INTEN_MASK (0x4U)
843#define ADC_INTEN_OVR_INTEN_SHIFT (2U)
844/*! OVR_INTEN - Overrun interrupt enable.
845 * 0b0..Disabled. The overrun interrupt is disabled.
846 * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel
847 * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular
848 * sequence is 0, then an overrun in the global data register for that sequence will also cause this
849 * interrupt/DMA trigger to be asserted.
850 */
851#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
852#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U)
853#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U)
854/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0.
855 * 0b00..Disabled.
856 * 0b01..Outside threshold.
857 * 0b10..Crossing threshold.
858 * 0b11..Reserved
859 */
860#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
861#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U)
862#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U)
863/*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0.
864 */
865#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
866#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U)
867#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U)
868/*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0.
869 */
870#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
871#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U)
872#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U)
873/*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0.
874 */
875#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
876#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U)
877#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U)
878/*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0.
879 */
880#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
881#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U)
882#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U)
883/*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0.
884 */
885#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
886#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U)
887#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U)
888/*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0.
889 */
890#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
891#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U)
892#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U)
893/*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0.
894 */
895#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
896#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U)
897#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U)
898/*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0.
899 */
900#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
901#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U)
902#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U)
903/*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0.
904 */
905#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
906#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U)
907#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U)
908/*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0.
909 */
910#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
911#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U)
912#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U)
913/*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0.
914 */
915#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
916/*! @} */
917
918/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
919/*! @{ */
920#define ADC_FLAGS_THCMP0_MASK (0x1U)
921#define ADC_FLAGS_THCMP0_SHIFT (0U)
922/*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or
923 * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by
924 * writing a 1.
925 */
926#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
927#define ADC_FLAGS_THCMP1_MASK (0x2U)
928#define ADC_FLAGS_THCMP1_SHIFT (1U)
929/*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0.
930 */
931#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
932#define ADC_FLAGS_THCMP2_MASK (0x4U)
933#define ADC_FLAGS_THCMP2_SHIFT (2U)
934/*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0.
935 */
936#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
937#define ADC_FLAGS_THCMP3_MASK (0x8U)
938#define ADC_FLAGS_THCMP3_SHIFT (3U)
939/*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0.
940 */
941#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
942#define ADC_FLAGS_THCMP4_MASK (0x10U)
943#define ADC_FLAGS_THCMP4_SHIFT (4U)
944/*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0.
945 */
946#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
947#define ADC_FLAGS_THCMP5_MASK (0x20U)
948#define ADC_FLAGS_THCMP5_SHIFT (5U)
949/*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0.
950 */
951#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
952#define ADC_FLAGS_THCMP6_MASK (0x40U)
953#define ADC_FLAGS_THCMP6_SHIFT (6U)
954/*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0.
955 */
956#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
957#define ADC_FLAGS_THCMP7_MASK (0x80U)
958#define ADC_FLAGS_THCMP7_SHIFT (7U)
959/*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0.
960 */
961#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
962#define ADC_FLAGS_THCMP8_MASK (0x100U)
963#define ADC_FLAGS_THCMP8_SHIFT (8U)
964/*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0.
965 */
966#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
967#define ADC_FLAGS_THCMP9_MASK (0x200U)
968#define ADC_FLAGS_THCMP9_SHIFT (9U)
969/*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0.
970 */
971#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
972#define ADC_FLAGS_THCMP10_MASK (0x400U)
973#define ADC_FLAGS_THCMP10_SHIFT (10U)
974/*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0.
975 */
976#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
977#define ADC_FLAGS_THCMP11_MASK (0x800U)
978#define ADC_FLAGS_THCMP11_SHIFT (11U)
979/*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0.
980 */
981#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
982#define ADC_FLAGS_OVERRUN0_MASK (0x1000U)
983#define ADC_FLAGS_OVERRUN0_SHIFT (12U)
984/*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0
985 */
986#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
987#define ADC_FLAGS_OVERRUN1_MASK (0x2000U)
988#define ADC_FLAGS_OVERRUN1_SHIFT (13U)
989/*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1
990 */
991#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
992#define ADC_FLAGS_OVERRUN2_MASK (0x4000U)
993#define ADC_FLAGS_OVERRUN2_SHIFT (14U)
994/*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2
995 */
996#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
997#define ADC_FLAGS_OVERRUN3_MASK (0x8000U)
998#define ADC_FLAGS_OVERRUN3_SHIFT (15U)
999/*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3
1000 */
1001#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
1002#define ADC_FLAGS_OVERRUN4_MASK (0x10000U)
1003#define ADC_FLAGS_OVERRUN4_SHIFT (16U)
1004/*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4
1005 */
1006#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
1007#define ADC_FLAGS_OVERRUN5_MASK (0x20000U)
1008#define ADC_FLAGS_OVERRUN5_SHIFT (17U)
1009/*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5
1010 */
1011#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
1012#define ADC_FLAGS_OVERRUN6_MASK (0x40000U)
1013#define ADC_FLAGS_OVERRUN6_SHIFT (18U)
1014/*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6
1015 */
1016#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
1017#define ADC_FLAGS_OVERRUN7_MASK (0x80000U)
1018#define ADC_FLAGS_OVERRUN7_SHIFT (19U)
1019/*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7
1020 */
1021#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
1022#define ADC_FLAGS_OVERRUN8_MASK (0x100000U)
1023#define ADC_FLAGS_OVERRUN8_SHIFT (20U)
1024/*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8
1025 */
1026#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
1027#define ADC_FLAGS_OVERRUN9_MASK (0x200000U)
1028#define ADC_FLAGS_OVERRUN9_SHIFT (21U)
1029/*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9
1030 */
1031#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
1032#define ADC_FLAGS_OVERRUN10_MASK (0x400000U)
1033#define ADC_FLAGS_OVERRUN10_SHIFT (22U)
1034/*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10
1035 */
1036#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
1037#define ADC_FLAGS_OVERRUN11_MASK (0x800000U)
1038#define ADC_FLAGS_OVERRUN11_SHIFT (23U)
1039/*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11
1040 */
1041#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
1042#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U)
1043#define ADC_FLAGS_SEQA_OVR_SHIFT (24U)
1044/*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register
1045 */
1046#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
1047#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U)
1048#define ADC_FLAGS_SEQB_OVR_SHIFT (25U)
1049/*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register
1050 */
1051#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
1052#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U)
1053#define ADC_FLAGS_SEQA_INT_SHIFT (28U)
1054/*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0,
1055 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which
1056 * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared
1057 * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register
1058 * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be
1059 * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN
1060 * register.
1061 */
1062#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
1063#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U)
1064#define ADC_FLAGS_SEQB_INT_SHIFT (29U)
1065/*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0,
1066 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which
1067 * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared
1068 * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register
1069 * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be
1070 * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN
1071 * register.
1072 */
1073#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
1074#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U)
1075#define ADC_FLAGS_THCMP_INT_SHIFT (30U)
1076/*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in
1077 * the lower bits of this register are set to 1 (due to an enabled out-of-range or
1078 * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be
1079 * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared
1080 * when all of the individual threshold flags are cleared via writing 1s to those bits.
1081 */
1082#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
1083#define ADC_FLAGS_OVR_INT_MASK (0x80000000U)
1084#define ADC_FLAGS_OVR_INT_SHIFT (31U)
1085/*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data
1086 * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers
1087 * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this
1088 * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all
1089 * of the individual overrun bits have been cleared via reading the corresponding data registers.
1090 */
1091#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
1092/*! @} */
1093
1094/*! @name TRM - ADC Startup register. */
1095/*! @{ */
1096#define ADC_TRM_VRANGE_MASK (0x20U)
1097#define ADC_TRM_VRANGE_SHIFT (5U)
1098/*! VRANGE - 1.8V to 3.6V Vdd range: This bit MUST be set to '1' if operation below 2.7V is to be
1099 * used. Failure to set this bit will result in invalid ADC results. Note: This bit will not be
1100 * spec'd on parts that do not support operation below 2.7V
1101 */
1102#define ADC_TRM_VRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_TRM_VRANGE_SHIFT)) & ADC_TRM_VRANGE_MASK)
1103/*! @} */
1104
1105
1106/*!
1107 * @}
1108 */ /* end of group ADC_Register_Masks */
1109
1110
1111/* ADC - Peripheral instance base addresses */
1112/** Peripheral ADC0 base address */
1113#define ADC0_BASE (0x4001C000u)
1114/** Peripheral ADC0 base pointer */
1115#define ADC0 ((ADC_Type *)ADC0_BASE)
1116/** Array initializer of ADC peripheral base addresses */
1117#define ADC_BASE_ADDRS { ADC0_BASE }
1118/** Array initializer of ADC peripheral base pointers */
1119#define ADC_BASE_PTRS { ADC0 }
1120/** Interrupt vectors for the ADC peripheral type */
1121#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
1122#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn }
1123
1124/*!
1125 * @}
1126 */ /* end of group ADC_Peripheral_Access_Layer */
1127
1128
1129/* ----------------------------------------------------------------------------
1130 -- CAPT Peripheral Access Layer
1131 ---------------------------------------------------------------------------- */
1132
1133/*!
1134 * @addtogroup CAPT_Peripheral_Access_Layer CAPT Peripheral Access Layer
1135 * @{
1136 */
1137
1138/** CAPT - Register Layout Typedef */
1139typedef struct {
1140 __IO uint32_t CTRL; /**< Configuration and control to setup the functional clock, the rules, and the pin selections and rules., offset: 0x0 */
1141 __IO uint32_t STATUS; /**< Status from triggers and time-outs including if in a poll now. Some are used for interrupts., offset: 0x4 */
1142 __IO uint32_t POLL_TCNT; /**< This sets up the polling counter and measurement counter rules., offset: 0x8 */
1143 uint8_t RESERVED_0[4];
1144 __IO uint32_t INTENSET; /**< Interrupt enable, offset: 0x10 */
1145 __IO uint32_t INTENCLR; /**< Interrupt enable clear, offset: 0x14 */
1146 __I uint32_t INTSTAT; /**< Interrupt status (mask of STATUS and INTEN), offset: 0x18 */
1147 uint8_t RESERVED_1[4];
1148 __I uint32_t TOUCH; /**< Last touch event (touch or no-touch) in context., offset: 0x20 */
1149 uint8_t RESERVED_2[4056];
1150 __I uint32_t ID; /**< Block ID, offset: 0xFFC */
1151} CAPT_Type;
1152
1153/* ----------------------------------------------------------------------------
1154 -- CAPT Register Masks
1155 ---------------------------------------------------------------------------- */
1156
1157/*!
1158 * @addtogroup CAPT_Register_Masks CAPT Register Masks
1159 * @{
1160 */
1161
1162/*! @name CTRL - Configuration and control to setup the functional clock, the rules, and the pin selections and rules. */
1163/*! @{ */
1164#define CAPT_CTRL_POLLMODE_MASK (0x3U)
1165#define CAPT_CTRL_POLLMODE_SHIFT (0U)
1166/*! POLLMODE - Mode of operation. May only change from 0 to another value. So, if 2 or 3, must be
1167 * changed to 0 1st. Any attempt to go from non-0 to non-0 will result in 0 anyway.
1168 * 0b00..None, inactive. Poll and time counters are turned off. Writing this will reset state and stop any
1169 * collection in progress. Note: this has no effect on STATUS - those must be cleared manually.
1170 * 0b01..Poll now - forces a manual poll to be started immediately, using XPINSEL X pin(s) to activate in the
1171 * integration loop (all pins set together). Self clears - clear is not indication it is done (see STATUS).
1172 * 0b10..Normal polling using poll delay from POLL_TCNT register. This will start with the poll delay (which can be 0).
1173 * 0b11..The CAPT block will operate in low-power mode. This means it will use GPIO as input, use combination
1174 * touch measurements, and assume it is to wake the system. This will use the POLL_TCNT poll delay, and start
1175 * with the delay.
1176 */
1177#define CAPT_CTRL_POLLMODE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_POLLMODE_SHIFT)) & CAPT_CTRL_POLLMODE_MASK)
1178#define CAPT_CTRL_TYPE_MASK (0xCU)
1179#define CAPT_CTRL_TYPE_SHIFT (2U)
1180/*! TYPE - Selects type of Touch arrangement to use and so how to handle XPINSEL bits
1181 * 0b00..Normal - all X elements are treated as normal, such as buttons and sliders.
1182 * 0b01..3x3 grid using NXP Complementary measurements. The 1st 9 Xs are assumed to be the 3x3 grid. After that
1183 * would be normal X elements. This will also allow 3x1 and 3x2 Note: Only possible if XMAX in STATUS is >=8
1184 * 0b10..5 Sensors interleaved to act as 3x3 touch area using NXP Complementary measurements. 1st 5 Xs used for
1185 * this, all remaining are treated as normal. Note that if 16 X pins allowed, the 16th will not be usable
1186 * when TYPE=1. (use TYPE=0 and select 1 smaller than 15 ( and any others from 1 smaller than 5 on up in
1187 * XPINSEL).
1188 * 0b11..9 Sensors interleaved to act as 5x5 touch area using NXP Complementary measurements. 1st 9 Xs used for
1189 * this, all remaining are treated as normal. Note: Only possible if XMAX in STATUS is >=8
1190 */
1191#define CAPT_CTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_TYPE_SHIFT)) & CAPT_CTRL_TYPE_MASK)
1192#define CAPT_CTRL_TRIGGER_MASK (0x10U)
1193#define CAPT_CTRL_TRIGGER_SHIFT (4U)
1194/*! TRIGGER - This selects what is being used as the trigger
1195 * 0b0..Uses YH GPIO. This is not normally used except in Low-power mode. But, it can be used with POLLNOW to baseline that measurement.
1196 * 0b1..ACMP (if fitted). This assumes the ACMP state is fed in asynchronously and it will sample.
1197 */
1198#define CAPT_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_TRIGGER_SHIFT)) & CAPT_CTRL_TRIGGER_MASK)
1199#define CAPT_CTRL_WAIT_MASK (0x20U)
1200#define CAPT_CTRL_WAIT_SHIFT (5U)
1201/*! WAIT - If 0, the block will continue its X based measurements, even if the TOUCH register has
1202 * not been read (and so could OVERRUN). If 1, it will wait until read when a touch (TOUCH's
1203 * ISTOUCH bit is set) before starting the next. This should not normally be needed.
1204 */
1205#define CAPT_CTRL_WAIT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_WAIT_SHIFT)) & CAPT_CTRL_WAIT_MASK)
1206#define CAPT_CTRL_DMA_MASK (0xC0U)
1207#define CAPT_CTRL_DMA_SHIFT (6U)
1208/*! DMA - If not 0, will use the DMA to read out touch events from TOUCH register. The values are
1209 * shown below. This may be changed while active.
1210 * 0b00..No DMA. Application will use ISRs to read out data
1211 * 0b01..Trigger DMA on Touch events
1212 * 0b10..Trigger DMA on both Touch and No-Touch events
1213 * 0b11..Trigger DMA on both plus Timeout.
1214 */
1215#define CAPT_CTRL_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_DMA_SHIFT)) & CAPT_CTRL_DMA_MASK)
1216#define CAPT_CTRL_FDIV_MASK (0xF00U)
1217#define CAPT_CTRL_FDIV_SHIFT (8U)
1218/*! FDIV - Functional clock divider, or 0 if no divide. The term "clocks" in this spec then refer to
1219 * divided clocks. For a 12MHz input (e.g. FRO 12MHz), this would normally be set to generate a
1220 * 4MHz output (so, 2). For a 1MHz input, it should be 0. Note for internal use: this does not
1221 * produce a 50/50 duty cycle when non even divide.
1222 * 0b0000..No divide
1223 * 0b0001../2
1224 * 0b0010../3
1225 * 0b0011../4
1226 * 0b0100../5
1227 * 0b0101../6
1228 * 0b0111../(FDIV+1)
1229 * 0b1000../(FDIV+1)
1230 * 0b1001../(FDIV+1)
1231 * 0b1010../(FDIV+1)
1232 * 0b1011../(FDIV+1)
1233 * 0b1100../(FDIV+1)
1234 * 0b1101../(FDIV+1)
1235 * 0b1110../(FDIV+1)
1236 * 0b1111../(FDIV+1)
1237 */
1238#define CAPT_CTRL_FDIV(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_FDIV_SHIFT)) & CAPT_CTRL_FDIV_MASK)
1239#define CAPT_CTRL_XPINUSE_MASK (0x3000U)
1240#define CAPT_CTRL_XPINUSE_SHIFT (12U)
1241/*! XPINUSE - Controls how X pins selected in XPINSEL are used when not active in the current polling round.
1242 * 0b00..Normal mode. Each inactive X pin is Hi-Z.
1243 * 0b01..Ground mode. Each inactive X pin is Low
1244 */
1245#define CAPT_CTRL_XPINUSE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_XPINUSE_SHIFT)) & CAPT_CTRL_XPINUSE_MASK)
1246#define CAPT_CTRL_INCHANGE_MASK (0x8000U)
1247#define CAPT_CTRL_INCHANGE_SHIFT (15U)
1248/*! INCHANGE - If 1, do not attempt to write to this register again. This means the last change has
1249 * not been propagated. This can only happen after changing POLLMODE and DMA. Worse case time
1250 * would be based on divided FCLK.
1251 */
1252#define CAPT_CTRL_INCHANGE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_INCHANGE_SHIFT)) & CAPT_CTRL_INCHANGE_MASK)
1253#define CAPT_CTRL_XPINSEL_MASK (0xFFFF0000U)
1254#define CAPT_CTRL_XPINSEL_SHIFT (16U)
1255/*! XPINSEL - Selects which of the X pins are to be used within the allowed pins - see XMAX in
1256 * STATUS. The X pins are mapped via the IOCON (as are the YH and YL pins) to physical pads. So, this
1257 * only selects which are to be used as the X half of the touch element. Note: when polling,
1258 * these are "walked" (active) one at a time. When using POLLNOW, the 1 or more selected are used at
1259 * the same time. Likewise, when in low-power mode, they are used at the same time (or small
1260 * groups). X pads not selected by XPINSEL are kept at High-Z if they are connected to a pad. This
1261 * allows using controlled sets for touch detection based on context.
1262 */
1263#define CAPT_CTRL_XPINSEL(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_XPINSEL_SHIFT)) & CAPT_CTRL_XPINSEL_MASK)
1264/*! @} */
1265
1266/*! @name STATUS - Status from triggers and time-outs including if in a poll now. Some are used for interrupts. */
1267/*! @{ */
1268#define CAPT_STATUS_YESTOUCH_MASK (0x1U)
1269#define CAPT_STATUS_YESTOUCH_SHIFT (0U)
1270/*! YESTOUCH - Is 1 if a touch has been detected, including a wakeup from low-power mode.
1271 */
1272#define CAPT_STATUS_YESTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_YESTOUCH_SHIFT)) & CAPT_STATUS_YESTOUCH_MASK)
1273#define CAPT_STATUS_NOTOUCH_MASK (0x2U)
1274#define CAPT_STATUS_NOTOUCH_SHIFT (1U)
1275/*! NOTOUCH - Is 1 if a no-touch has been detected (ie. completed an integration cycle and found
1276 * no-touch). This is not set when in low-power mode.
1277 */
1278#define CAPT_STATUS_NOTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_NOTOUCH_SHIFT)) & CAPT_STATUS_NOTOUCH_MASK)
1279#define CAPT_STATUS_POLLDONE_MASK (0x4U)
1280#define CAPT_STATUS_POLLDONE_SHIFT (2U)
1281/*! POLLDONE - Is 1 if a poll or POLLNOW is complete.
1282 */
1283#define CAPT_STATUS_POLLDONE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_POLLDONE_SHIFT)) & CAPT_STATUS_POLLDONE_MASK)
1284#define CAPT_STATUS_TIMEOUT_MASK (0x8U)
1285#define CAPT_STATUS_TIMEOUT_SHIFT (3U)
1286/*! TIMEOUT - Is 1 if an integration cycle ended with a timeout (should not happen).
1287 */
1288#define CAPT_STATUS_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_TIMEOUT_SHIFT)) & CAPT_STATUS_TIMEOUT_MASK)
1289#define CAPT_STATUS_OVERUN_MASK (0x10U)
1290#define CAPT_STATUS_OVERUN_SHIFT (4U)
1291/*! OVERUN - Is 1 if new data was collected before application read out previous ISTOUCH. No-touch
1292 * (ISTOUCH==0) data will be silently overrun. Is not possible if WAIT=1.
1293 */
1294#define CAPT_STATUS_OVERUN(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_OVERUN_SHIFT)) & CAPT_STATUS_OVERUN_MASK)
1295#define CAPT_STATUS_BUSY_MASK (0x100U)
1296#define CAPT_STATUS_BUSY_SHIFT (8U)
1297/*! BUSY - In a poll now.
1298 */
1299#define CAPT_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_BUSY_SHIFT)) & CAPT_STATUS_BUSY_MASK)
1300#define CAPT_STATUS_XMAX_MASK (0xF0000U)
1301#define CAPT_STATUS_XMAX_SHIFT (16U)
1302/*! XMAX - Indicates the maximum number of X pins allowed 0-relative. So, 15 means there are pins 0
1303 * to 15, or 16 total X pins. INTERNAL note: this may be setup to be written by ROM boot.
1304 */
1305#define CAPT_STATUS_XMAX(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_XMAX_SHIFT)) & CAPT_STATUS_XMAX_MASK)
1306/*! @} */
1307
1308/*! @name POLL_TCNT - This sets up the polling counter and measurement counter rules. */
1309/*! @{ */
1310#define CAPT_POLL_TCNT_TCNT_MASK (0xFFFU)
1311#define CAPT_POLL_TCNT_TCNT_SHIFT (0U)
1312/*! TCNT - Sets the threshold between touch and no-touch count. If not used, then the block will
1313 * treat all events as touch or no-touch, depending whether at max or min. This is in terms of
1314 * divided FCLK. If the comparator triggers it is no-touch; if bigger than TCNT counts, it is a touch
1315 * event.
1316 */
1317#define CAPT_POLL_TCNT_TCNT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_POLL_TCNT_TCNT_SHIFT)) & CAPT_POLL_TCNT_TCNT_MASK)
1318#define CAPT_POLL_TCNT_TOUT_MASK (0xF000U)
1319#define CAPT_POLL_TCNT_TOUT_SHIFT (12U)
1320/*! TOUT - Time-out count expressed as 1 is smaller than TOUT, allowing for up to 12 bits. Must be
1321 * less than 13. So, for example, 1 is smaller than 12=4096 counts; if TOUT=12, then if 4096
1322 * counts occur without a trigger, it is a time-out. This should be set to be large enough above TCNT
1323 * to prevent timeout invalidly.
1324 */
1325#define CAPT_POLL_TCNT_TOUT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_POLL_TCNT_TOUT_SHIFT)) & CAPT_POLL_TCNT_TOUT_MASK)
1326#define CAPT_POLL_TCNT_POLL_MASK (0xFF0000U)
1327#define CAPT_POLL_TCNT_POLL_SHIFT (16U)
1328/*! POLL - Poll counter in (internal) 12-bit counter wraparounds (loosely 1msec), so related to
1329 * divided FCLK. This expresses time delay between measurement cycles (ie. after one set of X
1330 * measurements, time before starting next). This count is used to delay before the next set of
1331 * measurements. Measuring too often wastes power and does not add value since movement of fingers is
1332 * relatively slow. For low power mode, this must allow for the clock being used (e.g. a 1MHz osc)
1333 * so 12 bit count will be potentially much longer. That means, lowering the count to get the
1334 * reasonable delay period.
1335 */
1336#define CAPT_POLL_TCNT_POLL(x) (((uint32_t)(((uint32_t)(x)) << CAPT_POLL_TCNT_POLL_SHIFT)) & CAPT_POLL_TCNT_POLL_MASK)
1337#define CAPT_POLL_TCNT_MDELAY_MASK (0x3000000U)
1338#define CAPT_POLL_TCNT_MDELAY_SHIFT (24U)
1339/*! MDELAY - If not 0, this selects the number of divided FCLKs to wait after entry of measurement
1340 * mode before deciding if has triggered. This gives the ACMP time to react to the transferred
1341 * charge. It is used as 1+(1 smaller than MDELAY), , so between 2 and 8 ticks of the divided FCLK
1342 * added during the measurement.
1343 */
1344#define CAPT_POLL_TCNT_MDELAY(x) (((uint32_t)(((uint32_t)(x)) << CAPT_POLL_TCNT_MDELAY_SHIFT)) & CAPT_POLL_TCNT_MDELAY_MASK)
1345#define CAPT_POLL_TCNT_RDELAY_MASK (0xC000000U)
1346#define CAPT_POLL_TCNT_RDELAY_SHIFT (26U)
1347/*! RDELAY - If not 0, this is the number of divided FCLKs to hold in Step 0 'Reset' state (draining
1348 * capacitance). It is used as (1 is smaller than RDELAY), so between 2 and 8 ticks of the
1349 * divided FCLK added to the 'Reset' state.
1350 */
1351#define CAPT_POLL_TCNT_RDELAY(x) (((uint32_t)(((uint32_t)(x)) << CAPT_POLL_TCNT_RDELAY_SHIFT)) & CAPT_POLL_TCNT_RDELAY_MASK)
1352#define CAPT_POLL_TCNT_TCHLOW_ER_MASK (0x80000000U)
1353#define CAPT_POLL_TCNT_TCHLOW_ER_SHIFT (31U)
1354/*! TCHLOW_ER - If 1, then the touch/no-touch boundary of TCNT is reversed. In a floating system
1355 * (most common), the no-touch case triggers at a lower count vs. touch; this is due to touch
1356 * drawing off charge. In a grounded system, the reverse is true and the touch adds to the charge and
1357 * so touch is a lower count. In a system which can switch between grounded and non-grounded, the
1358 * SW will check for all of the Xs looking like they have been touched and reverse the setting of
1359 * this bit. This should only be changed between polls.
1360 */
1361#define CAPT_POLL_TCNT_TCHLOW_ER(x) (((uint32_t)(((uint32_t)(x)) << CAPT_POLL_TCNT_TCHLOW_ER_SHIFT)) & CAPT_POLL_TCNT_TCHLOW_ER_MASK)
1362/*! @} */
1363
1364/*! @name INTENSET - Interrupt enable */
1365/*! @{ */
1366#define CAPT_INTENSET_YESTOUCH_MASK (0x1U)
1367#define CAPT_INTENSET_YESTOUCH_SHIFT (0U)
1368/*! YESTOUCH - Is 1 if a touch detected should interrupt. This includes wake from low-power mode.
1369 */
1370#define CAPT_INTENSET_YESTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENSET_YESTOUCH_SHIFT)) & CAPT_INTENSET_YESTOUCH_MASK)
1371#define CAPT_INTENSET_NOTOUCH_MASK (0x2U)
1372#define CAPT_INTENSET_NOTOUCH_SHIFT (1U)
1373/*! NOTOUCH - Is 1 if a no-touch detected should interrupt
1374 */
1375#define CAPT_INTENSET_NOTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENSET_NOTOUCH_SHIFT)) & CAPT_INTENSET_NOTOUCH_MASK)
1376#define CAPT_INTENSET_POLLDONE_MASK (0x4U)
1377#define CAPT_INTENSET_POLLDONE_SHIFT (2U)
1378/*! POLLDONE - Is 1 if a poll or POLLNOW completing should interrupt
1379 */
1380#define CAPT_INTENSET_POLLDONE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENSET_POLLDONE_SHIFT)) & CAPT_INTENSET_POLLDONE_MASK)
1381#define CAPT_INTENSET_TIMEOUT_MASK (0x8U)
1382#define CAPT_INTENSET_TIMEOUT_SHIFT (3U)
1383/*! TIMEOUT - Is 1 if an integration cycle ending with timeout should interrupt
1384 */
1385#define CAPT_INTENSET_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENSET_TIMEOUT_SHIFT)) & CAPT_INTENSET_TIMEOUT_MASK)
1386#define CAPT_INTENSET_OVERUN_MASK (0x10U)
1387#define CAPT_INTENSET_OVERUN_SHIFT (4U)
1388/*! OVERUN - Is 1 if an overrun should interrupt.
1389 */
1390#define CAPT_INTENSET_OVERUN(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENSET_OVERUN_SHIFT)) & CAPT_INTENSET_OVERUN_MASK)
1391/*! @} */
1392
1393/*! @name INTENCLR - Interrupt enable clear */
1394/*! @{ */
1395#define CAPT_INTENCLR_YESTOUCH_MASK (0x1U)
1396#define CAPT_INTENCLR_YESTOUCH_SHIFT (0U)
1397/*! YESTOUCH - clear the touch interrupt
1398 */
1399#define CAPT_INTENCLR_YESTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENCLR_YESTOUCH_SHIFT)) & CAPT_INTENCLR_YESTOUCH_MASK)
1400#define CAPT_INTENCLR_NOTOUCH_MASK (0x2U)
1401#define CAPT_INTENCLR_NOTOUCH_SHIFT (1U)
1402/*! NOTOUCH - clear the no-touch interrupt
1403 */
1404#define CAPT_INTENCLR_NOTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENCLR_NOTOUCH_SHIFT)) & CAPT_INTENCLR_NOTOUCH_MASK)
1405#define CAPT_INTENCLR_POLLDONE_MASK (0x4U)
1406#define CAPT_INTENCLR_POLLDONE_SHIFT (2U)
1407/*! POLLDONE - clear the poll or POLLNOW completing interrupt
1408 */
1409#define CAPT_INTENCLR_POLLDONE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENCLR_POLLDONE_SHIFT)) & CAPT_INTENCLR_POLLDONE_MASK)
1410#define CAPT_INTENCLR_TIMEOUT_MASK (0x8U)
1411#define CAPT_INTENCLR_TIMEOUT_SHIFT (3U)
1412/*! TIMEOUT - clear the timeout interrupt
1413 */
1414#define CAPT_INTENCLR_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENCLR_TIMEOUT_SHIFT)) & CAPT_INTENCLR_TIMEOUT_MASK)
1415#define CAPT_INTENCLR_OVERUN_MASK (0x10U)
1416#define CAPT_INTENCLR_OVERUN_SHIFT (4U)
1417/*! OVERUN - clear the overrun interrupt
1418 */
1419#define CAPT_INTENCLR_OVERUN(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENCLR_OVERUN_SHIFT)) & CAPT_INTENCLR_OVERUN_MASK)
1420/*! @} */
1421
1422/*! @name INTSTAT - Interrupt status (mask of STATUS and INTEN) */
1423/*! @{ */
1424#define CAPT_INTSTAT_YESTOUCH_MASK (0x1U)
1425#define CAPT_INTSTAT_YESTOUCH_SHIFT (0U)
1426/*! YESTOUCH - the status of touch interrrupt
1427 */
1428#define CAPT_INTSTAT_YESTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTSTAT_YESTOUCH_SHIFT)) & CAPT_INTSTAT_YESTOUCH_MASK)
1429#define CAPT_INTSTAT_NOTOUCH_MASK (0x2U)
1430#define CAPT_INTSTAT_NOTOUCH_SHIFT (1U)
1431/*! NOTOUCH - the status of no-touch interrrupt
1432 */
1433#define CAPT_INTSTAT_NOTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTSTAT_NOTOUCH_SHIFT)) & CAPT_INTSTAT_NOTOUCH_MASK)
1434#define CAPT_INTSTAT_POLLDONE_MASK (0x4U)
1435#define CAPT_INTSTAT_POLLDONE_SHIFT (2U)
1436/*! POLLDONE - the status of poll or pollnow completing interrupt
1437 */
1438#define CAPT_INTSTAT_POLLDONE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTSTAT_POLLDONE_SHIFT)) & CAPT_INTSTAT_POLLDONE_MASK)
1439#define CAPT_INTSTAT_TIMEOUT_MASK (0x8U)
1440#define CAPT_INTSTAT_TIMEOUT_SHIFT (3U)
1441/*! TIMEOUT - the status of timeout interrupt
1442 */
1443#define CAPT_INTSTAT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTSTAT_TIMEOUT_SHIFT)) & CAPT_INTSTAT_TIMEOUT_MASK)
1444#define CAPT_INTSTAT_OVERUN_MASK (0x10U)
1445#define CAPT_INTSTAT_OVERUN_SHIFT (4U)
1446/*! OVERUN - the status of overrun interrupt
1447 */
1448#define CAPT_INTSTAT_OVERUN(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTSTAT_OVERUN_SHIFT)) & CAPT_INTSTAT_OVERUN_MASK)
1449/*! @} */
1450
1451/*! @name TOUCH - Last touch event (touch or no-touch) in context. */
1452/*! @{ */
1453#define CAPT_TOUCH_COUNT_MASK (0xFFFU)
1454#define CAPT_TOUCH_COUNT_SHIFT (0U)
1455/*! COUNT - Count value reached at trigger. If timeout, will be (1 bigger than TOUT)-1; e.g. if TOUT=12, then 0xFFF.
1456 */
1457#define CAPT_TOUCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_TOUCH_COUNT_SHIFT)) & CAPT_TOUCH_COUNT_MASK)
1458#define CAPT_TOUCH_XVAL_MASK (0xF000U)
1459#define CAPT_TOUCH_XVAL_SHIFT (12U)
1460/*! XVAL - Is the X that triggered this, or lowest X if more than one.
1461 */
1462#define CAPT_TOUCH_XVAL(x) (((uint32_t)(((uint32_t)(x)) << CAPT_TOUCH_XVAL_SHIFT)) & CAPT_TOUCH_XVAL_MASK)
1463#define CAPT_TOUCH_ISTOUCH_MASK (0x10000U)
1464#define CAPT_TOUCH_ISTOUCH_SHIFT (16U)
1465/*! ISTOUCH - 1 if is Touch (by count) or 0 if is no-touch.
1466 */
1467#define CAPT_TOUCH_ISTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_TOUCH_ISTOUCH_SHIFT)) & CAPT_TOUCH_ISTOUCH_MASK)
1468#define CAPT_TOUCH_ISTO_MASK (0x20000U)
1469#define CAPT_TOUCH_ISTO_SHIFT (17U)
1470/*! ISTO - 1 if is Timeout.
1471 */
1472#define CAPT_TOUCH_ISTO(x) (((uint32_t)(((uint32_t)(x)) << CAPT_TOUCH_ISTO_SHIFT)) & CAPT_TOUCH_ISTO_MASK)
1473#define CAPT_TOUCH_SEQ_MASK (0xF00000U)
1474#define CAPT_TOUCH_SEQ_SHIFT (20U)
1475/*! SEQ - Sequence number - rolling counter of polls. Changes after all selected Xs per poll (so, 0
1476 * for 1st set of Xs, then 1 for next set, etc).
1477 */
1478#define CAPT_TOUCH_SEQ(x) (((uint32_t)(((uint32_t)(x)) << CAPT_TOUCH_SEQ_SHIFT)) & CAPT_TOUCH_SEQ_MASK)
1479#define CAPT_TOUCH_CHANGE_MASK (0x80000000U)
1480#define CAPT_TOUCH_CHANGE_SHIFT (31U)
1481/*! CHANGE - If 1, the rest of the register is 0 because the data is changing. This will only happen
1482 * for 1 cycle and would never happen if using interrupts to read, unless took so long as to
1483 * overrun.
1484 */
1485#define CAPT_TOUCH_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_TOUCH_CHANGE_SHIFT)) & CAPT_TOUCH_CHANGE_MASK)
1486/*! @} */
1487
1488/*! @name ID - Block ID */
1489/*! @{ */
1490#define CAPT_ID_APERTURE_MASK (0xFFU)
1491#define CAPT_ID_APERTURE_SHIFT (0U)
1492/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 is a 4 K aperture.
1493 */
1494#define CAPT_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_ID_APERTURE_SHIFT)) & CAPT_ID_APERTURE_MASK)
1495#define CAPT_ID_MINOR_REV_MASK (0xF00U)
1496#define CAPT_ID_MINOR_REV_SHIFT (8U)
1497/*! MINOR_REV - Minor revision of module implementation, starting at 0. Software compatibility is expected between minor revisions.
1498 */
1499#define CAPT_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << CAPT_ID_MINOR_REV_SHIFT)) & CAPT_ID_MINOR_REV_MASK)
1500#define CAPT_ID_MAJOR_REV_MASK (0xF000U)
1501#define CAPT_ID_MAJOR_REV_SHIFT (12U)
1502/*! MAJOR_REV - Major revision of module implementation, starting at 0. There may not be software compatibility between major revisions.
1503 */
1504#define CAPT_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << CAPT_ID_MAJOR_REV_SHIFT)) & CAPT_ID_MAJOR_REV_MASK)
1505#define CAPT_ID_ID_MASK (0xFFFF0000U)
1506#define CAPT_ID_ID_SHIFT (16U)
1507/*! ID - 1 if is Timeout.
1508 */
1509#define CAPT_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << CAPT_ID_ID_SHIFT)) & CAPT_ID_ID_MASK)
1510/*! @} */
1511
1512
1513/*!
1514 * @}
1515 */ /* end of group CAPT_Register_Masks */
1516
1517
1518/* CAPT - Peripheral instance base addresses */
1519/** Peripheral CAPT base address */
1520#define CAPT_BASE (0x40060000u)
1521/** Peripheral CAPT base pointer */
1522#define CAPT ((CAPT_Type *)CAPT_BASE)
1523/** Array initializer of CAPT peripheral base addresses */
1524#define CAPT_BASE_ADDRS { CAPT_BASE }
1525/** Array initializer of CAPT peripheral base pointers */
1526#define CAPT_BASE_PTRS { CAPT }
1527/** Interrupt vectors for the CAPT peripheral type */
1528#define CAPT_IRQS { CMP_CAPT_IRQn }
1529
1530/*!
1531 * @}
1532 */ /* end of group CAPT_Peripheral_Access_Layer */
1533
1534
1535/* ----------------------------------------------------------------------------
1536 -- CRC Peripheral Access Layer
1537 ---------------------------------------------------------------------------- */
1538
1539/*!
1540 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
1541 * @{
1542 */
1543
1544/** CRC - Register Layout Typedef */
1545typedef struct {
1546 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
1547 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
1548 union { /* offset: 0x8 */
1549 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
1550 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
1551 };
1552} CRC_Type;
1553
1554/* ----------------------------------------------------------------------------
1555 -- CRC Register Masks
1556 ---------------------------------------------------------------------------- */
1557
1558/*!
1559 * @addtogroup CRC_Register_Masks CRC Register Masks
1560 * @{
1561 */
1562
1563/*! @name MODE - CRC mode register */
1564/*! @{ */
1565#define CRC_MODE_CRC_POLY_MASK (0x3U)
1566#define CRC_MODE_CRC_POLY_SHIFT (0U)
1567/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
1568 */
1569#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
1570#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
1571#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
1572/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
1573 */
1574#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
1575#define CRC_MODE_CMPL_WR_MASK (0x8U)
1576#define CRC_MODE_CMPL_WR_SHIFT (3U)
1577/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
1578 */
1579#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
1580#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
1581#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
1582/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
1583 */
1584#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
1585#define CRC_MODE_CMPL_SUM_MASK (0x20U)
1586#define CRC_MODE_CMPL_SUM_SHIFT (5U)
1587/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
1588 */
1589#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
1590/*! @} */
1591
1592/*! @name SEED - CRC seed register */
1593/*! @{ */
1594#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
1595#define CRC_SEED_CRC_SEED_SHIFT (0U)
1596/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
1597 * selected bit order and 1's complement pre-processes. A write access to this register will
1598 * overrule the CRC calculation in progresses.
1599 */
1600#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
1601/*! @} */
1602
1603/*! @name SUM - CRC checksum register */
1604/*! @{ */
1605#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
1606#define CRC_SUM_CRC_SUM_SHIFT (0U)
1607/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
1608 */
1609#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
1610/*! @} */
1611
1612/*! @name WR_DATA - CRC data register */
1613/*! @{ */
1614#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
1615#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
1616/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
1617 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
1618 * accept back-to-back transactions.
1619 */
1620#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
1621/*! @} */
1622
1623
1624/*!
1625 * @}
1626 */ /* end of group CRC_Register_Masks */
1627
1628
1629/* CRC - Peripheral instance base addresses */
1630/** Peripheral CRC base address */
1631#define CRC_BASE (0x50000000u)
1632/** Peripheral CRC base pointer */
1633#define CRC ((CRC_Type *)CRC_BASE)
1634/** Array initializer of CRC peripheral base addresses */
1635#define CRC_BASE_ADDRS { CRC_BASE }
1636/** Array initializer of CRC peripheral base pointers */
1637#define CRC_BASE_PTRS { CRC }
1638
1639/*!
1640 * @}
1641 */ /* end of group CRC_Peripheral_Access_Layer */
1642
1643
1644/* ----------------------------------------------------------------------------
1645 -- CTIMER Peripheral Access Layer
1646 ---------------------------------------------------------------------------- */
1647
1648/*!
1649 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
1650 * @{
1651 */
1652
1653/** CTIMER - Register Layout Typedef */
1654typedef struct {
1655 __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
1656 __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
1657 __IO uint32_t TC; /**< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR., offset: 0x8 */
1658 __IO uint32_t PR; /**< Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC., offset: 0xC */
1659 __IO uint32_t PC; /**< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface., offset: 0x10 */
1660 __IO uint32_t MCR; /**< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs., offset: 0x14 */
1661 __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
1662 __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
1663 __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
1664 __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
1665 uint8_t RESERVED_0[48];
1666 __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
1667 __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
1668 __IO uint32_t MSR[4]; /**< Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero., array offset: 0x78, array step: 0x4 */
1669} CTIMER_Type;
1670
1671/* ----------------------------------------------------------------------------
1672 -- CTIMER Register Masks
1673 ---------------------------------------------------------------------------- */
1674
1675/*!
1676 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
1677 * @{
1678 */
1679
1680/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
1681/*! @{ */
1682#define CTIMER_IR_MR0INT_MASK (0x1U)
1683#define CTIMER_IR_MR0INT_SHIFT (0U)
1684/*! MR0INT - Interrupt flag for match channel 0.
1685 */
1686#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
1687#define CTIMER_IR_MR1INT_MASK (0x2U)
1688#define CTIMER_IR_MR1INT_SHIFT (1U)
1689/*! MR1INT - Interrupt flag for match channel 1.
1690 */
1691#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
1692#define CTIMER_IR_MR2INT_MASK (0x4U)
1693#define CTIMER_IR_MR2INT_SHIFT (2U)
1694/*! MR2INT - Interrupt flag for match channel 2.
1695 */
1696#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
1697#define CTIMER_IR_MR3INT_MASK (0x8U)
1698#define CTIMER_IR_MR3INT_SHIFT (3U)
1699/*! MR3INT - Interrupt flag for match channel 3.
1700 */
1701#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
1702#define CTIMER_IR_CR0INT_MASK (0x10U)
1703#define CTIMER_IR_CR0INT_SHIFT (4U)
1704/*! CR0INT - Interrupt flag for capture channel 0 event.
1705 */
1706#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
1707#define CTIMER_IR_CR1INT_MASK (0x20U)
1708#define CTIMER_IR_CR1INT_SHIFT (5U)
1709/*! CR1INT - Interrupt flag for capture channel 1 event.
1710 */
1711#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
1712#define CTIMER_IR_CR2INT_MASK (0x40U)
1713#define CTIMER_IR_CR2INT_SHIFT (6U)
1714/*! CR2INT - Interrupt flag for capture channel 2 event.
1715 */
1716#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
1717#define CTIMER_IR_CR3INT_MASK (0x80U)
1718#define CTIMER_IR_CR3INT_SHIFT (7U)
1719/*! CR3INT - Interrupt flag for capture channel 3 event.
1720 */
1721#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
1722/*! @} */
1723
1724/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
1725/*! @{ */
1726#define CTIMER_TCR_CEN_MASK (0x1U)
1727#define CTIMER_TCR_CEN_SHIFT (0U)
1728/*! CEN - Counter enable.
1729 * 0b0..Disabled.The counters are disabled.
1730 * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
1731 */
1732#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
1733#define CTIMER_TCR_CRST_MASK (0x2U)
1734#define CTIMER_TCR_CRST_SHIFT (1U)
1735/*! CRST - Counter reset.
1736 * 0b0..Disabled. Do nothing.
1737 * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
1738 * the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
1739 */
1740#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
1741/*! @} */
1742
1743/*! @name TC - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. */
1744/*! @{ */
1745#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
1746#define CTIMER_TC_TCVAL_SHIFT (0U)
1747/*! TCVAL - Timer counter value.
1748 */
1749#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
1750/*! @} */
1751
1752/*! @name PR - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. */
1753/*! @{ */
1754#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
1755#define CTIMER_PR_PRVAL_SHIFT (0U)
1756/*! PRVAL - Prescale counter value.
1757 */
1758#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
1759/*! @} */
1760
1761/*! @name PC - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
1762/*! @{ */
1763#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
1764#define CTIMER_PC_PCVAL_SHIFT (0U)
1765/*! PCVAL - Prescale counter value.
1766 */
1767#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
1768/*! @} */
1769
1770/*! @name MCR - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
1771/*! @{ */
1772#define CTIMER_MCR_MR0I_MASK (0x1U)
1773#define CTIMER_MCR_MR0I_SHIFT (0U)
1774/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled.
1775 */
1776#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
1777#define CTIMER_MCR_MR0R_MASK (0x2U)
1778#define CTIMER_MCR_MR0R_SHIFT (1U)
1779/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled.
1780 */
1781#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
1782#define CTIMER_MCR_MR0S_MASK (0x4U)
1783#define CTIMER_MCR_MR0S_SHIFT (2U)
1784/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled.
1785 */
1786#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
1787#define CTIMER_MCR_MR1I_MASK (0x8U)
1788#define CTIMER_MCR_MR1I_SHIFT (3U)
1789/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 =
1790 * disabled. 1 = enabled. 0 = disabled. 1 = enabled.
1791 */
1792#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
1793#define CTIMER_MCR_MR1R_MASK (0x10U)
1794#define CTIMER_MCR_MR1R_SHIFT (4U)
1795/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled.
1796 */
1797#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
1798#define CTIMER_MCR_MR1S_MASK (0x20U)
1799#define CTIMER_MCR_MR1S_SHIFT (5U)
1800/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled.
1801 */
1802#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
1803#define CTIMER_MCR_MR2I_MASK (0x40U)
1804#define CTIMER_MCR_MR2I_SHIFT (6U)
1805/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled.
1806 */
1807#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
1808#define CTIMER_MCR_MR2R_MASK (0x80U)
1809#define CTIMER_MCR_MR2R_SHIFT (7U)
1810/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled.
1811 */
1812#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
1813#define CTIMER_MCR_MR2S_MASK (0x100U)
1814#define CTIMER_MCR_MR2S_SHIFT (8U)
1815/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled.
1816 */
1817#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
1818#define CTIMER_MCR_MR3I_MASK (0x200U)
1819#define CTIMER_MCR_MR3I_SHIFT (9U)
1820/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled.
1821 */
1822#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
1823#define CTIMER_MCR_MR3R_MASK (0x400U)
1824#define CTIMER_MCR_MR3R_SHIFT (10U)
1825/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled.
1826 */
1827#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
1828#define CTIMER_MCR_MR3S_MASK (0x800U)
1829#define CTIMER_MCR_MR3S_SHIFT (11U)
1830/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled.
1831 */
1832#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
1833#define CTIMER_MCR_MR0RL_MASK (0x1000000U)
1834#define CTIMER_MCR_MR0RL_SHIFT (24U)
1835/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
1836 * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.
1837 */
1838#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
1839#define CTIMER_MCR_MR1RL_MASK (0x2000000U)
1840#define CTIMER_MCR_MR1RL_SHIFT (25U)
1841/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
1842 * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.
1843 */
1844#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
1845#define CTIMER_MCR_MR2RL_MASK (0x4000000U)
1846#define CTIMER_MCR_MR2RL_SHIFT (26U)
1847/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
1848 * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.
1849 */
1850#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
1851#define CTIMER_MCR_MR3RL_MASK (0x8000000U)
1852#define CTIMER_MCR_MR3RL_SHIFT (27U)
1853/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
1854 * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.
1855 */
1856#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
1857/*! @} */
1858
1859/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
1860/*! @{ */
1861#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
1862#define CTIMER_MR_MATCH_SHIFT (0U)
1863/*! MATCH - Timer counter match value.
1864 */
1865#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
1866/*! @} */
1867
1868/* The count of CTIMER_MR */
1869#define CTIMER_MR_COUNT (4U)
1870
1871/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
1872/*! @{ */
1873#define CTIMER_CCR_CAP0RE_MASK (0x1U)
1874#define CTIMER_CCR_CAP0RE_SHIFT (0U)
1875/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
1876 * the contents of TC. 0 = disabled. 1 = enabled.
1877 */
1878#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
1879#define CTIMER_CCR_CAP0FE_MASK (0x2U)
1880#define CTIMER_CCR_CAP0FE_SHIFT (1U)
1881/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
1882 * the contents of TC. 0 = disabled. 1 = enabled.
1883 */
1884#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
1885#define CTIMER_CCR_CAP0I_MASK (0x4U)
1886#define CTIMER_CCR_CAP0I_SHIFT (2U)
1887/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
1888 */
1889#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
1890#define CTIMER_CCR_CAP1RE_MASK (0x8U)
1891#define CTIMER_CCR_CAP1RE_SHIFT (3U)
1892/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
1893 * the contents of TC. 0 = disabled. 1 = enabled.
1894 */
1895#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
1896#define CTIMER_CCR_CAP1FE_MASK (0x10U)
1897#define CTIMER_CCR_CAP1FE_SHIFT (4U)
1898/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
1899 * the contents of TC. 0 = disabled. 1 = enabled.
1900 */
1901#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
1902#define CTIMER_CCR_CAP1I_MASK (0x20U)
1903#define CTIMER_CCR_CAP1I_SHIFT (5U)
1904/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
1905 */
1906#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
1907#define CTIMER_CCR_CAP2RE_MASK (0x40U)
1908#define CTIMER_CCR_CAP2RE_SHIFT (6U)
1909/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
1910 * the contents of TC. 0 = disabled. 1 = enabled.
1911 */
1912#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
1913#define CTIMER_CCR_CAP2FE_MASK (0x80U)
1914#define CTIMER_CCR_CAP2FE_SHIFT (7U)
1915/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
1916 * the contents of TC. 0 = disabled. 1 = enabled.
1917 */
1918#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
1919#define CTIMER_CCR_CAP2I_MASK (0x100U)
1920#define CTIMER_CCR_CAP2I_SHIFT (8U)
1921/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
1922 */
1923#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
1924#define CTIMER_CCR_CAP3RE_MASK (0x200U)
1925#define CTIMER_CCR_CAP3RE_SHIFT (9U)
1926/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with
1927 * the contents of TC. 0 = disabled. 1 = enabled.
1928 */
1929#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
1930#define CTIMER_CCR_CAP3FE_MASK (0x400U)
1931#define CTIMER_CCR_CAP3FE_SHIFT (10U)
1932/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with
1933 * the contents of TC. 0 = disabled. 1 = enabled.
1934 */
1935#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
1936#define CTIMER_CCR_CAP3I_MASK (0x800U)
1937#define CTIMER_CCR_CAP3I_SHIFT (11U)
1938/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
1939 */
1940#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
1941/*! @} */
1942
1943/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
1944/*! @{ */
1945#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
1946#define CTIMER_CR_CAP_SHIFT (0U)
1947/*! CAP - Timer counter capture value.
1948 */
1949#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
1950/*! @} */
1951
1952/* The count of CTIMER_CR */
1953#define CTIMER_CR_COUNT (4U)
1954
1955/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
1956/*! @{ */
1957#define CTIMER_EMR_EM0_MASK (0x1U)
1958#define CTIMER_EMR_EM0_SHIFT (0U)
1959/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
1960 * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
1961 * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
1962 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1963 */
1964#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
1965#define CTIMER_EMR_EM1_MASK (0x2U)
1966#define CTIMER_EMR_EM1_SHIFT (1U)
1967/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
1968 * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
1969 * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
1970 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1971 */
1972#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
1973#define CTIMER_EMR_EM2_MASK (0x4U)
1974#define CTIMER_EMR_EM2_SHIFT (2U)
1975/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
1976 * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
1977 * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
1978 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1979 */
1980#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
1981#define CTIMER_EMR_EM3_MASK (0x8U)
1982#define CTIMER_EMR_EM3_SHIFT (3U)
1983/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
1984 * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
1985 * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
1986 * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1987 */
1988#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
1989#define CTIMER_EMR_EMC0_MASK (0x30U)
1990#define CTIMER_EMR_EMC0_SHIFT (4U)
1991/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
1992 * 0b00..Do Nothing.
1993 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
1994 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
1995 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
1996 */
1997#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
1998#define CTIMER_EMR_EMC1_MASK (0xC0U)
1999#define CTIMER_EMR_EMC1_SHIFT (6U)
2000/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
2001 * 0b00..Do Nothing.
2002 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
2003 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
2004 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
2005 */
2006#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
2007#define CTIMER_EMR_EMC2_MASK (0x300U)
2008#define CTIMER_EMR_EMC2_SHIFT (8U)
2009/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
2010 * 0b00..Do Nothing.
2011 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
2012 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
2013 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
2014 */
2015#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
2016#define CTIMER_EMR_EMC3_MASK (0xC00U)
2017#define CTIMER_EMR_EMC3_SHIFT (10U)
2018/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
2019 * 0b00..Do Nothing.
2020 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
2021 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
2022 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
2023 */
2024#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
2025/*! @} */
2026
2027/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
2028/*! @{ */
2029#define CTIMER_CTCR_CTMODE_MASK (0x3U)
2030#define CTIMER_CTCR_CTMODE_SHIFT (0U)
2031/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
2032 * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
2033 * is incremented when the Prescale Counter matches the Prescale Register.
2034 * 0b00..Timer Mode. Incremented every rising APB bus clock edge.
2035 * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
2036 * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
2037 * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
2038 */
2039#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
2040#define CTIMER_CTCR_CINSEL_MASK (0xCU)
2041#define CTIMER_CTCR_CINSEL_SHIFT (2U)
2042/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
2043 * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
2044 * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
2045 * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
2046 * same timer.
2047 * 0b00..Channel 0. CAPn.0 for CTIMERn
2048 * 0b01..Channel 1. CAPn.1 for CTIMERn
2049 * 0b10..Channel 2. CAPn.2 for CTIMERn
2050 * 0b11..Channel 3. CAPn.3 for CTIMERn
2051 */
2052#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
2053#define CTIMER_CTCR_ENCC_MASK (0x10U)
2054#define CTIMER_CTCR_ENCC_SHIFT (4U)
2055/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
2056 * capture-edge event specified in bits 7:5 occurs.
2057 */
2058#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
2059#define CTIMER_CTCR_SELCC_MASK (0xE0U)
2060#define CTIMER_CTCR_SELCC_SHIFT (5U)
2061/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
2062 * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
2063 * 0x3 and 0x6 to 0x7 are reserved.
2064 * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
2065 * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
2066 * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
2067 * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
2068 * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
2069 * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
2070 * 0b110..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
2071 * 0b111..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
2072 */
2073#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
2074/*! @} */
2075
2076/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
2077/*! @{ */
2078#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
2079#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
2080/*! PWMEN0 - PWM mode enable for channel0.
2081 * 0b0..Match. CTIMERn_MAT0 is controlled by EM0.
2082 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
2083 */
2084#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
2085#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
2086#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
2087/*! PWMEN1 - PWM mode enable for channel1.
2088 * 0b0..Match. CTIMERn_MAT01 is controlled by EM1.
2089 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
2090 */
2091#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
2092#define CTIMER_PWMC_PWMEN2_MASK (0x4U)
2093#define CTIMER_PWMC_PWMEN2_SHIFT (2U)
2094/*! PWMEN2 - PWM mode enable for channel2.
2095 * 0b0..Match. CTIMERn_MAT2 is controlled by EM2.
2096 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
2097 */
2098#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
2099#define CTIMER_PWMC_PWMEN3_MASK (0x8U)
2100#define CTIMER_PWMC_PWMEN3_SHIFT (3U)
2101/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
2102 * 0b0..Match. CTIMERn_MAT3 is controlled by EM3.
2103 * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
2104 */
2105#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
2106/*! @} */
2107
2108/*! @name MSR - Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero. */
2109/*! @{ */
2110#define CTIMER_MSR_MATCH_SHADOW_MASK (0xFFFFFFFFU)
2111#define CTIMER_MSR_MATCH_SHADOW_SHIFT (0U)
2112/*! MATCH_SHADOW - Timer counter match value.
2113 */
2114#define CTIMER_MSR_MATCH_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK)
2115/*! @} */
2116
2117/* The count of CTIMER_MSR */
2118#define CTIMER_MSR_COUNT (4U)
2119
2120
2121/*!
2122 * @}
2123 */ /* end of group CTIMER_Register_Masks */
2124
2125
2126/* CTIMER - Peripheral instance base addresses */
2127/** Peripheral CTIMER0 base address */
2128#define CTIMER0_BASE (0x40038000u)
2129/** Peripheral CTIMER0 base pointer */
2130#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
2131/** Array initializer of CTIMER peripheral base addresses */
2132#define CTIMER_BASE_ADDRS { CTIMER0_BASE }
2133/** Array initializer of CTIMER peripheral base pointers */
2134#define CTIMER_BASE_PTRS { CTIMER0 }
2135/** Interrupt vectors for the CTIMER peripheral type */
2136#define CTIMER_IRQS { CTIMER0_IRQn }
2137
2138/*!
2139 * @}
2140 */ /* end of group CTIMER_Peripheral_Access_Layer */
2141
2142
2143/* ----------------------------------------------------------------------------
2144 -- DAC Peripheral Access Layer
2145 ---------------------------------------------------------------------------- */
2146
2147/*!
2148 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
2149 * @{
2150 */
2151
2152/** DAC - Register Layout Typedef */
2153typedef struct {
2154 __IO uint32_t CR; /**< D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit., offset: 0x0 */
2155 __IO uint32_t CTRL; /**< DAC Control register. This register controls DMA and timer operation., offset: 0x4 */
2156 __IO uint32_t CNTVAL; /**< DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer., offset: 0x8 */
2157} DAC_Type;
2158
2159/* ----------------------------------------------------------------------------
2160 -- DAC Register Masks
2161 ---------------------------------------------------------------------------- */
2162
2163/*!
2164 * @addtogroup DAC_Register_Masks DAC Register Masks
2165 * @{
2166 */
2167
2168/*! @name CR - D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit. */
2169/*! @{ */
2170#define DAC_CR_VALUE_MASK (0xFFC0U)
2171#define DAC_CR_VALUE_SHIFT (6U)
2172/*! VALUE - After the selected settling time after this field is written with a new VALUE, the
2173 * voltage on the DAC_OUT pin (with respect to VSSA) is VALUE (VREFP - VREFN)/1024 + VREFN.
2174 */
2175#define DAC_CR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_VALUE_SHIFT)) & DAC_CR_VALUE_MASK)
2176#define DAC_CR_BIAS_MASK (0x10000U)
2177#define DAC_CR_BIAS_SHIFT (16U)
2178/*! BIAS - The settling time of the DAC
2179 * 0b0..The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz.
2180 * 0b1..The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz.
2181 */
2182#define DAC_CR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_BIAS_SHIFT)) & DAC_CR_BIAS_MASK)
2183/*! @} */
2184
2185/*! @name CTRL - DAC Control register. This register controls DMA and timer operation. */
2186/*! @{ */
2187#define DAC_CTRL_INT_DMA_REQ_MASK (0x1U)
2188#define DAC_CTRL_INT_DMA_REQ_SHIFT (0U)
2189/*! INT_DMA_REQ - DMA request
2190 * 0b0..This bit is cleared on any write to the DACR register.
2191 * 0b1..This bit is set by hardware when the timer times out.
2192 */
2193#define DAC_CTRL_INT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_INT_DMA_REQ_SHIFT)) & DAC_CTRL_INT_DMA_REQ_MASK)
2194#define DAC_CTRL_DBLBUF_ENA_MASK (0x2U)
2195#define DAC_CTRL_DBLBUF_ENA_SHIFT (1U)
2196/*! DBLBUF_ENA - dacr double buffer
2197 * 0b0..DACR double-buffering is disabled.
2198 * 0b1..When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be
2199 * enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the
2200 * next time-out of the counter.
2201 */
2202#define DAC_CTRL_DBLBUF_ENA(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_DBLBUF_ENA_SHIFT)) & DAC_CTRL_DBLBUF_ENA_MASK)
2203#define DAC_CTRL_CNT_ENA_MASK (0x4U)
2204#define DAC_CTRL_CNT_ENA_SHIFT (2U)
2205/*! CNT_ENA - time-out counter operation
2206 * 0b0..Time-out counter operation is disabled.
2207 * 0b1..Time-out counter operation is enabled.
2208 */
2209#define DAC_CTRL_CNT_ENA(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_CNT_ENA_SHIFT)) & DAC_CTRL_CNT_ENA_MASK)
2210#define DAC_CTRL_DMA_ENA_MASK (0x8U)
2211#define DAC_CTRL_DMA_ENA_SHIFT (3U)
2212/*! DMA_ENA - DMA access
2213 * 0b0..DMA access is disabled.
2214 * 0b1..DMA Burst Request Input 7 is enabled for the DAC
2215 */
2216#define DAC_CTRL_DMA_ENA(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_DMA_ENA_SHIFT)) & DAC_CTRL_DMA_ENA_MASK)
2217/*! @} */
2218
2219/*! @name CNTVAL - DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer. */
2220/*! @{ */
2221#define DAC_CNTVAL_VALUE_MASK (0xFFFFU)
2222#define DAC_CNTVAL_VALUE_SHIFT (0U)
2223/*! VALUE - 16-bit reload value for the DAC interrupt/DMA timer.
2224 */
2225#define DAC_CNTVAL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CNTVAL_VALUE_SHIFT)) & DAC_CNTVAL_VALUE_MASK)
2226/*! @} */
2227
2228
2229/*!
2230 * @}
2231 */ /* end of group DAC_Register_Masks */
2232
2233
2234/* DAC - Peripheral instance base addresses */
2235/** Peripheral DAC0 base address */
2236#define DAC0_BASE (0x40014000u)
2237/** Peripheral DAC0 base pointer */
2238#define DAC0 ((DAC_Type *)DAC0_BASE)
2239/** Peripheral DAC1 base address */
2240#define DAC1_BASE (0x40018000u)
2241/** Peripheral DAC1 base pointer */
2242#define DAC1 ((DAC_Type *)DAC1_BASE)
2243/** Array initializer of DAC peripheral base addresses */
2244#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
2245/** Array initializer of DAC peripheral base pointers */
2246#define DAC_BASE_PTRS { DAC0, DAC1 }
2247
2248/*!
2249 * @}
2250 */ /* end of group DAC_Peripheral_Access_Layer */
2251
2252
2253/* ----------------------------------------------------------------------------
2254 -- DMA Peripheral Access Layer
2255 ---------------------------------------------------------------------------- */
2256
2257/*!
2258 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
2259 * @{
2260 */
2261
2262/** DMA - Register Layout Typedef */
2263typedef struct {
2264 __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
2265 __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
2266 __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
2267 uint8_t RESERVED_0[20];
2268 struct { /* offset: 0x20, array step: 0x5C */
2269 __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
2270 uint8_t RESERVED_0[4];
2271 __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
2272 uint8_t RESERVED_1[4];
2273 __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
2274 uint8_t RESERVED_2[4];
2275 __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
2276 uint8_t RESERVED_3[4];
2277 __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
2278 uint8_t RESERVED_4[4];
2279 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
2280 uint8_t RESERVED_5[4];
2281 __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
2282 uint8_t RESERVED_6[4];
2283 __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
2284 uint8_t RESERVED_7[4];
2285 __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
2286 uint8_t RESERVED_8[4];
2287 __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
2288 uint8_t RESERVED_9[4];
2289 __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
2290 uint8_t RESERVED_10[4];
2291 __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
2292 } COMMON[1];
2293 uint8_t RESERVED_1[900];
2294 struct { /* offset: 0x400, array step: 0x10 */
2295 __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
2296 __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
2297 __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
2298 uint8_t RESERVED_0[4];
2299 } CHANNEL[25];
2300} DMA_Type;
2301
2302/* ----------------------------------------------------------------------------
2303 -- DMA Register Masks
2304 ---------------------------------------------------------------------------- */
2305
2306/*!
2307 * @addtogroup DMA_Register_Masks DMA Register Masks
2308 * @{
2309 */
2310
2311/*! @name CTRL - DMA control. */
2312/*! @{ */
2313#define DMA_CTRL_ENABLE_MASK (0x1U)
2314#define DMA_CTRL_ENABLE_SHIFT (0U)
2315/*! ENABLE - DMA controller master enable.
2316 * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
2317 * disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
2318 * 0b1..Enabled. The DMA controller is enabled.
2319 */
2320#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
2321/*! @} */
2322
2323/*! @name INTSTAT - Interrupt status. */
2324/*! @{ */
2325#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
2326#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
2327/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
2328 * 0b0..Not pending. No enabled interrupts are pending.
2329 * 0b1..Pending. At least one enabled interrupt is pending.
2330 */
2331#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
2332#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
2333#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
2334/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
2335 * 0b0..Not pending. No error interrupts are pending.
2336 * 0b1..Pending. At least one error interrupt is pending.
2337 */
2338#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
2339/*! @} */
2340
2341/*! @name SRAMBASE - SRAM address of the channel configuration table. */
2342/*! @{ */
2343#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
2344#define DMA_SRAMBASE_OFFSET_SHIFT (9U)
2345/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
2346 * table must begin on a 512 byte boundary.
2347 */
2348#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
2349/*! @} */
2350
2351/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
2352/*! @{ */
2353#define DMA_COMMON_ENABLESET_ENA_MASK (0x1FFFFFFU)
2354#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
2355/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
2356 * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
2357 */
2358#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
2359/*! @} */
2360
2361/* The count of DMA_COMMON_ENABLESET */
2362#define DMA_COMMON_ENABLESET_COUNT (1U)
2363
2364/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
2365/*! @{ */
2366#define DMA_COMMON_ENABLECLR_CLR_MASK (0x1FFFFFFU)
2367#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
2368/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
2369 * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
2370 * are reserved.
2371 */
2372#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
2373/*! @} */
2374
2375/* The count of DMA_COMMON_ENABLECLR */
2376#define DMA_COMMON_ENABLECLR_COUNT (1U)
2377
2378/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
2379/*! @{ */
2380#define DMA_COMMON_ACTIVE_ACT_MASK (0x1FFFFFFU)
2381#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
2382/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
2383 * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
2384 */
2385#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
2386/*! @} */
2387
2388/* The count of DMA_COMMON_ACTIVE */
2389#define DMA_COMMON_ACTIVE_COUNT (1U)
2390
2391/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
2392/*! @{ */
2393#define DMA_COMMON_BUSY_BSY_MASK (0x1FFFFFFU)
2394#define DMA_COMMON_BUSY_BSY_SHIFT (0U)
2395/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
2396 * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
2397 */
2398#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
2399/*! @} */
2400
2401/* The count of DMA_COMMON_BUSY */
2402#define DMA_COMMON_BUSY_COUNT (1U)
2403
2404/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
2405/*! @{ */
2406#define DMA_COMMON_ERRINT_ERR_MASK (0x1FFFFFFU)
2407#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
2408/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
2409 * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
2410 * not active. 1 = error interrupt is active.
2411 */
2412#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
2413/*! @} */
2414
2415/* The count of DMA_COMMON_ERRINT */
2416#define DMA_COMMON_ERRINT_COUNT (1U)
2417
2418/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
2419/*! @{ */
2420#define DMA_COMMON_INTENSET_INTEN_MASK (0x1FFFFFFU)
2421#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
2422/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
2423 * number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
2424 * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
2425 */
2426#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
2427/*! @} */
2428
2429/* The count of DMA_COMMON_INTENSET */
2430#define DMA_COMMON_INTENSET_COUNT (1U)
2431
2432/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
2433/*! @{ */
2434#define DMA_COMMON_INTENCLR_CLR_MASK (0x1FFFFFFU)
2435#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
2436/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
2437 * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
2438 * reserved.
2439 */
2440#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
2441/*! @} */
2442
2443/* The count of DMA_COMMON_INTENCLR */
2444#define DMA_COMMON_INTENCLR_COUNT (1U)
2445
2446/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
2447/*! @{ */
2448#define DMA_COMMON_INTA_IA_MASK (0x1FFFFFFU)
2449#define DMA_COMMON_INTA_IA_SHIFT (0U)
2450/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
2451 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
2452 * interrupt A is not active. 1 = the DMA channel interrupt A is active.
2453 */
2454#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
2455/*! @} */
2456
2457/* The count of DMA_COMMON_INTA */
2458#define DMA_COMMON_INTA_COUNT (1U)
2459
2460/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
2461/*! @{ */
2462#define DMA_COMMON_INTB_IB_MASK (0x1FFFFFFU)
2463#define DMA_COMMON_INTB_IB_SHIFT (0U)
2464/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
2465 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
2466 * interrupt B is not active. 1 = the DMA channel interrupt B is active.
2467 */
2468#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
2469/*! @} */
2470
2471/* The count of DMA_COMMON_INTB */
2472#define DMA_COMMON_INTB_COUNT (1U)
2473
2474/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
2475/*! @{ */
2476#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)
2477#define DMA_COMMON_SETVALID_SV_SHIFT (0U)
2478/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
2479 * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
2480 * VALIDPENDING control bit for DMA channel n
2481 */
2482#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
2483/*! @} */
2484
2485/* The count of DMA_COMMON_SETVALID */
2486#define DMA_COMMON_SETVALID_COUNT (1U)
2487
2488/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
2489/*! @{ */
2490#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)
2491#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
2492/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
2493 * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
2494 * sets the TRIG bit for DMA channel n.
2495 */
2496#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
2497/*! @} */
2498
2499/* The count of DMA_COMMON_SETTRIG */
2500#define DMA_COMMON_SETTRIG_COUNT (1U)
2501
2502/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
2503/*! @{ */
2504#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)
2505#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
2506/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
2507 * 1 = aborts DMA operations on channel n.
2508 */
2509#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
2510/*! @} */
2511
2512/* The count of DMA_COMMON_ABORT */
2513#define DMA_COMMON_ABORT_COUNT (1U)
2514
2515/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
2516/*! @{ */
2517#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
2518#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
2519/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
2520 * move, any peripheral DMA request associated with that channel can be disabled to prevent any
2521 * interaction between the peripheral and the DMA controller.
2522 * 0b0..Disabled. Peripheral DMA requests are disabled.
2523 * 0b1..Enabled. Peripheral DMA requests are enabled.
2524 */
2525#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
2526#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
2527#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
2528/*! HWTRIGEN - Hardware Triggering Enable for this channel.
2529 * 0b0..Disabled. Hardware triggering is not used.
2530 * 0b1..Enabled. Use hardware triggering.
2531 */
2532#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
2533#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
2534#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
2535/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
2536 * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
2537 * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
2538 */
2539#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
2540#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
2541#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
2542/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
2543 * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
2544 * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
2545 * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
2546 * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
2547 * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
2548 * current BURSTPOWER length are completed.
2549 */
2550#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
2551#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
2552#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
2553/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
2554 * 0b0..Single transfer. Hardware trigger causes a single transfer.
2555 * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
2556 * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a
2557 * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
2558 * complete.
2559 */
2560#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
2561#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
2562#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
2563/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
2564 * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
2565 * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
2566 * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that
2567 * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:
2568 * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =
2569 * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The
2570 * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
2571 * multiple of the burst size.
2572 */
2573#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
2574#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
2575#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
2576/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
2577 * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this
2578 * could be used to read several sequential registers from a peripheral for each DMA burst,
2579 * reading the same registers again for each burst.
2580 * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
2581 * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
2582 */
2583#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
2584#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
2585#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
2586/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
2587 * 'wrapped', meaning that the destination address range for each burst will be the same. As an
2588 * example, this could be used to write several sequential registers to a peripheral for each DMA
2589 * burst, writing the same registers again for each burst.
2590 * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
2591 * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
2592 */
2593#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
2594#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
2595#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
2596/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority
2597 * levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
2598 */
2599#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
2600/*! @} */
2601
2602/* The count of DMA_CHANNEL_CFG */
2603#define DMA_CHANNEL_CFG_COUNT (25U)
2604
2605/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
2606/*! @{ */
2607#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
2608#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
2609/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the
2610 * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
2611 * 0b0..No effect. No effect on DMA operation.
2612 * 0b1..Valid pending.
2613 */
2614#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
2615#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
2616#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
2617/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is
2618 * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2619 * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
2620 * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
2621 */
2622#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
2623/*! @} */
2624
2625/* The count of DMA_CHANNEL_CTLSTAT */
2626#define DMA_CHANNEL_CTLSTAT_COUNT (25U)
2627
2628/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
2629/*! @{ */
2630#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
2631#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
2632/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor
2633 * is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
2634 * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
2635 * 0b1..Valid. The current channel descriptor is considered valid.
2636 */
2637#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
2638#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
2639#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
2640/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current
2641 * descriptor is exhausted. Reloading allows ping-pong and linked transfers.
2642 * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
2643 * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.
2644 */
2645#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
2646#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
2647#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
2648/*! SWTRIG - Software Trigger.
2649 * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by
2650 * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
2651 * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not
2652 * be used with level triggering when TRIGBURST = 0.
2653 */
2654#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
2655#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)
2656#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)
2657/*! CLRTRIG - Clear Trigger.
2658 * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
2659 * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted
2660 */
2661#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
2662#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)
2663#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)
2664/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between
2665 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
2666 * convention, interrupt A may be used when only one interrupt flag is needed.
2667 * 0b0..No effect.
2668 * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
2669 */
2670#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
2671#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)
2672#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)
2673/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between
2674 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
2675 * convention, interrupt A may be used when only one interrupt flag is needed.
2676 * 0b0..No effect.
2677 * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
2678 */
2679#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
2680#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)
2681#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)
2682/*! WIDTH - Transfer width used for this DMA channel.
2683 * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
2684 * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
2685 * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
2686 * 0b11..Reserved. Reserved setting, do not use.
2687 */
2688#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
2689#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)
2690#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)
2691/*! SRCINC - Determines whether the source address is incremented for each DMA transfer.
2692 * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
2693 * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is
2694 * the usual case when the source is memory.
2695 * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
2696 * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
2697 */
2698#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
2699#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)
2700#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)
2701/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer.
2702 * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when
2703 * the destination is a peripheral device.
2704 * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer.
2705 * This is the usual case when the destination is memory.
2706 * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
2707 * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
2708 */
2709#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
2710#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)
2711#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)
2712/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes
2713 * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller
2714 * uses this bit field during transfer to count down. Hence, it cannot be used by software to read
2715 * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1
2716 * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of
2717 * 1,024 transfers will be performed.
2718 */
2719#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
2720/*! @} */
2721
2722/* The count of DMA_CHANNEL_XFERCFG */
2723#define DMA_CHANNEL_XFERCFG_COUNT (25U)
2724
2725
2726/*!
2727 * @}
2728 */ /* end of group DMA_Register_Masks */
2729
2730
2731/* DMA - Peripheral instance base addresses */
2732/** Peripheral DMA0 base address */
2733#define DMA0_BASE (0x50008000u)
2734/** Peripheral DMA0 base pointer */
2735#define DMA0 ((DMA_Type *)DMA0_BASE)
2736/** Array initializer of DMA peripheral base addresses */
2737#define DMA_BASE_ADDRS { DMA0_BASE }
2738/** Array initializer of DMA peripheral base pointers */
2739#define DMA_BASE_PTRS { DMA0 }
2740/** Interrupt vectors for the DMA peripheral type */
2741#define DMA_IRQS { DMA0_IRQn }
2742
2743/*!
2744 * @}
2745 */ /* end of group DMA_Peripheral_Access_Layer */
2746
2747
2748/* ----------------------------------------------------------------------------
2749 -- FLASH_CTRL Peripheral Access Layer
2750 ---------------------------------------------------------------------------- */
2751
2752/*!
2753 * @addtogroup FLASH_CTRL_Peripheral_Access_Layer FLASH_CTRL Peripheral Access Layer
2754 * @{
2755 */
2756
2757/** FLASH_CTRL - Register Layout Typedef */
2758typedef struct {
2759 uint8_t RESERVED_0[16];
2760 __IO uint32_t FLASHCFG; /**< Flash configuration register, offset: 0x10 */
2761 uint8_t RESERVED_1[12];
2762 __IO uint32_t FMSSTART; /**< Flash signature start address register, offset: 0x20 */
2763 __IO uint32_t FMSSTOP; /**< Flash signaure stop address register, offset: 0x24 */
2764 uint8_t RESERVED_2[4];
2765 __I uint32_t FMSW0; /**< Flash signature generation result register returns the flash signature produced by the embedded signature generator.., offset: 0x2C */
2766 uint8_t RESERVED_3[4016];
2767 __I uint32_t FMSTAT; /**< Flash signature generation status bit, offset: 0xFE0 */
2768 uint8_t RESERVED_4[4];
2769 __O uint32_t FMSTATCLR; /**< Clear FLASH signature generation status bit, offset: 0xFE8 */
2770} FLASH_CTRL_Type;
2771
2772/* ----------------------------------------------------------------------------
2773 -- FLASH_CTRL Register Masks
2774 ---------------------------------------------------------------------------- */
2775
2776/*!
2777 * @addtogroup FLASH_CTRL_Register_Masks FLASH_CTRL Register Masks
2778 * @{
2779 */
2780
2781/*! @name FLASHCFG - Flash configuration register */
2782/*! @{ */
2783#define FLASH_CTRL_FLASHCFG_FLASHTIM_MASK (0x3U)
2784#define FLASH_CTRL_FLASHCFG_FLASHTIM_SHIFT (0U)
2785/*! FLASHTIM - Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
2786 * 0b00..1 system clock flash access time.
2787 * 0b01..2 system clock flash access time.
2788 * 0b10..3 system clock flash access time.
2789 * 0b11..Reserved.
2790 */
2791#define FLASH_CTRL_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FLASHCFG_FLASHTIM_SHIFT)) & FLASH_CTRL_FLASHCFG_FLASHTIM_MASK)
2792/*! @} */
2793
2794/*! @name FMSSTART - Flash signature start address register */
2795/*! @{ */
2796#define FLASH_CTRL_FMSSTART_START_MASK (0x1FFFFU)
2797#define FLASH_CTRL_FMSSTART_START_SHIFT (0U)
2798/*! START - Signature generation start address (corresponds to AHB byte address bits[18:2]).
2799 */
2800#define FLASH_CTRL_FMSSTART_START(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTART_START_SHIFT)) & FLASH_CTRL_FMSSTART_START_MASK)
2801/*! @} */
2802
2803/*! @name FMSSTOP - Flash signaure stop address register */
2804/*! @{ */
2805#define FLASH_CTRL_FMSSTOP_STOPA_MASK (0x1FFFFU)
2806#define FLASH_CTRL_FMSSTOP_STOPA_SHIFT (0U)
2807/*! STOPA - Stop address for signature generation (the word specified by STOP is included in the
2808 * address range). The address is in units of memory words, not bytes.
2809 */
2810#define FLASH_CTRL_FMSSTOP_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTOP_STOPA_SHIFT)) & FLASH_CTRL_FMSSTOP_STOPA_MASK)
2811#define FLASH_CTRL_FMSSTOP_STRTBIST_MASK (0x80000000U)
2812#define FLASH_CTRL_FMSSTOP_STRTBIST_SHIFT (31U)
2813/*! STRTBIST - When this bit is written to 1, signature generation starts. At the end of signature
2814 * generation, this bit is automatically cleared.
2815 */
2816#define FLASH_CTRL_FMSSTOP_STRTBIST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTOP_STRTBIST_SHIFT)) & FLASH_CTRL_FMSSTOP_STRTBIST_MASK)
2817/*! @} */
2818
2819/*! @name FMSW0 - Flash signature generation result register returns the flash signature produced by the embedded signature generator.. */
2820/*! @{ */
2821#define FLASH_CTRL_FMSW0_SIG_MASK (0xFFFFFFFFU)
2822#define FLASH_CTRL_FMSW0_SIG_SHIFT (0U)
2823/*! SIG - 32-bit signature.
2824 */
2825#define FLASH_CTRL_FMSW0_SIG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSW0_SIG_SHIFT)) & FLASH_CTRL_FMSW0_SIG_MASK)
2826/*! @} */
2827
2828/*! @name FMSTAT - Flash signature generation status bit */
2829/*! @{ */
2830#define FLASH_CTRL_FMSTAT_SIG_DONE_MASK (0x2U)
2831#define FLASH_CTRL_FMSTAT_SIG_DONE_SHIFT (1U)
2832/*! SIG_DONE - This status bit is set at the end of signature computation
2833 */
2834#define FLASH_CTRL_FMSTAT_SIG_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSTAT_SIG_DONE_SHIFT)) & FLASH_CTRL_FMSTAT_SIG_DONE_MASK)
2835/*! @} */
2836
2837/*! @name FMSTATCLR - Clear FLASH signature generation status bit */
2838/*! @{ */
2839#define FLASH_CTRL_FMSTATCLR_SIG_DONE_CLR_MASK (0x2U)
2840#define FLASH_CTRL_FMSTATCLR_SIG_DONE_CLR_SHIFT (1U)
2841/*! SIG_DONE_CLR - When the bit is written to 1, the SIGNATURE_DONE bit is cleared.
2842 */
2843#define FLASH_CTRL_FMSTATCLR_SIG_DONE_CLR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSTATCLR_SIG_DONE_CLR_SHIFT)) & FLASH_CTRL_FMSTATCLR_SIG_DONE_CLR_MASK)
2844/*! @} */
2845
2846
2847/*!
2848 * @}
2849 */ /* end of group FLASH_CTRL_Register_Masks */
2850
2851
2852/* FLASH_CTRL - Peripheral instance base addresses */
2853/** Peripheral FLASH_CTRL base address */
2854#define FLASH_CTRL_BASE (0x40040000u)
2855/** Peripheral FLASH_CTRL base pointer */
2856#define FLASH_CTRL ((FLASH_CTRL_Type *)FLASH_CTRL_BASE)
2857/** Array initializer of FLASH_CTRL peripheral base addresses */
2858#define FLASH_CTRL_BASE_ADDRS { FLASH_CTRL_BASE }
2859/** Array initializer of FLASH_CTRL peripheral base pointers */
2860#define FLASH_CTRL_BASE_PTRS { FLASH_CTRL }
2861/** Interrupt vectors for the FLASH_CTRL peripheral type */
2862#define FLASH_CTRL_IRQS { FLASH_IRQn }
2863
2864/*!
2865 * @}
2866 */ /* end of group FLASH_CTRL_Peripheral_Access_Layer */
2867
2868
2869/* ----------------------------------------------------------------------------
2870 -- GPIO Peripheral Access Layer
2871 ---------------------------------------------------------------------------- */
2872
2873/*!
2874 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
2875 * @{
2876 */
2877
2878/** GPIO - Register Layout Typedef */
2879typedef struct {
2880 __IO uint8_t B[2][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
2881 uint8_t RESERVED_0[4032];
2882 __IO uint32_t W[2][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
2883 uint8_t RESERVED_1[3840];
2884 __IO uint32_t DIR[2]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */
2885 uint8_t RESERVED_2[120];
2886 __IO uint32_t MASK[2]; /**< Mask register, array offset: 0x2080, array step: 0x4 */
2887 uint8_t RESERVED_3[120];
2888 __IO uint32_t PIN[2]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */
2889 uint8_t RESERVED_4[120];
2890 __IO uint32_t MPIN[2]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */
2891 uint8_t RESERVED_5[120];
2892 __IO uint32_t SET[2]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
2893 uint8_t RESERVED_6[120];
2894 __O uint32_t CLR[2]; /**< Clear port, array offset: 0x2280, array step: 0x4 */
2895 uint8_t RESERVED_7[120];
2896 __O uint32_t NOT[2]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */
2897 uint8_t RESERVED_8[120];
2898 __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
2899 uint8_t RESERVED_9[120];
2900 __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
2901 uint8_t RESERVED_10[120];
2902 __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
2903} GPIO_Type;
2904
2905/* ----------------------------------------------------------------------------
2906 -- GPIO Register Masks
2907 ---------------------------------------------------------------------------- */
2908
2909/*!
2910 * @addtogroup GPIO_Register_Masks GPIO Register Masks
2911 * @{
2912 */
2913
2914/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
2915/*! @{ */
2916#define GPIO_B_PBYTE_MASK (0x1U)
2917#define GPIO_B_PBYTE_SHIFT (0U)
2918/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function,
2919 * except that pins configured as analog I/O always read as 0. One register for each port pin.
2920 * Supported pins depends on the specific device and package. Write: loads the pin's output bit.
2921 * One register for each port pin. Supported pins depends on the specific device and package.
2922 */
2923#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
2924/*! @} */
2925
2926/* The count of GPIO_B */
2927#define GPIO_B_COUNT (2U)
2928
2929/* The count of GPIO_B */
2930#define GPIO_B_COUNT2 (32U)
2931
2932/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
2933/*! @{ */
2934#define GPIO_W_PWORD_MASK (0xFFFFFFFFU)
2935#define GPIO_W_PWORD_SHIFT (0U)
2936/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is
2937 * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be
2938 * read. Writing any value other than 0 will set the output bit. One register for each port pin.
2939 * Supported pins depends on the specific device and package.
2940 */
2941#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
2942/*! @} */
2943
2944/* The count of GPIO_W */
2945#define GPIO_W_COUNT (2U)
2946
2947/* The count of GPIO_W */
2948#define GPIO_W_COUNT2 (32U)
2949
2950/*! @name DIR - Direction registers */
2951/*! @{ */
2952#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU)
2953#define GPIO_DIR_DIRP_SHIFT (0U)
2954/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
2955 * pins depends on the specific device and package. 0 = input. 1 = output.
2956 */
2957#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
2958/*! @} */
2959
2960/* The count of GPIO_DIR */
2961#define GPIO_DIR_COUNT (2U)
2962
2963/*! @name MASK - Mask register */
2964/*! @{ */
2965#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU)
2966#define GPIO_MASK_MASKP_SHIFT (0U)
2967/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 =
2968 * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 =
2969 * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit
2970 * not affected.
2971 */
2972#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
2973/*! @} */
2974
2975/* The count of GPIO_MASK */
2976#define GPIO_MASK_COUNT (2U)
2977
2978/*! @name PIN - Port pin register */
2979/*! @{ */
2980#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU)
2981#define GPIO_PIN_PORT_SHIFT (0U)
2982/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
2983 * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit.
2984 * 1 = Read: pin is high; write: set output bit.
2985 */
2986#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
2987/*! @} */
2988
2989/* The count of GPIO_PIN */
2990#define GPIO_PIN_COUNT (2U)
2991
2992/*! @name MPIN - Masked port register */
2993/*! @{ */
2994#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU)
2995#define GPIO_MPIN_MPORTP_SHIFT (0U)
2996/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
2997 * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK
2998 * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1
2999 * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit
3000 * if the corresponding bit in the MASK register is 0.
3001 */
3002#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
3003/*! @} */
3004
3005/* The count of GPIO_MPIN */
3006#define GPIO_MPIN_COUNT (2U)
3007
3008/*! @name SET - Write: Set register for port Read: output bits for port */
3009/*! @{ */
3010#define GPIO_SET_SETP_MASK (0xFFFFFFFFU)
3011#define GPIO_SET_SETP_SHIFT (0U)
3012/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
3013 * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output
3014 * bit; write: set output bit.
3015 */
3016#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
3017/*! @} */
3018
3019/* The count of GPIO_SET */
3020#define GPIO_SET_COUNT (2U)
3021
3022/*! @name CLR - Clear port */
3023/*! @{ */
3024#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU)
3025#define GPIO_CLR_CLRP_SHIFT (0U)
3026/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
3027 * specific device and package. 0 = No operation. 1 = Clear output bit.
3028 */
3029#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
3030/*! @} */
3031
3032/* The count of GPIO_CLR */
3033#define GPIO_CLR_COUNT (2U)
3034
3035/*! @name NOT - Toggle port */
3036/*! @{ */
3037#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU)
3038#define GPIO_NOT_NOTP_SHIFT (0U)
3039/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
3040 * specific device and package. 0 = no operation. 1 = Toggle output bit.
3041 */
3042#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
3043/*! @} */
3044
3045/* The count of GPIO_NOT */
3046#define GPIO_NOT_COUNT (2U)
3047
3048/*! @name DIRSET - Set pin direction bits for port */
3049/*! @{ */
3050#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU)
3051#define GPIO_DIRSET_DIRSETP_SHIFT (0U)
3052/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
3053 * the specific device and package. 0 = No operation. 1 = Set direction bit.
3054 */
3055#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
3056/*! @} */
3057
3058/* The count of GPIO_DIRSET */
3059#define GPIO_DIRSET_COUNT (2U)
3060
3061/*! @name DIRCLR - Clear pin direction bits for port */
3062/*! @{ */
3063#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU)
3064#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U)
3065/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
3066 * the specific device and package. 0 = No operation. 1 = Clear direction bit.
3067 */
3068#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
3069/*! @} */
3070
3071/* The count of GPIO_DIRCLR */
3072#define GPIO_DIRCLR_COUNT (2U)
3073
3074/*! @name DIRNOT - Toggle pin direction bits for port */
3075/*! @{ */
3076#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU)
3077#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U)
3078/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends
3079 * on the specific device and package. 0 = no operation. 1 = Toggle direction bit.
3080 */
3081#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
3082/*! @} */
3083
3084/* The count of GPIO_DIRNOT */
3085#define GPIO_DIRNOT_COUNT (2U)
3086
3087
3088/*!
3089 * @}
3090 */ /* end of group GPIO_Register_Masks */
3091
3092
3093/* GPIO - Peripheral instance base addresses */
3094/** Peripheral GPIO base address */
3095#define GPIO_BASE (0xA0000000u)
3096/** Peripheral GPIO base pointer */
3097#define GPIO ((GPIO_Type *)GPIO_BASE)
3098/** Array initializer of GPIO peripheral base addresses */
3099#define GPIO_BASE_ADDRS { GPIO_BASE }
3100/** Array initializer of GPIO peripheral base pointers */
3101#define GPIO_BASE_PTRS { GPIO }
3102
3103/*!
3104 * @}
3105 */ /* end of group GPIO_Peripheral_Access_Layer */
3106
3107
3108/* ----------------------------------------------------------------------------
3109 -- I2C Peripheral Access Layer
3110 ---------------------------------------------------------------------------- */
3111
3112/*!
3113 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
3114 * @{
3115 */
3116
3117/** I2C - Register Layout Typedef */
3118typedef struct {
3119 __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x0 */
3120 __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x4 */
3121 __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x8 */
3122 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0xC */
3123 __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x10 */
3124 __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x14 */
3125 __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x18 */
3126 uint8_t RESERVED_0[4];
3127 __IO uint32_t MSTCTL; /**< Master control register., offset: 0x20 */
3128 __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x24 */
3129 __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x28 */
3130 uint8_t RESERVED_1[20];
3131 __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x40 */
3132 __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x44 */
3133 __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x48, array step: 0x4 */
3134 __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x58 */
3135 uint8_t RESERVED_2[36];
3136 __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x80 */
3137} I2C_Type;
3138
3139/* ----------------------------------------------------------------------------
3140 -- I2C Register Masks
3141 ---------------------------------------------------------------------------- */
3142
3143/*!
3144 * @addtogroup I2C_Register_Masks I2C Register Masks
3145 * @{
3146 */
3147
3148/*! @name CFG - Configuration for shared functions. */
3149/*! @{ */
3150#define I2C_CFG_MSTEN_MASK (0x1U)
3151#define I2C_CFG_MSTEN_SHIFT (0U)
3152/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not
3153 * changed, but the Master function is internally reset.
3154 * 0b0..Disabled. The I2C Master function is disabled.
3155 * 0b1..Enabled. The I2C Master function is enabled.
3156 */
3157#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
3158#define I2C_CFG_SLVEN_MASK (0x2U)
3159#define I2C_CFG_SLVEN_SHIFT (1U)
3160/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not
3161 * changed, but the Slave function is internally reset.
3162 * 0b0..Disabled. The I2C slave function is disabled.
3163 * 0b1..Enabled. The I2C slave function is enabled.
3164 */
3165#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
3166#define I2C_CFG_MONEN_MASK (0x4U)
3167#define I2C_CFG_MONEN_SHIFT (2U)
3168/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not
3169 * changed, but the Monitor function is internally reset.
3170 * 0b0..Disabled. The I2C Monitor function is disabled.
3171 * 0b1..Enabled. The I2C Monitor function is enabled.
3172 */
3173#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
3174#define I2C_CFG_TIMEOUTEN_MASK (0x8U)
3175#define I2C_CFG_TIMEOUTEN_SHIFT (3U)
3176/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
3177 * 0b0..Disabled. Time-out function is disabled.
3178 * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause
3179 * interrupts if they are enabled. Typically, only one time-out will be used in a system.
3180 */
3181#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
3182#define I2C_CFG_MONCLKSTR_MASK (0x10U)
3183#define I2C_CFG_MONCLKSTR_SHIFT (4U)
3184/*! MONCLKSTR - Monitor function Clock Stretching.
3185 * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able
3186 * to read data provided by the Monitor function before it is overwritten. This mode may be used when
3187 * non-invasive monitoring is critical.
3188 * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can
3189 * read all incoming data supplied by the Monitor function.
3190 */
3191#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
3192/*! @} */
3193
3194/*! @name STAT - Status register for Master, Slave, and Monitor functions. */
3195/*! @{ */
3196#define I2C_STAT_MSTPENDING_MASK (0x1U)
3197#define I2C_STAT_MSTPENDING_SHIFT (0U)
3198/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on
3199 * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what
3200 * type of software service if any the master expects. This flag will cause an interrupt when set
3201 * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling
3202 * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle
3203 * state, and no communication is needed, mask this interrupt.
3204 * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
3205 * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the
3206 * idle state, it is waiting to receive or transmit data or the NACK bit.
3207 */
3208#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
3209#define I2C_STAT_MSTSTATE_MASK (0xEU)
3210#define I2C_STAT_MSTSTATE_SHIFT (1U)
3211/*! MSTSTATE - Master State code. The master state code reflects the master state when the
3212 * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field
3213 * indicates a specific required service for the Master function. All other values are reserved. See
3214 * Table 400 for details of state values and appropriate responses.
3215 * 0b000..Idle. The Master function is available to be used for a new transaction.
3216 * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
3217 * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
3218 * 0b011..NACK Address. Slave NACKed address.
3219 * 0b100..NACK Data. Slave NACKed transmitted data.
3220 */