1 files changed, 292 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC845/LPC845_features.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC845/LPC845_features.h
new file mode 100644
index 000000000..cabfd9f33
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC845/LPC845_features.h
@@ -0,0 +1,292 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.2, 2017-06-08
+**     Build:               b200222
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2020 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**     - rev. 1.2 (2017-06-08)
+**         Remove RTC_CTRL_RTC_OSC_BYPASS.
+**         SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
+**         Remove RESET and HALT from SYSCON_AHBCLKDIV.
+**
+** ###################################################################
+*/
+#ifndef _LPC845_FEATURES_H_
+#define _LPC845_FEATURES_H_
+/* SOC module features */
+#if defined(CPU_LPC845M301JBD48) || defined(CPU_LPC845M301JBD64) || defined(CPU_LPC845M301JHI48)
+/* @brief ADC availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC_COUNT (1)
+/* @brief CAPT availability on the SoC. */
+#define FSL_FEATURE_SOC_CAPT_COUNT (1)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief CTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_CTIMER_COUNT (1)
+/* @brief DAC availability on the SoC. */
+#define FSL_FEATURE_SOC_DAC_COUNT (2)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (1)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (1)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (4)
+/* @brief INPUTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief IOCON availability on the SoC. */
+#define FSL_FEATURE_SOC_IOCON_COUNT (1)
+/* @brief MRT availability on the SoC. */
+#define FSL_FEATURE_SOC_MRT_COUNT (1)
+/* @brief MTB availability on the SoC. */
+#define FSL_FEATURE_SOC_MTB_COUNT (1)
+/* @brief PINT availability on the SoC. */
+#define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief PMU availability on the SoC. */
+#define FSL_FEATURE_SOC_PMU_COUNT (1)
+/* @brief SCT availability on the SoC. */
+#define FSL_FEATURE_SOC_SCT_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (2)
+/* @brief SWM availability on the SoC. */
+#define FSL_FEATURE_SOC_SWM_COUNT (1)
+/* @brief SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_USART_COUNT (5)
+/* @brief WWDT availability on the SoC. */
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)
+#elif defined(CPU_LPC845M301JHI33)
+/* @brief ADC availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC_COUNT      (1)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT      (1)
+/* @brief CTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_CTIMER_COUNT   (1)
+/* @brief DAC availability on the SoC. */
+#define FSL_FEATURE_SOC_DAC_COUNT      (1)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT      (1)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT     (1)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT      (4)
+/* @brief INPUTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief IOCON availability on the SoC. */
+#define FSL_FEATURE_SOC_IOCON_COUNT    (1)
+/* @brief MRT availability on the SoC. */
+#define FSL_FEATURE_SOC_MRT_COUNT      (1)
+/* @brief MTB availability on the SoC. */
+#define FSL_FEATURE_SOC_MTB_COUNT      (1)
+/* @brief PINT availability on the SoC. */
+#define FSL_FEATURE_SOC_PINT_COUNT     (1)
+/* @brief PMU availability on the SoC. */
+#define FSL_FEATURE_SOC_PMU_COUNT      (1)
+/* @brief SCT availability on the SoC. */
+#define FSL_FEATURE_SOC_SCT_COUNT      (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT      (2)
+/* @brief SWM availability on the SoC. */
+#define FSL_FEATURE_SOC_SWM_COUNT      (1)
+/* @brief SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCON_COUNT   (1)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_USART_COUNT    (5)
+/* @brief WWDT availability on the SoC. */
+#define FSL_FEATURE_SOC_WWDT_COUNT     (1)
+#endif
+/* ACOMP module features */
+/* @brief Has INTENA bitfile in CTRL reigster. */
+#define FSL_FEATURE_ACOMP_HAS_CTRL_INTENA (1)
+/* ADC module features */
+/* @brief Do not has input select (register INSEL). */
+#define FSL_FEATURE_ADC_HAS_NO_INSEL (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (0)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (0)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (0)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (1)
+/* @brief Has startup register. */
+#define FSL_FEATURE_ADC_HAS_STARTUP_REG (0)
+/* @brief Has ADC Trim register */
+#define FSL_FEATURE_ADC_HAS_TRIM_REG (1)
+/* @brief Has Calibration register. */
+#define FSL_FEATURE_ADC_HAS_CALIB_REG (0)
+/* CAPT module features */
+#if defined(CPU_LPC845M301JBD48) || defined(CPU_LPC845M301JBD64) || defined(CPU_LPC845M301JHI48)
+/* @brief Has DMA bitfile in CTRL reigster. */
+#define FSL_FEATURE_CAPT_HAS_CTRL_DMA (1)
+#endif /* defined(CPU_LPC845M301JBD48) || defined(CPU_LPC845M301JBD64) || defined(CPU_LPC845M301JHI48) */
+/* CLOCK module features */
+/* @brief GPIOINT clock source. */
+#define FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE (1)
+/* CTIMER module features */
+/* @brief Writing a zero asserts the CTIMER reset. */
+#define FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET (1)
+/* DAC module features */
+/* @brief Has DMA_ENA bitfile in CTRL reigster. */
+#define FSL_FEATURE_DAC_HAS_CTRL_DMA_ENA (1)
+/* DMA module features */
+/* @brief Number of channels */
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (25)
+/* @brief Align size of DMA descriptor */
+#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
+/* @brief DMA head link descriptor table align size */
+#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
+/* FAIM module features */
+/* @brief Size of the FAIM */
+#define FSL_FEATURE_FAIM_SIZE (32)
+/* @brief Page count of the FAIM */
+#define FSL_FEATURE_FAIM_PAGE_COUNT (8)
+/* INPUTMUX module features */
+/* @brief Inputmux clock source. */
+#define FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE (1)
+/* IOCON module features */
+/* No feature definitions */
+/* MRT module features */
+/* @brief Writing a zero asserts the MRT reset. */
+#define FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET (1)
+/* @brief Has no MULTITASK bitfile in MODCFG reigster. */
+#define FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK (1)
+/* @brief Has no INUSE bitfile in STAT reigster. */
+#define FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE (1)
+/* @brief number of channels. */
+#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
+/* NVIC module features */
+/* @brief Number of connected outputs. */
+#define FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER (1)
+/* PINT module features */
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
+/* SCT module features */
+/* @brief Number of events */
+#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (8)
+/* @brief Number of states */
+#define FSL_FEATURE_SCT_NUMBER_OF_STATES (8)
+/* @brief Number of match capture */
+#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (8)
+/* @brief Writing a zero asserts the SCT reset. */
+#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (1)
+/* @brief Number of outputs */
+#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (7)
+/* SPI module features */
+/* @brief Has SPOL0 bitfile in CFG reigster. */
+#define FSL_FEATURE_SPI_HAS_SSEL0 (1)
+/* @brief Has SPOL1 bitfile in CFG reigster. */
+#define FSL_FEATURE_SPI_HAS_SSEL1 (1)
+/* @brief Has SPOL2 bitfile in CFG reigster. */
+#define FSL_FEATURE_SPI_HAS_SSEL2 (1)
+/* @brief Has SPOL3 bitfile in CFG reigster. */
+#define FSL_FEATURE_SPI_HAS_SSEL3 (1)
+/* SWM module features */
+/* @brief Has SWM PINENABLE0 ACMP I3. */
+#define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I3 (1)
+/* @brief Has SWM PINENABLE0 ACMP I4. */
+#define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I4 (1)
+/* @brief Has SWM PINENABLE0 ACMP I5. */
+#define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I5 (1)
+/* @brief Has SWM PINENABLE1. */
+#define FSL_FEATURE_SWM_HAS_PINENABLE1_REGISTER (1)
+/* SYSCON module features */
+/* @brief Pointer to ROM IAP entry functions */
+#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x0F001FF1)
+/* @brief Flash page size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (64)
+/* @brief Flash sector size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (1024)
+/* @brief Flash size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (65536)
+/* @brief IAP has Flash read & write function */
+#define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1)
+/* @brief IAP has FAIM read & write function */
+#define FSL_FEATURE_IAP_HAS_FAIM_FUNCTION (1)
+/* @brief IAP has read Flash signature function */
+#define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (0)
+/* @brief IAP has read extended Flash signature function */
+#define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (1)
+/* @brief Starter register discontinuous. */
+#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)
+/* @brief Has PINTSEL register. */
+#define FSL_FEATURE_SYSCON_HAS_PINT_SEL_REGISTER (1)
+/* USART module features */
+/* @brief Has OSR (register OSR). */
+#define FSL_FEATURE_USART_HAS_OSR_REGISTER (1)
+/* @brief Has TXIDLEEN bitfile in INTENSET reigster. */
+#define FSL_FEATURE_USART_HAS_INTENSET_TXIDLEEN (1)
+/* @brief Has ABERREN bitfile in INTENSET reigster. */
+#define FSL_FEATURE_USART_HAS_ABERR_CHECK (1)
+/* WKT module features */
+/* @brief Has SEL_EXTCLK bitfile in CTRL reigster. */
+#define FSL_FEATURE_WKT_HAS_CTRL_SEL_EXTCLK (1)
+/* WWDT module features */
+/* @brief Has no RESET register. */
+#define FSL_FEATURE_WWDT_HAS_NO_RESET (1)
+#endif /* _LPC845_FEATURES_H_ */

diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC845/LPC845_features.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC845/LPC845_features.h new file mode 100644 index 000000000..cabfd9f33 --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC845/LPC845_features.h
@@ -0,0 +1,292 @@
	1	/*
	2	** ###################################################################
	3	** Version: rev. 1.2, 2017-06-08
	4	** Build: b200222
	5	**
	6	** Abstract:
	7	** Chip specific module features.
	8	**
	9	** Copyright 2016 Freescale Semiconductor, Inc.
	10	** Copyright 2016-2020 NXP
	11	** All rights reserved.
	12	**
	13	** SPDX-License-Identifier: BSD-3-Clause
	14	**
	15	** http: www.nxp.com
	16	** mail: [email protected]
	17	**
	18	** Revisions:
	19	** - rev. 1.0 (2016-08-12)
	20	** Initial version.
	21	** - rev. 1.1 (2016-11-25)
	22	** Update CANFD and Classic CAN register.
	23	** Add MAC TIMERSTAMP registers.
	24	** - rev. 1.2 (2017-06-08)
	25	** Remove RTC_CTRL_RTC_OSC_BYPASS.
	26	** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
	27	** Remove RESET and HALT from SYSCON_AHBCLKDIV.
	28	**
	29	** ###################################################################
	30	*/
	31
	32	#ifndef _LPC845_FEATURES_H_
	33	#define _LPC845_FEATURES_H_
	34
	35	/* SOC module features */
	36
	37	#if defined(CPU_LPC845M301JBD48) \|\| defined(CPU_LPC845M301JBD64) \|\| defined(CPU_LPC845M301JHI48)
	38	/* @brief ADC availability on the SoC. */
	39	#define FSL_FEATURE_SOC_ADC_COUNT (1)
	40	/* @brief CAPT availability on the SoC. */
	41	#define FSL_FEATURE_SOC_CAPT_COUNT (1)
	42	/* @brief CRC availability on the SoC. */
	43	#define FSL_FEATURE_SOC_CRC_COUNT (1)
	44	/* @brief CTIMER availability on the SoC. */
	45	#define FSL_FEATURE_SOC_CTIMER_COUNT (1)
	46	/* @brief DAC availability on the SoC. */
	47	#define FSL_FEATURE_SOC_DAC_COUNT (2)
	48	/* @brief DMA availability on the SoC. */
	49	#define FSL_FEATURE_SOC_DMA_COUNT (1)
	50	/* @brief GPIO availability on the SoC. */
	51	#define FSL_FEATURE_SOC_GPIO_COUNT (1)
	52	/* @brief I2C availability on the SoC. */
	53	#define FSL_FEATURE_SOC_I2C_COUNT (4)
	54	/* @brief INPUTMUX availability on the SoC. */
	55	#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
	56	/* @brief IOCON availability on the SoC. */
	57	#define FSL_FEATURE_SOC_IOCON_COUNT (1)
	58	/* @brief MRT availability on the SoC. */
	59	#define FSL_FEATURE_SOC_MRT_COUNT (1)
	60	/* @brief MTB availability on the SoC. */
	61	#define FSL_FEATURE_SOC_MTB_COUNT (1)
	62	/* @brief PINT availability on the SoC. */
	63	#define FSL_FEATURE_SOC_PINT_COUNT (1)
	64	/* @brief PMU availability on the SoC. */
	65	#define FSL_FEATURE_SOC_PMU_COUNT (1)
	66	/* @brief SCT availability on the SoC. */
	67	#define FSL_FEATURE_SOC_SCT_COUNT (1)
	68	/* @brief SPI availability on the SoC. */
	69	#define FSL_FEATURE_SOC_SPI_COUNT (2)
	70	/* @brief SWM availability on the SoC. */
	71	#define FSL_FEATURE_SOC_SWM_COUNT (1)
	72	/* @brief SYSCON availability on the SoC. */
	73	#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
	74	/* @brief USART availability on the SoC. */
	75	#define FSL_FEATURE_SOC_USART_COUNT (5)
	76	/* @brief WWDT availability on the SoC. */
	77	#define FSL_FEATURE_SOC_WWDT_COUNT (1)
	78	#elif defined(CPU_LPC845M301JHI33)
	79	/* @brief ADC availability on the SoC. */
	80	#define FSL_FEATURE_SOC_ADC_COUNT (1)
	81	/* @brief CRC availability on the SoC. */
	82	#define FSL_FEATURE_SOC_CRC_COUNT (1)
	83	/* @brief CTIMER availability on the SoC. */
	84	#define FSL_FEATURE_SOC_CTIMER_COUNT (1)
	85	/* @brief DAC availability on the SoC. */
	86	#define FSL_FEATURE_SOC_DAC_COUNT (1)
	87	/* @brief DMA availability on the SoC. */
	88	#define FSL_FEATURE_SOC_DMA_COUNT (1)
	89	/* @brief GPIO availability on the SoC. */
	90	#define FSL_FEATURE_SOC_GPIO_COUNT (1)
	91	/* @brief I2C availability on the SoC. */
	92	#define FSL_FEATURE_SOC_I2C_COUNT (4)
	93	/* @brief INPUTMUX availability on the SoC. */
	94	#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
	95	/* @brief IOCON availability on the SoC. */
	96	#define FSL_FEATURE_SOC_IOCON_COUNT (1)
	97	/* @brief MRT availability on the SoC. */
	98	#define FSL_FEATURE_SOC_MRT_COUNT (1)
	99	/* @brief MTB availability on the SoC. */
	100	#define FSL_FEATURE_SOC_MTB_COUNT (1)
	101	/* @brief PINT availability on the SoC. */
	102	#define FSL_FEATURE_SOC_PINT_COUNT (1)
	103	/* @brief PMU availability on the SoC. */
	104	#define FSL_FEATURE_SOC_PMU_COUNT (1)
	105	/* @brief SCT availability on the SoC. */
	106	#define FSL_FEATURE_SOC_SCT_COUNT (1)
	107	/* @brief SPI availability on the SoC. */
	108	#define FSL_FEATURE_SOC_SPI_COUNT (2)
	109	/* @brief SWM availability on the SoC. */
	110	#define FSL_FEATURE_SOC_SWM_COUNT (1)
	111	/* @brief SYSCON availability on the SoC. */
	112	#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
	113	/* @brief USART availability on the SoC. */
	114	#define FSL_FEATURE_SOC_USART_COUNT (5)
	115	/* @brief WWDT availability on the SoC. */
	116	#define FSL_FEATURE_SOC_WWDT_COUNT (1)
	117	#endif
	118
	119	/* ACOMP module features */
	120
	121	/* @brief Has INTENA bitfile in CTRL reigster. */
	122	#define FSL_FEATURE_ACOMP_HAS_CTRL_INTENA (1)
	123
	124	/* ADC module features */
	125
	126	/* @brief Do not has input select (register INSEL). */
	127	#define FSL_FEATURE_ADC_HAS_NO_INSEL (1)
	128	/* @brief Has ASYNMODE bitfile in CTRL reigster. */
	129	#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
	130	/* @brief Has ASYNMODE bitfile in CTRL reigster. */
	131	#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (0)
	132	/* @brief Has ASYNMODE bitfile in CTRL reigster. */
	133	#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (0)
	134	/* @brief Has ASYNMODE bitfile in CTRL reigster. */
	135	#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (0)
	136	/* @brief Has ASYNMODE bitfile in CTRL reigster. */
	137	#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (1)
	138	/* @brief Has ASYNMODE bitfile in CTRL reigster. */
	139	#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (1)
	140	/* @brief Has startup register. */
	141	#define FSL_FEATURE_ADC_HAS_STARTUP_REG (0)
	142	/* @brief Has ADC Trim register */
	143	#define FSL_FEATURE_ADC_HAS_TRIM_REG (1)
	144	/* @brief Has Calibration register. */
	145	#define FSL_FEATURE_ADC_HAS_CALIB_REG (0)
	146
	147	/* CAPT module features */
	148
	149	#if defined(CPU_LPC845M301JBD48) \|\| defined(CPU_LPC845M301JBD64) \|\| defined(CPU_LPC845M301JHI48)
	150	/* @brief Has DMA bitfile in CTRL reigster. */
	151	#define FSL_FEATURE_CAPT_HAS_CTRL_DMA (1)
	152	#endif /* defined(CPU_LPC845M301JBD48) \|\| defined(CPU_LPC845M301JBD64) \|\| defined(CPU_LPC845M301JHI48) */
	153
	154	/* CLOCK module features */
	155
	156	/* @brief GPIOINT clock source. */
	157	#define FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE (1)
	158
	159	/* CTIMER module features */
	160
	161	/* @brief Writing a zero asserts the CTIMER reset. */
	162	#define FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET (1)
	163
	164	/* DAC module features */
	165
	166	/* @brief Has DMA_ENA bitfile in CTRL reigster. */
	167	#define FSL_FEATURE_DAC_HAS_CTRL_DMA_ENA (1)
	168
	169	/* DMA module features */
	170
	171	/* @brief Number of channels */
	172	#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (25)
	173	/* @brief Align size of DMA descriptor */
	174	#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
	175	/* @brief DMA head link descriptor table align size */
	176	#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
	177
	178	/* FAIM module features */
	179
	180	/* @brief Size of the FAIM */
	181	#define FSL_FEATURE_FAIM_SIZE (32)
	182	/* @brief Page count of the FAIM */
	183	#define FSL_FEATURE_FAIM_PAGE_COUNT (8)
	184
	185	/* INPUTMUX module features */
	186
	187	/* @brief Inputmux clock source. */
	188	#define FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE (1)
	189
	190	/* IOCON module features */
	191
	192	/* No feature definitions */
	193
	194	/* MRT module features */
	195
	196	/* @brief Writing a zero asserts the MRT reset. */
	197	#define FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET (1)
	198	/* @brief Has no MULTITASK bitfile in MODCFG reigster. */
	199	#define FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK (1)
	200	/* @brief Has no INUSE bitfile in STAT reigster. */
	201	#define FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE (1)
	202	/* @brief number of channels. */
	203	#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
	204
	205	/* NVIC module features */
	206
	207	/* @brief Number of connected outputs. */
	208	#define FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER (1)
	209
	210	/* PINT module features */
	211
	212	/* @brief Number of connected outputs */
	213	#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
	214
	215	/* SCT module features */
	216
	217	/* @brief Number of events */
	218	#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (8)
	219	/* @brief Number of states */
	220	#define FSL_FEATURE_SCT_NUMBER_OF_STATES (8)
	221	/* @brief Number of match capture */
	222	#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (8)
	223	/* @brief Writing a zero asserts the SCT reset. */
	224	#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (1)
	225	/* @brief Number of outputs */
	226	#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (7)
	227
	228	/* SPI module features */
	229
	230	/* @brief Has SPOL0 bitfile in CFG reigster. */
	231	#define FSL_FEATURE_SPI_HAS_SSEL0 (1)
	232	/* @brief Has SPOL1 bitfile in CFG reigster. */
	233	#define FSL_FEATURE_SPI_HAS_SSEL1 (1)
	234	/* @brief Has SPOL2 bitfile in CFG reigster. */
	235	#define FSL_FEATURE_SPI_HAS_SSEL2 (1)
	236	/* @brief Has SPOL3 bitfile in CFG reigster. */
	237	#define FSL_FEATURE_SPI_HAS_SSEL3 (1)
	238
	239	/* SWM module features */
	240
	241	/* @brief Has SWM PINENABLE0 ACMP I3. */
	242	#define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I3 (1)
	243	/* @brief Has SWM PINENABLE0 ACMP I4. */
	244	#define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I4 (1)
	245	/* @brief Has SWM PINENABLE0 ACMP I5. */
	246	#define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I5 (1)
	247	/* @brief Has SWM PINENABLE1. */
	248	#define FSL_FEATURE_SWM_HAS_PINENABLE1_REGISTER (1)
	249
	250	/* SYSCON module features */
	251
	252	/* @brief Pointer to ROM IAP entry functions */
	253	#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x0F001FF1)
	254	/* @brief Flash page size in bytes */
	255	#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (64)
	256	/* @brief Flash sector size in bytes */
	257	#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (1024)
	258	/* @brief Flash size in bytes */
	259	#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (65536)
	260	/* @brief IAP has Flash read & write function */
	261	#define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1)
	262	/* @brief IAP has FAIM read & write function */
	263	#define FSL_FEATURE_IAP_HAS_FAIM_FUNCTION (1)
	264	/* @brief IAP has read Flash signature function */
	265	#define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (0)
	266	/* @brief IAP has read extended Flash signature function */
	267	#define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (1)
	268	/* @brief Starter register discontinuous. */
	269	#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)
	270	/* @brief Has PINTSEL register. */
	271	#define FSL_FEATURE_SYSCON_HAS_PINT_SEL_REGISTER (1)
	272
	273	/* USART module features */
	274
	275	/* @brief Has OSR (register OSR). */
	276	#define FSL_FEATURE_USART_HAS_OSR_REGISTER (1)
	277	/* @brief Has TXIDLEEN bitfile in INTENSET reigster. */
	278	#define FSL_FEATURE_USART_HAS_INTENSET_TXIDLEEN (1)
	279	/* @brief Has ABERREN bitfile in INTENSET reigster. */
	280	#define FSL_FEATURE_USART_HAS_ABERR_CHECK (1)
	281
	282	/* WKT module features */
	283
	284	/* @brief Has SEL_EXTCLK bitfile in CTRL reigster. */
	285	#define FSL_FEATURE_WKT_HAS_CTRL_SEL_EXTCLK (1)
	286
	287	/* WWDT module features */
	288
	289	/* @brief Has no RESET register. */
	290	#define FSL_FEATURE_WWDT_HAS_NO_RESET (1)
	291
	292	#endif /* _LPC845_FEATURES_H_ */