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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC845/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC845/drivers/fsl_clock.h
new file mode 100644
index 000000000..2e8ff2cc4
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC845/drivers/fsl_clock.h
@@ -0,0 +1,732 @@
1/*
2 * Copyright 2017-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_common.h"
12
13/*! @addtogroup clock */
14/*! @{ */
15
16/*! @file */
17
18/*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22/*! @name Driver version */
23/*@{*/
24/*! @brief CLOCK driver version 2.3.2. */
25#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
26/*@}*/
27
28/* Definition for delay API in clock driver, users can redefine it to the real application. */
29#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
30#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (30000000UL)
31#endif
32
33/*! @brief watchdog oscilltor clock frequency.
34 *
35 * This variable is used to store the watchdog oscillator frequency which is
36 * set by CLOCK_InitWdtOsc, and it is returned by CLOCK_GetWdtOscFreq.
37 */
38extern volatile uint32_t g_Wdt_Osc_Freq;
39
40/*! @brief external clock frequency.
41 *
42 * This variable is used to store the external clock frequency which is include
43 * external oscillator clock and external clk in clock frequency value, it is
44 * set by CLOCK_InitExtClkin when CLK IN is used as external clock or by CLOCK_InitSysOsc
45 * when external oscillator is used as external clock ,and it is returned by
46 * CLOCK_GetExtClkFreq.
47 */
48extern volatile uint32_t g_Ext_Clk_Freq;
49
50/*! @brief FRO clock setting API address in ROM. */
51#define CLOCK_FRO_SETTING_API_ROM_ADDRESS (0x0F0026F5U)
52/*! @brief FAIM base address*/
53#define CLOCK_FAIM_BASE (0x50010000U)
54
55/*! @brief Clock ip name array for ADC. */
56#define ADC_CLOCKS \
57 { \
58 kCLOCK_Adc, \
59 }
60/*! @brief Clock ip name array for ACMP. */
61#define ACMP_CLOCKS \
62 { \
63 kCLOCK_Acmp, \
64 }
65/*! @brief Clock ip name array for DAC. */
66#define DAC_CLOCKS \
67 { \
68 kCLOCK_Dac0, kCLOCK_Dac1, \
69 }
70/*! @brief Clock ip name array for SWM. */
71#define SWM_CLOCKS \
72 { \
73 kCLOCK_Swm, \
74 }
75/*! @brief Clock ip name array for ROM. */
76#define ROM_CLOCKS \
77 { \
78 kCLOCK_Rom, \
79 }
80/*! @brief Clock ip name array for SRAM. */
81#define SRAM_CLOCKS \
82 { \
83 kCLOCK_Ram0_1, \
84 }
85/*! @brief Clock ip name array for IOCON. */
86#define IOCON_CLOCKS \
87 { \
88 kCLOCK_Iocon, \
89 }
90/*! @brief Clock ip name array for GPIO. */
91#define GPIO_CLOCKS \
92 { \
93 kCLOCK_Gpio0, kCLOCK_Gpio1, \
94 }
95/*! @brief Clock ip name array for GPIO_INT. */
96#define GPIO_INT_CLOCKS \
97 { \
98 kCLOCK_GpioInt, \
99 }
100/*! @brief Clock ip name array for DMA. */
101#define DMA_CLOCKS \
102 { \
103 kCLOCK_Dma, \
104 }
105/*! @brief Clock ip name array for CRC. */
106#define CRC_CLOCKS \
107 { \
108 kCLOCK_Crc, \
109 }
110/*! @brief Clock ip name array for WWDT. */
111#define WWDT_CLOCKS \
112 { \
113 kCLOCK_Wwdt, \
114 }
115/*! @brief Clock ip name array for SCT0. */
116#define SCT_CLOCKS \
117 { \
118 kCLOCK_Sct, \
119 }
120/*! @brief Clock ip name array for I2C. */
121#define I2C_CLOCKS \
122 { \
123 kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, \
124 }
125/*! @brief Clock ip name array for I2C. */
126#define USART_CLOCKS \
127 { \
128 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, \
129 }
130/*! @brief Clock ip name array for SPI. */
131#define SPI_CLOCKS \
132 { \
133 kCLOCK_Spi0, kCLOCK_Spi1, \
134 }
135/*! @brief Clock ip name array for CAPT. */
136#define CAPT_CLOCKS \
137 { \
138 kCLOCK_Capt, \
139 }
140/*! @brief Clock ip name array for CTIMER. */
141#define CTIMER_CLOCKS \
142 { \
143 kCLOCK_Ctimer0, \
144 }
145/*! @brief Clock ip name array for MTB. */
146#define MTB_CLOCKS \
147 { \
148 kCLOCK_Mtb, \
149 }
150/*! @brief Clock ip name array for MRT. */
151#define MRT_CLOCKS \
152 { \
153 kCLOCK_Mrt, \
154 }
155/*! @brief Clock ip name array for WKT. */
156#define WKT_CLOCKS \
157 { \
158 kCLOCK_Wkt, \
159 }
160
161/*! @brief Internal used Clock definition only. */
162#define CLK_GATE_DEFINE(reg, bit) ((((reg)&0xFFU) << 8U) | ((bit)&0xFFU))
163#define CLK_GATE_GET_REG(x) (((uint32_t)(x) >> 8U) & 0xFFU)
164#define CLK_GATE_GET_BITS_SHIFT(x) ((uint32_t)(x)&0xFFU)
165/* clock mux register definition */
166#define CLK_MUX_DEFINE(reg, mux) (((offsetof(SYSCON_Type, reg) & 0xFFU) << 8U) | ((mux)&0xFFU))
167#define CLK_MUX_GET_REG(x) ((volatile uint32_t *)(((uint32_t)(SYSCON)) + (((uint32_t)(x) >> 8U) & 0xFFU)))
168#define CLK_MUX_GET_MUX(x) (((uint32_t)(x)) & 0xFFU)
169#define CLK_MAIN_CLK_MUX_DEFINE(preMux, mux) ((preMux) << 8U | (mux))
170#define CLK_MAIN_CLK_MUX_GET_PRE_MUX(x) (((uint32_t)(x) >> 8U) & 0xFFU)
171#define CLK_MAIN_CLK_MUX_GET_MUX(x) ((uint32_t)(x)&0xFFU)
172/* clock divider register definition */
173#define CLK_DIV_DEFINE(reg) (((uint32_t)offsetof(SYSCON_Type, reg)) & 0xFFFU)
174#define CLK_DIV_GET_REG(x) *((volatile uint32_t *)(((uint32_t)(SYSCON)) + ((uint32_t)(x)&0xFFFU)))
175/* watch dog oscillator definition */
176#define CLK_WDT_OSC_DEFINE(freq, regValue) (((freq)&0xFFFFFFU) | (((regValue)&0xFFU) << 24U))
177#define CLK_WDT_OSC_GET_FREQ(x) ((uint32_t)(x)&0xFFFFFFU)
178#define CLK_WDT_OSC_GET_REG(x) (((x) >> 24U) & 0xFFU)
179/* Fractional clock register map */
180#define CLK_FRG_DIV_REG_MAP(base) (*(base))
181#define CLK_FRG_MUL_REG_MAP(base) (*((uint32_t *)((uint32_t)(base) + 4U)))
182#define CLK_FRG_SEL_REG_MAP(base) (*((uint32_t *)((uint32_t)(base) + 8U)))
183/* register offset */
184#define SYS_AHB_CLK_CTRL0 (0U)
185#define SYS_AHB_CLK_CTRL1 (4U)
186
187/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
188typedef enum _clock_ip_name
189{
190 kCLOCK_IpInvalid = 0U,
191 kCLOCK_Rom = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 1U),
192 kCLOCK_Ram0_1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 2U),
193 kCLOCK_I2c0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 5U),
194 kCLOCK_Gpio0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 6U),
195 kCLOCK_Swm = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 7U),
196 kCLOCK_Sct = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 8U),
197 kCLOCK_Wkt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 9U),
198 kCLOCK_Mrt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 10U),
199 kCLOCK_Spi0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 11U),
200 kCLOCK_Spi1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 12U),
201 kCLOCK_Crc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 13U),
202 kCLOCK_Uart0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 14U),
203 kCLOCK_Uart1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 15U),
204 kCLOCK_Uart2 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 16U),
205 kCLOCK_Wwdt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 17U),
206 kCLOCK_Iocon = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 18U),
207 kCLOCK_Acmp = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 19U),
208 kCLOCK_Gpio1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 20U),
209 kCLOCK_I2c1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 21U),
210 kCLOCK_I2c2 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 22U),
211 kCLOCK_I2c3 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 23U),
212 kCLOCK_Adc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 24U),
213 kCLOCK_Ctimer0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 25U),
214 kCLOCK_Mtb = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 26U),
215 kCLOCK_Dac0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 27U),
216 kCLOCK_GpioInt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 28U),
217 kCLOCK_Dma = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 29U),
218 kCLOCK_Uart3 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 30U),
219 kCLOCK_Uart4 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 31U),
220 kCLOCK_Capt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL1, 0U),
221 kCLOCK_Dac1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL1, 1U),
222} clock_ip_name_t;
223
224/*! @brief Clock name used to get clock frequency. */
225typedef enum _clock_name
226{
227 kCLOCK_CoreSysClk, /*!< Cpu/AHB/AHB matrix/Memories,etc */
228 kCLOCK_MainClk, /*!< Main clock */
229
230 kCLOCK_Fro, /*!< FRO18/24/30 */
231 kCLOCK_FroDiv, /*!< FRO div clock */
232 kCLOCK_ExtClk, /*!< External Clock */
233 kCLOCK_PllOut, /*!< PLL Output */
234 kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
235 kCLOCK_Frg0, /*!< fractional rate0 */
236 kCLOCK_Frg1, /*!< fractional rate1 */
237} clock_name_t;
238
239/*! @brief Clock Mux Switches
240 *CLK_MUX_DEFINE(reg, mux)
241 *reg is used to define the mux register
242 *mux is used to define the mux value
243 *
244 */
245typedef enum _clock_select
246{
247 kCAPT_Clk_From_Fro = CLK_MUX_DEFINE(CAPTCLKSEL, 0U),
248 kCAPT_Clk_From_MainClk = CLK_MUX_DEFINE(CAPTCLKSEL, 1U),
249 kCAPT_Clk_From_SysPll = CLK_MUX_DEFINE(CAPTCLKSEL, 2U),
250 kCAPT_Clk_From_Fro_Div = CLK_MUX_DEFINE(CAPTCLKSEL, 3U),
251 kCAPT_Clk_From_WdtOsc = CLK_MUX_DEFINE(CAPTCLKSEL, 4U),
252
253 kADC_Clk_From_Fro = CLK_MUX_DEFINE(ADCCLKSEL, 0U),
254 kADC_Clk_From_SysPll = CLK_MUX_DEFINE(ADCCLKSEL, 1U),
255
256 kSCT_Clk_From_Fro = CLK_MUX_DEFINE(SCTCLKSEL, 0U),
257 kSCT_Clk_From_MainClk = CLK_MUX_DEFINE(SCTCLKSEL, 1U),
258 kSCT_Clk_From_SysPll = CLK_MUX_DEFINE(SCTCLKSEL, 2U),
259
260 kEXT_Clk_From_SysOsc = CLK_MUX_DEFINE(EXTCLKSEL, 0U),
261 kEXT_Clk_From_ClkIn = CLK_MUX_DEFINE(EXTCLKSEL, 1U),
262
263 kUART0_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[0U], 0U),
264 kUART0_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[0U], 1U),
265 kUART0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[0U], 2U),
266 kUART0_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[0U], 3U),
267 kUART0_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[0U], 4U),
268
269 kUART1_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[1U], 0U),
270 kUART1_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[1U], 1U),
271 kUART1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[1U], 2U),
272 kUART1_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[1U], 3U),
273 kUART1_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[1U], 4U),
274
275 kUART2_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[2U], 0U),
276 kUART2_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[2U], 1U),
277 kUART2_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[2U], 2U),
278 kUART2_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[2U], 3U),
279 kUART2_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[2U], 4U),
280
281 kUART3_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[3U], 0U),
282 kUART3_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[3U], 1U),
283 kUART3_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[3U], 2U),
284 kUART3_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[3U], 3U),
285 kUART3_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[3U], 4U),
286
287 kUART4_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[4U], 0U),
288 kUART4_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[4U], 1U),
289 kUART4_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[4U], 2U),
290 kUART4_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[4U], 3U),
291 kUART4_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[4U], 4U),
292
293 kI2C0_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[5U], 0U),
294 kI2C0_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[5U], 1U),
295 kI2C0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[5U], 2U),
296 kI2C0_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[5U], 3U),
297 kI2C0_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[5U], 4U),
298
299 kI2C1_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[6U], 0U),
300 kI2C1_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[6U], 1U),
301 kI2C1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[6U], 2U),
302 kI2C1_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[6U], 3U),
303 kI2C1_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[6U], 4U),
304
305 kI2C2_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[7U], 0U),
306 kI2C2_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[7U], 1U),
307 kI2C2_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[7U], 2U),
308 kI2C2_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[7U], 3U),
309 kI2C2_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[7U], 4U),
310
311 kI2C3_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[8U], 0U),
312 kI2C3_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[8U], 1U),
313 kI2C3_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[8U], 2U),
314 kI2C3_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[8U], 3U),
315 kI2C3_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[8U], 4U),
316
317 kSPI0_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[9U], 0U),
318 kSPI0_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[9U], 1U),
319 kSPI0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[9U], 2U),
320 kSPI0_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[9U], 3U),
321 kSPI0_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[9U], 4U),
322
323 kSPI1_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[10U], 0U),
324 kSPI1_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[10U], 1U),
325 kSPI1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[10U], 2U),
326 kSPI1_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[10U], 3U),
327 kSPI1_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[10U], 4U),
328
329 kFRG0_Clk_From_Fro = CLK_MUX_DEFINE(FRG[0U].FRGCLKSEL, 0U),
330 kFRG0_Clk_From_MainClk = CLK_MUX_DEFINE(FRG[0U].FRGCLKSEL, 1U),
331 kFRG0_Clk_From_SysPll = CLK_MUX_DEFINE(FRG[0U].FRGCLKSEL, 2U),
332
333 kFRG1_Clk_From_Fro = CLK_MUX_DEFINE(FRG[1U].FRGCLKSEL, 0U),
334 kFRG1_Clk_From_MainClk = CLK_MUX_DEFINE(FRG[1U].FRGCLKSEL, 1U),
335 kFRG1_Clk_From_SysPll = CLK_MUX_DEFINE(FRG[1U].FRGCLKSEL, 2U),
336
337 kCLKOUT_From_Fro = CLK_MUX_DEFINE(CLKOUTSEL, 0U),
338 kCLKOUT_From_MainClk = CLK_MUX_DEFINE(CLKOUTSEL, 1U),
339 kCLKOUT_From_SysPll = CLK_MUX_DEFINE(CLKOUTSEL, 2U),
340 kCLKOUT_From_ExtClk = CLK_MUX_DEFINE(CLKOUTSEL, 3U),
341 kCLKOUT_From_WdtOsc = CLK_MUX_DEFINE(CLKOUTSEL, 4U),
342} clock_select_t;
343
344/*! @brief Clock divider
345 */
346typedef enum _clock_divider
347{
348 kCLOCK_DivAdcClk = CLK_DIV_DEFINE(ADCCLKDIV),
349 kCLOCK_DivSctClk = CLK_DIV_DEFINE(SCTCLKDIV),
350 kCLOCK_DivClkOut = CLK_DIV_DEFINE(CLKOUTDIV),
351
352 kCLOCK_IOCONCLKDiv6 = CLK_DIV_DEFINE(IOCONCLKDIV6),
353 kCLOCK_IOCONCLKDiv5 = CLK_DIV_DEFINE(IOCONCLKDIV5),
354 kCLOCK_IOCONCLKDiv4 = CLK_DIV_DEFINE(IOCONCLKDIV4),
355 kCLOCK_IOCONCLKDiv3 = CLK_DIV_DEFINE(IOCONCLKDIV3),
356 kCLOCK_IOCONCLKDiv2 = CLK_DIV_DEFINE(IOCONCLKDIV2),
357 kCLOCK_IOCONCLKDiv1 = CLK_DIV_DEFINE(IOCONCLKDIV1),
358 kCLOCK_IOCONCLKDiv0 = CLK_DIV_DEFINE(IOCONCLKDIV0),
359} clock_divider_t;
360
361/*! @brief watch dog analog output frequency */
362typedef enum _clock_wdt_analog_freq
363{
364 kCLOCK_WdtAnaFreq0HZ = CLK_WDT_OSC_DEFINE(0U, 0U),
365 kCLOCK_WdtAnaFreq600KHZ = CLK_WDT_OSC_DEFINE(600000U, 1U),
366 kCLOCK_WdtAnaFreq1050KHZ = CLK_WDT_OSC_DEFINE(1050000U, 2u),
367 kCLOCK_WdtAnaFreq1400KHZ = CLK_WDT_OSC_DEFINE(1400000U, 3U),
368 kCLOCK_WdtAnaFreq1750KHZ = CLK_WDT_OSC_DEFINE(1750000U, 4U),
369 kCLOCK_WdtAnaFreq2100KHZ = CLK_WDT_OSC_DEFINE(2100000U, 5U),
370 kCLOCK_WdtAnaFreq2400KHZ = CLK_WDT_OSC_DEFINE(2400000U, 6U),
371 kCLOCK_WdtAnaFreq2700KHZ = CLK_WDT_OSC_DEFINE(2700000U, 7U),
372 kCLOCK_WdtAnaFreq3000KHZ = CLK_WDT_OSC_DEFINE(3000000U, 8U),
373 kCLOCK_WdtAnaFreq3250KHZ = CLK_WDT_OSC_DEFINE(3250000U, 9U),
374 kCLOCK_WdtAnaFreq3500KHZ = CLK_WDT_OSC_DEFINE(3500000U, 10U),
375 kCLOCK_WdtAnaFreq3750KHZ = CLK_WDT_OSC_DEFINE(3750000U, 11U),
376 kCLOCK_WdtAnaFreq4000KHZ = CLK_WDT_OSC_DEFINE(4000000U, 12U),
377 kCLOCK_WdtAnaFreq4200KHZ = CLK_WDT_OSC_DEFINE(4200000U, 13U),
378 kCLOCK_WdtAnaFreq4400KHZ = CLK_WDT_OSC_DEFINE(4400000U, 14U),
379 kCLOCK_WdtAnaFreq4600KHZ = CLK_WDT_OSC_DEFINE(4600000U, 15U),
380} clock_wdt_analog_freq_t;
381
382/*! @brief fro output frequency source definition */
383typedef enum _clock_fro_src
384{
385 kCLOCK_FroSrcLpwrBootValue = 0U, /*!< fro source from the fro oscillator divided by low power boot value */
386 kCLOCK_FroSrcFroOsc = 1U << SYSCON_FROOSCCTRL_FRO_DIRECT_SHIFT, /*!< fre source from the fro oscillator directly */
387} clock_fro_src_t;
388
389/*! @brief fro oscillator output frequency value definition */
390typedef enum _clock_fro_osc_freq
391{
392 kCLOCK_FroOscOut18M = 18000U, /*!< FRO oscillator output 18M */
393 kCLOCK_FroOscOut24M = 24000U, /*!< FRO oscillator output 24M */
394 kCLOCK_FroOscOut30M = 30000U, /*!< FRO oscillator output 30M */
395} clock_fro_osc_freq_t;
396
397/*! @brief PLL clock definition.*/
398typedef enum _clock_sys_pll_src
399{
400 kCLOCK_SysPllSrcFRO = 0U, /*!< system pll source from FRO */
401 kCLOCK_SysPllSrcExtClk = 1U, /*!< system pll source from external clock */
402 kCLOCK_SysPllSrcWdtOsc = 2U, /*!< system pll source from watchdog oscillator */
403 kCLOCK_SysPllSrcFroDiv = 3U, /*!< system pll source from FRO divided clock */
404} clock_sys_pll_src;
405
406/*! @brief Main clock source definition */
407typedef enum _clock_main_clk_src
408{
409 kCLOCK_MainClkSrcFro = CLK_MAIN_CLK_MUX_DEFINE(0U, 0U), /*!< main clock source from FRO */
410 kCLOCK_MainClkSrcExtClk = CLK_MAIN_CLK_MUX_DEFINE(1U, 0U), /*!< main clock source from Ext clock */
411 kCLOCK_MainClkSrcWdtOsc = CLK_MAIN_CLK_MUX_DEFINE(2U, 0U), /*!< main clock source from watchdog oscillator */
412 kCLOCK_MainClkSrcFroDiv = CLK_MAIN_CLK_MUX_DEFINE(3U, 0U), /*!< main clock source from FRO Div */
413 kCLOCK_MainClkSrcSysPll = CLK_MAIN_CLK_MUX_DEFINE(0U, 1U), /*!< main clock source from system pll */
414} clock_main_clk_src_t;
415
416/*! @brief PLL configuration structure */
417typedef struct _clock_sys_pll
418{
419 uint32_t targetFreq; /*!< System pll fclk output frequency, the output frequency should be lower than 100MHZ*/
420 clock_sys_pll_src src; /*!< System pll clock source */
421} clock_sys_pll_t;
422
423/*******************************************************************************
424 * API
425 ******************************************************************************/
426
427#if defined(__cplusplus)
428extern "C" {
429#endif /* __cplusplus */
430
431/*!
432 * @name Clock gate, mux, and divider.
433 * @{
434 */
435
436/*
437 *! @brief enable ip clock.
438 *
439 * @param clk clock ip definition.
440 */
441static inline void CLOCK_EnableClock(clock_ip_name_t clk)
442{
443 *(volatile uint32_t *)(((uint32_t)(&SYSCON->SYSAHBCLKCTRL0)) + CLK_GATE_GET_REG(clk)) |=
444 1UL << CLK_GATE_GET_BITS_SHIFT(clk);
445}
446
447/*
448 *!@brief disable ip clock.
449 *
450 * @param clk clock ip definition.
451 */
452static inline void CLOCK_DisableClock(clock_ip_name_t clk)
453{
454 *(volatile uint32_t *)(((uint32_t)(&SYSCON->SYSAHBCLKCTRL0)) + CLK_GATE_GET_REG(clk)) &=
455 ~(1UL << CLK_GATE_GET_BITS_SHIFT(clk));
456}
457
458/*
459 *! @brief Configure the clock selection muxes.
460 * @param mux : Clock to be configured.
461 * @return Nothing
462 */
463static inline void CLOCK_Select(clock_select_t sel)
464{
465 *(CLK_MUX_GET_REG(sel)) = CLK_MUX_GET_MUX(sel);
466}
467
468/*
469 *! @brief Setup peripheral clock dividers.
470 * @param name : Clock divider name
471 * @param value: Value to be divided
472 * @return Nothing
473 */
474static inline void CLOCK_SetClkDivider(clock_divider_t name, uint32_t value)
475{
476 CLK_DIV_GET_REG(name) = value & 0xFFU;
477}
478
479/*
480 *! @brief Get peripheral clock dividers.
481 * @param name : Clock divider name
482 * @return clock divider value
483 */
484static inline uint32_t CLOCK_GetClkDivider(clock_divider_t name)
485{
486 return CLK_DIV_GET_REG(name) & 0xFFU;
487}
488
489/*
490 *! @brief Setup Core clock dividers.
491 * Be careful about the core divider value, due to core/system frequency should be lower than 30MHZ.
492 * @param value: Value to be divided
493 * @return Nothing
494 */
495static inline void CLOCK_SetCoreSysClkDiv(uint32_t value)
496{
497 assert(value != 0U);
498
499 SYSCON->SYSAHBCLKDIV = (SYSCON->SYSAHBCLKDIV & (~SYSCON_SYSAHBCLKDIV_DIV_MASK)) | SYSCON_SYSAHBCLKDIV_DIV(value);
500}
501
502/*! @brief Set main clock reference source.
503 * @param src Refer to clock_main_clk_src_t to set the main clock source.
504 */
505void CLOCK_SetMainClkSrc(clock_main_clk_src_t src);
506
507/*! @brief Set FRO clock source
508 * @param src Please refer to _clock_fro_src definition.
509 *
510 */
511void CLOCK_SetFroOutClkSrc(clock_fro_src_t src);
512
513/*
514 *! @brief Set Fractional generator multiplier value.
515 * @param base: Fractional generator register address
516 * @param mul : FRG multiplier value.
517 * @return Nothing
518 */
519static inline void CLOCK_SetFRGClkMul(uint32_t *base, uint32_t mul)
520{
521 CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK;
522 CLK_FRG_MUL_REG_MAP(base) = SYSCON_FRG_FRGMULT_MULT(mul);
523}
524/* @} */
525
526/*!
527 * @name Get frequency
528 * @{
529 */
530
531/*! @brief Return Frequency of FRG0 Clock.
532 * @return Frequency of FRG0 Clock.
533 */
534uint32_t CLOCK_GetFRG0ClkFreq(void);
535
536/*! @brief Return Frequency of FRG1 Clock.
537 * @return Frequency of FRG1 Clock.
538 */
539uint32_t CLOCK_GetFRG1ClkFreq(void);
540
541/*! @brief Return Frequency of Main Clock.
542 * @return Frequency of Main Clock.
543 */
544uint32_t CLOCK_GetMainClkFreq(void);
545
546/*! @brief Return Frequency of FRO.
547 * @return Frequency of FRO.
548 */
549uint32_t CLOCK_GetFroFreq(void);
550
551/*! @brief Return Frequency of core.
552 * @return Frequency of core.
553 */
554static inline uint32_t CLOCK_GetCoreSysClkFreq(void)
555{
556 return CLOCK_GetMainClkFreq() / (SYSCON->SYSAHBCLKDIV & 0xffU);
557}
558
559/*! @brief Return Frequency of ClockOut
560 * @return Frequency of ClockOut
561 */
562uint32_t CLOCK_GetClockOutClkFreq(void);
563
564/*! @brief Get UART0 frequency
565 * @retval UART0 frequency value.
566 */
567uint32_t CLOCK_GetUart0ClkFreq(void);
568
569/*! @brief Get UART1 frequency
570 * @retval UART1 frequency value.
571 */
572uint32_t CLOCK_GetUart1ClkFreq(void);
573
574/*! @brief Get UART2 frequency
575 * @retval UART2 frequency value.
576 */
577uint32_t CLOCK_GetUart2ClkFreq(void);
578
579/*! @brief Get UART3 frequency
580 * @retval UART3 frequency value.
581 */
582uint32_t CLOCK_GetUart3ClkFreq(void);
583
584/*! @brief Get UART4 frequency
585 * @retval UART4 frequency value.
586 */
587uint32_t CLOCK_GetUart4ClkFreq(void);
588
589/*! @brief Return Frequency of selected clock
590 * @return Frequency of selected clock
591 */
592uint32_t CLOCK_GetFreq(clock_name_t clockName);
593
594/*! @brief Return System PLL input clock rate
595 * @return System PLL input clock rate
596 */
597uint32_t CLOCK_GetSystemPLLInClockRate(void);
598
599/*! @brief Return Frequency of System PLL
600 * @return Frequency of PLL
601 */
602static inline uint32_t CLOCK_GetSystemPLLFreq(void)
603{
604 return CLOCK_GetSystemPLLInClockRate() * ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK) + 1U);
605}
606
607/*! @brief Get watch dog OSC frequency
608 * @retval watch dog OSC frequency value.
609 */
610static inline uint32_t CLOCK_GetWdtOscFreq(void)
611{
612 return g_Wdt_Osc_Freq;
613}
614
615/*! @brief Get external clock frequency
616 * @retval external clock frequency value.
617 */
618static inline uint32_t CLOCK_GetExtClkFreq(void)
619{
620 return g_Ext_Clk_Freq;
621}
622/* @} */
623
624/*!
625 * @name PLL operations
626 * @{
627 */
628
629/*! @brief System PLL initialize.
630 * @param config System PLL configurations.
631 */
632void CLOCK_InitSystemPll(const clock_sys_pll_t *config);
633
634/*! @brief System PLL Deinitialize.*/
635static inline void CLOCK_DenitSystemPll(void)
636{
637 /* Power off PLL */
638 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSPLL_PD_MASK;
639}
640
641/* @} */
642
643/*!
644 * @name Fractional clock operations
645 * @{
646 */
647
648/*! @brief Set FRG0 output frequency.
649 * @param freq Target output frequency, freq < input and (input / freq) < 2 should be satisfy.
650 * @retval true - successfully, false - input argument is invalid.
651 *
652 */
653bool CLOCK_SetFRG0ClkFreq(uint32_t freq);
654
655/*! @brief Set FRG1 output frequency.
656 * @param freq Target output frequency, freq < input and (input / freq) < 2 should be satisfy.
657 * @retval true - successfully, false - input argument is invalid.
658 *
659 */
660bool CLOCK_SetFRG1ClkFreq(uint32_t freq);
661
662/* @} */
663
664/*!
665 * @name External/internal oscillator clock operations
666 * @{
667 */
668
669/*! @brief Init external CLK IN, select the CLKIN as the external clock source.
670 * @param clkInFreq external clock in frequency.
671 */
672void CLOCK_InitExtClkin(uint32_t clkInFreq);
673
674/*! @brief Init SYS OSC
675 * @param oscFreq oscillator frequency value.
676 */
677void CLOCK_InitSysOsc(uint32_t oscFreq);
678
679/*! @brief XTALIN init function
680 * system oscillator is bypassed, sys_osc_clk is fed driectly from the XTALIN.
681 * @param xtalInFreq XTALIN frequency value
682 * @return Frequency of PLL
683 */
684void CLOCK_InitXtalin(uint32_t xtalInFreq);
685
686/*! @brief Deinit SYS OSC
687 */
688static inline void CLOCK_DeinitSysOsc(void)
689{
690 /* Deinit system osc power */
691 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSOSC_PD_MASK;
692}
693
694/*! @brief Init watch dog OSC
695 * Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the
696 * listed frequency value. The watchdog oscillator is the clock source with the lowest power
697 * consumption. If accurate timing is required, use the FRO or system oscillator.
698 * The frequency of the watchdog oscillator is undefined after reset. The watchdog
699 * oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
700 * using the watchdog oscillator.
701 * Watchdog osc output frequency = wdtOscFreq / wdtOscDiv, should in range 9.3KHZ to 2.3MHZ.
702 * @param wdtOscFreq watch dog analog part output frequency, reference _wdt_analog_output_freq.
703 * @param wdtOscDiv watch dog analog part output frequency divider, shoule be a value >= 2U and multiple of 2
704 */
705void CLOCK_InitWdtOsc(clock_wdt_analog_freq_t wdtOscFreq, uint32_t wdtOscDiv);
706
707/*! @brief Deinit watch dog OSC
708 */
709static inline void CLOCK_DeinitWdtOsc(void)
710{
711 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_WDTOSC_PD_MASK;
712}
713
714/*! @brief Set FRO oscillator output frequency.
715 * Initialize the FRO clock to given frequency (18, 24 or 30 MHz).
716 * @param freq Please refer to clock_fro_osc_freq_t definition, frequency must be one of 18000, 24000 or 30000 KHz.
717 *
718 */
719static inline void CLOCK_SetFroOscFreq(clock_fro_osc_freq_t freq)
720{
721 (*((void (*)(uint32_t freq))(CLOCK_FRO_SETTING_API_ROM_ADDRESS)))(freq);
722}
723
724/* @} */
725
726#if defined(__cplusplus)
727}
728#endif /* __cplusplus */
729
730/*! @} */
731
732#endif /* _FSL_CLOCK_H_ */
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