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1/*
2** ###################################################################
3** Version: rev. 7.0, 2018-11-05
4** Build: b200927
5**
6** Abstract:
7** Chip specific module features.
8**
9** Copyright 2016 Freescale Semiconductor, Inc.
10** Copyright 2016-2020 NXP
11** All rights reserved.
12**
13** SPDX-License-Identifier: BSD-3-Clause
14**
15** http: www.nxp.com
16** mail: [email protected]
17**
18** Revisions:
19** - rev. 1.0 (2016-04-13)
20** Initial version.
21** - rev. 2.0 (2016-07-19)
22** RevC Header ER
23** - rev. 3.0 (2017-02-28)
24** RevD Header ER
25** - rev. 4.0 (2017-05-02)
26** RevE Header ER
27** - rev. 5.0 (2017-12-22)
28** RevA(B0) Header GA
29** - rev. 6.0 (2018-02-01)
30** RevB(B0) Header GA
31** - rev. 7.0 (2018-11-05)
32** RevA(B1) Header
33**
34** ###################################################################
35*/
36
37#ifndef _MCIMX7U3_cm4_FEATURES_H_
38#define _MCIMX7U3_cm4_FEATURES_H_
39
40/* SOC module features */
41
42/* @brief ACMP availability on the SoC. */
43#define FSL_FEATURE_SOC_ACMP_COUNT (2)
44/* @brief AXBS availability on the SoC. */
45#define FSL_FEATURE_SOC_AXBS_COUNT (2)
46/* @brief CRC availability on the SoC. */
47#define FSL_FEATURE_SOC_CRC_COUNT (1)
48/* @brief DAC availability on the SoC. */
49#define FSL_FEATURE_SOC_DAC_COUNT (2)
50/* @brief DMAMUX availability on the SoC. */
51#define FSL_FEATURE_SOC_DMAMUX_COUNT (2)
52/* @brief EDMA availability on the SoC. */
53#define FSL_FEATURE_SOC_EDMA_COUNT (2)
54/* @brief EWM availability on the SoC. */
55#define FSL_FEATURE_SOC_EWM_COUNT (1)
56/* @brief FB availability on the SoC. */
57#define FSL_FEATURE_SOC_FB_COUNT (1)
58/* @brief FGPIO availability on the SoC. */
59#define FSL_FEATURE_SOC_FGPIO_COUNT (2)
60/* @brief FLEXIO availability on the SoC. */
61#define FSL_FEATURE_SOC_FLEXIO_COUNT (2)
62/* @brief GPIO availability on the SoC. */
63#define FSL_FEATURE_SOC_GPIO_COUNT (6)
64/* @brief I2S availability on the SoC. */
65#define FSL_FEATURE_SOC_I2S_COUNT (2)
66/* @brief LCDIF availability on the SoC. */
67#define FSL_FEATURE_SOC_LCDIF_COUNT (1)
68/* @brief LLWU availability on the SoC. */
69#define FSL_FEATURE_SOC_LLWU_COUNT (1)
70/* @brief LMEM availability on the SoC. */
71#define FSL_FEATURE_SOC_LMEM_COUNT (1)
72/* @brief LPADC availability on the SoC. */
73#define FSL_FEATURE_SOC_LPADC_COUNT (2)
74/* @brief LPI2C availability on the SoC. */
75#define FSL_FEATURE_SOC_LPI2C_COUNT (8)
76/* @brief LPIT availability on the SoC. */
77#define FSL_FEATURE_SOC_LPIT_COUNT (2)
78/* @brief LPSPI availability on the SoC. */
79#define FSL_FEATURE_SOC_LPSPI_COUNT (4)
80/* @brief LPTMR availability on the SoC. */
81#define FSL_FEATURE_SOC_LPTMR_COUNT (2)
82/* @brief LPUART availability on the SoC. */
83#define FSL_FEATURE_SOC_LPUART_COUNT (8)
84/* @brief LTC availability on the SoC. */
85#define FSL_FEATURE_SOC_LTC_COUNT (1)
86/* @brief MCM availability on the SoC. */
87#define FSL_FEATURE_SOC_MCM_COUNT (1)
88/* @brief MIPI_DSI_HOST availability on the SoC. */
89#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (1)
90/* @brief MMCAU availability on the SoC. */
91#define FSL_FEATURE_SOC_MMCAU_COUNT (1)
92/* @brief MMDC availability on the SoC. */
93#define FSL_FEATURE_SOC_MMDC_COUNT (1)
94/* @brief MU availability on the SoC. */
95#define FSL_FEATURE_SOC_MU_COUNT (1)
96/* @brief OCOTP availability on the SoC. */
97#define FSL_FEATURE_SOC_OCOTP_COUNT (1)
98/* @brief OTFAD availability on the SoC. */
99#define FSL_FEATURE_SOC_OTFAD_COUNT (1)
100/* @brief PCC availability on the SoC. */
101#define FSL_FEATURE_SOC_PCC_COUNT (4)
102/* @brief PMC availability on the SoC. */
103#define FSL_FEATURE_SOC_PMC_COUNT (2)
104/* @brief PORT availability on the SoC. */
105#define FSL_FEATURE_SOC_PORT_COUNT (6)
106/* @brief QuadSPI availability on the SoC. */
107#define FSL_FEATURE_SOC_QuadSPI_COUNT (1)
108/* @brief ROMC availability on the SoC. */
109#define FSL_FEATURE_SOC_ROMC_COUNT (2)
110/* @brief SCG availability on the SoC. */
111#define FSL_FEATURE_SOC_SCG_COUNT (2)
112/* @brief SEMA42 availability on the SoC. */
113#define FSL_FEATURE_SOC_SEMA42_COUNT (2)
114/* @brief SIM availability on the SoC. */
115#define FSL_FEATURE_SOC_SIM_COUNT (1)
116/* @brief SMC availability on the SoC. */
117#define FSL_FEATURE_SOC_SMC_COUNT (2)
118/* @brief SNVS availability on the SoC. */
119#define FSL_FEATURE_SOC_SNVS_COUNT (1)
120/* @brief TPM availability on the SoC. */
121#define FSL_FEATURE_SOC_TPM_COUNT (8)
122/* @brief TRGMUX availability on the SoC. */
123#define FSL_FEATURE_SOC_TRGMUX_COUNT (2)
124/* @brief TRNG availability on the SoC. */
125#define FSL_FEATURE_SOC_TRNG_COUNT (1)
126/* @brief TSTMR availability on the SoC. */
127#define FSL_FEATURE_SOC_TSTMR_COUNT (2)
128/* @brief USBHS availability on the SoC. */
129#define FSL_FEATURE_SOC_USBHS_COUNT (2)
130/* @brief USBHSDCD availability on the SoC. */
131#define FSL_FEATURE_SOC_USBHSDCD_COUNT (1)
132/* @brief USBNC availability on the SoC. */
133#define FSL_FEATURE_SOC_USBNC_COUNT (2)
134/* @brief USBPHY availability on the SoC. */
135#define FSL_FEATURE_SOC_USBPHY_COUNT (1)
136/* @brief USDHC availability on the SoC. */
137#define FSL_FEATURE_SOC_USDHC_COUNT (2)
138/* @brief VIU availability on the SoC. */
139#define FSL_FEATURE_SOC_VIU_COUNT (1)
140/* @brief WDOG availability on the SoC. */
141#define FSL_FEATURE_SOC_WDOG_COUNT (3)
142/* @brief XRDC availability on the SoC. */
143#define FSL_FEATURE_SOC_XRDC_COUNT (1)
144
145/* LPADC module features */
146
147/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */
148#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1)
149/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
150#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (1)
151/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
152#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (1)
153/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
154#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (0)
155/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */
156#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (0)
157/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
158#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (0)
159/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
160#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (0)
161/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
162#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (0)
163/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
164#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (0)
165/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
166#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
167/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
168#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
169/* @brief Has calibration (bitfield CFG[CALOFS]). */
170#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
171/* @brief Has offset trim (register OFSTRIM). */
172#define FSL_FEATURE_LPADC_HAS_OFSTRIM (0)
173
174/* ACMP module features */
175
176/* @brief Has CMP_C3. */
177#define FSL_FEATURE_ACMP_HAS_C3_REG (1)
178/* @brief Has C0 LINKEN Bit */
179#define FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT (1)
180/* @brief Has C0 OFFSET Bit */
181#define FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT (0)
182/* @brief Has C1 INPSEL Bit */
183#define FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT (0)
184/* @brief Has C1 INNSEL Bit */
185#define FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT (0)
186/* @brief Has C1 DACOE Bit */
187#define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (1)
188/* @brief Has C1 DMODE Bit */
189#define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1)
190/* @brief Has C2 RRE Bit */
191#define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0)
192
193/* CRC module features */
194
195/* @brief Has data register with name CRC */
196#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
197
198/* EDMA module features */
199
200/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
201#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32)
202/* @brief Total number of DMA channels on all modules. */
203#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32)
204/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
205#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
206/* @brief Has DMA_Error interrupt vector. */
207#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
208/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
209#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
210/* @brief Channel IRQ entry shared offset. */
211#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (4)
212/* @brief If 8 bytes transfer supported. */
213#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1)
214/* @brief If 16 bytes transfer supported. */
215#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (0)
216
217/* DMAMUX module features */
218
219/* @brief Number of DMA channels (related to number of register CHCFGn). */
220#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32)
221/* @brief Total number of DMA channels on all modules. */
222#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (64)
223/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
224#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
225/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */
226#define FSL_FEATURE_DMAMUX_HAS_A_ON (1)
227
228/* EWM module features */
229
230/* @brief Has clock select (register CLKCTRL). */
231#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1)
232/* @brief Has clock prescaler (register CLKPRESCALER). */
233#define FSL_FEATURE_EWM_HAS_PRESCALER (1)
234
235/* FLEXIO module features */
236
237/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
238#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
239/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
240#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
241/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
242#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
243/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
244#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1)
245/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
246#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1)
247/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
248#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1)
249/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
250#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1)
251/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
252#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1)
253/* @brief Reset value of the FLEXIO_VERID register */
254#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001)
255/* @brief Reset value of the FLEXIO_PARAM register */
256#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808)
257/* @brief Flexio DMA request base channel */
258#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0)
259
260/* GPIO module features */
261
262/* @brief Has port input disable register (PIDR). */
263#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
264/* @brief Has GPIO attribute checker register (GACR). */
265#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0)
266
267/* SAI module features */
268
269/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
270#define FSL_FEATURE_SAI_FIFO_COUNT (16)
271/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
272#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \
273 (((x) == I2S0) ? (2) : \
274 (((x) == I2S1) ? (4) : (-1)))
275/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
276#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
277/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
278#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
279/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
280#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
281/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
282#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
283/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
284#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
285/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
286#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
287/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
288#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
289/* @brief Interrupt source number */
290#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1)
291/* @brief Has register of MCR. */
292#define FSL_FEATURE_SAI_HAS_MCR (0)
293/* @brief Has bit field MICS of the MCR register. */
294#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1)
295/* @brief Has register of MDR */
296#define FSL_FEATURE_SAI_HAS_MDR (0)
297/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
298#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0)
299/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */
300#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0)
301/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */
302#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1)
303
304/* LLWU module features */
305
306/* @brief Maximum number of pins connected to LLWU device. */
307#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
308/* @brief Maximum number of internal modules connected to LLWU device. */
309#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
310/* @brief Number of digital filters. */
311#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4)
312/* @brief Has MF register. */
313#define FSL_FEATURE_LLWU_HAS_MF (1)
314/* @brief Has PF register. */
315#define FSL_FEATURE_LLWU_HAS_PF (1)
316/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
317#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
318/* @brief Has no internal module wakeup flag register. */
319#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
320/* @brief Has external pin 0 connected to LLWU device. */
321#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
322/* @brief Index of port of external pin. */
323#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOA_IDX)
324/* @brief Number of external pin port on specified port. */
325#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0)
326/* @brief Has external pin 1 connected to LLWU device. */
327#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
328/* @brief Index of port of external pin. */
329#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOA_IDX)
330/* @brief Number of external pin port on specified port. */
331#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (3)
332/* @brief Has external pin 2 connected to LLWU device. */
333#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
334/* @brief Index of port of external pin. */
335#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOA_IDX)
336/* @brief Number of external pin port on specified port. */
337#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (13)
338/* @brief Has external pin 3 connected to LLWU device. */
339#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
340/* @brief Index of port of external pin. */
341#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
342/* @brief Number of external pin port on specified port. */
343#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (14)
344/* @brief Has external pin 4 connected to LLWU device. */
345#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
346/* @brief Index of port of external pin. */
347#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
348/* @brief Number of external pin port on specified port. */
349#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (18)
350/* @brief Has external pin 5 connected to LLWU device. */
351#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
352/* @brief Index of port of external pin. */
353#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX)
354/* @brief Number of external pin port on specified port. */
355#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (19)
356/* @brief Has external pin 6 connected to LLWU device. */
357#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
358/* @brief Index of port of external pin. */
359#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX)
360/* @brief Number of external pin port on specified port. */
361#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (23)
362/* @brief Has external pin 7 connected to LLWU device. */
363#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
364/* @brief Index of port of external pin. */
365#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX)
366/* @brief Number of external pin port on specified port. */
367#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (31)
368/* @brief Has external pin 8 connected to LLWU device. */
369#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
370/* @brief Index of port of external pin. */
371#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX)
372/* @brief Number of external pin port on specified port. */
373#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (1)
374/* @brief Has external pin 9 connected to LLWU device. */
375#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
376/* @brief Index of port of external pin. */
377#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOB_IDX)
378/* @brief Number of external pin port on specified port. */
379#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (3)
380/* @brief Has external pin 10 connected to LLWU device. */
381#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
382/* @brief Index of port of external pin. */
383#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOB_IDX)
384/* @brief Number of external pin port on specified port. */
385#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
386/* @brief Has external pin 11 connected to LLWU device. */
387#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
388/* @brief Index of port of external pin. */
389#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOB_IDX)
390/* @brief Number of external pin port on specified port. */
391#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (7)
392/* @brief Has external pin 12 connected to LLWU device. */
393#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
394/* @brief Index of port of external pin. */
395#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOB_IDX)
396/* @brief Number of external pin port on specified port. */
397#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (9)
398/* @brief Has external pin 13 connected to LLWU device. */
399#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
400/* @brief Index of port of external pin. */
401#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOB_IDX)
402/* @brief Number of external pin port on specified port. */
403#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (14)
404/* @brief Has external pin 14 connected to LLWU device. */
405#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
406/* @brief Index of port of external pin. */
407#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOB_IDX)
408/* @brief Number of external pin port on specified port. */
409#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (16)
410/* @brief Has external pin 15 connected to LLWU device. */
411#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
412/* @brief Index of port of external pin. */
413#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOB_IDX)
414/* @brief Number of external pin port on specified port. */
415#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (19)
416/* @brief Has external pin 16 connected to LLWU device. */
417#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
418/* @brief Index of port of external pin. */
419#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
420/* @brief Number of external pin port on specified port. */
421#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
422/* @brief Has external pin 17 connected to LLWU device. */
423#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
424/* @brief Index of port of external pin. */
425#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
426/* @brief Number of external pin port on specified port. */
427#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
428/* @brief Has external pin 18 connected to LLWU device. */
429#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
430/* @brief Index of port of external pin. */
431#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
432/* @brief Number of external pin port on specified port. */
433#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
434/* @brief Has external pin 19 connected to LLWU device. */
435#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
436/* @brief Index of port of external pin. */
437#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
438/* @brief Number of external pin port on specified port. */
439#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
440/* @brief Has external pin 20 connected to LLWU device. */
441#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
442/* @brief Index of port of external pin. */
443#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
444/* @brief Number of external pin port on specified port. */
445#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
446/* @brief Has external pin 21 connected to LLWU device. */
447#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
448/* @brief Index of port of external pin. */
449#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
450/* @brief Number of external pin port on specified port. */
451#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
452/* @brief Has external pin 22 connected to LLWU device. */
453#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
454/* @brief Index of port of external pin. */
455#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
456/* @brief Number of external pin port on specified port. */
457#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
458/* @brief Has external pin 23 connected to LLWU device. */
459#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
460/* @brief Index of port of external pin. */
461#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
462/* @brief Number of external pin port on specified port. */
463#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
464/* @brief Has external pin 24 connected to LLWU device. */
465#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
466/* @brief Index of port of external pin. */
467#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
468/* @brief Number of external pin port on specified port. */
469#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
470/* @brief Has external pin 25 connected to LLWU device. */
471#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
472/* @brief Index of port of external pin. */
473#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
474/* @brief Number of external pin port on specified port. */
475#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
476/* @brief Has external pin 26 connected to LLWU device. */
477#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
478/* @brief Index of port of external pin. */
479#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
480/* @brief Number of external pin port on specified port. */
481#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
482/* @brief Has external pin 27 connected to LLWU device. */
483#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
484/* @brief Index of port of external pin. */
485#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
486/* @brief Number of external pin port on specified port. */
487#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
488/* @brief Has external pin 28 connected to LLWU device. */
489#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
490/* @brief Index of port of external pin. */
491#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
492/* @brief Number of external pin port on specified port. */
493#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
494/* @brief Has external pin 29 connected to LLWU device. */
495#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
496/* @brief Index of port of external pin. */
497#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
498/* @brief Number of external pin port on specified port. */
499#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
500/* @brief Has external pin 30 connected to LLWU device. */
501#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
502/* @brief Index of port of external pin. */
503#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
504/* @brief Number of external pin port on specified port. */
505#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
506/* @brief Has external pin 31 connected to LLWU device. */
507#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
508/* @brief Index of port of external pin. */
509#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
510/* @brief Number of external pin port on specified port. */
511#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
512/* @brief Has internal module 0 connected to LLWU device. */
513#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
514/* @brief Has internal module 1 connected to LLWU device. */
515#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
516/* @brief Has internal module 2 connected to LLWU device. */
517#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
518/* @brief Has internal module 3 connected to LLWU device. */
519#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
520/* @brief Has internal module 4 connected to LLWU device. */
521#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
522/* @brief Has internal module 5 connected to LLWU device. */
523#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
524/* @brief Has internal module 6 connected to LLWU device. */
525#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (1)
526/* @brief Has internal module 7 connected to LLWU device. */
527#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
528/* @brief Has LLWU_VERID. */
529#define FSL_FEATURE_LLWU_HAS_VERID (1)
530/* @brief Has LLWU_PARAM. */
531#define FSL_FEATURE_LLWU_HAS_PARAM (1)
532/* @brief LLWU register bit width. */
533#define FSL_FEATURE_LLWU_REG_BITWIDTH (32)
534/* @brief Has DMA Enable register LLWU_DE. */
535#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
536
537/* LMEM module features */
538
539/* @brief Has process identifier support. */
540#define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (0)
541/* @brief Support instruction cache demote. */
542#define FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE (1)
543/* @brief Has no NONCACHEABLE section. */
544#define FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION (1)
545/* @brief L1 ICACHE line size in byte. */
546#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32)
547/* @brief L1 DCACHE line size in byte. */
548#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32)
549
550/* LPI2C module features */
551
552/* @brief Has separate DMA RX and TX requests. */
553#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
554/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
555#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
556
557/* LPIT module features */
558
559/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
560#define FSL_FEATURE_LPIT_TIMER_COUNT (4)
561/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
562#define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0)
563/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
564#define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (0)
565
566/* LPSPI module features */
567
568/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
569#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) \
570 (((x) == LPSPI0) ? (4) : \
571 (((x) == LPSPI1) ? (4) : \
572 (((x) == LPSPI2) ? (16) : \
573 (((x) == LPSPI3) ? (16) : (-1)))))
574/* @brief Has separate DMA RX and TX requests. */
575#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
576
577/* LPTMR module features */
578
579/* @brief Has shared interrupt handler with another LPTMR module. */
580#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
581/* @brief Whether LPTMR counter is 32 bits width. */
582#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
583/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
584#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1)
585/* @brief Do not has prescaler clock source 1. */
586#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0)
587
588/* LPUART module features */
589
590/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
591#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
592/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
593#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
594/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
595#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
596/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
597#define FSL_FEATURE_LPUART_HAS_FIFO (1)
598/* @brief Has 32-bit register MODIR */
599#define FSL_FEATURE_LPUART_HAS_MODIR (1)
600/* @brief Hardware flow control (RTS, CTS) is supported. */
601#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
602/* @brief Infrared (modulation) is supported. */
603#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
604/* @brief 2 bits long stop bit is available. */
605#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
606/* @brief If 10-bit mode is supported. */
607#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
608/* @brief If 7-bit mode is supported. */
609#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
610/* @brief Baud rate fine adjustment is available. */
611#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
612/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
613#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
614/* @brief Baud rate oversampling is available. */
615#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
616/* @brief Baud rate oversampling is available. */
617#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
618/* @brief Peripheral type. */
619#define FSL_FEATURE_LPUART_IS_SCI (1)
620/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
621#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \
622 (((x) == LPUART0) ? (4) : \
623 (((x) == LPUART1) ? (4) : \
624 (((x) == LPUART2) ? (8) : \
625 (((x) == LPUART3) ? (8) : \
626 (((x) == LPUART4) ? (8) : \
627 (((x) == LPUART5) ? (8) : \
628 (((x) == LPUART6) ? (8) : \
629 (((x) == LPUART7) ? (8) : (-1)))))))))
630/* @brief Supports two match addresses to filter incoming frames. */
631#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
632/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
633#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
634/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
635#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
636/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
637#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
638/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
639#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
640/* @brief Has improved smart card (ISO7816 protocol) support. */
641#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
642/* @brief Has local operation network (CEA709.1-B protocol) support. */
643#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
644/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
645#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
646/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
647#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
648/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
649#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
650/* @brief Has separate DMA RX and TX requests. */
651#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
652/* @brief Has separate RX and TX interrupts. */
653#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
654/* @brief Has LPAURT_PARAM. */
655#define FSL_FEATURE_LPUART_HAS_PARAM (1)
656/* @brief Has LPUART_VERID. */
657#define FSL_FEATURE_LPUART_HAS_VERID (1)
658/* @brief Has LPUART_GLOBAL. */
659#define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
660/* @brief Has LPUART_PINCFG. */
661#define FSL_FEATURE_LPUART_HAS_PINCFG (1)
662
663/* LTC module features */
664
665/* @brief LTC module supports DES algorithm. */
666#define FSL_FEATURE_LTC_HAS_DES (0)
667/* @brief LTC module supports PKHA algorithm. */
668#define FSL_FEATURE_LTC_HAS_PKHA (0)
669/* @brief LTC module supports SHA algorithm. */
670#define FSL_FEATURE_LTC_HAS_SHA (0)
671/* @brief LTC module supports AES GCM mode. */
672#define FSL_FEATURE_LTC_HAS_GCM (0)
673/* @brief LTC module supports DPAMS registers. */
674#define FSL_FEATURE_LTC_HAS_DPAMS (0)
675/* @brief LTC module supports AES with 24 bytes key. */
676#define FSL_FEATURE_LTC_HAS_AES192 (0)
677/* @brief LTC module supports AES with 32 bytes key. */
678#define FSL_FEATURE_LTC_HAS_AES256 (0)
679
680/* SMC module features */
681
682/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
683#define FSL_FEATURE_SMC_HAS_PSTOPO (0)
684/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
685#define FSL_FEATURE_SMC_HAS_LPOPO (0)
686/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
687#define FSL_FEATURE_SMC_HAS_PORPO (0)
688/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
689#define FSL_FEATURE_SMC_HAS_LPWUI (0)
690/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
691#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
692/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
693#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
694/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
695#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
696/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
697#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
698/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
699#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
700/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
701#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
702/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
703#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
704/* @brief Has stop submode. */
705#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (0)
706/* @brief Has stop submode 0(VLLS0). */
707#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (0)
708/* @brief Has stop submode 2(VLLS2). */
709#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0)
710/* @brief Has SMC_PARAM. */
711#define FSL_FEATURE_SMC_HAS_PARAM (1)
712/* @brief Has SMC_VERID. */
713#define FSL_FEATURE_SMC_HAS_VERID (1)
714/* @brief Has SMC_CSRE. */
715#define FSL_FEATURE_SMC_HAS_CSRE (1)
716/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
717#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1)
718/* @brief Has tamper reset (register bit SRS[TAMPER]). */
719#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (1)
720/* @brief Has security violation reset (register bit SRS[SECVIO]). */
721#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (1)
722/* @brief Has security violation reset (register bit SRS[VBAT]). */
723#define FSL_FEATURE_SMC_HAS_SRS_VBAT (1)
724/* @brief Has security violation reset (register bit SRS[CORE0]). */
725#define FSL_FEATURE_SMC_HAS_SRS_CORE0 (1)
726/* @brief Has security violation reset (register bit SRS[CORE1]). */
727#define FSL_FEATURE_SMC_HAS_SRS_CORE1 (1)
728/* @brief Has security violation reset (register bit SRIE[VBAT]). */
729#define FSL_FEATURE_SMC_HAS_SRIE_VBAT (1)
730/* @brief Has security violation reset (register bit SRIE[CORE0]). */
731#define FSL_FEATURE_SMC_HAS_SRIE_CORE0 (0)
732/* @brief Has security violation reset (register bit SRIE[CORE1]). */
733#define FSL_FEATURE_SMC_HAS_SRIE_CORE1 (0)
734/* @brief Width of SMC registers. */
735#define FSL_FEATURE_SMC_REG_WIDTH (32)
736
737/* MU module features */
738
739/* @brief MU side for current core */
740#define FSL_FEATURE_MU_SIDE_A (1)
741/* @brief MU Has register CCR */
742#define FSL_FEATURE_MU_HAS_CCR (0)
743/* @brief MU Has register SR[RS], BSR[ARS] */
744#define FSL_FEATURE_MU_HAS_SR_RS (1)
745/* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */
746#define FSL_FEATURE_MU_HAS_RESET_INT (1)
747/* @brief MU Has register SR[MURIP] */
748#define FSL_FEATURE_MU_HAS_SR_MURIP (0)
749/* @brief MU Has register SR[HRIP] */
750#define FSL_FEATURE_MU_HAS_SR_HRIP (0)
751/* @brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */
752#define FSL_FEATURE_MU_NO_CLKE (0)
753/* @brief MU does not support NMI, CR[NMI]. */
754#define FSL_FEATURE_MU_NO_NMI (0)
755/* @brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */
756#define FSL_FEATURE_MU_NO_RSTH (0)
757/* @brief MU does not supports MU reset, CR[MUR]. */
758#define FSL_FEATURE_MU_NO_MUR (0)
759/* @brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */
760#define FSL_FEATURE_MU_NO_HR (0)
761/* @brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */
762#define FSL_FEATURE_MU_HAS_HRM (0)
763/* @brief MU does not support check the other core power mode. SR[PM]. */
764#define FSL_FEATURE_MU_NO_PM (0)
765/* @brief MU supports reset assert interrupt. CR[RAIE] or BCR[RAIE]. */
766#define FSL_FEATURE_MU_HAS_RESET_ASSERT_INT (1)
767/* @brief MU supports reset de-assert interrupt. CR[RDIE] or BCR[RDIE]. */
768#define FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT (1)
769
770/* interrupt module features */
771
772/* @brief Lowest interrupt request number. */
773#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
774/* @brief Highest interrupt request number. */
775#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105)
776
777/* PCC module features */
778
779/* @brief PCC has SAI clock divider. */
780#define FSL_FEATURE_PCC_HAS_SAI_DIVIDER (1)
781/* @brief Remove EWM Clock Gate. */
782#define FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE (1)
783
784/* PORT module features */
785
786/* @brief Has control lock (register bit PCR[LK]). */
787#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
788/* @brief Has open drain control (register bit PCR[ODE]). */
789#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
790/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
791#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
792/* @brief Has DMA request (register bit field PCR[IRQC] values). */
793#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
794/* @brief Has pull resistor selection available. */
795#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (0)
796/* @brief Has pull resistor enable (register bit PCR[PE]). */
797#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (0)
798/* @brief Has slew rate control (register bit PCR[SRE]). */
799#define FSL_FEATURE_PORT_HAS_SLEW_RATE (0)
800/* @brief Has passive filter (register bit field PCR[PFE]). */
801#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (0)
802/* @brief Has drive strength control (register bit PCR[DSE]). */
803#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (0)
804/* @brief Has separate drive strength register (HDRVE). */
805#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
806/* @brief Has glitch filter (register IOFLT). */
807#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
808/* @brief Defines width of PCR[MUX] field. */
809#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (0)
810/* @brief Has dedicated interrupt vector. */
811#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
812/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
813#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (1)
814/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
815#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (1)
816/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
817#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (1)
818
819/* QSPI module features */
820
821/* @brief QSPI lookup table depth. */
822#define FSL_FEATURE_QSPI_LUT_DEPTH (64)
823/* @brief QSPI Tx FIFO depth. */
824#define FSL_FEATURE_QSPI_TXFIFO_DEPTH (16)
825/* @brief QSPI Rx FIFO depth. */
826#define FSL_FEATURE_QSPI_RXFIFO_DEPTH (16)
827/* @brief QSPI AHB buffer count. */
828#define FSL_FEATURE_QSPI_AHB_BUFFER_COUNT (4)
829/* @brief QSPI has command usage error flag. */
830#define FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR (0)
831/* @brief QSPI support parallel mode. */
832#define FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE (0)
833/* @brief QSPI support dual die. */
834#define FSL_FEATURE_QSPI_SUPPORT_DUAL_DIE (0)
835/* @brief there is no SCLKCFG bit in MCR register. */
836#define FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL (0)
837/* @brief there is no AITEF bit in FR register. */
838#define FSL_FEATURE_QSPI_HAS_NO_AITEF (1)
839/* @brief there is no AIBSEF bit in FR register. */
840#define FSL_FEATURE_QSPI_HAS_NO_AIBSEF (0)
841/* @brief there is no TXDMA and TXWA bit in SR register. */
842#define FSL_FEATURE_QSPI_HAS_NO_TXDMA (0)
843/* @brief there is no SFACR register. */
844#define FSL_FEATURE_QSPI_HAS_NO_SFACR (0)
845/* @brief there is no TDH bit in FLSHCR register. */
846#define FSL_FEATURE_QSPI_HAS_NO_TDH (0)
847/* @brief QSPI AHB buffer size in byte. */
848#define FSL_FEATURE_QSPI_AHB_BUFFER_SIZE (128U)
849/* @brief QSPI AMBA base address. */
850#define FSL_FEATURE_QSPI_AMBA_BASE (0xC0000000U)
851/* @brief QSPI AHB buffer ARDB base address. */
852#define FSL_FEATURE_QSPI_ARDB_BASE (0x24000000U)
853
854/* SCG module features */
855
856/* @brief Has platform clock divider SCG_CSR[DIVPLAT]. */
857#define FSL_FEATURE_SCG_HAS_DIVPLAT (1)
858/* @brief Has bus clock divider SCG_CSR[DIVBUS]. */
859#define FSL_FEATURE_SCG_HAS_DIVBUS (1)
860/* @brief Has external clock divide ratio SCG_CSR[DIVEXT]. */
861#define FSL_FEATURE_SCG_HAS_DIVEXT (0)
862/* @brief Has OSC capacitor setting SOSCCFG[SC2P ~ SC16P]. */
863#define FSL_FEATURE_SCG_HAS_OSC_SCXP (0)
864/* @brief Has SOSCCSR[SOSCERCLKEN]. */
865#define FSL_FEATURE_SCG_HAS_OSC_ERCLK (0)
866/* @brief Has OSC freq range SOSCCFG[RANGE]. */
867#define FSL_FEATURE_SCG_HAS_SOSC_RANGE (0)
868/* @brief Has CLKOUT configure register SCG_CLKOUTCNFG. */
869#define FSL_FEATURE_SCG_HAS_CLKOUTCNFG (1)
870/* @brief Has SCG_SOSCDIV[SOSCDIV1]. */
871#define FSL_FEATURE_SCG_HAS_SOSCDIV1 (1)
872/* @brief Has SCG_SOSCDIV[SOSCDIV3]. */
873#define FSL_FEATURE_SCG_HAS_SOSCDIV3 (1)
874/* @brief Has SCG_SIRCDIV[SIRCDIV1]. */
875#define FSL_FEATURE_SCG_HAS_SIRCDIV1 (1)
876/* @brief Has SCG_SIRCDIV[SIRCDIV3]. */
877#define FSL_FEATURE_SCG_HAS_SIRCDIV3 (1)
878/* @brief Has SCG_SIRCCSR[LPOPO]. */
879#define FSL_FEATURE_SCG_HAS_SIRC_LPOPO (1)
880/* @brief Has SCG_FIRCDIV[FIRCDIV1]. */
881#define FSL_FEATURE_SCG_HAS_FIRCDIV1 (1)
882/* @brief Has SCG_FIRCDIV[FIRCDIV3]. */
883#define FSL_FEATURE_SCG_HAS_FIRCDIV3 (1)
884/* @brief Has SCG_FIRCCSR[FIRCLPEN]. */
885#define FSL_FEATURE_SCG_HAS_FIRCLPEN (1)
886/* @brief Has SCG_FIRCCSR[FIRCREGOFF]. */
887#define FSL_FEATURE_SCG_HAS_FIRCREGOFF (0)
888/* @brief Has SCG_SPLLDIV[SPLLDIV1]. */
889#define FSL_FEATURE_SCG_HAS_SPLLDIV1 (1)
890/* @brief Has SCG_SPLLDIV[SPLLDIV3]. */
891#define FSL_FEATURE_SCG_HAS_SPLLDIV3 (1)
892/* @brief Has SCG_SPLLCFG[PLLPOSTDIV1]. */
893#define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV1 (0)
894/* @brief Has SCG_SPLLCFG[PLLPOSTDIV2]. */
895#define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV2 (0)
896/* @brief Has SCG_SPLLCFG[PLLS]. */
897#define FSL_FEATURE_SCG_HAS_SPLL_PLLS (1)
898/* @brief Has SCG_SPLLCFG[BYPASS]. */
899#define FSL_FEATURE_SCG_HAS_SPLL_BYPASS (0)
900/* @brief Has SCG_SPLLCFG[PFDSEL]. */
901#define FSL_FEATURE_SCG_HAS_SPLL_PFDSEL (1)
902/* @brief Has SCG_SPLLCSR[SPLLCM]. */
903#define FSL_FEATURE_SCG_HAS_SPLL_MONITOR (0)
904/* @brief Has SCG_LPFLLDIV[FLLDIV1]. */
905#define FSL_FEATURE_SCG_HAS_FLLDIV1 (0)
906/* @brief Has SCG_LPFLLDIV[FLLDIV3]. */
907#define FSL_FEATURE_SCG_HAS_FLLDIV3 (0)
908/* @brief Has low power FLL, SCG_LPFLLCSR. */
909#define FSL_FEATURE_SCG_HAS_LPFLL (0)
910/* @brief Has system PLL, SCG_SPLLCSR. */
911#define FSL_FEATURE_SCG_HAS_SPLL (1)
912/* @brief Has system PLL PFD, SCG_SPLLPFD. */
913#define FSL_FEATURE_SCG_HAS_SPLLPFD (1)
914/* @brief Has auxiliary PLL, SCG_APLLCSR. */
915#define FSL_FEATURE_SCG_HAS_APLL (1)
916/* @brief Has RTC OSC control, SCG_ROSCCSR. */
917#define FSL_FEATURE_SCG_HAS_ROSC (1)
918/* @brief Has RTC OSC clock source. */
919#define FSL_FEATURE_SCG_HAS_ROSC_SYS_CLK_SRC (1)
920/* @brief Has RTC OSC clock out select. */
921#define FSL_FEATURE_SCG_HAS_ROSC_CLKOUT (1)
922/* @brief Has EXTERNAL clock out select. */
923#define FSL_FEATURE_SCG_HAS_EXT_CLKOUT (0)
924/* @brief Has no System OSC configuration register, SCG_SOSCCFG. */
925#define FSL_FEATURE_SCG_HAS_NO_SOSCCFG (1)
926/* @brief Has no SCG_SOSCCSR[SOSCEN]. */
927#define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCEN (1)
928/* @brief Has no SCG_SOSCCSR[SOSCSTEN]. */
929#define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCSTEN (1)
930/* @brief Has no SCG_SOSCCSR[SOSCLPEN]. */
931#define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCLPEN (1)
932/* @brief Has no FIRC trim configuration register, SCG_FIRCTCFG. */
933#define FSL_FEATURE_SCG_HAS_NO_FIRCTCFG (1)
934/* @brief Has FIRC trim source USB0 Start of Frame. */
935#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB0 (1)
936/* @brief Has FIRC trim source USB1 Start of Frame. */
937#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB1 (1)
938/* @brief Has FIRC trim source system OSC. */
939#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_SOSC (1)
940/* @brief Has FIRC trim source RTC OSC. */
941#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_RTCOSC (1)
942
943/* SEMA42 module features */
944
945/* @brief Gate counts */
946#define FSL_FEATURE_SEMA42_GATE_COUNT (16)
947
948/* SIM module features */
949
950/* @brief Has USB FS divider. */
951#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
952/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
953#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
954/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
955#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
956/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
957#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
958/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
959#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (0)
960/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
961#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (0)
962/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
963#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
964/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
965#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
966/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
967#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
968/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
969#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
970/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
971#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
972/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
973#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
974/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
975#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
976/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
977#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
978/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
979#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
980/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
981#define FSL_FEATURE_SIM_OPT_UART_COUNT (0)
982/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
983#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
984/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
985#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
986/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
987#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
988/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
989#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
990/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
991#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
992/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
993#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
994/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
995#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
996/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
997#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
998/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
999#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
1000/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
1001#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
1002/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
1003#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
1004/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
1005#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
1006/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
1007#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
1008/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
1009#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
1010/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
1011#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
1012/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
1013#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
1014/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
1015#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
1016/* @brief Has FTM module(s) configuration. */
1017#define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
1018/* @brief Number of FTM modules. */
1019#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
1020/* @brief Number of FTM triggers with selectable source. */
1021#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
1022/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
1023#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
1024/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
1025#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
1026/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
1027#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
1028/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
1029#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
1030/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
1031#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
1032/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
1033#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
1034/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
1035#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
1036/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
1037#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
1038/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
1039#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
1040/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
1041#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
1042/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
1043#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
1044/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
1045#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
1046/* @brief Has TPM module(s) configuration. */
1047#define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
1048/* @brief The highest TPM module index. */
1049#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
1050/* @brief Has TPM module with index 0. */
1051#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
1052/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
1053#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
1054/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
1055#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
1056/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1057#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
1058/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
1059#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
1060/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1061#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
1062/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
1063#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
1064/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
1065#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
1066/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
1067#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
1068/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
1069#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
1070/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
1071#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
1072/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
1073#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
1074/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
1075#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
1076/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
1077#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
1078/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
1079#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
1080/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
1081#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
1082/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
1083#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
1084/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
1085#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
1086/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
1087#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
1088/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
1089#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
1090/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
1091#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
1092/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
1093#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
1094/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
1095#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
1096/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
1097#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
1098/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
1099#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
1100/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
1101#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
1102/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
1103#define FSL_FEATURE_SIM_OPT_ADC_COUNT (0)
1104/* @brief ADC module has alternate trigger (register bit SOPT7[ADC0ALTTRGEN]). */
1105#define FSL_FEATURE_SIM_OPT_ADC_HAS_ALTERNATE_TRIGGER (0)
1106/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
1107#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (0)
1108/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
1109#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0)
1110/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
1111#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
1112/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
1113#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
1114/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
1115#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
1116/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
1117#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
1118/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
1119#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
1120/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
1121#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
1122/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
1123#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
1124/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
1125#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
1126/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
1127#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
1128/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
1129#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
1130/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
1131#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (0)
1132/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
1133#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (0)
1134/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
1135#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
1136/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
1137#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
1138/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
1139#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
1140/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
1141#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
1142/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
1143#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
1144/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
1145#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
1146/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
1147#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
1148/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
1149#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
1150/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
1151#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
1152/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
1153#define FSL_FEATURE_SIM_SDID_HAS_FAMID (0)
1154/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
1155#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (0)
1156/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
1157#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (0)
1158/* @brief Has device die ID (register bit field SDID[DIEID]). */
1159#define FSL_FEATURE_SIM_SDID_HAS_DIEID (0)
1160/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
1161#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
1162/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
1163#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (0)
1164/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
1165#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (0)
1166/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
1167#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
1168/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
1169#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
1170/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
1171#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
1172/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
1173#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
1174/* @brief Has flash for core0(CM4) (register bit field FCFG1[CORE0_PFSIZE]). */
1175#define FSL_FEATURE_SIM_FCFG_HAS_CORE0_PFSIZE (0)
1176/* @brief Has flash for core1(CM0) (register bit field FCFG1[CORE1_PFSIZE]). */
1177#define FSL_FEATURE_SIM_FCFG_HAS_CORE1_PFSIZE (0)
1178/* @brief Has sram for core0(CM4) (register bit field FCFG1[CORE0_SRAMSIZE]). */
1179#define FSL_FEATURE_SIM_FCFG_HAS_CORE0_SRAMSIZE (0)
1180/* @brief Has sram for core1(CM0) (register bit field FCFG1[CORE1_SRAMSIZE]). */
1181#define FSL_FEATURE_SIM_FCFG_HAS_CORE1_SRAMSIZE (0)
1182/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
1183#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (0)
1184/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
1185#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
1186/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
1187#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
1188/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
1189#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
1190/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
1191#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
1192/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
1193#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
1194/* @brief Has miscellanious control register (register MCR). */
1195#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
1196/* @brief Has COP watchdog (registers COPC and SRVCOP). */
1197#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
1198/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
1199#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
1200/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
1201#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
1202/* @brief Has MISCCTRL reg. */
1203#define FSL_FEATURE_SIM_HAS_MISCCTRL (0)
1204/* @brief Has LTCEN bit (e.g SIM_MISCCTRL). */
1205#define FSL_FEATURE_SIM_HAS_MISCCTRL_LTCEN (0)
1206/* @brief Has DMAINTSEL0 bit (e.g SIM_MISCCTRL). */
1207#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL0 (0)
1208/* @brief Has DMAINTSEL1 bit (e.g SIM_MISCCTRL). */
1209#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL1 (0)
1210/* @brief Has DMAINTSEL2 bit (e.g SIM_MISCCTRL). */
1211#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL2 (0)
1212/* @brief Has DMAINTSEL3 bit (e.g SIM_MISCCTRL). */
1213#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL3 (0)
1214/* @brief Has SECKEY0 reg. */
1215#define FSL_FEATURE_SIM_HAS_SECKEY0 (0)
1216/* @brief Has SECKEY bit (e.g SIM_SECKEY0). */
1217#define FSL_FEATURE_SIM_HAS_SECKEY0_SECKEY (0)
1218/* @brief Has SECKEY1 reg. */
1219#define FSL_FEATURE_SIM_HAS_SECKEY1 (0)
1220/* @brief Has SECKEY bit (e.g SIM_SECKEY1). */
1221#define FSL_FEATURE_SIM_HAS_SECKEY1_SECKEY (0)
1222/* @brief Has SECKEY2 reg. */
1223#define FSL_FEATURE_SIM_HAS_SECKEY2 (0)
1224/* @brief Has SECKEY bit (e.g SIM_SECKEY2). */
1225#define FSL_FEATURE_SIM_HAS_SECKEY2_SECKEY (0)
1226/* @brief Has SECKEY3 reg. */
1227#define FSL_FEATURE_SIM_HAS_SECKEY3 (0)
1228/* @brief Has SECKEY bit (e.g SIM_SECKEY3). */
1229#define FSL_FEATURE_SIM_HAS_SECKEY3_SECKEY (0)
1230/* @brief Has no SDID reg. */
1231#define FSL_FEATURE_SIM_HAS_NO_SDID (1)
1232/* @brief Has no UID reg. */
1233#define FSL_FEATURE_SIM_HAS_NO_UID (1)
1234/* @brief Has RFADDRL and RFADDRH registers. */
1235#define FSL_FEATURE_SIM_HAS_RF_MAC_ADDR (0)
1236/* @brief Has SYSTICK_CLK_EN bit in SIM_MISC2 register. */
1237#define FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN (0)
1238/* @brief Has UIDM registers. */
1239#define FSL_FEATURE_SIM_HAS_UIDM (0)
1240
1241/* SNVS module features */
1242
1243/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */
1244#define FSL_FEATURE_SNVS_HAS_SRTC (1)
1245/* @brief Has Set Lock. */
1246#define FSL_FEATURE_SNVS_HAS_SET_LOCK (1)
1247/* @brief Has State Transition. */
1248#define FSL_FEATURE_SNVS_HAS_STATE_TRANSITION (1)
1249
1250/* SysTick module features */
1251
1252/* @brief Systick has external reference clock. */
1253#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
1254/* @brief Systick external reference clock is core clock divided by this value. */
1255#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
1256
1257/* TPM module features */
1258
1259/* @brief Number of channels. */
1260#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
1261 (((x) == TPM0) ? (6) : \
1262 (((x) == TPM1) ? (2) : \
1263 (((x) == TPM2) ? (2) : \
1264 (((x) == TPM3) ? (6) : \
1265 (((x) == TPM4) ? (6) : \
1266 (((x) == TPM5) ? (2) : \
1267 (((x) == TPM6) ? (2) : \
1268 (((x) == TPM7) ? (6) : (-1)))))))))
1269/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
1270#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
1271/* @brief Has TPM_PARAM. */
1272#define FSL_FEATURE_TPM_HAS_PARAM (1)
1273/* @brief Has TPM_VERID. */
1274#define FSL_FEATURE_TPM_HAS_VERID (1)
1275/* @brief Has TPM_GLOBAL. */
1276#define FSL_FEATURE_TPM_HAS_GLOBAL (1)
1277/* @brief Has TPM_TRIG. */
1278#define FSL_FEATURE_TPM_HAS_TRIG (1)
1279/* @brief Has counter pause on trigger. */
1280#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
1281/* @brief Has external trigger selection. */
1282#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
1283/* @brief Has TPM_COMBINE register. */
1284#define FSL_FEATURE_TPM_HAS_COMBINE (1)
1285/* @brief Whether COMBINE register has effect. */
1286#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1)
1287/* @brief Has TPM_POL. */
1288#define FSL_FEATURE_TPM_HAS_POL (1)
1289/* @brief Has TPM_FILTER register. */
1290#define FSL_FEATURE_TPM_HAS_FILTER (1)
1291/* @brief Whether FILTER register has effect. */
1292#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1)
1293/* @brief Has TPM_QDCTRL register. */
1294#define FSL_FEATURE_TPM_HAS_QDCTRL (1)
1295/* @brief Whether QDCTRL register has effect. */
1296#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1)
1297
1298/* TRNG module features */
1299
1300/* No feature definitions */
1301
1302/* TSTMR module features */
1303
1304/* @brief TSTMR clock frequency is 1MHZ. */
1305#define FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ (1)
1306
1307/* USBHS module features */
1308
1309/* @brief EHCI module instance count */
1310#define FSL_FEATURE_USBHS_EHCI_COUNT (2)
1311/* @brief Number of endpoints supported */
1312#define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
1313
1314/* USBPHY module features */
1315
1316/* @brief USBPHY contain DCD analog module */
1317#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0)
1318/* @brief USBPHY has register TRIM_OVERRIDE_EN */
1319#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1)
1320/* @brief USBPHY is 28FDSOI */
1321#define FSL_FEATURE_USBPHY_28FDSOI (0)
1322
1323/* WDOG module features */
1324
1325/* @brief Watchdog is available. */
1326#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
1327/* @brief WDOG_CNT can be 32-bit written. */
1328#define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1)
1329
1330/* XRDC module features */
1331
1332/* @brief Has domain ID of faulted access (register bit FDID[FDID]). */
1333#define FSL_FEATURE_XRDC_HAS_FDID (0)
1334/* @brief Has special 4-state model option (register bit PID[SP4SM]). */
1335#define FSL_FEATURE_XRDC_HAS_PID_SP4SM (0)
1336/* @brief Does not have logical partition identifier (register bit MDA_W[LPID]). */
1337#define FSL_FEATURE_XRDC_NO_MDA_LPID (1)
1338/* @brief Does not have logical partition enable option (register bit MDA_W[LPE]). */
1339#define FSL_FEATURE_XRDC_NO_MDA_LPE (1)
1340/* @brief Does not have peripheral semaphore enable option (register bit PDAC_W0[SE]). */
1341#define FSL_FEATURE_XRDC_NO_PDAC_SE (0)
1342/* @brief Does not have peripheral semaphore number (register bit PDAC_W0[SNUM]). */
1343#define FSL_FEATURE_XRDC_NO_PDAC_SNUM (0)
1344/* @brief Has peripheral excessive access lock owner (register bit PDAC_W0[EALO]). */
1345#define FSL_FEATURE_XRDC_HAS_PDAC_EALO (0)
1346/* @brief Has peripheral excessive access lock option (register bit PDAC_W1[EAL]). */
1347#define FSL_FEATURE_XRDC_HAS_PDAC_EAL (0)
1348/* @brief Has memory region end address (register bit MRGD_W1[ENDADDR]). */
1349#define FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR (0)
1350/* @brief Does not have region size configuration (register bit MRGD_W1[SZ]). */
1351#define FSL_FEATURE_XRDC_NO_MRGD_SZ (0)
1352/* @brief Does not have subregion disable option (register bit MRGD_W1[SRD]). */
1353#define FSL_FEATURE_XRDC_NO_MRGD_SRD (0)
1354/* @brief Does not have memory region semaphore enable option (register bit MRGD_W2[SE]). */
1355#define FSL_FEATURE_XRDC_NO_MRGD_SE (0)
1356/* @brief Does not have memory region semaphore number (register bit MRGD_W2[SNUM]). */
1357#define FSL_FEATURE_XRDC_NO_MRGD_SNUM (0)
1358/* @brief Does not domain x access control policy option (register bit MRGD_W2[DxACP]). */
1359#define FSL_FEATURE_XRDC_NO_MRGD_DXACP (0)
1360/* @brief Has memory region excessive access lock owner (register bit MRGD_W2[EALO]). */
1361#define FSL_FEATURE_XRDC_HAS_MRGD_EALO (0)
1362/* @brief Has domain x access policy select option (register bit MRGD_W2[DxSEL]). */
1363#define FSL_FEATURE_XRDC_HAS_MRGD_DXSEL (0)
1364/* @brief Has memory region excessive access lock option (register bit MRGD_W3[EAL]). */
1365#define FSL_FEATURE_XRDC_HAS_MRGD_EAL (0)
1366/* @brief Does not have lock option in MRGD_W3 register (register bit MRGD_W3[LK2]). */
1367#define FSL_FEATURE_XRDC_NO_MRGD_W3_LK2 (0)
1368/* @brief Does not have valid option in MRGD_W3 register (register bit MRGD_W3[VLD]). */
1369#define FSL_FEATURE_XRDC_NO_MRGD_W3_VLD (0)
1370/* @brief Has code region indicator select option (register bit MRGD_W3[CR]). */
1371#define FSL_FEATURE_XRDC_HAS_MRGD_CR (0)
1372/* @brief XRDC domain number (reset value of HWCFG0[NDID] plus 1). */
1373#define FSL_FEATURE_XRDC_DOMAIN_COUNT (8)
1374
1375#endif /* _MCIMX7U3_cm4_FEATURES_H_ */
1376
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