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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MCIMX7U5/MCIMX7U5_cm4.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MCIMX7U5/MCIMX7U5_cm4.h
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1/*
2** ###################################################################
3** Processors: MCIMX7U5CVP06
4** MCIMX7U5DVK07
5** MCIMX7U5DVP07
6**
7** Compilers: GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9** Keil ARM C/C++ Compiler
10**
11** Reference manual: IMX7ULPRM, Rev. 0, Nov. 2018
12** Version: rev. 7.0, 2018-11-05
13** Build: b200408
14**
15** Abstract:
16** CMSIS Peripheral Access Layer for MCIMX7U5_cm4
17**
18** Copyright 1997-2016 Freescale Semiconductor, Inc.
19** Copyright 2016-2020 NXP
20** All rights reserved.
21**
22** SPDX-License-Identifier: BSD-3-Clause
23**
24** http: www.nxp.com
25** mail: [email protected]
26**
27** Revisions:
28** - rev. 1.0 (2016-04-13)
29** Initial version.
30** - rev. 2.0 (2016-07-19)
31** RevC Header ER
32** - rev. 3.0 (2017-02-28)
33** RevD Header ER
34** - rev. 4.0 (2017-05-02)
35** RevE Header ER
36** - rev. 5.0 (2017-12-22)
37** RevA(B0) Header GA
38** - rev. 6.0 (2018-02-01)
39** RevB(B0) Header GA
40** - rev. 7.0 (2018-11-05)
41** RevA(B1) Header
42**
43** ###################################################################
44*/
45
46/*!
47 * @file MCIMX7U5_cm4.h
48 * @version 7.0
49 * @date 2018-11-05
50 * @brief CMSIS Peripheral Access Layer for MCIMX7U5_cm4
51 *
52 * CMSIS Peripheral Access Layer for MCIMX7U5_cm4
53 */
54
55#ifndef _MCIMX7U5_CM4_H_
56#define _MCIMX7U5_CM4_H_ /**< Symbol preventing repeated inclusion */
57
58/** Memory map major version (memory maps with equal major version number are
59 * compatible) */
60#define MCU_MEM_MAP_VERSION 0x0700U
61/** Memory map minor version */
62#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
63
64
65/* ----------------------------------------------------------------------------
66 -- Interrupt vector numbers
67 ---------------------------------------------------------------------------- */
68
69/*!
70 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
71 * @{
72 */
73
74/** Interrupt Number Definitions */
75#define NUMBER_OF_INT_VECTORS 144 /**< Number of interrupts in the Vector table */
76
77typedef enum IRQn {
78 /* Auxiliary constants */
79 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
80
81 /* Core interrupts */
82 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
83 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
84 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
85 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
86 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
87 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
88 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
89 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
90 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
91
92 /* Device specific interrupts */
93 CTI0_IRQn = 0, /**< Cross Trigger Interface for CM4 */
94 DMA0_0_4_IRQn = 1, /**< DMA Channel 0, 4 Transfer Complete */
95 DMA0_1_5_IRQn = 2, /**< DMA Channel 1, 5 Transfer Complete */
96 DMA0_2_6_IRQn = 3, /**< DMA Channel 2, 6 Transfer Complete */
97 DMA0_3_7_IRQn = 4, /**< DMA Channel 3, 7 Transfer Complete */
98 DMA0_8_12_IRQn = 5, /**< DMA Channel 8, 12 Transfer Complete */
99 DMA0_9_13_IRQn = 6, /**< DMA Channel 9, 13 Transfer Complete */
100 DMA0_10_14_IRQn = 7, /**< DMA Channel 10, 14 Transfer Complete */
101 DMA0_11_15_IRQn = 8, /**< DMA Channel 11, 15 Transfer Complete */
102 DMA0_16_20_IRQn = 9, /**< DMA Channel 16, 20 Transfer Complete */
103 DMA0_17_21_IRQn = 10, /**< DMA Channel 17, 21 Transfer Complete */
104 DMA0_18_22_IRQn = 11, /**< DMA Channel 18, 22 Transfer Complete */
105 DMA0_19_23_IRQn = 12, /**< DMA Channel 19, 23 Transfer Complete */
106 DMA0_24_28_IRQn = 13, /**< DMA Channel 24, 28 Transfer Complete */
107 DMA0_25_29_IRQn = 14, /**< DMA Channel 25, 29 Transfer Complete */
108 DMA0_26_30_IRQn = 15, /**< DMA Channel 26, 30 Transfer Complete */
109 DMA0_27_31_IRQn = 16, /**< DMA Channel 27, 31 Transfer Complete */
110 DMA0_Error_IRQn = 17, /**< DMA Error Interrupt - All Channels */
111 MCM0_IRQn = 18, /**< MCM Interrupt */
112 EWM_IRQn = 19, /**< External Watchdog Monitor Interrupt */
113 LLWU0_IRQn = 20, /**< Low Leakage Wake Up */
114 SIM_IRQn = 21, /**< System Integation Module */
115 MU_A_IRQn = 22, /**< Messaging Unit - Side A */
116 Reserved39_IRQn = 23, /**< Secured JTAG Controller */
117 Software1_IRQn = 24, /**< Software Interrupt */
118 Software2_IRQn = 25, /**< Software Interrupt */
119 WDOG0_IRQn = 26, /**< Watchdog Interrupt */
120 SCG0_IRQn = 27, /**< System Clock Generator for M4 domain */
121 QSPI_IRQn = 28, /**< Quad Serial Peripheral Interface */
122 LTC_IRQn = 29, /**< Low Power Trusted Cryptography */
123 XRDC_IRQn = 30, /**< Extended Domain Resource Controller */
124 SNVS_IRQn = 31, /**< Secure Non-Volatile Storage Consolidated Interrupt */
125 TRNG0_IRQn = 32, /**< Random Number Generator */
126 LPIT0_IRQn = 33, /**< Low Power Periodic Interrupt Timer */
127 PMC0_IRQn = 34, /**< Power Management Control interrupts for M4 domain */
128 CMC0_IRQn = 35, /**< Core Mode Controller interrupts for M4 domain */
129 LPTMR0_IRQn = 36, /**< Low Power Timer */
130 LPTMR1_IRQn = 37, /**< Low Power Timer */
131 TPM0_IRQn = 38, /**< Timer PWM module */
132 TPM1_IRQn = 39, /**< Timer PWM module */
133 TPM2_IRQn = 40, /**< Timer PWM module */
134 TPM3_IRQn = 41, /**< Timer PWM module */
135 FLEXIO0_IRQn = 42, /**< Flexible IO */
136 LPI2C0_IRQn = 43, /**< Inter-integrated circuit 0 */
137 LPI2C1_IRQn = 44, /**< Inter-integrated circuit 1 */
138 LPI2C2_IRQn = 45, /**< Inter-integrated circuit 2 */
139 LPI2C3_IRQn = 46, /**< Inter-integrated circuit 3 */
140 I2S0_IRQn = 47, /**< Serial Audio Interface 0 */
141 I2S1_IRQn = 48, /**< Serial Audio Interface 1 */
142 LPSPI0_IRQn = 49, /**< Low Power Serial Peripheral Interface */
143 LPSPI1_IRQn = 50, /**< Low Power Serial Peripheral Interface */
144 LPUART0_IRQn = 51, /**< Low Power UART */
145 LPUART1_IRQn = 52, /**< Low Power UART */
146 LPUART2_IRQn = 53, /**< Low Power UART */
147 LPUART3_IRQn = 54, /**< Low Power UART */
148 DPM_IRQn = 55, /**< Dynamic Process Monitor */
149 PCTLA_IRQn = 56, /**< Port A pin interrupt */
150 PCTLB_IRQn = 57, /**< Port B pin interrupt */
151 ADC0_IRQn = 58, /**< Analog to Digital Convertor */
152 ADC1_IRQn = 59, /**< Analog to Digital Convertor */
153 CMP0_IRQn = 60, /**< Comparator */
154 CMP1_IRQn = 61, /**< Comparator */
155 DAC0_IRQn = 62, /**< Digital to Analog Convertor */
156 DAC1_IRQn = 63, /**< Digital to Analog Convertor */
157 WDOG1_IRQn = 64, /**< Watchdog Interrupt from A7 subsystem */
158 USB0_IRQn = 65, /**< USB 0 Interrupt from A7 subsystem */
159 USB1_IRQn = 66, /**< USB 1 Interrupt from A7 subsystem */
160 Reserved83_IRQn = 67,
161 WDOG2_IRQn = 68, /**< Watchdog Interrupt from A7 subsystem */
162 USBPHY_IRQn = 69, /**< USB PHY (used in conjunction with USBOTG1) */
163 CMC1_IRQn = 70, /**< A7 resets */
164 Reserved87_IRQn = 71, /**< Reserved interrupt */
165 Reserved88_IRQn = 72, /**< Reserved interrupt */
166 Reserved89_IRQn = 73, /**< Reserved interrupt */
167 Reserved90_IRQn = 74, /**< Reserved interrupt */
168 GPU3D_IRQn = 75, /**< Graphics Processing Unit 3D */
169 GPU2D_IRQn = 76, /**< Graphics Processing Unit 2D */
170 Reserved93_IRQn = 77, /**< Reserved interrupt */
171 Reserved94_IRQn = 78, /**< Reserved interrupt */
172 Reserved95_IRQn = 79, /**< Reserved interrupt */
173 Reserved96_IRQn = 80, /**< Reserved interrupt */
174 Reserved97_IRQn = 81, /**< Reserved interrupt */
175 Reserved98_IRQn = 82, /**< Reserved interrupt */
176 Reserved99_IRQn = 83, /**< Reserved interrupt */
177 Reserved100_IRQn = 84, /**< Reserved interrupt */
178 Reserved101_IRQn = 85, /**< Reserved interrupt */
179 Reserved102_IRQn = 86, /**< Reserved interrupt */
180 Reserved103_IRQn = 87, /**< Reserved interrupt */
181 Reserved104_IRQn = 88, /**< Reserved interrupt */
182 Reserved105_IRQn = 89, /**< Reserved interrupt */
183 Reserved106_IRQn = 90, /**< Reserved interrupt */
184 Reserved107_IRQn = 91, /**< Reserved interrupt */
185 Reserved108_IRQn = 92, /**< Reserved interrupt */
186 Reserved109_IRQn = 93, /**< Reserved interrupt */
187 Reserved110_IRQn = 94, /**< Reserved interrupt */
188 Reserved111_IRQn = 95, /**< Reserved interrupt */
189 Reserved112_IRQn = 96, /**< Reserved interrupt */
190 Reserved113_IRQn = 97, /**< Reserved interrupt */
191 Reserved114_IRQn = 98, /**< Reserved interrupt */
192 Reserved115_IRQn = 99, /**< Reserved interrupt */
193 Reserved116_IRQn = 100, /**< Reserved interrupt */
194 Reserved117_IRQn = 101, /**< Reserved interrupt */
195 Reserved118_IRQn = 102, /**< Reserved interrupt */
196 Reserved119_IRQn = 103, /**< Reserved interrupt */
197 Reserved120_IRQn = 104, /**< Reserved interrupt */
198 Reserved121_IRQn = 105, /**< Reserved interrupt */
199 Reserved122_IRQn = 106, /**< Reserved interrupt */
200 Reserved123_IRQn = 107, /**< Reserved interrupt */
201 Reserved124_IRQn = 108, /**< Reserved interrupt */
202 Reserved125_IRQn = 109, /**< Reserved interrupt */
203 Reserved126_IRQn = 110, /**< Reserved interrupt */
204 Reserved127_IRQn = 111, /**< Reserved interrupt */
205 Reserved128_IRQn = 112, /**< Reserved interrupt */
206 Reserved129_IRQn = 113, /**< Reserved interrupt */
207 Reserved130_IRQn = 114, /**< Reserved interrupt */
208 Reserved131_IRQn = 115, /**< Reserved interrupt */
209 Reserved132_IRQn = 116, /**< Reserved interrupt */
210 Reserved133_IRQn = 117, /**< Reserved interrupt */
211 Reserved134_IRQn = 118, /**< Reserved interrupt */
212 Reserved135_IRQn = 119, /**< Reserved interrupt */
213 Reserved136_IRQn = 120, /**< Reserved interrupt */
214 Reserved137_IRQn = 121, /**< Reserved interrupt */
215 Reserved138_IRQn = 122, /**< Reserved interrupt */
216 Reserved139_IRQn = 123, /**< Reserved interrupt */
217 Reserved140_IRQn = 124, /**< Reserved interrupt */
218 Reserved141_IRQn = 125, /**< Reserved interrupt */
219 Reserved142_IRQn = 126, /**< Reserved interrupt */
220 Reserved143_IRQn = 127 /**< Reserved interrupt */
221} IRQn_Type;
222
223/*!
224 * @}
225 */ /* end of group Interrupt_vector_numbers */
226
227
228/* ----------------------------------------------------------------------------
229 -- Configuration of the Cortex-M4 Processor and Core Peripherals
230 ---------------------------------------------------------------------------- */
231
232/*!
233 * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-M4 Processor and Core Peripherals
234 * @{
235 */
236
237#define __CM4_REV 0x0001 /**< Core revision r0p1 */
238#define __MPU_PRESENT 1 /**< MPU present or not */
239#define __NVIC_PRIO_BITS 4 /**< Number of Bits used for Priority Levels */
240#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
241#define __FPU_PRESENT 1 /**< FPU present or not */
242
243#include "core_cm4.h" /* Core Peripheral Access Layer */
244#include "system_MCIMX7U5_cm4.h" /* Device specific configuration file */
245
246/*!
247 * @}
248 */ /* end of group Cortex_Core_Configuration */
249
250
251/* ----------------------------------------------------------------------------
252 -- Mapping Information
253 ---------------------------------------------------------------------------- */
254
255/*!
256 * @addtogroup Mapping_Information Mapping Information
257 * @{
258 */
259
260/** Mapping Information */
261/*!
262 * @addtogroup iomuxc0_pads
263 * @{ */
264
265/*******************************************************************************
266 * Definitions
267*******************************************************************************/
268
269/*!
270 * @brief Enumeration for the IOMUXC0 SW_MUX_CTL_PAD
271 *
272 * Defines the enumeration for the IOMUXC0 SW_MUX_CTL_PAD collections.
273 */
274typedef enum _iomuxc0_sw_mux_ctl_pad
275{
276 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA0 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
277 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA1 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
278 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA2 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
279 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA3 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
280 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA4 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
281 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA5 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
282 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA6 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
283 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA7 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
284 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA8 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
285 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA9 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
286 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
287 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
288 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
289 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
290 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
291 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
292 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA16 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */
293 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA17 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */
294 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA18 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */
295 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA19 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */
296 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA20 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */
297 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA21 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */
298 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA22 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */
299 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA23 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */
300 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA24 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */
301 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA25 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */
302 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA26 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */
303 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA27 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */
304 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA28 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */
305 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA29 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */
306 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA30 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */
307 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA31 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */
308 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB0 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */
309 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB1 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */
310 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB2 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */
311 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB3 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */
312 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB4 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */
313 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB5 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */
314 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB6 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */
315 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB7 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */
316 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB8 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */
317 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB9 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */
318 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB10 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */
319 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB11 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */
320 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB12 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */
321 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB13 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */
322 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB14 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */
323 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB15 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */
324 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB16 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */
325 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB17 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */
326 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB18 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */
327 kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB19 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */
328} iomuxc0_sw_mux_ctl_pad_t;
329
330/* @} */
331
332/*!
333 * @brief Enumeration for the IOMUXC0 select input
334 *
335 * Defines the enumeration for the IOMUXC0 select input collections.
336 */
337typedef enum _iomuxc0_select_input
338{
339 kIOMUXC0_IOMUXC0_LPSPI0_IPP_IND_LPSPI_PCS0_SELECT_INPUT = 0U, /**< IOMUXC select input index */
340 kIOMUXC0_IOMUXC0_LPSPI0_IPP_IND_LPSPI_PCS1_SELECT_INPUT = 1U, /**< IOMUXC select input index */
341 kIOMUXC0_IOMUXC0_LPSPI0_IPP_IND_LPSPI_PCS2_SELECT_INPUT = 2U, /**< IOMUXC select input index */
342 kIOMUXC0_IOMUXC0_LPSPI0_IPP_IND_LPSPI_PCS3_SELECT_INPUT = 3U, /**< IOMUXC select input index */
343 kIOMUXC0_IOMUXC0_LPSPI0_IPP_IND_LPSPI_SCK_SELECT_INPUT = 4U, /**< IOMUXC select input index */
344 kIOMUXC0_IOMUXC0_LPSPI0_IPP_IND_LPSPI_SDI_SELECT_INPUT = 5U, /**< IOMUXC select input index */
345 kIOMUXC0_IOMUXC0_LPSPI0_IPP_IND_LPSPI_SDO_SELECT_INPUT = 6U, /**< IOMUXC select input index */
346 kIOMUXC0_IOMUXC0_LPSPI1_IPP_IND_LPSPI_PCS0_SELECT_INPUT = 7U, /**< IOMUXC select input index */
347 kIOMUXC0_IOMUXC0_LPSPI1_IPP_IND_LPSPI_PCS1_SELECT_INPUT = 8U, /**< IOMUXC select input index */
348 kIOMUXC0_IOMUXC0_LPSPI1_IPP_IND_LPSPI_PCS2_SELECT_INPUT = 9U, /**< IOMUXC select input index */
349 kIOMUXC0_IOMUXC0_LPSPI1_IPP_IND_LPSPI_PCS3_SELECT_INPUT = 10U, /**< IOMUXC select input index */
350 kIOMUXC0_IOMUXC0_LPSPI1_IPP_IND_LPSPI_SCK_SELECT_INPUT = 11U, /**< IOMUXC select input index */
351 kIOMUXC0_IOMUXC0_LPSPI1_IPP_IND_LPSPI_SDI_SELECT_INPUT = 12U, /**< IOMUXC select input index */
352 kIOMUXC0_IOMUXC0_LPSPI1_IPP_IND_LPSPI_SDO_SELECT_INPUT = 13U, /**< IOMUXC select input index */
353 kIOMUXC0_IOMUXC0_LPTPM0_IPP_IND_LPTPM_CH0_SELECT_INPUT = 14U, /**< IOMUXC select input index */
354 kIOMUXC0_IOMUXC0_LPTPM0_IPP_IND_LPTPM_CH1_SELECT_INPUT = 15U, /**< IOMUXC select input index */
355 kIOMUXC0_IOMUXC0_LPTPM0_IPP_IND_LPTPM_CH2_SELECT_INPUT = 16U, /**< IOMUXC select input index */
356 kIOMUXC0_IOMUXC0_LPTPM0_IPP_IND_LPTPM_CH3_SELECT_INPUT = 17U, /**< IOMUXC select input index */
357 kIOMUXC0_IOMUXC0_LPTPM0_IPP_IND_LPTPM_CH4_SELECT_INPUT = 18U, /**< IOMUXC select input index */
358 kIOMUXC0_IOMUXC0_LPTPM0_IPP_IND_LPTPM_CH5_SELECT_INPUT = 19U, /**< IOMUXC select input index */
359 kIOMUXC0_IOMUXC0_LPTPM1_IPP_IND_LPTPM_CH0_SELECT_INPUT = 20U, /**< IOMUXC select input index */
360 kIOMUXC0_IOMUXC0_LPTPM1_IPP_IND_LPTPM_CH1_SELECT_INPUT = 21U, /**< IOMUXC select input index */
361 kIOMUXC0_IOMUXC0_LPTPM2_IPP_IND_LPTPM_CH0_SELECT_INPUT = 22U, /**< IOMUXC select input index */
362 kIOMUXC0_IOMUXC0_LPTPM2_IPP_IND_LPTPM_CH1_SELECT_INPUT = 23U, /**< IOMUXC select input index */
363 kIOMUXC0_IOMUXC0_LPTPM3_IPP_IND_LPTPM_CH0_SELECT_INPUT = 24U, /**< IOMUXC select input index */
364 kIOMUXC0_IOMUXC0_LPTPM3_IPP_IND_LPTPM_CH1_SELECT_INPUT = 25U, /**< IOMUXC select input index */
365 kIOMUXC0_IOMUXC0_LPTPM3_IPP_IND_LPTPM_CH2_SELECT_INPUT = 26U, /**< IOMUXC select input index */
366 kIOMUXC0_IOMUXC0_LPTPM3_IPP_IND_LPTPM_CH3_SELECT_INPUT = 27U, /**< IOMUXC select input index */
367 kIOMUXC0_IOMUXC0_LPTPM3_IPP_IND_LPTPM_CH4_SELECT_INPUT = 28U, /**< IOMUXC select input index */
368 kIOMUXC0_IOMUXC0_LPTPM3_IPP_IND_LPTPM_CH5_SELECT_INPUT = 29U, /**< IOMUXC select input index */
369 kIOMUXC0_IOMUXC0_LPI2C0_IPP_IND_LPI2C_HREQ_SELECT_INPUT = 30U, /**< IOMUXC select input index */
370 kIOMUXC0_IOMUXC0_LPI2C0_IPP_IND_LPI2C_SCL_SELECT_INPUT = 31U, /**< IOMUXC select input index */
371 kIOMUXC0_IOMUXC0_LPI2C0_IPP_IND_LPI2C_SDA_SELECT_INPUT = 32U, /**< IOMUXC select input index */
372 kIOMUXC0_IOMUXC0_LPI2C1_IPP_IND_LPI2C_HREQ_SELECT_INPUT = 33U, /**< IOMUXC select input index */
373 kIOMUXC0_IOMUXC0_LPI2C1_IPP_IND_LPI2C_SCL_SELECT_INPUT = 34U, /**< IOMUXC select input index */
374 kIOMUXC0_IOMUXC0_LPI2C1_IPP_IND_LPI2C_SDA_SELECT_INPUT = 35U, /**< IOMUXC select input index */
375 kIOMUXC0_IOMUXC0_LPI2C2_IPP_IND_LPI2C_HREQ_SELECT_INPUT = 36U, /**< IOMUXC select input index */
376 kIOMUXC0_IOMUXC0_LPI2C2_IPP_IND_LPI2C_SCL_SELECT_INPUT = 37U, /**< IOMUXC select input index */
377 kIOMUXC0_IOMUXC0_LPI2C2_IPP_IND_LPI2C_SDA_SELECT_INPUT = 38U, /**< IOMUXC select input index */
378 kIOMUXC0_IOMUXC0_LPI2C3_IPP_IND_LPI2C_HREQ_SELECT_INPUT = 39U, /**< IOMUXC select input index */
379 kIOMUXC0_IOMUXC0_LPI2C3_IPP_IND_LPI2C_SCL_SELECT_INPUT = 40U, /**< IOMUXC select input index */
380 kIOMUXC0_IOMUXC0_LPI2C3_IPP_IND_LPI2C_SDA_SELECT_INPUT = 41U, /**< IOMUXC select input index */
381 kIOMUXC0_IOMUXC0_LPTPM0_IPP_IND_LPTPM_CLK_SELECT_INPUT = 42U, /**< IOMUXC select input index */
382 kIOMUXC0_IOMUXC0_LPTPM1_IPP_IND_LPTPM_CLK_SELECT_INPUT = 43U, /**< IOMUXC select input index */
383 kIOMUXC0_IOMUXC0_LPTPM3_IPP_IND_LPTPM_CLK_SELECT_INPUT = 44U, /**< IOMUXC select input index */
384 kIOMUXC0_IOMUXC0_PCC_AIPS0_IPP_IND_EXTCLK55_SELECT_INPUT = 45U, /**< IOMUXC select input index */
385 kIOMUXC0_IOMUXC0_SAI0_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 46U, /**< IOMUXC select input index */
386 kIOMUXC0_IOMUXC0_SAI0_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 47U, /**< IOMUXC select input index */
387 kIOMUXC0_IOMUXC0_SAI0_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 48U, /**< IOMUXC select input index */
388 kIOMUXC0_IOMUXC0_SAI0_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 49U, /**< IOMUXC select input index */
389 kIOMUXC0_IOMUXC0_PCC_AIPS1_IPP_IND_EXTCLK42_SELECT_INPUT = 50U, /**< IOMUXC select input index */
390 kIOMUXC0_IOMUXC0_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 51U, /**< IOMUXC select input index */
391 kIOMUXC0_IOMUXC0_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 52U, /**< IOMUXC select input index */
392 kIOMUXC0_IOMUXC0_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 53U, /**< IOMUXC select input index */
393 kIOMUXC0_IOMUXC0_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 54U, /**< IOMUXC select input index */
394 kIOMUXC0_IOMUXC0_SAI0_IPP_IND_SAI_RXDATA0_SELECT_INPUT = 55U, /**< IOMUXC select input index */
395 kIOMUXC0_IOMUXC0_SAI0_IPP_IND_SAI_RXDATA1_SELECT_INPUT = 56U, /**< IOMUXC select input index */
396 kIOMUXC0_IOMUXC0_SAI1_IPP_IND_SAI_RXDATA0_SELECT_INPUT = 57U, /**< IOMUXC select input index */
397 kIOMUXC0_IOMUXC0_SAI1_IPP_IND_SAI_RXDATA1_SELECT_INPUT = 58U, /**< IOMUXC select input index */
398 kIOMUXC0_IOMUXC0_SAI1_IPP_IND_SAI_RXDATA2_SELECT_INPUT = 59U, /**< IOMUXC select input index */
399 kIOMUXC0_IOMUXC0_SAI1_IPP_IND_SAI_RXDATA3_SELECT_INPUT = 60U, /**< IOMUXC select input index */
400 kIOMUXC0_IOMUXC0_LPTPM2_IPP_IND_LPTPM_CLK_SELECT_INPUT = 61U, /**< IOMUXC select input index */
401 kIOMUXC0_IOMUXC0_LPUART0_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 62U, /**< IOMUXC select input index */
402 kIOMUXC0_IOMUXC0_LPUART0_IPP_IND_LPUART_RXD_SELECT_INPUT = 63U, /**< IOMUXC select input index */
403 kIOMUXC0_IOMUXC0_LPUART0_IPP_IND_LPUART_TXD_SELECT_INPUT = 64U, /**< IOMUXC select input index */
404 kIOMUXC0_IOMUXC0_LPUART1_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 65U, /**< IOMUXC select input index */
405 kIOMUXC0_IOMUXC0_LPUART1_IPP_IND_LPUART_RXD_SELECT_INPUT = 66U, /**< IOMUXC select input index */
406 kIOMUXC0_IOMUXC0_LPUART1_IPP_IND_LPUART_TXD_SELECT_INPUT = 67U, /**< IOMUXC select input index */
407 kIOMUXC0_IOMUXC0_LPUART2_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 68U, /**< IOMUXC select input index */
408 kIOMUXC0_IOMUXC0_LPUART2_IPP_IND_LPUART_RXD_SELECT_INPUT = 69U, /**< IOMUXC select input index */
409 kIOMUXC0_IOMUXC0_LPUART2_IPP_IND_LPUART_TXD_SELECT_INPUT = 70U, /**< IOMUXC select input index */
410 kIOMUXC0_IOMUXC0_LPUART3_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 71U, /**< IOMUXC select input index */
411 kIOMUXC0_IOMUXC0_LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT = 72U, /**< IOMUXC select input index */
412 kIOMUXC0_IOMUXC0_LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT = 73U, /**< IOMUXC select input index */
413 kIOMUXC0_IOMUXC0_D_IP_EWM_SYN_EWM_IN_SELECT_INPUT = 74U, /**< IOMUXC select input index */
414} iomuxc0_select_input_t;
415
416/*!
417 * @addtogroup iomuxc1_pads
418 * @{ */
419
420/*******************************************************************************
421 * Definitions
422*******************************************************************************/
423
424/*!
425 * @brief Enumeration for the IOMUXC1 SW_MUX_CTL_PAD
426 *
427 * Defines the enumeration for the IOMUXC1 SW_MUX_CTL_PAD collections.
428 */
429typedef enum _iomuxc1_sw_mux_ctl_pad
430{
431 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC0 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
432 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC1 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
433 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC2 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
434 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC3 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
435 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC4 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
436 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC5 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
437 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC6 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
438 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC7 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
439 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC8 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
440 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC9 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
441 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
442 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
443 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
444 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
445 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
446 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
447 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC16 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */
448 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC17 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */
449 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC18 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */
450 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC19 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */
451 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED0 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */
452 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED1 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */
453 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED2 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */
454 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED3 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */
455 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED4 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */
456 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED5 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */
457 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED6 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */
458 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED7 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */
459 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED8 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */
460 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED9 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */
461 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED10 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */
462 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED11 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */
463 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD0 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */
464 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD1 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */
465 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD2 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */
466 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD3 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */
467 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD4 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */
468 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD5 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */
469 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD6 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */
470 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD7 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */
471 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD8 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */
472 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD9 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */
473 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD10 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */
474 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD11 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */
475 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED12 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */
476 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED13 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */
477 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED14 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */
478 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED15 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */
479 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED16 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */
480 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED17 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */
481 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED18 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */
482 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED19 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */
483 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED20 = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */
484 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED21 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */
485 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED22 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */
486 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED23 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */
487 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED24 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */
488 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED25 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */
489 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED26 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */
490 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED27 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */
491 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED28 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */
492 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED29 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */
493 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED30 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */
494 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED31 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */
495 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE0 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */
496 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE1 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */
497 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE2 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */
498 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE3 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */
499 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE4 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */
500 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE5 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */
501 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE6 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */
502 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE7 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */
503 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE8 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */
504 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE9 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */
505 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE10 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */
506 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE11 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */
507 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE12 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */
508 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE13 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */
509 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE14 = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */
510 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE15 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */
511 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED32 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */
512 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED33 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */
513 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED34 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */
514 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED35 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */
515 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED36 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */
516 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED37 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */
517 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED38 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */
518 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED39 = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */
519 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED40 = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */
520 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED41 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */
521 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED42 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */
522 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED43 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */
523 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED44 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */
524 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED45 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */
525 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED46 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */
526 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED47 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */
527 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF0 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */
528 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF1 = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */
529 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF2 = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */
530 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF3 = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */
531 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF4 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */
532 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF5 = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */
533 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF6 = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */
534 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF7 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */
535 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF8 = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */
536 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF9 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */
537 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF10 = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */
538 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF11 = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */
539 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF12 = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */
540 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF13 = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */
541 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF14 = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */
542 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF15 = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */
543 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF16 = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */
544 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF17 = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */
545 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF18 = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */
546 kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF19 = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */
547} iomuxc1_sw_mux_ctl_pad_t;
548
549/*!
550 * @brief Enumeration for the IOMUXC1 select input
551 *
552 * Defines the enumeration for the IOMUXC1 select input collections.
553 */
554typedef enum _iomuxc1_select_input
555{
556 kIOMUXC1_IOMUXC1_USDHC1_IPP_WP_ON_SELECT_INPUT = 0U, /**< IOMUXC select input index */
557 kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO0_SELECT_INPUT = 1U, /**< IOMUXC select input index */
558 kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO1_SELECT_INPUT = 2U, /**< IOMUXC select input index */
559 kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO2_SELECT_INPUT = 3U, /**< IOMUXC select input index */
560 kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO3_SELECT_INPUT = 4U, /**< IOMUXC select input index */
561 kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO4_SELECT_INPUT = 5U, /**< IOMUXC select input index */
562 kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO5_SELECT_INPUT = 6U, /**< IOMUXC select input index */
563 kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO6_SELECT_INPUT = 7U, /**< IOMUXC select input index */
564 kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO7_SELECT_INPUT = 8U, /**< IOMUXC select input index */
565 kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO8_SELECT_INPUT = 9U, /**< IOMUXC select input index */
566 kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO9_SELECT_INPUT = 10U, /**< IOMUXC select input index */
567 kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO10_SELECT_INPUT = 11U, /**< IOMUXC select input index */
568 kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO11_SELECT_INPUT = 12U, /**< IOMUXC select input index */
569 kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO12_SELECT_INPUT = 13U, /**< IOMUXC select input index */
570 kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO13_SELECT_INPUT = 14U, /**< IOMUXC select input index */
571 kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO14_SELECT_INPUT = 15U, /**< IOMUXC select input index */
572 kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO15_SELECT_INPUT = 16U, /**< IOMUXC select input index */
573 kIOMUXC1_IOMUXC1_LPUART4_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 17U, /**< IOMUXC select input index */
574 kIOMUXC1_IOMUXC1_LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT = 18U, /**< IOMUXC select input index */
575 kIOMUXC1_IOMUXC1_LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT = 19U, /**< IOMUXC select input index */
576 kIOMUXC1_IOMUXC1_LPUART5_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 20U, /**< IOMUXC select input index */
577 kIOMUXC1_IOMUXC1_LPUART5_IPP_IND_LPUART_RXD_SELECT_INPUT = 21U, /**< IOMUXC select input index */
578 kIOMUXC1_IOMUXC1_LPUART5_IPP_IND_LPUART_TXD_SELECT_INPUT = 22U, /**< IOMUXC select input index */
579 kIOMUXC1_IOMUXC1_LPUART6_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 23U, /**< IOMUXC select input index */
580 kIOMUXC1_IOMUXC1_LPUART6_IPP_IND_LPUART_RXD_SELECT_INPUT = 24U, /**< IOMUXC select input index */
581 kIOMUXC1_IOMUXC1_LPUART6_IPP_IND_LPUART_TXD_SELECT_INPUT = 25U, /**< IOMUXC select input index */
582 kIOMUXC1_IOMUXC1_LPUART7_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 26U, /**< IOMUXC select input index */
583 kIOMUXC1_IOMUXC1_LPUART7_IPP_IND_LPUART_RXD_SELECT_INPUT = 27U, /**< IOMUXC select input index */
584 kIOMUXC1_IOMUXC1_LPUART7_IPP_IND_LPUART_TXD_SELECT_INPUT = 28U, /**< IOMUXC select input index */
585 kIOMUXC1_IOMUXC1_LPI2C4_IPP_IND_LPI2C_HREQ_SELECT_INPUT = 29U, /**< IOMUXC select input index */
586 kIOMUXC1_IOMUXC1_LPI2C4_IPP_IND_LPI2C_SCL_SELECT_INPUT = 30U, /**< IOMUXC select input index */
587 kIOMUXC1_IOMUXC1_LPI2C4_IPP_IND_LPI2C_SDA_SELECT_INPUT = 31U, /**< IOMUXC select input index */
588 kIOMUXC1_IOMUXC1_LPTPM4_IPP_IND_LPTPM_CH0_SELECT_INPUT = 32U, /**< IOMUXC select input index */
589 kIOMUXC1_IOMUXC1_LPTPM4_IPP_IND_LPTPM_CH1_SELECT_INPUT = 33U, /**< IOMUXC select input index */
590 kIOMUXC1_IOMUXC1_LPTPM4_IPP_IND_LPTPM_CH2_SELECT_INPUT = 34U, /**< IOMUXC select input index */
591 kIOMUXC1_IOMUXC1_LPTPM4_IPP_IND_LPTPM_CH3_SELECT_INPUT = 35U, /**< IOMUXC select input index */
592 kIOMUXC1_IOMUXC1_LPTPM4_IPP_IND_LPTPM_CH4_SELECT_INPUT = 36U, /**< IOMUXC select input index */
593 kIOMUXC1_IOMUXC1_LPTPM4_IPP_IND_LPTPM_CH5_SELECT_INPUT = 37U, /**< IOMUXC select input index */
594 kIOMUXC1_IOMUXC1_LPTPM4_IPP_IND_LPTPM_CLK_SELECT_INPUT = 38U, /**< IOMUXC select input index */
595 kIOMUXC1_IOMUXC1_LPSPI2_IPP_IND_LPSPI_PCS0_SELECT_INPUT = 39U, /**< IOMUXC select input index */
596 kIOMUXC1_IOMUXC1_LPSPI2_IPP_IND_LPSPI_PCS1_SELECT_INPUT = 40U, /**< IOMUXC select input index */
597 kIOMUXC1_IOMUXC1_LPSPI2_IPP_IND_LPSPI_PCS2_SELECT_INPUT = 41U, /**< IOMUXC select input index */
598 kIOMUXC1_IOMUXC1_LPSPI2_IPP_IND_LPSPI_PCS3_SELECT_INPUT = 42U, /**< IOMUXC select input index */
599 kIOMUXC1_IOMUXC1_LPSPI2_IPP_IND_LPSPI_SCK_SELECT_INPUT = 43U, /**< IOMUXC select input index */
600 kIOMUXC1_IOMUXC1_LPSPI2_IPP_IND_LPSPI_SDI_SELECT_INPUT = 44U, /**< IOMUXC select input index */
601 kIOMUXC1_IOMUXC1_LPSPI2_IPP_IND_LPSPI_SDO_SELECT_INPUT = 45U, /**< IOMUXC select input index */
602 kIOMUXC1_IOMUXC1_LPI2C5_IPP_IND_LPI2C_HREQ_SELECT_INPUT = 46U, /**< IOMUXC select input index */
603 kIOMUXC1_IOMUXC1_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT = 47U, /**< IOMUXC select input index */
604 kIOMUXC1_IOMUXC1_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT = 48U, /**< IOMUXC select input index */
605 kIOMUXC1_IOMUXC1_LPTPM5_IPP_IND_LPTPM_CH0_SELECT_INPUT = 49U, /**< IOMUXC select input index */
606 kIOMUXC1_IOMUXC1_LPTPM5_IPP_IND_LPTPM_CH1_SELECT_INPUT = 50U, /**< IOMUXC select input index */
607 kIOMUXC1_IOMUXC1_LPTPM5_IPP_IND_LPTPM_CLK_SELECT_INPUT = 51U, /**< IOMUXC select input index */
608 kIOMUXC1_IOMUXC1_LPTPM6_IPP_IND_LPTPM_CH0_SELECT_INPUT = 52U, /**< IOMUXC select input index */
609 kIOMUXC1_IOMUXC1_LPTPM6_IPP_IND_LPTPM_CH1_SELECT_INPUT = 53U, /**< IOMUXC select input index */
610 kIOMUXC1_IOMUXC1_LPTPM6_IPP_IND_LPTPM_CLK_SELECT_INPUT = 54U, /**< IOMUXC select input index */
611 kIOMUXC1_IOMUXC1_LPTPM7_IPP_IND_LPTPM_CH0_SELECT_INPUT = 55U, /**< IOMUXC select input index */
612 kIOMUXC1_IOMUXC1_LPTPM7_IPP_IND_LPTPM_CH1_SELECT_INPUT = 56U, /**< IOMUXC select input index */
613 kIOMUXC1_IOMUXC1_LPTPM7_IPP_IND_LPTPM_CH2_SELECT_INPUT = 57U, /**< IOMUXC select input index */
614 kIOMUXC1_IOMUXC1_LPTPM7_IPP_IND_LPTPM_CH3_SELECT_INPUT = 58U, /**< IOMUXC select input index */
615 kIOMUXC1_IOMUXC1_LPTPM7_IPP_IND_LPTPM_CH4_SELECT_INPUT = 59U, /**< IOMUXC select input index */
616 kIOMUXC1_IOMUXC1_LPTPM7_IPP_IND_LPTPM_CH5_SELECT_INPUT = 60U, /**< IOMUXC select input index */
617 kIOMUXC1_IOMUXC1_LPTPM7_IPP_IND_LPTPM_CLK_SELECT_INPUT = 61U, /**< IOMUXC select input index */
618 kIOMUXC1_IOMUXC1_LPI2C6_IPP_IND_LPI2C_HREQ_SELECT_INPUT = 62U, /**< IOMUXC select input index */
619 kIOMUXC1_IOMUXC1_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT = 63U, /**< IOMUXC select input index */
620 kIOMUXC1_IOMUXC1_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT = 64U, /**< IOMUXC select input index */
621 kIOMUXC1_IOMUXC1_LPI2C7_IPP_IND_LPI2C_HREQ_SELECT_INPUT = 65U, /**< IOMUXC select input index */
622 kIOMUXC1_IOMUXC1_LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT = 66U, /**< IOMUXC select input index */
623 kIOMUXC1_IOMUXC1_LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT = 67U, /**< IOMUXC select input index */
624 kIOMUXC1_IOMUXC1_LPSPI3_IPP_IND_LPSPI_PCS0_SELECT_INPUT = 68U, /**< IOMUXC select input index */
625 kIOMUXC1_IOMUXC1_LPSPI3_IPP_IND_LPSPI_PCS1_SELECT_INPUT = 69U, /**< IOMUXC select input index */
626 kIOMUXC1_IOMUXC1_LPSPI3_IPP_IND_LPSPI_PCS2_SELECT_INPUT = 70U, /**< IOMUXC select input index */
627 kIOMUXC1_IOMUXC1_LPSPI3_IPP_IND_LPSPI_PCS3_SELECT_INPUT = 71U, /**< IOMUXC select input index */
628 kIOMUXC1_IOMUXC1_LPSPI3_IPP_IND_LPSPI_SCK_SELECT_INPUT = 72U, /**< IOMUXC select input index */
629 kIOMUXC1_IOMUXC1_LPSPI3_IPP_IND_LPSPI_SDI_SELECT_INPUT = 73U, /**< IOMUXC select input index */
630 kIOMUXC1_IOMUXC1_LPSPI3_IPP_IND_LPSPI_SDO_SELECT_INPUT = 74U, /**< IOMUXC select input index */
631 kIOMUXC1_IOMUXC1_USDHC1_IPP_CARD_DET_SELECT_INPUT = 75U, /**< IOMUXC select input index */
632 kIOMUXC1_IOMUXC1_USBO2_ULP1_IPP_IND_OTG_OC_SELECT_INPUT = 76U, /**< IOMUXC select input index */
633 kIOMUXC1_IOMUXC1_USBO2_ULP1_IPP_IND_OTG2_OC_SELECT_INPUT = 77U, /**< IOMUXC select input index */
634 kIOMUXC1_IOMUXC1_DA_IP_HS_USB2PHY_28FDSOI_USB_ID_SELECT_INPUT = 78U, /**< IOMUXC select input index */
635 kIOMUXC1_IOMUXC1_VIDEO_IN_IPP_IND_DE_SELECT_INPUT = 79U, /**< IOMUXC select input index */
636} iomuxc1_select_input_t;
637
638/* @} */
639
640/*!
641 * @addtogroup edma0_request
642 * @{ */
643
644/*******************************************************************************
645 * Definitions
646*******************************************************************************/
647
648/*!
649 * @brief Enumeration for the DMA0 hardware request
650 *
651 * Defines the enumeration for the DMA0 hardware request collections.
652 */
653typedef enum _dma0_request_source
654{
655 kDmaRequestMux0Disable = 0|0x100U, /**< Channel disabled */
656 kDmaRequestMux0QSPIRx = 1|0x100U, /**< QSPI Receive */
657 kDmaRequestMux0QSPITx = 2|0x100U, /**< QSPI Transmit */
658 kDmaRequestMux0LTCRx = 3|0x100U, /**< Low Power Trusted Cryptography RX */
659 kDmaRequestMux0LTCTx = 4|0x100U, /**< Low Power Trusted Cryptography TX */
660 kDmaRequestMux0LPTMR0 = 5|0x100U, /**< Low Power Timer */
661 kDmaRequestMux0LPTMR1 = 6|0x100U, /**< Low Power Timer */
662 kDmaRequestMux0TPM0Channel0 = 7|0x100U, /**< TPM0 Channel 0 */
663 kDmaRequestMux0TPM0Channel1 = 8|0x100U, /**< TPM0 Channel 1 */
664 kDmaRequestMux0TPM0Channel2 = 9|0x100U, /**< TPM0 Channel 2 */
665 kDmaRequestMux0TPM0Channel3 = 10|0x100U, /**< TPM0 Channel 3 */
666 kDmaRequestMux0TPM0Channel4 = 11|0x100U, /**< TPM0 Channel 4 */
667 kDmaRequestMux0TPM0Channel5 = 12|0x100U, /**< TPM0 Channel 5 */
668 kDmaRequestMux0TPM0Overflow = 13|0x100U, /**< TPM0 Overflow */
669 kDmaRequestMux0TPM1Channel0 = 14|0x100U, /**< TPM1 Channel 0 */
670 kDmaRequestMux0TPM1Channel1 = 15|0x100U, /**< TPM1 Channel 1 */
671 kDmaRequestMux0TPM1Overflow = 16|0x100U, /**< TPM1 Overflow */
672 kDmaRequestMux0TPM2Channel0 = 17|0x100U, /**< TPM2 Channel 0 */
673 kDmaRequestMux0TPM2Channel1 = 18|0x100U, /**< TPM2 Channel 1 */
674 kDmaRequestMux0TPM2Overflow = 19|0x100U, /**< TPM2 Overflow */
675 kDmaRequestMux0TPM3Channel0 = 20|0x100U, /**< TPM3 Channel 0 */
676 kDmaRequestMux0TPM3Channel1 = 21|0x100U, /**< TPM3 Channel 1 */
677 kDmaRequestMux0TPM3Channel2 = 22|0x100U, /**< TPM3 Channel 2 */
678 kDmaRequestMux0TPM3Channel3 = 23|0x100U, /**< TPM3 Channel 3 */
679 kDmaRequestMux0TPM3Channel4 = 24|0x100U, /**< TPM3 Channel 4 */
680 kDmaRequestMux0TPM3Channel5 = 25|0x100U, /**< TPM3 Channel 5 */
681 kDmaRequestMux0TPM3Overflow = 26|0x100U, /**< TPM3 Overflow */
682 kDmaRequestMux0FlexIO0Shifter0 = 27|0x100U, /**< FlexIO0 Shifter 0 */
683 kDmaRequestMux0FlexIO0Shifter1 = 28|0x100U, /**< FlexIO0 Shifter 1 */
684 kDmaRequestMux0FlexIO0Shifter2 = 29|0x100U, /**< FlexIO0 Shifter 2 */
685 kDmaRequestMux0FlexIO0Shifter3 = 30|0x100U, /**< FlexIO0 Shifter 3 */
686 kDmaRequestMux0FlexIO0Shifter4 = 31|0x100U, /**< FlexIO0 Shifter 4 */
687 kDmaRequestMux0FlexIO0Shifter5 = 32|0x100U, /**< FlexIO0 Shifter 5 */
688 kDmaRequestMux0FlexIO0Shifter6 = 33|0x100U, /**< FlexIO0 Shifter 6 */
689 kDmaRequestMux0FlexIO0Shifter7 = 34|0x100U, /**< FlexIO0 Shifter 7 */
690 kDmaRequestMux0LPI2C0Rx = 35|0x100U, /**< LPI2C0 Master/Slave Receive */
691 kDmaRequestMux0LPI2C0Tx = 36|0x100U, /**< LPI2C0 Master/Slave Transmit */
692 kDmaRequestMux0LPI2C1Rx = 37|0x100U, /**< LPI2C1 Master/Slave Receive */
693 kDmaRequestMux0LPI2C1Tx = 38|0x100U, /**< LPI2C1 Master/Slave Transmit */
694 kDmaRequestMux0LPI2C2Rx = 39|0x100U, /**< LPI2C2 Master/Slave Receive */
695 kDmaRequestMux0LPI2C2Tx = 40|0x100U, /**< LPI2C2 Master/Slave Transmit */
696 kDmaRequestMux0LPI2C3Rx = 41|0x100U, /**< LPI2C3 Master/Slave Receive */
697 kDmaRequestMux0LPI2C3Tx = 42|0x100U, /**< LPI2C3 Master/Slave Transmit */
698 kDmaRequestMux0SAI0Rx = 43|0x100U, /**< SAI0 Receive */
699 kDmaRequestMux0SAI0Tx = 44|0x100U, /**< SAI0 Transmit */
700 kDmaRequestMux0SAI1Rx = 45|0x100U, /**< SAI1 Receive */
701 kDmaRequestMux0SAI1Tx = 46|0x100U, /**< SAI1 Transmit */
702 kDmaRequestMux0LPSPI0Rx = 47|0x100U, /**< LPSPI0 Receive */
703 kDmaRequestMux0LPSPI0Tx = 48|0x100U, /**< LPSPI0 Transmit */
704 kDmaRequestMux0LPSPI1Rx = 49|0x100U, /**< LPSPI1 Receive */
705 kDmaRequestMux0LPSPI1Tx = 50|0x100U, /**< LPSPI1 Transmit */
706 kDmaRequestMux0LPUART0Rx = 51|0x100U, /**< LPUART0 Receive */
707 kDmaRequestMux0LPUART0Tx = 52|0x100U, /**< LPUART0 Transmit */
708 kDmaRequestMux0LPUART1Rx = 53|0x100U, /**< LPUART1 Receive */
709 kDmaRequestMux0LPUART1Tx = 54|0x100U, /**< LPUART1 Transmit */
710 kDmaRequestMux0LPUART2Rx = 55|0x100U, /**< LPUART2 Receive */
711 kDmaRequestMux0LPUART2Tx = 56|0x100U, /**< LPUART2 Transmit */
712 kDmaRequestMux0LPUART3Rx = 57|0x100U, /**< LPUART3 Receive */
713 kDmaRequestMux0LPUART3Tx = 58|0x100U, /**< LPUART3 Transmit */
714 kDmaRequestMux0PCTLA = 60|0x100U, /**< Port A pin request */
715 kDmaRequestMux0PCTLB = 61|0x100U, /**< Port B pin request */
716 kDmaRequestMux0ADC0 = 62|0x100U, /**< ADC0 Conversion Complete */
717 kDmaRequestMux0ADC1 = 63|0x100U, /**< ADC1 Conversion Complete */
718 kDmaRequestMux0CMP0 = 64|0x100U, /**< CMP0 Comparison Event */
719 kDmaRequestMux0CMP1 = 65|0x100U, /**< CMP1 Comparison Event */
720 kDmaRequestMux0DAC0 = 66|0x100U, /**< DAC0 Request */
721 kDmaRequestMux0DAC1 = 67|0x100U, /**< DAC1 Request */
722} dma0_request_source_t;
723
724/* @} */
725
726/*!
727 * @addtogroup edma1_request
728 * @{ */
729
730/*******************************************************************************
731 * Definitions
732*******************************************************************************/
733
734/*!
735 * @brief Enumeration for the DMA1 hardware request
736 *
737 * Defines the enumeration for the DMA1 hardware request collections.
738 */
739typedef enum _dma1_request_source
740{
741 kDmaRequestMux1Disable = 0|0x200U, /**< Channel disabled */
742 kDmaRequestMux1FlexIO1Shifter0 = 1|0x200U, /**< FlexIO1 Shifter 0 */
743 kDmaRequestMux1FlexIO1Shifter1 = 2|0x200U, /**< FlexIO1 Shifter 1 */
744 kDmaRequestMux1FlexIO1Shifter2 = 3|0x200U, /**< FlexIO1 Shifter 2 */
745 kDmaRequestMux1FlexIO1Shifter3 = 4|0x200U, /**< FlexIO1 Shifter 3 */
746 kDmaRequestMux1FlexIO1Shifter4 = 5|0x200U, /**< FlexIO1 Shifter 4 */
747 kDmaRequestMux1FlexIO1Shifter5 = 6|0x200U, /**< FlexIO1 Shifter 5 */
748 kDmaRequestMux1FlexIO1Shifter6 = 7|0x200U, /**< FlexIO1 Shifter 6 */
749 kDmaRequestMux1FlexIO1Shifter7 = 8|0x200U, /**< FlexIO1 Shifter 7 */
750 kDmaRequestMux1LPI2C4Rx = 9|0x200U, /**< LPI2C4 Master/Slave Receive */
751 kDmaRequestMux1LPI2C4Tx = 10|0x200U, /**< LPI2C4 Master/Slave Transmit */
752 kDmaRequestMux1LPI2C5Rx = 11|0x200U, /**< LPI2C5 Master/Slave Receive */
753 kDmaRequestMux1LPI2C5Tx = 12|0x200U, /**< LPI2C5 Master/Slave Transmit */
754 kDmaRequestMux1LPI2C6Rx = 13|0x200U, /**< LPI2C6 Master/Slave Receive */
755 kDmaRequestMux1LPI2C6Tx = 14|0x200U, /**< LPI2C6 Master/Slave Transmit */
756 kDmaRequestMux1LPI2C7Rx = 15|0x200U, /**< LPI2C7 Master/Slave Receive */
757 kDmaRequestMux1LPI2C7Tx = 16|0x200U, /**< LPI2C7 Master/Slave Transmit */
758 kDmaRequestMux1LPUART4Rx = 17|0x200U, /**< LPUART4 Receive */
759 kDmaRequestMux1LPUART4Tx = 18|0x200U, /**< LPUART4 Transmit */
760 kDmaRequestMux1LPUART5Rx = 19|0x200U, /**< LPUART5 Receive */
761 kDmaRequestMux1LPUART5Tx = 20|0x200U, /**< LPUART5 Transmit */
762 kDmaRequestMux1LPUART6Rx = 21|0x200U, /**< LPUART6 Receive */
763 kDmaRequestMux1LPUART6Tx = 22|0x200U, /**< LPUART6 Transmit */
764 kDmaRequestMux1LPUART7Rx = 23|0x200U, /**< LPUART7 Receive */
765 kDmaRequestMux1LPUART7Tx = 24|0x200U, /**< LPUART7 Transmit */
766 kDmaRequestMux1LPSPI2Rx = 25|0x200U, /**< LPSPI2 Receive */
767 kDmaRequestMux1LPSPI2Tx = 26|0x200U, /**< LPSPI2 Transmit */
768 kDmaRequestMux1LPSPI3Rx = 27|0x200U, /**< LPSPI3 Receive */
769 kDmaRequestMux1LPSPI3Tx = 28|0x200U, /**< LPSPI3 Transmit */
770 kDmaRequestMux1TPM4Channel0 = 29|0x200U, /**< TPM4 Channel 0 */
771 kDmaRequestMux1TPM4Channel1 = 30|0x200U, /**< TPM4 Channel 1 */
772 kDmaRequestMux1TPM4Channel2 = 31|0x200U, /**< TPM4 Channel 2 */
773 kDmaRequestMux1TPM4Channel3 = 32|0x200U, /**< TPM4 Channel 3 */
774 kDmaRequestMux1TPM4Channel4 = 33|0x200U, /**< TPM4 Channel 4 */
775 kDmaRequestMux1TPM4Channel5 = 34|0x200U, /**< TPM4 Channel 5 */
776 kDmaRequestMux1TPM4Overflow = 35|0x200U, /**< TPM4 Overflow */
777 kDmaRequestMux1TPM5Channel0 = 36|0x200U, /**< TPM5 Channel 0 */
778 kDmaRequestMux1TPM5Channel1 = 37|0x200U, /**< TPM5 Channel 1 */
779 kDmaRequestMux1TPM5Overflow = 38|0x200U, /**< TPM5 Overflow */
780 kDmaRequestMux1TPM6Channel3 = 39|0x200U, /**< TPM6 Channel 3 */
781 kDmaRequestMux1TPM6Channel4 = 40|0x200U, /**< TPM6 Channel 4 */
782 kDmaRequestMux1TPM6Overflow = 41|0x200U, /**< TPM6 Overflow */
783 kDmaRequestMux1TPM7Channel0 = 42|0x200U, /**< TPM7 Channel 0 */
784 kDmaRequestMux1TPM7Channel1 = 43|0x200U, /**< TPM7 Channel 1 */
785 kDmaRequestMux1TPM7Channel2 = 44|0x200U, /**< TPM7 Channel 2 */
786 kDmaRequestMux1TPM7Channel3 = 45|0x200U, /**< TPM7 Channel 3 */
787 kDmaRequestMux1TPM7Channel4 = 46|0x200U, /**< TPM7 Channel 4 */
788 kDmaRequestMux1TPM7Channel5 = 47|0x200U, /**< TPM7 Channel 5 */
789 kDmaRequestMux1TPM7Overflow = 48|0x200U, /**< TPM7 Overflow */
790 kDmaRequestMux1PCTLC = 51|0x200U, /**< Port Interrupt Control module C */
791 kDmaRequestMux1PCTLD = 52|0x200U, /**< Port Interrupt Control module D */
792 kDmaRequestMux1PCTLE = 53|0x200U, /**< Port Interrupt Control module E */
793 kDmaRequestMux1PCTLF = 54|0x200U, /**< Port Interrupt Control module F */
794 kDmaRequestMux1QSPIRx = 57|0x200U, /**< QSPI Receive */
795 kDmaRequestMux1QSPITx = 58|0x200U, /**< QSPI Transmit */
796 kDmaRequestMux1SAI0Rx = 59|0x200U, /**< SAI0 Receive */
797 kDmaRequestMux1SAI0Tx = 60|0x200U, /**< SAI0 Transmit */
798 kDmaRequestMux1SAI1Rx = 61|0x200U, /**< SAI1 Receive */
799 kDmaRequestMux1SAI1Tx = 62|0x200U, /**< SAI1 Transmit */
800 kDmaRequestMux1PCTLA = 63|0x200U, /**< Port Interrupt Control module A */
801 kDmaRequestMux1PCTLB = 64|0x200U, /**< Port Interrupt Control module B */
802} dma1_request_source_t;
803
804/* @} */
805
806/*!
807 * @addtogroup trgmux0_source
808 * @{ */
809
810/*******************************************************************************
811 * Definitions
812*******************************************************************************/
813
814/*!
815 * @brief Enumeration for the TRGMUX0 source
816 *
817 * Defines the enumeration for the TRGMUX0 source collections.
818 */
819typedef enum _trgmux0_source
820{
821 kTRGMUX0_SourceDisabled = 0U, /**< Trigger function is disabled */
822 kTRGMUX0_SourceFlexIO0Timer0 = 2U, /**< FlexIO0 Timer0 input is selected */
823 kTRGMUX0_SourceFlexIO0Timer1 = 3U, /**< FlexIO0 Timer1 input is selected */
824 kTRGMUX0_SourceFlexIO0Timer2 = 4U, /**< FlexIO0 Timer2 input is selected */
825 kTRGMUX0_SourceFlexIO0Timer3 = 5U, /**< FlexIO0 Timer3 input is selected */
826 kTRGMUX0_SourceFlexIO0Timer4 = 6U, /**< FlexIO0 Timer4 input is selected */
827 kTRGMUX0_SourceFlexIO0Timer5 = 7U, /**< FlexIO0 Timer5 input is selected */
828 kTRGMUX0_SourceFlexIO0Timer6 = 8U, /**< FlexIO0 Timer6 input is selected */
829 kTRGMUX0_SourceFlexIO0Timer7 = 9U, /**< FlexIO0 Timer7 input is selected */
830 kTRGMUX0_SourceTPM0Overflow = 10U, /**< TPM0 Overflow input is selected */
831 kTRGMUX0_SourceTPM0Channel0 = 11U, /**< TPM0 Channel0 input is selected */
832 kTRGMUX0_SourceTPM0Channel1 = 12U, /**< TPM0 Channel1 input is selected */
833 kTRGMUX0_SourceTPM1Overflow = 13U, /**< TPM1 Overflow input is selected */
834 kTRGMUX0_SourceTPM1Channel0 = 14U, /**< TPM1 Channel0 input is selected */
835 kTRGMUX0_SourceTPM1Channel1 = 15U, /**< TPM1 Channel1 input is selected */
836 kTRGMUX0_SourceTPM2Overflow = 16U, /**< TPM2 Overflow input is selected */
837 kTRGMUX0_SourceTPM2Channel0 = 17U, /**< TPM2 Channel0 input is selected */
838 kTRGMUX0_SourceTPM2Channel1 = 18U, /**< TPM2 Channel1 input is selected */
839 kTRGMUX0_SourceTPM3Overflow = 19U, /**< TPM3 Overflow input is selected */
840 kTRGMUX0_SourceTPM3Channel0 = 20U, /**< TPM3 Channel0 input is selected */
841 kTRGMUX0_SourceTPM3Channel1 = 21U, /**< TPM3 Channel1 input is selected */
842 kTRGMUX0_SourceLPIT0Channel0 = 22U, /**< LPIT0 Channel0 input is selected */
843 kTRGMUX0_SourceLPIT0Channel1 = 23U, /**< LPIT0 Channel1 input is selected */
844 kTRGMUX0_SourceLPIT0Channel2 = 24U, /**< LPIT0 Channel2 input is selected */
845 kTRGMUX0_SourceLPIT0Channel3 = 25U, /**< LPIT0 Channel3 input is selected */
846 kTRGMUX0_SourceLPUART0RxData = 30U, /**< LPUART0 RX Data input is selected */
847 kTRGMUX0_SourceLPUART0TxData = 31U, /**< LPUART0 TX Data input is selected */
848 kTRGMUX0_SourceLPUART0RxIdle = 32U, /**< LPUART0 RX Idle input is selected */
849 kTRGMUX0_SourceLPUART1RxData = 33U, /**< LPUART1 RX Data input is selected */
850 kTRGMUX0_SourceLPUART1TxData = 34U, /**< LPUART1 TX Data input is selected */
851 kTRGMUX0_SourceLPUART1RxIdle = 35U, /**< LPUART1 RX Idle input is selected */
852 kTRGMUX0_SourceLPUART2RxData = 36U, /**< LPUART2 RX Data input is selected */
853 kTRGMUX0_SourceLPUART2TxData = 37U, /**< LPUART2 TX Data input is selected */
854 kTRGMUX0_SourceLPUART2RxIdle = 38U, /**< LPUART2 RX Idle input is selected */
855 kTRGMUX0_SourceLPUART3RxData = 39U, /**< LPUART3 RX Data input is selected */
856 kTRGMUX0_SourceLPUART3TxData = 40U, /**< LPUART3 TX Data input is selected */
857 kTRGMUX0_SourceLPUART3RxIdle = 41U, /**< LPUART3 RX Idle input is selected */
858 kTRGMUX0_SourceLPI2C0MasterStop = 42U, /**< LPI2C0 Master Stop input is selected */
859 kTRGMUX0_SourceLPI2C0SlaveStop = 43U, /**< LPI2C0 Slave Stop input is selected */
860 kTRGMUX0_SourceLPI2C1MasterStop = 44U, /**< LPI2C1 Master Stop input is selected */
861 kTRGMUX0_SourceLPI2C1SlaveStop = 45U, /**< LPI2C1 Slave Stop input is selected */
862 kTRGMUX0_SourceLPI2C2MasterStop = 46U, /**< LPI2C2 Master Stop input is selected */
863 kTRGMUX0_SourceLPI2C2SlaveStop = 47U, /**< LPI2C2 Slave Stop input is selected */
864 kTRGMUX0_SourceLPI2C3MasterStop = 48U, /**< LPI2C3 Master Stop input is selected */
865 kTRGMUX0_SourceLPI2C3SlaveStop = 49U, /**< LPI2C3 Slave Stop input is selected */
866 kTRGMUX0_SourceLPSPI0Frame = 50U, /**< LPSPI0 Frame input is selected */
867 kTRGMUX0_SourceLPSPI0RxData = 51U, /**< LPSPI0 RX Data input is selected */
868 kTRGMUX0_SourceLPSPI1Frame = 52U, /**< LPSPI1 Frame input is selected */
869 kTRGMUX0_SourceLPSPI1RxData = 53U, /**< LPSPI1 RX Data input is selected */
870 kTRGMUX0_SourceLPTMR0 = 56U, /**< LPTMR0 input is selected */
871 kTRGMUX0_SourceLPTMR1 = 57U, /**< LPTMR1 input is selected */
872 kTRGMUX0_SourceCMP0Output = 58U, /**< CMP0 Output input is selected */
873 kTRGMUX0_SourceCMP1Output = 59U, /**< CMP1 Output input is selected */
874 kTRGMUX0_SourcePORTAPin = 64U, /**< PORT A Pin input is selected */
875 kTRGMUX0_SourcePORTBPin = 65U, /**< PORT B Pin input is selected */
876 kTRGMUX0_SourceI2S0TxFrameSync = 66U, /**< I2S0 TX Frame Sync input is selected */
877 kTRGMUX0_SourceI2S0RxFrameSync = 67U, /**< I2S0 RX Frame Sync input is selected */
878 kTRGMUX0_SourceI2S1TxFrameSync = 68U, /**< I2S1 TX Frame Sync input is selected */
879 kTRGMUX0_SourceI2S1RxFrameSync = 69U, /**< I2S1 RX Frame Sync input is selected */
880} trgmux0_source_t;
881
882/* @} */
883
884/*!
885 * @addtogroup trgmux1_source
886 * @{ */
887
888/*******************************************************************************
889 * Definitions
890*******************************************************************************/
891
892/*!
893 * @brief Enumeration for the TRGMUX1 source
894 *
895 * Defines the enumeration for the TRGMUX1 source collections.
896 */
897typedef enum _trgmux1_source
898{
899 kTRGMUX1_SourceDisabled = 0U, /**< Trigger function is disabled */
900 kTRGMUX1_SourceFlexIO1Timer0 = 1U, /**< FlexIO1 Timer0 input is selected */
901 kTRGMUX1_SourceFlexIO1Timer1 = 2U, /**< FlexIO1 Timer1 input is selected */
902 kTRGMUX1_SourceFlexIO1Timer2 = 3U, /**< FlexIO1 Timer2 input is selected */
903 kTRGMUX1_SourceFlexIO1Timer3 = 4U, /**< FlexIO1 Timer3 input is selected */
904 kTRGMUX1_SourceFlexIO1Timer4 = 5U, /**< FlexIO1 Timer4 input is selected */
905 kTRGMUX1_SourceFlexIO1Timer5 = 6U, /**< FlexIO1 Timer5 input is selected */
906 kTRGMUX1_SourceFlexIO1Timer6 = 7U, /**< FlexIO1 Timer6 input is selected */
907 kTRGMUX1_SourceFlexIO1Timer7 = 8U, /**< FlexIO1 Timer7 input is selected */
908 kTRGMUX1_SourceTPM4Overflow = 9U, /**< TPM4 Overflow input is selected */
909 kTRGMUX1_SourceTPM4Channel0 = 10U, /**< TPM4 Channel0 input is selected */
910 kTRGMUX1_SourceTPM4Channel1 = 11U, /**< TPM4 Channel1 input is selected */
911 kTRGMUX1_SourceTPM5Overflow = 12U, /**< TPM5 Overflow input is selected */
912 kTRGMUX1_SourceTPM5Channel0 = 13U, /**< TPM5 Channel0 input is selected */
913 kTRGMUX1_SourceTPM5Channel1 = 14U, /**< TPM5 Channel1 input is selected */
914 kTRGMUX1_SourceTPM6Overflow = 15U, /**< TPM6 Overflow input is selected */
915 kTRGMUX1_SourceTPM6Channel0 = 16U, /**< TPM6 Channel0 input is selected */
916 kTRGMUX1_SourceTPM6Channel1 = 17U, /**< TPM6 Channel1 input is selected */
917 kTRGMUX1_SourceTPM7Overflow = 18U, /**< TPM7 Overflow input is selected */
918 kTRGMUX1_SourceTPM7Channel0 = 19U, /**< TPM7 Channel0 input is selected */
919 kTRGMUX1_SourceTPM7Channel1 = 20U, /**< TPM7 Channel1 input is selected */
920 kTRGMUX1_SourceLPUART4RxData = 21U, /**< LPUART4 RX data input is selected */
921 kTRGMUX1_SourceLPUART4TxData = 22U, /**< LPUART4 TX data input is selected */
922 kTRGMUX1_SourceLPUART4RxIdle = 23U, /**< LPUART4 RX idle input is selected */
923 kTRGMUX1_SourceLPUART5RxData = 24U, /**< LPUART5 RX data input is selected */
924 kTRGMUX1_SourceLPUART5TxData = 25U, /**< LPUART5 TX data input is selected */
925 kTRGMUX1_SourceLPUART5RXIdle = 26U, /**< LPUART5 RX Idle input is selected */
926 kTRGMUX1_SourceLPUART6RxData = 27U, /**< LPUART6 RX data input is selected */
927 kTRGMUX1_SourceLPUART6TxData = 28U, /**< LPUART6 TX data input is selected */
928 kTRGMUX1_SourceLPUART6RxIdle = 29U, /**< LPUART6 RX idle input is selected */
929 kTRGMUX1_SourceLPUART7RxData = 30U, /**< LPUART7 RX data input is selected */
930 kTRGMUX1_SourceLPUART7TxData = 31U, /**< LPUART7 TX data input is selected */
931 kTRGMUX1_SourceLPUART7RxIdle = 32U, /**< LPUART7 RX idle input is selected */
932 kTRGMUX1_SourceLPI2C4MasterSTOP = 33U, /**< LPI2C4 Master STOP input is selected */
933 kTRGMUX1_SourceLPI2C4SlaveSTOP = 34U, /**< LPI2C4 Slave STOP input is selected */
934 kTRGMUX1_SourceLPI2C5MasterSTOP = 35U, /**< LPI2C5 Master STOP input is selected */
935 kTRGMUX1_SourceLPI2C5SlaveSTOP = 36U, /**< LPI2C5 Slave STOP input is selected */
936 kTRGMUX1_SourceLPI2C6MasterSTOP = 37U, /**< LPI2C6 Master STOP input is selected */
937 kTRGMUX1_SourceLPI2C6SlaveSTOP = 38U, /**< LPI2C6 Slave STOP input is selected */
938 kTRGMUX1_SourceLPI2C7MasterSTOP = 39U, /**< LPI2C7 Master STOP input is selected */
939 kTRGMUX1_SourceLPI2C7SlaveSTOP = 40U, /**< LPI2C7 Slave STOP input is selected */
940 kTRGMUX1_SourceLPSPI2Frame = 41U, /**< LPSPI2 Frame input is selected */
941 kTRGMUX1_SourceLPSPI2RxData = 42U, /**< LPSPI2 RX data input is selected */
942 kTRGMUX1_SourceLPSPI3Frame = 43U, /**< LPSPI3 Frame input is selected */
943 kTRGMUX1_SourceLPSPI3RxData = 44U, /**< LPSPI3 RX data input is selected */
944 kTRGMUX1_SourcePORTCPin = 45U, /**< PORT C Pin input is selected */
945 kTRGMUX1_SourcePORTDPin = 46U, /**< PORT D Pin input is selected */
946 kTRGMUX1_SourcePORTEPin = 47U, /**< PORT E Pin input is selected */
947 kTRGMUX1_SourcePORTFPin = 48U, /**< PORT F Pin input is selected */
948 kTRGMUX1_SourceUSB0StartOfFrame = 49U, /**< USB0 Start of Frame input is selected */
949 kTRGMUX1_SourceUSB1StartOfFrame = 50U, /**< USB1 Start of Frame input is selected */
950 kTRGMUX1_SourceLPIT1Channel0 = 51U, /**< LPIT1 Channel 0 input is selected */
951 kTRGMUX1_SourceLPIT1Channel1 = 52U, /**< LPIT1 Channel 1 input is selected */
952 kTRGMUX1_SourceLPIT1Channel2 = 53U, /**< LPIT1 Channel 2 input is selected */
953 kTRGMUX1_SourceLPIT1Channel3 = 54U, /**< LPIT1 Channel 3 input is selected */
954} trgmux1_source_t;
955
956/* @} */
957
958/*!
959 * @brief Enumeration for the TRGMUX0 device
960 *
961 * Defines the enumeration for the TRGMUX0 device collections.
962 */
963typedef enum _trgmux0_device
964{
965 kTRGMUX0_DMAMUX0_CH0_3 = 0U, /**< DMAMUX0 channel 0-3 trigger */
966 kTRGMUX0_DMAMUX0_CH4_7 = 1U, /**< DMAMUX0 channel 4-7 trigger */
967 kTRGMUX0_LPIT0 = 2U, /**< LPIT0 trigger 0-3 */
968 kTRGMUX0_TPM0 = 4U, /**< TPM0 channel 0-1 trigger */
969 kTRGMUX0_TPM1 = 5U, /**< TPM1 channel 0-1 trigger */
970 kTRGMUX0_TPM2 = 6U, /**< TPM2 channel 0-1 trigger */
971 kTRGMUX0_TPM3 = 7U, /**< TPM3 channel 0-1 trigger */
972 kTRGMUX0_ADC0 = 8U, /**< ADC0 Trigger A, B */
973 kTRGMUX0_ADC1 = 9U, /**< ADC1 Trigger A, B */
974 kTRGMUX0_CMP0 = 10U, /**< CMP0 Window trigger */
975 kTRGMUX0_CMP1 = 11U, /**< CMP1 Window trigger */
976 kTRGMUX0_DAC0 = 12U, /**< DAC0 Trigger */
977 kTRGMUX0_DAC1 = 13U, /**< DAC1 Trigger */
978 kTRGMUX0_LPUART0 = 14U, /**< LPUART0 input */
979 kTRGMUX0_LPUART1 = 15U, /**< LPUART1 input */
980 kTRGMUX0_LPUART2 = 16U, /**< LPUART2 input */
981 kTRGMUX0_LPUART3 = 17U, /**< LPUART3 input */
982 kTRGMUX0_LPI2C0 = 18U, /**< LPI2C0 Host request */
983 kTRGMUX0_LPI2C1 = 19U, /**< LPI2C1 Host request */
984 kTRGMUX0_LPI2C2 = 20U, /**< LPI2C2 Host request */
985 kTRGMUX0_LPI2C3 = 21U, /**< LPI2C3 Host request */
986 kTRGMUX0_LPSPI0 = 22U, /**< LPSPI0 Host request */
987 kTRGMUX0_LPSPI1 = 23U, /**< LPSPI1 Host request */
988 kTRGMUX0_FLEXIO0 = 24U, /**< FlexIO0 trigger 0-3 */
989} trgmux0_device_t;
990
991/*!
992 * @brief Enumeration for the TRGMUX1 device
993 *
994 * Defines the enumeration for the TRGMUX1 device collections.
995 */
996typedef enum _trgmux1_device
997{
998 kTRGMUX1_DMAMUX1_CH0_3 = 0U, /**< DMAMUX1 channel 0-3 trigger */
999 kTRGMUX1_DMAMUX1_CH4_7 = 1U, /**< DMAMUX1 channel 4-7 trigger */
1000 kTRGMUX1_TPM4 = 2U, /**< TPM4 channel 0-1 trigger */
1001 kTRGMUX1_TPM5 = 3U, /**< TPM5 channel 0-1 trigger */
1002 kTRGMUX1_TPM6 = 4U, /**< TPM6 channel 0-1 trigger */
1003 kTRGMUX1_TPM7 = 5U, /**< TPM7 channel 0-1 trigger */
1004 kTRGMUX1_LPUART4 = 6U, /**< LPUART4 input */
1005 kTRGMUX1_LPUART5 = 7U, /**< LPUART5 input */
1006 kTRGMUX1_LPUART6 = 8U, /**< LPUART6 input */
1007 kTRGMUX1_LPUART7 = 9U, /**< LPUART7 input */
1008 kTRGMUX1_LPI2C4 = 10U, /**< LPI2C4 Host request */
1009 kTRGMUX1_LPI2C5 = 11U, /**< LPI2C5 Host request */
1010 kTRGMUX1_LPI2C6 = 12U, /**< LPI2C6 Host request */
1011 kTRGMUX1_LPI2C7 = 13U, /**< LPI2C7 Host request */
1012 kTRGMUX1_LPSPI2 = 14U, /**< LPSPI2 Host request */
1013 kTRGMUX1_LPSPI3 = 15U, /**< LPSPI3 Host request */
1014 kTRGMUX1_FLEXIO1 = 16U, /**< FlexIO1 trigger 0-3 */
1015 kTRGMUX1_LPIT1 = 17U, /**< LPIT1 trigger 0-3 */
1016} trgmux1_device_t;
1017
1018/*!
1019 * @addtogroup xrdc_mapping
1020 * @{
1021 */
1022
1023/*******************************************************************************
1024 * Definitions
1025 ******************************************************************************/
1026
1027/*!
1028 * @brief Structure for the XRDC mapping
1029 *
1030 * Defines the structure for the XRDC resource collections.
1031 */
1032
1033typedef enum _xrdc_master
1034{
1035 kXRDC_MasterCM4Code = 0U, /**< Cortex-M4 Code Bus Master */
1036 kXRDC_MasterCM4System = 1U, /**< Cortex-M4 System Bus Master */
1037 kXRDC_MasterDma0 = 2U, /**< DMA0 Bus Master */
1038 kXRDC_MasterCA7 = 3U, /**< Cortex-A7 Bus Master */
1039 kXRDC_MasterLcdif = 4U, /**< LCDIF Bus Master */
1040 kXRDC_MasterGpu3D = 5U, /**< GPU 3D Bus Master */
1041 kXRDC_MasterDma1 = 6U, /**< DMA1 Bus Master */
1042 kXRDC_MasterAxbs2NIC1 = 7U, /**< AXBS2NIC1 Bus Master */
1043 kXRDC_MasterCaam = 8U, /**< CAAM Bus Master */
1044 kXRDC_MasterUsb_0_1 = 9U, /**< USB0/1 Bus Master */
1045 kXRDC_MasterViu = 10U, /**< VIU Bus Master */
1046 kXRDC_MasterSdhc0 = 11U, /**< SDHC0 Bus Master */
1047 kXRDC_MasterSdhc1 = 12U, /**< SDHC1 Bus Master */
1048 kXRDC_MasterGpu2D = 13U, /**< GPU 2D Bus Master */
1049} xrdc_master_t;
1050
1051/* @} */
1052
1053typedef enum _xrdc_mem
1054{
1055 kXRDC_MemMrc0_0 = 0U, /**< MRC0_0 Memory: Cortex-M4 TCMs */
1056 kXRDC_MemMrc0_1 = 1U, /**< MRC0_1 Memory: Cortex-M4 TCMs */
1057 kXRDC_MemMrc0_2 = 2U, /**< MRC0_2 Memory: Cortex-M4 TCMs */
1058 kXRDC_MemMrc0_3 = 3U, /**< MRC0_3 Memory: Cortex-M4 TCMs */
1059 kXRDC_MemMrc1_0 = 16U, /**< MRC1_0 Memory: QSPI Flash */
1060 kXRDC_MemMrc1_1 = 17U, /**< MRC1_1 Memory: QSPI Flash */
1061 kXRDC_MemMrc1_2 = 18U, /**< MRC1_2 Memory: QSPI Flash */
1062 kXRDC_MemMrc1_3 = 19U, /**< MRC1_3 Memory: QSPI Flash */
1063 kXRDC_MemMrc1_4 = 20U, /**< MRC1_4 Memory: QSPI Flash */
1064 kXRDC_MemMrc1_5 = 21U, /**< MRC1_5 Memory: QSPI Flash */
1065 kXRDC_MemMrc1_6 = 22U, /**< MRC1_6 Memory: QSPI Flash */
1066 kXRDC_MemMrc1_7 = 23U, /**< MRC1_7 Memory: QSPI Flash */
1067 kXRDC_MemMrc2_0 = 32U, /**< MRC2_0 Memory: SRAM0 */
1068 kXRDC_MemMrc2_1 = 33U, /**< MRC2_1 Memory: SRAM0 */
1069 kXRDC_MemMrc2_2 = 34U, /**< MRC2_2 Memory: SRAM0 */
1070 kXRDC_MemMrc2_3 = 35U, /**< MRC2_3 Memory: SRAM0 */
1071 kXRDC_MemMrc3_0 = 48U, /**< MRC3_0 Memory: SecRAM */
1072 kXRDC_MemMrc3_1 = 49U, /**< MRC3_1 Memory: SecRAM */
1073 kXRDC_MemMrc3_2 = 50U, /**< MRC3_2 Memory: SecRAM */
1074 kXRDC_MemMrc3_3 = 51U, /**< MRC3_3 Memory: SecRAM */
1075 kXRDC_MemMrc4_0 = 64U, /**< MRC4_0 Memory: FlexBus */
1076 kXRDC_MemMrc4_1 = 65U, /**< MRC4_1 Memory: FlexBus */
1077 kXRDC_MemMrc4_2 = 66U, /**< MRC4_2 Memory: FlexBus */
1078 kXRDC_MemMrc4_3 = 67U, /**< MRC4_3 Memory: FlexBus */
1079 kXRDC_MemMrc5_0 = 80U, /**< MRC5_0 Memory: SRAM1 */
1080 kXRDC_MemMrc5_1 = 81U, /**< MRC5_1 Memory: SRAM1 */
1081 kXRDC_MemMrc5_2 = 82U, /**< MRC5_2 Memory: SRAM1 */
1082 kXRDC_MemMrc5_3 = 83U, /**< MRC5_3 Memory: SRAM1 */
1083 kXRDC_MemMrc6_0 = 96U, /**< MRC6_0 Memory: MMDC Flash */
1084 kXRDC_MemMrc6_1 = 97U, /**< MRC6_1 Memory: MMDC Flash */
1085 kXRDC_MemMrc6_2 = 98U, /**< MRC6_2 Memory: MMDC Flash */
1086 kXRDC_MemMrc6_3 = 99U, /**< MRC6_3 Memory: MMDC Flash */
1087 kXRDC_MemMrc6_4 = 100U, /**< MRC6_4 Memory: MMDC Flash */
1088 kXRDC_MemMrc6_5 = 101U, /**< MRC6_5 Memory: MMDC Flash */
1089 kXRDC_MemMrc6_6 = 102U, /**< MRC6_6 Memory: MMDC Flash */
1090 kXRDC_MemMrc6_7 = 103U, /**< MRC6_7 Memory: MMDC Flash */
1091} xrdc_mem_t;
1092
1093typedef enum _xrdc_periph
1094{
1095 kXRDC_PeriphEdma0 = 8U, /**< Direct Memory Access Controller 0 */
1096 kXRDC_PeriphEdma0_tcd = 9U, /**< Direct Memory Access Controller 0 Transfer */
1097 kXRDC_PeriphRgpio0 = 15U, /**< Rapid GPIO Controller 0 */
1098 kXRDC_PeriphXrdc0 = 20U, /**< Extended Resource Domain Controller */
1099 kXRDC_PeriphXrdc1 = 21U, /**< Extended Resource Domain Controller */
1100 kXRDC_PeriphXrdc2 = 22U, /**< Extended Resource Domain Controller */
1101 kXRDC_PeriphXrdc3 = 23U, /**< Extended Resource Domain Controller */
1102 kXRDC_PeriphSema42_0 = 27U, /**< Hardware Semaphore Module 0 */
1103 kXRDC_PeriphDmamux0 = 32U, /**< Direct Memory Access Multiplexer 0 */
1104 kXRDC_PeriphLlwu = 33U, /**< Low-Leakage Wakeup Unit */
1105 kXRDC_PeriphMu_A = 34U, /**< Messaging Unit - Side A */
1106 kXRDC_PeriphTrgmux0 = 36U, /**< Trigger MUX Control 0 */
1107 kXRDC_PeriphWdog0 = 37U, /**< Watchdog Timer 0 */
1108 kXRDC_PeriphPcc0 = 38U, /**< Peripheral Clock Control 0 */
1109 kXRDC_PeriphScg0 = 39U, /**< System Clock Generator 0 */
1110 kXRDC_PeriphCrc = 41U, /**< Cyclic Redundancy Check */
1111 kXRDC_PeriphLtc = 42U, /**< Low Power Trusted Cryptography */
1112 kXRDC_PeriphTrng = 44U, /**< True Random Number Generator */
1113 kXRDC_PeriphLpit0 = 45U, /**< Low Power Interrupt Timer */
1114 kXRDC_PeriphLptmr0 = 46U, /**< Low Power Timer 0 */
1115 kXRDC_PeriphLptmr1 = 47U, /**< Low power Timer 1 */
1116 kXRDC_PeriphTpm0 = 48U, /**< Timer/PWM Module 0 */
1117 kXRDC_PeriphTpm1 = 49U, /**< Timer/PWM Module 1 */
1118 kXRDC_PeriphFlexio0 = 50U, /**< Flexible IO Controller 0 */
1119 kXRDC_PeriphLpi2c0 = 51U, /**< Low Power Inter-Integrated Circuit 0 */
1120 kXRDC_PeriphLpi2c1 = 52U, /**< Low Power Inter-Integrated Circuit 1 */
1121 kXRDC_PeriphLpi2c2 = 53U, /**< Low Power Inter-Integrated Circuit 2 */
1122 kXRDC_PeriphLpi2c3 = 54U, /**< Low Power Inter-Integrated Circuit 3 */
1123 kXRDC_PeriphSai0 = 55U, /**< Synchronous Audio Interface 0 */
1124 kXRDC_PeriphLpspi0 = 56U, /**< Low Power Serial Peripheral Interface 0 */
1125 kXRDC_PeriphLpspi1 = 57U, /**< Low Power Serial Peripheral Interface 1 */
1126 kXRDC_PeriphLpuart0 = 58U, /**< Low Power Universal Asynchronous Receiver/Transmitter 0 */
1127 kXRDC_PeriphLpuart1 = 59U, /**< Low Power Universal Asynchronous Receiver/Transmitter 1 */
1128 kXRDC_PeriphIomuxc0 = 61U, /**< Input/Output Multiplexing Controller 0 */
1129 kXRDC_PeriphPctlA = 63U, /**< Port Interrupt Control A */
1130 kXRDC_PeriphPctlB = 64U, /**< Port Interrupt Control B */
1131 kXRDC_PeriphAdc0 = 65U, /**< Analog to Digital Converter 0 */
1132 kXRDC_PeriphCmp0 = 66U, /**< Analog Comparator 0 */
1133 kXRDC_PeriphCmp1 = 67U, /**< Analog Comparator 1 */
1134 kXRDC_PeriphDac0 = 68U, /**< Digital to Analog Converter 0 */
1135 kXRDC_PeriphDac1 = 69U, /**< Digital to Analog Converter 1 */
1136 kXRDC_PeriphSnvs = 112U, /**< Secure Non-Volatile Storage */
1137 kXRDC_PeriphRomc0 = 144U, /**< ROM Controller 0 */
1138 kXRDC_PeriphDaprom = 145U, /**< Debug Access Port ROM */
1139 kXRDC_PeriphFunnel = 146U, /**< Coresight Funnel */
1140 kXRDC_PeriphEtf = 147U, /**< Embedded Trace FIFO */
1141 kXRDC_PeriphTpiu = 148U, /**< Trace Port Interface Unit */
1142 kXRDC_PeriphEtr = 149U, /**< Embedded Trace Router */
1143 kXRDC_PeriphCti = 150U, /**< Cross Trigger Interface */
1144 kXRDC_PeriphSwo = 151U, /**< Single Wire Output */
1145 kXRDC_PeriphTimestampGen = 152U, /**< Timestamp Generator */
1146 kXRDC_PeriphA7_apb_rom = 154U, /**< Cortex-A7 APB ROM */
1147 kXRDC_PeriphA7_apb_cpu_dbg = 155U, /**< Cortex-A7 APB CPU Debug */
1148 kXRDC_PeriphA7_apb_pmu = 156U, /**< Cortex-A7 APB Performance Monitoring Unit */
1149 kXRDC_PeriphA7_apb_cti = 157U, /**< Cortex-A7 APB Cross Trigger Interface */
1150 kXRDC_PeriphA7_apb_etm = 158U, /**< Cortex-A7 APB Embedded Trace Module */
1151 kXRDC_PeriphEwm = 160U, /**< External Watchdog Monitor */
1152 kXRDC_PeriphPmc0 = 161U, /**< Power Management Controller 0 */
1153 kXRDC_PeriphSim = 163U, /**< System Integration Module */
1154 kXRDC_PeriphCmc0 = 164U, /**< Core Mode Controller 0 */
1155 kXRDC_PeriphQspi = 165U, /**< Quad Serial Peripheral Interface And Onthe-fly AES Decryptor */
1156 kXRDC_PeriphOcotp_ctrl = 166U, /**< On-chip One Time Programmable Controller */
1157 kXRDC_PeriphTpm2 = 168U, /**< Timer/PWM Module 2 */
1158 kXRDC_PeriphTpm3 = 169U, /**< Timer/PWM Module 3 */
1159 kXRDC_PeriphSai1 = 170U, /**< Synchronous Audio Interface 1 */
1160 kXRDC_PeriphLpuart2 = 171U, /**< Low Power Universal Asynchronous Receiver/Transmitter 2 */
1161 kXRDC_PeriphLpuart3 = 172U, /**< Low Power Universal Asynchronous Receiver/Transmitter 3 */
1162 kXRDC_PeriphAdc1 = 173U, /**< Analog to Digital Converter 1 */
1163 kXRDC_PeriphPcc1 = 178U, /**< Peripheral Clock Control 1 */
1164 kXRDC_PeriphEdma1 = 264U, /**< Direct Memory Access Controller 1 */
1165 kXRDC_PeriphEdma1_tcd = 265U, /**< Direct Memory Access Controller 1 Transfer */
1166 kXRDC_PeriphRgpio1 = 271U, /**< Rapid GPIO Controller 1 */
1167 kXRDC_PeriphFlexbus = 272U, /**< External Bus Interface */
1168 kXRDC_PeriphSema42_1 = 283U, /**< Hardware Semaphore Module 1 */
1169 kXRDC_PeriphDmamux1 = 289U, /**< Direct Memory Access Multiplexer 1 */
1170 kXRDC_PeriphMu_B = 290U, /**< Messaging Unit - Side B */
1171 kXRDC_PeriphCaam = 292U, /**< Cryptographic Acceleration and Assurance Module */
1172 kXRDC_PeriphTpm4 = 293U, /**< Timer/PWM Module 4 */
1173 kXRDC_PeriphTpm5 = 294U, /**< Timer/PWM Module 5 */
1174 kXRDC_PeriphLpit1 = 295U, /**< Low Power Periodic Interrupt Timer 1 */
1175 kXRDC_PeriphLpspi2 = 297U, /**< Low Power Serial Peripheral Interface 2 */
1176 kXRDC_PeriphLpspi3 = 298U, /**< Low Power Serial Peripheral Interface 3 */
1177 kXRDC_PeriphLpi2c4 = 299U, /**< Low Power Inter-Integrated Circuit 4 */
1178 kXRDC_PeriphLpi2c5 = 300U, /**< Low Power Inter-Integrated Circuit 5 */
1179 kXRDC_PeriphLpuart4 = 301U, /**< Low Power Universal Asynchronous Receiver/Transmitter 4 */
1180 kXRDC_PeriphLpuart5 = 302U, /**< Low Power Universal Asynchronous Receiver/Transmitter 5 */
1181 kXRDC_PeriphFlexio1 = 305U, /**< Flexible Input/Ouput 1 */
1182 kXRDC_PeriphUsb0 = 307U, /**< High Speed On-The-Go USB 1 */
1183 kXRDC_PeriphUsb1 = 308U, /**< High Speed On-The-Go USB 2 */
1184 kXRDC_PeriphUsbPhy = 309U, /**< USB-PHY Control */
1185 kXRDC_PeriphUsb_pl301 = 310U, /**< USB PL301 */
1186 kXRDC_PeriphUsdhc0 = 311U, /**< ultra Secure Digital Host Controller 0 */
1187 kXRDC_PeriphUsdhc1 = 312U, /**< ultra Secure Digital Host Controller 1 */
1188 kXRDC_PeriphTrgmux1 = 314U, /**< Trigger Multiplexer 1 */
1189 kXRDC_PeriphWdog1 = 317U, /**< Watchdog 1 */
1190 kXRDC_PeriphScg1 = 318U, /**< System Clock Generator 1 */
1191 kXRDC_PeriphPcc2 = 319U, /**< Peripheral Clock Control 2 */
1192 kXRDC_PeriphPmc1 = 320U, /**< Power Management Control 1 */
1193 kXRDC_PeriphCmc1 = 321U, /**< Core Mode Controller 1 */
1194 kXRDC_PeriphWdog2 = 323U, /**< Watchdog2 */
1195 kXRDC_PeriphRomc1 = 400U, /**< ROM Controller 1 */
1196 kXRDC_PeriphTpm6 = 417U, /**< Timer/PWM Module 6 */
1197 kXRDC_PeriphTpm7 = 418U, /**< Timer/PWM Module 7 */
1198 kXRDC_PeriphLpi2c6 = 420U, /**< Low Power I2C 6 */
1199 kXRDC_PeriphLpi2c7 = 421U, /**< Low Power I2C 7 */
1200 kXRDC_PeriphLpuart6 = 422U, /**< Low Power UART 6 */
1201 kXRDC_PeriphLpuart7 = 423U, /**< Low Power UART 7 */
1202 kXRDC_PeriphViu = 424U, /**< Video-In Unit */
1203 kXRDC_PeriphDsi = 425U, /**< MIPI Display Serial Interface */
1204 kXRDC_PeriphLcdif = 426U, /**< LCD Interface */
1205 kXRDC_PeriphMmdc = 427U, /**< Multi Mode DDR Controller */
1206 kXRDC_PeriphIomuxc1 = 428U, /**< Input/Output Multiplexing Control 1 */
1207 kXRDC_PeriphIomuxc_ddr = 429U, /**< Input/Output Multiplexing Control DDR */
1208 kXRDC_PeriphPctlC = 430U, /**< Port Interupt Control C */
1209 kXRDC_PeriphPctlD = 431U, /**< Port Interupt Control D */
1210 kXRDC_PeriphPctlE = 432U, /**< Port Interupt Control E */
1211 kXRDC_PeriphPctlF = 433U, /**< Port Interupt Control F */
1212 kXRDC_PeriphPcc3 = 435U, /**< Peripheral Clock Control 3 */
1213} xrdc_periph_t;
1214
1215
1216/*!
1217 * @}
1218 */ /* end of group Mapping_Information */
1219
1220
1221/* ----------------------------------------------------------------------------
1222 -- Device Peripheral Access Layer
1223 ---------------------------------------------------------------------------- */
1224
1225/*!
1226 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
1227 * @{
1228 */
1229
1230
1231/*
1232** Start of section using anonymous unions
1233*/
1234
1235#if defined(__ARMCC_VERSION)
1236 #if (__ARMCC_VERSION >= 6010050)
1237 #pragma clang diagnostic push
1238 #else
1239 #pragma push
1240 #pragma anon_unions
1241 #endif
1242#elif defined(__GNUC__)
1243 /* anonymous unions are enabled by default */
1244#elif defined(__IAR_SYSTEMS_ICC__)
1245 #pragma language=extended
1246#else
1247 #error Not supported compiler type
1248#endif
1249
1250/* ----------------------------------------------------------------------------
1251 -- ADC Peripheral Access Layer
1252 ---------------------------------------------------------------------------- */
1253
1254/*!
1255 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
1256 * @{
1257 */
1258
1259/** ADC - Register Layout Typedef */
1260typedef struct {
1261 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
1262 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
1263 uint8_t RESERVED_0[8];
1264 __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */
1265 __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */
1266 __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */
1267 __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */
1268 __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */
1269 __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */
1270 uint8_t RESERVED_1[8];
1271 __IO uint32_t FCTRL; /**< ADC FIFO Control Register, offset: 0x30 */
1272 __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
1273 uint8_t RESERVED_2[136];
1274 __IO uint32_t TCTRL[2]; /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */
1275 uint8_t RESERVED_3[56];
1276 struct { /* offset: 0x100, array step: 0x8 */
1277 __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
1278 __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
1279 } CMD[15];
1280 uint8_t RESERVED_4[136];
1281 __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
1282 uint8_t RESERVED_5[240];
1283 __I uint32_t RESFIFO; /**< ADC Data Result FIFO Register, offset: 0x300 */
1284} ADC_Type;
1285
1286/* ----------------------------------------------------------------------------
1287 -- ADC Register Masks
1288 ---------------------------------------------------------------------------- */
1289
1290/*!
1291 * @addtogroup ADC_Register_Masks ADC Register Masks
1292 * @{
1293 */
1294
1295/*! @name VERID - Version ID Register */
1296/*! @{ */
1297#define ADC_VERID_RES_MASK (0x1U)
1298#define ADC_VERID_RES_SHIFT (0U)
1299/*! RES - Resolution
1300 * 0b0..Up to 13-bit differential/12-bit single ended resolution supported.
1301 * 0b1..Up to 16-bit differential/15-bit single ended resolution supported.
1302 */
1303#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
1304#define ADC_VERID_DIFFEN_MASK (0x2U)
1305#define ADC_VERID_DIFFEN_SHIFT (1U)
1306/*! DIFFEN - Differential Supported
1307 * 0b0..Differential operation not supported.
1308 * 0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
1309 */
1310#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
1311#define ADC_VERID_MVI_MASK (0x8U)
1312#define ADC_VERID_MVI_SHIFT (3U)
1313/*! MVI - Multi Vref Implemented
1314 * 0b0..Single voltage reference high (VREFH) input supported.
1315 * 0b1..Multiple voltage reference high (VREFH) inputs supported.
1316 */
1317#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
1318#define ADC_VERID_CSW_MASK (0x70U)
1319#define ADC_VERID_CSW_SHIFT (4U)
1320/*! CSW - Channel Scale Width
1321 * 0b000..Channel scaling not supported.
1322 * 0b001..Channel scaling supported. 1-bit CSCALE control field.
1323 * 0b110..Channel scaling supported. 6-bit CSCALE control field.
1324 */
1325#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
1326#define ADC_VERID_VR1RNGI_MASK (0x100U)
1327#define ADC_VERID_VR1RNGI_SHIFT (8U)
1328/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
1329 * 0b0..Range control not required. CFG[VREF1RNG] is not implemented.
1330 * 0b1..Range control required. CFG[VREF1RNG] is implemented.
1331 */
1332#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
1333#define ADC_VERID_IADCKI_MASK (0x200U)
1334#define ADC_VERID_IADCKI_SHIFT (9U)
1335/*! IADCKI - Internal ADC Clock implemented
1336 * 0b0..Internal clock source not implemented.
1337 * 0b1..Internal clock source (and CFG[ADCKEN]) implemented.
1338 */
1339#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
1340#define ADC_VERID_CALOFSI_MASK (0x400U)
1341#define ADC_VERID_CALOFSI_SHIFT (10U)
1342/*! CALOFSI - Calibration Offset Function Implemented
1343 * 0b0..Offset calibration and offset trimming not implemented.
1344 * 0b1..Offset calibration and offset trimming implemented.
1345 */
1346#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
1347#define ADC_VERID_MINOR_MASK (0xFF0000U)
1348#define ADC_VERID_MINOR_SHIFT (16U)
1349/*! MINOR - Minor Version Number
1350 */
1351#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
1352#define ADC_VERID_MAJOR_MASK (0xFF000000U)
1353#define ADC_VERID_MAJOR_SHIFT (24U)
1354/*! MAJOR - Major Version Number
1355 */
1356#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
1357/*! @} */
1358
1359/*! @name PARAM - Parameter Register */
1360/*! @{ */
1361#define ADC_PARAM_TRIG_NUM_MASK (0xFFU)
1362#define ADC_PARAM_TRIG_NUM_SHIFT (0U)
1363/*! TRIG_NUM - Trigger Number
1364 */
1365#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
1366#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U)
1367#define ADC_PARAM_FIFOSIZE_SHIFT (8U)
1368/*! FIFOSIZE - Result FIFO Depth
1369 * 0b00000001..Result FIFO depth = 1 dataword.
1370 * 0b00000100..Result FIFO depth = 4 datawords.
1371 * 0b00001000..Result FIFO depth = 8 datawords.
1372 * 0b00010000..Result FIFO depth = 16 datawords.
1373 * 0b00100000..Result FIFO depth = 32 datawords.
1374 * 0b01000000..Result FIFO depth = 64 datawords.
1375 */
1376#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
1377#define ADC_PARAM_CV_NUM_MASK (0xFF0000U)
1378#define ADC_PARAM_CV_NUM_SHIFT (16U)
1379/*! CV_NUM - Compare Value Number
1380 */
1381#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
1382#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U)
1383#define ADC_PARAM_CMD_NUM_SHIFT (24U)
1384/*! CMD_NUM - Command Buffer Number
1385 */
1386#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
1387/*! @} */
1388
1389/*! @name CTRL - ADC Control Register */
1390/*! @{ */
1391#define ADC_CTRL_ADCEN_MASK (0x1U)
1392#define ADC_CTRL_ADCEN_SHIFT (0U)
1393/*! ADCEN - ADC Enable
1394 * 0b0..ADC is disabled.
1395 * 0b1..ADC is enabled.
1396 */
1397#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
1398#define ADC_CTRL_RST_MASK (0x2U)
1399#define ADC_CTRL_RST_SHIFT (1U)
1400/*! RST - Software Reset
1401 * 0b0..ADC logic is not reset.
1402 * 0b1..ADC logic is reset.
1403 */
1404#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
1405#define ADC_CTRL_DOZEN_MASK (0x4U)
1406#define ADC_CTRL_DOZEN_SHIFT (2U)
1407/*! DOZEN - Doze Enable
1408 * 0b0..ADC is enabled in Doze mode.
1409 * 0b1..ADC is disabled in Doze mode.
1410 */
1411#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
1412#define ADC_CTRL_RSTFIFO_MASK (0x100U)
1413#define ADC_CTRL_RSTFIFO_SHIFT (8U)
1414/*! RSTFIFO - Reset FIFO
1415 * 0b0..No effect.
1416 * 0b1..FIFO is reset.
1417 */
1418#define ADC_CTRL_RSTFIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)
1419/*! @} */
1420
1421/*! @name STAT - ADC Status Register */
1422/*! @{ */
1423#define ADC_STAT_RDY_MASK (0x1U)
1424#define ADC_STAT_RDY_SHIFT (0U)
1425/*! RDY - Result FIFO Ready Flag
1426 * 0b0..Result FIFO data level not above watermark level.
1427 * 0b1..Result FIFO holding data above watermark level.
1428 */
1429#define ADC_STAT_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
1430#define ADC_STAT_FOF_MASK (0x2U)
1431#define ADC_STAT_FOF_SHIFT (1U)
1432/*! FOF - Result FIFO Overflow Flag
1433 * 0b0..No result FIFO overflow has occurred since the last time the flag was cleared.
1434 * 0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared.
1435 */
1436#define ADC_STAT_FOF(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
1437#define ADC_STAT_ADC_ACTIVE_MASK (0x100U)
1438#define ADC_STAT_ADC_ACTIVE_SHIFT (8U)
1439/*! ADC_ACTIVE - ADC Active
1440 * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
1441 * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
1442 */
1443#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
1444#define ADC_STAT_TRGACT_MASK (0x10000U)
1445#define ADC_STAT_TRGACT_SHIFT (16U)
1446/*! TRGACT - Trigger Active
1447 * 0b0..Command (sequence) associated with Trigger 0 currently being executed.
1448 * 0b1..Command (sequence) associated with Trigger 1 currently being executed.
1449 */
1450#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
1451#define ADC_STAT_CMDACT_MASK (0xF000000U)
1452#define ADC_STAT_CMDACT_SHIFT (24U)
1453/*! CMDACT - Command Active
1454 * 0b0000..No command is currently in progress.
1455 * 0b0001..Command 1 currently being executed.
1456 * 0b0010..Command 2 currently being executed.
1457 * 0b0011-0b1111..Associated command number is currently being executed.
1458 */
1459#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
1460/*! @} */
1461
1462/*! @name IE - Interrupt Enable Register */
1463/*! @{ */
1464#define ADC_IE_FWMIE_MASK (0x1U)
1465#define ADC_IE_FWMIE_SHIFT (0U)
1466/*! FWMIE - FIFO Watermark Interrupt Enable
1467 * 0b0..FIFO watermark interrupts are not enabled.
1468 * 0b1..FIFO watermark interrupts are enabled.
1469 */
1470#define ADC_IE_FWMIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
1471#define ADC_IE_FOFIE_MASK (0x2U)
1472#define ADC_IE_FOFIE_SHIFT (1U)
1473/*! FOFIE - Result FIFO Overflow Interrupt Enable
1474 * 0b0..FIFO overflow interrupts are not enabled.
1475 * 0b1..FIFO overflow interrupts are enabled.
1476 */
1477#define ADC_IE_FOFIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)
1478/*! @} */
1479
1480/*! @name DE - DMA Enable Register */
1481/*! @{ */
1482#define ADC_DE_FWMDE_MASK (0x1U)
1483#define ADC_DE_FWMDE_SHIFT (0U)
1484/*! FWMDE - FIFO Watermark DMA Enable
1485 * 0b0..DMA request disabled.
1486 * 0b1..DMA request enabled.
1487 */
1488#define ADC_DE_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)
1489/*! @} */
1490
1491/*! @name CFG - ADC Configuration Register */
1492/*! @{ */
1493#define ADC_CFG_TPRICTRL_MASK (0x1U)
1494#define ADC_CFG_TPRICTRL_SHIFT (0U)
1495/*! TPRICTRL - ADC trigger priority control
1496 * 0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and
1497 * the new command specified by the trigger is started.
1498 * 0b1..If a higher priority trigger is received during command processing, the current conversion is completed
1499 * (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority
1500 * trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true
1501 * conversion.
1502 */
1503#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
1504#define ADC_CFG_PWRSEL_MASK (0x30U)
1505#define ADC_CFG_PWRSEL_SHIFT (4U)
1506/*! PWRSEL - Power Configuration Select
1507 * 0b00..Level 1 (Lowest power setting)
1508 * 0b01..Level 2
1509 * 0b10..Level 3
1510 * 0b11..Level 4 (Highest power setting)
1511 */
1512#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
1513#define ADC_CFG_REFSEL_MASK (0xC0U)
1514#define ADC_CFG_REFSEL_SHIFT (6U)
1515/*! REFSEL - Voltage Reference Selection
1516 * 0b00..(Default) Option 1 setting.
1517 * 0b01..Option 2 setting.
1518 * 0b10..Option 3 setting.
1519 * 0b11..Reserved
1520 */
1521#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
1522#define ADC_CFG_PUDLY_MASK (0xFF0000U)
1523#define ADC_CFG_PUDLY_SHIFT (16U)
1524/*! PUDLY - Power Up Delay
1525 */
1526#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
1527#define ADC_CFG_PWREN_MASK (0x10000000U)
1528#define ADC_CFG_PWREN_SHIFT (28U)
1529/*! PWREN - ADC Analog Pre-Enable
1530 * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
1531 * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
1532 * of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any
1533 * detected trigger does not begin ADC operation until the power up delay time has passed.
1534 */
1535#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
1536/*! @} */
1537
1538/*! @name PAUSE - ADC Pause Register */
1539/*! @{ */
1540#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU)
1541#define ADC_PAUSE_PAUSEDLY_SHIFT (0U)
1542/*! PAUSEDLY - Pause Delay
1543 */
1544#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
1545#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U)
1546#define ADC_PAUSE_PAUSEEN_SHIFT (31U)
1547/*! PAUSEEN - PAUSE Option Enable
1548 * 0b0..Pause operation disabled
1549 * 0b1..Pause operation enabled
1550 */
1551#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
1552/*! @} */
1553
1554/*! @name FCTRL - ADC FIFO Control Register */
1555/*! @{ */
1556#define ADC_FCTRL_FCOUNT_MASK (0x1FU)
1557#define ADC_FCTRL_FCOUNT_SHIFT (0U)
1558/*! FCOUNT - Result FIFO counter
1559 */
1560#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
1561#define ADC_FCTRL_FWMARK_MASK (0xF0000U)
1562#define ADC_FCTRL_FWMARK_SHIFT (16U)
1563/*! FWMARK - Watermark level selection
1564 */
1565#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
1566/*! @} */
1567
1568/*! @name SWTRIG - Software Trigger Register */
1569/*! @{ */
1570#define ADC_SWTRIG_SWT0_MASK (0x1U)
1571#define ADC_SWTRIG_SWT0_SHIFT (0U)
1572/*! SWT0 - Software trigger 0 event
1573 * 0b0..No trigger 0 event generated.
1574 * 0b1..Trigger 0 event generated.
1575 */
1576#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
1577#define ADC_SWTRIG_SWT1_MASK (0x2U)
1578#define ADC_SWTRIG_SWT1_SHIFT (1U)
1579/*! SWT1 - Software trigger 1 event
1580 * 0b0..No trigger 1 event generated.
1581 * 0b1..Trigger 1 event generated.
1582 */
1583#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
1584/*! @} */
1585
1586/*! @name TCTRL - Trigger Control Register */
1587/*! @{ */
1588#define ADC_TCTRL_HTEN_MASK (0x1U)
1589#define ADC_TCTRL_HTEN_SHIFT (0U)
1590/*! HTEN - Trigger enable
1591 * 0b0..Hardware trigger source disabled
1592 * 0b1..Hardware trigger source enabled
1593 */
1594#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
1595#define ADC_TCTRL_TPRI_MASK (0x100U)
1596#define ADC_TCTRL_TPRI_SHIFT (8U)
1597/*! TPRI - Trigger priority setting
1598 * 0b0..Set to highest priority, Level 1
1599 * 0b1..Set to lower priority, Level 2
1600 */
1601#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
1602#define ADC_TCTRL_TDLY_MASK (0xF0000U)
1603#define ADC_TCTRL_TDLY_SHIFT (16U)
1604/*! TDLY - Trigger delay select
1605 */
1606#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
1607#define ADC_TCTRL_TCMD_MASK (0xF000000U)
1608#define ADC_TCTRL_TCMD_SHIFT (24U)
1609/*! TCMD - Trigger command select
1610 * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
1611 * 0b0001..CMD1 is executed
1612 * 0b0010-0b1110..Corresponding CMD is executed
1613 * 0b1111..CMD15 is executed
1614 */
1615#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
1616/*! @} */
1617
1618/* The count of ADC_TCTRL */
1619#define ADC_TCTRL_COUNT (2U)
1620
1621/*! @name CMDL - ADC Command Low Buffer Register */
1622/*! @{ */
1623#define ADC_CMDL_ADCH_MASK (0x1FU)
1624#define ADC_CMDL_ADCH_SHIFT (0U)
1625/*! ADCH - Input channel select
1626 * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
1627 * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
1628 * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
1629 * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
1630 * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
1631 * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
1632 * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
1633 */
1634#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
1635#define ADC_CMDL_ABSEL_MASK (0x20U)
1636#define ADC_CMDL_ABSEL_SHIFT (5U)
1637/*! ABSEL - A-side vs. B-side Select
1638 * 0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB).
1639 * 0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA).
1640 */
1641#define ADC_CMDL_ABSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
1642#define ADC_CMDL_DIFF_MASK (0x40U)
1643#define ADC_CMDL_DIFF_SHIFT (6U)
1644/*! DIFF - Differential Mode Enable
1645 * 0b0..Single-ended mode.
1646 * 0b1..Differential mode.
1647 */
1648#define ADC_CMDL_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)
1649#define ADC_CMDL_CSCALE_MASK (0x2000U)
1650#define ADC_CMDL_CSCALE_SHIFT (13U)
1651/*! CSCALE - Channel Scale
1652 * 0b0..Scale selected analog channel (Factor of 30/64)
1653 * 0b1..(Default) Full scale (Factor of 1)
1654 */
1655#define ADC_CMDL_CSCALE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)
1656/*! @} */
1657
1658/* The count of ADC_CMDL */
1659#define ADC_CMDL_COUNT (15U)
1660
1661/*! @name CMDH - ADC Command High Buffer Register */
1662/*! @{ */
1663#define ADC_CMDH_CMPEN_MASK (0x3U)
1664#define ADC_CMDH_CMPEN_SHIFT (0U)
1665/*! CMPEN - Compare Function Enable
1666 * 0b00..Compare disabled.
1667 * 0b01..Reserved
1668 * 0b10..Compare enabled. Store on true.
1669 * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
1670 */
1671#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
1672#define ADC_CMDH_LWI_MASK (0x80U)
1673#define ADC_CMDH_LWI_SHIFT (7U)
1674/*! LWI - Loop with Increment
1675 * 0b0..Auto channel increment disabled
1676 * 0b1..Auto channel increment enabled
1677 */
1678#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
1679#define ADC_CMDH_STS_MASK (0x700U)
1680#define ADC_CMDH_STS_SHIFT (8U)
1681/*! STS - Sample Time Select
1682 * 0b000..Minimum sample time of 3 ADCK cycles.
1683 * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
1684 * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
1685 * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
1686 * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
1687 * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
1688 * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
1689 * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
1690 */
1691#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
1692#define ADC_CMDH_AVGS_MASK (0x7000U)
1693#define ADC_CMDH_AVGS_SHIFT (12U)
1694/*! AVGS - Hardware Average Select
1695 * 0b000..Single conversion.
1696 * 0b001..2 conversions averaged.
1697 * 0b010..4 conversions averaged.
1698 * 0b011..8 conversions averaged.
1699 * 0b100..16 conversions averaged.
1700 * 0b101..32 conversions averaged.
1701 * 0b110..64 conversions averaged.
1702 * 0b111..128 conversions averaged.
1703 */
1704#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
1705#define ADC_CMDH_LOOP_MASK (0xF0000U)
1706#define ADC_CMDH_LOOP_SHIFT (16U)
1707/*! LOOP - Loop Count Select
1708 * 0b0000..Looping not enabled. Command executes 1 time.
1709 * 0b0001..Loop 1 time. Command executes 2 times.
1710 * 0b0010..Loop 2 times. Command executes 3 times.
1711 * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
1712 * 0b1111..Loop 15 times. Command executes 16 times.
1713 */
1714#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
1715#define ADC_CMDH_NEXT_MASK (0xF000000U)
1716#define ADC_CMDH_NEXT_SHIFT (24U)
1717/*! NEXT - Next Command Select
1718 * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
1719 * trigger pending, begin command associated with lower priority trigger.
1720 * 0b0001..Select CMD1 command buffer register as next command.
1721 * 0b0010-0b1110..Select corresponding CMD command buffer register as next command
1722 * 0b1111..Select CMD15 command buffer register as next command.
1723 */
1724#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
1725/*! @} */
1726
1727/* The count of ADC_CMDH */
1728#define ADC_CMDH_COUNT (15U)
1729
1730/*! @name CV - Compare Value Register */
1731/*! @{ */
1732#define ADC_CV_CVL_MASK (0xFFFFU)
1733#define ADC_CV_CVL_SHIFT (0U)
1734/*! CVL - Compare Value Low.
1735 */
1736#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
1737#define ADC_CV_CVH_MASK (0xFFFF0000U)
1738#define ADC_CV_CVH_SHIFT (16U)
1739/*! CVH - Compare Value High.
1740 */
1741#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
1742/*! @} */
1743
1744/* The count of ADC_CV */
1745#define ADC_CV_COUNT (4U)
1746
1747/*! @name RESFIFO - ADC Data Result FIFO Register */
1748/*! @{ */
1749#define ADC_RESFIFO_D_MASK (0xFFFFU)
1750#define ADC_RESFIFO_D_SHIFT (0U)
1751/*! D - Data result
1752 */
1753#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
1754#define ADC_RESFIFO_TSRC_MASK (0x10000U)
1755#define ADC_RESFIFO_TSRC_SHIFT (16U)
1756/*! TSRC - Trigger Source
1757 * 0b0..Trigger source 0 initiated this conversion.
1758 * 0b1..Trigger source 1 initiated this conversion.
1759 */
1760#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
1761#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U)
1762#define ADC_RESFIFO_LOOPCNT_SHIFT (20U)
1763/*! LOOPCNT - Loop count value
1764 * 0b0000..Result is from initial conversion in command.
1765 * 0b0001..Result is from second conversion in command.
1766 * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
1767 * 0b1111..Result is from 16th conversion in command.
1768 */
1769#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
1770#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U)
1771#define ADC_RESFIFO_CMDSRC_SHIFT (24U)
1772/*! CMDSRC - Command Buffer Source
1773 * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
1774 * prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
1775 * 0b0001..CMD1 buffer used as control settings for this conversion.
1776 * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
1777 * 0b1111..CMD15 buffer used as control settings for this conversion.
1778 */
1779#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
1780#define ADC_RESFIFO_VALID_MASK (0x80000000U)
1781#define ADC_RESFIFO_VALID_SHIFT (31U)
1782/*! VALID - FIFO entry is valid
1783 * 0b0..FIFO is empty. Discard any read from RESFIFO.
1784 * 0b1..FIFO record read from RESFIFO is valid.
1785 */
1786#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
1787/*! @} */
1788
1789
1790/*!
1791 * @}
1792 */ /* end of group ADC_Register_Masks */
1793
1794
1795/* ADC - Peripheral instance base addresses */
1796/** Peripheral ADC0 base address */
1797#define ADC0_BASE (0x41041000u)
1798/** Peripheral ADC0 base pointer */
1799#define ADC0 ((ADC_Type *)ADC0_BASE)
1800/** Peripheral ADC1 base address */
1801#define ADC1_BASE (0x410AD000u)
1802/** Peripheral ADC1 base pointer */
1803#define ADC1 ((ADC_Type *)ADC1_BASE)
1804/** Array initializer of ADC peripheral base addresses */
1805#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
1806/** Array initializer of ADC peripheral base pointers */
1807#define ADC_BASE_PTRS { ADC0, ADC1 }
1808/** Interrupt vectors for the ADC peripheral type */
1809#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
1810
1811/*!
1812 * @}
1813 */ /* end of group ADC_Peripheral_Access_Layer */
1814
1815
1816/* ----------------------------------------------------------------------------
1817 -- CMP Peripheral Access Layer
1818 ---------------------------------------------------------------------------- */
1819
1820/*!
1821 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
1822 * @{
1823 */
1824
1825/** CMP - Register Layout Typedef */
1826typedef struct {
1827 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
1828 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
1829 __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x8 */
1830 __IO uint32_t C1; /**< CMP Control Register 1, offset: 0xC */
1831 __IO uint32_t C2; /**< CMP Control Register 2, offset: 0x10 */
1832 __IO uint32_t C3; /**< CMP Control Register 3, offset: 0x14 */
1833} CMP_Type;
1834
1835/* ----------------------------------------------------------------------------
1836 -- CMP Register Masks
1837 ---------------------------------------------------------------------------- */
1838
1839/*!
1840 * @addtogroup CMP_Register_Masks CMP Register Masks
1841 * @{
1842 */
1843
1844/*! @name VERID - Version ID Register */
1845/*! @{ */
1846#define CMP_VERID_FEATURE_MASK (0xFFFFU)
1847#define CMP_VERID_FEATURE_SHIFT (0U)
1848/*! FEATURE - Feature Specification Number. This read only filed returns the feature set number.
1849 */
1850#define CMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK)
1851#define CMP_VERID_MINOR_MASK (0xFF0000U)
1852#define CMP_VERID_MINOR_SHIFT (16U)
1853/*! MINOR - Minor Version Number. This read only field returns the minor version number for the module specification.
1854 */
1855#define CMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK)
1856#define CMP_VERID_MAJOR_MASK (0xFF000000U)
1857#define CMP_VERID_MAJOR_SHIFT (24U)
1858/*! MAJOR - Major Version Number. This read only field returns the major version number for the module specification.
1859 */
1860#define CMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK)
1861/*! @} */
1862
1863/*! @name PARAM - Parameter Register */
1864/*! @{ */
1865#define CMP_PARAM_PARAM_MASK (0xFFFFFFFFU)
1866#define CMP_PARAM_PARAM_SHIFT (0U)
1867/*! PARAM - Parameter Registers. This read only filed returns the feature parameters implemented along with the Version ID register.
1868 */
1869#define CMP_PARAM_PARAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK)
1870/*! @} */
1871
1872/*! @name C0 - CMP Control Register 0 */
1873/*! @{ */
1874#define CMP_C0_HYSTCTR_MASK (0x3U)
1875#define CMP_C0_HYSTCTR_SHIFT (0U)
1876/*! HYSTCTR - Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level
1877 * 0b00..The hard block output has level 0 hysteresis internally.
1878 * 0b01..The hard block output has level 1 hysteresis internally.
1879 * 0b10..The hard block output has level 2 hysteresis internally.
1880 * 0b11..The hard block output has level 3 hysteresis internally.
1881 */
1882#define CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK)
1883#define CMP_C0_FILTER_CNT_MASK (0x70U)
1884#define CMP_C0_FILTER_CNT_SHIFT (4U)
1885/*! FILTER_CNT - Filter Sample Count
1886 * 0b000..Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA.
1887 * 0b001..1 consecutive sample must agree (comparator output is simply sampled).
1888 * 0b010..2 consecutive samples must agree.
1889 * 0b011..3 consecutive samples must agree.
1890 * 0b100..4 consecutive samples must agree.
1891 * 0b101..5 consecutive samples must agree.
1892 * 0b110..6 consecutive samples must agree.
1893 * 0b111..7 consecutive samples must agree.
1894 */
1895#define CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK)
1896#define CMP_C0_EN_MASK (0x100U)
1897#define CMP_C0_EN_SHIFT (8U)
1898/*! EN - Comparator Module Enable
1899 * 0b0..Analog Comparator is disabled.
1900 * 0b1..Analog Comparator is enabled.
1901 */
1902#define CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK)
1903#define CMP_C0_OPE_MASK (0x200U)
1904#define CMP_C0_OPE_SHIFT (9U)
1905/*! OPE - Comparator Output Pin Enable
1906 * 0b0..When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin.
1907 * 0b1..When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin.
1908 */
1909#define CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK)
1910#define CMP_C0_COS_MASK (0x400U)
1911#define CMP_C0_COS_SHIFT (10U)
1912/*! COS - Comparator Output Select
1913 * 0b0..Set CMPO to equal COUT (filtered comparator output).
1914 * 0b1..Set CMPO to equal COUTA (unfiltered comparator output).
1915 */
1916#define CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK)
1917#define CMP_C0_INVT_MASK (0x800U)
1918#define CMP_C0_INVT_SHIFT (11U)
1919/*! INVT - Comparator invert
1920 * 0b0..Does not invert the comparator output.
1921 * 0b1..Inverts the comparator output.
1922 */
1923#define CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK)
1924#define CMP_C0_PMODE_MASK (0x1000U)
1925#define CMP_C0_PMODE_SHIFT (12U)
1926/*! PMODE - Power Mode Select
1927 * 0b0..Low Speed (LS) comparison mode is selected.
1928 * 0b1..High Speed (HS) comparison mode is selected.
1929 */
1930#define CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK)
1931#define CMP_C0_WE_MASK (0x4000U)
1932#define CMP_C0_WE_SHIFT (14U)
1933/*! WE - Windowing Enable
1934 * 0b0..Windowing mode is not selected.
1935 * 0b1..Windowing mode is selected.
1936 */
1937#define CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK)
1938#define CMP_C0_SE_MASK (0x8000U)
1939#define CMP_C0_SE_SHIFT (15U)
1940/*! SE - Sample Enable
1941 * 0b0..Sampling mode is not selected.
1942 * 0b1..Sampling mode is selected.
1943 */
1944#define CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK)
1945#define CMP_C0_FPR_MASK (0xFF0000U)
1946#define CMP_C0_FPR_SHIFT (16U)
1947/*! FPR - Filter Sample Period
1948 */
1949#define CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK)
1950#define CMP_C0_COUT_MASK (0x1000000U)
1951#define CMP_C0_COUT_SHIFT (24U)
1952/*! COUT - Analog Comparator Output
1953 */
1954#define CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK)
1955#define CMP_C0_CFF_MASK (0x2000000U)
1956#define CMP_C0_CFF_SHIFT (25U)
1957/*! CFF - Analog Comparator Flag Falling
1958 * 0b0..A falling edge has not been detected on COUT.
1959 * 0b1..A falling edge on COUT has occurred.
1960 */
1961#define CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK)
1962#define CMP_C0_CFR_MASK (0x4000000U)
1963#define CMP_C0_CFR_SHIFT (26U)
1964/*! CFR - Analog Comparator Flag Rising
1965 * 0b0..A rising edge has not been detected on COUT.
1966 * 0b1..A rising edge on COUT has occurred.
1967 */
1968#define CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
1969#define CMP_C0_IEF_MASK (0x8000000U)
1970#define CMP_C0_IEF_SHIFT (27U)
1971/*! IEF - Comparator Interrupt Enable Falling
1972 * 0b0..Interrupt is disabled.
1973 * 0b1..Interrupt is enabled.
1974 */
1975#define CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK)
1976#define CMP_C0_IER_MASK (0x10000000U)
1977#define CMP_C0_IER_SHIFT (28U)
1978/*! IER - Comparator Interrupt Enable Rising
1979 * 0b0..Interrupt is disabled.
1980 * 0b1..Interrupt is enabled.
1981 */
1982#define CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK)
1983#define CMP_C0_DMAEN_MASK (0x40000000U)
1984#define CMP_C0_DMAEN_SHIFT (30U)
1985/*! DMAEN - DMA Enable
1986 * 0b0..DMA is disabled.
1987 * 0b1..DMA is enabled.
1988 */
1989#define CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK)
1990#define CMP_C0_LINKEN_MASK (0x80000000U)
1991#define CMP_C0_LINKEN_SHIFT (31U)
1992/*! LINKEN - CMP to DAC link enable.
1993 * 0b0..CMP to DAC link is disabled
1994 * 0b1..CMP to DAC link is enabled.
1995 */
1996#define CMP_C0_LINKEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_LINKEN_SHIFT)) & CMP_C0_LINKEN_MASK)
1997/*! @} */
1998
1999/*! @name C1 - CMP Control Register 1 */
2000/*! @{ */
2001#define CMP_C1_VOSEL_MASK (0xFFU)
2002#define CMP_C1_VOSEL_SHIFT (0U)
2003/*! VOSEL - DAC Output Voltage Select
2004 */
2005#define CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK)
2006#define CMP_C1_DMODE_MASK (0x100U)
2007#define CMP_C1_DMODE_SHIFT (8U)
2008/*! DMODE - DAC Mode Selection
2009 * 0b0..DAC is selected to work in low speed and low power mode.
2010 * 0b1..DAC is selected to work in high speed high power mode.
2011 */
2012#define CMP_C1_DMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DMODE_SHIFT)) & CMP_C1_DMODE_MASK)
2013#define CMP_C1_VRSEL_MASK (0x200U)
2014#define CMP_C1_VRSEL_SHIFT (9U)
2015/*! VRSEL - Supply Voltage Reference Source Select
2016 * 0b0..Vin1 is selected as resistor ladder network supply reference Vin. Vin1 is from internal PMC.
2017 * 0b1..Vin2 is selected as resistor ladder network supply reference Vin. Vin2 is from PAD.
2018 */
2019#define CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK)
2020#define CMP_C1_DACEN_MASK (0x400U)
2021#define CMP_C1_DACEN_SHIFT (10U)
2022/*! DACEN - DAC Enable
2023 * 0b0..DAC is disabled.
2024 * 0b1..DAC is enabled.
2025 */
2026#define CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK)
2027#define CMP_C1_DACOE_MASK (0x800U)
2028#define CMP_C1_DACOE_SHIFT (11U)
2029/*! DACOE - DAC Output Enable
2030 * 0b0..DAC output is enabled
2031 * 0b1..DAC output is disabled
2032 */
2033#define CMP_C1_DACOE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACOE_SHIFT)) & CMP_C1_DACOE_MASK)
2034#define CMP_C1_CHN0_MASK (0x10000U)
2035#define CMP_C1_CHN0_SHIFT (16U)
2036/*! CHN0 - Channel 0 input enable
2037 */
2038#define CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK)
2039#define CMP_C1_CHN1_MASK (0x20000U)
2040#define CMP_C1_CHN1_SHIFT (17U)
2041/*! CHN1 - Channel 1 input enable
2042 */
2043#define CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK)
2044#define CMP_C1_CHN2_MASK (0x40000U)
2045#define CMP_C1_CHN2_SHIFT (18U)
2046/*! CHN2 - Channel 2 input enable
2047 */
2048#define CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK)
2049#define CMP_C1_CHN3_MASK (0x80000U)
2050#define CMP_C1_CHN3_SHIFT (19U)
2051/*! CHN3 - Channel 3 input enable
2052 */
2053#define CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK)
2054#define CMP_C1_CHN4_MASK (0x100000U)
2055#define CMP_C1_CHN4_SHIFT (20U)
2056/*! CHN4 - Channel 4 input enable
2057 */
2058#define CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK)
2059#define CMP_C1_CHN5_MASK (0x200000U)
2060#define CMP_C1_CHN5_SHIFT (21U)
2061/*! CHN5 - Channel 5 input enable
2062 */
2063#define CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK)
2064#define CMP_C1_MSEL_MASK (0x7000000U)
2065#define CMP_C1_MSEL_SHIFT (24U)
2066/*! MSEL - Minus Input MUX Control
2067 * 0b000..Internal Negative Input 0 for Minus Channel -- Internal Minus Input
2068 * 0b001..External Input 1 for Minus Channel -- Reference Input 0
2069 * 0b010..External Input 2 for Minus Channel -- Reference Input 1
2070 * 0b011..External Input 3 for Minus Channel -- Reference Input 2
2071 * 0b100..External Input 4 for Minus Channel -- Reference Input 3
2072 * 0b101..External Input 5 for Minus Channel -- Reference Input 4
2073 * 0b110..External Input 6 for Minus Channel -- Reference Input 5
2074 * 0b111..Internal 8b DAC output
2075 */
2076#define CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK)
2077#define CMP_C1_PSEL_MASK (0x70000000U)
2078#define CMP_C1_PSEL_SHIFT (28U)
2079/*! PSEL - Plus Input MUX Control
2080 * 0b000..Internal Positive Input 0 for Plus Channel -- Internal Plus Input
2081 * 0b001..External Input 1 for Plus Channel -- Reference Input 0
2082 * 0b010..External Input 2 for Plus Channel -- Reference Input 1
2083 * 0b011..External Input 3 for Plus Channel -- Reference Input 2
2084 * 0b100..External Input 4 for Plus Channel -- Reference Input 3
2085 * 0b101..External Input 5 for Plus Channel -- Reference Input 4
2086 * 0b110..External Input 6 for Plus Channel -- Reference Input 5
2087 * 0b111..Internal 8b DAC output
2088 */
2089#define CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK)
2090/*! @} */
2091
2092/*! @name C2 - CMP Control Register 2 */
2093/*! @{ */
2094#define CMP_C2_ACOn_MASK (0x3FU)
2095#define CMP_C2_ACOn_SHIFT (0U)
2096/*! ACOn - ACOn
2097 */
2098#define CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK)
2099#define CMP_C2_INITMOD_MASK (0x3F00U)
2100#define CMP_C2_INITMOD_SHIFT (8U)
2101/*! INITMOD - Comparator and DAC initialization delay modulus.
2102 */
2103#define CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK)
2104#define CMP_C2_NSAM_MASK (0xC000U)
2105#define CMP_C2_NSAM_SHIFT (14U)
2106/*! NSAM - Number of sample clocks
2107 * 0b00..The comparison result is sampled as soon as the active channel is scanned in one round-robin clock.
2108 * 0b01..The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock.
2109 * 0b10..The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock.
2110 * 0b11..The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock.
2111 */
2112#define CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK)
2113#define CMP_C2_CH0F_MASK (0x10000U)
2114#define CMP_C2_CH0F_SHIFT (16U)
2115/*! CH0F - CH0F
2116 */
2117#define CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK)
2118#define CMP_C2_CH1F_MASK (0x20000U)
2119#define CMP_C2_CH1F_SHIFT (17U)
2120/*! CH1F - CH1F
2121 */
2122#define CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK)
2123#define CMP_C2_CH2F_MASK (0x40000U)
2124#define CMP_C2_CH2F_SHIFT (18U)
2125/*! CH2F - CH2F
2126 */
2127#define CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK)
2128#define CMP_C2_CH3F_MASK (0x80000U)
2129#define CMP_C2_CH3F_SHIFT (19U)
2130/*! CH3F - CH3F
2131 */
2132#define CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK)
2133#define CMP_C2_CH4F_MASK (0x100000U)
2134#define CMP_C2_CH4F_SHIFT (20U)
2135/*! CH4F - CH4F
2136 */
2137#define CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK)
2138#define CMP_C2_CH5F_MASK (0x200000U)
2139#define CMP_C2_CH5F_SHIFT (21U)
2140/*! CH5F - CH5F
2141 */
2142#define CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK)
2143#define CMP_C2_FXMXCH_MASK (0xE000000U)
2144#define CMP_C2_FXMXCH_SHIFT (25U)
2145/*! FXMXCH - Fixed channel selection
2146 * 0b000..External Reference Input 0 is selected as the fixed reference input for the fixed mux port.
2147 * 0b001..External Reference Input 1 is selected as the fixed reference input for the fixed mux port.
2148 * 0b010..External Reference Input 2 is selected as the fixed reference input for the fixed mux port.
2149 * 0b011..External Reference Input 3 is selected as the fixed reference input for the fixed mux port.
2150 * 0b100..External Reference Input 4 is selected as the fixed reference input for the fixed mux port.
2151 * 0b101..External Reference Input 5 is selected as the fixed reference input for the fixed mux port.
2152 * 0b110..Reserved.
2153 * 0b111..The 8bit DAC is selected as the fixed reference input for the fixed mux port.
2154 */
2155#define CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK)
2156#define CMP_C2_FXMP_MASK (0x20000000U)
2157#define CMP_C2_FXMP_SHIFT (29U)
2158/*! FXMP - Fixed MUX Port
2159 * 0b0..The Plus port is fixed. Only the inputs to the Minus port are swept in each round.
2160 * 0b1..The Minus port is fixed. Only the inputs to the Plus port are swept in each round.
2161 */
2162#define CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK)
2163#define CMP_C2_RRIE_MASK (0x40000000U)
2164#define CMP_C2_RRIE_SHIFT (30U)
2165/*! RRIE - Round-Robin interrupt enable
2166 * 0b0..The round-robin interrupt is disabled.
2167 * 0b1..The round-robin interrupt is enabled when a comparison result changes from the last sample.
2168 */
2169#define CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK)
2170/*! @} */
2171
2172/*! @name C3 - CMP Control Register 3 */
2173/*! @{ */
2174#define CMP_C3_ACPH2TC_MASK (0x70U)
2175#define CMP_C3_ACPH2TC_SHIFT (4U)
2176/*! ACPH2TC - Analog Comparator Phase2 Timing Control.
2177 * 0b000..Phase2 active time in one sampling period equals to T
2178 * 0b001..Phase2 active time in one sampling period equals to 2*T
2179 * 0b010..Phase2 active time in one sampling period equals to 4*T
2180 * 0b011..Phase2 active time in one sampling period equals to 8*T
2181 * 0b100..Phase2 active time in one sampling period equals to 16*T
2182 * 0b101..Phase2 active time in one sampling period equals to 32*T
2183 * 0b110..Phase2 active time in one sampling period equals to 64*T
2184 * 0b111..Phase2 active time in one sampling period equals to 16*T
2185 */
2186#define CMP_C3_ACPH2TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH2TC_SHIFT)) & CMP_C3_ACPH2TC_MASK)
2187#define CMP_C3_ACPH1TC_MASK (0x700U)
2188#define CMP_C3_ACPH1TC_SHIFT (8U)
2189/*! ACPH1TC - Analog Comparator Phase1 Timing Control.
2190 * 0b000..Phase1 active time in one sampling period equals to T
2191 * 0b001..Phase1 active time in one sampling period equals to 2*T
2192 * 0b010..Phase1 active time in one sampling period equals to 4*T
2193 * 0b011..Phase1 active time in one sampling period equals to 8*T
2194 * 0b100..Phase1 active time in one sampling period equals to T
2195 * 0b101..Phase1 active time in one sampling period equals to T
2196 * 0b110..Phase1 active time in one sampling period equals to T
2197 * 0b111..Phase1 active time in one sampling period equals to 0
2198 */
2199#define CMP_C3_ACPH1TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH1TC_SHIFT)) & CMP_C3_ACPH1TC_MASK)
2200#define CMP_C3_ACSAT_MASK (0x7000U)
2201#define CMP_C3_ACSAT_SHIFT (12U)
2202/*! ACSAT - Analog Comparator Sampling Time control.
2203 * 0b000..The sampling time equals to T
2204 * 0b001..The sampling time equasl to 2*T
2205 * 0b010..The sampling time equasl to 4*T
2206 * 0b011..The sampling time equasl to 8*T
2207 * 0b100..The sampling time equasl to 16*T
2208 * 0b101..The sampling time equasl to 32*T
2209 * 0b110..The sampling time equasl to 64*T
2210 * 0b111..The sampling time equasl to 256*T
2211 */
2212#define CMP_C3_ACSAT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACSAT_SHIFT)) & CMP_C3_ACSAT_MASK)
2213#define CMP_C3_DMCS_MASK (0x10000U)
2214#define CMP_C3_DMCS_SHIFT (16U)
2215/*! DMCS - Discrete Mode Clock Selection
2216 * 0b0..Slow clock is selected for the timing generation.
2217 * 0b1..Fast clock is selected for the timing generation.
2218 */
2219#define CMP_C3_DMCS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_DMCS_SHIFT)) & CMP_C3_DMCS_MASK)
2220#define CMP_C3_RDIVE_MASK (0x100000U)
2221#define CMP_C3_RDIVE_SHIFT (20U)
2222/*! RDIVE - Resistor Divider Enable
2223 * 0b0..The resistor is not enabled even when either NCHEN or PCHEN is set to1 but the actual input is in the range of 0 - 1.8v.
2224 * 0b1..The resistor is enabled because the inputs are above 1.8v.
2225 */
2226#define CMP_C3_RDIVE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_RDIVE_SHIFT)) & CMP_C3_RDIVE_MASK)
2227#define CMP_C3_NCHCTEN_MASK (0x1000000U)
2228#define CMP_C3_NCHCTEN_SHIFT (24U)
2229/*! NCHCTEN - Negative Channel Continuous Mode Enable.
2230 * 0b0..Negative channel is in Discrete Mode and special timing needs to be configured.
2231 * 0b1..Negative channel is in Continuous Mode and no special timing is requried.
2232 */
2233#define CMP_C3_NCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_NCHCTEN_SHIFT)) & CMP_C3_NCHCTEN_MASK)
2234#define CMP_C3_PCHCTEN_MASK (0x10000000U)
2235#define CMP_C3_PCHCTEN_SHIFT (28U)
2236/*! PCHCTEN - Positive Channel Continuous Mode Enable.
2237 * 0b0..Positive channel is in Discrete Mode and special timing needs to be configured.
2238 * 0b1..Positive channel is in Continuous Mode and no special timing is requried.
2239 */
2240#define CMP_C3_PCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_PCHCTEN_SHIFT)) & CMP_C3_PCHCTEN_MASK)
2241/*! @} */
2242
2243
2244/*!
2245 * @}
2246 */ /* end of group CMP_Register_Masks */
2247
2248
2249/* CMP - Peripheral instance base addresses */
2250/** Peripheral CMP0 base address */
2251#define CMP0_BASE (0x41042000u)
2252/** Peripheral CMP0 base pointer */
2253#define CMP0 ((CMP_Type *)CMP0_BASE)
2254/** Peripheral CMP1 base address */
2255#define CMP1_BASE (0x41043000u)
2256/** Peripheral CMP1 base pointer */
2257#define CMP1 ((CMP_Type *)CMP1_BASE)
2258/** Array initializer of CMP peripheral base addresses */
2259#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
2260/** Array initializer of CMP peripheral base pointers */
2261#define CMP_BASE_PTRS { CMP0, CMP1 }
2262/** Interrupt vectors for the CMP peripheral type */
2263#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
2264
2265/*!
2266 * @}
2267 */ /* end of group CMP_Peripheral_Access_Layer */
2268
2269
2270/* ----------------------------------------------------------------------------
2271 -- CRC Peripheral Access Layer
2272 ---------------------------------------------------------------------------- */
2273
2274/*!
2275 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
2276 * @{
2277 */
2278
2279/** CRC - Register Layout Typedef */
2280typedef struct {
2281 union { /* offset: 0x0 */
2282 struct { /* offset: 0x0 */
2283 __IO uint8_t DATALL; /**< CRC_DATALL register, offset: 0x0 */
2284 __IO uint8_t DATALU; /**< CRC_DATALU register, offset: 0x1 */
2285 __IO uint8_t DATAHL; /**< CRC_DATAHL register, offset: 0x2 */
2286 __IO uint8_t DATAHU; /**< CRC_DATAHU register, offset: 0x3 */
2287 } ACCESS8BIT;
2288 struct { /* offset: 0x0 */
2289 __IO uint16_t DATAL; /**< CRC_DATAL register, offset: 0x0 */
2290 __IO uint16_t DATAH; /**< CRC_DATAH register, offset: 0x2 */
2291 } ACCESS16BIT;
2292 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
2293 };
2294 union { /* offset: 0x4 */
2295 struct { /* offset: 0x4 */
2296 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register, offset: 0x4 */
2297 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register, offset: 0x5 */
2298 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register, offset: 0x6 */
2299 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register, offset: 0x7 */
2300 } GPOLY_ACCESS8BIT;
2301 struct { /* offset: 0x4 */
2302 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register, offset: 0x4 */
2303 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register, offset: 0x6 */
2304 } GPOLY_ACCESS16BIT;
2305 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
2306 };
2307 union { /* offset: 0x8 */
2308 struct { /* offset: 0x8 */
2309 uint8_t RESERVED_0[3];
2310 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register, offset: 0xB */
2311 } CTRL_ACCESS8BIT;
2312 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
2313 };
2314} CRC_Type;
2315
2316/* ----------------------------------------------------------------------------
2317 -- CRC Register Masks
2318 ---------------------------------------------------------------------------- */
2319
2320/*!
2321 * @addtogroup CRC_Register_Masks CRC Register Masks
2322 * @{
2323 */
2324
2325/*! @name DATALL - CRC_DATALL register */
2326/*! @{ */
2327#define CRC_DATALL_DATALL_MASK (0xFFU)
2328#define CRC_DATALL_DATALL_SHIFT (0U)
2329#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
2330/*! @} */
2331
2332/*! @name DATALU - CRC_DATALU register */
2333/*! @{ */
2334#define CRC_DATALU_DATALU_MASK (0xFFU)
2335#define CRC_DATALU_DATALU_SHIFT (0U)
2336#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
2337/*! @} */
2338
2339/*! @name DATAHL - CRC_DATAHL register */
2340/*! @{ */
2341#define CRC_DATAHL_DATAHL_MASK (0xFFU)
2342#define CRC_DATAHL_DATAHL_SHIFT (0U)
2343#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
2344/*! @} */
2345
2346/*! @name DATAHU - CRC_DATAHU register */
2347/*! @{ */
2348#define CRC_DATAHU_DATAHU_MASK (0xFFU)
2349#define CRC_DATAHU_DATAHU_SHIFT (0U)
2350#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
2351/*! @} */
2352
2353/*! @name DATAL - CRC_DATAL register */
2354/*! @{ */
2355#define CRC_DATAL_DATAL_MASK (0xFFFFU)
2356#define CRC_DATAL_DATAL_SHIFT (0U)
2357#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
2358/*! @} */
2359
2360/*! @name DATAH - CRC_DATAH register */
2361/*! @{ */
2362#define CRC_DATAH_DATAH_MASK (0xFFFFU)
2363#define CRC_DATAH_DATAH_SHIFT (0U)
2364#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
2365/*! @} */
2366
2367/*! @name DATA - CRC Data register */
2368/*! @{ */
2369#define CRC_DATA_LL_MASK (0xFFU)
2370#define CRC_DATA_LL_SHIFT (0U)
2371/*! LL - CRC Low Lower Byte
2372 */
2373#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
2374#define CRC_DATA_LU_MASK (0xFF00U)
2375#define CRC_DATA_LU_SHIFT (8U)
2376/*! LU - CRC Low Upper Byte
2377 */
2378#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
2379#define CRC_DATA_HL_MASK (0xFF0000U)
2380#define CRC_DATA_HL_SHIFT (16U)
2381/*! HL - CRC High Lower Byte
2382 */
2383#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
2384#define CRC_DATA_HU_MASK (0xFF000000U)
2385#define CRC_DATA_HU_SHIFT (24U)
2386/*! HU - CRC High Upper Byte
2387 */
2388#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
2389/*! @} */
2390
2391/*! @name GPOLYLL - CRC_GPOLYLL register */
2392/*! @{ */
2393#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
2394#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
2395#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
2396/*! @} */
2397
2398/*! @name GPOLYLU - CRC_GPOLYLU register */
2399/*! @{ */
2400#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
2401#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
2402#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
2403/*! @} */
2404
2405/*! @name GPOLYHL - CRC_GPOLYHL register */
2406/*! @{ */
2407#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
2408#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
2409#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
2410/*! @} */
2411
2412/*! @name GPOLYHU - CRC_GPOLYHU register */
2413/*! @{ */
2414#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
2415#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
2416#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
2417/*! @} */
2418
2419/*! @name GPOLYL - CRC_GPOLYL register */
2420/*! @{ */
2421#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
2422#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
2423#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
2424/*! @} */
2425
2426/*! @name GPOLYH - CRC_GPOLYH register */
2427/*! @{ */
2428#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
2429#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
2430#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
2431/*! @} */
2432
2433/*! @name GPOLY - CRC Polynomial register */
2434/*! @{ */
2435#define CRC_GPOLY_LOW_MASK (0xFFFFU)
2436#define CRC_GPOLY_LOW_SHIFT (0U)
2437/*! LOW - Low Polynominal Half-word
2438 */
2439#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
2440#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
2441#define CRC_GPOLY_HIGH_SHIFT (16U)
2442/*! HIGH - High Polynominal Half-word
2443 */
2444#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
2445/*! @} */
2446
2447/*! @name CTRLHU - CRC_CTRLHU register */
2448/*! @{ */
2449#define CRC_CTRLHU_TCRC_MASK (0x1U)
2450#define CRC_CTRLHU_TCRC_SHIFT (0U)
2451/*! TCRC - TCRC
2452 * 0b0..16-bit CRC protocol.
2453 * 0b1..32-bit CRC protocol.
2454 */
2455#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
2456#define CRC_CTRLHU_WAS_MASK (0x2U)
2457#define CRC_CTRLHU_WAS_SHIFT (1U)
2458/*! WAS - Write CRC Data Register As Seed
2459 * 0b0..Writes to the CRC data register are data values.
2460 * 0b1..Writes to the CRC data register are seed values.
2461 */
2462#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
2463#define CRC_CTRLHU_FXOR_MASK (0x4U)
2464#define CRC_CTRLHU_FXOR_SHIFT (2U)
2465/*! FXOR - Complement Read Of CRC Data Register
2466 * 0b0..No XOR on reading.
2467 * 0b1..Invert or complement the read value of the CRC Data register.
2468 */
2469#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
2470#define CRC_CTRLHU_TOTR_MASK (0x30U)
2471#define CRC_CTRLHU_TOTR_SHIFT (4U)
2472/*! TOTR - Type Of Transpose For Read
2473 * 0b00..No transposition.
2474 * 0b01..Bits in bytes are transposed; bytes are not transposed.
2475 * 0b10..Both bits in bytes and bytes are transposed.
2476 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
2477 */
2478#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
2479#define CRC_CTRLHU_TOT_MASK (0xC0U)
2480#define CRC_CTRLHU_TOT_SHIFT (6U)
2481/*! TOT - Type Of Transpose For Writes
2482 * 0b00..No transposition.
2483 * 0b01..Bits in bytes are transposed; bytes are not transposed.
2484 * 0b10..Both bits in bytes and bytes are transposed.
2485 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
2486 */
2487#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
2488/*! @} */
2489
2490/*! @name CTRL - CRC Control register */
2491/*! @{ */
2492#define CRC_CTRL_TCRC_MASK (0x1000000U)
2493#define CRC_CTRL_TCRC_SHIFT (24U)
2494/*! TCRC - TCRC
2495 * 0b0..16-bit CRC protocol.
2496 * 0b1..32-bit CRC protocol.
2497 */
2498#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
2499#define CRC_CTRL_WAS_MASK (0x2000000U)
2500#define CRC_CTRL_WAS_SHIFT (25U)
2501/*! WAS - Write CRC Data Register As Seed
2502 * 0b0..Writes to the CRC data register are data values.
2503 * 0b1..Writes to the CRC data register are seed values.
2504 */
2505#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
2506#define CRC_CTRL_FXOR_MASK (0x4000000U)
2507#define CRC_CTRL_FXOR_SHIFT (26U)
2508/*! FXOR - Complement Read Of CRC Data Register
2509 * 0b0..No XOR on reading.
2510 * 0b1..Invert or complement the read value of the CRC Data register.
2511 */
2512#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
2513#define CRC_CTRL_TOTR_MASK (0x30000000U)
2514#define CRC_CTRL_TOTR_SHIFT (28U)
2515/*! TOTR - Type Of Transpose For Read
2516 * 0b00..No transposition.
2517 * 0b01..Bits in bytes are transposed; bytes are not transposed.
2518 * 0b10..Both bits in bytes and bytes are transposed.
2519 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
2520 */
2521#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
2522#define CRC_CTRL_TOT_MASK (0xC0000000U)
2523#define CRC_CTRL_TOT_SHIFT (30U)
2524/*! TOT - Type Of Transpose For Writes
2525 * 0b00..No transposition.
2526 * 0b01..Bits in bytes are transposed; bytes are not transposed.
2527 * 0b10..Both bits in bytes and bytes are transposed.
2528 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
2529 */
2530#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
2531/*! @} */
2532
2533
2534/*!
2535 * @}
2536 */ /* end of group CRC_Register_Masks */
2537
2538
2539/* CRC - Peripheral instance base addresses */
2540/** Peripheral CRC0 base address */
2541#define CRC0_BASE (0x41029000u)
2542/** Peripheral CRC0 base pointer */
2543#define CRC0 ((CRC_Type *)CRC0_BASE)
2544/** Array initializer of CRC peripheral base addresses */
2545#define CRC_BASE_ADDRS { CRC0_BASE }
2546/** Array initializer of CRC peripheral base pointers */
2547#define CRC_BASE_PTRS { CRC0 }
2548
2549/*!
2550 * @}
2551 */ /* end of group CRC_Peripheral_Access_Layer */
2552
2553
2554/* ----------------------------------------------------------------------------
2555 -- DAC Peripheral Access Layer
2556 ---------------------------------------------------------------------------- */
2557
2558/*!
2559 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
2560 * @{
2561 */
2562
2563/** DAC - Register Layout Typedef */
2564typedef struct {
2565 __I uint32_t VERID; /**< Version Identifier Register, offset: 0x0 */
2566 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
2567 __O uint32_t DATA; /**< DAC Data Register, offset: 0x8 */
2568 __IO uint32_t CR; /**< DAC Status and Control Register, offset: 0xC */
2569 __I uint32_t PTR; /**< DAC FIFO Pointer Register, offset: 0x10 */
2570 __IO uint32_t CR2; /**< DAC Status and Control Register 2, offset: 0x14 */
2571 __IO uint32_t ITRM; /**< Internal Current Reference Trim Register, offset: 0x18 */
2572} DAC_Type;
2573
2574/* ----------------------------------------------------------------------------
2575 -- DAC Register Masks
2576 ---------------------------------------------------------------------------- */
2577
2578/*!
2579 * @addtogroup DAC_Register_Masks DAC Register Masks
2580 * @{
2581 */
2582
2583/*! @name VERID - Version Identifier Register */
2584/*! @{ */
2585#define DAC_VERID_FEATURE_MASK (0xFFFFU)
2586#define DAC_VERID_FEATURE_SHIFT (0U)
2587/*! FEATURE - Feature Identification Number
2588 * 0b0000000000000000..Standard feature set
2589 * 0b0000000000000001..C40 feature set
2590 * 0b0000000000000010..5V DAC feature set
2591 * 0b0000000000000100..ADC BIST feature set
2592 */
2593#define DAC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_FEATURE_SHIFT)) & DAC_VERID_FEATURE_MASK)
2594#define DAC_VERID_MINOR_MASK (0xFF0000U)
2595#define DAC_VERID_MINOR_SHIFT (16U)
2596/*! MINOR - Minor version number
2597 */
2598#define DAC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MINOR_SHIFT)) & DAC_VERID_MINOR_MASK)
2599#define DAC_VERID_MAJOR_MASK (0xFF000000U)
2600#define DAC_VERID_MAJOR_SHIFT (24U)
2601/*! MAJOR - Major version number
2602 */
2603#define DAC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MAJOR_SHIFT)) & DAC_VERID_MAJOR_MASK)
2604/*! @} */
2605
2606/*! @name PARAM - Parameter Register */
2607/*! @{ */
2608#define DAC_PARAM_FIFOSZ_MASK (0x7U)
2609#define DAC_PARAM_FIFOSZ_SHIFT (0U)
2610/*! FIFOSZ - FIFO size
2611 * 0b000..FIFO depth is 2
2612 * 0b001..FIFO depth is 4
2613 * 0b010..FIFO depth is 8
2614 * 0b011..FIFO depth is 16
2615 * 0b100..FIFO depth is 32
2616 * 0b101..FIFO depth is 64
2617 * 0b110..FIFO depth is 128
2618 * 0b111..FIFO depth is 256
2619 */
2620#define DAC_PARAM_FIFOSZ(x) (((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK)
2621/*! @} */
2622
2623/*! @name DATA - DAC Data Register */
2624/*! @{ */
2625#define DAC_DATA_DATA0_MASK (0xFFFU)
2626#define DAC_DATA_DATA0_SHIFT (0U)
2627/*! DATA0 - FIFO DATA0
2628 */
2629#define DAC_DATA_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DAC_DATA_DATA0_SHIFT)) & DAC_DATA_DATA0_MASK)
2630/*! @} */
2631
2632/*! @name CR - DAC Status and Control Register */
2633/*! @{ */
2634#define DAC_CR_FULLF_MASK (0x1U)
2635#define DAC_CR_FULLF_SHIFT (0U)
2636/*! FULLF - Full Flag
2637 * 0b0..FIFO is not full.
2638 * 0b1..FIFO is full.
2639 */
2640#define DAC_CR_FULLF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLF_SHIFT)) & DAC_CR_FULLF_MASK)
2641#define DAC_CR_NEMPTF_MASK (0x2U)
2642#define DAC_CR_NEMPTF_SHIFT (1U)
2643/*! NEMPTF - Nearly Empty Flag
2644 * 0b0..More than one data is available in the FIFO.
2645 * 0b1..One data is available in the FIFO.
2646 */
2647#define DAC_CR_NEMPTF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_NEMPTF_SHIFT)) & DAC_CR_NEMPTF_MASK)
2648#define DAC_CR_WMF_MASK (0x4U)
2649#define DAC_CR_WMF_SHIFT (2U)
2650/*! WMF - FIFO Watermark Status Flag
2651 * 0b0..The DAC buffer read pointer has not reached the watermark level.
2652 * 0b1..The DAC buffer read pointer has reached the watermark level.
2653 */
2654#define DAC_CR_WMF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WMF_SHIFT)) & DAC_CR_WMF_MASK)
2655#define DAC_CR_UDFF_MASK (0x8U)
2656#define DAC_CR_UDFF_SHIFT (3U)
2657/*! UDFF - Underflow Flag
2658 * 0b0..No underflow has occurred since the last time the flag was cleared.
2659 * 0b1..At least one trigger underflow has occurred since the last time the flag was cleared.
2660 */
2661#define DAC_CR_UDFF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UDFF_SHIFT)) & DAC_CR_UDFF_MASK)
2662#define DAC_CR_OVFF_MASK (0x10U)
2663#define DAC_CR_OVFF_SHIFT (4U)
2664/*! OVFF - Overflow Flag
2665 * 0b0..No overflow has occurred since the last time the flag was cleared.
2666 * 0b1..At least one FIFO overflow has occurred since the last time the flag was cleared.
2667 */
2668#define DAC_CR_OVFF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_OVFF_SHIFT)) & DAC_CR_OVFF_MASK)
2669#define DAC_CR_FULLIE_MASK (0x100U)
2670#define DAC_CR_FULLIE_SHIFT (8U)
2671/*! FULLIE - Full Interrupt Enable
2672 * 0b0..FIFO Full interrupt is disabled.
2673 * 0b1..FIFO Full interrupt is enabled.
2674 */
2675#define DAC_CR_FULLIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLIE_SHIFT)) & DAC_CR_FULLIE_MASK)
2676#define DAC_CR_EMPTIE_MASK (0x200U)
2677#define DAC_CR_EMPTIE_SHIFT (9U)
2678/*! EMPTIE - Nearly Empty Interrupt Enable
2679 * 0b0..FIFO Nearly Empty interrupt is disabled.
2680 * 0b1..FIFO Nearly Empty interrupt is enabled.
2681 */
2682#define DAC_CR_EMPTIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_EMPTIE_SHIFT)) & DAC_CR_EMPTIE_MASK)
2683#define DAC_CR_WTMIE_MASK (0x400U)
2684#define DAC_CR_WTMIE_SHIFT (10U)
2685/*! WTMIE - Watermark Interrupt Enable
2686 * 0b0..Watermark interrupt is disabled.
2687 * 0b1..Watermark interrupt is enabled.
2688 */
2689#define DAC_CR_WTMIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WTMIE_SHIFT)) & DAC_CR_WTMIE_MASK)
2690#define DAC_CR_SWTRG_MASK (0x1000U)
2691#define DAC_CR_SWTRG_SHIFT (12U)
2692/*! SWTRG - DAC Software Trigger
2693 * 0b0..The DAC soft trigger is not valid.
2694 * 0b1..The DAC soft trigger is valid.
2695 */
2696#define DAC_CR_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWTRG_SHIFT)) & DAC_CR_SWTRG_MASK)
2697#define DAC_CR_TRGSEL_MASK (0x2000U)
2698#define DAC_CR_TRGSEL_SHIFT (13U)
2699/*! TRGSEL - DAC Trigger Select
2700 * 0b0..The DAC hardware trigger is selected.
2701 * 0b1..The DAC software trigger is selected.
2702 */
2703#define DAC_CR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_TRGSEL_SHIFT)) & DAC_CR_TRGSEL_MASK)
2704#define DAC_CR_DACRFS_MASK (0x4000U)
2705#define DAC_CR_DACRFS_SHIFT (14U)
2706/*! DACRFS - DAC Reference Select
2707 * 0b0..The DAC selects DACREF_1 as the reference voltage.
2708 * 0b1..The DAC selects DACREF_2 as the reference voltage.
2709 */
2710#define DAC_CR_DACRFS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACRFS_SHIFT)) & DAC_CR_DACRFS_MASK)
2711#define DAC_CR_DACEN_MASK (0x8000U)
2712#define DAC_CR_DACEN_SHIFT (15U)
2713/*! DACEN - DAC Enable
2714 * 0b0..The DAC system is disabled.
2715 * 0b1..The DAC system is enabled.
2716 */
2717#define DAC_CR_DACEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACEN_SHIFT)) & DAC_CR_DACEN_MASK)
2718#define DAC_CR_FIFOEN_MASK (0x10000U)
2719#define DAC_CR_FIFOEN_SHIFT (16U)
2720/*! FIFOEN - FIFO Enable
2721 * 0b0..FIFO is disabled and only one level buffer is enabled. Any data written from this buffer goes to conversion.
2722 * 0b1..FIFO is enabled. Data will first read from FIFO to buffer then go to conversion.
2723 */
2724#define DAC_CR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFOEN_SHIFT)) & DAC_CR_FIFOEN_MASK)
2725#define DAC_CR_SWMD_MASK (0x20000U)
2726#define DAC_CR_SWMD_SHIFT (17U)
2727/*! SWMD - DAC FIFO Mode Select
2728 * 0b0..Normal mode
2729 * 0b1..Swing back mode
2730 */
2731#define DAC_CR_SWMD(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWMD_SHIFT)) & DAC_CR_SWMD_MASK)
2732#define DAC_CR_UVIE_MASK (0x40000U)
2733#define DAC_CR_UVIE_SHIFT (18U)
2734/*! UVIE - Underflow and overflow interrupt enable
2735 * 0b0..Underflow and overflow interrupt is disabled.
2736 * 0b1..Underflow and overflow interrupt is enabled.
2737 */
2738#define DAC_CR_UVIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UVIE_SHIFT)) & DAC_CR_UVIE_MASK)
2739#define DAC_CR_FIFORST_MASK (0x200000U)
2740#define DAC_CR_FIFORST_SHIFT (21U)
2741/*! FIFORST - FIFO Reset
2742 * 0b0..No effect
2743 * 0b1..FIFO reset
2744 */
2745#define DAC_CR_FIFORST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFORST_SHIFT)) & DAC_CR_FIFORST_MASK)
2746#define DAC_CR_SWRST_MASK (0x400000U)
2747#define DAC_CR_SWRST_SHIFT (22U)
2748/*! SWRST - Software reset
2749 */
2750#define DAC_CR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWRST_SHIFT)) & DAC_CR_SWRST_MASK)
2751#define DAC_CR_DMAEN_MASK (0x800000U)
2752#define DAC_CR_DMAEN_SHIFT (23U)
2753/*! DMAEN - DMA Enable Select
2754 * 0b0..DMA is disabled.
2755 * 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The
2756 * interrupts will not be presented on this module at the same time.
2757 */
2758#define DAC_CR_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DMAEN_SHIFT)) & DAC_CR_DMAEN_MASK)
2759#define DAC_CR_WML_MASK (0xFF000000U)
2760#define DAC_CR_WML_SHIFT (24U)
2761/*! WML - Watermark Level Select
2762 */
2763#define DAC_CR_WML(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WML_SHIFT)) & DAC_CR_WML_MASK)
2764/*! @} */
2765
2766/*! @name PTR - DAC FIFO Pointer Register */
2767/*! @{ */
2768#define DAC_PTR_DACWFP_MASK (0xFFU)
2769#define DAC_PTR_DACWFP_SHIFT (0U)
2770/*! DACWFP - DACWFP
2771 */
2772#define DAC_PTR_DACWFP(x) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACWFP_SHIFT)) & DAC_PTR_DACWFP_MASK)
2773#define DAC_PTR_DACRFP_MASK (0xFF0000U)
2774#define DAC_PTR_DACRFP_SHIFT (16U)
2775/*! DACRFP - DACRFP
2776 */
2777#define DAC_PTR_DACRFP(x) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACRFP_SHIFT)) & DAC_PTR_DACRFP_MASK)
2778/*! @} */
2779
2780/*! @name CR2 - DAC Status and Control Register 2 */
2781/*! @{ */
2782#define DAC_CR2_BFEN_MASK (0x1U)
2783#define DAC_CR2_BFEN_SHIFT (0U)
2784/*! BFEN - Buffer Enable
2785 * 0b0..Opamp is not used as buffer
2786 * 0b1..Opamp is used as buffer
2787 */
2788#define DAC_CR2_BFEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFEN_SHIFT)) & DAC_CR2_BFEN_MASK)
2789#define DAC_CR2_OEN_MASK (0x2U)
2790#define DAC_CR2_OEN_SHIFT (1U)
2791/*! OEN - Optional Enable
2792 * 0b0..Output buffer is not bypassed
2793 * 0b1..Output buffer is bypassed
2794 */
2795#define DAC_CR2_OEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_OEN_SHIFT)) & DAC_CR2_OEN_MASK)
2796#define DAC_CR2_BFMS_MASK (0x4U)
2797#define DAC_CR2_BFMS_SHIFT (2U)
2798/*! BFMS - Buffer Middle Speed Select
2799 * 0b0..Buffer middle speed not selected
2800 * 0b1..Buffer middle speed selected
2801 */
2802#define DAC_CR2_BFMS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFMS_SHIFT)) & DAC_CR2_BFMS_MASK)
2803#define DAC_CR2_BFHS_MASK (0x8U)
2804#define DAC_CR2_BFHS_SHIFT (3U)
2805/*! BFHS - Buffer High Speed Select
2806 * 0b0..Buffer high speed not selected
2807 * 0b1..Buffer high speed selected
2808 */
2809#define DAC_CR2_BFHS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFHS_SHIFT)) & DAC_CR2_BFHS_MASK)
2810#define DAC_CR2_IREF2_MASK (0x10U)
2811#define DAC_CR2_IREF2_SHIFT (4U)
2812/*! IREF2 - Internal PTAT (Proportional To Absolute Temperature) Current Reference Select
2813 * 0b0..Internal PTAT Current Reference not selected
2814 * 0b1..Internal PTAT Current Reference selected
2815 */
2816#define DAC_CR2_IREF2(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF2_SHIFT)) & DAC_CR2_IREF2_MASK)
2817#define DAC_CR2_IREF1_MASK (0x20U)
2818#define DAC_CR2_IREF1_SHIFT (5U)
2819/*! IREF1 - Internal ZTC (Zero Temperature Coefficient) Current Reference Select
2820 * 0b0..Internal ZTC Current Reference not selected
2821 * 0b1..Internal ZTC Current Reference selected
2822 */
2823#define DAC_CR2_IREF1(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF1_SHIFT)) & DAC_CR2_IREF1_MASK)
2824#define DAC_CR2_IREF_MASK (0x40U)
2825#define DAC_CR2_IREF_SHIFT (6U)
2826/*! IREF - Internal Current Reference Select
2827 * 0b0..Internal Current Reference not selected
2828 * 0b1..Internal Current Reference selected
2829 */
2830#define DAC_CR2_IREF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF_SHIFT)) & DAC_CR2_IREF_MASK)
2831/*! @} */
2832
2833/*! @name ITRM - Internal Current Reference Trim Register */
2834/*! @{ */
2835#define DAC_ITRM_TRIM_MASK (0x7U)
2836#define DAC_ITRM_TRIM_SHIFT (0U)
2837/*! TRIM - Internal Current Trim Register
2838 */
2839#define DAC_ITRM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DAC_ITRM_TRIM_SHIFT)) & DAC_ITRM_TRIM_MASK)
2840/*! @} */
2841
2842
2843/*!
2844 * @}
2845 */ /* end of group DAC_Register_Masks */
2846
2847
2848/* DAC - Peripheral instance base addresses */
2849/** Peripheral DAC0 base address */
2850#define DAC0_BASE (0x41044000u)
2851/** Peripheral DAC0 base pointer */
2852#define DAC0 ((DAC_Type *)DAC0_BASE)
2853/** Peripheral DAC1 base address */
2854#define DAC1_BASE (0x41045000u)
2855/** Peripheral DAC1 base pointer */
2856#define DAC1 ((DAC_Type *)DAC1_BASE)
2857/** Array initializer of DAC peripheral base addresses */
2858#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
2859/** Array initializer of DAC peripheral base pointers */
2860#define DAC_BASE_PTRS { DAC0, DAC1 }
2861/** Interrupt vectors for the DAC peripheral type */
2862#define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
2863
2864/*!
2865 * @}
2866 */ /* end of group DAC_Peripheral_Access_Layer */
2867
2868
2869/* ----------------------------------------------------------------------------
2870 -- DMA Peripheral Access Layer
2871 ---------------------------------------------------------------------------- */
2872
2873/*!
2874 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
2875 * @{
2876 */
2877
2878/** DMA - Register Layout Typedef */
2879typedef struct {
2880 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
2881 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
2882 uint8_t RESERVED_0[4];
2883 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
2884 uint8_t RESERVED_1[4];
2885 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
2886 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
2887 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
2888 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
2889 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
2890 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
2891 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
2892 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
2893 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
2894 uint8_t RESERVED_2[4];
2895 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
2896 uint8_t RESERVED_3[4];
2897 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
2898 uint8_t RESERVED_4[4];
2899 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
2900 uint8_t RESERVED_5[12];
2901 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
2902 uint8_t RESERVED_6[184];
2903 __IO uint8_t DCHPRI3; /**< Channel Priority Register, offset: 0x100 */
2904 __IO uint8_t DCHPRI2; /**< Channel Priority Register, offset: 0x101 */
2905 __IO uint8_t DCHPRI1; /**< Channel Priority Register, offset: 0x102 */
2906 __IO uint8_t DCHPRI0; /**< Channel Priority Register, offset: 0x103 */
2907 __IO uint8_t DCHPRI7; /**< Channel Priority Register, offset: 0x104 */
2908 __IO uint8_t DCHPRI6; /**< Channel Priority Register, offset: 0x105 */
2909 __IO uint8_t DCHPRI5; /**< Channel Priority Register, offset: 0x106 */
2910 __IO uint8_t DCHPRI4; /**< Channel Priority Register, offset: 0x107 */
2911 __IO uint8_t DCHPRI11; /**< Channel Priority Register, offset: 0x108 */
2912 __IO uint8_t DCHPRI10; /**< Channel Priority Register, offset: 0x109 */
2913 __IO uint8_t DCHPRI9; /**< Channel Priority Register, offset: 0x10A */
2914 __IO uint8_t DCHPRI8; /**< Channel Priority Register, offset: 0x10B */
2915 __IO uint8_t DCHPRI15; /**< Channel Priority Register, offset: 0x10C */
2916 __IO uint8_t DCHPRI14; /**< Channel Priority Register, offset: 0x10D */
2917 __IO uint8_t DCHPRI13; /**< Channel Priority Register, offset: 0x10E */
2918 __IO uint8_t DCHPRI12; /**< Channel Priority Register, offset: 0x10F */
2919 __IO uint8_t DCHPRI19; /**< Channel Priority Register, offset: 0x110 */
2920 __IO uint8_t DCHPRI18; /**< Channel Priority Register, offset: 0x111 */
2921 __IO uint8_t DCHPRI17; /**< Channel Priority Register, offset: 0x112 */
2922 __IO uint8_t DCHPRI16; /**< Channel Priority Register, offset: 0x113 */
2923 __IO uint8_t DCHPRI23; /**< Channel Priority Register, offset: 0x114 */
2924 __IO uint8_t DCHPRI22; /**< Channel Priority Register, offset: 0x115 */
2925 __IO uint8_t DCHPRI21; /**< Channel Priority Register, offset: 0x116 */
2926 __IO uint8_t DCHPRI20; /**< Channel Priority Register, offset: 0x117 */
2927 __IO uint8_t DCHPRI27; /**< Channel Priority Register, offset: 0x118 */
2928 __IO uint8_t DCHPRI26; /**< Channel Priority Register, offset: 0x119 */
2929 __IO uint8_t DCHPRI25; /**< Channel Priority Register, offset: 0x11A */
2930 __IO uint8_t DCHPRI24; /**< Channel Priority Register, offset: 0x11B */
2931 __IO uint8_t DCHPRI31; /**< Channel Priority Register, offset: 0x11C */
2932 __IO uint8_t DCHPRI30; /**< Channel Priority Register, offset: 0x11D */
2933 __IO uint8_t DCHPRI29; /**< Channel Priority Register, offset: 0x11E */
2934 __IO uint8_t DCHPRI28; /**< Channel Priority Register, offset: 0x11F */
2935 uint8_t RESERVED_7[3808];
2936 struct { /* offset: 0x1000, array step: 0x20 */
2937 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
2938 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
2939 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
2940 union { /* offset: 0x1008, array step: 0x20 */
2941 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
2942 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
2943 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
2944 };
2945 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
2946 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
2947 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
2948 union { /* offset: 0x1016, array step: 0x20 */
2949 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
2950 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
2951 };
2952 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
2953 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
2954 union { /* offset: 0x101E, array step: 0x20 */
2955 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
2956 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
2957 };
2958 } TCD[32];
2959} DMA_Type;
2960
2961/* ----------------------------------------------------------------------------
2962 -- DMA Register Masks
2963 ---------------------------------------------------------------------------- */
2964
2965/*!
2966 * @addtogroup DMA_Register_Masks DMA Register Masks
2967 * @{
2968 */
2969
2970/*! @name CR - Control Register */
2971/*! @{ */
2972#define DMA_CR_EBWR_MASK (0x1U)
2973#define DMA_CR_EBWR_SHIFT (0U)
2974/*! EBWR - Enable Buffered Writes
2975 * 0b0..Buffered writes are disabled.
2976 * 0b1..Buffered writes are enabled.
2977 */
2978#define DMA_CR_EBWR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EBWR_SHIFT)) & DMA_CR_EBWR_MASK)
2979#define DMA_CR_EDBG_MASK (0x2U)
2980#define DMA_CR_EDBG_SHIFT (1U)
2981/*! EDBG - Enable Debug
2982 * 0b0..When in debug mode, the DMA continues to operate.
2983 * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to
2984 * complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
2985 */
2986#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
2987#define DMA_CR_ERCA_MASK (0x4U)
2988#define DMA_CR_ERCA_SHIFT (2U)
2989/*! ERCA - Enable Round Robin Channel Arbitration
2990 * 0b0..Fixed priority arbitration is used for channel selection within each group.
2991 * 0b1..Round robin arbitration is used for channel selection within each group.
2992 */
2993#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
2994#define DMA_CR_ERGA_MASK (0x8U)
2995#define DMA_CR_ERGA_SHIFT (3U)
2996/*! ERGA - Enable Round Robin Group Arbitration
2997 * 0b0..Fixed priority arbitration is used for selection among the groups.
2998 * 0b1..Round robin arbitration is used for selection among the groups.
2999 */
3000#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
3001#define DMA_CR_HOE_MASK (0x10U)
3002#define DMA_CR_HOE_SHIFT (4U)
3003/*! HOE - Halt On Error
3004 * 0b0..Normal operation
3005 * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
3006 */
3007#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
3008#define DMA_CR_HALT_MASK (0x20U)
3009#define DMA_CR_HALT_SHIFT (5U)
3010/*! HALT - Halt DMA Operations
3011 * 0b0..Normal operation
3012 * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
3013 */
3014#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
3015#define DMA_CR_CLM_MASK (0x40U)
3016#define DMA_CR_CLM_SHIFT (6U)
3017/*! CLM - Continuous Link Mode
3018 * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again.
3019 * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated
3020 * again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel
3021 * link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the
3022 * next minor loop.
3023 */
3024#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
3025#define DMA_CR_EMLM_MASK (0x80U)
3026#define DMA_CR_EMLM_SHIFT (7U)
3027/*! EMLM - Enable Minor Loop Mapping
3028 * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
3029 * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES
3030 * field. The individual enable fields allow the minor loop offset to be applied to the source address, the
3031 * destination address, or both. The NBYTES field is reduced when either offset is enabled.
3032 */
3033#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
3034#define DMA_CR_GRP0PRI_MASK (0x100U)
3035#define DMA_CR_GRP0PRI_SHIFT (8U)
3036/*! GRP0PRI - Channel Group 0 Priority
3037 */
3038#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
3039#define DMA_CR_GRP1PRI_MASK (0x400U)
3040#define DMA_CR_GRP1PRI_SHIFT (10U)
3041/*! GRP1PRI - Channel Group 1 Priority
3042 */
3043#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
3044#define DMA_CR_ECX_MASK (0x10000U)
3045#define DMA_CR_ECX_SHIFT (16U)
3046/*! ECX - Error Cancel Transfer
3047 * 0b0..Normal operation
3048 * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and
3049 * force the minor loop to finish. The cancel takes effect after the last write of the current read/write
3050 * sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX
3051 * treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an
3052 * optional error interrupt.
3053 */
3054#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
3055#define DMA_CR_CX_MASK (0x20000U)
3056#define DMA_CR_CX_SHIFT (17U)
3057/*! CX - Cancel Transfer
3058 * 0b0..Normal operation
3059 * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The
3060 * cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after
3061 * the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
3062 */
3063#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
3064#define DMA_CR_ACTIVE_MASK (0x80000000U)
3065#define DMA_CR_ACTIVE_SHIFT (31U)
3066/*! ACTIVE - DMA Active Status
3067 * 0b0..eDMA is idle.
3068 * 0b1..eDMA is executing a channel.
3069 */
3070#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
3071/*! @} */
3072
3073/*! @name ES - Error Status Register */
3074/*! @{ */
3075#define DMA_ES_DBE_MASK (0x1U)
3076#define DMA_ES_DBE_SHIFT (0U)
3077/*! DBE - Destination Bus Error
3078 * 0b0..No destination bus error
3079 * 0b1..The last recorded error was a bus error on a destination write
3080 */
3081#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
3082#define DMA_ES_SBE_MASK (0x2U)
3083#define DMA_ES_SBE_SHIFT (1U)
3084/*! SBE - Source Bus Error
3085 * 0b0..No source bus error
3086 * 0b1..The last recorded error was a bus error on a source read
3087 */
3088#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
3089#define DMA_ES_SGE_MASK (0x4U)
3090#define DMA_ES_SGE_SHIFT (2U)
3091/*! SGE - Scatter/Gather Configuration Error
3092 * 0b0..No scatter/gather configuration error
3093 * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is
3094 * checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is
3095 * enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
3096 */
3097#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
3098#define DMA_ES_NCE_MASK (0x8U)
3099#define DMA_ES_NCE_SHIFT (3U)
3100/*! NCE - NBYTES/CITER Configuration Error
3101 * 0b0..No NBYTES/CITER configuration error
3102 * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields.
3103 * TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero,
3104 * or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
3105 */
3106#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
3107#define DMA_ES_DOE_MASK (0x10U)
3108#define DMA_ES_DOE_SHIFT (4U)
3109/*! DOE - Destination Offset Error
3110 * 0b0..No destination offset configuration error
3111 * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
3112 */
3113#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
3114#define DMA_ES_DAE_MASK (0x20U)
3115#define DMA_ES_DAE_SHIFT (5U)
3116/*! DAE - Destination Address Error
3117 * 0b0..No destination address configuration error
3118 * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
3119 */
3120#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
3121#define DMA_ES_SOE_MASK (0x40U)
3122#define DMA_ES_SOE_SHIFT (6U)
3123/*! SOE - Source Offset Error
3124 * 0b0..No source offset configuration error
3125 * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
3126 */
3127#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
3128#define DMA_ES_SAE_MASK (0x80U)
3129#define DMA_ES_SAE_SHIFT (7U)
3130/*! SAE - Source Address Error
3131 * 0b0..No source address configuration error.
3132 * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
3133 */
3134#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
3135#define DMA_ES_ERRCHN_MASK (0x1F00U)
3136#define DMA_ES_ERRCHN_SHIFT (8U)
3137/*! ERRCHN - Error Channel Number or Canceled Channel Number
3138 */
3139#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
3140#define DMA_ES_CPE_MASK (0x4000U)
3141#define DMA_ES_CPE_SHIFT (14U)
3142/*! CPE - Channel Priority Error
3143 * 0b0..No channel priority error
3144 * 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel
3145 * priorities within a group are not unique.
3146 */
3147#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
3148#define DMA_ES_GPE_MASK (0x8000U)
3149#define DMA_ES_GPE_SHIFT (15U)
3150/*! GPE - Group Priority Error
3151 * 0b0..No group priority error
3152 * 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique.
3153 */
3154#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
3155#define DMA_ES_ECX_MASK (0x10000U)
3156#define DMA_ES_ECX_SHIFT (16U)
3157/*! ECX - Transfer Canceled
3158 * 0b0..No canceled transfers
3159 * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input
3160 */
3161#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
3162#define DMA_ES_VLD_MASK (0x80000000U)
3163#define DMA_ES_VLD_SHIFT (31U)
3164/*! VLD - VLD
3165 * 0b0..No ERR bits are set.
3166 * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.
3167 */
3168#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
3169/*! @} */
3170
3171/*! @name ERQ - Enable Request Register */
3172/*! @{ */
3173#define DMA_ERQ_ERQ0_MASK (0x1U)
3174#define DMA_ERQ_ERQ0_SHIFT (0U)
3175/*! ERQ0 - Enable DMA Request 0
3176 * 0b0..The DMA request signal for the corresponding channel is disabled
3177 * 0b1..The DMA request signal for the corresponding channel is enabled
3178 */
3179#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
3180#define DMA_ERQ_ERQ1_MASK (0x2U)
3181#define DMA_ERQ_ERQ1_SHIFT (1U)
3182/*! ERQ1 - Enable DMA Request 1
3183 * 0b0..The DMA request signal for the corresponding channel is disabled
3184 * 0b1..The DMA request signal for the corresponding channel is enabled
3185 */
3186#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
3187#define DMA_ERQ_ERQ2_MASK (0x4U)
3188#define DMA_ERQ_ERQ2_SHIFT (2U)
3189/*! ERQ2 - Enable DMA Request 2
3190 * 0b0..The DMA request signal for the corresponding channel is disabled
3191 * 0b1..The DMA request signal for the corresponding channel is enabled
3192 */
3193#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
3194#define DMA_ERQ_ERQ3_MASK (0x8U)
3195#define DMA_ERQ_ERQ3_SHIFT (3U)
3196/*! ERQ3 - Enable DMA Request 3
3197 * 0b0..The DMA request signal for the corresponding channel is disabled
3198 * 0b1..The DMA request signal for the corresponding channel is enabled
3199 */
3200#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
3201#define DMA_ERQ_ERQ4_MASK (0x10U)
3202#define DMA_ERQ_ERQ4_SHIFT (4U)
3203/*! ERQ4 - Enable DMA Request 4
3204 * 0b0..The DMA request signal for the corresponding channel is disabled
3205 * 0b1..The DMA request signal for the corresponding channel is enabled
3206 */
3207#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
3208#define DMA_ERQ_ERQ5_MASK (0x20U)
3209#define DMA_ERQ_ERQ5_SHIFT (5U)
3210/*! ERQ5 - Enable DMA Request 5
3211 * 0b0..The DMA request signal for the corresponding channel is disabled
3212 * 0b1..The DMA request signal for the corresponding channel is enabled
3213 */
3214#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
3215#define DMA_ERQ_ERQ6_MASK (0x40U)
3216#define DMA_ERQ_ERQ6_SHIFT (6U)
3217/*! ERQ6 - Enable DMA Request 6
3218 * 0b0..The DMA request signal for the corresponding channel is disabled
3219 * 0b1..The DMA request signal for the corresponding channel is enabled
3220 */
3221#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
3222#define DMA_ERQ_ERQ7_MASK (0x80U)
3223#define DMA_ERQ_ERQ7_SHIFT (7U)
3224/*! ERQ7 - Enable DMA Request 7
3225 * 0b0..The DMA request signal for the corresponding channel is disabled
3226 * 0b1..The DMA request signal for the corresponding channel is enabled
3227 */
3228#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
3229#define DMA_ERQ_ERQ8_MASK (0x100U)
3230#define DMA_ERQ_ERQ8_SHIFT (8U)
3231/*! ERQ8 - Enable DMA Request 8
3232 * 0b0..The DMA request signal for the corresponding channel is disabled
3233 * 0b1..The DMA request signal for the corresponding channel is enabled
3234 */
3235#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
3236#define DMA_ERQ_ERQ9_MASK (0x200U)
3237#define DMA_ERQ_ERQ9_SHIFT (9U)
3238/*! ERQ9 - Enable DMA Request 9
3239 * 0b0..The DMA request signal for the corresponding channel is disabled
3240 * 0b1..The DMA request signal for the corresponding channel is enabled
3241 */
3242#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
3243#define DMA_ERQ_ERQ10_MASK (0x400U)
3244#define DMA_ERQ_ERQ10_SHIFT (10U)
3245/*! ERQ10 - Enable DMA Request 10
3246 * 0b0..The DMA request signal for the corresponding channel is disabled
3247 * 0b1..The DMA request signal for the corresponding channel is enabled
3248 */
3249#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
3250#define DMA_ERQ_ERQ11_MASK (0x800U)
3251#define DMA_ERQ_ERQ11_SHIFT (11U)
3252/*! ERQ11 - Enable DMA Request 11
3253 * 0b0..The DMA request signal for the corresponding channel is disabled
3254 * 0b1..The DMA request signal for the corresponding channel is enabled
3255 */
3256#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
3257#define DMA_ERQ_ERQ12_MASK (0x1000U)
3258#define DMA_ERQ_ERQ12_SHIFT (12U)
3259/*! ERQ12 - Enable DMA Request 12
3260 * 0b0..The DMA request signal for the corresponding channel is disabled
3261 * 0b1..The DMA request signal for the corresponding channel is enabled
3262 */
3263#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
3264#define DMA_ERQ_ERQ13_MASK (0x2000U)
3265#define DMA_ERQ_ERQ13_SHIFT (13U)
3266/*! ERQ13 - Enable DMA Request 13
3267 * 0b0..The DMA request signal for the corresponding channel is disabled
3268 * 0b1..The DMA request signal for the corresponding channel is enabled
3269 */
3270#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
3271#define DMA_ERQ_ERQ14_MASK (0x4000U)
3272#define DMA_ERQ_ERQ14_SHIFT (14U)
3273/*! ERQ14 - Enable DMA Request 14
3274 * 0b0..The DMA request signal for the corresponding channel is disabled
3275 * 0b1..The DMA request signal for the corresponding channel is enabled
3276 */
3277#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
3278#define DMA_ERQ_ERQ15_MASK (0x8000U)
3279#define DMA_ERQ_ERQ15_SHIFT (15U)
3280/*! ERQ15 - Enable DMA Request 15
3281 * 0b0..The DMA request signal for the corresponding channel is disabled
3282 * 0b1..The DMA request signal for the corresponding channel is enabled
3283 */
3284#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
3285#define DMA_ERQ_ERQ16_MASK (0x10000U)
3286#define DMA_ERQ_ERQ16_SHIFT (16U)
3287/*! ERQ16 - Enable DMA Request 16
3288 * 0b0..The DMA request signal for the corresponding channel is disabled
3289 * 0b1..The DMA request signal for the corresponding channel is enabled
3290 */
3291#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
3292#define DMA_ERQ_ERQ17_MASK (0x20000U)
3293#define DMA_ERQ_ERQ17_SHIFT (17U)
3294/*! ERQ17 - Enable DMA Request 17
3295 * 0b0..The DMA request signal for the corresponding channel is disabled
3296 * 0b1..The DMA request signal for the corresponding channel is enabled
3297 */
3298#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
3299#define DMA_ERQ_ERQ18_MASK (0x40000U)
3300#define DMA_ERQ_ERQ18_SHIFT (18U)
3301/*! ERQ18 - Enable DMA Request 18
3302 * 0b0..The DMA request signal for the corresponding channel is disabled
3303 * 0b1..The DMA request signal for the corresponding channel is enabled
3304 */
3305#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
3306#define DMA_ERQ_ERQ19_MASK (0x80000U)
3307#define DMA_ERQ_ERQ19_SHIFT (19U)
3308/*! ERQ19 - Enable DMA Request 19
3309 * 0b0..The DMA request signal for the corresponding channel is disabled
3310 * 0b1..The DMA request signal for the corresponding channel is enabled
3311 */
3312#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
3313#define DMA_ERQ_ERQ20_MASK (0x100000U)
3314#define DMA_ERQ_ERQ20_SHIFT (20U)
3315/*! ERQ20 - Enable DMA Request 20
3316 * 0b0..The DMA request signal for the corresponding channel is disabled
3317 * 0b1..The DMA request signal for the corresponding channel is enabled
3318 */
3319#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
3320#define DMA_ERQ_ERQ21_MASK (0x200000U)
3321#define DMA_ERQ_ERQ21_SHIFT (21U)
3322/*! ERQ21 - Enable DMA Request 21
3323 * 0b0..The DMA request signal for the corresponding channel is disabled
3324 * 0b1..The DMA request signal for the corresponding channel is enabled
3325 */
3326#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
3327#define DMA_ERQ_ERQ22_MASK (0x400000U)
3328#define DMA_ERQ_ERQ22_SHIFT (22U)
3329/*! ERQ22 - Enable DMA Request 22
3330 * 0b0..The DMA request signal for the corresponding channel is disabled
3331 * 0b1..The DMA request signal for the corresponding channel is enabled
3332 */
3333#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
3334#define DMA_ERQ_ERQ23_MASK (0x800000U)
3335#define DMA_ERQ_ERQ23_SHIFT (23U)
3336/*! ERQ23 - Enable DMA Request 23
3337 * 0b0..The DMA request signal for the corresponding channel is disabled
3338 * 0b1..The DMA request signal for the corresponding channel is enabled
3339 */
3340#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
3341#define DMA_ERQ_ERQ24_MASK (0x1000000U)
3342#define DMA_ERQ_ERQ24_SHIFT (24U)
3343/*! ERQ24 - Enable DMA Request 24
3344 * 0b0..The DMA request signal for the corresponding channel is disabled
3345 * 0b1..The DMA request signal for the corresponding channel is enabled
3346 */
3347#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
3348#define DMA_ERQ_ERQ25_MASK (0x2000000U)
3349#define DMA_ERQ_ERQ25_SHIFT (25U)
3350/*! ERQ25 - Enable DMA Request 25
3351 * 0b0..The DMA request signal for the corresponding channel is disabled
3352 * 0b1..The DMA request signal for the corresponding channel is enabled
3353 */
3354#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
3355#define DMA_ERQ_ERQ26_MASK (0x4000000U)
3356#define DMA_ERQ_ERQ26_SHIFT (26U)
3357/*! ERQ26 - Enable DMA Request 26
3358 * 0b0..The DMA request signal for the corresponding channel is disabled
3359 * 0b1..The DMA request signal for the corresponding channel is enabled
3360 */
3361#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
3362#define DMA_ERQ_ERQ27_MASK (0x8000000U)
3363#define DMA_ERQ_ERQ27_SHIFT (27U)
3364/*! ERQ27 - Enable DMA Request 27
3365 * 0b0..The DMA request signal for the corresponding channel is disabled
3366 * 0b1..The DMA request signal for the corresponding channel is enabled
3367 */
3368#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
3369#define DMA_ERQ_ERQ28_MASK (0x10000000U)
3370#define DMA_ERQ_ERQ28_SHIFT (28U)
3371/*! ERQ28 - Enable DMA Request 28
3372 * 0b0..The DMA request signal for the corresponding channel is disabled
3373 * 0b1..The DMA request signal for the corresponding channel is enabled
3374 */
3375#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
3376#define DMA_ERQ_ERQ29_MASK (0x20000000U)
3377#define DMA_ERQ_ERQ29_SHIFT (29U)
3378/*! ERQ29 - Enable DMA Request 29
3379 * 0b0..The DMA request signal for the corresponding channel is disabled
3380 * 0b1..The DMA request signal for the corresponding channel is enabled
3381 */
3382#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
3383#define DMA_ERQ_ERQ30_MASK (0x40000000U)
3384#define DMA_ERQ_ERQ30_SHIFT (30U)
3385/*! ERQ30 - Enable DMA Request 30
3386 * 0b0..The DMA request signal for the corresponding channel is disabled
3387 * 0b1..The DMA request signal for the corresponding channel is enabled
3388 */
3389#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
3390#define DMA_ERQ_ERQ31_MASK (0x80000000U)
3391#define DMA_ERQ_ERQ31_SHIFT (31U)
3392/*! ERQ31 - Enable DMA Request 31
3393 * 0b0..The DMA request signal for the corresponding channel is disabled
3394 * 0b1..The DMA request signal for the corresponding channel is enabled
3395 */
3396#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
3397/*! @} */
3398
3399/*! @name EEI - Enable Error Interrupt Register */
3400/*! @{ */
3401#define DMA_EEI_EEI0_MASK (0x1U)
3402#define DMA_EEI_EEI0_SHIFT (0U)
3403/*! EEI0 - Enable Error Interrupt 0
3404 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3405 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3406 */
3407#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
3408#define DMA_EEI_EEI1_MASK (0x2U)
3409#define DMA_EEI_EEI1_SHIFT (1U)
3410/*! EEI1 - Enable Error Interrupt 1
3411 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3412 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3413 */
3414#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
3415#define DMA_EEI_EEI2_MASK (0x4U)
3416#define DMA_EEI_EEI2_SHIFT (2U)
3417/*! EEI2 - Enable Error Interrupt 2
3418 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3419 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3420 */
3421#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
3422#define DMA_EEI_EEI3_MASK (0x8U)
3423#define DMA_EEI_EEI3_SHIFT (3U)
3424/*! EEI3 - Enable Error Interrupt 3
3425 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3426 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3427 */
3428#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
3429#define DMA_EEI_EEI4_MASK (0x10U)
3430#define DMA_EEI_EEI4_SHIFT (4U)
3431/*! EEI4 - Enable Error Interrupt 4
3432 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3433 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3434 */
3435#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
3436#define DMA_EEI_EEI5_MASK (0x20U)
3437#define DMA_EEI_EEI5_SHIFT (5U)
3438/*! EEI5 - Enable Error Interrupt 5
3439 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3440 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3441 */
3442#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
3443#define DMA_EEI_EEI6_MASK (0x40U)
3444#define DMA_EEI_EEI6_SHIFT (6U)
3445/*! EEI6 - Enable Error Interrupt 6
3446 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3447 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3448 */
3449#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
3450#define DMA_EEI_EEI7_MASK (0x80U)
3451#define DMA_EEI_EEI7_SHIFT (7U)
3452/*! EEI7 - Enable Error Interrupt 7
3453 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3454 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3455 */
3456#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
3457#define DMA_EEI_EEI8_MASK (0x100U)
3458#define DMA_EEI_EEI8_SHIFT (8U)
3459/*! EEI8 - Enable Error Interrupt 8
3460 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3461 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3462 */
3463#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
3464#define DMA_EEI_EEI9_MASK (0x200U)
3465#define DMA_EEI_EEI9_SHIFT (9U)
3466/*! EEI9 - Enable Error Interrupt 9
3467 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3468 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3469 */
3470#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
3471#define DMA_EEI_EEI10_MASK (0x400U)
3472#define DMA_EEI_EEI10_SHIFT (10U)
3473/*! EEI10 - Enable Error Interrupt 10
3474 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3475 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3476 */
3477#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
3478#define DMA_EEI_EEI11_MASK (0x800U)
3479#define DMA_EEI_EEI11_SHIFT (11U)
3480/*! EEI11 - Enable Error Interrupt 11
3481 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3482 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3483 */
3484#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
3485#define DMA_EEI_EEI12_MASK (0x1000U)
3486#define DMA_EEI_EEI12_SHIFT (12U)
3487/*! EEI12 - Enable Error Interrupt 12
3488 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3489 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3490 */
3491#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
3492#define DMA_EEI_EEI13_MASK (0x2000U)
3493#define DMA_EEI_EEI13_SHIFT (13U)
3494/*! EEI13 - Enable Error Interrupt 13
3495 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3496 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3497 */
3498#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
3499#define DMA_EEI_EEI14_MASK (0x4000U)
3500#define DMA_EEI_EEI14_SHIFT (14U)
3501/*! EEI14 - Enable Error Interrupt 14
3502 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3503 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3504 */
3505#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
3506#define DMA_EEI_EEI15_MASK (0x8000U)
3507#define DMA_EEI_EEI15_SHIFT (15U)
3508/*! EEI15 - Enable Error Interrupt 15
3509 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3510 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3511 */
3512#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
3513#define DMA_EEI_EEI16_MASK (0x10000U)
3514#define DMA_EEI_EEI16_SHIFT (16U)
3515/*! EEI16 - Enable Error Interrupt 16
3516 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3517 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3518 */
3519#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
3520#define DMA_EEI_EEI17_MASK (0x20000U)
3521#define DMA_EEI_EEI17_SHIFT (17U)
3522/*! EEI17 - Enable Error Interrupt 17
3523 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3524 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3525 */
3526#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
3527#define DMA_EEI_EEI18_MASK (0x40000U)
3528#define DMA_EEI_EEI18_SHIFT (18U)
3529/*! EEI18 - Enable Error Interrupt 18
3530 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3531 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3532 */
3533#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
3534#define DMA_EEI_EEI19_MASK (0x80000U)
3535#define DMA_EEI_EEI19_SHIFT (19U)
3536/*! EEI19 - Enable Error Interrupt 19
3537 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3538 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3539 */
3540#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
3541#define DMA_EEI_EEI20_MASK (0x100000U)
3542#define DMA_EEI_EEI20_SHIFT (20U)
3543/*! EEI20 - Enable Error Interrupt 20
3544 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3545 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3546 */
3547#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
3548#define DMA_EEI_EEI21_MASK (0x200000U)
3549#define DMA_EEI_EEI21_SHIFT (21U)
3550/*! EEI21 - Enable Error Interrupt 21
3551 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3552 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3553 */
3554#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
3555#define DMA_EEI_EEI22_MASK (0x400000U)
3556#define DMA_EEI_EEI22_SHIFT (22U)
3557/*! EEI22 - Enable Error Interrupt 22
3558 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3559 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3560 */
3561#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
3562#define DMA_EEI_EEI23_MASK (0x800000U)
3563#define DMA_EEI_EEI23_SHIFT (23U)
3564/*! EEI23 - Enable Error Interrupt 23
3565 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3566 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3567 */
3568#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
3569#define DMA_EEI_EEI24_MASK (0x1000000U)
3570#define DMA_EEI_EEI24_SHIFT (24U)
3571/*! EEI24 - Enable Error Interrupt 24
3572 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3573 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3574 */
3575#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
3576#define DMA_EEI_EEI25_MASK (0x2000000U)
3577#define DMA_EEI_EEI25_SHIFT (25U)
3578/*! EEI25 - Enable Error Interrupt 25
3579 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3580 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3581 */
3582#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
3583#define DMA_EEI_EEI26_MASK (0x4000000U)
3584#define DMA_EEI_EEI26_SHIFT (26U)
3585/*! EEI26 - Enable Error Interrupt 26
3586 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3587 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3588 */
3589#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
3590#define DMA_EEI_EEI27_MASK (0x8000000U)
3591#define DMA_EEI_EEI27_SHIFT (27U)
3592/*! EEI27 - Enable Error Interrupt 27
3593 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3594 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3595 */
3596#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
3597#define DMA_EEI_EEI28_MASK (0x10000000U)
3598#define DMA_EEI_EEI28_SHIFT (28U)
3599/*! EEI28 - Enable Error Interrupt 28
3600 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3601 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3602 */
3603#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
3604#define DMA_EEI_EEI29_MASK (0x20000000U)
3605#define DMA_EEI_EEI29_SHIFT (29U)
3606/*! EEI29 - Enable Error Interrupt 29
3607 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3608 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3609 */
3610#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
3611#define DMA_EEI_EEI30_MASK (0x40000000U)
3612#define DMA_EEI_EEI30_SHIFT (30U)
3613/*! EEI30 - Enable Error Interrupt 30
3614 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3615 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3616 */
3617#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
3618#define DMA_EEI_EEI31_MASK (0x80000000U)
3619#define DMA_EEI_EEI31_SHIFT (31U)
3620/*! EEI31 - Enable Error Interrupt 31
3621 * 0b0..The error signal for corresponding channel does not generate an error interrupt
3622 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
3623 */
3624#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
3625/*! @} */
3626
3627/*! @name CEEI - Clear Enable Error Interrupt Register */
3628/*! @{ */
3629#define DMA_CEEI_CEEI_MASK (0x1FU)
3630#define DMA_CEEI_CEEI_SHIFT (0U)
3631/*! CEEI - Clear Enable Error Interrupt
3632 */
3633#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
3634#define DMA_CEEI_CAEE_MASK (0x40U)
3635#define DMA_CEEI_CAEE_SHIFT (6U)
3636/*! CAEE - Clear All Enable Error Interrupts
3637 * 0b0..Clear only the EEI bit specified in the CEEI field
3638 * 0b1..Clear all bits in EEI
3639 */
3640#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
3641#define DMA_CEEI_NOP_MASK (0x80U)
3642#define DMA_CEEI_NOP_SHIFT (7U)
3643/*! NOP - No Op enable
3644 * 0b0..Normal operation
3645 * 0b1..No operation, ignore the other bits in this register
3646 */
3647#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
3648/*! @} */
3649
3650/*! @name SEEI - Set Enable Error Interrupt Register */
3651/*! @{ */
3652#define DMA_SEEI_SEEI_MASK (0x1FU)
3653#define DMA_SEEI_SEEI_SHIFT (0U)
3654/*! SEEI - Set Enable Error Interrupt
3655 */
3656#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
3657#define DMA_SEEI_SAEE_MASK (0x40U)
3658#define DMA_SEEI_SAEE_SHIFT (6U)
3659/*! SAEE - Sets All Enable Error Interrupts
3660 * 0b0..Set only the EEI bit specified in the SEEI field.
3661 * 0b1..Sets all bits in EEI
3662 */
3663#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
3664#define DMA_SEEI_NOP_MASK (0x80U)
3665#define DMA_SEEI_NOP_SHIFT (7U)
3666/*! NOP - No Op enable
3667 * 0b0..Normal operation
3668 * 0b1..No operation, ignore the other bits in this register
3669 */
3670#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
3671/*! @} */
3672
3673/*! @name CERQ - Clear Enable Request Register */
3674/*! @{ */
3675#define DMA_CERQ_CERQ_MASK (0x1FU)
3676#define DMA_CERQ_CERQ_SHIFT (0U)
3677/*! CERQ - Clear Enable Request
3678 */
3679#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
3680#define DMA_CERQ_CAER_MASK (0x40U)
3681#define DMA_CERQ_CAER_SHIFT (6U)
3682/*! CAER - Clear All Enable Requests
3683 * 0b0..Clear only the ERQ bit specified in the CERQ field
3684 * 0b1..Clear all bits in ERQ
3685 */
3686#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
3687#define DMA_CERQ_NOP_MASK (0x80U)
3688#define DMA_CERQ_NOP_SHIFT (7U)
3689/*! NOP - No Op enable
3690 * 0b0..Normal operation
3691 * 0b1..No operation, ignore the other bits in this register
3692 */
3693#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
3694/*! @} */
3695
3696/*! @name SERQ - Set Enable Request Register */
3697/*! @{ */
3698#define DMA_SERQ_SERQ_MASK (0x1FU)
3699#define DMA_SERQ_SERQ_SHIFT (0U)
3700/*! SERQ - Set Enable Request
3701 */
3702#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
3703#define DMA_SERQ_SAER_MASK (0x40U)
3704#define DMA_SERQ_SAER_SHIFT (6U)
3705/*! SAER - Set All Enable Requests
3706 * 0b0..Set only the ERQ bit specified in the SERQ field
3707 * 0b1..Set all bits in ERQ
3708 */
3709#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
3710#define DMA_SERQ_NOP_MASK (0x80U)
3711#define DMA_SERQ_NOP_SHIFT (7U)
3712/*! NOP - No Op enable
3713 * 0b0..Normal operation
3714 * 0b1..No operation, ignore the other bits in this register
3715 */
3716#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
3717/*! @} */
3718
3719/*! @name CDNE - Clear DONE Status Bit Register */
3720/*! @{ */
3721#define DMA_CDNE_CDNE_MASK (0x1FU)
3722#define DMA_CDNE_CDNE_SHIFT (0U)
3723/*! CDNE - Clear DONE Bit
3724 */
3725#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
3726#define DMA_CDNE_CADN_MASK (0x40U)
3727#define DMA_CDNE_CADN_SHIFT (6U)
3728/*! CADN - Clears All DONE Bits
3729 * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
3730 * 0b1..Clears all bits in TCDn_CSR[DONE]
3731 */
3732#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
3733#define DMA_CDNE_NOP_MASK (0x80U)
3734#define DMA_CDNE_NOP_SHIFT (7U)
3735/*! NOP - No Op enable
3736 * 0b0..Normal operation
3737 * 0b1..No operation, ignore the other bits in this register
3738 */
3739#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
3740/*! @} */
3741
3742/*! @name SSRT - Set START Bit Register */
3743/*! @{ */
3744#define DMA_SSRT_SSRT_MASK (0x1FU)
3745#define DMA_SSRT_SSRT_SHIFT (0U)
3746/*! SSRT - Set START Bit
3747 */
3748#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
3749#define DMA_SSRT_SAST_MASK (0x40U)
3750#define DMA_SSRT_SAST_SHIFT (6U)
3751/*! SAST - Set All START Bits (activates all channels)
3752 * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field
3753 * 0b1..Set all bits in TCDn_CSR[START]
3754 */
3755#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
3756#define DMA_SSRT_NOP_MASK (0x80U)
3757#define DMA_SSRT_NOP_SHIFT (7U)
3758/*! NOP - No Op enable
3759 * 0b0..Normal operation
3760 * 0b1..No operation, ignore the other bits in this register
3761 */
3762#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
3763/*! @} */
3764
3765/*! @name CERR - Clear Error Register */
3766/*! @{ */
3767#define DMA_CERR_CERR_MASK (0x1FU)
3768#define DMA_CERR_CERR_SHIFT (0U)
3769/*! CERR - Clear Error Indicator
3770 */
3771#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
3772#define DMA_CERR_CAEI_MASK (0x40U)
3773#define DMA_CERR_CAEI_SHIFT (6U)
3774/*! CAEI - Clear All Error Indicators
3775 * 0b0..Clear only the ERR bit specified in the CERR field
3776 * 0b1..Clear all bits in ERR
3777 */
3778#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
3779#define DMA_CERR_NOP_MASK (0x80U)
3780#define DMA_CERR_NOP_SHIFT (7U)
3781/*! NOP - No Op enable
3782 * 0b0..Normal operation
3783 * 0b1..No operation, ignore the other bits in this register
3784 */
3785#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
3786/*! @} */
3787
3788/*! @name CINT - Clear Interrupt Request Register */
3789/*! @{ */
3790#define DMA_CINT_CINT_MASK (0x1FU)
3791#define DMA_CINT_CINT_SHIFT (0U)
3792/*! CINT - Clear Interrupt Request
3793 */
3794#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
3795#define DMA_CINT_CAIR_MASK (0x40U)
3796#define DMA_CINT_CAIR_SHIFT (6U)
3797/*! CAIR - Clear All Interrupt Requests
3798 * 0b0..Clear only the INT bit specified in the CINT field
3799 * 0b1..Clear all bits in INT
3800 */
3801#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
3802#define DMA_CINT_NOP_MASK (0x80U)
3803#define DMA_CINT_NOP_SHIFT (7U)
3804/*! NOP - No Op enable
3805 * 0b0..Normal operation
3806 * 0b1..No operation, ignore the other bits in this register
3807 */
3808#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
3809/*! @} */
3810
3811/*! @name INT - Interrupt Request Register */
3812/*! @{ */
3813#define DMA_INT_INT0_MASK (0x1U)
3814#define DMA_INT_INT0_SHIFT (0U)
3815/*! INT0 - Interrupt Request 0
3816 * 0b0..The interrupt request for corresponding channel is cleared
3817 * 0b1..The interrupt request for corresponding channel is active
3818 */
3819#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
3820#define DMA_INT_INT1_MASK (0x2U)
3821#define DMA_INT_INT1_SHIFT (1U)
3822/*! INT1 - Interrupt Request 1
3823 * 0b0..The interrupt request for corresponding channel is cleared
3824 * 0b1..The interrupt request for corresponding channel is active
3825 */
3826#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
3827#define DMA_INT_INT2_MASK (0x4U)
3828#define DMA_INT_INT2_SHIFT (2U)
3829/*! INT2 - Interrupt Request 2
3830 * 0b0..The interrupt request for corresponding channel is cleared
3831 * 0b1..The interrupt request for corresponding channel is active
3832 */
3833#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
3834#define DMA_INT_INT3_MASK (0x8U)
3835#define DMA_INT_INT3_SHIFT (3U)
3836/*! INT3 - Interrupt Request 3
3837 * 0b0..The interrupt request for corresponding channel is cleared
3838 * 0b1..The interrupt request for corresponding channel is active
3839 */
3840#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
3841#define DMA_INT_INT4_MASK (0x10U)
3842#define DMA_INT_INT4_SHIFT (4U)
3843/*! INT4 - Interrupt Request 4
3844 * 0b0..The interrupt request for corresponding channel is cleared
3845 * 0b1..The interrupt request for corresponding channel is active
3846 */
3847#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
3848#define DMA_INT_INT5_MASK (0x20U)
3849#define DMA_INT_INT5_SHIFT (5U)
3850/*! INT5 - Interrupt Request 5
3851 * 0b0..The interrupt request for corresponding channel is cleared
3852 * 0b1..The interrupt request for corresponding channel is active
3853 */
3854#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
3855#define DMA_INT_INT6_MASK (0x40U)
3856#define DMA_INT_INT6_SHIFT (6U)
3857/*! INT6 - Interrupt Request 6
3858 * 0b0..The interrupt request for corresponding channel is cleared
3859 * 0b1..The interrupt request for corresponding channel is active
3860 */
3861#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
3862#define DMA_INT_INT7_MASK (0x80U)
3863#define DMA_INT_INT7_SHIFT (7U)
3864/*! INT7 - Interrupt Request 7
3865 * 0b0..The interrupt request for corresponding channel is cleared
3866 * 0b1..The interrupt request for corresponding channel is active
3867 */
3868#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
3869#define DMA_INT_INT8_MASK (0x100U)
3870#define DMA_INT_INT8_SHIFT (8U)
3871/*! INT8 - Interrupt Request 8
3872 * 0b0..The interrupt request for corresponding channel is cleared
3873 * 0b1..The interrupt request for corresponding channel is active
3874 */
3875#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
3876#define DMA_INT_INT9_MASK (0x200U)
3877#define DMA_INT_INT9_SHIFT (9U)
3878/*! INT9 - Interrupt Request 9
3879 * 0b0..The interrupt request for corresponding channel is cleared
3880 * 0b1..The interrupt request for corresponding channel is active
3881 */
3882#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
3883#define DMA_INT_INT10_MASK (0x400U)
3884#define DMA_INT_INT10_SHIFT (10U)
3885/*! INT10 - Interrupt Request 10
3886 * 0b0..The interrupt request for corresponding channel is cleared
3887 * 0b1..The interrupt request for corresponding channel is active
3888 */
3889#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
3890#define DMA_INT_INT11_MASK (0x800U)
3891#define DMA_INT_INT11_SHIFT (11U)
3892/*! INT11 - Interrupt Request 11
3893 * 0b0..The interrupt request for corresponding channel is cleared
3894 * 0b1..The interrupt request for corresponding channel is active
3895 */
3896#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
3897#define DMA_INT_INT12_MASK (0x1000U)
3898#define DMA_INT_INT12_SHIFT (12U)
3899/*! INT12 - Interrupt Request 12
3900 * 0b0..The interrupt request for corresponding channel is cleared
3901 * 0b1..The interrupt request for corresponding channel is active
3902 */
3903#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
3904#define DMA_INT_INT13_MASK (0x2000U)
3905#define DMA_INT_INT13_SHIFT (13U)
3906/*! INT13 - Interrupt Request 13
3907 * 0b0..The interrupt request for corresponding channel is cleared
3908 * 0b1..The interrupt request for corresponding channel is active
3909 */
3910#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
3911#define DMA_INT_INT14_MASK (0x4000U)
3912#define DMA_INT_INT14_SHIFT (14U)
3913/*! INT14 - Interrupt Request 14
3914 * 0b0..The interrupt request for corresponding channel is cleared
3915 * 0b1..The interrupt request for corresponding channel is active
3916 */
3917#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
3918#define DMA_INT_INT15_MASK (0x8000U)
3919#define DMA_INT_INT15_SHIFT (15U)
3920/*! INT15 - Interrupt Request 15
3921 * 0b0..The interrupt request for corresponding channel is cleared
3922 * 0b1..The interrupt request for corresponding channel is active
3923 */
3924#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
3925#define DMA_INT_INT16_MASK (0x10000U)
3926#define DMA_INT_INT16_SHIFT (16U)
3927/*! INT16 - Interrupt Request 16
3928 * 0b0..The interrupt request for corresponding channel is cleared
3929 * 0b1..The interrupt request for corresponding channel is active
3930 */
3931#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
3932#define DMA_INT_INT17_MASK (0x20000U)
3933#define DMA_INT_INT17_SHIFT (17U)
3934/*! INT17 - Interrupt Request 17
3935 * 0b0..The interrupt request for corresponding channel is cleared
3936 * 0b1..The interrupt request for corresponding channel is active
3937 */
3938#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
3939#define DMA_INT_INT18_MASK (0x40000U)
3940#define DMA_INT_INT18_SHIFT (18U)
3941/*! INT18 - Interrupt Request 18
3942 * 0b0..The interrupt request for corresponding channel is cleared
3943 * 0b1..The interrupt request for corresponding channel is active
3944 */
3945#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
3946#define DMA_INT_INT19_MASK (0x80000U)
3947#define DMA_INT_INT19_SHIFT (19U)
3948/*! INT19 - Interrupt Request 19
3949 * 0b0..The interrupt request for corresponding channel is cleared
3950 * 0b1..The interrupt request for corresponding channel is active
3951 */
3952#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
3953#define DMA_INT_INT20_MASK (0x100000U)
3954#define DMA_INT_INT20_SHIFT (20U)
3955/*! INT20 - Interrupt Request 20
3956 * 0b0..The interrupt request for corresponding channel is cleared
3957 * 0b1..The interrupt request for corresponding channel is active
3958 */
3959#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
3960#define DMA_INT_INT21_MASK (0x200000U)
3961#define DMA_INT_INT21_SHIFT (21U)
3962/*! INT21 - Interrupt Request 21
3963 * 0b0..The interrupt request for corresponding channel is cleared
3964 * 0b1..The interrupt request for corresponding channel is active
3965 */
3966#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
3967#define DMA_INT_INT22_MASK (0x400000U)
3968#define DMA_INT_INT22_SHIFT (22U)
3969/*! INT22 - Interrupt Request 22
3970 * 0b0..The interrupt request for corresponding channel is cleared
3971 * 0b1..The interrupt request for corresponding channel is active
3972 */
3973#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
3974#define DMA_INT_INT23_MASK (0x800000U)
3975#define DMA_INT_INT23_SHIFT (23U)
3976/*! INT23 - Interrupt Request 23
3977 * 0b0..The interrupt request for corresponding channel is cleared
3978 * 0b1..The interrupt request for corresponding channel is active
3979 */
3980#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
3981#define DMA_INT_INT24_MASK (0x1000000U)
3982#define DMA_INT_INT24_SHIFT (24U)
3983/*! INT24 - Interrupt Request 24
3984 * 0b0..The interrupt request for corresponding channel is cleared
3985 * 0b1..The interrupt request for corresponding channel is active
3986 */
3987#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
3988#define DMA_INT_INT25_MASK (0x2000000U)
3989#define DMA_INT_INT25_SHIFT (25U)
3990/*! INT25 - Interrupt Request 25
3991 * 0b0..The interrupt request for corresponding channel is cleared
3992 * 0b1..The interrupt request for corresponding channel is active
3993 */
3994#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
3995#define DMA_INT_INT26_MASK (0x4000000U)
3996#define DMA_INT_INT26_SHIFT (26U)
3997/*! INT26 - Interrupt Request 26
3998 * 0b0..The interrupt request for corresponding channel is cleared
3999 * 0b1..The interrupt request for corresponding channel is active
4000 */
4001#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
4002#define DMA_INT_INT27_MASK (0x8000000U)
4003#define DMA_INT_INT27_SHIFT (27U)
4004/*! INT27 - Interrupt Request 27
4005 * 0b0..The interrupt request for corresponding channel is cleared
4006 * 0b1..The interrupt request for corresponding channel is active
4007 */
4008#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
4009#define DMA_INT_INT28_MASK (0x10000000U)
4010#define DMA_INT_INT28_SHIFT (28U)
4011/*! INT28 - Interrupt Request 28
4012 * 0b0..The interrupt request for corresponding channel is cleared
4013 * 0b1..The interrupt request for corresponding channel is active
4014 */
4015#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
4016#define DMA_INT_INT29_MASK (0x20000000U)
4017#define DMA_INT_INT29_SHIFT (29U)
4018/*! INT29 - Interrupt Request 29
4019 * 0b0..The interrupt request for corresponding channel is cleared
4020 * 0b1..The interrupt request for corresponding channel is active
4021 */
4022#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
4023#define DMA_INT_INT30_MASK (0x40000000U)
4024#define DMA_INT_INT30_SHIFT (30U)
4025/*! INT30 - Interrupt Request 30
4026 * 0b0..The interrupt request for corresponding channel is cleared
4027 * 0b1..The interrupt request for corresponding channel is active
4028 */
4029#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
4030#define DMA_INT_INT31_MASK (0x80000000U)
4031#define DMA_INT_INT31_SHIFT (31U)
4032/*! INT31 - Interrupt Request 31
4033 * 0b0..The interrupt request for corresponding channel is cleared
4034 * 0b1..The interrupt request for corresponding channel is active
4035 */
4036#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
4037/*! @} */
4038
4039/*! @name ERR - Error Register */
4040/*! @{ */
4041#define DMA_ERR_ERR0_MASK (0x1U)
4042#define DMA_ERR_ERR0_SHIFT (0U)
4043/*! ERR0 - Error In Channel 0
4044 * 0b0..An error in this channel has not occurred
4045 * 0b1..An error in this channel has occurred
4046 */
4047#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
4048#define DMA_ERR_ERR1_MASK (0x2U)
4049#define DMA_ERR_ERR1_SHIFT (1U)
4050/*! ERR1 - Error In Channel 1
4051 * 0b0..An error in this channel has not occurred
4052 * 0b1..An error in this channel has occurred
4053 */
4054#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
4055#define DMA_ERR_ERR2_MASK (0x4U)
4056#define DMA_ERR_ERR2_SHIFT (2U)
4057/*! ERR2 - Error In Channel 2
4058 * 0b0..An error in this channel has not occurred
4059 * 0b1..An error in this channel has occurred
4060 */
4061#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
4062#define DMA_ERR_ERR3_MASK (0x8U)
4063#define DMA_ERR_ERR3_SHIFT (3U)
4064/*! ERR3 - Error In Channel 3
4065 * 0b0..An error in this channel has not occurred
4066 * 0b1..An error in this channel has occurred
4067 */
4068#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
4069#define DMA_ERR_ERR4_MASK (0x10U)
4070#define DMA_ERR_ERR4_SHIFT (4U)
4071/*! ERR4 - Error In Channel 4
4072 * 0b0..An error in this channel has not occurred
4073 * 0b1..An error in this channel has occurred
4074 */
4075#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
4076#define DMA_ERR_ERR5_MASK (0x20U)
4077#define DMA_ERR_ERR5_SHIFT (5U)
4078/*! ERR5 - Error In Channel 5
4079 * 0b0..An error in this channel has not occurred
4080 * 0b1..An error in this channel has occurred
4081 */
4082#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
4083#define DMA_ERR_ERR6_MASK (0x40U)
4084#define DMA_ERR_ERR6_SHIFT (6U)
4085/*! ERR6 - Error In Channel 6
4086 * 0b0..An error in this channel has not occurred
4087 * 0b1..An error in this channel has occurred
4088 */
4089#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
4090#define DMA_ERR_ERR7_MASK (0x80U)
4091#define DMA_ERR_ERR7_SHIFT (7U)
4092/*! ERR7 - Error In Channel 7
4093 * 0b0..An error in this channel has not occurred
4094 * 0b1..An error in this channel has occurred
4095 */
4096#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
4097#define DMA_ERR_ERR8_MASK (0x100U)
4098#define DMA_ERR_ERR8_SHIFT (8U)
4099/*! ERR8 - Error In Channel 8
4100 * 0b0..An error in this channel has not occurred
4101 * 0b1..An error in this channel has occurred
4102 */
4103#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
4104#define DMA_ERR_ERR9_MASK (0x200U)
4105#define DMA_ERR_ERR9_SHIFT (9U)
4106/*! ERR9 - Error In Channel 9
4107 * 0b0..An error in this channel has not occurred
4108 * 0b1..An error in this channel has occurred
4109 */
4110#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
4111#define DMA_ERR_ERR10_MASK (0x400U)
4112#define DMA_ERR_ERR10_SHIFT (10U)
4113/*! ERR10 - Error In Channel 10
4114 * 0b0..An error in this channel has not occurred
4115 * 0b1..An error in this channel has occurred
4116 */
4117#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
4118#define DMA_ERR_ERR11_MASK (0x800U)
4119#define DMA_ERR_ERR11_SHIFT (11U)
4120/*! ERR11 - Error In Channel 11
4121 * 0b0..An error in this channel has not occurred
4122 * 0b1..An error in this channel has occurred
4123 */
4124#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
4125#define DMA_ERR_ERR12_MASK (0x1000U)
4126#define DMA_ERR_ERR12_SHIFT (12U)
4127/*! ERR12 - Error In Channel 12
4128 * 0b0..An error in this channel has not occurred
4129 * 0b1..An error in this channel has occurred
4130 */
4131#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
4132#define DMA_ERR_ERR13_MASK (0x2000U)
4133#define DMA_ERR_ERR13_SHIFT (13U)
4134/*! ERR13 - Error In Channel 13
4135 * 0b0..An error in this channel has not occurred
4136 * 0b1..An error in this channel has occurred
4137 */
4138#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
4139#define DMA_ERR_ERR14_MASK (0x4000U)
4140#define DMA_ERR_ERR14_SHIFT (14U)
4141/*! ERR14 - Error In Channel 14
4142 * 0b0..An error in this channel has not occurred
4143 * 0b1..An error in this channel has occurred
4144 */
4145#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
4146#define DMA_ERR_ERR15_MASK (0x8000U)
4147#define DMA_ERR_ERR15_SHIFT (15U)
4148/*! ERR15 - Error In Channel 15
4149 * 0b0..An error in this channel has not occurred
4150 * 0b1..An error in this channel has occurred
4151 */
4152#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
4153#define DMA_ERR_ERR16_MASK (0x10000U)
4154#define DMA_ERR_ERR16_SHIFT (16U)
4155/*! ERR16 - Error In Channel 16
4156 * 0b0..An error in this channel has not occurred
4157 * 0b1..An error in this channel has occurred
4158 */
4159#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
4160#define DMA_ERR_ERR17_MASK (0x20000U)
4161#define DMA_ERR_ERR17_SHIFT (17U)
4162/*! ERR17 - Error In Channel 17
4163 * 0b0..An error in this channel has not occurred
4164 * 0b1..An error in this channel has occurred
4165 */
4166#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
4167#define DMA_ERR_ERR18_MASK (0x40000U)
4168#define DMA_ERR_ERR18_SHIFT (18U)
4169/*! ERR18 - Error In Channel 18
4170 * 0b0..An error in this channel has not occurred
4171 * 0b1..An error in this channel has occurred
4172 */
4173#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
4174#define DMA_ERR_ERR19_MASK (0x80000U)
4175#define DMA_ERR_ERR19_SHIFT (19U)
4176/*! ERR19 - Error In Channel 19
4177 * 0b0..An error in this channel has not occurred
4178 * 0b1..An error in this channel has occurred
4179 */
4180#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
4181#define DMA_ERR_ERR20_MASK (0x100000U)
4182#define DMA_ERR_ERR20_SHIFT (20U)
4183/*! ERR20 - Error In Channel 20
4184 * 0b0..An error in this channel has not occurred
4185 * 0b1..An error in this channel has occurred
4186 */
4187#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
4188#define DMA_ERR_ERR21_MASK (0x200000U)
4189#define DMA_ERR_ERR21_SHIFT (21U)
4190/*! ERR21 - Error In Channel 21
4191 * 0b0..An error in this channel has not occurred
4192 * 0b1..An error in this channel has occurred
4193 */
4194#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
4195#define DMA_ERR_ERR22_MASK (0x400000U)
4196#define DMA_ERR_ERR22_SHIFT (22U)
4197/*! ERR22 - Error In Channel 22
4198 * 0b0..An error in this channel has not occurred
4199 * 0b1..An error in this channel has occurred
4200 */
4201#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
4202#define DMA_ERR_ERR23_MASK (0x800000U)
4203#define DMA_ERR_ERR23_SHIFT (23U)
4204/*! ERR23 - Error In Channel 23
4205 * 0b0..An error in this channel has not occurred
4206 * 0b1..An error in this channel has occurred
4207 */
4208#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
4209#define DMA_ERR_ERR24_MASK (0x1000000U)
4210#define DMA_ERR_ERR24_SHIFT (24U)
4211/*! ERR24 - Error In Channel 24
4212 * 0b0..An error in this channel has not occurred
4213 * 0b1..An error in this channel has occurred
4214 */
4215#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
4216#define DMA_ERR_ERR25_MASK (0x2000000U)
4217#define DMA_ERR_ERR25_SHIFT (25U)
4218/*! ERR25 - Error In Channel 25
4219 * 0b0..An error in this channel has not occurred
4220 * 0b1..An error in this channel has occurred
4221 */
4222#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
4223#define DMA_ERR_ERR26_MASK (0x4000000U)
4224#define DMA_ERR_ERR26_SHIFT (26U)
4225/*! ERR26 - Error In Channel 26
4226 * 0b0..An error in this channel has not occurred
4227 * 0b1..An error in this channel has occurred
4228 */
4229#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
4230#define DMA_ERR_ERR27_MASK (0x8000000U)
4231#define DMA_ERR_ERR27_SHIFT (27U)
4232/*! ERR27 - Error In Channel 27
4233 * 0b0..An error in this channel has not occurred
4234 * 0b1..An error in this channel has occurred
4235 */
4236#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
4237#define DMA_ERR_ERR28_MASK (0x10000000U)
4238#define DMA_ERR_ERR28_SHIFT (28U)
4239/*! ERR28 - Error In Channel 28
4240 * 0b0..An error in this channel has not occurred
4241 * 0b1..An error in this channel has occurred
4242 */
4243#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
4244#define DMA_ERR_ERR29_MASK (0x20000000U)
4245#define DMA_ERR_ERR29_SHIFT (29U)
4246/*! ERR29 - Error In Channel 29
4247 * 0b0..An error in this channel has not occurred
4248 * 0b1..An error in this channel has occurred
4249 */
4250#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
4251#define DMA_ERR_ERR30_MASK (0x40000000U)
4252#define DMA_ERR_ERR30_SHIFT (30U)
4253/*! ERR30 - Error In Channel 30
4254 * 0b0..An error in this channel has not occurred
4255 * 0b1..An error in this channel has occurred
4256 */
4257#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
4258#define DMA_ERR_ERR31_MASK (0x80000000U)
4259#define DMA_ERR_ERR31_SHIFT (31U)
4260/*! ERR31 - Error In Channel 31
4261 * 0b0..An error in this channel has not occurred
4262 * 0b1..An error in this channel has occurred
4263 */
4264#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
4265/*! @} */
4266
4267/*! @name HRS - Hardware Request Status Register */
4268/*! @{ */
4269#define DMA_HRS_HRS0_MASK (0x1U)
4270#define DMA_HRS_HRS0_SHIFT (0U)
4271/*! HRS0 - Hardware Request Status Channel 0
4272 * 0b0..A hardware service request for channel 0 is not present
4273 * 0b1..A hardware service request for channel 0 is present
4274 */
4275#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
4276#define DMA_HRS_HRS1_MASK (0x2U)
4277#define DMA_HRS_HRS1_SHIFT (1U)
4278/*! HRS1 - Hardware Request Status Channel 1
4279 * 0b0..A hardware service request for channel 1 is not present
4280 * 0b1..A hardware service request for channel 1 is present
4281 */
4282#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
4283#define DMA_HRS_HRS2_MASK (0x4U)
4284#define DMA_HRS_HRS2_SHIFT (2U)
4285/*! HRS2 - Hardware Request Status Channel 2
4286 * 0b0..A hardware service request for channel 2 is not present
4287 * 0b1..A hardware service request for channel 2 is present
4288 */
4289#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
4290#define DMA_HRS_HRS3_MASK (0x8U)
4291#define DMA_HRS_HRS3_SHIFT (3U)
4292/*! HRS3 - Hardware Request Status Channel 3
4293 * 0b0..A hardware service request for channel 3 is not present
4294 * 0b1..A hardware service request for channel 3 is present
4295 */
4296#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
4297#define DMA_HRS_HRS4_MASK (0x10U)
4298#define DMA_HRS_HRS4_SHIFT (4U)
4299/*! HRS4 - Hardware Request Status Channel 4
4300 * 0b0..A hardware service request for channel 4 is not present
4301 * 0b1..A hardware service request for channel 4 is present
4302 */
4303#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
4304#define DMA_HRS_HRS5_MASK (0x20U)
4305#define DMA_HRS_HRS5_SHIFT (5U)
4306/*! HRS5 - Hardware Request Status Channel 5
4307 * 0b0..A hardware service request for channel 5 is not present
4308 * 0b1..A hardware service request for channel 5 is present
4309 */
4310#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
4311#define DMA_HRS_HRS6_MASK (0x40U)
4312#define DMA_HRS_HRS6_SHIFT (6U)
4313/*! HRS6 - Hardware Request Status Channel 6
4314 * 0b0..A hardware service request for channel 6 is not present
4315 * 0b1..A hardware service request for channel 6 is present
4316 */
4317#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
4318#define DMA_HRS_HRS7_MASK (0x80U)
4319#define DMA_HRS_HRS7_SHIFT (7U)
4320/*! HRS7 - Hardware Request Status Channel 7
4321 * 0b0..A hardware service request for channel 7 is not present
4322 * 0b1..A hardware service request for channel 7 is present
4323 */
4324#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
4325#define DMA_HRS_HRS8_MASK (0x100U)
4326#define DMA_HRS_HRS8_SHIFT (8U)
4327/*! HRS8 - Hardware Request Status Channel 8
4328 * 0b0..A hardware service request for channel 8 is not present
4329 * 0b1..A hardware service request for channel 8 is present
4330 */
4331#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
4332#define DMA_HRS_HRS9_MASK (0x200U)
4333#define DMA_HRS_HRS9_SHIFT (9U)
4334/*! HRS9 - Hardware Request Status Channel 9
4335 * 0b0..A hardware service request for channel 9 is not present
4336 * 0b1..A hardware service request for channel 9 is present
4337 */
4338#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
4339#define DMA_HRS_HRS10_MASK (0x400U)
4340#define DMA_HRS_HRS10_SHIFT (10U)
4341/*! HRS10 - Hardware Request Status Channel 10
4342 * 0b0..A hardware service request for channel 10 is not present
4343 * 0b1..A hardware service request for channel 10 is present
4344 */
4345#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
4346#define DMA_HRS_HRS11_MASK (0x800U)
4347#define DMA_HRS_HRS11_SHIFT (11U)
4348/*! HRS11 - Hardware Request Status Channel 11
4349 * 0b0..A hardware service request for channel 11 is not present
4350 * 0b1..A hardware service request for channel 11 is present
4351 */
4352#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
4353#define DMA_HRS_HRS12_MASK (0x1000U)
4354#define DMA_HRS_HRS12_SHIFT (12U)
4355/*! HRS12 - Hardware Request Status Channel 12
4356 * 0b0..A hardware service request for channel 12 is not present
4357 * 0b1..A hardware service request for channel 12 is present
4358 */
4359#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
4360#define DMA_HRS_HRS13_MASK (0x2000U)
4361#define DMA_HRS_HRS13_SHIFT (13U)
4362/*! HRS13 - Hardware Request Status Channel 13
4363 * 0b0..A hardware service request for channel 13 is not present
4364 * 0b1..A hardware service request for channel 13 is present
4365 */
4366#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
4367#define DMA_HRS_HRS14_MASK (0x4000U)
4368#define DMA_HRS_HRS14_SHIFT (14U)
4369/*! HRS14 - Hardware Request Status Channel 14
4370 * 0b0..A hardware service request for channel 14 is not present
4371 * 0b1..A hardware service request for channel 14 is present
4372 */
4373#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
4374#define DMA_HRS_HRS15_MASK (0x8000U)
4375#define DMA_HRS_HRS15_SHIFT (15U)
4376/*! HRS15 - Hardware Request Status Channel 15
4377 * 0b0..A hardware service request for channel 15 is not present
4378 * 0b1..A hardware service request for channel 15 is present
4379 */
4380#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
4381#define DMA_HRS_HRS16_MASK (0x10000U)
4382#define DMA_HRS_HRS16_SHIFT (16U)
4383/*! HRS16 - Hardware Request Status Channel 16
4384 * 0b0..A hardware service request for channel 16 is not present
4385 * 0b1..A hardware service request for channel 16 is present
4386 */
4387#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
4388#define DMA_HRS_HRS17_MASK (0x20000U)
4389#define DMA_HRS_HRS17_SHIFT (17U)
4390/*! HRS17 - Hardware Request Status Channel 17
4391 * 0b0..A hardware service request for channel 17 is not present
4392 * 0b1..A hardware service request for channel 17 is present
4393 */
4394#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
4395#define DMA_HRS_HRS18_MASK (0x40000U)
4396#define DMA_HRS_HRS18_SHIFT (18U)
4397/*! HRS18 - Hardware Request Status Channel 18
4398 * 0b0..A hardware service request for channel 18 is not present
4399 * 0b1..A hardware service request for channel 18 is present
4400 */
4401#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
4402#define DMA_HRS_HRS19_MASK (0x80000U)
4403#define DMA_HRS_HRS19_SHIFT (19U)
4404/*! HRS19 - Hardware Request Status Channel 19
4405 * 0b0..A hardware service request for channel 19 is not present
4406 * 0b1..A hardware service request for channel 19 is present
4407 */
4408#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
4409#define DMA_HRS_HRS20_MASK (0x100000U)
4410#define DMA_HRS_HRS20_SHIFT (20U)
4411/*! HRS20 - Hardware Request Status Channel 20
4412 * 0b0..A hardware service request for channel 20 is not present
4413 * 0b1..A hardware service request for channel 20 is present
4414 */
4415#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
4416#define DMA_HRS_HRS21_MASK (0x200000U)
4417#define DMA_HRS_HRS21_SHIFT (21U)
4418/*! HRS21 - Hardware Request Status Channel 21
4419 * 0b0..A hardware service request for channel 21 is not present
4420 * 0b1..A hardware service request for channel 21 is present
4421 */
4422#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
4423#define DMA_HRS_HRS22_MASK (0x400000U)
4424#define DMA_HRS_HRS22_SHIFT (22U)
4425/*! HRS22 - Hardware Request Status Channel 22
4426 * 0b0..A hardware service request for channel 22 is not present
4427 * 0b1..A hardware service request for channel 22 is present
4428 */
4429#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
4430#define DMA_HRS_HRS23_MASK (0x800000U)
4431#define DMA_HRS_HRS23_SHIFT (23U)
4432/*! HRS23 - Hardware Request Status Channel 23
4433 * 0b0..A hardware service request for channel 23 is not present
4434 * 0b1..A hardware service request for channel 23 is present
4435 */
4436#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
4437#define DMA_HRS_HRS24_MASK (0x1000000U)
4438#define DMA_HRS_HRS24_SHIFT (24U)
4439/*! HRS24 - Hardware Request Status Channel 24
4440 * 0b0..A hardware service request for channel 24 is not present
4441 * 0b1..A hardware service request for channel 24 is present
4442 */
4443#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
4444#define DMA_HRS_HRS25_MASK (0x2000000U)
4445#define DMA_HRS_HRS25_SHIFT (25U)
4446/*! HRS25 - Hardware Request Status Channel 25
4447 * 0b0..A hardware service request for channel 25 is not present
4448 * 0b1..A hardware service request for channel 25 is present
4449 */
4450#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
4451#define DMA_HRS_HRS26_MASK (0x4000000U)
4452#define DMA_HRS_HRS26_SHIFT (26U)
4453/*! HRS26 - Hardware Request Status Channel 26
4454 * 0b0..A hardware service request for channel 26 is not present
4455 * 0b1..A hardware service request for channel 26 is present
4456 */
4457#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
4458#define DMA_HRS_HRS27_MASK (0x8000000U)
4459#define DMA_HRS_HRS27_SHIFT (27U)
4460/*! HRS27 - Hardware Request Status Channel 27
4461 * 0b0..A hardware service request for channel 27 is not present
4462 * 0b1..A hardware service request for channel 27 is present
4463 */
4464#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
4465#define DMA_HRS_HRS28_MASK (0x10000000U)
4466#define DMA_HRS_HRS28_SHIFT (28U)
4467/*! HRS28 - Hardware Request Status Channel 28
4468 * 0b0..A hardware service request for channel 28 is not present
4469 * 0b1..A hardware service request for channel 28 is present
4470 */
4471#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
4472#define DMA_HRS_HRS29_MASK (0x20000000U)
4473#define DMA_HRS_HRS29_SHIFT (29U)
4474/*! HRS29 - Hardware Request Status Channel 29
4475 * 0b0..A hardware service request for channel 29 is not preset
4476 * 0b1..A hardware service request for channel 29 is present
4477 */
4478#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
4479#define DMA_HRS_HRS30_MASK (0x40000000U)
4480#define DMA_HRS_HRS30_SHIFT (30U)
4481/*! HRS30 - Hardware Request Status Channel 30
4482 * 0b0..A hardware service request for channel 30 is not present
4483 * 0b1..A hardware service request for channel 30 is present
4484 */
4485#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
4486#define DMA_HRS_HRS31_MASK (0x80000000U)
4487#define DMA_HRS_HRS31_SHIFT (31U)
4488/*! HRS31 - Hardware Request Status Channel 31
4489 * 0b0..A hardware service request for channel 31 is not present
4490 * 0b1..A hardware service request for channel 31 is present
4491 */
4492#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
4493/*! @} */
4494
4495/*! @name EARS - Enable Asynchronous Request in Stop Register */
4496/*! @{ */
4497#define DMA_EARS_EDREQ_0_MASK (0x1U)
4498#define DMA_EARS_EDREQ_0_SHIFT (0U)
4499/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0.
4500 * 0b0..Disable asynchronous DMA request for channel 0.
4501 * 0b1..Enable asynchronous DMA request for channel 0.
4502 */
4503#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
4504#define DMA_EARS_EDREQ_1_MASK (0x2U)
4505#define DMA_EARS_EDREQ_1_SHIFT (1U)
4506/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1.
4507 * 0b0..Disable asynchronous DMA request for channel 1
4508 * 0b1..Enable asynchronous DMA request for channel 1.
4509 */
4510#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
4511#define DMA_EARS_EDREQ_2_MASK (0x4U)
4512#define DMA_EARS_EDREQ_2_SHIFT (2U)
4513/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2.
4514 * 0b0..Disable asynchronous DMA request for channel 2.
4515 * 0b1..Enable asynchronous DMA request for channel 2.
4516 */
4517#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
4518#define DMA_EARS_EDREQ_3_MASK (0x8U)
4519#define DMA_EARS_EDREQ_3_SHIFT (3U)
4520/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3.
4521 * 0b0..Disable asynchronous DMA request for channel 3.
4522 * 0b1..Enable asynchronous DMA request for channel 3.
4523 */
4524#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
4525#define DMA_EARS_EDREQ_4_MASK (0x10U)
4526#define DMA_EARS_EDREQ_4_SHIFT (4U)
4527/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4
4528 * 0b0..Disable asynchronous DMA request for channel 4.
4529 * 0b1..Enable asynchronous DMA request for channel 4.
4530 */
4531#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
4532#define DMA_EARS_EDREQ_5_MASK (0x20U)
4533#define DMA_EARS_EDREQ_5_SHIFT (5U)
4534/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5
4535 * 0b0..Disable asynchronous DMA request for channel 5.
4536 * 0b1..Enable asynchronous DMA request for channel 5.
4537 */
4538#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
4539#define DMA_EARS_EDREQ_6_MASK (0x40U)
4540#define DMA_EARS_EDREQ_6_SHIFT (6U)
4541/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6
4542 * 0b0..Disable asynchronous DMA request for channel 6.
4543 * 0b1..Enable asynchronous DMA request for channel 6.
4544 */
4545#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
4546#define DMA_EARS_EDREQ_7_MASK (0x80U)
4547#define DMA_EARS_EDREQ_7_SHIFT (7U)
4548/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7
4549 * 0b0..Disable asynchronous DMA request for channel 7.
4550 * 0b1..Enable asynchronous DMA request for channel 7.
4551 */
4552#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
4553#define DMA_EARS_EDREQ_8_MASK (0x100U)
4554#define DMA_EARS_EDREQ_8_SHIFT (8U)
4555/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8
4556 * 0b0..Disable asynchronous DMA request for channel 8.
4557 * 0b1..Enable asynchronous DMA request for channel 8.
4558 */
4559#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
4560#define DMA_EARS_EDREQ_9_MASK (0x200U)
4561#define DMA_EARS_EDREQ_9_SHIFT (9U)
4562/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9
4563 * 0b0..Disable asynchronous DMA request for channel 9.
4564 * 0b1..Enable asynchronous DMA request for channel 9.
4565 */
4566#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
4567#define DMA_EARS_EDREQ_10_MASK (0x400U)
4568#define DMA_EARS_EDREQ_10_SHIFT (10U)
4569/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10
4570 * 0b0..Disable asynchronous DMA request for channel 10.
4571 * 0b1..Enable asynchronous DMA request for channel 10.
4572 */
4573#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
4574#define DMA_EARS_EDREQ_11_MASK (0x800U)
4575#define DMA_EARS_EDREQ_11_SHIFT (11U)
4576/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11
4577 * 0b0..Disable asynchronous DMA request for channel 11.
4578 * 0b1..Enable asynchronous DMA request for channel 11.
4579 */
4580#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
4581#define DMA_EARS_EDREQ_12_MASK (0x1000U)
4582#define DMA_EARS_EDREQ_12_SHIFT (12U)
4583/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12
4584 * 0b0..Disable asynchronous DMA request for channel 12.
4585 * 0b1..Enable asynchronous DMA request for channel 12.
4586 */
4587#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
4588#define DMA_EARS_EDREQ_13_MASK (0x2000U)
4589#define DMA_EARS_EDREQ_13_SHIFT (13U)
4590/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13
4591 * 0b0..Disable asynchronous DMA request for channel 13.
4592 * 0b1..Enable asynchronous DMA request for channel 13.
4593 */
4594#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
4595#define DMA_EARS_EDREQ_14_MASK (0x4000U)
4596#define DMA_EARS_EDREQ_14_SHIFT (14U)
4597/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14
4598 * 0b0..Disable asynchronous DMA request for channel 14.
4599 * 0b1..Enable asynchronous DMA request for channel 14.
4600 */
4601#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
4602#define DMA_EARS_EDREQ_15_MASK (0x8000U)
4603#define DMA_EARS_EDREQ_15_SHIFT (15U)
4604/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15
4605 * 0b0..Disable asynchronous DMA request for channel 15.
4606 * 0b1..Enable asynchronous DMA request for channel 15.
4607 */
4608#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
4609#define DMA_EARS_EDREQ_16_MASK (0x10000U)
4610#define DMA_EARS_EDREQ_16_SHIFT (16U)
4611/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16
4612 * 0b0..Disable asynchronous DMA request for channel 16
4613 * 0b1..Enable asynchronous DMA request for channel 16
4614 */
4615#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
4616#define DMA_EARS_EDREQ_17_MASK (0x20000U)
4617#define DMA_EARS_EDREQ_17_SHIFT (17U)
4618/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17
4619 * 0b0..Disable asynchronous DMA request for channel 17
4620 * 0b1..Enable asynchronous DMA request for channel 17
4621 */
4622#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
4623#define DMA_EARS_EDREQ_18_MASK (0x40000U)
4624#define DMA_EARS_EDREQ_18_SHIFT (18U)
4625/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18
4626 * 0b0..Disable asynchronous DMA request for channel 18
4627 * 0b1..Enable asynchronous DMA request for channel 18
4628 */
4629#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
4630#define DMA_EARS_EDREQ_19_MASK (0x80000U)
4631#define DMA_EARS_EDREQ_19_SHIFT (19U)
4632/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19
4633 * 0b0..Disable asynchronous DMA request for channel 19
4634 * 0b1..Enable asynchronous DMA request for channel 19
4635 */
4636#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
4637#define DMA_EARS_EDREQ_20_MASK (0x100000U)
4638#define DMA_EARS_EDREQ_20_SHIFT (20U)
4639/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20
4640 * 0b0..Disable asynchronous DMA request for channel 20
4641 * 0b1..Enable asynchronous DMA request for channel 20
4642 */
4643#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
4644#define DMA_EARS_EDREQ_21_MASK (0x200000U)
4645#define DMA_EARS_EDREQ_21_SHIFT (21U)
4646/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21
4647 * 0b0..Disable asynchronous DMA request for channel 21
4648 * 0b1..Enable asynchronous DMA request for channel 21
4649 */
4650#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
4651#define DMA_EARS_EDREQ_22_MASK (0x400000U)
4652#define DMA_EARS_EDREQ_22_SHIFT (22U)
4653/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22
4654 * 0b0..Disable asynchronous DMA request for channel 22
4655 * 0b1..Enable asynchronous DMA request for channel 22
4656 */
4657#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
4658#define DMA_EARS_EDREQ_23_MASK (0x800000U)
4659#define DMA_EARS_EDREQ_23_SHIFT (23U)
4660/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23
4661 * 0b0..Disable asynchronous DMA request for channel 23
4662 * 0b1..Enable asynchronous DMA request for channel 23
4663 */
4664#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
4665#define DMA_EARS_EDREQ_24_MASK (0x1000000U)
4666#define DMA_EARS_EDREQ_24_SHIFT (24U)
4667/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24
4668 * 0b0..Disable asynchronous DMA request for channel 24
4669 * 0b1..Enable asynchronous DMA request for channel 24
4670 */
4671#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
4672#define DMA_EARS_EDREQ_25_MASK (0x2000000U)
4673#define DMA_EARS_EDREQ_25_SHIFT (25U)
4674/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25
4675 * 0b0..Disable asynchronous DMA request for channel 25
4676 * 0b1..Enable asynchronous DMA request for channel 25
4677 */
4678#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
4679#define DMA_EARS_EDREQ_26_MASK (0x4000000U)
4680#define DMA_EARS_EDREQ_26_SHIFT (26U)
4681/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26
4682 * 0b0..Disable asynchronous DMA request for channel 26
4683 * 0b1..Enable asynchronous DMA request for channel 26
4684 */
4685#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
4686#define DMA_EARS_EDREQ_27_MASK (0x8000000U)
4687#define DMA_EARS_EDREQ_27_SHIFT (27U)
4688/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27
4689 * 0b0..Disable asynchronous DMA request for channel 27
4690 * 0b1..Enable asynchronous DMA request for channel 27
4691 */
4692#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
4693#define DMA_EARS_EDREQ_28_MASK (0x10000000U)
4694#define DMA_EARS_EDREQ_28_SHIFT (28U)
4695/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28
4696 * 0b0..Disable asynchronous DMA request for channel 28
4697 * 0b1..Enable asynchronous DMA request for channel 28
4698 */
4699#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
4700#define DMA_EARS_EDREQ_29_MASK (0x20000000U)
4701#define DMA_EARS_EDREQ_29_SHIFT (29U)
4702/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29
4703 * 0b0..Disable asynchronous DMA request for channel 29
4704 * 0b1..Enable asynchronous DMA request for channel 29
4705 */
4706#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
4707#define DMA_EARS_EDREQ_30_MASK (0x40000000U)
4708#define DMA_EARS_EDREQ_30_SHIFT (30U)
4709/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30
4710 * 0b0..Disable asynchronous DMA request for channel 30
4711 * 0b1..Enable asynchronous DMA request for channel 30
4712 */
4713#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
4714#define DMA_EARS_EDREQ_31_MASK (0x80000000U)
4715#define DMA_EARS_EDREQ_31_SHIFT (31U)
4716/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31
4717 * 0b0..Disable asynchronous DMA request for channel 31
4718 * 0b1..Enable asynchronous DMA request for channel 31
4719 */
4720#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
4721/*! @} */
4722
4723/*! @name DCHPRI3 - Channel Priority Register */
4724/*! @{ */
4725#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
4726#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
4727/*! CHPRI - Channel n Arbitration Priority
4728 */
4729#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
4730#define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
4731#define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
4732/*! GRPPRI - Channel n Current Group Priority
4733 */
4734#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
4735#define DMA_DCHPRI3_DPA_MASK (0x40U)
4736#define DMA_DCHPRI3_DPA_SHIFT (6U)
4737/*! DPA - Disable Preempt Ability. This field resets to 0.
4738 * 0b0..Channel n can suspend a lower priority channel.
4739 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4740 */
4741#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
4742#define DMA_DCHPRI3_ECP_MASK (0x80U)
4743#define DMA_DCHPRI3_ECP_SHIFT (7U)
4744/*! ECP - Enable Channel Preemption. This field resets to 0.
4745 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4746 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4747 */
4748#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
4749/*! @} */
4750
4751/*! @name DCHPRI2 - Channel Priority Register */
4752/*! @{ */
4753#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
4754#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
4755/*! CHPRI - Channel n Arbitration Priority
4756 */
4757#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
4758#define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
4759#define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
4760/*! GRPPRI - Channel n Current Group Priority
4761 */
4762#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
4763#define DMA_DCHPRI2_DPA_MASK (0x40U)
4764#define DMA_DCHPRI2_DPA_SHIFT (6U)
4765/*! DPA - Disable Preempt Ability. This field resets to 0.
4766 * 0b0..Channel n can suspend a lower priority channel.
4767 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4768 */
4769#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
4770#define DMA_DCHPRI2_ECP_MASK (0x80U)
4771#define DMA_DCHPRI2_ECP_SHIFT (7U)
4772/*! ECP - Enable Channel Preemption. This field resets to 0.
4773 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4774 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4775 */
4776#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
4777/*! @} */
4778
4779/*! @name DCHPRI1 - Channel Priority Register */
4780/*! @{ */
4781#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
4782#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
4783/*! CHPRI - Channel n Arbitration Priority
4784 */
4785#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
4786#define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
4787#define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
4788/*! GRPPRI - Channel n Current Group Priority
4789 */
4790#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
4791#define DMA_DCHPRI1_DPA_MASK (0x40U)
4792#define DMA_DCHPRI1_DPA_SHIFT (6U)
4793/*! DPA - Disable Preempt Ability. This field resets to 0.
4794 * 0b0..Channel n can suspend a lower priority channel.
4795 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4796 */
4797#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
4798#define DMA_DCHPRI1_ECP_MASK (0x80U)
4799#define DMA_DCHPRI1_ECP_SHIFT (7U)
4800/*! ECP - Enable Channel Preemption. This field resets to 0.
4801 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4802 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4803 */
4804#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
4805/*! @} */
4806
4807/*! @name DCHPRI0 - Channel Priority Register */
4808/*! @{ */
4809#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
4810#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
4811/*! CHPRI - Channel n Arbitration Priority
4812 */
4813#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
4814#define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
4815#define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
4816/*! GRPPRI - Channel n Current Group Priority
4817 */
4818#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
4819#define DMA_DCHPRI0_DPA_MASK (0x40U)
4820#define DMA_DCHPRI0_DPA_SHIFT (6U)
4821/*! DPA - Disable Preempt Ability. This field resets to 0.
4822 * 0b0..Channel n can suspend a lower priority channel.
4823 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4824 */
4825#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
4826#define DMA_DCHPRI0_ECP_MASK (0x80U)
4827#define DMA_DCHPRI0_ECP_SHIFT (7U)
4828/*! ECP - Enable Channel Preemption. This field resets to 0.
4829 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4830 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4831 */
4832#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
4833/*! @} */
4834
4835/*! @name DCHPRI7 - Channel Priority Register */
4836/*! @{ */
4837#define DMA_DCHPRI7_CHPRI_MASK (0xFU)
4838#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
4839/*! CHPRI - Channel n Arbitration Priority
4840 */
4841#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
4842#define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
4843#define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
4844/*! GRPPRI - Channel n Current Group Priority
4845 */
4846#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
4847#define DMA_DCHPRI7_DPA_MASK (0x40U)
4848#define DMA_DCHPRI7_DPA_SHIFT (6U)
4849/*! DPA - Disable Preempt Ability. This field resets to 0.
4850 * 0b0..Channel n can suspend a lower priority channel.
4851 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4852 */
4853#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
4854#define DMA_DCHPRI7_ECP_MASK (0x80U)
4855#define DMA_DCHPRI7_ECP_SHIFT (7U)
4856/*! ECP - Enable Channel Preemption. This field resets to 0.
4857 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4858 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4859 */
4860#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
4861/*! @} */
4862
4863/*! @name DCHPRI6 - Channel Priority Register */
4864/*! @{ */
4865#define DMA_DCHPRI6_CHPRI_MASK (0xFU)
4866#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
4867/*! CHPRI - Channel n Arbitration Priority
4868 */
4869#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
4870#define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
4871#define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
4872/*! GRPPRI - Channel n Current Group Priority
4873 */
4874#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
4875#define DMA_DCHPRI6_DPA_MASK (0x40U)
4876#define DMA_DCHPRI6_DPA_SHIFT (6U)
4877/*! DPA - Disable Preempt Ability. This field resets to 0.
4878 * 0b0..Channel n can suspend a lower priority channel.
4879 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4880 */
4881#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
4882#define DMA_DCHPRI6_ECP_MASK (0x80U)
4883#define DMA_DCHPRI6_ECP_SHIFT (7U)
4884/*! ECP - Enable Channel Preemption. This field resets to 0.
4885 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4886 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4887 */
4888#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
4889/*! @} */
4890
4891/*! @name DCHPRI5 - Channel Priority Register */
4892/*! @{ */
4893#define DMA_DCHPRI5_CHPRI_MASK (0xFU)
4894#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
4895/*! CHPRI - Channel n Arbitration Priority
4896 */
4897#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
4898#define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
4899#define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
4900/*! GRPPRI - Channel n Current Group Priority
4901 */
4902#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
4903#define DMA_DCHPRI5_DPA_MASK (0x40U)
4904#define DMA_DCHPRI5_DPA_SHIFT (6U)
4905/*! DPA - Disable Preempt Ability. This field resets to 0.
4906 * 0b0..Channel n can suspend a lower priority channel.
4907 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4908 */
4909#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
4910#define DMA_DCHPRI5_ECP_MASK (0x80U)
4911#define DMA_DCHPRI5_ECP_SHIFT (7U)
4912/*! ECP - Enable Channel Preemption. This field resets to 0.
4913 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4914 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4915 */
4916#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
4917/*! @} */
4918
4919/*! @name DCHPRI4 - Channel Priority Register */
4920/*! @{ */
4921#define DMA_DCHPRI4_CHPRI_MASK (0xFU)
4922#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
4923/*! CHPRI - Channel n Arbitration Priority
4924 */
4925#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
4926#define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
4927#define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
4928/*! GRPPRI - Channel n Current Group Priority
4929 */
4930#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
4931#define DMA_DCHPRI4_DPA_MASK (0x40U)
4932#define DMA_DCHPRI4_DPA_SHIFT (6U)
4933/*! DPA - Disable Preempt Ability. This field resets to 0.
4934 * 0b0..Channel n can suspend a lower priority channel.
4935 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4936 */
4937#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
4938#define DMA_DCHPRI4_ECP_MASK (0x80U)
4939#define DMA_DCHPRI4_ECP_SHIFT (7U)
4940/*! ECP - Enable Channel Preemption. This field resets to 0.
4941 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4942 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4943 */
4944#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
4945/*! @} */
4946
4947/*! @name DCHPRI11 - Channel Priority Register */
4948/*! @{ */
4949#define DMA_DCHPRI11_CHPRI_MASK (0xFU)
4950#define DMA_DCHPRI11_CHPRI_SHIFT (0U)
4951/*! CHPRI - Channel n Arbitration Priority
4952 */
4953#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
4954#define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
4955#define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
4956/*! GRPPRI - Channel n Current Group Priority
4957 */
4958#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
4959#define DMA_DCHPRI11_DPA_MASK (0x40U)
4960#define DMA_DCHPRI11_DPA_SHIFT (6U)
4961/*! DPA - Disable Preempt Ability. This field resets to 0.
4962 * 0b0..Channel n can suspend a lower priority channel.
4963 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4964 */
4965#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
4966#define DMA_DCHPRI11_ECP_MASK (0x80U)
4967#define DMA_DCHPRI11_ECP_SHIFT (7U)
4968/*! ECP - Enable Channel Preemption. This field resets to 0.
4969 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4970 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4971 */
4972#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
4973/*! @} */
4974
4975/*! @name DCHPRI10 - Channel Priority Register */
4976/*! @{ */
4977#define DMA_DCHPRI10_CHPRI_MASK (0xFU)
4978#define DMA_DCHPRI10_CHPRI_SHIFT (0U)
4979/*! CHPRI - Channel n Arbitration Priority
4980 */
4981#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
4982#define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
4983#define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
4984/*! GRPPRI - Channel n Current Group Priority
4985 */
4986#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
4987#define DMA_DCHPRI10_DPA_MASK (0x40U)
4988#define DMA_DCHPRI10_DPA_SHIFT (6U)
4989/*! DPA - Disable Preempt Ability. This field resets to 0.
4990 * 0b0..Channel n can suspend a lower priority channel.
4991 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
4992 */
4993#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
4994#define DMA_DCHPRI10_ECP_MASK (0x80U)
4995#define DMA_DCHPRI10_ECP_SHIFT (7U)
4996/*! ECP - Enable Channel Preemption. This field resets to 0.
4997 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
4998 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
4999 */
5000#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
5001/*! @} */
5002
5003/*! @name DCHPRI9 - Channel Priority Register */
5004/*! @{ */
5005#define DMA_DCHPRI9_CHPRI_MASK (0xFU)
5006#define DMA_DCHPRI9_CHPRI_SHIFT (0U)
5007/*! CHPRI - Channel n Arbitration Priority
5008 */
5009#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
5010#define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
5011#define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
5012/*! GRPPRI - Channel n Current Group Priority
5013 */
5014#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
5015#define DMA_DCHPRI9_DPA_MASK (0x40U)
5016#define DMA_DCHPRI9_DPA_SHIFT (6U)
5017/*! DPA - Disable Preempt Ability. This field resets to 0.
5018 * 0b0..Channel n can suspend a lower priority channel.
5019 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5020 */
5021#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
5022#define DMA_DCHPRI9_ECP_MASK (0x80U)
5023#define DMA_DCHPRI9_ECP_SHIFT (7U)
5024/*! ECP - Enable Channel Preemption. This field resets to 0.
5025 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5026 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5027 */
5028#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
5029/*! @} */
5030
5031/*! @name DCHPRI8 - Channel Priority Register */
5032/*! @{ */
5033#define DMA_DCHPRI8_CHPRI_MASK (0xFU)
5034#define DMA_DCHPRI8_CHPRI_SHIFT (0U)
5035/*! CHPRI - Channel n Arbitration Priority
5036 */
5037#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
5038#define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
5039#define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
5040/*! GRPPRI - Channel n Current Group Priority
5041 */
5042#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
5043#define DMA_DCHPRI8_DPA_MASK (0x40U)
5044#define DMA_DCHPRI8_DPA_SHIFT (6U)
5045/*! DPA - Disable Preempt Ability. This field resets to 0.
5046 * 0b0..Channel n can suspend a lower priority channel.
5047 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5048 */
5049#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
5050#define DMA_DCHPRI8_ECP_MASK (0x80U)
5051#define DMA_DCHPRI8_ECP_SHIFT (7U)
5052/*! ECP - Enable Channel Preemption. This field resets to 0.
5053 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5054 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5055 */
5056#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
5057/*! @} */
5058
5059/*! @name DCHPRI15 - Channel Priority Register */
5060/*! @{ */
5061#define DMA_DCHPRI15_CHPRI_MASK (0xFU)
5062#define DMA_DCHPRI15_CHPRI_SHIFT (0U)
5063/*! CHPRI - Channel n Arbitration Priority
5064 */
5065#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
5066#define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
5067#define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
5068/*! GRPPRI - Channel n Current Group Priority
5069 */
5070#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
5071#define DMA_DCHPRI15_DPA_MASK (0x40U)
5072#define DMA_DCHPRI15_DPA_SHIFT (6U)
5073/*! DPA - Disable Preempt Ability. This field resets to 0.
5074 * 0b0..Channel n can suspend a lower priority channel.
5075 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5076 */
5077#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
5078#define DMA_DCHPRI15_ECP_MASK (0x80U)
5079#define DMA_DCHPRI15_ECP_SHIFT (7U)
5080/*! ECP - Enable Channel Preemption. This field resets to 0.
5081 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5082 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5083 */
5084#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
5085/*! @} */
5086
5087/*! @name DCHPRI14 - Channel Priority Register */
5088/*! @{ */
5089#define DMA_DCHPRI14_CHPRI_MASK (0xFU)
5090#define DMA_DCHPRI14_CHPRI_SHIFT (0U)
5091/*! CHPRI - Channel n Arbitration Priority
5092 */
5093#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
5094#define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
5095#define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
5096/*! GRPPRI - Channel n Current Group Priority
5097 */
5098#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
5099#define DMA_DCHPRI14_DPA_MASK (0x40U)
5100#define DMA_DCHPRI14_DPA_SHIFT (6U)
5101/*! DPA - Disable Preempt Ability. This field resets to 0.
5102 * 0b0..Channel n can suspend a lower priority channel.
5103 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5104 */
5105#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
5106#define DMA_DCHPRI14_ECP_MASK (0x80U)
5107#define DMA_DCHPRI14_ECP_SHIFT (7U)
5108/*! ECP - Enable Channel Preemption. This field resets to 0.
5109 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5110 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5111 */
5112#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
5113/*! @} */
5114
5115/*! @name DCHPRI13 - Channel Priority Register */
5116/*! @{ */
5117#define DMA_DCHPRI13_CHPRI_MASK (0xFU)
5118#define DMA_DCHPRI13_CHPRI_SHIFT (0U)
5119/*! CHPRI - Channel n Arbitration Priority
5120 */
5121#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
5122#define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
5123#define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
5124/*! GRPPRI - Channel n Current Group Priority
5125 */
5126#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
5127#define DMA_DCHPRI13_DPA_MASK (0x40U)
5128#define DMA_DCHPRI13_DPA_SHIFT (6U)
5129/*! DPA - Disable Preempt Ability. This field resets to 0.
5130 * 0b0..Channel n can suspend a lower priority channel.
5131 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5132 */
5133#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
5134#define DMA_DCHPRI13_ECP_MASK (0x80U)
5135#define DMA_DCHPRI13_ECP_SHIFT (7U)
5136/*! ECP - Enable Channel Preemption. This field resets to 0.
5137 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5138 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5139 */
5140#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
5141/*! @} */
5142
5143/*! @name DCHPRI12 - Channel Priority Register */
5144/*! @{ */
5145#define DMA_DCHPRI12_CHPRI_MASK (0xFU)
5146#define DMA_DCHPRI12_CHPRI_SHIFT (0U)
5147/*! CHPRI - Channel n Arbitration Priority
5148 */
5149#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
5150#define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
5151#define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
5152/*! GRPPRI - Channel n Current Group Priority
5153 */
5154#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
5155#define DMA_DCHPRI12_DPA_MASK (0x40U)
5156#define DMA_DCHPRI12_DPA_SHIFT (6U)
5157/*! DPA - Disable Preempt Ability. This field resets to 0.
5158 * 0b0..Channel n can suspend a lower priority channel.
5159 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5160 */
5161#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
5162#define DMA_DCHPRI12_ECP_MASK (0x80U)
5163#define DMA_DCHPRI12_ECP_SHIFT (7U)
5164/*! ECP - Enable Channel Preemption. This field resets to 0.
5165 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5166 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5167 */
5168#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
5169/*! @} */
5170
5171/*! @name DCHPRI19 - Channel Priority Register */
5172/*! @{ */
5173#define DMA_DCHPRI19_CHPRI_MASK (0xFU)
5174#define DMA_DCHPRI19_CHPRI_SHIFT (0U)
5175/*! CHPRI - Channel n Arbitration Priority
5176 */
5177#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
5178#define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
5179#define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
5180/*! GRPPRI - Channel n Current Group Priority
5181 */
5182#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
5183#define DMA_DCHPRI19_DPA_MASK (0x40U)
5184#define DMA_DCHPRI19_DPA_SHIFT (6U)
5185/*! DPA - Disable Preempt Ability. This field resets to 0.
5186 * 0b0..Channel n can suspend a lower priority channel.
5187 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5188 */
5189#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
5190#define DMA_DCHPRI19_ECP_MASK (0x80U)
5191#define DMA_DCHPRI19_ECP_SHIFT (7U)
5192/*! ECP - Enable Channel Preemption. This field resets to 0.
5193 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5194 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5195 */
5196#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
5197/*! @} */
5198
5199/*! @name DCHPRI18 - Channel Priority Register */
5200/*! @{ */
5201#define DMA_DCHPRI18_CHPRI_MASK (0xFU)
5202#define DMA_DCHPRI18_CHPRI_SHIFT (0U)
5203/*! CHPRI - Channel n Arbitration Priority
5204 */
5205#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
5206#define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
5207#define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
5208/*! GRPPRI - Channel n Current Group Priority
5209 */
5210#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
5211#define DMA_DCHPRI18_DPA_MASK (0x40U)
5212#define DMA_DCHPRI18_DPA_SHIFT (6U)
5213/*! DPA - Disable Preempt Ability. This field resets to 0.
5214 * 0b0..Channel n can suspend a lower priority channel.
5215 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5216 */
5217#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
5218#define DMA_DCHPRI18_ECP_MASK (0x80U)
5219#define DMA_DCHPRI18_ECP_SHIFT (7U)
5220/*! ECP - Enable Channel Preemption. This field resets to 0.
5221 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5222 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5223 */
5224#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
5225/*! @} */
5226
5227/*! @name DCHPRI17 - Channel Priority Register */
5228/*! @{ */
5229#define DMA_DCHPRI17_CHPRI_MASK (0xFU)
5230#define DMA_DCHPRI17_CHPRI_SHIFT (0U)
5231/*! CHPRI - Channel n Arbitration Priority
5232 */
5233#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
5234#define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
5235#define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
5236/*! GRPPRI - Channel n Current Group Priority
5237 */
5238#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
5239#define DMA_DCHPRI17_DPA_MASK (0x40U)
5240#define DMA_DCHPRI17_DPA_SHIFT (6U)
5241/*! DPA - Disable Preempt Ability. This field resets to 0.
5242 * 0b0..Channel n can suspend a lower priority channel.
5243 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5244 */
5245#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
5246#define DMA_DCHPRI17_ECP_MASK (0x80U)
5247#define DMA_DCHPRI17_ECP_SHIFT (7U)
5248/*! ECP - Enable Channel Preemption. This field resets to 0.
5249 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5250 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5251 */
5252#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
5253/*! @} */
5254
5255/*! @name DCHPRI16 - Channel Priority Register */
5256/*! @{ */
5257#define DMA_DCHPRI16_CHPRI_MASK (0xFU)
5258#define DMA_DCHPRI16_CHPRI_SHIFT (0U)
5259/*! CHPRI - Channel n Arbitration Priority
5260 */
5261#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
5262#define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
5263#define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
5264/*! GRPPRI - Channel n Current Group Priority
5265 */
5266#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
5267#define DMA_DCHPRI16_DPA_MASK (0x40U)
5268#define DMA_DCHPRI16_DPA_SHIFT (6U)
5269/*! DPA - Disable Preempt Ability. This field resets to 0.
5270 * 0b0..Channel n can suspend a lower priority channel.
5271 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5272 */
5273#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
5274#define DMA_DCHPRI16_ECP_MASK (0x80U)
5275#define DMA_DCHPRI16_ECP_SHIFT (7U)
5276/*! ECP - Enable Channel Preemption. This field resets to 0.
5277 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5278 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5279 */
5280#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
5281/*! @} */
5282
5283/*! @name DCHPRI23 - Channel Priority Register */
5284/*! @{ */
5285#define DMA_DCHPRI23_CHPRI_MASK (0xFU)
5286#define DMA_DCHPRI23_CHPRI_SHIFT (0U)
5287/*! CHPRI - Channel n Arbitration Priority
5288 */
5289#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
5290#define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
5291#define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
5292/*! GRPPRI - Channel n Current Group Priority
5293 */
5294#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
5295#define DMA_DCHPRI23_DPA_MASK (0x40U)
5296#define DMA_DCHPRI23_DPA_SHIFT (6U)
5297/*! DPA - Disable Preempt Ability. This field resets to 0.
5298 * 0b0..Channel n can suspend a lower priority channel.
5299 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5300 */
5301#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
5302#define DMA_DCHPRI23_ECP_MASK (0x80U)
5303#define DMA_DCHPRI23_ECP_SHIFT (7U)
5304/*! ECP - Enable Channel Preemption. This field resets to 0.
5305 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5306 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5307 */
5308#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
5309/*! @} */
5310
5311/*! @name DCHPRI22 - Channel Priority Register */
5312/*! @{ */
5313#define DMA_DCHPRI22_CHPRI_MASK (0xFU)
5314#define DMA_DCHPRI22_CHPRI_SHIFT (0U)
5315/*! CHPRI - Channel n Arbitration Priority
5316 */
5317#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
5318#define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
5319#define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
5320/*! GRPPRI - Channel n Current Group Priority
5321 */
5322#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
5323#define DMA_DCHPRI22_DPA_MASK (0x40U)
5324#define DMA_DCHPRI22_DPA_SHIFT (6U)
5325/*! DPA - Disable Preempt Ability. This field resets to 0.
5326 * 0b0..Channel n can suspend a lower priority channel.
5327 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5328 */
5329#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
5330#define DMA_DCHPRI22_ECP_MASK (0x80U)
5331#define DMA_DCHPRI22_ECP_SHIFT (7U)
5332/*! ECP - Enable Channel Preemption. This field resets to 0.
5333 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5334 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5335 */
5336#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
5337/*! @} */
5338
5339/*! @name DCHPRI21 - Channel Priority Register */
5340/*! @{ */
5341#define DMA_DCHPRI21_CHPRI_MASK (0xFU)
5342#define DMA_DCHPRI21_CHPRI_SHIFT (0U)
5343/*! CHPRI - Channel n Arbitration Priority
5344 */
5345#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
5346#define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
5347#define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
5348/*! GRPPRI - Channel n Current Group Priority
5349 */
5350#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
5351#define DMA_DCHPRI21_DPA_MASK (0x40U)
5352#define DMA_DCHPRI21_DPA_SHIFT (6U)
5353/*! DPA - Disable Preempt Ability. This field resets to 0.
5354 * 0b0..Channel n can suspend a lower priority channel.
5355 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5356 */
5357#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
5358#define DMA_DCHPRI21_ECP_MASK (0x80U)
5359#define DMA_DCHPRI21_ECP_SHIFT (7U)
5360/*! ECP - Enable Channel Preemption. This field resets to 0.
5361 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5362 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5363 */
5364#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
5365/*! @} */
5366
5367/*! @name DCHPRI20 - Channel Priority Register */
5368/*! @{ */
5369#define DMA_DCHPRI20_CHPRI_MASK (0xFU)
5370#define DMA_DCHPRI20_CHPRI_SHIFT (0U)
5371/*! CHPRI - Channel n Arbitration Priority
5372 */
5373#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
5374#define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
5375#define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
5376/*! GRPPRI - Channel n Current Group Priority
5377 */
5378#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
5379#define DMA_DCHPRI20_DPA_MASK (0x40U)
5380#define DMA_DCHPRI20_DPA_SHIFT (6U)
5381/*! DPA - Disable Preempt Ability. This field resets to 0.
5382 * 0b0..Channel n can suspend a lower priority channel.
5383 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5384 */
5385#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
5386#define DMA_DCHPRI20_ECP_MASK (0x80U)
5387#define DMA_DCHPRI20_ECP_SHIFT (7U)
5388/*! ECP - Enable Channel Preemption. This field resets to 0.
5389 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5390 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5391 */
5392#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
5393/*! @} */
5394
5395/*! @name DCHPRI27 - Channel Priority Register */
5396/*! @{ */
5397#define DMA_DCHPRI27_CHPRI_MASK (0xFU)
5398#define DMA_DCHPRI27_CHPRI_SHIFT (0U)
5399/*! CHPRI - Channel n Arbitration Priority
5400 */
5401#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
5402#define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
5403#define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
5404/*! GRPPRI - Channel n Current Group Priority
5405 */
5406#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
5407#define DMA_DCHPRI27_DPA_MASK (0x40U)
5408#define DMA_DCHPRI27_DPA_SHIFT (6U)
5409/*! DPA - Disable Preempt Ability. This field resets to 0.
5410 * 0b0..Channel n can suspend a lower priority channel.
5411 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5412 */
5413#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
5414#define DMA_DCHPRI27_ECP_MASK (0x80U)
5415#define DMA_DCHPRI27_ECP_SHIFT (7U)
5416/*! ECP - Enable Channel Preemption. This field resets to 0.
5417 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5418 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5419 */
5420#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
5421/*! @} */
5422
5423/*! @name DCHPRI26 - Channel Priority Register */
5424/*! @{ */
5425#define DMA_DCHPRI26_CHPRI_MASK (0xFU)
5426#define DMA_DCHPRI26_CHPRI_SHIFT (0U)
5427/*! CHPRI - Channel n Arbitration Priority
5428 */
5429#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
5430#define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
5431#define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
5432/*! GRPPRI - Channel n Current Group Priority
5433 */
5434#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
5435#define DMA_DCHPRI26_DPA_MASK (0x40U)
5436#define DMA_DCHPRI26_DPA_SHIFT (6U)
5437/*! DPA - Disable Preempt Ability. This field resets to 0.
5438 * 0b0..Channel n can suspend a lower priority channel.
5439 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5440 */
5441#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
5442#define DMA_DCHPRI26_ECP_MASK (0x80U)
5443#define DMA_DCHPRI26_ECP_SHIFT (7U)
5444/*! ECP - Enable Channel Preemption. This field resets to 0.
5445 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5446 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5447 */
5448#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
5449/*! @} */
5450
5451/*! @name DCHPRI25 - Channel Priority Register */
5452/*! @{ */
5453#define DMA_DCHPRI25_CHPRI_MASK (0xFU)
5454#define DMA_DCHPRI25_CHPRI_SHIFT (0U)
5455/*! CHPRI - Channel n Arbitration Priority
5456 */
5457#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
5458#define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
5459#define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
5460/*! GRPPRI - Channel n Current Group Priority
5461 */
5462#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
5463#define DMA_DCHPRI25_DPA_MASK (0x40U)
5464#define DMA_DCHPRI25_DPA_SHIFT (6U)
5465/*! DPA - Disable Preempt Ability. This field resets to 0.
5466 * 0b0..Channel n can suspend a lower priority channel.
5467 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5468 */
5469#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
5470#define DMA_DCHPRI25_ECP_MASK (0x80U)
5471#define DMA_DCHPRI25_ECP_SHIFT (7U)
5472/*! ECP - Enable Channel Preemption. This field resets to 0.
5473 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5474 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5475 */
5476#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
5477/*! @} */
5478
5479/*! @name DCHPRI24 - Channel Priority Register */
5480/*! @{ */
5481#define DMA_DCHPRI24_CHPRI_MASK (0xFU)
5482#define DMA_DCHPRI24_CHPRI_SHIFT (0U)
5483/*! CHPRI - Channel n Arbitration Priority
5484 */
5485#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
5486#define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
5487#define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
5488/*! GRPPRI - Channel n Current Group Priority
5489 */
5490#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
5491#define DMA_DCHPRI24_DPA_MASK (0x40U)
5492#define DMA_DCHPRI24_DPA_SHIFT (6U)
5493/*! DPA - Disable Preempt Ability. This field resets to 0.
5494 * 0b0..Channel n can suspend a lower priority channel.
5495 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5496 */
5497#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
5498#define DMA_DCHPRI24_ECP_MASK (0x80U)
5499#define DMA_DCHPRI24_ECP_SHIFT (7U)
5500/*! ECP - Enable Channel Preemption. This field resets to 0.
5501 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5502 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5503 */
5504#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
5505/*! @} */
5506
5507/*! @name DCHPRI31 - Channel Priority Register */
5508/*! @{ */
5509#define DMA_DCHPRI31_CHPRI_MASK (0xFU)
5510#define DMA_DCHPRI31_CHPRI_SHIFT (0U)
5511/*! CHPRI - Channel n Arbitration Priority
5512 */
5513#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
5514#define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
5515#define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
5516/*! GRPPRI - Channel n Current Group Priority
5517 */
5518#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
5519#define DMA_DCHPRI31_DPA_MASK (0x40U)
5520#define DMA_DCHPRI31_DPA_SHIFT (6U)
5521/*! DPA - Disable Preempt Ability. This field resets to 0.
5522 * 0b0..Channel n can suspend a lower priority channel.
5523 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5524 */
5525#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
5526#define DMA_DCHPRI31_ECP_MASK (0x80U)
5527#define DMA_DCHPRI31_ECP_SHIFT (7U)
5528/*! ECP - Enable Channel Preemption. This field resets to 0.
5529 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5530 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5531 */
5532#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
5533/*! @} */
5534
5535/*! @name DCHPRI30 - Channel Priority Register */
5536/*! @{ */
5537#define DMA_DCHPRI30_CHPRI_MASK (0xFU)
5538#define DMA_DCHPRI30_CHPRI_SHIFT (0U)
5539/*! CHPRI - Channel n Arbitration Priority
5540 */
5541#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
5542#define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
5543#define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
5544/*! GRPPRI - Channel n Current Group Priority
5545 */
5546#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
5547#define DMA_DCHPRI30_DPA_MASK (0x40U)
5548#define DMA_DCHPRI30_DPA_SHIFT (6U)
5549/*! DPA - Disable Preempt Ability. This field resets to 0.
5550 * 0b0..Channel n can suspend a lower priority channel.
5551 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5552 */
5553#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
5554#define DMA_DCHPRI30_ECP_MASK (0x80U)
5555#define DMA_DCHPRI30_ECP_SHIFT (7U)
5556/*! ECP - Enable Channel Preemption. This field resets to 0.
5557 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5558 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5559 */
5560#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
5561/*! @} */
5562
5563/*! @name DCHPRI29 - Channel Priority Register */
5564/*! @{ */
5565#define DMA_DCHPRI29_CHPRI_MASK (0xFU)
5566#define DMA_DCHPRI29_CHPRI_SHIFT (0U)
5567/*! CHPRI - Channel n Arbitration Priority
5568 */
5569#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
5570#define DMA_DCHPRI29_GRPPRI_MASK (0x30U)
5571#define DMA_DCHPRI29_GRPPRI_SHIFT (4U)
5572/*! GRPPRI - Channel n Current Group Priority
5573 */
5574#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
5575#define DMA_DCHPRI29_DPA_MASK (0x40U)
5576#define DMA_DCHPRI29_DPA_SHIFT (6U)
5577/*! DPA - Disable Preempt Ability. This field resets to 0.
5578 * 0b0..Channel n can suspend a lower priority channel.
5579 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5580 */
5581#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
5582#define DMA_DCHPRI29_ECP_MASK (0x80U)
5583#define DMA_DCHPRI29_ECP_SHIFT (7U)
5584/*! ECP - Enable Channel Preemption. This field resets to 0.
5585 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5586 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5587 */
5588#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
5589/*! @} */
5590
5591/*! @name DCHPRI28 - Channel Priority Register */
5592/*! @{ */
5593#define DMA_DCHPRI28_CHPRI_MASK (0xFU)
5594#define DMA_DCHPRI28_CHPRI_SHIFT (0U)
5595/*! CHPRI - Channel n Arbitration Priority
5596 */
5597#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
5598#define DMA_DCHPRI28_GRPPRI_MASK (0x30U)
5599#define DMA_DCHPRI28_GRPPRI_SHIFT (4U)
5600/*! GRPPRI - Channel n Current Group Priority
5601 */
5602#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
5603#define DMA_DCHPRI28_DPA_MASK (0x40U)
5604#define DMA_DCHPRI28_DPA_SHIFT (6U)
5605/*! DPA - Disable Preempt Ability. This field resets to 0.
5606 * 0b0..Channel n can suspend a lower priority channel.
5607 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
5608 */
5609#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
5610#define DMA_DCHPRI28_ECP_MASK (0x80U)
5611#define DMA_DCHPRI28_ECP_SHIFT (7U)
5612/*! ECP - Enable Channel Preemption. This field resets to 0.
5613 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
5614 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
5615 */
5616#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
5617/*! @} */
5618
5619/*! @name SADDR - TCD Source Address */
5620/*! @{ */
5621#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
5622#define DMA_SADDR_SADDR_SHIFT (0U)
5623/*! SADDR - Source Address
5624 */
5625#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
5626/*! @} */
5627
5628/* The count of DMA_SADDR */
5629#define DMA_SADDR_COUNT (32U)
5630
5631/*! @name SOFF - TCD Signed Source Address Offset */
5632/*! @{ */
5633#define DMA_SOFF_SOFF_MASK (0xFFFFU)
5634#define DMA_SOFF_SOFF_SHIFT (0U)
5635/*! SOFF - Source address signed offset
5636 */
5637#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
5638/*! @} */
5639
5640/* The count of DMA_SOFF */
5641#define DMA_SOFF_COUNT (32U)
5642
5643/*! @name ATTR - TCD Transfer Attributes */
5644/*! @{ */
5645#define DMA_ATTR_DSIZE_MASK (0x7U)
5646#define DMA_ATTR_DSIZE_SHIFT (0U)
5647/*! DSIZE - Destination data transfer size
5648 */
5649#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
5650#define DMA_ATTR_DMOD_MASK (0xF8U)
5651#define DMA_ATTR_DMOD_SHIFT (3U)
5652/*! DMOD - Destination Address Modulo
5653 */
5654#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
5655#define DMA_ATTR_SSIZE_MASK (0x700U)
5656#define DMA_ATTR_SSIZE_SHIFT (8U)
5657/*! SSIZE - Source data transfer size
5658 * 0b000..8-bit
5659 * 0b001..16-bit
5660 * 0b010..32-bit
5661 * 0b011..64-bit
5662 * 0b100..Reserved
5663 * 0b101..32-byte burst (4 beats of 64 bits)
5664 * 0b110..Reserved
5665 * 0b111..Reserved
5666 */
5667#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
5668#define DMA_ATTR_SMOD_MASK (0xF800U)
5669#define DMA_ATTR_SMOD_SHIFT (11U)
5670/*! SMOD - Source Address Modulo
5671 * 0b00000..Source address modulo feature is disabled
5672 * 0b00001-0b11111..This value defines a specific address range specified to be the value after SADDR + SOFF
5673 * calculation is performed on the original register value. Setting this field provides the ability
5674 * to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the
5675 * queue should start at a 0-modulo-size address and the SMOD field should be set to the
5676 * appropriate value for the queue, freezing the desired number of upper address bits. The value
5677 * programmed into this field specifies the number of lower address bits allowed to change. For a
5678 * circular queue application, the SOFF is typically set to the transfer size to implement
5679 * post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
5680 */
5681#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
5682/*! @} */
5683
5684/* The count of DMA_ATTR */
5685#define DMA_ATTR_COUNT (32U)
5686
5687/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
5688/*! @{ */
5689#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
5690#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
5691/*! NBYTES - Minor Byte Transfer Count
5692 */
5693#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
5694/*! @} */
5695
5696/* The count of DMA_NBYTES_MLNO */
5697#define DMA_NBYTES_MLNO_COUNT (32U)
5698
5699/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
5700/*! @{ */
5701#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
5702#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
5703/*! NBYTES - Minor Byte Transfer Count
5704 */
5705#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
5706#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
5707#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
5708/*! DMLOE - Destination Minor Loop Offset enable
5709 * 0b0..The minor loop offset is not applied to the DADDR
5710 * 0b1..The minor loop offset is applied to the DADDR
5711 */
5712#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
5713#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
5714#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
5715/*! SMLOE - Source Minor Loop Offset Enable
5716 * 0b0..The minor loop offset is not applied to the SADDR
5717 * 0b1..The minor loop offset is applied to the SADDR
5718 */
5719#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
5720/*! @} */
5721
5722/* The count of DMA_NBYTES_MLOFFNO */
5723#define DMA_NBYTES_MLOFFNO_COUNT (32U)
5724
5725/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
5726/*! @{ */
5727#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
5728#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
5729/*! NBYTES - Minor Byte Transfer Count
5730 */
5731#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
5732#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
5733#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
5734/*! MLOFF - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the
5735 * source or destination address to form the next-state value after the minor loop completes.
5736 */
5737#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
5738#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
5739#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
5740/*! DMLOE - Destination Minor Loop Offset enable
5741 * 0b0..The minor loop offset is not applied to the DADDR
5742 * 0b1..The minor loop offset is applied to the DADDR
5743 */
5744#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
5745#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
5746#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
5747/*! SMLOE - Source Minor Loop Offset Enable
5748 * 0b0..The minor loop offset is not applied to the SADDR
5749 * 0b1..The minor loop offset is applied to the SADDR
5750 */
5751#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
5752/*! @} */
5753
5754/* The count of DMA_NBYTES_MLOFFYES */
5755#define DMA_NBYTES_MLOFFYES_COUNT (32U)
5756
5757/*! @name SLAST - TCD Last Source Address Adjustment */
5758/*! @{ */
5759#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
5760#define DMA_SLAST_SLAST_SHIFT (0U)
5761/*! SLAST - Last Source Address Adjustment
5762 */
5763#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
5764/*! @} */
5765
5766/* The count of DMA_SLAST */
5767#define DMA_SLAST_COUNT (32U)
5768
5769/*! @name DADDR - TCD Destination Address */
5770/*! @{ */
5771#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
5772#define DMA_DADDR_DADDR_SHIFT (0U)
5773/*! DADDR - Destination Address
5774 */
5775#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
5776/*! @} */
5777
5778/* The count of DMA_DADDR */
5779#define DMA_DADDR_COUNT (32U)
5780
5781/*! @name DOFF - TCD Signed Destination Address Offset */
5782/*! @{ */
5783#define DMA_DOFF_DOFF_MASK (0xFFFFU)
5784#define DMA_DOFF_DOFF_SHIFT (0U)
5785/*! DOFF - Destination Address Signed Offset
5786 */
5787#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
5788/*! @} */
5789
5790/* The count of DMA_DOFF */
5791#define DMA_DOFF_COUNT (32U)
5792
5793/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
5794/*! @{ */
5795#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
5796#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
5797/*! CITER - Current Major Iteration Count
5798 */
5799#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
5800#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
5801#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
5802/*! ELINK - Enable channel-to-channel linking on minor-loop complete
5803 * 0b0..The channel-to-channel linking is disabled
5804 * 0b1..The channel-to-channel linking is enabled
5805 */
5806#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
5807/*! @} */
5808
5809/* The count of DMA_CITER_ELINKNO */
5810#define DMA_CITER_ELINKNO_COUNT (32U)
5811
5812/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
5813/*! @{ */
5814#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
5815#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
5816/*! CITER - Current Major Iteration Count
5817 */
5818#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
5819#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
5820#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
5821/*! LINKCH - Minor Loop Link Channel Number
5822 */
5823#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
5824#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
5825#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
5826/*! ELINK - Enable channel-to-channel linking on minor-loop complete
5827 * 0b0..The channel-to-channel linking is disabled
5828 * 0b1..The channel-to-channel linking is enabled
5829 */
5830#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
5831/*! @} */
5832
5833/* The count of DMA_CITER_ELINKYES */
5834#define DMA_CITER_ELINKYES_COUNT (32U)
5835
5836/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
5837/*! @{ */
5838#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
5839#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
5840/*! DLASTSGA - DLASTSGA
5841 */
5842#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
5843/*! @} */
5844
5845/* The count of DMA_DLAST_SGA */
5846#define DMA_DLAST_SGA_COUNT (32U)
5847
5848/*! @name CSR - TCD Control and Status */
5849/*! @{ */
5850#define DMA_CSR_START_MASK (0x1U)
5851#define DMA_CSR_START_SHIFT (0U)
5852/*! START - Channel Start
5853 * 0b0..The channel is not explicitly started.
5854 * 0b1..The channel is explicitly started via a software initiated service request.
5855 */
5856#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
5857#define DMA_CSR_INTMAJOR_MASK (0x2U)
5858#define DMA_CSR_INTMAJOR_SHIFT (1U)
5859/*! INTMAJOR - Enable an interrupt when major iteration count completes.
5860 * 0b0..The end-of-major loop interrupt is disabled.
5861 * 0b1..The end-of-major loop interrupt is enabled.
5862 */
5863#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
5864#define DMA_CSR_INTHALF_MASK (0x4U)
5865#define DMA_CSR_INTHALF_SHIFT (2U)
5866/*! INTHALF - Enable an interrupt when major counter is half complete.
5867 * 0b0..The half-point interrupt is disabled.
5868 * 0b1..The half-point interrupt is enabled.
5869 */
5870#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
5871#define DMA_CSR_DREQ_MASK (0x8U)
5872#define DMA_CSR_DREQ_SHIFT (3U)
5873/*! DREQ - Disable Request
5874 * 0b0..The channel's ERQ bit is not affected.
5875 * 0b1..The channel's ERQ bit is cleared when the major loop is complete.
5876 */
5877#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
5878#define DMA_CSR_ESG_MASK (0x10U)
5879#define DMA_CSR_ESG_SHIFT (4U)
5880/*! ESG - Enable Scatter/Gather Processing
5881 * 0b0..The current channel's TCD is normal format.
5882 * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer
5883 * to the next TCD to be loaded into this channel after the major loop completes its execution.
5884 */
5885#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
5886#define DMA_CSR_MAJORELINK_MASK (0x20U)
5887#define DMA_CSR_MAJORELINK_SHIFT (5U)
5888/*! MAJORELINK - Enable channel-to-channel linking on major loop complete
5889 * 0b0..The channel-to-channel linking is disabled.
5890 * 0b1..The channel-to-channel linking is enabled.
5891 */
5892#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
5893#define DMA_CSR_ACTIVE_MASK (0x40U)
5894#define DMA_CSR_ACTIVE_SHIFT (6U)
5895/*! ACTIVE - Channel Active
5896 */
5897#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
5898#define DMA_CSR_DONE_MASK (0x80U)
5899#define DMA_CSR_DONE_SHIFT (7U)
5900/*! DONE - Channel Done
5901 */
5902#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
5903#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
5904#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
5905/*! MAJORLINKCH - Major Loop Link Channel Number
5906 */
5907#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
5908#define DMA_CSR_BWC_MASK (0xC000U)
5909#define DMA_CSR_BWC_SHIFT (14U)
5910/*! BWC - Bandwidth Control
5911 * 0b00..No eDMA engine stalls.
5912 * 0b01..Reserved
5913 * 0b10..eDMA engine stalls for 4 cycles after each R/W.
5914 * 0b11..eDMA engine stalls for 8 cycles after each R/W.
5915 */
5916#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
5917/*! @} */
5918
5919/* The count of DMA_CSR */
5920#define DMA_CSR_COUNT (32U)
5921
5922/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
5923/*! @{ */
5924#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
5925#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
5926/*! BITER - Starting Major Iteration Count
5927 */
5928#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
5929#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
5930#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
5931/*! ELINK - Enables channel-to-channel linking on minor loop complete
5932 * 0b0..The channel-to-channel linking is disabled
5933 * 0b1..The channel-to-channel linking is enabled
5934 */
5935#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
5936/*! @} */
5937
5938/* The count of DMA_BITER_ELINKNO */
5939#define DMA_BITER_ELINKNO_COUNT (32U)
5940
5941/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
5942/*! @{ */
5943#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
5944#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
5945/*! BITER - Starting major iteration count
5946 */
5947#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
5948#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
5949#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
5950/*! LINKCH - Link Channel Number
5951 */
5952#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
5953#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
5954#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
5955/*! ELINK - Enables channel-to-channel linking on minor loop complete
5956 * 0b0..The channel-to-channel linking is disabled
5957 * 0b1..The channel-to-channel linking is enabled
5958 */
5959#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
5960/*! @} */
5961
5962/* The count of DMA_BITER_ELINKYES */
5963#define DMA_BITER_ELINKYES_COUNT (32U)
5964
5965
5966/*!
5967 * @}
5968 */ /* end of group DMA_Register_Masks */
5969
5970
5971/* DMA - Peripheral instance base addresses */
5972/** Peripheral DMA0 base address */
5973#define DMA0_BASE (0x41008000u)
5974/** Peripheral DMA0 base pointer */
5975#define DMA0 ((DMA_Type *)DMA0_BASE)
5976/** Peripheral DMA1 base address */
5977#define DMA1_BASE (0x40080000u)
5978/** Peripheral DMA1 base pointer */
5979#define DMA1 ((DMA_Type *)DMA1_BASE)
5980/** Array initializer of DMA peripheral base addresses */
5981#define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE }
5982/** Array initializer of DMA peripheral base pointers */
5983#define DMA_BASE_PTRS { DMA0, DMA1 }
5984/** Interrupt vectors for the DMA peripheral type */
5985#define DMA_CHN_IRQS { { DMA0_0_4_IRQn, DMA0_1_5_IRQn, DMA0_2_6_IRQn, DMA0_3_7_IRQn, DMA0_0_4_IRQn, DMA0_1_5_IRQn, DMA0_2_6_IRQn, DMA0_3_7_IRQn, DMA0_8_12_IRQn, DMA0_9_13_IRQn, DMA0_10_14_IRQn, DMA0_11_15_IRQn, DMA0_8_12_IRQn, DMA0_9_13_IRQn, DMA0_10_14_IRQn, DMA0_11_15_IRQn, DMA0_16_20_IRQn, DMA0_17_21_IRQn, DMA0_18_22_IRQn, DMA0_19_23_IRQn, DMA0_16_20_IRQn, DMA0_17_21_IRQn, DMA0_18_22_IRQn, DMA0_19_23_IRQn, DMA0_24_28_IRQn, DMA0_25_29_IRQn, DMA0_26_30_IRQn, DMA0_27_31_IRQn, DMA0_24_28_IRQn, DMA0_25_29_IRQn, DMA0_26_30_IRQn, DMA0_27_31_IRQn }, \
5986 { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } }
5987#define DMA_ERROR_IRQS { DMA0_Error_IRQn, NotAvail_IRQn }
5988
5989/*!
5990 * @}
5991 */ /* end of group DMA_Peripheral_Access_Layer */
5992
5993
5994/* ----------------------------------------------------------------------------
5995 -- DMAMUX Peripheral Access Layer
5996 ---------------------------------------------------------------------------- */
5997
5998/*!
5999 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
6000 * @{
6001 */
6002
6003/** DMAMUX - Register Layout Typedef */
6004typedef struct {
6005 __IO uint32_t CHCFG[32]; /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */
6006} DMAMUX_Type;
6007
6008/* ----------------------------------------------------------------------------
6009 -- DMAMUX Register Masks
6010 ---------------------------------------------------------------------------- */
6011
6012/*!
6013 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
6014 * @{
6015 */
6016
6017/*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */
6018/*! @{ */
6019#define DMAMUX_CHCFG_SOURCE_MASK (0x7FU)
6020#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
6021/*! SOURCE - DMA Channel Source (Slot Number)
6022 */
6023#define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
6024#define DMAMUX_CHCFG_A_ON_MASK (0x20000000U)
6025#define DMAMUX_CHCFG_A_ON_SHIFT (29U)
6026/*! A_ON - DMA Channel Always Enable
6027 * 0b0..DMA Channel Always ON function is disabled
6028 * 0b1..DMA Channel Always ON function is enabled
6029 */
6030#define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
6031#define DMAMUX_CHCFG_TRIG_MASK (0x40000000U)
6032#define DMAMUX_CHCFG_TRIG_SHIFT (30U)
6033/*! TRIG - DMA Channel Trigger Enable
6034 * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the
6035 * specified source to the DMA channel. (Normal mode)
6036 * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
6037 */
6038#define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
6039#define DMAMUX_CHCFG_ENBL_MASK (0x80000000U)
6040#define DMAMUX_CHCFG_ENBL_SHIFT (31U)
6041/*! ENBL - DMA Mux Channel Enable
6042 * 0b0..DMA Mux channel is disabled
6043 * 0b1..DMA Mux channel is enabled
6044 */
6045#define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
6046/*! @} */
6047
6048/* The count of DMAMUX_CHCFG */
6049#define DMAMUX_CHCFG_COUNT (32U)
6050
6051
6052/*!
6053 * @}
6054 */ /* end of group DMAMUX_Register_Masks */
6055
6056
6057/* DMAMUX - Peripheral instance base addresses */
6058/** Peripheral DMA_CH_MUX0 base address */
6059#define DMA_CH_MUX0_BASE (0x41020000u)
6060/** Peripheral DMA_CH_MUX0 base pointer */
6061#define DMA_CH_MUX0 ((DMAMUX_Type *)DMA_CH_MUX0_BASE)
6062/** Peripheral DMA_CH_MUX1 base address */
6063#define DMA_CH_MUX1_BASE (0x40210000u)
6064/** Peripheral DMA_CH_MUX1 base pointer */
6065#define DMA_CH_MUX1 ((DMAMUX_Type *)DMA_CH_MUX1_BASE)
6066/** Array initializer of DMAMUX peripheral base addresses */
6067#define DMAMUX_BASE_ADDRS { DMA_CH_MUX0_BASE, DMA_CH_MUX1_BASE }
6068/** Array initializer of DMAMUX peripheral base pointers */
6069#define DMAMUX_BASE_PTRS { DMA_CH_MUX0, DMA_CH_MUX1 }
6070
6071/*!
6072 * @}
6073 */ /* end of group DMAMUX_Peripheral_Access_Layer */
6074
6075
6076/* ----------------------------------------------------------------------------
6077 -- EWM Peripheral Access Layer
6078 ---------------------------------------------------------------------------- */
6079
6080/*!
6081 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
6082 * @{
6083 */
6084
6085/** EWM - Register Layout Typedef */
6086typedef struct {
6087 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
6088 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
6089 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
6090 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
6091 __IO uint8_t CLKCTRL; /**< Clock Control Register, offset: 0x4 */
6092 __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
6093} EWM_Type;
6094
6095/* ----------------------------------------------------------------------------
6096 -- EWM Register Masks
6097 ---------------------------------------------------------------------------- */
6098
6099/*!
6100 * @addtogroup EWM_Register_Masks EWM Register Masks
6101 * @{
6102 */
6103
6104/*! @name CTRL - Control Register */
6105/*! @{ */
6106#define EWM_CTRL_EWMEN_MASK (0x1U)
6107#define EWM_CTRL_EWMEN_SHIFT (0U)
6108/*! EWMEN - EWM enable.
6109 */
6110#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
6111#define EWM_CTRL_ASSIN_MASK (0x2U)
6112#define EWM_CTRL_ASSIN_SHIFT (1U)
6113/*! ASSIN - EWM_in's Assertion State Select.
6114 */
6115#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
6116#define EWM_CTRL_INEN_MASK (0x4U)
6117#define EWM_CTRL_INEN_SHIFT (2U)
6118/*! INEN - Input Enable.
6119 */
6120#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
6121#define EWM_CTRL_INTEN_MASK (0x8U)
6122#define EWM_CTRL_INTEN_SHIFT (3U)
6123/*! INTEN - Interrupt Enable.
6124 */
6125#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
6126/*! @} */
6127
6128/*! @name SERV - Service Register */
6129/*! @{ */
6130#define EWM_SERV_SERVICE_MASK (0xFFU)
6131#define EWM_SERV_SERVICE_SHIFT (0U)
6132/*! SERVICE - SERVICE
6133 */
6134#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
6135/*! @} */
6136
6137/*! @name CMPL - Compare Low Register */
6138/*! @{ */
6139#define EWM_CMPL_COMPAREL_MASK (0xFFU)
6140#define EWM_CMPL_COMPAREL_SHIFT (0U)
6141/*! COMPAREL - COMPAREL
6142 */
6143#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
6144/*! @} */
6145
6146/*! @name CMPH - Compare High Register */
6147/*! @{ */
6148#define EWM_CMPH_COMPAREH_MASK (0xFFU)
6149#define EWM_CMPH_COMPAREH_SHIFT (0U)
6150/*! COMPAREH - COMPAREH
6151 */
6152#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
6153/*! @} */
6154
6155/*! @name CLKCTRL - Clock Control Register */
6156/*! @{ */
6157#define EWM_CLKCTRL_CLKSEL_MASK (0x3U)
6158#define EWM_CLKCTRL_CLKSEL_SHIFT (0U)
6159/*! CLKSEL - CLKSEL
6160 */
6161#define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
6162/*! @} */
6163
6164/*! @name CLKPRESCALER - Clock Prescaler Register */
6165/*! @{ */
6166#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
6167#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
6168/*! CLK_DIV - CLK_DIV
6169 */
6170#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
6171/*! @} */
6172
6173
6174/*!
6175 * @}
6176 */ /* end of group EWM_Register_Masks */
6177
6178
6179/* EWM - Peripheral instance base addresses */
6180/** Peripheral EWM base address */
6181#define EWM_BASE (0x410A0000u)
6182/** Peripheral EWM base pointer */
6183#define EWM ((EWM_Type *)EWM_BASE)
6184/** Array initializer of EWM peripheral base addresses */
6185#define EWM_BASE_ADDRS { EWM_BASE }
6186/** Array initializer of EWM peripheral base pointers */
6187#define EWM_BASE_PTRS { EWM }
6188/** Interrupt vectors for the EWM peripheral type */
6189#define EWM_IRQS { EWM_IRQn }
6190
6191/*!
6192 * @}
6193 */ /* end of group EWM_Peripheral_Access_Layer */
6194
6195
6196/* ----------------------------------------------------------------------------
6197 -- FB Peripheral Access Layer
6198 ---------------------------------------------------------------------------- */
6199
6200/*!
6201 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
6202 * @{
6203 */
6204
6205/** FB - Register Layout Typedef */
6206typedef struct {
6207 struct { /* offset: 0x0, array step: 0xC */
6208 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
6209 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
6210 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
6211 } CS[6];
6212 uint8_t RESERVED_0[24];
6213 __IO uint32_t CSPMCR; /**< Chip Select Port Multiplexing Control Register, offset: 0x60 */
6214} FB_Type;
6215
6216/* ----------------------------------------------------------------------------
6217 -- FB Register Masks
6218 ---------------------------------------------------------------------------- */
6219
6220/*!
6221 * @addtogroup FB_Register_Masks FB Register Masks
6222 * @{
6223 */
6224
6225/*! @name CSAR - Chip Select Address Register */
6226/*! @{ */
6227#define FB_CSAR_BA_MASK (0xFFFF0000U)
6228#define FB_CSAR_BA_SHIFT (16U)
6229/*! BA - Base Address
6230 */
6231#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
6232/*! @} */
6233
6234/* The count of FB_CSAR */
6235#define FB_CSAR_COUNT (6U)
6236
6237/*! @name CSMR - Chip Select Mask Register */
6238/*! @{ */
6239#define FB_CSMR_V_MASK (0x1U)
6240#define FB_CSMR_V_SHIFT (0U)
6241/*! V - Valid
6242 * 0b0..Chip-select is invalid.
6243 * 0b1..Chip-select is valid.
6244 */
6245#define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
6246#define FB_CSMR_WP_MASK (0x100U)
6247#define FB_CSMR_WP_SHIFT (8U)
6248/*! WP - Write Protect
6249 * 0b0..Write accesses are allowed.
6250 * 0b1..Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set
6251 * results in a bus error termination of the internal cycle and no external cycle.
6252 */
6253#define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
6254#define FB_CSMR_BAM_MASK (0xFFFF0000U)
6255#define FB_CSMR_BAM_SHIFT (16U)
6256/*! BAM - Base Address Mask
6257 * 0b0000000000000000..The corresponding address bit in CSAR is used in the chip-select decode.
6258 * 0b0000000000000001..The corresponding address bit in CSAR is a don't care in the chip-select decode.
6259 */
6260#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
6261/*! @} */
6262
6263/* The count of FB_CSMR */
6264#define FB_CSMR_COUNT (6U)
6265
6266/*! @name CSCR - Chip Select Control Register */
6267/*! @{ */
6268#define FB_CSCR_BSTW_MASK (0x8U)
6269#define FB_CSCR_BSTW_SHIFT (3U)
6270/*! BSTW - Burst-Write Enable
6271 * 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes.
6272 * For example, a 32-bit write to an 8-bit port takes four byte writes.
6273 * 0b1..Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8-
6274 * and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
6275 */
6276#define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
6277#define FB_CSCR_BSTR_MASK (0x10U)
6278#define FB_CSCR_BSTR_SHIFT (4U)
6279/*! BSTR - Burst-Read Enable
6280 * 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads.
6281 * For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
6282 * 0b1..Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and
6283 * 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
6284 */
6285#define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
6286#define FB_CSCR_BEM_MASK (0x20U)
6287#define FB_CSCR_BEM_SHIFT (5U)
6288/*! BEM - Byte-Enable Mode
6289 * 0b0..FB_BE_B is asserted for data write only.
6290 * 0b1..FB_BE_B is asserted for data read and write accesses.
6291 */
6292#define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
6293#define FB_CSCR_PS_MASK (0xC0U)
6294#define FB_CSCR_PS_SHIFT (6U)
6295/*! PS - Port Size
6296 * 0b00..32-bit port size. Valid data is sampled and driven on FB_D[31:0].
6297 * 0b01..8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b.
6298 * 0b1x..16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.
6299 */
6300#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
6301#define FB_CSCR_AA_MASK (0x100U)
6302#define FB_CSCR_AA_SHIFT (8U)
6303/*! AA - Auto-Acknowledge Enable
6304 * 0b0..Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
6305 * 0b1..Enabled. Internal transfer acknowledge is asserted as specified by WS.
6306 */
6307#define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
6308#define FB_CSCR_BLS_MASK (0x200U)
6309#define FB_CSCR_BLS_SHIFT (9U)
6310/*! BLS - Byte-Lane Shift
6311 * 0b0..Not shifted. Data is left-aligned on FB_AD.
6312 * 0b1..Shifted. Data is right-aligned on FB_AD.
6313 */
6314#define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
6315#define FB_CSCR_WS_MASK (0xFC00U)
6316#define FB_CSCR_WS_SHIFT (10U)
6317/*! WS - Wait States
6318 */
6319#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
6320#define FB_CSCR_WRAH_MASK (0x30000U)
6321#define FB_CSCR_WRAH_SHIFT (16U)
6322/*! WRAH - Write Address Hold or Deselect
6323 * 0b00..1 cycle (default for all but FB_CS0_B)
6324 * 0b01..2 cycles
6325 * 0b10..3 cycles
6326 * 0b11..4 cycles (default for FB_CS0_B)
6327 */
6328#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
6329#define FB_CSCR_RDAH_MASK (0xC0000U)
6330#define FB_CSCR_RDAH_SHIFT (18U)
6331/*! RDAH - Read Address Hold or Deselect
6332 * 0b00..When AA is 1b, 1 cycle. When AA is 0b, 0 cycles.
6333 * 0b01..When AA is 1b, 2 cycles. When AA is 0b, 1 cycle.
6334 * 0b10..When AA is 1b, 3 cycles. When AA is 0b, 2 cycles.
6335 * 0b11..When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.
6336 */
6337#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
6338#define FB_CSCR_ASET_MASK (0x300000U)
6339#define FB_CSCR_ASET_SHIFT (20U)
6340/*! ASET - Address Setup
6341 * 0b00..Assert FB_CSn_B on the first rising clock edge after the address is asserted (default for all but FB_CS0_B).
6342 * 0b01..Assert FB_CSn_B on the second rising clock edge after the address is asserted.
6343 * 0b10..Assert FB_CSn_B on the third rising clock edge after the address is asserted.
6344 * 0b11..Assert FB_CSn_B on the fourth rising clock edge after the address is asserted (default for FB_CS0_B ).
6345 */
6346#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
6347#define FB_CSCR_EXTS_MASK (0x400000U)
6348#define FB_CSCR_EXTS_SHIFT (22U)
6349/*! EXTS - EXTS
6350 * 0b0..Disabled. FB_TS_B/FB_ALE asserts for one bus clock cycle.
6351 * 0b1..Enabled. FB_TS_B/FB_ALE remains asserted until the first positive clock edge after FB_CSn_B asserts.
6352 */
6353#define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
6354#define FB_CSCR_SWSEN_MASK (0x800000U)
6355#define FB_CSCR_SWSEN_SHIFT (23U)
6356/*! SWSEN - Secondary Wait State Enable
6357 * 0b0..Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers.
6358 * 0b1..Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge
6359 * is generated for burst transfer secondary terminations.
6360 */
6361#define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
6362#define FB_CSCR_SWS_MASK (0xFC000000U)
6363#define FB_CSCR_SWS_SHIFT (26U)
6364/*! SWS - Secondary Wait States
6365 */
6366#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
6367/*! @} */
6368
6369/* The count of FB_CSCR */
6370#define FB_CSCR_COUNT (6U)
6371
6372/*! @name CSPMCR - Chip Select Port Multiplexing Control Register */
6373/*! @{ */
6374#define FB_CSPMCR_GROUP5_MASK (0xF000U)
6375#define FB_CSPMCR_GROUP5_SHIFT (12U)
6376/*! GROUP5 - FlexBus Signal Group 5 Multiplex control
6377 * 0b0000..FB_TA_B
6378 * 0b0001..FB_CS3_B. You must also write 1b to CSCR[AA].
6379 * 0b0010..FB_BE_7_0_B. You must also write 1b to CSCR[AA].
6380 */
6381#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
6382#define FB_CSPMCR_GROUP4_MASK (0xF0000U)
6383#define FB_CSPMCR_GROUP4_SHIFT (16U)
6384/*! GROUP4 - FlexBus Signal Group 4 Multiplex control
6385 * 0b0000..FB_TBST_B
6386 * 0b0001..FB_CS2_B
6387 * 0b0010..FB_BE_15_8_B
6388 */
6389#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
6390#define FB_CSPMCR_GROUP3_MASK (0xF00000U)
6391#define FB_CSPMCR_GROUP3_SHIFT (20U)
6392/*! GROUP3 - FlexBus Signal Group 3 Multiplex control
6393 * 0b0000..FB_CS5_B
6394 * 0b0001..FB_TSIZ1
6395 * 0b0010..FB_BE_23_16_B
6396 */
6397#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
6398#define FB_CSPMCR_GROUP2_MASK (0xF000000U)
6399#define FB_CSPMCR_GROUP2_SHIFT (24U)
6400/*! GROUP2 - FlexBus Signal Group 2 Multiplex control
6401 * 0b0000..FB_CS4_B
6402 * 0b0001..FB_TSIZ0
6403 * 0b0010..FB_BE_31_24_B
6404 */
6405#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
6406#define FB_CSPMCR_GROUP1_MASK (0xF0000000U)
6407#define FB_CSPMCR_GROUP1_SHIFT (28U)
6408/*! GROUP1 - FlexBus Signal Group 1 Multiplex control
6409 * 0b0000..FB_ALE
6410 * 0b0001..FB_CS1_B
6411 * 0b0010..FB_TS_B
6412 */
6413#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
6414/*! @} */
6415
6416
6417/*!
6418 * @}
6419 */ /* end of group FB_Register_Masks */
6420
6421
6422/* FB - Peripheral instance base addresses */
6423/** Peripheral FB base address */
6424#define FB_BASE (0x40100000u)
6425/** Peripheral FB base pointer */
6426#define FB ((FB_Type *)FB_BASE)
6427/** Array initializer of FB peripheral base addresses */
6428#define FB_BASE_ADDRS { FB_BASE }
6429/** Array initializer of FB peripheral base pointers */
6430#define FB_BASE_PTRS { FB }
6431
6432/*!
6433 * @}
6434 */ /* end of group FB_Peripheral_Access_Layer */
6435
6436
6437/* ----------------------------------------------------------------------------
6438 -- FGPIO Peripheral Access Layer
6439 ---------------------------------------------------------------------------- */
6440
6441/*!
6442 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
6443 * @{
6444 */
6445
6446/** FGPIO - Register Layout Typedef */
6447typedef struct {
6448 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
6449 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
6450 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
6451 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
6452 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
6453 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
6454 uint8_t RESERVED_0[8];
6455 __IO uint32_t BDACP0[4]; /**< Port Byte Domain Access Control Register 0, array offset: 0x20, array step: 0x4 */
6456} FGPIO_Type;
6457
6458/* ----------------------------------------------------------------------------
6459 -- FGPIO Register Masks
6460 ---------------------------------------------------------------------------- */
6461
6462/*!
6463 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
6464 * @{
6465 */
6466
6467/*! @name PDOR - Port Data Output Register */
6468/*! @{ */
6469#define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
6470#define FGPIO_PDOR_PDO_SHIFT (0U)
6471/*! PDO - Port Data Output
6472 */
6473#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK)
6474/*! @} */
6475
6476/*! @name PSOR - Port Set Output Register */
6477/*! @{ */
6478#define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
6479#define FGPIO_PSOR_PTSO_SHIFT (0U)
6480/*! PTSO - Port Set Output
6481 */
6482#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK)
6483/*! @} */
6484
6485/*! @name PCOR - Port Clear Output Register */
6486/*! @{ */
6487#define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
6488#define FGPIO_PCOR_PTCO_SHIFT (0U)
6489/*! PTCO - Port Clear Output
6490 */
6491#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK)
6492/*! @} */
6493
6494/*! @name PTOR - Port Toggle Output Register */
6495/*! @{ */
6496#define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
6497#define FGPIO_PTOR_PTTO_SHIFT (0U)
6498/*! PTTO - Port Toggle Output
6499 */
6500#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK)
6501/*! @} */
6502
6503/*! @name PDIR - Port Data Input Register */
6504/*! @{ */
6505#define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
6506#define FGPIO_PDIR_PDI_SHIFT (0U)
6507/*! PDI - Port Data Input
6508 */
6509#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK)
6510/*! @} */
6511
6512/*! @name PDDR - Port Data Direction Register */
6513/*! @{ */
6514#define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
6515#define FGPIO_PDDR_PDD_SHIFT (0U)
6516/*! PDD - Port Data Direction
6517 */
6518#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK)
6519/*! @} */
6520
6521/*! @name BDACP0 - Port Byte Domain Access Control Register 0 */
6522/*! @{ */
6523#define FGPIO_BDACP0_D0ACP_MASK (0x7U)
6524#define FGPIO_BDACP0_D0ACP_SHIFT (0U)
6525/*! D0ACP - Domain Access Control Policy
6526 */
6527#define FGPIO_BDACP0_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_D0ACP_SHIFT)) & FGPIO_BDACP0_D0ACP_MASK)
6528#define FGPIO_BDACP0_D1ACP_MASK (0x38U)
6529#define FGPIO_BDACP0_D1ACP_SHIFT (3U)
6530/*! D1ACP - Domain Access Control Policy
6531 */
6532#define FGPIO_BDACP0_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_D1ACP_SHIFT)) & FGPIO_BDACP0_D1ACP_MASK)
6533#define FGPIO_BDACP0_D2ACP_MASK (0x1C0U)
6534#define FGPIO_BDACP0_D2ACP_SHIFT (6U)
6535/*! D2ACP - Domain Access Control Policy
6536 */
6537#define FGPIO_BDACP0_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_D2ACP_SHIFT)) & FGPIO_BDACP0_D2ACP_MASK)
6538#define FGPIO_BDACP0_D3ACP_MASK (0xE00U)
6539#define FGPIO_BDACP0_D3ACP_SHIFT (9U)
6540/*! D3ACP - Domain Access Control Policy
6541 */
6542#define FGPIO_BDACP0_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_D3ACP_SHIFT)) & FGPIO_BDACP0_D3ACP_MASK)
6543#define FGPIO_BDACP0_D4ACP_MASK (0x7000U)
6544#define FGPIO_BDACP0_D4ACP_SHIFT (12U)
6545/*! D4ACP - Domain Access Control Policy
6546 */
6547#define FGPIO_BDACP0_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_D4ACP_SHIFT)) & FGPIO_BDACP0_D4ACP_MASK)
6548#define FGPIO_BDACP0_D5ACP_MASK (0x38000U)
6549#define FGPIO_BDACP0_D5ACP_SHIFT (15U)
6550/*! D5ACP - Domain Access Control Policy
6551 */
6552#define FGPIO_BDACP0_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_D5ACP_SHIFT)) & FGPIO_BDACP0_D5ACP_MASK)
6553#define FGPIO_BDACP0_D6ACP_MASK (0x1C0000U)
6554#define FGPIO_BDACP0_D6ACP_SHIFT (18U)
6555/*! D6ACP - Domain Access Control Policy
6556 */
6557#define FGPIO_BDACP0_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_D6ACP_SHIFT)) & FGPIO_BDACP0_D6ACP_MASK)
6558#define FGPIO_BDACP0_D7ACP_MASK (0xE00000U)
6559#define FGPIO_BDACP0_D7ACP_SHIFT (21U)
6560/*! D7ACP - Domain Access Control Policy
6561 */
6562#define FGPIO_BDACP0_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_D7ACP_SHIFT)) & FGPIO_BDACP0_D7ACP_MASK)
6563#define FGPIO_BDACP0_LK2_MASK (0x60000000U)
6564#define FGPIO_BDACP0_LK2_SHIFT (29U)
6565/*! LK2 - LK2
6566 * 0b00..Entire DxACP can be written.
6567 * 0b01..Entire DxACP can be written.
6568 * 0b10..Domain x can only update the DxACP field; no other D*ACP fields can be written.
6569 * 0b11..DxACP is locked (read-only) until the next reset.
6570 */
6571#define FGPIO_BDACP0_LK2(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_LK2_SHIFT)) & FGPIO_BDACP0_LK2_MASK)
6572#define FGPIO_BDACP0_VLD_MASK (0x80000000U)
6573#define FGPIO_BDACP0_VLD_SHIFT (31U)
6574/*! VLD - Valid
6575 * 0b0..The DxACP assignment is invalid.
6576 * 0b1..The DxACP assignment is valid.
6577 */
6578#define FGPIO_BDACP0_VLD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_VLD_SHIFT)) & FGPIO_BDACP0_VLD_MASK)
6579/*! @} */
6580
6581/* The count of FGPIO_BDACP0 */
6582#define FGPIO_BDACP0_COUNT (4U)
6583
6584
6585/*!
6586 * @}
6587 */ /* end of group FGPIO_Register_Masks */
6588
6589
6590/* FGPIO - Peripheral instance base addresses */
6591/** Peripheral FGPIOA base address */
6592#define FGPIOA_BASE (0xF9000000u)
6593/** Peripheral FGPIOA base pointer */
6594#define FGPIOA ((FGPIO_Type *)FGPIOA_BASE)
6595/** Peripheral FGPIOB base address */
6596#define FGPIOB_BASE (0xF9000040u)
6597/** Peripheral FGPIOB base pointer */
6598#define FGPIOB ((FGPIO_Type *)FGPIOB_BASE)
6599/** Array initializer of FGPIO peripheral base addresses */
6600#define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOB_BASE }
6601/** Array initializer of FGPIO peripheral base pointers */
6602#define FGPIO_BASE_PTRS { FGPIOA, FGPIOB }
6603
6604/*!
6605 * @}
6606 */ /* end of group FGPIO_Peripheral_Access_Layer */
6607
6608
6609/* ----------------------------------------------------------------------------
6610 -- FLEXIO Peripheral Access Layer
6611 ---------------------------------------------------------------------------- */
6612
6613/*!
6614 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
6615 * @{
6616 */
6617
6618/** FLEXIO - Register Layout Typedef */
6619typedef struct {
6620 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
6621 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
6622 __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
6623 __I uint32_t PIN; /**< Pin State Register, offset: 0xC */
6624 __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
6625 __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
6626 __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
6627 uint8_t RESERVED_0[4];
6628 __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
6629 __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
6630 __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
6631 uint8_t RESERVED_1[4];
6632 __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
6633 uint8_t RESERVED_2[12];
6634 __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */
6635 uint8_t RESERVED_3[60];
6636 __IO uint32_t SHIFTCTL[8]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
6637 uint8_t RESERVED_4[96];
6638 __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
6639 uint8_t RESERVED_5[224];
6640 __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
6641 uint8_t RESERVED_6[96];
6642 __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
6643 uint8_t RESERVED_7[96];
6644 __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
6645 uint8_t RESERVED_8[96];
6646 __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
6647 uint8_t RESERVED_9[96];
6648 __IO uint32_t TIMCTL[8]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
6649 uint8_t RESERVED_10[96];
6650 __IO uint32_t TIMCFG[8]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
6651 uint8_t RESERVED_11[96];
6652 __IO uint32_t TIMCMP[8]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
6653 uint8_t RESERVED_12[352];
6654 __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
6655 uint8_t RESERVED_13[96];
6656 __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
6657 uint8_t RESERVED_14[96];
6658 __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
6659} FLEXIO_Type;
6660
6661/* ----------------------------------------------------------------------------
6662 -- FLEXIO Register Masks
6663 ---------------------------------------------------------------------------- */
6664
6665/*!
6666 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
6667 * @{
6668 */
6669
6670/*! @name VERID - Version ID Register */
6671/*! @{ */
6672#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
6673#define FLEXIO_VERID_FEATURE_SHIFT (0U)
6674/*! FEATURE - Feature Specification Number
6675 * 0b0000000000000000..Standard features implemented.
6676 * 0b0000000000000001..Supports state, logic and parallel modes.
6677 */
6678#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
6679#define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
6680#define FLEXIO_VERID_MINOR_SHIFT (16U)
6681/*! MINOR - Minor Version Number
6682 */
6683#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
6684#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
6685#define FLEXIO_VERID_MAJOR_SHIFT (24U)
6686/*! MAJOR - Major Version Number
6687 */
6688#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
6689/*! @} */
6690
6691/*! @name PARAM - Parameter Register */
6692/*! @{ */
6693#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
6694#define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
6695/*! SHIFTER - Shifter Number
6696 */
6697#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
6698#define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
6699#define FLEXIO_PARAM_TIMER_SHIFT (8U)
6700/*! TIMER - Timer Number
6701 */
6702#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
6703#define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
6704#define FLEXIO_PARAM_PIN_SHIFT (16U)
6705/*! PIN - Pin Number
6706 */
6707#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
6708#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
6709#define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
6710/*! TRIGGER - Trigger Number
6711 */
6712#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
6713/*! @} */
6714
6715/*! @name CTRL - FlexIO Control Register */
6716/*! @{ */
6717#define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
6718#define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
6719/*! FLEXEN - FlexIO Enable
6720 * 0b0..FlexIO module is disabled.
6721 * 0b1..FlexIO module is enabled.
6722 */
6723#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
6724#define FLEXIO_CTRL_SWRST_MASK (0x2U)
6725#define FLEXIO_CTRL_SWRST_SHIFT (1U)
6726/*! SWRST - Software Reset
6727 * 0b0..Software reset is disabled
6728 * 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
6729 */
6730#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
6731#define FLEXIO_CTRL_FASTACC_MASK (0x4U)
6732#define FLEXIO_CTRL_FASTACC_SHIFT (2U)
6733/*! FASTACC - Fast Access
6734 * 0b0..Configures for normal register accesses to FlexIO
6735 * 0b1..Configures for fast register accesses to FlexIO
6736 */
6737#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
6738#define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
6739#define FLEXIO_CTRL_DBGE_SHIFT (30U)
6740/*! DBGE - Debug Enable
6741 * 0b0..FlexIO is disabled in debug modes.
6742 * 0b1..FlexIO is enabled in debug modes
6743 */
6744#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
6745#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
6746#define FLEXIO_CTRL_DOZEN_SHIFT (31U)
6747/*! DOZEN - Doze Enable
6748 * 0b0..FlexIO enabled in Doze modes.
6749 * 0b1..FlexIO disabled in Doze modes.
6750 */
6751#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
6752/*! @} */
6753
6754/*! @name PIN - Pin State Register */
6755/*! @{ */
6756#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU)
6757#define FLEXIO_PIN_PDI_SHIFT (0U)
6758/*! PDI - Pin Data Input
6759 */
6760#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
6761/*! @} */
6762
6763/*! @name SHIFTSTAT - Shifter Status Register */
6764/*! @{ */
6765#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU)
6766#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
6767/*! SSF - Shifter Status Flag
6768 */
6769#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
6770/*! @} */
6771
6772/*! @name SHIFTERR - Shifter Error Register */
6773/*! @{ */
6774#define FLEXIO_SHIFTERR_SEF_MASK (0xFFU)
6775#define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
6776/*! SEF - Shifter Error Flags
6777 */
6778#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
6779/*! @} */
6780
6781/*! @name TIMSTAT - Timer Status Register */
6782/*! @{ */
6783#define FLEXIO_TIMSTAT_TSF_MASK (0xFFU)
6784#define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
6785/*! TSF - Timer Status Flags
6786 */
6787#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
6788/*! @} */
6789
6790/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
6791/*! @{ */
6792#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU)
6793#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
6794/*! SSIE - Shifter Status Interrupt Enable
6795 */
6796#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
6797/*! @} */
6798
6799/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
6800/*! @{ */
6801#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU)
6802#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
6803/*! SEIE - Shifter Error Interrupt Enable
6804 */
6805#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
6806/*! @} */
6807
6808/*! @name TIMIEN - Timer Interrupt Enable Register */
6809/*! @{ */
6810#define FLEXIO_TIMIEN_TEIE_MASK (0xFFU)
6811#define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
6812/*! TEIE - Timer Status Interrupt Enable
6813 */
6814#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
6815/*! @} */
6816
6817/*! @name SHIFTSDEN - Shifter Status DMA Enable */
6818/*! @{ */
6819#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU)
6820#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
6821/*! SSDE - Shifter Status DMA Enable
6822 */
6823#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
6824/*! @} */
6825
6826/*! @name SHIFTSTATE - Shifter State Register */
6827/*! @{ */
6828#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U)
6829#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U)
6830/*! STATE - Current State Pointer
6831 */
6832#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
6833/*! @} */
6834
6835/*! @name SHIFTCTL - Shifter Control N Register */
6836/*! @{ */
6837#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
6838#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
6839/*! SMOD - Shifter Mode
6840 * 0b000..Disabled.
6841 * 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
6842 * 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
6843 * 0b011..Reserved.
6844 * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
6845 * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
6846 * 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes.
6847 * 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
6848 */
6849#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
6850#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
6851#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
6852/*! PINPOL - Shifter Pin Polarity
6853 * 0b0..Pin is active high
6854 * 0b1..Pin is active low
6855 */
6856#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
6857#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U)
6858#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
6859/*! PINSEL - Shifter Pin Select
6860 */
6861#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
6862#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
6863#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
6864/*! PINCFG - Shifter Pin Configuration
6865 * 0b00..Shifter pin output disabled
6866 * 0b01..Shifter pin open drain or bidirectional output enable
6867 * 0b10..Shifter pin bidirectional output data
6868 * 0b11..Shifter pin output
6869 */
6870#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
6871#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
6872#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
6873/*! TIMPOL - Timer Polarity
6874 * 0b0..Shift on posedge of Shift clock
6875 * 0b1..Shift on negedge of Shift clock
6876 */
6877#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
6878#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U)
6879#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
6880/*! TIMSEL - Timer Select
6881 */
6882#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
6883/*! @} */
6884
6885/* The count of FLEXIO_SHIFTCTL */
6886#define FLEXIO_SHIFTCTL_COUNT (8U)
6887
6888/*! @name SHIFTCFG - Shifter Configuration N Register */
6889/*! @{ */
6890#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
6891#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
6892/*! SSTART - Shifter Start bit
6893 * 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
6894 * 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
6895 * 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
6896 * 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
6897 */
6898#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
6899#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
6900#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
6901/*! SSTOP - Shifter Stop bit
6902 * 0b00..Stop bit disabled for transmitter/receiver/match store
6903 * 0b01..Reserved for transmitter/receiver/match store
6904 * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
6905 * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
6906 */
6907#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
6908#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
6909#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
6910/*! INSRC - Input Source
6911 * 0b0..Pin
6912 * 0b1..Shifter N+1 Output
6913 */
6914#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
6915#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U)
6916#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)
6917/*! PWIDTH - Parallel Width
6918 */
6919#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
6920/*! @} */
6921
6922/* The count of FLEXIO_SHIFTCFG */
6923#define FLEXIO_SHIFTCFG_COUNT (8U)
6924
6925/*! @name SHIFTBUF - Shifter Buffer N Register */
6926/*! @{ */
6927#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
6928#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
6929/*! SHIFTBUF - Shift Buffer
6930 */
6931#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
6932/*! @} */
6933
6934/* The count of FLEXIO_SHIFTBUF */
6935#define FLEXIO_SHIFTBUF_COUNT (8U)
6936
6937/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
6938/*! @{ */
6939#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
6940#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
6941/*! SHIFTBUFBIS - Shift Buffer
6942 */
6943#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
6944/*! @} */
6945
6946/* The count of FLEXIO_SHIFTBUFBIS */
6947#define FLEXIO_SHIFTBUFBIS_COUNT (8U)
6948
6949/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
6950/*! @{ */
6951#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
6952#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
6953/*! SHIFTBUFBYS - Shift Buffer
6954 */
6955#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
6956/*! @} */
6957
6958/* The count of FLEXIO_SHIFTBUFBYS */
6959#define FLEXIO_SHIFTBUFBYS_COUNT (8U)
6960
6961/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
6962/*! @{ */
6963#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
6964#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
6965/*! SHIFTBUFBBS - Shift Buffer
6966 */
6967#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
6968/*! @} */
6969
6970/* The count of FLEXIO_SHIFTBUFBBS */
6971#define FLEXIO_SHIFTBUFBBS_COUNT (8U)
6972
6973/*! @name TIMCTL - Timer Control N Register */
6974/*! @{ */
6975#define FLEXIO_TIMCTL_TIMOD_MASK (0x3U)
6976#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
6977/*! TIMOD - Timer Mode
6978 * 0b00..Timer Disabled.
6979 * 0b01..Dual 8-bit counters baud mode.
6980 * 0b10..Dual 8-bit counters PWM high mode.
6981 * 0b11..Single 16-bit counter mode.
6982 */
6983#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
6984#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
6985#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
6986/*! PINPOL - Timer Pin Polarity
6987 * 0b0..Pin is active high
6988 * 0b1..Pin is active low
6989 */
6990#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
6991#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U)
6992#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
6993/*! PINSEL - Timer Pin Select
6994 */
6995#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
6996#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
6997#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
6998/*! PINCFG - Timer Pin Configuration
6999 * 0b00..Timer pin output disabled
7000 * 0b01..Timer pin open drain or bidirectional output enable
7001 * 0b10..Timer pin bidirectional output data
7002 * 0b11..Timer pin output
7003 */
7004#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
7005#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
7006#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
7007/*! TRGSRC - Trigger Source
7008 * 0b0..External trigger selected
7009 * 0b1..Internal trigger selected
7010 */
7011#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
7012#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
7013#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
7014/*! TRGPOL - Trigger Polarity
7015 * 0b0..Trigger active high
7016 * 0b1..Trigger active low
7017 */
7018#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
7019#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U)
7020#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
7021/*! TRGSEL - Trigger Select
7022 */
7023#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
7024/*! @} */
7025
7026/* The count of FLEXIO_TIMCTL */
7027#define FLEXIO_TIMCTL_COUNT (8U)
7028
7029/*! @name TIMCFG - Timer Configuration N Register */
7030/*! @{ */
7031#define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
7032#define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
7033/*! TSTART - Timer Start Bit
7034 * 0b0..Start bit disabled
7035 * 0b1..Start bit enabled
7036 */
7037#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
7038#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
7039#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
7040/*! TSTOP - Timer Stop Bit
7041 * 0b00..Stop bit disabled
7042 * 0b01..Stop bit is enabled on timer compare
7043 * 0b10..Stop bit is enabled on timer disable
7044 * 0b11..Stop bit is enabled on timer compare and timer disable
7045 */
7046#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
7047#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
7048#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
7049/*! TIMENA - Timer Enable
7050 * 0b000..Timer always enabled
7051 * 0b001..Timer enabled on Timer N-1 enable
7052 * 0b010..Timer enabled on Trigger high
7053 * 0b011..Timer enabled on Trigger high and Pin high
7054 * 0b100..Timer enabled on Pin rising edge
7055 * 0b101..Timer enabled on Pin rising edge and Trigger high
7056 * 0b110..Timer enabled on Trigger rising edge
7057 * 0b111..Timer enabled on Trigger rising or falling edge
7058 */
7059#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
7060#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
7061#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
7062/*! TIMDIS - Timer Disable
7063 * 0b000..Timer never disabled
7064 * 0b001..Timer disabled on Timer N-1 disable
7065 * 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement)
7066 * 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
7067 * 0b100..Timer disabled on Pin rising or falling edge
7068 * 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
7069 * 0b110..Timer disabled on Trigger falling edge
7070 * 0b111..Reserved
7071 */
7072#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
7073#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
7074#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
7075/*! TIMRST - Timer Reset
7076 * 0b000..Timer never reset
7077 * 0b001..Reserved
7078 * 0b010..Timer reset on Timer Pin equal to Timer Output
7079 * 0b011..Timer reset on Timer Trigger equal to Timer Output
7080 * 0b100..Timer reset on Timer Pin rising edge
7081 * 0b101..Reserved
7082 * 0b110..Timer reset on Trigger rising edge
7083 * 0b111..Timer reset on Trigger rising or falling edge
7084 */
7085#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
7086#define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)
7087#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
7088/*! TIMDEC - Timer Decrement
7089 * 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output.
7090 * 0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
7091 * 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
7092 * 0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
7093 */
7094#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
7095#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
7096#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
7097/*! TIMOUT - Timer Output
7098 * 0b00..Timer output is logic one when enabled and is not affected by timer reset
7099 * 0b01..Timer output is logic zero when enabled and is not affected by timer reset
7100 * 0b10..Timer output is logic one when enabled and on timer reset
7101 * 0b11..Timer output is logic zero when enabled and on timer reset
7102 */
7103#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
7104/*! @} */
7105
7106/* The count of FLEXIO_TIMCFG */
7107#define FLEXIO_TIMCFG_COUNT (8U)
7108
7109/*! @name TIMCMP - Timer Compare N Register */
7110/*! @{ */
7111#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
7112#define FLEXIO_TIMCMP_CMP_SHIFT (0U)
7113/*! CMP - Timer Compare Value
7114 */
7115#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
7116/*! @} */
7117
7118/* The count of FLEXIO_TIMCMP */
7119#define FLEXIO_TIMCMP_COUNT (8U)
7120
7121/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
7122/*! @{ */
7123#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)
7124#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)
7125/*! SHIFTBUFNBS - Shift Buffer
7126 */
7127#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
7128/*! @} */
7129
7130/* The count of FLEXIO_SHIFTBUFNBS */
7131#define FLEXIO_SHIFTBUFNBS_COUNT (8U)
7132
7133/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
7134/*! @{ */
7135#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)
7136#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)
7137/*! SHIFTBUFHWS - Shift Buffer
7138 */
7139#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
7140/*! @} */
7141
7142/* The count of FLEXIO_SHIFTBUFHWS */
7143#define FLEXIO_SHIFTBUFHWS_COUNT (8U)
7144
7145/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
7146/*! @{ */
7147#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)
7148#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)
7149/*! SHIFTBUFNIS - Shift Buffer
7150 */
7151#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
7152/*! @} */
7153
7154/* The count of FLEXIO_SHIFTBUFNIS */
7155#define FLEXIO_SHIFTBUFNIS_COUNT (8U)
7156
7157
7158/*!
7159 * @}
7160 */ /* end of group FLEXIO_Register_Masks */
7161
7162
7163/* FLEXIO - Peripheral instance base addresses */
7164/** Peripheral FLEXIO0 base address */
7165#define FLEXIO0_BASE (0x41032000u)
7166/** Peripheral FLEXIO0 base pointer */
7167#define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE)
7168/** Peripheral FLEXIO1 base address */
7169#define FLEXIO1_BASE (0x40310000u)
7170/** Peripheral FLEXIO1 base pointer */
7171#define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE)
7172/** Array initializer of FLEXIO peripheral base addresses */
7173#define FLEXIO_BASE_ADDRS { FLEXIO0_BASE, FLEXIO1_BASE }
7174/** Array initializer of FLEXIO peripheral base pointers */
7175#define FLEXIO_BASE_PTRS { FLEXIO0, FLEXIO1 }
7176/** Interrupt vectors for the FLEXIO peripheral type */
7177#define FLEXIO_IRQS { FLEXIO0_IRQn, NotAvail_IRQn }
7178
7179/*!
7180 * @}
7181 */ /* end of group FLEXIO_Peripheral_Access_Layer */
7182
7183
7184/* ----------------------------------------------------------------------------
7185 -- GPIO Peripheral Access Layer
7186 ---------------------------------------------------------------------------- */
7187
7188/*!
7189 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
7190 * @{
7191 */
7192
7193/** GPIO - Register Layout Typedef */
7194typedef struct {
7195 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
7196 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
7197 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
7198 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
7199 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
7200 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
7201 uint8_t RESERVED_0[8];
7202 __IO uint32_t BDACP0[4]; /**< Port Byte Domain Access Control Register 0, array offset: 0x20, array step: 0x4 */
7203} GPIO_Type;
7204
7205/* ----------------------------------------------------------------------------
7206 -- GPIO Register Masks
7207 ---------------------------------------------------------------------------- */
7208
7209/*!
7210 * @addtogroup GPIO_Register_Masks GPIO Register Masks
7211 * @{
7212 */
7213
7214/*! @name PDOR - Port Data Output Register */
7215/*! @{ */
7216#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
7217#define GPIO_PDOR_PDO_SHIFT (0U)
7218/*! PDO - Port Data Output
7219 */
7220#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
7221/*! @} */
7222
7223/*! @name PSOR - Port Set Output Register */
7224/*! @{ */
7225#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
7226#define GPIO_PSOR_PTSO_SHIFT (0U)
7227/*! PTSO - Port Set Output
7228 */
7229#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
7230/*! @} */
7231
7232/*! @name PCOR - Port Clear Output Register */
7233/*! @{ */
7234#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
7235#define GPIO_PCOR_PTCO_SHIFT (0U)
7236/*! PTCO - Port Clear Output
7237 */
7238#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
7239/*! @} */
7240
7241/*! @name PTOR - Port Toggle Output Register */
7242/*! @{ */
7243#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
7244#define GPIO_PTOR_PTTO_SHIFT (0U)
7245/*! PTTO - Port Toggle Output
7246 */
7247#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
7248/*! @} */
7249
7250/*! @name PDIR - Port Data Input Register */
7251/*! @{ */
7252#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
7253#define GPIO_PDIR_PDI_SHIFT (0U)
7254/*! PDI - Port Data Input
7255 */
7256#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
7257/*! @} */
7258
7259/*! @name PDDR - Port Data Direction Register */
7260/*! @{ */
7261#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
7262#define GPIO_PDDR_PDD_SHIFT (0U)
7263/*! PDD - Port Data Direction
7264 */
7265#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
7266/*! @} */
7267
7268/*! @name BDACP0 - Port Byte Domain Access Control Register 0 */
7269/*! @{ */
7270#define GPIO_BDACP0_D0ACP_MASK (0x7U)
7271#define GPIO_BDACP0_D0ACP_SHIFT (0U)
7272/*! D0ACP - Domain Access Control Policy
7273 */
7274#define GPIO_BDACP0_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_D0ACP_SHIFT)) & GPIO_BDACP0_D0ACP_MASK)
7275#define GPIO_BDACP0_D1ACP_MASK (0x38U)
7276#define GPIO_BDACP0_D1ACP_SHIFT (3U)
7277/*! D1ACP - Domain Access Control Policy
7278 */
7279#define GPIO_BDACP0_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_D1ACP_SHIFT)) & GPIO_BDACP0_D1ACP_MASK)
7280#define GPIO_BDACP0_D2ACP_MASK (0x1C0U)
7281#define GPIO_BDACP0_D2ACP_SHIFT (6U)
7282/*! D2ACP - Domain Access Control Policy
7283 */
7284#define GPIO_BDACP0_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_D2ACP_SHIFT)) & GPIO_BDACP0_D2ACP_MASK)
7285#define GPIO_BDACP0_D3ACP_MASK (0xE00U)
7286#define GPIO_BDACP0_D3ACP_SHIFT (9U)
7287/*! D3ACP - Domain Access Control Policy
7288 */
7289#define GPIO_BDACP0_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_D3ACP_SHIFT)) & GPIO_BDACP0_D3ACP_MASK)
7290#define GPIO_BDACP0_D4ACP_MASK (0x7000U)
7291#define GPIO_BDACP0_D4ACP_SHIFT (12U)
7292/*! D4ACP - Domain Access Control Policy
7293 */
7294#define GPIO_BDACP0_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_D4ACP_SHIFT)) & GPIO_BDACP0_D4ACP_MASK)
7295#define GPIO_BDACP0_D5ACP_MASK (0x38000U)
7296#define GPIO_BDACP0_D5ACP_SHIFT (15U)
7297/*! D5ACP - Domain Access Control Policy
7298 */
7299#define GPIO_BDACP0_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_D5ACP_SHIFT)) & GPIO_BDACP0_D5ACP_MASK)
7300#define GPIO_BDACP0_D6ACP_MASK (0x1C0000U)
7301#define GPIO_BDACP0_D6ACP_SHIFT (18U)
7302/*! D6ACP - Domain Access Control Policy
7303 */
7304#define GPIO_BDACP0_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_D6ACP_SHIFT)) & GPIO_BDACP0_D6ACP_MASK)
7305#define GPIO_BDACP0_D7ACP_MASK (0xE00000U)
7306#define GPIO_BDACP0_D7ACP_SHIFT (21U)
7307/*! D7ACP - Domain Access Control Policy
7308 */
7309#define GPIO_BDACP0_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_D7ACP_SHIFT)) & GPIO_BDACP0_D7ACP_MASK)
7310#define GPIO_BDACP0_LK2_MASK (0x60000000U)
7311#define GPIO_BDACP0_LK2_SHIFT (29U)
7312/*! LK2 - LK2
7313 * 0b00..Entire DxACP can be written.
7314 * 0b01..Entire DxACP can be written.
7315 * 0b10..Domain x can only update the DxACP field; no other D*ACP fields can be written.
7316 * 0b11..DxACP is locked (read-only) until the next reset.
7317 */
7318#define GPIO_BDACP0_LK2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_LK2_SHIFT)) & GPIO_BDACP0_LK2_MASK)
7319#define GPIO_BDACP0_VLD_MASK (0x80000000U)
7320#define GPIO_BDACP0_VLD_SHIFT (31U)
7321/*! VLD - Valid
7322 * 0b0..The DxACP assignment is invalid.
7323 * 0b1..The DxACP assignment is valid.
7324 */
7325#define GPIO_BDACP0_VLD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_VLD_SHIFT)) & GPIO_BDACP0_VLD_MASK)
7326/*! @} */
7327
7328/* The count of GPIO_BDACP0 */
7329#define GPIO_BDACP0_COUNT (4U)
7330
7331
7332/*!
7333 * @}
7334 */ /* end of group GPIO_Register_Masks */
7335
7336
7337/* GPIO - Peripheral instance base addresses */
7338/** Peripheral GPIOA base address */
7339#define GPIOA_BASE (0x4100F000u)
7340/** Peripheral GPIOA base pointer */
7341#define GPIOA ((GPIO_Type *)GPIOA_BASE)
7342/** Peripheral GPIOB base address */
7343#define GPIOB_BASE (0x4100F040u)
7344/** Peripheral GPIOB base pointer */
7345#define GPIOB ((GPIO_Type *)GPIOB_BASE)
7346/** Peripheral GPIOC base address */
7347#define GPIOC_BASE (0x400F0000u)
7348/** Peripheral GPIOC base pointer */
7349#define GPIOC ((GPIO_Type *)GPIOC_BASE)
7350/** Peripheral GPIOD base address */
7351#define GPIOD_BASE (0x400F0040u)
7352/** Peripheral GPIOD base pointer */
7353#define GPIOD ((GPIO_Type *)GPIOD_BASE)
7354/** Peripheral GPIOE base address */
7355#define GPIOE_BASE (0x400F0080u)
7356/** Peripheral GPIOE base pointer */
7357#define GPIOE ((GPIO_Type *)GPIOE_BASE)
7358/** Peripheral GPIOF base address */
7359#define GPIOF_BASE (0x400F00C0u)
7360/** Peripheral GPIOF base pointer */
7361#define GPIOF ((GPIO_Type *)GPIOF_BASE)
7362/** Array initializer of GPIO peripheral base addresses */
7363#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE, GPIOF_BASE }
7364/** Array initializer of GPIO peripheral base pointers */
7365#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF }
7366
7367/*!
7368 * @}
7369 */ /* end of group GPIO_Peripheral_Access_Layer */
7370
7371
7372/* ----------------------------------------------------------------------------
7373 -- I2S Peripheral Access Layer
7374 ---------------------------------------------------------------------------- */
7375
7376/*!
7377 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
7378 * @{
7379 */
7380
7381/** I2S - Register Layout Typedef */
7382typedef struct {
7383 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
7384 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
7385 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */
7386 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */
7387 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */
7388 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */
7389 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */
7390 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */
7391 __O uint32_t TDR[4]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
7392 uint8_t RESERVED_0[16];
7393 __I uint32_t TFR[4]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
7394 uint8_t RESERVED_1[16];
7395 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
7396 uint8_t RESERVED_2[36];
7397 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */
7398 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */
7399 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */
7400 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */
7401 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */
7402 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */
7403 __I uint32_t RDR[4]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
7404 uint8_t RESERVED_3[16];
7405 __I uint32_t RFR[4]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
7406 uint8_t RESERVED_4[16];
7407 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
7408} I2S_Type;
7409
7410/* ----------------------------------------------------------------------------
7411 -- I2S Register Masks
7412 ---------------------------------------------------------------------------- */
7413
7414/*!
7415 * @addtogroup I2S_Register_Masks I2S Register Masks
7416 * @{
7417 */
7418
7419/*! @name VERID - Version ID Register */
7420/*! @{ */
7421#define I2S_VERID_FEATURE_MASK (0xFFFFU)
7422#define I2S_VERID_FEATURE_SHIFT (0U)
7423/*! FEATURE - Feature Specification Number
7424 * 0b0000000000000000..Standard feature set.
7425 */
7426#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
7427#define I2S_VERID_MINOR_MASK (0xFF0000U)
7428#define I2S_VERID_MINOR_SHIFT (16U)
7429/*! MINOR - Minor Version Number
7430 */
7431#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
7432#define I2S_VERID_MAJOR_MASK (0xFF000000U)
7433#define I2S_VERID_MAJOR_SHIFT (24U)
7434/*! MAJOR - Major Version Number
7435 */
7436#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
7437/*! @} */
7438
7439/*! @name PARAM - Parameter Register */
7440/*! @{ */
7441#define I2S_PARAM_DATALINE_MASK (0xFU)
7442#define I2S_PARAM_DATALINE_SHIFT (0U)
7443/*! DATALINE - Number of Datalines
7444 */
7445#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
7446#define I2S_PARAM_FIFO_MASK (0xF00U)
7447#define I2S_PARAM_FIFO_SHIFT (8U)
7448/*! FIFO - FIFO Size
7449 */
7450#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
7451#define I2S_PARAM_FRAME_MASK (0xF0000U)
7452#define I2S_PARAM_FRAME_SHIFT (16U)
7453/*! FRAME - Frame Size
7454 */
7455#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
7456/*! @} */
7457
7458/*! @name TCSR - SAI Transmit Control Register */
7459/*! @{ */
7460#define I2S_TCSR_FRDE_MASK (0x1U)
7461#define I2S_TCSR_FRDE_SHIFT (0U)
7462/*! FRDE - FIFO Request DMA Enable
7463 * 0b0..Disables the DMA request.
7464 * 0b1..Enables the DMA request.
7465 */
7466#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
7467#define I2S_TCSR_FWDE_MASK (0x2U)
7468#define I2S_TCSR_FWDE_SHIFT (1U)
7469/*! FWDE - FIFO Warning DMA Enable
7470 * 0b0..Disables the DMA request.
7471 * 0b1..Enables the DMA request.
7472 */
7473#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
7474#define I2S_TCSR_FRIE_MASK (0x100U)
7475#define I2S_TCSR_FRIE_SHIFT (8U)
7476/*! FRIE - FIFO Request Interrupt Enable
7477 * 0b0..Disables the interrupt.
7478 * 0b1..Enables the interrupt.
7479 */
7480#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
7481#define I2S_TCSR_FWIE_MASK (0x200U)
7482#define I2S_TCSR_FWIE_SHIFT (9U)
7483/*! FWIE - FIFO Warning Interrupt Enable
7484 * 0b0..Disables the interrupt.
7485 * 0b1..Enables the interrupt.
7486 */
7487#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
7488#define I2S_TCSR_FEIE_MASK (0x400U)
7489#define I2S_TCSR_FEIE_SHIFT (10U)
7490/*! FEIE - FIFO Error Interrupt Enable
7491 * 0b0..Disables the interrupt.
7492 * 0b1..Enables the interrupt.
7493 */
7494#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
7495#define I2S_TCSR_SEIE_MASK (0x800U)
7496#define I2S_TCSR_SEIE_SHIFT (11U)
7497/*! SEIE - Sync Error Interrupt Enable
7498 * 0b0..Disables interrupt.
7499 * 0b1..Enables interrupt.
7500 */
7501#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
7502#define I2S_TCSR_WSIE_MASK (0x1000U)
7503#define I2S_TCSR_WSIE_SHIFT (12U)
7504/*! WSIE - Word Start Interrupt Enable
7505 * 0b0..Disables interrupt.
7506 * 0b1..Enables interrupt.
7507 */
7508#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
7509#define I2S_TCSR_FRF_MASK (0x10000U)
7510#define I2S_TCSR_FRF_SHIFT (16U)
7511/*! FRF - FIFO Request Flag
7512 * 0b0..Transmit FIFO watermark has not been reached.
7513 * 0b1..Transmit FIFO watermark has been reached.
7514 */
7515#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
7516#define I2S_TCSR_FWF_MASK (0x20000U)
7517#define I2S_TCSR_FWF_SHIFT (17U)
7518/*! FWF - FIFO Warning Flag
7519 * 0b0..No enabled transmit FIFO is empty.
7520 * 0b1..Enabled transmit FIFO is empty.
7521 */
7522#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
7523#define I2S_TCSR_FEF_MASK (0x40000U)
7524#define I2S_TCSR_FEF_SHIFT (18U)
7525/*! FEF - FIFO Error Flag
7526 * 0b0..Transmit underrun not detected.
7527 * 0b1..Transmit underrun detected.
7528 */
7529#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
7530#define I2S_TCSR_SEF_MASK (0x80000U)
7531#define I2S_TCSR_SEF_SHIFT (19U)
7532/*! SEF - Sync Error Flag
7533 * 0b0..Sync error not detected.
7534 * 0b1..Frame sync error detected.
7535 */
7536#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
7537#define I2S_TCSR_WSF_MASK (0x100000U)
7538#define I2S_TCSR_WSF_SHIFT (20U)
7539/*! WSF - Word Start Flag
7540 * 0b0..Start of word not detected.
7541 * 0b1..Start of word detected.
7542 */
7543#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
7544#define I2S_TCSR_SR_MASK (0x1000000U)
7545#define I2S_TCSR_SR_SHIFT (24U)
7546/*! SR - Software Reset
7547 * 0b0..No effect.
7548 * 0b1..Software reset.
7549 */
7550#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
7551#define I2S_TCSR_FR_MASK (0x2000000U)
7552#define I2S_TCSR_FR_SHIFT (25U)
7553/*! FR - FIFO Reset
7554 * 0b0..No effect.
7555 * 0b1..FIFO reset.
7556 */
7557#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
7558#define I2S_TCSR_BCE_MASK (0x10000000U)
7559#define I2S_TCSR_BCE_SHIFT (28U)
7560/*! BCE - Bit Clock Enable
7561 * 0b0..Transmit bit clock is disabled.
7562 * 0b1..Transmit bit clock is enabled.
7563 */
7564#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
7565#define I2S_TCSR_DBGE_MASK (0x20000000U)
7566#define I2S_TCSR_DBGE_SHIFT (29U)
7567/*! DBGE - Debug Enable
7568 * 0b0..Transmitter is disabled in Debug mode, after completing the current frame.
7569 * 0b1..Transmitter is enabled in Debug mode.
7570 */
7571#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
7572#define I2S_TCSR_STOPE_MASK (0x40000000U)
7573#define I2S_TCSR_STOPE_SHIFT (30U)
7574/*! STOPE - Stop Enable
7575 * 0b0..Transmitter disabled in Stop mode.
7576 * 0b1..Transmitter enabled in Stop mode.
7577 */
7578#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
7579#define I2S_TCSR_TE_MASK (0x80000000U)
7580#define I2S_TCSR_TE_SHIFT (31U)
7581/*! TE - Transmitter Enable
7582 * 0b0..Transmitter is disabled.
7583 * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
7584 */
7585#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
7586/*! @} */
7587
7588/*! @name TCR1 - SAI Transmit Configuration 1 Register */
7589/*! @{ */
7590#define I2S_TCR1_TFW_MASK (0xFU)
7591#define I2S_TCR1_TFW_SHIFT (0U)
7592/*! TFW - Transmit FIFO Watermark
7593 */
7594#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
7595/*! @} */
7596
7597/*! @name TCR2 - SAI Transmit Configuration 2 Register */
7598/*! @{ */
7599#define I2S_TCR2_DIV_MASK (0xFFU)
7600#define I2S_TCR2_DIV_SHIFT (0U)
7601/*! DIV - Bit Clock Divide
7602 */
7603#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
7604#define I2S_TCR2_BCD_MASK (0x1000000U)
7605#define I2S_TCR2_BCD_SHIFT (24U)
7606/*! BCD - Bit Clock Direction
7607 * 0b0..Bit clock is generated externally in Slave mode.
7608 * 0b1..Bit clock is generated internally in Master mode.
7609 */
7610#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
7611#define I2S_TCR2_BCP_MASK (0x2000000U)
7612#define I2S_TCR2_BCP_SHIFT (25U)
7613/*! BCP - Bit Clock Polarity
7614 * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
7615 * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
7616 */
7617#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
7618#define I2S_TCR2_MSEL_MASK (0xC000000U)
7619#define I2S_TCR2_MSEL_SHIFT (26U)
7620/*! MSEL - MCLK Select
7621 * 0b00..Bus Clock selected.
7622 * 0b01..Master Clock (MCLK) 1 option selected.
7623 * 0b10..Master Clock (MCLK) 2 option selected.
7624 * 0b11..Master Clock (MCLK) 3 option selected.
7625 */
7626#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
7627#define I2S_TCR2_BCI_MASK (0x10000000U)
7628#define I2S_TCR2_BCI_SHIFT (28U)
7629/*! BCI - Bit Clock Input
7630 * 0b0..No effect.
7631 * 0b1..Internal logic is clocked as if bit clock was externally generated.
7632 */
7633#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
7634#define I2S_TCR2_BCS_MASK (0x20000000U)
7635#define I2S_TCR2_BCS_SHIFT (29U)
7636/*! BCS - Bit Clock Swap
7637 * 0b0..Use the normal bit clock source.
7638 * 0b1..Swap the bit clock source.
7639 */
7640#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
7641#define I2S_TCR2_SYNC_MASK (0xC0000000U)
7642#define I2S_TCR2_SYNC_SHIFT (30U)
7643/*! SYNC - Synchronous Mode
7644 * 0b00..Asynchronous mode.
7645 * 0b01..Synchronous with receiver.
7646 * 0b10..Synchronous with another SAI transmitter.
7647 * 0b11..Synchronous with another SAI receiver.
7648 */
7649#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
7650/*! @} */
7651
7652/*! @name TCR3 - SAI Transmit Configuration 3 Register */
7653/*! @{ */
7654#define I2S_TCR3_WDFL_MASK (0x1FU)
7655#define I2S_TCR3_WDFL_SHIFT (0U)
7656/*! WDFL - Word Flag Configuration
7657 */
7658#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
7659#define I2S_TCR3_TCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
7660#define I2S_TCR3_TCE_SHIFT (16U)
7661/*! TCE - Transmit Channel Enable
7662 */
7663#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
7664#define I2S_TCR3_CFR_MASK (0xF000000U) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
7665#define I2S_TCR3_CFR_SHIFT (24U)
7666/*! CFR - Channel FIFO Reset
7667 */
7668#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
7669/*! @} */
7670
7671/*! @name TCR4 - SAI Transmit Configuration 4 Register */
7672/*! @{ */
7673#define I2S_TCR4_FSD_MASK (0x1U)
7674#define I2S_TCR4_FSD_SHIFT (0U)
7675/*! FSD - Frame Sync Direction
7676 * 0b0..Frame sync is generated externally in Slave mode.
7677 * 0b1..Frame sync is generated internally in Master mode.
7678 */
7679#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
7680#define I2S_TCR4_FSP_MASK (0x2U)
7681#define I2S_TCR4_FSP_SHIFT (1U)
7682/*! FSP - Frame Sync Polarity
7683 * 0b0..Frame sync is active high.
7684 * 0b1..Frame sync is active low.
7685 */
7686#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
7687#define I2S_TCR4_ONDEM_MASK (0x4U)
7688#define I2S_TCR4_ONDEM_SHIFT (2U)
7689/*! ONDEM - On Demand Mode
7690 * 0b0..Internal frame sync is generated continuously.
7691 * 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
7692 */
7693#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
7694#define I2S_TCR4_FSE_MASK (0x8U)
7695#define I2S_TCR4_FSE_SHIFT (3U)
7696/*! FSE - Frame Sync Early
7697 * 0b0..Frame sync asserts with the first bit of the frame.
7698 * 0b1..Frame sync asserts one bit before the first bit of the frame.
7699 */
7700#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
7701#define I2S_TCR4_MF_MASK (0x10U)
7702#define I2S_TCR4_MF_SHIFT (4U)
7703/*! MF - MSB First
7704 * 0b0..LSB is transmitted first.
7705 * 0b1..MSB is transmitted first.
7706 */
7707#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
7708#define I2S_TCR4_CHMOD_MASK (0x20U)
7709#define I2S_TCR4_CHMOD_SHIFT (5U)
7710/*! CHMOD - Channel Mode
7711 * 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.
7712 * 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.
7713 */
7714#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
7715#define I2S_TCR4_SYWD_MASK (0x1F00U)
7716#define I2S_TCR4_SYWD_SHIFT (8U)
7717/*! SYWD - Sync Width
7718 */
7719#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
7720#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
7721#define I2S_TCR4_FRSZ_SHIFT (16U)
7722/*! FRSZ - Frame size
7723 */
7724#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
7725#define I2S_TCR4_FPACK_MASK (0x3000000U)
7726#define I2S_TCR4_FPACK_SHIFT (24U)
7727/*! FPACK - FIFO Packing Mode
7728 * 0b00..FIFO packing is disabled
7729 * 0b01..Reserved
7730 * 0b10..8-bit FIFO packing is enabled
7731 * 0b11..16-bit FIFO packing is enabled
7732 */
7733#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
7734#define I2S_TCR4_FCOMB_MASK (0xC000000U)
7735#define I2S_TCR4_FCOMB_SHIFT (26U)
7736/*! FCOMB - FIFO Combine Mode
7737 * 0b00..FIFO combine mode disabled.
7738 * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
7739 * 0b10..FIFO combine mode enabled on FIFO writes (by software).
7740 * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
7741 */
7742#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
7743#define I2S_TCR4_FCONT_MASK (0x10000000U)
7744#define I2S_TCR4_FCONT_SHIFT (28U)
7745/*! FCONT - FIFO Continue on Error
7746 * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
7747 * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
7748 */
7749#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
7750/*! @} */
7751
7752/*! @name TCR5 - SAI Transmit Configuration 5 Register */
7753/*! @{ */
7754#define I2S_TCR5_FBT_MASK (0x1F00U)
7755#define I2S_TCR5_FBT_SHIFT (8U)
7756/*! FBT - First Bit Shifted
7757 */
7758#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
7759#define I2S_TCR5_W0W_MASK (0x1F0000U)
7760#define I2S_TCR5_W0W_SHIFT (16U)
7761/*! W0W - Word 0 Width
7762 */
7763#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
7764#define I2S_TCR5_WNW_MASK (0x1F000000U)
7765#define I2S_TCR5_WNW_SHIFT (24U)
7766/*! WNW - Word N Width
7767 */
7768#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
7769/*! @} */
7770
7771/*! @name TDR - SAI Transmit Data Register */
7772/*! @{ */
7773#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
7774#define I2S_TDR_TDR_SHIFT (0U)
7775/*! TDR - Transmit Data Register
7776 */
7777#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
7778/*! @} */
7779
7780/* The count of I2S_TDR */
7781#define I2S_TDR_COUNT (4U)
7782
7783/*! @name TFR - SAI Transmit FIFO Register */
7784/*! @{ */
7785#define I2S_TFR_RFP_MASK (0x1FU)
7786#define I2S_TFR_RFP_SHIFT (0U)
7787/*! RFP - Read FIFO Pointer
7788 */
7789#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
7790#define I2S_TFR_WFP_MASK (0x1F0000U)
7791#define I2S_TFR_WFP_SHIFT (16U)
7792/*! WFP - Write FIFO Pointer
7793 */
7794#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
7795#define I2S_TFR_WCP_MASK (0x80000000U)
7796#define I2S_TFR_WCP_SHIFT (31U)
7797/*! WCP - Write Channel Pointer
7798 * 0b0..No effect.
7799 * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
7800 */
7801#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
7802/*! @} */
7803
7804/* The count of I2S_TFR */
7805#define I2S_TFR_COUNT (4U)
7806
7807/*! @name TMR - SAI Transmit Mask Register */
7808/*! @{ */
7809#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
7810#define I2S_TMR_TWM_SHIFT (0U)
7811/*! TWM - Transmit Word Mask
7812 * 0b00000000000000000000000000000000..Word N is enabled.
7813 * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.
7814 */
7815#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
7816/*! @} */
7817
7818/*! @name RCSR - SAI Receive Control Register */
7819/*! @{ */
7820#define I2S_RCSR_FRDE_MASK (0x1U)
7821#define I2S_RCSR_FRDE_SHIFT (0U)
7822/*! FRDE - FIFO Request DMA Enable
7823 * 0b0..Disables the DMA request.
7824 * 0b1..Enables the DMA request.
7825 */
7826#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
7827#define I2S_RCSR_FWDE_MASK (0x2U)
7828#define I2S_RCSR_FWDE_SHIFT (1U)
7829/*! FWDE - FIFO Warning DMA Enable
7830 * 0b0..Disables the DMA request.
7831 * 0b1..Enables the DMA request.
7832 */
7833#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
7834#define I2S_RCSR_FRIE_MASK (0x100U)
7835#define I2S_RCSR_FRIE_SHIFT (8U)
7836/*! FRIE - FIFO Request Interrupt Enable
7837 * 0b0..Disables the interrupt.
7838 * 0b1..Enables the interrupt.
7839 */
7840#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
7841#define I2S_RCSR_FWIE_MASK (0x200U)
7842#define I2S_RCSR_FWIE_SHIFT (9U)
7843/*! FWIE - FIFO Warning Interrupt Enable
7844 * 0b0..Disables the interrupt.
7845 * 0b1..Enables the interrupt.
7846 */
7847#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
7848#define I2S_RCSR_FEIE_MASK (0x400U)
7849#define I2S_RCSR_FEIE_SHIFT (10U)
7850/*! FEIE - FIFO Error Interrupt Enable
7851 * 0b0..Disables the interrupt.
7852 * 0b1..Enables the interrupt.
7853 */
7854#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
7855#define I2S_RCSR_SEIE_MASK (0x800U)
7856#define I2S_RCSR_SEIE_SHIFT (11U)
7857/*! SEIE - Sync Error Interrupt Enable
7858 * 0b0..Disables interrupt.
7859 * 0b1..Enables interrupt.
7860 */
7861#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
7862#define I2S_RCSR_WSIE_MASK (0x1000U)
7863#define I2S_RCSR_WSIE_SHIFT (12U)
7864/*! WSIE - Word Start Interrupt Enable
7865 * 0b0..Disables interrupt.
7866 * 0b1..Enables interrupt.
7867 */
7868#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
7869#define I2S_RCSR_FRF_MASK (0x10000U)
7870#define I2S_RCSR_FRF_SHIFT (16U)
7871/*! FRF - FIFO Request Flag
7872 * 0b0..Receive FIFO watermark not reached.
7873 * 0b1..Receive FIFO watermark has been reached.
7874 */
7875#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
7876#define I2S_RCSR_FWF_MASK (0x20000U)
7877#define I2S_RCSR_FWF_SHIFT (17U)
7878/*! FWF - FIFO Warning Flag
7879 * 0b0..No enabled receive FIFO is full.
7880 * 0b1..Enabled receive FIFO is full.
7881 */
7882#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
7883#define I2S_RCSR_FEF_MASK (0x40000U)
7884#define I2S_RCSR_FEF_SHIFT (18U)
7885/*! FEF - FIFO Error Flag
7886 * 0b0..Receive overflow not detected.
7887 * 0b1..Receive overflow detected.
7888 */
7889#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
7890#define I2S_RCSR_SEF_MASK (0x80000U)
7891#define I2S_RCSR_SEF_SHIFT (19U)
7892/*! SEF - Sync Error Flag
7893 * 0b0..Sync error not detected.
7894 * 0b1..Frame sync error detected.
7895 */
7896#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
7897#define I2S_RCSR_WSF_MASK (0x100000U)
7898#define I2S_RCSR_WSF_SHIFT (20U)
7899/*! WSF - Word Start Flag
7900 * 0b0..Start of word not detected.
7901 * 0b1..Start of word detected.
7902 */
7903#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
7904#define I2S_RCSR_SR_MASK (0x1000000U)
7905#define I2S_RCSR_SR_SHIFT (24U)
7906/*! SR - Software Reset
7907 * 0b0..No effect.
7908 * 0b1..Software reset.
7909 */
7910#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
7911#define I2S_RCSR_FR_MASK (0x2000000U)
7912#define I2S_RCSR_FR_SHIFT (25U)
7913/*! FR - FIFO Reset
7914 * 0b0..No effect.
7915 * 0b1..FIFO reset.
7916 */
7917#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
7918#define I2S_RCSR_BCE_MASK (0x10000000U)
7919#define I2S_RCSR_BCE_SHIFT (28U)
7920/*! BCE - Bit Clock Enable
7921 * 0b0..Receive bit clock is disabled.
7922 * 0b1..Receive bit clock is enabled.
7923 */
7924#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
7925#define I2S_RCSR_DBGE_MASK (0x20000000U)
7926#define I2S_RCSR_DBGE_SHIFT (29U)
7927/*! DBGE - Debug Enable
7928 * 0b0..Receiver is disabled in Debug mode, after completing the current frame.
7929 * 0b1..Receiver is enabled in Debug mode.
7930 */
7931#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
7932#define I2S_RCSR_STOPE_MASK (0x40000000U)
7933#define I2S_RCSR_STOPE_SHIFT (30U)
7934/*! STOPE - Stop Enable
7935 * 0b0..Receiver disabled in Stop mode.
7936 * 0b1..Receiver enabled in Stop mode.
7937 */
7938#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
7939#define I2S_RCSR_RE_MASK (0x80000000U)
7940#define I2S_RCSR_RE_SHIFT (31U)
7941/*! RE - Receiver Enable
7942 * 0b0..Receiver is disabled.
7943 * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
7944 */
7945#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
7946/*! @} */
7947
7948/*! @name RCR1 - SAI Receive Configuration 1 Register */
7949/*! @{ */
7950#define I2S_RCR1_RFW_MASK (0xFU)
7951#define I2S_RCR1_RFW_SHIFT (0U)
7952/*! RFW - Receive FIFO Watermark
7953 */
7954#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
7955/*! @} */
7956
7957/*! @name RCR2 - SAI Receive Configuration 2 Register */
7958/*! @{ */
7959#define I2S_RCR2_DIV_MASK (0xFFU)
7960#define I2S_RCR2_DIV_SHIFT (0U)
7961/*! DIV - Bit Clock Divide
7962 */
7963#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
7964#define I2S_RCR2_BCD_MASK (0x1000000U)
7965#define I2S_RCR2_BCD_SHIFT (24U)
7966/*! BCD - Bit Clock Direction
7967 * 0b0..Bit clock is generated externally in Slave mode.
7968 * 0b1..Bit clock is generated internally in Master mode.
7969 */
7970#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
7971#define I2S_RCR2_BCP_MASK (0x2000000U)
7972#define I2S_RCR2_BCP_SHIFT (25U)
7973/*! BCP - Bit Clock Polarity
7974 * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
7975 * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
7976 */
7977#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
7978#define I2S_RCR2_MSEL_MASK (0xC000000U)
7979#define I2S_RCR2_MSEL_SHIFT (26U)
7980/*! MSEL - MCLK Select
7981 * 0b00..Bus Clock selected.
7982 * 0b01..Master Clock (MCLK) 1 option selected.
7983 * 0b10..Master Clock (MCLK) 2 option selected.
7984 * 0b11..Master Clock (MCLK) 3 option selected.
7985 */
7986#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
7987#define I2S_RCR2_BCI_MASK (0x10000000U)
7988#define I2S_RCR2_BCI_SHIFT (28U)
7989/*! BCI - Bit Clock Input
7990 * 0b0..No effect.
7991 * 0b1..Internal logic is clocked as if bit clock was externally generated.
7992 */
7993#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
7994#define I2S_RCR2_BCS_MASK (0x20000000U)
7995#define I2S_RCR2_BCS_SHIFT (29U)
7996/*! BCS - Bit Clock Swap
7997 * 0b0..Use the normal bit clock source.
7998 * 0b1..Swap the bit clock source.
7999 */
8000#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
8001#define I2S_RCR2_SYNC_MASK (0xC0000000U)
8002#define I2S_RCR2_SYNC_SHIFT (30U)
8003/*! SYNC - Synchronous Mode
8004 * 0b00..Asynchronous mode.
8005 * 0b01..Synchronous with transmitter.
8006 * 0b10..Synchronous with another SAI receiver.
8007 * 0b11..Synchronous with another SAI transmitter.
8008 */
8009#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
8010/*! @} */
8011
8012/*! @name RCR3 - SAI Receive Configuration 3 Register */
8013/*! @{ */
8014#define I2S_RCR3_WDFL_MASK (0x1FU)
8015#define I2S_RCR3_WDFL_SHIFT (0U)
8016/*! WDFL - Word Flag Configuration
8017 */
8018#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
8019#define I2S_RCR3_RCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
8020#define I2S_RCR3_RCE_SHIFT (16U)
8021/*! RCE - Receive Channel Enable
8022 */
8023#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
8024#define I2S_RCR3_CFR_MASK (0xF000000U) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
8025#define I2S_RCR3_CFR_SHIFT (24U)
8026/*! CFR - Channel FIFO Reset
8027 */
8028#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
8029/*! @} */
8030
8031/*! @name RCR4 - SAI Receive Configuration 4 Register */
8032/*! @{ */
8033#define I2S_RCR4_FSD_MASK (0x1U)
8034#define I2S_RCR4_FSD_SHIFT (0U)
8035/*! FSD - Frame Sync Direction
8036 * 0b0..Frame Sync is generated externally in Slave mode.
8037 * 0b1..Frame Sync is generated internally in Master mode.
8038 */
8039#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
8040#define I2S_RCR4_FSP_MASK (0x2U)
8041#define I2S_RCR4_FSP_SHIFT (1U)
8042/*! FSP - Frame Sync Polarity
8043 * 0b0..Frame sync is active high.
8044 * 0b1..Frame sync is active low.
8045 */
8046#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
8047#define I2S_RCR4_ONDEM_MASK (0x4U)
8048#define I2S_RCR4_ONDEM_SHIFT (2U)
8049/*! ONDEM - On Demand Mode
8050 * 0b0..Internal frame sync is generated continuously.
8051 * 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
8052 */
8053#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
8054#define I2S_RCR4_FSE_MASK (0x8U)
8055#define I2S_RCR4_FSE_SHIFT (3U)
8056/*! FSE - Frame Sync Early
8057 * 0b0..Frame sync asserts with the first bit of the frame.
8058 * 0b1..Frame sync asserts one bit before the first bit of the frame.
8059 */
8060#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
8061#define I2S_RCR4_MF_MASK (0x10U)
8062#define I2S_RCR4_MF_SHIFT (4U)
8063/*! MF - MSB First
8064 * 0b0..LSB is received first.
8065 * 0b1..MSB is received first.
8066 */
8067#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
8068#define I2S_RCR4_SYWD_MASK (0x1F00U)
8069#define I2S_RCR4_SYWD_SHIFT (8U)
8070/*! SYWD - Sync Width
8071 */
8072#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
8073#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
8074#define I2S_RCR4_FRSZ_SHIFT (16U)
8075/*! FRSZ - Frame Size
8076 */
8077#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
8078#define I2S_RCR4_FPACK_MASK (0x3000000U)
8079#define I2S_RCR4_FPACK_SHIFT (24U)
8080/*! FPACK - FIFO Packing Mode
8081 * 0b00..FIFO packing is disabled
8082 * 0b01..Reserved.
8083 * 0b10..8-bit FIFO packing is enabled
8084 * 0b11..16-bit FIFO packing is enabled
8085 */
8086#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
8087#define I2S_RCR4_FCOMB_MASK (0xC000000U)
8088#define I2S_RCR4_FCOMB_SHIFT (26U)
8089/*! FCOMB - FIFO Combine Mode
8090 * 0b00..FIFO combine mode disabled.
8091 * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
8092 * 0b10..FIFO combine mode enabled on FIFO reads (by software).
8093 * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
8094 */
8095#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
8096#define I2S_RCR4_FCONT_MASK (0x10000000U)
8097#define I2S_RCR4_FCONT_SHIFT (28U)
8098/*! FCONT - FIFO Continue on Error
8099 * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
8100 * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
8101 */
8102#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
8103/*! @} */
8104
8105/*! @name RCR5 - SAI Receive Configuration 5 Register */
8106/*! @{ */
8107#define I2S_RCR5_FBT_MASK (0x1F00U)
8108#define I2S_RCR5_FBT_SHIFT (8U)
8109/*! FBT - First Bit Shifted
8110 */
8111#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
8112#define I2S_RCR5_W0W_MASK (0x1F0000U)
8113#define I2S_RCR5_W0W_SHIFT (16U)
8114/*! W0W - Word 0 Width
8115 */
8116#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
8117#define I2S_RCR5_WNW_MASK (0x1F000000U)
8118#define I2S_RCR5_WNW_SHIFT (24U)
8119/*! WNW - Word N Width
8120 */
8121#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
8122/*! @} */
8123
8124/*! @name RDR - SAI Receive Data Register */
8125/*! @{ */
8126#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
8127#define I2S_RDR_RDR_SHIFT (0U)
8128/*! RDR - Receive Data Register
8129 */
8130#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
8131/*! @} */
8132
8133/* The count of I2S_RDR */
8134#define I2S_RDR_COUNT (4U)
8135
8136/*! @name RFR - SAI Receive FIFO Register */
8137/*! @{ */
8138#define I2S_RFR_RFP_MASK (0x1FU)
8139#define I2S_RFR_RFP_SHIFT (0U)
8140/*! RFP - Read FIFO Pointer
8141 */
8142#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
8143#define I2S_RFR_RCP_MASK (0x8000U)
8144#define I2S_RFR_RCP_SHIFT (15U)
8145/*! RCP - Receive Channel Pointer
8146 * 0b0..No effect.
8147 * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
8148 */
8149#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
8150#define I2S_RFR_WFP_MASK (0x1F0000U)
8151#define I2S_RFR_WFP_SHIFT (16U)
8152/*! WFP - Write FIFO Pointer
8153 */
8154#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
8155/*! @} */
8156
8157/* The count of I2S_RFR */
8158#define I2S_RFR_COUNT (4U)
8159
8160/*! @name RMR - SAI Receive Mask Register */
8161/*! @{ */
8162#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
8163#define I2S_RMR_RWM_SHIFT (0U)
8164/*! RWM - Receive Word Mask
8165 * 0b00000000000000000000000000000000..Word N is enabled.
8166 * 0b00000000000000000000000000000001..Word N is masked.
8167 */
8168#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
8169/*! @} */
8170
8171
8172/*!
8173 * @}
8174 */ /* end of group I2S_Register_Masks */
8175
8176
8177/* I2S - Peripheral instance base addresses */
8178/** Peripheral I2S0 base address */
8179#define I2S0_BASE (0x41037000u)
8180/** Peripheral I2S0 base pointer */
8181#define I2S0 ((I2S_Type *)I2S0_BASE)
8182/** Peripheral I2S1 base address */
8183#define I2S1_BASE (0x410AA000u)
8184/** Peripheral I2S1 base pointer */
8185#define I2S1 ((I2S_Type *)I2S1_BASE)
8186/** Array initializer of I2S peripheral base addresses */
8187#define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE }
8188/** Array initializer of I2S peripheral base pointers */
8189#define I2S_BASE_PTRS { I2S0, I2S1 }
8190/** Interrupt vectors for the I2S peripheral type */
8191#define I2S_RX_IRQS { I2S0_IRQn, I2S1_IRQn }
8192#define I2S_TX_IRQS { I2S0_IRQn, I2S1_IRQn }
8193
8194/*!
8195 * @}
8196 */ /* end of group I2S_Peripheral_Access_Layer */
8197
8198
8199/* ----------------------------------------------------------------------------
8200 -- IOMUXC0 Peripheral Access Layer
8201 ---------------------------------------------------------------------------- */
8202
8203/*!
8204 * @addtogroup IOMUXC0_Peripheral_Access_Layer IOMUXC0 Peripheral Access Layer
8205 * @{
8206 */
8207
8208/** IOMUXC0 - Register Layout Typedef */
8209typedef struct {
8210 __IO uint32_t SW_MUX_CTL_PAD[52]; /**< SW_MUX_CTL_PAD SW MUX Control Register, array offset: 0x0, array step: 0x4 */
8211 uint8_t RESERVED_0[48];
8212 __IO uint32_t SELECT_INPUT[75]; /**< N_SELECT_INPUT_DAISY_Register, array offset: 0x100, array step: 0x4 */
8213 uint8_t RESERVED_1[104];
8214 __IO uint32_t SW_MUX_CTL_PAD_RESET0_b; /**< SW_MUX_CTL_PAD_RESET0_b SW MUX Control Register, offset: 0x294 */
8215} IOMUXC0_Type;
8216
8217/* ----------------------------------------------------------------------------
8218 -- IOMUXC0 Register Masks
8219 ---------------------------------------------------------------------------- */
8220
8221/*!
8222 * @addtogroup IOMUXC0_Register_Masks IOMUXC0 Register Masks
8223 * @{
8224 */
8225
8226/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD SW MUX Control Register */
8227/*! @{ */
8228#define IOMUXC0_SW_MUX_CTL_PAD_PS_MASK (0x1U)
8229#define IOMUXC0_SW_MUX_CTL_PAD_PS_SHIFT (0U)
8230/*! PS - Pull Select Field
8231 * 0b0..pull-down
8232 * 0b1..pull-up
8233 */
8234#define IOMUXC0_SW_MUX_CTL_PAD_PS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_PS_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_PS_MASK)
8235#define IOMUXC0_SW_MUX_CTL_PAD_PE_MASK (0x2U)
8236#define IOMUXC0_SW_MUX_CTL_PAD_PE_SHIFT (1U)
8237/*! PE - Pull Enable field
8238 * 0b0..pull disabled
8239 * 0b1..pull enabled
8240 */
8241#define IOMUXC0_SW_MUX_CTL_PAD_PE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_PE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_PE_MASK)
8242#define IOMUXC0_SW_MUX_CTL_PAD_SRE_MASK (0x4U)
8243#define IOMUXC0_SW_MUX_CTL_PAD_SRE_SHIFT (2U)
8244/*! SRE - Slew Rate Enable Field
8245 * 0b0..Standard
8246 * 0b1..Slow
8247 */
8248#define IOMUXC0_SW_MUX_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_SRE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_SRE_MASK)
8249#define IOMUXC0_SW_MUX_CTL_PAD_ODE_MASK (0x20U)
8250#define IOMUXC0_SW_MUX_CTL_PAD_ODE_SHIFT (5U)
8251/*! ODE - Open-drain Enable Field
8252 * 0b0..Push-pull
8253 * 0b1..Open-drain
8254 */
8255#define IOMUXC0_SW_MUX_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_ODE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_ODE_MASK)
8256#define IOMUXC0_SW_MUX_CTL_PAD_DSE_MASK (0x40U)
8257#define IOMUXC0_SW_MUX_CTL_PAD_DSE_SHIFT (6U)
8258/*! DSE - Drive Strength Enable Field
8259 * 0b0..Standard
8260 * 0b1..Hi Drive
8261 */
8262#define IOMUXC0_SW_MUX_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_DSE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_DSE_MASK)
8263#define IOMUXC0_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xF00U)
8264#define IOMUXC0_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (8U)
8265/*! MUX_MODE - MUX Mode Select Field.
8266 */
8267#define IOMUXC0_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_MUX_MODE_MASK)
8268#define IOMUXC0_SW_MUX_CTL_PAD_LK_MASK (0x8000U)
8269#define IOMUXC0_SW_MUX_CTL_PAD_LK_SHIFT (15U)
8270/*! LK - Lock Field
8271 * 0b0..Disabled
8272 * 0b1..Enabled
8273 */
8274#define IOMUXC0_SW_MUX_CTL_PAD_LK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_LK_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_LK_MASK)
8275#define IOMUXC0_SW_MUX_CTL_PAD_IBE_MASK (0x10000U)
8276#define IOMUXC0_SW_MUX_CTL_PAD_IBE_SHIFT (16U)
8277/*! IBE - Input Buffer Enable Field
8278 * 0b0..Disabled
8279 * 0b1..Enabled
8280 */
8281#define IOMUXC0_SW_MUX_CTL_PAD_IBE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_IBE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_IBE_MASK)
8282#define IOMUXC0_SW_MUX_CTL_PAD_OBE_MASK (0x20000U)
8283#define IOMUXC0_SW_MUX_CTL_PAD_OBE_SHIFT (17U)
8284/*! OBE - Output Buffer Enable Field
8285 * 0b0..Disabled
8286 * 0b1..Enabled
8287 */
8288#define IOMUXC0_SW_MUX_CTL_PAD_OBE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_OBE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_OBE_MASK)
8289#define IOMUXC0_SW_MUX_CTL_PAD_DFE_MASK (0x100000U)
8290#define IOMUXC0_SW_MUX_CTL_PAD_DFE_SHIFT (20U)
8291/*! DFE - Digital Filter Enable Field
8292 * 0b0..Disabled
8293 * 0b1..Enabled
8294 */
8295#define IOMUXC0_SW_MUX_CTL_PAD_DFE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_DFE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_DFE_MASK)
8296#define IOMUXC0_SW_MUX_CTL_PAD_DFCS_MASK (0x200000U)
8297#define IOMUXC0_SW_MUX_CTL_PAD_DFCS_SHIFT (21U)
8298/*! DFCS - Digital Filter Clock Select Field
8299 * 0b0..IPG Clk
8300 * 0b1..1Khz CLK
8301 */
8302#define IOMUXC0_SW_MUX_CTL_PAD_DFCS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_DFCS_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_DFCS_MASK)
8303#define IOMUXC0_SW_MUX_CTL_PAD_DFD_MASK (0x7C00000U)
8304#define IOMUXC0_SW_MUX_CTL_PAD_DFD_SHIFT (22U)
8305/*! DFD - Digital Filter Duration Field
8306 * 0b00000..Disabled
8307 * 0b00001..Count1
8308 * 0b00010..Count2
8309 * 0b00011..Count3
8310 * 0b00100..Count4
8311 * 0b00101..Count5
8312 * 0b00110..Count6
8313 * 0b00111..Count7
8314 * 0b01000..Count8
8315 * 0b01001..Count9
8316 * 0b01010..Count10
8317 * 0b01011..Count11
8318 * 0b01100..Count12
8319 * 0b01101..Count13
8320 * 0b01110..Count14
8321 * 0b01111..Count15
8322 * 0b10000..Count16
8323 * 0b10001..Count17
8324 * 0b10010..Count18
8325 * 0b10011..Count19
8326 * 0b10100..Count20
8327 * 0b10101..Count21
8328 * 0b10110..Count22
8329 * 0b10111..Count23
8330 * 0b11000..Count24
8331 * 0b11001..Count25
8332 * 0b11010..Count26
8333 * 0b11011..Count27
8334 * 0b11100..Count28
8335 * 0b11101..Count29
8336 * 0b11110..Count30
8337 * 0b11111..Count31
8338 */
8339#define IOMUXC0_SW_MUX_CTL_PAD_DFD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_DFD_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_DFD_MASK)
8340/*! @} */
8341
8342/* The count of IOMUXC0_SW_MUX_CTL_PAD */
8343#define IOMUXC0_SW_MUX_CTL_PAD_COUNT (52U)
8344
8345/*! @name SELECT_INPUT - N_SELECT_INPUT_DAISY_Register */
8346/*! @{ */
8347#define IOMUXC0_SELECT_INPUT_DAISY_MASK (0x7U)
8348#define IOMUXC0_SELECT_INPUT_DAISY_SHIFT (0U)
8349/*! DAISY - Selects source pad for Module Input Function. Refer to "Input SSS" column from "Input Mux" tab on IOMUX Sheet.
8350 */
8351#define IOMUXC0_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC0_SELECT_INPUT_DAISY_MASK)
8352#define IOMUXC0_SELECT_INPUT_INVERSION_MASK (0x8000U)
8353#define IOMUXC0_SELECT_INPUT_INVERSION_SHIFT (15U)
8354/*! INVERSION - Controls the inversion of the pad->module input to instance
8355 * 0b0..Disable inversion.
8356 * 0b1..Enable inversion.
8357 */
8358#define IOMUXC0_SELECT_INPUT_INVERSION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SELECT_INPUT_INVERSION_SHIFT)) & IOMUXC0_SELECT_INPUT_INVERSION_MASK)
8359/*! @} */
8360
8361/* The count of IOMUXC0_SELECT_INPUT */
8362#define IOMUXC0_SELECT_INPUT_COUNT (75U)
8363
8364/*! @name SW_MUX_CTL_PAD_RESET0_b - SW_MUX_CTL_PAD_RESET0_b SW MUX Control Register */
8365/*! @{ */
8366#define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PS_MASK (0x1U)
8367#define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PS_SHIFT (0U)
8368/*! PS - Pull Select Field
8369 * 0b0..pull-down
8370 * 0b1..pull-up
8371 */
8372#define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PS_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PS_MASK)
8373#define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PE_MASK (0x2U)
8374#define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PE_SHIFT (1U)
8375/*! PE - Pull Enable field
8376 * 0b0..pull disabled
8377 * 0b1..pull enabled
8378 */
8379#define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PE_MASK)
8380#define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_SRE_MASK (0x4U)
8381#define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_SRE_SHIFT (2U)
8382/*! SRE - Slew Rate Enable Field
8383 * 0b0..Standard
8384 * 0b1..Slow
8385 */
8386#define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_SRE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_SRE_MASK)
8387#define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_ODE_MASK (0x20U)
8388#define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_ODE_SHIFT (5U)
8389/*! ODE - Open-drain Enable Field
8390 * 0b0..Push-pull
8391 * 0b1..Open-drain
8392 */
8393#define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_ODE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_ODE_MASK)
8394#define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_DSE_MASK (0x40U)
8395#define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_DSE_SHIFT (6U)
8396/*! DSE - Drive Strength Enable Field
8397 * 0b0..Standard
8398 * 0b1..Hi Drive
8399 */
8400#define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_DSE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_DSE_MASK)
8401#define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_LK_MASK (0x8000U)
8402#define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_LK_SHIFT (15U)
8403/*! LK - Lock Field
8404 * 0b0..Disabled
8405 * 0b1..Enabled
8406 */
8407#define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_LK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_LK_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_LK_MASK)
8408/*! @} */
8409
8410
8411/*!
8412 * @}
8413 */ /* end of group IOMUXC0_Register_Masks */
8414
8415
8416/* IOMUXC0 - Peripheral instance base addresses */
8417/** Peripheral IOMUXC0 base address */
8418#define IOMUXC0_BASE (0x4103D000u)
8419/** Peripheral IOMUXC0 base pointer */
8420#define IOMUXC0 ((IOMUXC0_Type *)IOMUXC0_BASE)
8421/** Array initializer of IOMUXC0 peripheral base addresses */
8422#define IOMUXC0_BASE_ADDRS { IOMUXC0_BASE }
8423/** Array initializer of IOMUXC0 peripheral base pointers */
8424#define IOMUXC0_BASE_PTRS { IOMUXC0 }
8425
8426/*!
8427 * @}
8428 */ /* end of group IOMUXC0_Peripheral_Access_Layer */
8429
8430
8431/* ----------------------------------------------------------------------------
8432 -- IOMUXC1 Peripheral Access Layer
8433 ---------------------------------------------------------------------------- */
8434
8435/*!
8436 * @addtogroup IOMUXC1_Peripheral_Access_Layer IOMUXC1 Peripheral Access Layer
8437 * @{
8438 */
8439
8440/** IOMUXC1 - Register Layout Typedef */
8441typedef struct {
8442 __IO uint32_t SW_MUX_CTL_PAD[116]; /**< SW_MUX_CTL_PAD SW MUX Control Register, array offset: 0x0, array step: 0x4 */
8443 uint8_t RESERVED_0[48];
8444 __IO uint32_t SELECT_INPUT[80]; /**< N_SELECT_INPUT DAISY Register, array offset: 0x200, array step: 0x4 */
8445 uint8_t RESERVED_1[92];
8446 __IO uint32_t SW_MUX_CTL_PAD_RESET1_b; /**< SW_MUX_CTL_PAD_RESET1_b SW MUX Control Register, offset: 0x39C */
8447} IOMUXC1_Type;
8448
8449/* ----------------------------------------------------------------------------
8450 -- IOMUXC1 Register Masks
8451 ---------------------------------------------------------------------------- */
8452
8453/*!
8454 * @addtogroup IOMUXC1_Register_Masks IOMUXC1 Register Masks
8455 * @{
8456 */
8457
8458/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD SW MUX Control Register */
8459/*! @{ */
8460#define IOMUXC1_SW_MUX_CTL_PAD_PS_MASK (0x1U)
8461#define IOMUXC1_SW_MUX_CTL_PAD_PS_SHIFT (0U)
8462/*! PS - Pull Select Field
8463 * 0b0..pull-down
8464 * 0b1..pull-up
8465 */
8466#define IOMUXC1_SW_MUX_CTL_PAD_PS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_PS_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_PS_MASK)
8467#define IOMUXC1_SW_MUX_CTL_PAD_PE_MASK (0x2U)
8468#define IOMUXC1_SW_MUX_CTL_PAD_PE_SHIFT (1U)
8469/*! PE - Pull-up Enable Field
8470 * 0b0..pull disabled
8471 * 0b1..pull enabled
8472 */
8473#define IOMUXC1_SW_MUX_CTL_PAD_PE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_PE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_PE_MASK)
8474#define IOMUXC1_SW_MUX_CTL_PAD_SRE_MASK (0x4U)
8475#define IOMUXC1_SW_MUX_CTL_PAD_SRE_SHIFT (2U)
8476/*! SRE - Slew Rate Enable Field
8477 * 0b0..Standard
8478 * 0b1..Slow
8479 */
8480#define IOMUXC1_SW_MUX_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_SRE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_SRE_MASK)
8481#define IOMUXC1_SW_MUX_CTL_PAD_ODE_MASK (0x20U)
8482#define IOMUXC1_SW_MUX_CTL_PAD_ODE_SHIFT (5U)
8483/*! ODE - Open-drain Enable Field
8484 * 0b0..Push-pull
8485 * 0b1..Open-drain
8486 */
8487#define IOMUXC1_SW_MUX_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_ODE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_ODE_MASK)
8488#define IOMUXC1_SW_MUX_CTL_PAD_DSE_MASK (0x40U)
8489#define IOMUXC1_SW_MUX_CTL_PAD_DSE_SHIFT (6U)
8490/*! DSE - Drive Strength Enable Field
8491 * 0b0..Standard
8492 * 0b1..Hi Drive
8493 */
8494#define IOMUXC1_SW_MUX_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_DSE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_DSE_MASK)
8495#define IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xF00U)
8496#define IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (8U)
8497/*! MUX_MODE - MUX Mode Select Field.
8498 */
8499#define IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE_MASK)
8500#define IOMUXC1_SW_MUX_CTL_PAD_LK_MASK (0x8000U)
8501#define IOMUXC1_SW_MUX_CTL_PAD_LK_SHIFT (15U)
8502/*! LK - Lock Field
8503 * 0b0..Disabled
8504 * 0b1..Enabled
8505 */
8506#define IOMUXC1_SW_MUX_CTL_PAD_LK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_LK_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_LK_MASK)
8507#define IOMUXC1_SW_MUX_CTL_PAD_IBE_MASK (0x10000U)
8508#define IOMUXC1_SW_MUX_CTL_PAD_IBE_SHIFT (16U)
8509/*! IBE - Input Buffer Enable Field
8510 * 0b0..Disabled
8511 * 0b1..Enabled
8512 */
8513#define IOMUXC1_SW_MUX_CTL_PAD_IBE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_IBE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_IBE_MASK)
8514#define IOMUXC1_SW_MUX_CTL_PAD_OBE_MASK (0x20000U)
8515#define IOMUXC1_SW_MUX_CTL_PAD_OBE_SHIFT (17U)
8516/*! OBE - Output Buffer Enable Field
8517 * 0b0..Disabled
8518 * 0b1..Enabled
8519 */
8520#define IOMUXC1_SW_MUX_CTL_PAD_OBE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_OBE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_OBE_MASK)
8521/*! @} */
8522
8523/* The count of IOMUXC1_SW_MUX_CTL_PAD */
8524#define IOMUXC1_SW_MUX_CTL_PAD_COUNT (116U)
8525
8526/*! @name SELECT_INPUT - N_SELECT_INPUT DAISY Register */
8527/*! @{ */
8528#define IOMUXC1_SELECT_INPUT_DAISY_MASK (0x7U)
8529#define IOMUXC1_SELECT_INPUT_DAISY_SHIFT (0U)
8530/*! DAISY - Selects source pad for Module Input Function. Refer to "Input SSS" column from "Input Mux" tab on IOMUX Sheet.
8531 */
8532#define IOMUXC1_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC1_SELECT_INPUT_DAISY_MASK)
8533#define IOMUXC1_SELECT_INPUT_INVERSION_MASK (0x8000U)
8534#define IOMUXC1_SELECT_INPUT_INVERSION_SHIFT (15U)
8535/*! INVERSION - Control the inversion of the pad->module input
8536 * 0b0..Disable inversion.
8537 * 0b1..Enable inversion.
8538 */
8539#define IOMUXC1_SELECT_INPUT_INVERSION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SELECT_INPUT_INVERSION_SHIFT)) & IOMUXC1_SELECT_INPUT_INVERSION_MASK)
8540/*! @} */
8541
8542/* The count of IOMUXC1_SELECT_INPUT */
8543#define IOMUXC1_SELECT_INPUT_COUNT (80U)
8544
8545/*! @name SW_MUX_CTL_PAD_RESET1_b - SW_MUX_CTL_PAD_RESET1_b SW MUX Control Register */
8546/*! @{ */
8547#define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PS_MASK (0x1U)
8548#define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PS_SHIFT (0U)
8549/*! PS - Pull Select Field
8550 * 0b0..pull-down
8551 * 0b1..pull-up
8552 */
8553#define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PS_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PS_MASK)
8554#define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PE_MASK (0x2U)
8555#define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PE_SHIFT (1U)
8556/*! PE - Pull-up Enable Field
8557 * 0b0..pull disabled
8558 * 0b1..pull enabled
8559 */
8560#define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PE_MASK)
8561#define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_SRE_MASK (0x4U)
8562#define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_SRE_SHIFT (2U)
8563/*! SRE - Slew Rate Enable Field
8564 * 0b0..Standard
8565 * 0b1..Slow
8566 */
8567#define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_SRE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_SRE_MASK)
8568#define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_ODE_MASK (0x20U)
8569#define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_ODE_SHIFT (5U)
8570/*! ODE - Open-drain Enable Field
8571 * 0b0..Push-pull
8572 * 0b1..Open-drain
8573 */
8574#define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_ODE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_ODE_MASK)
8575#define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_DSE_MASK (0x40U)
8576#define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_DSE_SHIFT (6U)
8577/*! DSE - Drive Strength Enable Field
8578 * 0b0..Standard
8579 * 0b1..Hi Drive
8580 */
8581#define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_DSE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_DSE_MASK)
8582#define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_LK_MASK (0x8000U)
8583#define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_LK_SHIFT (15U)
8584/*! LK - Lock Field
8585 * 0b0..Disabled
8586 * 0b1..Enabled
8587 */
8588#define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_LK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_LK_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_LK_MASK)
8589/*! @} */
8590
8591
8592/*!
8593 * @}
8594 */ /* end of group IOMUXC1_Register_Masks */
8595
8596
8597/* IOMUXC1 - Peripheral instance base addresses */
8598/** Peripheral IOMUXC1 base address */
8599#define IOMUXC1_BASE (0x40AC0000u)
8600/** Peripheral IOMUXC1 base pointer */
8601#define IOMUXC1 ((IOMUXC1_Type *)IOMUXC1_BASE)
8602/** Array initializer of IOMUXC1 peripheral base addresses */
8603#define IOMUXC1_BASE_ADDRS { IOMUXC1_BASE }
8604/** Array initializer of IOMUXC1 peripheral base pointers */
8605#define IOMUXC1_BASE_PTRS { IOMUXC1 }
8606
8607/*!
8608 * @}
8609 */ /* end of group IOMUXC1_Peripheral_Access_Layer */
8610
8611
8612/* ----------------------------------------------------------------------------
8613 -- IOMUXC1_DDR Peripheral Access Layer
8614 ---------------------------------------------------------------------------- */
8615
8616/*!
8617 * @addtogroup IOMUXC1_DDR_Peripheral_Access_Layer IOMUXC1_DDR Peripheral Access Layer
8618 * @{
8619 */
8620
8621/** IOMUXC1_DDR - Register Layout Typedef */
8622typedef struct {
8623 __IO uint32_t SW_PAD_CTL_PAD_DDR_DQ[32]; /**< SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register, array offset: 0x0, array step: 0x4 */
8624 __IO uint32_t SW_PAD_CTL_PAD_DDR_DQS[4]; /**< SW_PAD_CTL_PAD_DDR_DQSn SW PAD Control Register, array offset: 0x80, array step: 0x4 */
8625 __IO uint32_t SW_PAD_CTL_PAD_DDR_DQM[4]; /**< SW_PAD_CTL_PAD_DDR_DQMn SW PAD Control Register, array offset: 0x90, array step: 0x4 */
8626 __IO uint32_t SW_PAD_CTL_PAD_DDR[12]; /**< SW_PAD_CTL_PAD_DDR_n SW PAD Control Register, array offset: 0xA0, array step: 0x4 */
8627 __IO uint32_t SW_PAD_CTL_PAD_DDR_CKE[2]; /**< SW_PAD_CTL_PAD_DDR_CKEn SW PAD Control Register, array offset: 0xD0, array step: 0x4 */
8628 __IO uint32_t SW_PAD_CTL_PAD_DDR_CLK0; /**< SW_PAD_CTL_PAD_DDR_CLK0 SW PAD Control Register, offset: 0xD8 */
8629 __IO uint32_t SW_PAD_CTL_PAD_DDR_ODT; /**< SW_PAD_CTL_PAD_DDR_ODT SW PAD Control Register, offset: 0xDC */
8630 __IO uint32_t SW_PAD_CTL_PAD_DDR_ZQ[2]; /**< SW_PAD_CTL_PAD_DDR_ZQn SW PAD Control Register, array offset: 0xE0, array step: 0x4 */
8631 __IO uint32_t SW_PAD_CTL_PAD_HSIC_DATA; /**< SW_PAD_CTL_PAD_HSIC_DATA SW PAD Control Register, offset: 0xE8 */
8632 __IO uint32_t SW_PAD_CTL_PAD_HSIC_STROBE; /**< SW_PAD_CTL_PAD_HSIC_STROBE SW PAD Control Register, offset: 0xEC */
8633 __IO uint32_t SW_PAD_CTL_GRP_PUE; /**< SW_PAD_CTL_GRP_PUE SW GRP Register, offset: 0xF0 */
8634 __IO uint32_t SW_PAD_CTL_GRP_PUE_DAT; /**< SW_PAD_CTL_GRP_PUE_DAT SW GRP Register, offset: 0xF4 */
8635 __IO uint32_t SW_PAD_CTL_GRP_PKE; /**< SW_PAD_CTL_GRP_PKE SW GRP Register, offset: 0xF8 */
8636 __IO uint32_t SW_PAD_CTL_GRP_PKE_DAT; /**< SW_PAD_CTL_GRP_PKE_DAT SW GRP Register, offset: 0xFC */
8637 __IO uint32_t SW_PAD_CTL_GRP_PUS; /**< SW_PAD_CTL_GRP_PUS SW GRP Register, offset: 0x100 */
8638 __IO uint32_t SW_PAD_CTL_GRP_DS_ADDR; /**< SW_PAD_CTL_GRP_DS_ADDR SW GRP Register, offset: 0x104 */
8639 __IO uint32_t SW_PAD_CTL_GRP_DS_CTRL; /**< SW_PAD_CTL_GRP_DS_CTRL SW GRP Register, offset: 0x108 */
8640 __IO uint32_t SW_PAD_CTL_GRP_DS_DAT0; /**< SW_PAD_CTL_GRP_DS_DAT0 SW GRP Register, offset: 0x10C */
8641 __IO uint32_t SW_PAD_CTL_GRP_DS_DAT1; /**< SW_PAD_CTL_GRP_DS_DAT1 SW GRP Register, offset: 0x110 */
8642 __IO uint32_t SW_PAD_CTL_GRP_DS_DAT2; /**< SW_PAD_CTL_GRP_DS_DAT2 SW GRP Register, offset: 0x114 */
8643 __IO uint32_t SW_PAD_CTL_GRP_DS_DAT3; /**< SW_PAD_CTL_GRP_DS_DAT3 SW GRP Register, offset: 0x118 */
8644 __IO uint32_t SW_PAD_CTL_GRP_HYS; /**< SW_PAD_CTL_GRP_HYS SW GRP Register, offset: 0x11C */
8645 __IO uint32_t SW_PAD_CTL_GRP_INSEL_DAT; /**< SW_PAD_CTL_GRP_INSEL_DAT SW GRP Register, offset: 0x120 */
8646 __IO uint32_t SW_PAD_CTL_GRP_INSEL_DQS; /**< SW_PAD_CTL_GRP_INSEL_DQS SW GRP Register, offset: 0x124 */
8647 __IO uint32_t SW_PAD_CTL_GRP_DDRTYPE; /**< SW_PAD_CTL_GRP_DDRTYPE SW GRP Register, offset: 0x128 */
8648} IOMUXC1_DDR_Type;
8649
8650/* ----------------------------------------------------------------------------
8651 -- IOMUXC1_DDR Register Masks
8652 ---------------------------------------------------------------------------- */
8653
8654/*!
8655 * @addtogroup IOMUXC1_DDR_Register_Masks IOMUXC1_DDR Register Masks
8656 * @{
8657 */
8658
8659/*! @name SW_PAD_CTL_PAD_DDR_DQ - SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register */
8660/*! @{ */
8661#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DCYCLE_TRIM_MASK (0x3000U)
8662#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DCYCLE_TRIM_SHIFT (12U)
8663/*! DCYCLE_TRIM - Duty Cycle Control Field
8664 * 0b00..no duty cycle change
8665 * 0b01..duty cycle increased ~3.7%
8666 * 0b10..duty cycle decreased ~3.7%
8667 * 0b11..no duty cycle change
8668 */
8669#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DCYCLE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DCYCLE_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DCYCLE_TRIM_MASK)
8670#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DDR_TRIM_MASK (0xC000U)
8671#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DDR_TRIM_SHIFT (14U)
8672/*! DDR_TRIM - Output Driver Delay Trim Field
8673 * 0b00..0pS
8674 * 0b01..50pS
8675 * 0b10..100pS
8676 * 0b11..150pS
8677 */
8678#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DDR_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DDR_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DDR_TRIM_MASK)
8679/*! @} */
8680
8681/* The count of IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ */
8682#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_COUNT (32U)
8683
8684/*! @name SW_PAD_CTL_PAD_DDR_DQS - SW_PAD_CTL_PAD_DDR_DQSn SW PAD Control Register */
8685/*! @{ */
8686#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUE_MASK (0x4U)
8687#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUE_SHIFT (2U)
8688/*! PUE - Pull Up/Down or Keeper Selection Field
8689 * 0b0..Keeper Selected
8690 * 0b1..Pull Up/Down Selected
8691 */
8692#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUE_MASK)
8693#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PKE_MASK (0x8U)
8694#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PKE_SHIFT (3U)
8695/*! PKE - Pull Up/Pull Down/Keeper Enable Field
8696 * 0b0..Pull Up/Down and Keeper Disabled
8697 * 0b1..Pull Up/Down or Keeper Enabled
8698 */
8699#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PKE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PKE_MASK)
8700#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUS_MASK (0x30U)
8701#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUS_SHIFT (4U)
8702/*! PUS - Pull Up/Down Resistance Select Field
8703 * 0b00..100 kOhm Pull Down
8704 * 0b01..47 Kohm Pull Up
8705 * 0b10..100 kOhm Pull Up
8706 * 0b11..22 kOhm Pull Up
8707 */
8708#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUS_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUS_MASK)
8709#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DSE_MASK (0x1C0U)
8710#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DSE_SHIFT (6U)
8711/*! DSE - Output Drive Strength Select Field
8712 * 0b000..Driver Disabled
8713 * 0b001..240 Ohm
8714 * 0b010..240/2=120 Ohm
8715 * 0b011..240/3=80 Ohm
8716 * 0b100..240/4=60 Ohm
8717 * 0b101..240/5=48 Ohm
8718 * 0b110..240/6=40 Ohm
8719 * 0b111..240/7=34 Ohm
8720 */
8721#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DSE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DSE_MASK)
8722#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_CRPOINT_TRIM_MASK (0xC00U)
8723#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_CRPOINT_TRIM_SHIFT (10U)
8724/*! CRPOINT_TRIM - Crosspoint Adjustment Field
8725 * 0b00..no output crosspoint (Vix) change
8726 * 0b01..100mV Vix shift down
8727 * 0b10..100mV Vix shift up
8728 * 0b11..200mV Vix shift up
8729 */
8730#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_CRPOINT_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_CRPOINT_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_CRPOINT_TRIM_MASK)
8731#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DCYCLE_TRIM_MASK (0x3000U)
8732#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DCYCLE_TRIM_SHIFT (12U)
8733/*! DCYCLE_TRIM - Duty Cycle Control Field
8734 * 0b00..no duty cycle change
8735 * 0b01..duty cycle increased ~3.7%
8736 * 0b10..duty cycle decreased ~3.7%
8737 * 0b11..no duty cycle change
8738 */
8739#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DCYCLE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DCYCLE_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DCYCLE_TRIM_MASK)
8740/*! @} */
8741
8742/* The count of IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS */
8743#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_COUNT (4U)
8744
8745/*! @name SW_PAD_CTL_PAD_DDR_DQM - SW_PAD_CTL_PAD_DDR_DQMn SW PAD Control Register */
8746/*! @{ */
8747#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DSE_MASK (0x1C0U)
8748#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DSE_SHIFT (6U)
8749/*! DSE - Output Drive Strength Select Field
8750 * 0b000..Driver Disabled
8751 * 0b001..240 Ohm
8752 * 0b010..240/2=120 Ohm
8753 * 0b011..240/3=80 Ohm
8754 * 0b100..240/4=60 Ohm
8755 * 0b101..240/5=48 Ohm
8756 * 0b110..240/6=40 Ohm
8757 * 0b111..240/7=34 Ohm
8758 */
8759#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DSE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DSE_MASK)
8760#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_HYS_MASK (0x200U)
8761#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_HYS_SHIFT (9U)
8762/*! HYS - Input Hysteresis Field
8763 * 0b0..CMOS input
8764 * 0b1..Schmitt trigger input
8765 */
8766#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_HYS_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_HYS_MASK)
8767#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DCYCLE_TRIM_MASK (0x3000U)
8768#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DCYCLE_TRIM_SHIFT (12U)
8769/*! DCYCLE_TRIM - Duty Cycle Control Field
8770 * 0b00..no duty cycle change
8771 * 0b01..duty cycle increased ~3.7%
8772 * 0b10..duty cycle decreased ~3.7%
8773 * 0b11..no duty cycle change
8774 */
8775#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DCYCLE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DCYCLE_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DCYCLE_TRIM_MASK)
8776#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_TRIM_MASK (0xC000U)
8777#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_TRIM_SHIFT (14U)
8778/*! DDR_TRIM - Output Driver Delay Trim Field
8779 * 0b00..0pS
8780 * 0b01..50pS
8781 * 0b10..100pS
8782 * 0b11..150pS
8783 */
8784#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_TRIM_MASK)
8785#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_INPUT_MASK (0x10000U)
8786#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_INPUT_SHIFT (16U)
8787/*! DDR_INPUT - DDR/CMOS Input Select Field
8788 * 0b0..CMOS input type
8789 * 0b1..Differential input mode
8790 */
8791#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_INPUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_INPUT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_INPUT_MASK)
8792#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_ODT_MASK (0x380000U)
8793#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_ODT_SHIFT (19U)
8794/*! DDR_ODT - On Die Termination Select Field
8795 * 0b000..No Termination
8796 * 0b001..120 Ohm
8797 * 0b010..60 Ohm
8798 * 0b011..40 Ohm
8799 * 0b100..30 Ohm
8800 * 0b101..24 Ohm
8801 * 0b110..20 Ohm
8802 * 0b111..17 Ohm
8803 */
8804#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_ODT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_ODT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_ODT_MASK)
8805/*! @} */
8806
8807/* The count of IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM */
8808#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_COUNT (4U)
8809
8810/*! @name SW_PAD_CTL_PAD_DDR - SW_PAD_CTL_PAD_DDR_n SW PAD Control Register */
8811/*! @{ */
8812#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_HYS_MASK (0x200U)
8813#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_HYS_SHIFT (9U)
8814/*! HYS - Input Hysteresis Field
8815 * 0b0..CMOS input
8816 * 0b1..Schmitt trigger input
8817 */
8818#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_HYS_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_HYS_MASK)
8819#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DCYCLE_TRIM_MASK (0x3000U)
8820#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DCYCLE_TRIM_SHIFT (12U)
8821/*! DCYCLE_TRIM - Duty Cycle Control Field
8822 * 0b00..no duty cycle change
8823 * 0b01..duty cycle increased ~3.7%
8824 * 0b10..duty cycle decreased ~3.7%
8825 * 0b11..no duty cycle change
8826 */
8827#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DCYCLE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DCYCLE_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DCYCLE_TRIM_MASK)
8828#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_TRIM_MASK (0xC000U)
8829#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_TRIM_SHIFT (14U)
8830/*! DDR_TRIM - Output Driver Delay Trim Field
8831 * 0b00..0pS
8832 * 0b01..50pS
8833 * 0b10..100pS
8834 * 0b11..150pS
8835 */
8836#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_TRIM_MASK)
8837#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_INPUT_MASK (0x10000U)
8838#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_INPUT_SHIFT (16U)
8839/*! DDR_INPUT - DDR/CMOS Input Select Field
8840 * 0b0..CMOS input type
8841 * 0b1..Differential input mode
8842 */
8843#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_INPUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_INPUT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_INPUT_MASK)
8844#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_ODT_MASK (0x380000U)
8845#define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_ODT_SHIFT (19U)
8846/*! DDR_ODT - On Die Termination Select Field
8847 * 0b000..No Termination
8848 * 0b001..120 Ohm
8849 * 0b010..60 Ohm
8850 * 0b011..40 Ohm
8851 * 0b100..30 Ohm
8852 * 0b101..24 Ohm
8853 * 0b110..20 Ohm