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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX1/MIMX8DX1_cm4.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX1/MIMX8DX1_cm4.h
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+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX1/MIMX8DX1_cm4.h
@@ -0,0 +1,113953 @@
1/*
2** ###################################################################
3** Processors: MIMX8DX1AVLFZ
4** MIMX8DX1AVOFZ
5**
6** Compilers: GNU C Compiler
7** IAR ANSI C/C++ Compiler for ARM
8** Keil ARM C/C++ Compiler
9**
10** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
11** Version: rev. 4.0, 2020-06-19
12** Build: b200825
13**
14** Abstract:
15** CMSIS Peripheral Access Layer for MIMX8DX1_cm4
16**
17** Copyright 1997-2016 Freescale Semiconductor, Inc.
18** Copyright 2016-2020 NXP
19** All rights reserved.
20**
21** SPDX-License-Identifier: BSD-3-Clause
22**
23** http: www.nxp.com
24** mail: [email protected]
25**
26** Revisions:
27** - rev. 1.0 (2016-06-02)
28** Initial version.
29** - rev. 2.0 (2017-08-23)
30** RevA Header EAR
31** - rev. 3.0 (2018-08-22)
32** RevB Header EAR
33** - rev. 4.0 (2020-06-19)
34** RevC Header RFP
35**
36** ###################################################################
37*/
38
39/*!
40 * @file MIMX8DX1_cm4.h
41 * @version 4.0
42 * @date 2020-06-19
43 * @brief CMSIS Peripheral Access Layer for MIMX8DX1_cm4
44 *
45 * CMSIS Peripheral Access Layer for MIMX8DX1_cm4
46 */
47
48#ifndef _MIMX8DX1_CM4_H_
49#define _MIMX8DX1_CM4_H_ /**< Symbol preventing repeated inclusion */
50
51/** Memory map major version (memory maps with equal major version number are
52 * compatible) */
53#define MCU_MEM_MAP_VERSION 0x0400U
54/** Memory map minor version */
55#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
56
57
58/* ----------------------------------------------------------------------------
59 -- Interrupt vector numbers
60 ---------------------------------------------------------------------------- */
61
62/*!
63 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
64 * @{
65 */
66
67/** Interrupt Number Definitions */
68#define NUMBER_OF_INT_VECTORS 611 /**< Number of interrupts in the Vector table */
69
70typedef enum IRQn {
71 /* Auxiliary constants */
72 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
73
74 /* Core interrupts */
75 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
76 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
77 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
78 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
79 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
80 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
81 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
82 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
83 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
84
85 /* Device specific interrupts */
86 Reserved16_IRQn = 0, /**< Reserved */
87 Reserved17_IRQn = 1, /**< Reserved */
88 Reserved18_IRQn = 2, /**< Reserved */
89 Reserved19_IRQn = 3, /**< Reserved */
90 Reserved20_IRQn = 4, /**< Reserved */
91 M4_MCM_IRQn = 5, /**< MCM IRQ */
92 Reserved22_IRQn = 6, /**< Reserved */
93 Reserved23_IRQn = 7, /**< Reserved */
94 Reserved24_IRQn = 8, /**< Reserved */
95 Reserved25_IRQn = 9, /**< Reserved */
96 Reserved26_IRQn = 10, /**< Reserved */
97 Reserved27_IRQn = 11, /**< Reserved */
98 Reserved28_IRQn = 12, /**< Reserved */
99 Reserved29_IRQn = 13, /**< Reserved */
100 Reserved30_IRQn = 14, /**< Reserved */
101 Reserved31_IRQn = 15, /**< Reserved */
102 Reserved32_IRQn = 16, /**< Reserved */
103 Reserved33_IRQn = 17, /**< Reserved */
104 Reserved34_IRQn = 18, /**< Reserved */
105 M4_TPM_IRQn = 19, /**< Timer PWM Module */
106 Reserved36_IRQn = 20, /**< Reserved */
107 Reserved37_IRQn = 21, /**< Reserved */
108 M4_LPIT_IRQn = 22, /**< Low-Power Periodic Interrupt Timer */
109 Reserved39_IRQn = 23, /**< Reserved */
110 Reserved40_IRQn = 24, /**< Reserved */
111 M4_LPUART_IRQn = 25, /**< Low Power UART */
112 Reserved42_IRQn = 26, /**< Reserved */
113 M4_LPI2C_IRQn = 27, /**< Low-Power I2C - Logical OR of master and slave interrupts */
114 Reserved44_IRQn = 28, /**< Reserved */
115 M4_MU0_B0_IRQn = 29, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 0, Logical OR of all general-purpose, TX, and RX interrupts */
116 Reserved46_IRQn = 30, /**< Reserved */
117 Reserved47_IRQn = 31, /**< Reserved */
118 IRQSTEER_0_IRQn = 32, /**< External interrupt 0 */
119 IRQSTEER_1_IRQn = 33, /**< External interrupt 1 */
120 IRQSTEER_2_IRQn = 34, /**< External interrupt 2 */
121 IRQSTEER_3_IRQn = 35, /**< External interrupt 3 */
122 IRQSTEER_4_IRQn = 36, /**< External interrupt 4 */
123 IRQSTEER_5_IRQn = 37, /**< External interrupt 5 */
124 IRQSTEER_6_IRQn = 38, /**< External interrupt 6 */
125 IRQSTEER_7_IRQn = 39, /**< External interrupt 7 */
126 Reserved56_IRQn = 40, /**< Reserved */
127 Reserved57_IRQn = 41, /**< Reserved */
128 Reserved58_IRQn = 42, /**< Reserved */
129 Reserved59_IRQn = 43, /**< Reserved */
130 M4_MU0_B1_IRQn = 44, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 1, Logical OR of all general-purpose, TX, and RX interrupts */
131 M4_MU0_B2_IRQn = 45, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 2, Logical OR of all general-purpose, TX, and RX interrupts */
132 M4_MU0_B3_IRQn = 46, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 3, Logical OR of all general-purpose, TX, and RX interrupts */
133 Reserved63_IRQn = 47, /**< Reserved */
134 Reserved64_IRQn = 48, /**< Reserved */
135 M4_MU1_A_IRQn = 49, /**< Messaging Unit 1 (IPC with System Controller) - Side A (MCU), Logical OR of all general-purpose, TX, and RX interrupts */
136 M4_SW_IRQn = 50, /**< Software interrupt (asserted/cleared via NVIC registers, INTISR[50] input tied low) */
137 A35_NINTERRIRQ_IRQn = 83, /**< Shared Int Source nINTERRIRQ from A35 Sub-System */
138 A35_NEXTERRIRQ_IRQn = 84, /**< Shared Int Source nEXTERRIRQ from A35 Sub-System */
139 M4_INT_OUT0_IRQn = 99, /**< Shared Int Source INT_OUT[0] from M4 Sub-System */
140 M4_INT_OUT1_IRQn = 100, /**< Shared Int Source INT_OUT[1] from M4 Sub-System */
141 M4_INT_OUT2_IRQn = 101, /**< Shared Int Source INT_OUT[2] from M4 Sub-System */
142 M4_INT_OUT3_IRQn = 102, /**< Shared Int Source INT_OUT[3] from M4 Sub-System */
143 M4_INT_OUT4_IRQn = 103, /**< Shared Int Source INT_OUT[4] from M4 Sub-System */
144 M4_INT_OUT5_IRQn = 104, /**< Shared Int Source INT_OUT[5] from M4 Sub-System */
145 M4_INT_OUT6_IRQn = 105, /**< Shared Int Source INT_OUT[6] from M4 Sub-System */
146 M4_INT_OUT7_IRQn = 106, /**< Shared Int Source INT_OUT[7] from M4 Sub-System */
147 DISPLAY0_INT_OUT0_IRQn = 123, /**< Shared Int Source INT_OUT[0] from Display0 Sub-System */
148 DISPLAY0_INT_OUT1_IRQn = 124, /**< Shared Int Source INT_OUT[1] from Display0 Sub-System */
149 DISPLAY0_INT_OUT2_IRQn = 125, /**< Shared Int Source INT_OUT[2] from Display0 Sub-System */
150 DISPLAY0_INT_OUT3_IRQn = 126, /**< Shared Int Source INT_OUT[3] from Display0 Sub-System */
151 DISPLAY0_INT_OUT4_IRQn = 127, /**< Shared Int Source INT_OUT[4] from Display0 Sub-System */
152 DISPLAY0_INT_OUT5_IRQn = 128, /**< Shared Int Source INT_OUT[5] from Display0 Sub-System */
153 DISPLAY0_INT_OUT6_IRQn = 129, /**< Shared Int Source INT_OUT[6] from Display0 Sub-System */
154 DISPLAY0_INT_OUT7_IRQn = 130, /**< Shared Int Source INT_OUT[7] from Display0 Sub-System */
155 DISPLAY0_RESERVED_IRQn = 131, /**< Shared Int Source Reserved from Display0 Sub-System */
156 DISPLAY0_INT_OUT9_IRQn = 132, /**< Shared Int Source INT_OUT[9] from Display0 Sub-System */
157 DISPLAY0_INT_OUT10_IRQn = 133, /**< Shared Int Source INT_OUT[10] from Display0 Sub-System */
158 DISPLAY0_INT_OUT11_IRQn = 134, /**< Shared Int Source INT_OUT[11] from Display0 Sub-System */
159 DISPLAY0_INT_OUT12_IRQn = 135, /**< Shared Int Source INT_OUT[12] from Display0 Sub-System */
160 MIPI_DSI0_INT_OUT_IRQn = 142, /**< Shared Int Source INT_OUT from MIPI_DSI0 Sub-System */
161 MIPI_DSI1_INT_OUT_IRQn = 143, /**< Shared Int Source INT_OUT from MIPI_DSI1 Sub-System */
162 LCD_MOD_INT_IRQn = 145, /**< Shared Int Source INT_OUT from ADMA Sub-System */
163 LCD_PWM_INT_IRQn = 146, /**< Shared Int Source INT_OUT from ADMA Sub-System */
164 GPU0_XAQ2_INTR_IRQn = 147, /**< Shared Int Source xaq2_intr from GPU0 Sub-System */
165 ADMA_EDMA2_INT_IRQn = 149, /**< Shared Int Source eDMA2_INT from ADMA Sub-System */
166 ADMA_EDMA2_ERR_INT_IRQn = 150, /**< Shared Int Source eDMA2_ERR_INT from ADMA Sub-System */
167 ADMA_EDMA3_INT_IRQn = 151, /**< Shared Int Source eDMA3_INT from ADMA Sub-System */
168 ADMA_EDMA3_ERR_INT_IRQn = 152, /**< Shared Int Source eDMA3_ERR_INT from ADMA Sub-System */
169 LSIO_GPT0_INT_IRQn = 163, /**< Shared Int Source GPT0_INT from LSIO Sub-System */
170 LSIO_GPT1_INT_IRQn = 164, /**< Shared Int Source GPT1_INT from LSIO Sub-System */
171 LSIO_GPT2_INT_IRQn = 165, /**< Shared Int Source GPT2_INT from LSIO Sub-System */
172 LSIO_GPT3_INT_IRQn = 166, /**< Shared Int Source GPT3_INT from LSIO Sub-System */
173 LSIO_GPT4_INT_IRQn = 167, /**< Shared Int Source GPT4_INT from LSIO Sub-System */
174 LSIO_KPP_INT_IRQn = 168, /**< Shared Int Source KPP_INT from LSIO Sub-System */
175 LSIO_OCTASPI0_INT_IRQn = 175, /**< Shared Int Source OctaSPI0_INT from LSIO Sub-System */
176 LSIO_OCTASPI1_INT_IRQn = 176, /**< Shared Int Source OctaSPI1_INT from LSIO Sub-System */
177 LSIO_PWM0_INT_IRQn = 177, /**< Shared Int Source PWM0_INT from LSIO Sub-System */
178 LSIO_PWM1_INT_IRQn = 178, /**< Shared Int Source PWM1_INT from LSIO Sub-System */
179 LSIO_PWM2_INT_IRQn = 179, /**< Shared Int Source PWM2_INT from LSIO Sub-System */
180 LSIO_PWM3_INT_IRQn = 180, /**< Shared Int Source PWM3_INT from LSIO Sub-System */
181 LSIO_PWM4_INT_IRQn = 181, /**< Shared Int Source PWM4_INT from LSIO Sub-System */
182 LSIO_PWM5_INT_IRQn = 182, /**< Shared Int Source PWM5_INT from LSIO Sub-System */
183 LSIO_PWM6_INT_IRQn = 183, /**< Shared Int Source PWM6_INT from LSIO Sub-System */
184 LSIO_PWM7_INT_IRQn = 184, /**< Shared Int Source PWM7_INT from LSIO Sub-System */
185 HSIO_PCIEB_MSI_CTRL_INT_IRQn = 185, /**< Shared Int Source PCIeB_MSI_CTRL_INT from HSIO Sub-System */
186 HSIO_PCIEB_CLK_REQ_INT_IRQn = 186, /**< Shared Int Source PCIeB_CLK_REQ_INT from HSIO Sub-System */
187 HSIO_PCIEB_DMA_INT_IRQn = 187, /**< Shared Int Source PCIeB_DMA_INT from HSIO Sub-System */
188 HSIO_PCIEB_INT_D_IRQn = 188, /**< Shared Int Source PCIeB_INT_D from HSIO Sub-System */
189 HSIO_PCIEB_INT_C_IRQn = 189, /**< Shared Int Source PCIeB_INT_C from HSIO Sub-System */
190 HSIO_PCIEB_INT_B_IRQn = 190, /**< Shared Int Source PCIeB_INT_B from HSIO Sub-System */
191 HSIO_PCIEB_INT_A_IRQn = 191, /**< Shared Int Source PCIeB_INT_A from HSIO Sub-System */
192 HSIO_PCIEB_SMLH_REQ_RST_IRQn = 192, /**< Shared Int Source PCIeB_SMLH_REQ_RST from HSIO Sub-System */
193 HSIO_PCIEB_GPIO_WAKEUP0_IRQn = 193, /**< Shared Int Source PCIeB_GPIO_WAKEUP[0] from HSIO Sub-System */
194 HSIO_PCIEB_GPIO_WAKEUP1_IRQn = 194, /**< Shared Int Source PCIeB_GPIO_WAKEUP[1] from HSIO Sub-System */
195 SCU_INT_OUT0_IRQn = 195, /**< Shared Int Source INT_OUT[0] from SCU Sub-System */
196 SCU_INT_OUT1_IRQn = 196, /**< Shared Int Source INT_OUT[1] from SCU Sub-System */
197 SCU_INT_OUT2_IRQn = 197, /**< Shared Int Source INT_OUT[2] from SCU Sub-System */
198 SCU_INT_OUT3_IRQn = 198, /**< Shared Int Source INT_OUT[3] from SCU Sub-System */
199 SCU_INT_OUT4_IRQn = 199, /**< Shared Int Source INT_OUT[4] from SCU Sub-System */
200 SCU_INT_OUT5_IRQn = 200, /**< Shared Int Source INT_OUT[5] from SCU Sub-System */
201 SCU_INT_OUT6_IRQn = 201, /**< Shared Int Source INT_OUT[6] from SCU Sub-System */
202 SCU_INT_OUT7_IRQn = 202, /**< Shared Int Source INT_OUT[7] from SCU Sub-System */
203 SCU_SYS_COUNT_INT0_IRQn = 203, /**< Shared Int Source SYS_COUNT_INT0 from SCU Sub-System */
204 SCU_SYS_COUNT_INT1_IRQn = 204, /**< Shared Int Source SYS_COUNT_INT1 from SCU Sub-System */
205 SCU_SYS_COUNT_INT2_IRQn = 205, /**< Shared Int Source SYS_COUNT_INT2 from SCU Sub-System */
206 SCU_SYS_COUNT_INT3_IRQn = 206, /**< Shared Int Source SYS_COUNT_INT3 from SCU Sub-System */
207 DRC_ECC_CORRECT_INT_IRQn = 211, /**< Shared Int Source ECC_CORRECT_INT from DRC Sub-System */
208 DRC_ECC_NCORRECT_INT_IRQn = 212, /**< Shared Int Source ECC_NCORRECT_INT from DRC Sub-System */
209 DRC_SBR_DONE_INT_IRQn = 213, /**< Shared Int Source SBR_DONE_INT from DRC Sub-System */
210 DRC_PERF_CNT_INT_IRQn = 214, /**< Shared Int Source PERF_CNT_INT from DRC Sub-System */
211 LSIO_GPIO_INT0_IRQn = 219, /**< Shared Int Source GPIO_INT[0] from LSIO Sub-System */
212 LSIO_GPIO_INT1_IRQn = 220, /**< Shared Int Source GPIO_INT[1] from LSIO Sub-System */
213 LSIO_GPIO_INT2_IRQn = 221, /**< Shared Int Source GPIO_INT[2] from LSIO Sub-System */
214 LSIO_GPIO_INT3_IRQn = 222, /**< Shared Int Source GPIO_INT[3] from LSIO Sub-System */
215 LSIO_GPIO_INT4_IRQn = 223, /**< Shared Int Source GPIO_INT[4] from LSIO Sub-System */
216 LSIO_GPIO_INT5_IRQn = 224, /**< Shared Int Source GPIO_INT[5] from LSIO Sub-System */
217 LSIO_GPIO_INT6_IRQn = 225, /**< Shared Int Source GPIO_INT[6] from LSIO Sub-System */
218 LSIO_GPIO_INT7_IRQn = 226, /**< Shared Int Source GPIO_INT[7] from LSIO Sub-System */
219 LSIO_MU0_INT_IRQn = 259, /**< Shared Int Source MU0_INT from LSIO Sub-System */
220 LSIO_MU1_INT_IRQn = 260, /**< Shared Int Source MU1_INT from LSIO Sub-System */
221 LSIO_MU2_INT_IRQn = 261, /**< Shared Int Source MU2_INT from LSIO Sub-System */
222 LSIO_MU3_INT_IRQn = 262, /**< Shared Int Source MU3_INT from LSIO Sub-System */
223 LSIO_MU4_INT_IRQn = 263, /**< Shared Int Source MU4_INT from LSIO Sub-System */
224 LSIO_MU5_INT_A_IRQn = 267, /**< Shared Int Source MU5_INT_A from LSIO Sub-System */
225 LSIO_MU6_INT_A_IRQn = 268, /**< Shared Int Source MU6_INT_A from LSIO Sub-System */
226 LSIO_MU7_INT_A_IRQn = 269, /**< Shared Int Source MU7_INT_A from LSIO Sub-System */
227 LSIO_MU8_INT_A_IRQn = 270, /**< Shared Int Source MU8_INT_A from LSIO Sub-System */
228 LSIO_MU9_INT_A_IRQn = 271, /**< Shared Int Source MU9_INT_A from LSIO Sub-System */
229 LSIO_MU10_INT_A_IRQn = 272, /**< Shared Int Source MU10_INT_A from LSIO Sub-System */
230 LSIO_MU11_INT_A_IRQn = 273, /**< Shared Int Source MU11_INT_A from LSIO Sub-System */
231 LSIO_MU12_INT_A_IRQn = 274, /**< Shared Int Source MU12_INT_A from LSIO Sub-System */
232 LSIO_MU13_INT_A_IRQn = 275, /**< Shared Int Source MU13_INT_A from LSIO Sub-System */
233 LSIO_MU5_INT_B_IRQn = 283, /**< Shared Int Source MU5_INT_B from LSIO Sub-System */
234 LSIO_MU6_INT_B_IRQn = 284, /**< Shared Int Source MU6_INT_B from LSIO Sub-System */
235 LSIO_MU7_INT_B_IRQn = 285, /**< Shared Int Source MU7_INT_B from LSIO Sub-System */
236 LSIO_MU8_INT_B_IRQn = 286, /**< Shared Int Source MU8_INT_B from LSIO Sub-System */
237 LSIO_MU9_INT_B_IRQn = 287, /**< Shared Int Source MU9_INT_B from LSIO Sub-System */
238 LSIO_MU10_INT_B_IRQn = 288, /**< Shared Int Source MU10_INT_B from LSIO Sub-System */
239 LSIO_MU11_INT_B_IRQn = 289, /**< Shared Int Source MU11_INT_B from LSIO Sub-System */
240 LSIO_MU12_INT_B_IRQn = 290, /**< Shared Int Source MU12_INT_B from LSIO Sub-System */
241 LSIO_MU13_INT_B_IRQn = 291, /**< Shared Int Source MU13_INT_B from LSIO Sub-System */
242 ADMA_SPI0_INT_IRQn = 299, /**< Shared Int Source SPI0_INT from ADMA Sub-System */
243 ADMA_SPI1_INT_IRQn = 300, /**< Shared Int Source SPI1_INT from ADMA Sub-System */
244 ADMA_SPI2_INT_IRQn = 301, /**< Shared Int Source SPI2_INT from ADMA Sub-System */
245 ADMA_SPI3_INT_IRQn = 302, /**< Shared Int Source SPI3_INT from ADMA Sub-System */
246 ADMA_I2C0_INT_IRQn = 303, /**< Shared Int Source I2C0_INT from ADMA Sub-System */
247 ADMA_I2C1_INT_IRQn = 304, /**< Shared Int Source I2C1_INT from ADMA Sub-System */
248 ADMA_I2C2_INT_IRQn = 305, /**< Shared Int Source I2C2_INT from ADMA Sub-System */
249 ADMA_I2C3_INT_IRQn = 306, /**< Shared Int Source I2C3_INT from ADMA Sub-System */
250 ADMA_UART0_INT_IRQn = 308, /**< Shared Int Source UART0_INT from ADMA Sub-System */
251 ADMA_UART1_INT_IRQn = 309, /**< Shared Int Source UART1_INT from ADMA Sub-System */
252 ADMA_UART2_INT_IRQn = 310, /**< Shared Int Source UART2_INT from ADMA Sub-System */
253 ADMA_UART3_INT_IRQn = 311, /**< Shared Int Source UART3_INT from ADMA Sub-System */
254 CONNECTIVITY_USDHC0_INT_IRQn = 315, /**< Shared Int Source uSDHC0_INT from Connectivity Sub-System */
255 CONNECTIVITY_USDHC1_INT_IRQn = 316, /**< Shared Int Source uSDHC1_INT from Connectivity Sub-System */
256 CONNECTIVITY_USDHC2_INT_IRQn = 317, /**< Shared Int Source uSDHC2_INT from Connectivity Sub-System */
257 ADMA_FLEXCAN0_INT_IRQn = 318, /**< Shared Int Source FlexCAN0_INT from ADMA Sub-System */
258 ADMA_FLEXCAN1_INT_IRQn = 319, /**< Shared Int Source FlexCAN1_INT from ADMA Sub-System */
259 ADMA_FLEXCAN2_INT_IRQn = 320, /**< Shared Int Source FlexCAN2_INT from ADMA Sub-System */
260 ADMA_FTM0_INT_IRQn = 321, /**< Shared Int Source FTM0_INT from ADMA Sub-System */
261 ADMA_FTM1_INT_IRQn = 322, /**< Shared Int Source FTM1_INT from ADMA Sub-System */
262 ADMA_ADC0_INT_IRQn = 323, /**< Shared Int Source ADC0_INT from ADMA Sub-System */
263 ADMA_EXTERNAL_DMA_INT_0_IRQn = 325, /**< Shared Int Source EXTERNAL_DMA_INT_0 from ADMA Sub-System */
264 ADMA_EXTERNAL_DMA_INT_1_IRQn = 326, /**< Shared Int Source EXTERNAL_DMA_INT_1 from ADMA Sub-System */
265 ADMA_EXTERNAL_DMA_INT_2_IRQn = 327, /**< Shared Int Source EXTERNAL_DMA_INT_2 from ADMA Sub-System */
266 ADMA_EXTERNAL_DMA_INT_3_IRQn = 328, /**< Shared Int Source EXTERNAL_DMA_INT_3 from ADMA Sub-System */
267 ADMA_EXTERNAL_DMA_INT_4_IRQn = 329, /**< Shared Int Source EXTERNAL_DMA_INT_4 from ADMA Sub-System */
268 ADMA_EXTERNAL_DMA_INT_5_IRQn = 330, /**< Shared Int Source EXTERNAL_DMA_INT_5 from ADMA Sub-System */
269 CONNECTIVITY_ENET0_FRAME1_INT_IRQn = 339, /**< Shared Int Source ENET0_FRAME1_INT from Connectivity Sub-System */
270 CONNECTIVITY_ENET0_FRAME2_INT_IRQn = 340, /**< Shared Int Source ENET0_FRAME2_INT from Connectivity Sub-System */
271 CONNECTIVITY_ENET0_FRAME0_EVENT_INT_IRQn = 341, /**< Shared Int Source ENET0_FRAME0_EVENT_INT from Connectivity Sub-System */
272 CONNECTIVITY_ENET0_TIMER_INT_IRQn = 342, /**< Shared Int Source ENET0_TIMER_INT from Connectivity Sub-System */
273 CONNECTIVITY_ENET1_FRAME1_INT_IRQn = 343, /**< Shared Int Source ENET1_FRAME1_INT from Connectivity Sub-System */
274 CONNECTIVITY_ENET1_FRAME2_INT_IRQn = 344, /**< Shared Int Source ENET1_FRAME2_INT from Connectivity Sub-System */
275 CONNECTIVITY_ENET1_FRAME0_EVENT_INT_IRQn = 345, /**< Shared Int Source ENET1_FRAME0_EVENT_INT from Connectivity Sub-System */
276 CONNECTIVITY_ENET1_TIMER_INT_IRQn = 346, /**< Shared Int Source ENET1_TIMER_INT from Connectivity Sub-System */
277 CONNECTIVITY_DTCP_INT_IRQn = 347, /**< Shared Int Source DTCP_INT from Connectivity Sub-System */
278 CONNECTIVITY_MLB_INT_IRQn = 348, /**< Shared Int Source MLB_INT from Connectivity Sub-System */
279 CONNECTIVITY_MLB_AHB_INT_IRQn = 349, /**< Shared Int Source MLB_AHB_INT from Connectivity Sub-System */
280 CONNECTIVITY_USB_OTG_INT_IRQn = 350, /**< Shared Int Source USB_OTG_INT from Connectivity Sub-System */
281 CONNECTIVITY_USB_HOST_INT_IRQn = 351, /**< Shared Int Source USB_HOST_INT from Connectivity Sub-System */
282 CONNECTIVITY_UTMI_INT_IRQn = 352, /**< Shared Int Source UTMI_INT from Connectivity Sub-System */
283 CONNECTIVITY_WAKEUP_INT_IRQn = 353, /**< Shared Int Source WAKEUP_INT from Connectivity Sub-System */
284 CONNECTIVITY_USB3_INT_IRQn = 354, /**< Shared Int Source USB3_INT from Connectivity Sub-System */
285 CONNECTIVITY_ND_FLASH_BCH_INT_IRQn = 355, /**< Shared Int Source ND_FLASH_BCH_INT from Connectivity Sub-System */
286 CONNECTIVITY_ND_FLASH_GPMI_INT_IRQn = 356, /**< Shared Int Source ND_FLASH_GPMI_INT from Connectivity Sub-System */
287 CONNECTIVITY_APBHDMA_IRQn = 357, /**< Shared Int Source APBHDMA from Connectivity Sub-System */
288 CONNECTIVITY_DMA_INT_IRQn = 358, /**< Shared Int Source DMA_INT from Connectivity Sub-System */
289 CONNECTIVITY_DMA_ERR_INT_IRQn = 359, /**< Shared Int Source DMA_ERR_INT from Connectivity Sub-System */
290 IMAGING_MSI_INT_IRQn = 371, /**< Shared Int Source MSI_INT from Imaging Sub-System */
291 IMAGING_PDMA_STREAM0_INT_IRQn = 380, /**< Shared Int Source PDMA_STREAM0_INT from Imaging Sub-System */
292 IMAGING_PDMA_STREAM1_INT_IRQn = 381, /**< Shared Int Source PDMA_STREAM1_INT from Imaging Sub-System */
293 IMAGING_PDMA_STREAM2_INT_IRQn = 382, /**< Shared Int Source PDMA_STREAM2_INT from Imaging Sub-System */
294 IMAGING_PDMA_STREAM3_INT_IRQn = 383, /**< Shared Int Source PDMA_STREAM3_INT from Imaging Sub-System */
295 IMAGING_PDMA_STREAM4_INT_IRQn = 384, /**< Shared Int Source PDMA_STREAM4_INT from Imaging Sub-System */
296 IMAGING_PDMA_STREAM5_INT_IRQn = 385, /**< Shared Int Source PDMA_STREAM5_INT from Imaging Sub-System */
297 IMAGING_PDMA_STREAM6_INT_IRQn = 386, /**< Shared Int Source PDMA_STREAM6_INT from Imaging Sub-System */
298 IMAGING_PDMA_STREAM7_INT_IRQn = 387, /**< Shared Int Source PDMA_STREAM7_INT from Imaging Sub-System */
299 IMAGING_MJPEG_ENC0_INT_IRQn = 388, /**< Shared Int Source MJPEG_ENC0_INT from Imaging Sub-System */
300 IMAGING_MJPEG_ENC1_INT_IRQn = 389, /**< Shared Int Source MJPEG_ENC1_INT from Imaging Sub-System */
301 IMAGING_MJPEG_ENC2_INT_IRQn = 390, /**< Shared Int Source MJPEG_ENC2_INT from Imaging Sub-System */
302 IMAGING_MJPEG_ENC3_INT_IRQn = 391, /**< Shared Int Source MJPEG_ENC3_INT from Imaging Sub-System */
303 IMAGING_MJPEG_DEC0_INT_IRQn = 392, /**< Shared Int Source MJPEG_DEC0_INT from Imaging Sub-System */
304 IMAGING_MJPEG_DEC1_INT_IRQn = 393, /**< Shared Int Source MJPEG_DEC1_INT from Imaging Sub-System */
305 IMAGING_MJPEG_DEC2_INT_IRQn = 394, /**< Shared Int Source MJPEG_DEC2_INT from Imaging Sub-System */
306 IMAGING_MJPEG_DEC3_INT_IRQn = 395, /**< Shared Int Source MJPEG_DEC3_INT from Imaging Sub-System */
307 ADMA_SAI0_MOD_INT_IRQn = 397, /**< Shared Int Source SAI0_MOD_INT from ADMA Sub-System */
308 ADMA_SAI0_DMA_INT_IRQn = 398, /**< Shared Int Source SAI0_DMA_INT from ADMA Sub-System */
309 ADMA_SAI1_MOD_INT_IRQn = 399, /**< Shared Int Source SAI1_MOD_INT from ADMA Sub-System */
310 ADMA_SAI1_DMA_INT_IRQn = 400, /**< Shared Int Source SAI1_DMA_INT from ADMA Sub-System */
311 ADMA_SAI2_MOD_INT_IRQn = 401, /**< Shared Int Source SAI2_MOD_INT from ADMA Sub-System */
312 ADMA_SAI2_DMA_INT_IRQn = 402, /**< Shared Int Source SAI2_DMA_INT from ADMA Sub-System */
313 MIPI_CSI0_OUT_INT_IRQn = 403, /**< Shared Int Source OUT_INT from MIPI_CSI0 Sub-System */
314 ADMA_SAI3_MOD_INT_IRQn = 406, /**< Shared Int Source SAI3_MOD_INT from ADMA Sub-System */
315 ADMA_SAI3_DMA_INT_IRQn = 407, /**< Shared Int Source SAI3_DMA_INT from ADMA Sub-System */
316 ADMA_SAI4_MOD_INT_IRQn = 412, /**< Shared Int Source SAI4_MOD_INT from ADMA Sub-System */
317 ADMA_SAI4_DMA_INT_IRQn = 413, /**< Shared Int Source SAI4_DMA_INT from ADMA Sub-System */
318 ADMA_SAI5_MOD_INT_IRQn = 414, /**< Shared Int Source SAI5_MOD_INT from ADMA Sub-System */
319 ADMA_SAI5_DMA_INT_IRQn = 415, /**< Shared Int Source SAI5_DMA_INT from ADMA Sub-System */
320 ADMA_SPI0_MOD_INT_IRQn = 419, /**< Shared Int Source SPI0_MOD_INT from ADMA Sub-System */
321 ADMA_SPI1_MOD_INT_IRQn = 420, /**< Shared Int Source SPI1_MOD_INT from ADMA Sub-System */
322 ADMA_SPI2_MOD_INT_IRQn = 421, /**< Shared Int Source SPI2_MOD_INT from ADMA Sub-System */
323 ADMA_SPI3_MOD_INT_IRQn = 422, /**< Shared Int Source SPI3_MOD_INT from ADMA Sub-System */
324 ADMA_I2C0_MOD_INT_IRQn = 423, /**< Shared Int Source I2C0_MOD_INT from ADMA Sub-System */
325 ADMA_I2C1_MOD_INT_IRQn = 424, /**< Shared Int Source I2C1_MOD_INT from ADMA Sub-System */
326 ADMA_I2C2_MOD_INT_IRQn = 425, /**< Shared Int Source I2C2_MOD_INT from ADMA Sub-System */
327 ADMA_I2C3_MOD_INT_IRQn = 426, /**< Shared Int Source I2C3_MOD_INT from ADMA Sub-System */
328 ADMA_UART0_MOD_INT_IRQn = 428, /**< Shared Int Source UART0_MOD_INT from ADMA Sub-System */
329 ADMA_UART1_MOD_INT_IRQn = 429, /**< Shared Int Source UART1_MOD_INT from ADMA Sub-System */
330 ADMA_UART2_MOD_INT_IRQn = 430, /**< Shared Int Source UART2_MOD_INT from ADMA Sub-System */
331 ADMA_UART3_MOD_INT_IRQn = 431, /**< Shared Int Source UART3_MOD_INT from ADMA Sub-System */
332 ADMA_FLEXCAN0_MOD_INT_IRQn = 435, /**< Shared Int Source FLEXCAN0_MOD_INT from ADMA Sub-System */
333 ADMA_FLEXCAN1_MOD_INT_IRQn = 436, /**< Shared Int Source FLEXCAN1_MOD_INT from ADMA Sub-System */
334 ADMA_FLEXCAN2_MOD_INT_IRQn = 437, /**< Shared Int Source FLEXCAN2_MOD_INT from ADMA Sub-System */
335 ADMA_FTM0_MOD_INT_IRQn = 438, /**< Shared Int Source FTM0_MOD_INT from ADMA Sub-System */
336 ADMA_FTM1_MOD_INT_IRQn = 439, /**< Shared Int Source FTM1_MOD_INT from ADMA Sub-System */
337 ADMA_ADC0_MOD_INT_IRQn = 440, /**< Shared Int Source ADC0_MOD_INT from ADMA Sub-System */
338 ADMA_FLEXCAN0_DMA_INT_IRQn = 442, /**< Shared Int Source FLEXCAN0_DMA_INT from ADMA Sub-System */
339 ADMA_FLEXCAN1_DMA_INT_IRQn = 443, /**< Shared Int Source FLEXCAN1_DMA_INT from ADMA Sub-System */
340 ADMA_FLEXCAN2_DMA_INT_IRQn = 444, /**< Shared Int Source FLEXCAN2_DMA_INT from ADMA Sub-System */
341 ADMA_FTM0_DMA_INT_IRQn = 445, /**< Shared Int Source FTM0_DMA_INT from ADMA Sub-System */
342 ADMA_FTM1_DMA_INT_IRQn = 446, /**< Shared Int Source FTM1_DMA_INT from ADMA Sub-System */
343 ADMA_ADC0_DMA_INT_IRQn = 447, /**< Shared Int Source ADC0_DMA_INT from ADMA Sub-System */
344 ADMA_EDMA0_INT_IRQn = 451, /**< Shared Int Source eDMA0_INT from ADMA Sub-System */
345 ADMA_EDMA0_ERR_INT_IRQn = 452, /**< Shared Int Source eDMA0_ERR_INT from ADMA Sub-System */
346 ADMA_EDMA1_INT_IRQn = 453, /**< Shared Int Source eDMA1_INT from ADMA Sub-System */
347 ADMA_EDMA1_ERR_INT_IRQn = 454, /**< Shared Int Source eDMA1_ERR_INT from ADMA Sub-System */
348 ADMA_ASRC0_INT1_IRQn = 455, /**< Shared Int Source ASRC0_INT1 from ADMA Sub-System */
349 ADMA_ASRC0_INT2_IRQn = 456, /**< Shared Int Source ASRC0_INT2 from ADMA Sub-System */
350 ADMA_DMA0_CH0_INT_IRQn = 457, /**< Shared Int Source DMA0_CH0_INT from ADMA Sub-System */
351 ADMA_DMA0_CH1_INT_IRQn = 458, /**< Shared Int Source DMA0_CH1_INT from ADMA Sub-System */
352 ADMA_DMA0_CH2_INT_IRQn = 459, /**< Shared Int Source DMA0_CH2_INT from ADMA Sub-System */
353 ADMA_DMA0_CH3_INT_IRQn = 460, /**< Shared Int Source DMA0_CH3_INT from ADMA Sub-System */
354 ADMA_DMA0_CH4_INT_IRQn = 461, /**< Shared Int Source DMA0_CH4_INT from ADMA Sub-System */
355 ADMA_DMA0_CH5_INT_IRQn = 462, /**< Shared Int Source DMA0_CH5_INT from ADMA Sub-System */
356 ADMA_ASRC1_INT1_IRQn = 463, /**< Shared Int Source ASRC1_INT1 from ADMA Sub-System */
357 ADMA_ASRC1_INT2_IRQn = 464, /**< Shared Int Source ASRC1_INT2 from ADMA Sub-System */
358 ADMA_DMA1_CH0_INT_IRQn = 465, /**< Shared Int Source DMA1_CH0_INT from ADMA Sub-System */
359 ADMA_DMA1_CH1_INT_IRQn = 466, /**< Shared Int Source DMA1_CH1_INT from ADMA Sub-System */
360 ADMA_DMA1_CH2_INT_IRQn = 467, /**< Shared Int Source DMA1_CH2_INT from ADMA Sub-System */
361 ADMA_DMA1_CH3_INT_IRQn = 468, /**< Shared Int Source DMA1_CH3_INT from ADMA Sub-System */
362 ADMA_DMA1_CH4_INT_IRQn = 469, /**< Shared Int Source DMA1_CH4_INT from ADMA Sub-System */
363 ADMA_DMA1_CH5_INT_IRQn = 470, /**< Shared Int Source DMA1_CH5_INT from ADMA Sub-System */
364 ADMA_ESAI0_INT_IRQn = 471, /**< Shared Int Source ESAI0_INT from ADMA Sub-System */
365 ADMA_GPT0_INT_IRQn = 474, /**< Shared Int Source GPT0_INT from ADMA Sub-System */
366 ADMA_GPT1_INT_IRQn = 475, /**< Shared Int Source GPT1_INT from ADMA Sub-System */
367 ADMA_GPT2_INT_IRQn = 476, /**< Shared Int Source GPT2_INT from ADMA Sub-System */
368 ADMA_GPT3_INT_IRQn = 477, /**< Shared Int Source GPT3_INT from ADMA Sub-System */
369 ADMA_GPT4_INT_IRQn = 478, /**< Shared Int Source GPT4_INT from ADMA Sub-System */
370 ADMA_GPT5_INT_IRQn = 479, /**< Shared Int Source GPT5_INT from ADMA Sub-System */
371 ADMA_SAI0_INT_IRQn = 480, /**< Shared Int Source SAI0_INT from ADMA Sub-System */
372 ADMA_SAI1_INT_IRQn = 481, /**< Shared Int Source SAI1_INT from ADMA Sub-System */
373 ADMA_SAI2_INT_IRQn = 482, /**< Shared Int Source SAI2_INT from ADMA Sub-System */
374 ADMA_SAI3_INT_IRQn = 483, /**< Shared Int Source SAI3_INT from ADMA Sub-System */
375 ADMA_SAI4_INT_IRQn = 486, /**< Shared Int Source SAI4_INT from ADMA Sub-System */
376 ADMA_SAI5_INT_IRQn = 487, /**< Shared Int Source SAI5_INT from ADMA Sub-System */
377 ADMA_SPDIF0_RX_INT_IRQn = 488, /**< Shared Int Source SPDIF0_RX_INT from ADMA Sub-System */
378 ADMA_SPDIF0_TX_INT_IRQn = 489, /**< Shared Int Source SPDIF0_TX_INT from ADMA Sub-System */
379 ADMA_ESAI0_MOD_INT_IRQn = 492, /**< Shared Int Source ESAI0_MOD_INT from ADMA Sub-System */
380 ADMA_ESAI0_DMA_INT_IRQn = 493, /**< Shared Int Source ESAI0_DMA_INT from ADMA Sub-System */
381 ADMA_SPI0_DMA_RX_INT_IRQn = 499, /**< Shared Int Source SPI0_DMA_RX_INT from ADMA Sub-System */
382 ADMA_SPI0_DMA_TX_INT_IRQn = 500, /**< Shared Int Source SPI0_DMA_TX_INT from ADMA Sub-System */
383 ADMA_SPI1_DMA_RX_INT_IRQn = 501, /**< Shared Int Source SPI1_DMA_RX_INT from ADMA Sub-System */
384 ADMA_SPI1_DMA_TX_INT_IRQn = 502, /**< Shared Int Source SPI1_DMA_TX_INT from ADMA Sub-System */
385 ADMA_SPI2_DMA_RX_INT_IRQn = 503, /**< Shared Int Source SPI2_DMA_RX_INT from ADMA Sub-System */
386 ADMA_SPI2_DMA_TX_INT_IRQn = 504, /**< Shared Int Source SPI2_DMA_TX_INT from ADMA Sub-System */
387 ADMA_SPI3_DMA_RX_INT_IRQn = 505, /**< Shared Int Source SPI3_DMA_RX_INT from ADMA Sub-System */
388 ADMA_SPI3_DMA_TX_INT_IRQn = 506, /**< Shared Int Source SPI3_DMA_TX_INT from ADMA Sub-System */
389 ADMA_I2C0_DMA_RX_INT_IRQn = 507, /**< Shared Int Source I2C0_DMA_RX_INT from ADMA Sub-System */
390 ADMA_I2C0_DMA_TX_INT_IRQn = 508, /**< Shared Int Source I2C0_DMA_TX_INT from ADMA Sub-System */
391 ADMA_I2C1_DMA_RX_INT_IRQn = 509, /**< Shared Int Source I2C1_DMA_RX_INT from ADMA Sub-System */
392 ADMA_I2C1_DMA_TX_INT_IRQn = 510, /**< Shared Int Source I2C1_DMA_TX_INT from ADMA Sub-System */
393 ADMA_I2C2_DMA_RX_INT_IRQn = 511, /**< Shared Int Source I2C2_DMA_RX_INT from ADMA Sub-System */
394 ADMA_I2C2_DMA_TX_INT_IRQn = 512, /**< Shared Int Source I2C2_DMA_TX_INT from ADMA Sub-System */
395 ADMA_I2C3_DMA_RX_INT_IRQn = 513, /**< Shared Int Source I2C3_DMA_RX_INT from ADMA Sub-System */
396 ADMA_I2C3_DMA_TX_INT_IRQn = 514, /**< Shared Int Source I2C3_DMA_TX_INT from ADMA Sub-System */
397 ADMA_UART0_DMA_RX_INT_IRQn = 517, /**< Shared Int Source UART0_DMA_RX_INT from ADMA Sub-System */
398 ADMA_UART0_DMA_TX_INT_IRQn = 518, /**< Shared Int Source UART0_DMA_TX_INT from ADMA Sub-System */
399 ADMA_UART1_DMA_RX_INT_IRQn = 519, /**< Shared Int Source UART1_DMA_RX_INT from ADMA Sub-System */
400 ADMA_UART1_DMA_TX_INT_IRQn = 520, /**< Shared Int Source UART1_DMA_TX_INT from ADMA Sub-System */
401 ADMA_UART2_DMA_RX_INT_IRQn = 521, /**< Shared Int Source UART2_DMA_RX_INT from ADMA Sub-System */
402 ADMA_UART2_DMA_TX_INT_IRQn = 522, /**< Shared Int Source UART2_DMA_TX_INT from ADMA Sub-System */
403 ADMA_UART3_DMA_RX_INT_IRQn = 523, /**< Shared Int Source UART3_DMA_RX_INT from ADMA Sub-System */
404 ADMA_UART3_DMA_TX_INT_IRQn = 524, /**< Shared Int Source UART3_DMA_TX_INT from ADMA Sub-System */
405 SECURITY_MU1_A_INT_IRQn = 531, /**< Shared Int Source MU1_A_INT from Security Sub-System */
406 SECURITY_MU2_A_INT_IRQn = 532, /**< Shared Int Source MU2_A_INT from Security Sub-System */
407 SECURITY_MU3_A_INT_IRQn = 533, /**< Shared Int Source MU3_A_INT from Security Sub-System */
408 SECURITY_CAAM_INT0_IRQn = 534, /**< Shared Int Source CAAM_INT0 from Security Sub-System */
409 SECURITY_CAAM_INT1_IRQn = 535, /**< Shared Int Source CAAM_INT1 from Security Sub-System */
410 SECURITY_CAAM_INT2_IRQn = 536, /**< Shared Int Source CAAM_INT2 from Security Sub-System */
411 SECURITY_CAAM_INT3_IRQn = 537, /**< Shared Int Source CAAM_INT3 from Security Sub-System */
412 SECURITY_CAAM_RTIC_INT_IRQn = 538, /**< Shared Int Source CAAM_RTIC_INT from Security Sub-System */
413 ADMA_SPDIF0_RX_MOD_INT_IRQn = 539, /**< Shared Int Source SPDIF0_RX_MOD_INT from ADMA Sub-System */
414 ADMA_SPDIF0_RX_DMA_INT_IRQn = 540, /**< Shared Int Source SPDIF0_RX_DMA_INT from ADMA Sub-System */
415 ADMA_SPDIF0_TX_MOD_INT_IRQn = 541, /**< Shared Int Source SPDIF0_TX_MOD_INT from ADMA Sub-System */
416 ADMA_SPDIF0_TX_DMA_INT_IRQn = 542, /**< Shared Int Source SPDIF0_TX_DMA_INT from ADMA Sub-System */
417 VPU_VPU_INT_0_IRQn = 547, /**< Shared Int Source VPU_INT_0 from VPU Sub-System */
418 VPU_VPU_INT_1_IRQn = 548, /**< Shared Int Source VPU_INT_1 from VPU Sub-System */
419 VPU_VPU_INT_2_IRQn = 549, /**< Shared Int Source VPU_INT_2 from VPU Sub-System */
420 VPU_VPU_INT_3_IRQn = 550, /**< Shared Int Source VPU_INT_3 from VPU Sub-System */
421 VPU_VPU_INT_4_IRQn = 551, /**< Shared Int Source VPU_INT_4 from VPU Sub-System */
422 M4_INTMUX_SOURCE_TPM_IRQn = 564, /**< INTMUX Input source: TPM Interrupt */
423 M4_INTMUX_SOURCE_LPIT_IRQn = 567, /**< INTMUX Input source: LPIT Interrupt */
424 M4_INTMUX_SOURCE_LPUART_IRQn = 570, /**< INTMUX Input source: LPUART Interrupt */
425 M4_INTMUX_SOURCE_LPI2C_IRQn = 572, /**< INTMUX Input source: LPI2C Interrupt */
426 M4_INTMUX_SOURCE_MU0_A3_IRQn = 591, /**< INTMUX Input source: MU0_A3 Interrupt */
427 M4_INTMUX_SOURCE_MU0_A2_IRQn = 592, /**< INTMUX Input source: MU0_A2 Interrupt */
428 M4_INTMUX_SOURCE_MU0_A1_IRQn = 593, /**< INTMUX Input source: MU0_A1 Interrupt */
429 M4_INTMUX_SOURCE_MU0_A0_IRQn = 594 /**< INTMUX Input source: MU0_A0 Interrupt */
430} IRQn_Type;
431
432/*!
433 * @}
434 */ /* end of group Interrupt_vector_numbers */
435
436
437/* ----------------------------------------------------------------------------
438 -- Configuration of the Cortex-M4 Processor and Core Peripherals
439 ---------------------------------------------------------------------------- */
440
441/*!
442 * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-M4 Processor and Core Peripherals
443 * @{
444 */
445
446#define __CM4_REV 0x0001 /**< Core revision r0p1 */
447#define __MPU_PRESENT 1 /**< MPU present or not */
448#define __NVIC_PRIO_BITS 4 /**< Number of Bits used for Priority Levels */
449#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
450#define __FPU_PRESENT 1 /**< FPU present or not */
451
452#include "core_cm4.h" /* Core Peripheral Access Layer */
453#include "system_MIMX8DX1_cm4.h" /* Device specific configuration file */
454
455/*!
456 * @}
457 */ /* end of group Cortex_Core_Configuration */
458
459
460/* ----------------------------------------------------------------------------
461 -- Device Peripheral Access Layer
462 ---------------------------------------------------------------------------- */
463
464/*!
465 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
466 * @{
467 */
468
469
470/*
471** Start of section using anonymous unions
472*/
473
474#if defined(__ARMCC_VERSION)
475 #if (__ARMCC_VERSION >= 6010050)
476 #pragma clang diagnostic push
477 #else
478 #pragma push
479 #pragma anon_unions
480 #endif
481#elif defined(__GNUC__)
482 /* anonymous unions are enabled by default */
483#elif defined(__IAR_SYSTEMS_ICC__)
484 #pragma language=extended
485#else
486 #error Not supported compiler type
487#endif
488
489/* ----------------------------------------------------------------------------
490 -- ACM Peripheral Access Layer
491 ---------------------------------------------------------------------------- */
492
493/*!
494 * @addtogroup ACM_Peripheral_Access_Layer ACM Peripheral Access Layer
495 * @{
496 */
497
498/** ACM - Register Layout Typedef */
499typedef struct {
500 uint8_t RESERVED_0[14680064];
501 __IO uint32_t AUD_CLK0; /**< ACM_AUD_CLK0 Register, offset: 0xE00000 */
502 uint8_t RESERVED_1[65532];
503 __IO uint32_t AUD_CLK1; /**< ACM_AUD_CLK1 Register, offset: 0xE10000 */
504 uint8_t RESERVED_2[65532];
505 __IO uint32_t MCLKOUT0; /**< ACM_MCLKOUT0 Register, offset: 0xE20000 */
506 uint8_t RESERVED_3[65532];
507 __IO uint32_t MCLKOUT1; /**< ACM_MCLKOUT1 Register, offset: 0xE30000 */
508 uint8_t RESERVED_4[196604];
509 __IO uint32_t ESAI0_CLK; /**< ACM_ESAI0_CLK Register, offset: 0xE60000 */
510 uint8_t RESERVED_5[131068];
511 struct { /* offset: 0xE80000, array step: 0x10000 */
512 __IO uint32_t GPT_CLK; /**< ACM_GPT_CLK Register, array offset: 0xE80000, array step: 0x10000 */
513 uint8_t RESERVED_0[65532];
514 } GPT_CLK[6];
515 struct { /* offset: 0xEE0000, array step: 0x10000 */
516 __IO uint32_t SAI_MCLK; /**< ACM_SAI_MCLK Register, array offset: 0xEE0000, array step: 0x10000 */
517 uint8_t RESERVED_0[65532];
518 } SAI_MCLK[8];
519 uint8_t RESERVED_6[262144];
520 __IO uint32_t SPDIF0_TX_CLK; /**< ACM_SPDIF0_TX_CLK Register, offset: 0xFA0000 */
521 uint8_t RESERVED_7[131068];
522 __IO uint32_t MQS_HMCLK_CLK; /**< ACM_MQS_HMCLK_CLK Register, offset: 0xFC0000 */
523} ACM_Type;
524
525/* ----------------------------------------------------------------------------
526 -- ACM Register Masks
527 ---------------------------------------------------------------------------- */
528
529/*!
530 * @addtogroup ACM_Register_Masks ACM Register Masks
531 * @{
532 */
533
534/*! @name AUD_CLK0 - ACM_AUD_CLK0 Register */
535/*! @{ */
536#define ACM_AUD_CLK0_SEL_MASK (0x1FU)
537#define ACM_AUD_CLK0_SEL_SHIFT (0U)
538/*! SEL - Select
539 * 0b00000..ADMA_SLSLICE2
540 * 0b00001..ADMA_SLSLICE3
541 * 0b00010..EXT_AUD_MCLK0
542 * 0b00011..EXT_AUD_MCLK1
543 * 0b00100..ESAI0_RX_CLK
544 * 0b00101..ESAI0_RX_HF_CLKK
545 * 0b00110..ESAI0_TX_CLK
546 * 0b00111..ESAI0_TX_HF_CLK
547 * 0b01000..SPDIF0_RX
548 * 0b01001..SAI0_RX_BCLK
549 * 0b01010..SAI0_TX_BCLK
550 * 0b01011..SAI1_RX_BCLK
551 * 0b01100..SAI1_TX_BCLK
552 * 0b01101..SAI2_RX_BCLK
553 * 0b01110..SAI3_RX_BCLK
554 */
555#define ACM_AUD_CLK0_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK0_SEL_SHIFT)) & ACM_AUD_CLK0_SEL_MASK)
556/*! @} */
557
558/*! @name AUD_CLK1 - ACM_AUD_CLK1 Register */
559/*! @{ */
560#define ACM_AUD_CLK1_SEL_MASK (0x1FU)
561#define ACM_AUD_CLK1_SEL_SHIFT (0U)
562/*! SEL - Select
563 * 0b00000..ADMA_SLSLICE2
564 * 0b00001..ADMA_SLSLICE3
565 * 0b00010..EXT_AUD_MCLK0
566 * 0b00011..EXT_AUD_MCLK1
567 * 0b00100..ESAI0_RX_CLK
568 * 0b00101..ESAI0_RX_HF_CLKK
569 * 0b00110..ESAI0_TX_CLK
570 * 0b00111..ESAI0_TX_HF_CLK
571 * 0b01000..SPDIF0_RX
572 * 0b01001..SAI0_RX_BCLK
573 * 0b01010..SAI0_TX_BCLK
574 * 0b01011..SAI1_RX_BCLK
575 * 0b01100..SAI1_TX_BCLK
576 * 0b01101..SAI2_RX_BCLK
577 * 0b01110..SAI3_RX_BCLK
578 */
579#define ACM_AUD_CLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK1_SEL_SHIFT)) & ACM_AUD_CLK1_SEL_MASK)
580/*! @} */
581
582/*! @name MCLKOUT0 - ACM_MCLKOUT0 Register */
583/*! @{ */
584#define ACM_MCLKOUT0_SEL_MASK (0x7U)
585#define ACM_MCLKOUT0_SEL_SHIFT (0U)
586/*! SEL - Select
587 * 0b000..ADMA_SLSLICE2
588 * 0b001..ADMA_SLSLICE3
589 * 0b010..Reserved
590 * 0b011..Reserved
591 * 0b100..SPDIF0_RX
592 * 0b101..Reserved
593 * 0b110..Reserved
594 * 0b111..SAI4_RX_BCLK
595 */
596#define ACM_MCLKOUT0_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT0_SEL_SHIFT)) & ACM_MCLKOUT0_SEL_MASK)
597/*! @} */
598
599/*! @name MCLKOUT1 - ACM_MCLKOUT1 Register */
600/*! @{ */
601#define ACM_MCLKOUT1_SEL_MASK (0x7U)
602#define ACM_MCLKOUT1_SEL_SHIFT (0U)
603/*! SEL - Select
604 * 0b000..ADMA_SLSLICE2
605 * 0b001..ADMA_SLSLICE3
606 * 0b010..Reserved
607 * 0b011..Reserved
608 * 0b100..SPDIF0_RX
609 * 0b101..Reserved
610 * 0b110..Reserved
611 * 0b111..SAI4_RX_BCLK
612 */
613#define ACM_MCLKOUT1_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT1_SEL_SHIFT)) & ACM_MCLKOUT1_SEL_MASK)
614/*! @} */
615
616/*! @name ESAI0_CLK - ACM_ESAI0_CLK Register */
617/*! @{ */
618#define ACM_ESAI0_CLK_SEL_MASK (0x3U)
619#define ACM_ESAI0_CLK_SEL_SHIFT (0U)
620/*! SEL - Select
621 * 0b00..AUD_PLL_DIV_CLK0
622 * 0b01..AUD_PLL_DIV_CLK1
623 * 0b10..AUD_CLK0
624 * 0b11..AUD_CLK1
625 */
626#define ACM_ESAI0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_ESAI0_CLK_SEL_SHIFT)) & ACM_ESAI0_CLK_SEL_MASK)
627/*! @} */
628
629/*! @name GPT_CLK - ACM_GPT_CLK Register */
630/*! @{ */
631#define ACM_GPT_CLK_SEL_MASK (0x7U)
632#define ACM_GPT_CLK_SEL_SHIFT (0U)
633/*! SEL - Select
634 * 0b000..AUD_PLL_DIV_CLK0
635 * 0b001..AUD_PLL_DIV_CLK1
636 * 0b010..AUD_CLK0
637 * 0b011..AUD_CLK1
638 * 0b100..24M_REF_CLK
639 */
640#define ACM_GPT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT_CLK_SEL_SHIFT)) & ACM_GPT_CLK_SEL_MASK)
641/*! @} */
642
643/* The count of ACM_GPT_CLK */
644#define ACM_GPT_CLK_COUNT (6U)
645
646/*! @name SAI_MCLK - ACM_SAI_MCLK Register */
647/*! @{ */
648#define ACM_SAI_MCLK_SEL_MASK (0x3U)
649#define ACM_SAI_MCLK_SEL_SHIFT (0U)
650/*! SEL - Select
651 * 0b00..AUD_PLL_DIV_CLK0
652 * 0b01..AUD_PLL_DIV_CLK1
653 * 0b10..AUD_CLK0
654 * 0b11..AUD_CLK1
655 */
656#define ACM_SAI_MCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SAI_MCLK_SEL_SHIFT)) & ACM_SAI_MCLK_SEL_MASK)
657/*! @} */
658
659/* The count of ACM_SAI_MCLK */
660#define ACM_SAI_MCLK_COUNT (8U)
661
662/*! @name SPDIF0_TX_CLK - ACM_SPDIF0_TX_CLK Register */
663/*! @{ */
664#define ACM_SPDIF0_TX_CLK_SEL_MASK (0x3U)
665#define ACM_SPDIF0_TX_CLK_SEL_SHIFT (0U)
666/*! SEL - Select
667 * 0b00..AUD_PLL_DIV_CLK0
668 * 0b01..AUD_PLL_DIV_CLK1
669 * 0b10..AUD_CLK0
670 * 0b11..AUD_CLK1
671 */
672#define ACM_SPDIF0_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SPDIF0_TX_CLK_SEL_SHIFT)) & ACM_SPDIF0_TX_CLK_SEL_MASK)
673/*! @} */
674
675/*! @name MQS_HMCLK_CLK - ACM_MQS_HMCLK_CLK Register */
676/*! @{ */
677#define ACM_MQS_HMCLK_CLK_SEL_MASK (0x3U)
678#define ACM_MQS_HMCLK_CLK_SEL_SHIFT (0U)
679/*! SEL - Select
680 * 0b00..AUD_PLL_DIV_CLK0
681 * 0b01..AUD_PLL_DIV_CLK1
682 * 0b10..AUD_CLK0
683 * 0b11..AUD_CLK1
684 */
685#define ACM_MQS_HMCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MQS_HMCLK_CLK_SEL_SHIFT)) & ACM_MQS_HMCLK_CLK_SEL_MASK)
686/*! @} */
687
688
689/*!
690 * @}
691 */ /* end of group ACM_Register_Masks */
692
693
694/* ACM - Peripheral instance base addresses */
695/** Peripheral ADMA__ACM base address */
696#define ADMA__ACM_BASE (0x59000000u)
697/** Peripheral ADMA__ACM base pointer */
698#define ADMA__ACM ((ACM_Type *)ADMA__ACM_BASE)
699/** Array initializer of ACM peripheral base addresses */
700#define ACM_BASE_ADDRS { ADMA__ACM_BASE }
701/** Array initializer of ACM peripheral base pointers */
702#define ACM_BASE_PTRS { ADMA__ACM }
703
704/*!
705 * @}
706 */ /* end of group ACM_Peripheral_Access_Layer */
707
708
709/* ----------------------------------------------------------------------------
710 -- ADC Peripheral Access Layer
711 ---------------------------------------------------------------------------- */
712
713/*!
714 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
715 * @{
716 */
717
718/** ADC - Register Layout Typedef */
719typedef struct {
720 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
721 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
722 uint8_t RESERVED_0[8];
723 __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */
724 __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */
725 __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */
726 __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */
727 __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */
728 __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */
729 uint8_t RESERVED_1[8];
730 __IO uint32_t FCTRL; /**< ADC FIFO Control Register, offset: 0x30 */
731 __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
732 uint8_t RESERVED_2[136];
733 __IO uint32_t TCTRL[8]; /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */
734 uint8_t RESERVED_3[32];
735 struct { /* offset: 0x100, array step: 0x8 */
736 __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
737 __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
738 } CMD[15];
739 uint8_t RESERVED_4[136];
740 __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
741 uint8_t RESERVED_5[240];
742 __I uint32_t RESFIFO; /**< ADC Data Result FIFO Register, offset: 0x300 */
743} ADC_Type;
744
745/* ----------------------------------------------------------------------------
746 -- ADC Register Masks
747 ---------------------------------------------------------------------------- */
748
749/*!
750 * @addtogroup ADC_Register_Masks ADC Register Masks
751 * @{
752 */
753
754/*! @name VERID - Version ID Register */
755/*! @{ */
756#define ADC_VERID_RES_MASK (0x1U)
757#define ADC_VERID_RES_SHIFT (0U)
758/*! RES - Resolution
759 * 0b0..Up to 13-bit differential/12-bit single ended resolution supported.
760 * 0b1..Up to 16-bit differential/15-bit single ended resolution supported.
761 */
762#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
763#define ADC_VERID_DIFFEN_MASK (0x2U)
764#define ADC_VERID_DIFFEN_SHIFT (1U)
765/*! DIFFEN - Differential Supported
766 * 0b0..Differential operation not supported.
767 * 0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
768 */
769#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
770#define ADC_VERID_MVI_MASK (0x8U)
771#define ADC_VERID_MVI_SHIFT (3U)
772/*! MVI - Multi Vref Implemented
773 * 0b0..Single voltage reference high (VREFH) input supported.
774 * 0b1..Multiple voltage reference high (VREFH) inputs supported.
775 */
776#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
777#define ADC_VERID_CSW_MASK (0x70U)
778#define ADC_VERID_CSW_SHIFT (4U)
779/*! CSW - Channel Scale Width
780 * 0b000..Channel scaling not supported.
781 * 0b001..Channel scaling supported. 1-bit CSCALE control field.
782 * 0b110..Channel scaling supported. 6-bit CSCALE control field.
783 */
784#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
785#define ADC_VERID_VR1RNGI_MASK (0x100U)
786#define ADC_VERID_VR1RNGI_SHIFT (8U)
787/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
788 * 0b0..Range control not required. CFG[VREF1RNG] is not implemented.
789 * 0b1..Range control required. CFG[VREF1RNG] is implemented.
790 */
791#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
792#define ADC_VERID_IADCKI_MASK (0x200U)
793#define ADC_VERID_IADCKI_SHIFT (9U)
794/*! IADCKI - Internal ADC Clock implemented
795 * 0b0..Internal clock source not implemented.
796 * 0b1..Internal clock source (and CFG[ADCKEN]) implemented.
797 */
798#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
799#define ADC_VERID_CALOFSI_MASK (0x400U)
800#define ADC_VERID_CALOFSI_SHIFT (10U)
801/*! CALOFSI - Calibration Offset Function Implemented
802 * 0b0..Offset calibration and offset trimming not implemented.
803 * 0b1..Offset calibration and offset trimming implemented.
804 */
805#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
806#define ADC_VERID_MINOR_MASK (0xFF0000U)
807#define ADC_VERID_MINOR_SHIFT (16U)
808/*! MINOR - Minor Version Number
809 */
810#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
811#define ADC_VERID_MAJOR_MASK (0xFF000000U)
812#define ADC_VERID_MAJOR_SHIFT (24U)
813/*! MAJOR - Major Version Number
814 */
815#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
816/*! @} */
817
818/*! @name PARAM - Parameter Register */
819/*! @{ */
820#define ADC_PARAM_TRIG_NUM_MASK (0xFFU)
821#define ADC_PARAM_TRIG_NUM_SHIFT (0U)
822/*! TRIG_NUM - Trigger Number
823 */
824#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
825#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U)
826#define ADC_PARAM_FIFOSIZE_SHIFT (8U)
827/*! FIFOSIZE - Result FIFO Depth
828 * 0b00000001..Result FIFO depth = 1 dataword.
829 * 0b00000100..Result FIFO depth = 4 datawords.
830 * 0b00001000..Result FIFO depth = 8 datawords.
831 * 0b00010000..Result FIFO depth = 16 datawords.
832 * 0b00100000..Result FIFO depth = 32 datawords.
833 * 0b01000000..Result FIFO depth = 64 datawords.
834 */
835#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
836#define ADC_PARAM_CV_NUM_MASK (0xFF0000U)
837#define ADC_PARAM_CV_NUM_SHIFT (16U)
838/*! CV_NUM - Compare Value Number
839 */
840#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
841#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U)
842#define ADC_PARAM_CMD_NUM_SHIFT (24U)
843/*! CMD_NUM - Command Buffer Number
844 */
845#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
846/*! @} */
847
848/*! @name CTRL - ADC Control Register */
849/*! @{ */
850#define ADC_CTRL_ADCEN_MASK (0x1U)
851#define ADC_CTRL_ADCEN_SHIFT (0U)
852/*! ADCEN - ADC Enable
853 * 0b0..ADC is disabled.
854 * 0b1..ADC is enabled.
855 */
856#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
857#define ADC_CTRL_RST_MASK (0x2U)
858#define ADC_CTRL_RST_SHIFT (1U)
859/*! RST - Software Reset
860 * 0b0..ADC logic is not reset.
861 * 0b1..ADC logic is reset.
862 */
863#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
864#define ADC_CTRL_DOZEN_MASK (0x4U)
865#define ADC_CTRL_DOZEN_SHIFT (2U)
866/*! DOZEN - Doze Enable
867 * 0b0..ADC is enabled in Doze mode.
868 * 0b1..ADC is disabled in Doze mode.
869 */
870#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
871#define ADC_CTRL_RSTFIFO_MASK (0x100U)
872#define ADC_CTRL_RSTFIFO_SHIFT (8U)
873/*! RSTFIFO - Reset FIFO
874 * 0b0..No effect.
875 * 0b1..FIFO is reset.
876 */
877#define ADC_CTRL_RSTFIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)
878/*! @} */
879
880/*! @name STAT - ADC Status Register */
881/*! @{ */
882#define ADC_STAT_RDY_MASK (0x1U)
883#define ADC_STAT_RDY_SHIFT (0U)
884/*! RDY - Result FIFO Ready Flag
885 * 0b0..Result FIFO data level not above watermark level.
886 * 0b1..Result FIFO holding data above watermark level.
887 */
888#define ADC_STAT_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
889#define ADC_STAT_FOF_MASK (0x2U)
890#define ADC_STAT_FOF_SHIFT (1U)
891/*! FOF - Result FIFO Overflow Flag
892 * 0b0..No result FIFO overflow has occurred since the last time the flag was cleared.
893 * 0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared.
894 */
895#define ADC_STAT_FOF(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
896#define ADC_STAT_ADC_ACTIVE_MASK (0x100U)
897#define ADC_STAT_ADC_ACTIVE_SHIFT (8U)
898/*! ADC_ACTIVE - ADC Active
899 * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
900 * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
901 */
902#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
903#define ADC_STAT_TRGACT_MASK (0x70000U)
904#define ADC_STAT_TRGACT_SHIFT (16U)
905/*! TRGACT - Trigger Active
906 * 0b000..Command (sequence) associated with Trigger 0 currently being executed.
907 * 0b001..Command (sequence) associated with Trigger 1 currently being executed.
908 * 0b010..Command (sequence) associated with Trigger 2 currently being executed.
909 * 0b011-0b111..Command (sequence) from the associated Trigger number is currently being executed.
910 */
911#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
912#define ADC_STAT_CMDACT_MASK (0xF000000U)
913#define ADC_STAT_CMDACT_SHIFT (24U)
914/*! CMDACT - Command Active
915 * 0b0000..No command is currently in progress.
916 * 0b0001..Command 1 currently being executed.
917 * 0b0010..Command 2 currently being executed.
918 * 0b0011-0b1111..Associated command number is currently being executed.
919 */
920#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
921/*! @} */
922
923/*! @name IE - Interrupt Enable Register */
924/*! @{ */
925#define ADC_IE_FWMIE_MASK (0x1U)
926#define ADC_IE_FWMIE_SHIFT (0U)
927/*! FWMIE - FIFO Watermark Interrupt Enable
928 * 0b0..FIFO watermark interrupts are not enabled.
929 * 0b1..FIFO watermark interrupts are enabled.
930 */
931#define ADC_IE_FWMIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
932#define ADC_IE_FOFIE_MASK (0x2U)
933#define ADC_IE_FOFIE_SHIFT (1U)
934/*! FOFIE - Result FIFO Overflow Interrupt Enable
935 * 0b0..FIFO overflow interrupts are not enabled.
936 * 0b1..FIFO overflow interrupts are enabled.
937 */
938#define ADC_IE_FOFIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)
939/*! @} */
940
941/*! @name DE - DMA Enable Register */
942/*! @{ */
943#define ADC_DE_FWMDE_MASK (0x1U)
944#define ADC_DE_FWMDE_SHIFT (0U)
945/*! FWMDE - FIFO Watermark DMA Enable
946 * 0b0..DMA request disabled.
947 * 0b1..DMA request enabled.
948 */
949#define ADC_DE_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)
950/*! @} */
951
952/*! @name CFG - ADC Configuration Register */
953/*! @{ */
954#define ADC_CFG_TPRICTRL_MASK (0x1U)
955#define ADC_CFG_TPRICTRL_SHIFT (0U)
956/*! TPRICTRL - ADC trigger priority control
957 * 0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and
958 * the new command specified by the trigger is started.
959 * 0b1..If a higher priority trigger is received during command processing, the current conversion is completed
960 * (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority
961 * trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true
962 * conversion.
963 */
964#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
965#define ADC_CFG_PWRSEL_MASK (0x30U)
966#define ADC_CFG_PWRSEL_SHIFT (4U)
967/*! PWRSEL - Power Configuration Select
968 * 0b00..Level 1 (Lowest power setting)
969 * 0b01..Level 2
970 * 0b10..Level 3
971 * 0b11..Level 4 (Highest power setting)
972 */
973#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
974#define ADC_CFG_REFSEL_MASK (0xC0U)
975#define ADC_CFG_REFSEL_SHIFT (6U)
976/*! REFSEL - Voltage Reference Selection
977 * 0b00..(Default) Option 1 setting.
978 * 0b01..Option 2 setting.
979 * 0b10..Option 3 setting.
980 * 0b11..Reserved
981 */
982#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
983#define ADC_CFG_PUDLY_MASK (0xFF0000U)
984#define ADC_CFG_PUDLY_SHIFT (16U)
985/*! PUDLY - Power Up Delay
986 */
987#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
988#define ADC_CFG_PWREN_MASK (0x10000000U)
989#define ADC_CFG_PWREN_SHIFT (28U)
990/*! PWREN - ADC Analog Pre-Enable
991 * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
992 * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
993 * of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any
994 * detected trigger does not begin ADC operation until the power up delay time has passed.
995 */
996#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
997/*! @} */
998
999/*! @name PAUSE - ADC Pause Register */
1000/*! @{ */
1001#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU)
1002#define ADC_PAUSE_PAUSEDLY_SHIFT (0U)
1003/*! PAUSEDLY - Pause Delay
1004 */
1005#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
1006#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U)
1007#define ADC_PAUSE_PAUSEEN_SHIFT (31U)
1008/*! PAUSEEN - PAUSE Option Enable
1009 * 0b0..Pause operation disabled
1010 * 0b1..Pause operation enabled
1011 */
1012#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
1013/*! @} */
1014
1015/*! @name FCTRL - ADC FIFO Control Register */
1016/*! @{ */
1017#define ADC_FCTRL_FCOUNT_MASK (0x1FU)
1018#define ADC_FCTRL_FCOUNT_SHIFT (0U)
1019/*! FCOUNT - Result FIFO counter
1020 */
1021#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
1022#define ADC_FCTRL_FWMARK_MASK (0xF0000U)
1023#define ADC_FCTRL_FWMARK_SHIFT (16U)
1024/*! FWMARK - Watermark level selection
1025 */
1026#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
1027/*! @} */
1028
1029/*! @name SWTRIG - Software Trigger Register */
1030/*! @{ */
1031#define ADC_SWTRIG_SWT0_MASK (0x1U)
1032#define ADC_SWTRIG_SWT0_SHIFT (0U)
1033/*! SWT0 - Software trigger 0 event
1034 * 0b0..No trigger 0 event generated.
1035 * 0b1..Trigger 0 event generated.
1036 */
1037#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
1038#define ADC_SWTRIG_SWT1_MASK (0x2U)
1039#define ADC_SWTRIG_SWT1_SHIFT (1U)
1040/*! SWT1 - Software trigger 1 event
1041 * 0b0..No trigger 1 event generated.
1042 * 0b1..Trigger 1 event generated.
1043 */
1044#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
1045#define ADC_SWTRIG_SWT2_MASK (0x4U)
1046#define ADC_SWTRIG_SWT2_SHIFT (2U)
1047/*! SWT2 - Software trigger 2 event
1048 * 0b0..No trigger 2 event generated.
1049 * 0b1..Trigger 2 event generated.
1050 */
1051#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
1052#define ADC_SWTRIG_SWT3_MASK (0x8U)
1053#define ADC_SWTRIG_SWT3_SHIFT (3U)
1054/*! SWT3 - Software trigger 3 event
1055 * 0b0..No trigger 3 event generated.
1056 * 0b1..Trigger 3 event generated.
1057 */
1058#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
1059#define ADC_SWTRIG_SWT4_MASK (0x10U)
1060#define ADC_SWTRIG_SWT4_SHIFT (4U)
1061/*! SWT4 - Software trigger 4 event
1062 * 0b0..No trigger 4 event generated.
1063 * 0b1..Trigger 4 event generated.
1064 */
1065#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
1066#define ADC_SWTRIG_SWT5_MASK (0x20U)
1067#define ADC_SWTRIG_SWT5_SHIFT (5U)
1068/*! SWT5 - Software trigger 5 event
1069 * 0b0..No trigger 5 event generated.
1070 * 0b1..Trigger 5 event generated.
1071 */
1072#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
1073#define ADC_SWTRIG_SWT6_MASK (0x40U)
1074#define ADC_SWTRIG_SWT6_SHIFT (6U)
1075/*! SWT6 - Software trigger 6 event
1076 * 0b0..No trigger 6 event generated.
1077 * 0b1..Trigger 6 event generated.
1078 */
1079#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
1080#define ADC_SWTRIG_SWT7_MASK (0x80U)
1081#define ADC_SWTRIG_SWT7_SHIFT (7U)
1082/*! SWT7 - Software trigger 7 event
1083 * 0b0..No trigger 7 event generated.
1084 * 0b1..Trigger 7 event generated.
1085 */
1086#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
1087/*! @} */
1088
1089/*! @name TCTRL - Trigger Control Register */
1090/*! @{ */
1091#define ADC_TCTRL_HTEN_MASK (0x1U)
1092#define ADC_TCTRL_HTEN_SHIFT (0U)
1093/*! HTEN - Trigger enable
1094 * 0b0..Hardware trigger source disabled
1095 * 0b1..Hardware trigger source enabled
1096 */
1097#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
1098#define ADC_TCTRL_TPRI_MASK (0x700U)
1099#define ADC_TCTRL_TPRI_SHIFT (8U)
1100/*! TPRI - Trigger priority setting
1101 * 0b000..Set to highest priority, Level 1
1102 * 0b001-0b110..Set to corresponding priority level
1103 * 0b111..Set to lowest priority, Level 8
1104 */
1105#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
1106#define ADC_TCTRL_TDLY_MASK (0xF0000U)
1107#define ADC_TCTRL_TDLY_SHIFT (16U)
1108/*! TDLY - Trigger delay select
1109 */
1110#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
1111#define ADC_TCTRL_TCMD_MASK (0xF000000U)
1112#define ADC_TCTRL_TCMD_SHIFT (24U)
1113/*! TCMD - Trigger command select
1114 * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
1115 * 0b0001..CMD1 is executed
1116 * 0b0010-0b1110..Corresponding CMD is executed
1117 * 0b1111..CMD15 is executed
1118 */
1119#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
1120/*! @} */
1121
1122/* The count of ADC_TCTRL */
1123#define ADC_TCTRL_COUNT (8U)
1124
1125/*! @name CMDL - ADC Command Low Buffer Register */
1126/*! @{ */
1127#define ADC_CMDL_ADCH_MASK (0x1FU)
1128#define ADC_CMDL_ADCH_SHIFT (0U)
1129/*! ADCH - Input channel select
1130 * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
1131 * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
1132 * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
1133 * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
1134 * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
1135 * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
1136 * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
1137 */
1138#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
1139#define ADC_CMDL_ABSEL_MASK (0x20U)
1140#define ADC_CMDL_ABSEL_SHIFT (5U)
1141/*! ABSEL - A-side vs. B-side Select
1142 * 0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB).
1143 * 0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA).
1144 */
1145#define ADC_CMDL_ABSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
1146#define ADC_CMDL_DIFF_MASK (0x40U)
1147#define ADC_CMDL_DIFF_SHIFT (6U)
1148/*! DIFF - Differential Mode Enable
1149 * 0b0..Single-ended mode.
1150 * 0b1..Differential mode.
1151 */
1152#define ADC_CMDL_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)
1153#define ADC_CMDL_CSCALE_MASK (0x2000U)
1154#define ADC_CMDL_CSCALE_SHIFT (13U)
1155/*! CSCALE - Channel Scale
1156 * 0b0..Scale selected analog channel (Factor of 30/64)
1157 * 0b1..(Default) Full scale (Factor of 1)
1158 */
1159#define ADC_CMDL_CSCALE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)
1160/*! @} */
1161
1162/* The count of ADC_CMDL */
1163#define ADC_CMDL_COUNT (15U)
1164
1165/*! @name CMDH - ADC Command High Buffer Register */
1166/*! @{ */
1167#define ADC_CMDH_CMPEN_MASK (0x3U)
1168#define ADC_CMDH_CMPEN_SHIFT (0U)
1169/*! CMPEN - Compare Function Enable
1170 * 0b00..Compare disabled.
1171 * 0b01..Reserved
1172 * 0b10..Compare enabled. Store on true.
1173 * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
1174 */
1175#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
1176#define ADC_CMDH_LWI_MASK (0x80U)
1177#define ADC_CMDH_LWI_SHIFT (7U)
1178/*! LWI - Loop with Increment
1179 * 0b0..Auto channel increment disabled
1180 * 0b1..Auto channel increment enabled
1181 */
1182#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
1183#define ADC_CMDH_STS_MASK (0x700U)
1184#define ADC_CMDH_STS_SHIFT (8U)
1185/*! STS - Sample Time Select
1186 * 0b000..Minimum sample time of 3 ADCK cycles.
1187 * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
1188 * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
1189 * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
1190 * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
1191 * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
1192 * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
1193 * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
1194 */
1195#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
1196#define ADC_CMDH_AVGS_MASK (0x7000U)
1197#define ADC_CMDH_AVGS_SHIFT (12U)
1198/*! AVGS - Hardware Average Select
1199 * 0b000..Single conversion.
1200 * 0b001..2 conversions averaged.
1201 * 0b010..4 conversions averaged.
1202 * 0b011..8 conversions averaged.
1203 * 0b100..16 conversions averaged.
1204 * 0b101..32 conversions averaged.
1205 * 0b110..64 conversions averaged.
1206 * 0b111..128 conversions averaged.
1207 */
1208#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
1209#define ADC_CMDH_LOOP_MASK (0xF0000U)
1210#define ADC_CMDH_LOOP_SHIFT (16U)
1211/*! LOOP - Loop Count Select
1212 * 0b0000..Looping not enabled. Command executes 1 time.
1213 * 0b0001..Loop 1 time. Command executes 2 times.
1214 * 0b0010..Loop 2 times. Command executes 3 times.
1215 * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
1216 * 0b1111..Loop 15 times. Command executes 16 times.
1217 */
1218#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
1219#define ADC_CMDH_NEXT_MASK (0xF000000U)
1220#define ADC_CMDH_NEXT_SHIFT (24U)
1221/*! NEXT - Next Command Select
1222 * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
1223 * trigger pending, begin command associated with lower priority trigger.
1224 * 0b0001..Select CMD1 command buffer register as next command.
1225 * 0b0010-0b1110..Select corresponding CMD command buffer register as next command
1226 * 0b1111..Select CMD15 command buffer register as next command.
1227 */
1228#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
1229/*! @} */
1230
1231/* The count of ADC_CMDH */
1232#define ADC_CMDH_COUNT (15U)
1233
1234/*! @name CV - Compare Value Register */
1235/*! @{ */
1236#define ADC_CV_CVL_MASK (0xFFFFU)
1237#define ADC_CV_CVL_SHIFT (0U)
1238/*! CVL - Compare Value Low.
1239 */
1240#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
1241#define ADC_CV_CVH_MASK (0xFFFF0000U)
1242#define ADC_CV_CVH_SHIFT (16U)
1243/*! CVH - Compare Value High.
1244 */
1245#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
1246/*! @} */
1247
1248/* The count of ADC_CV */
1249#define ADC_CV_COUNT (4U)
1250
1251/*! @name RESFIFO - ADC Data Result FIFO Register */
1252/*! @{ */
1253#define ADC_RESFIFO_D_MASK (0xFFFFU)
1254#define ADC_RESFIFO_D_SHIFT (0U)
1255/*! D - Data result
1256 */
1257#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
1258#define ADC_RESFIFO_TSRC_MASK (0x70000U)
1259#define ADC_RESFIFO_TSRC_SHIFT (16U)
1260/*! TSRC - Trigger Source
1261 * 0b000..Trigger source 0 initiated this conversion.
1262 * 0b001..Trigger source 1 initiated this conversion.
1263 * 0b010-0b110..Corresponding trigger source initiated this conversion.
1264 * 0b111..Trigger source 7 initiated this conversion.
1265 */
1266#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
1267#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U)
1268#define ADC_RESFIFO_LOOPCNT_SHIFT (20U)
1269/*! LOOPCNT - Loop count value
1270 * 0b0000..Result is from initial conversion in command.
1271 * 0b0001..Result is from second conversion in command.
1272 * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
1273 * 0b1111..Result is from 16th conversion in command.
1274 */
1275#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
1276#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U)
1277#define ADC_RESFIFO_CMDSRC_SHIFT (24U)
1278/*! CMDSRC - Command Buffer Source
1279 * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
1280 * prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
1281 * 0b0001..CMD1 buffer used as control settings for this conversion.
1282 * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
1283 * 0b1111..CMD15 buffer used as control settings for this conversion.
1284 */
1285#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
1286#define ADC_RESFIFO_VALID_MASK (0x80000000U)
1287#define ADC_RESFIFO_VALID_SHIFT (31U)
1288/*! VALID - FIFO entry is valid
1289 * 0b0..FIFO is empty. Discard any read from RESFIFO.
1290 * 0b1..FIFO record read from RESFIFO is valid.
1291 */
1292#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
1293/*! @} */
1294
1295
1296/*!
1297 * @}
1298 */ /* end of group ADC_Register_Masks */
1299
1300
1301/* ADC - Peripheral instance base addresses */
1302/** Peripheral ADMA__ADC0 base address */
1303#define ADMA__ADC0_BASE (0x5A880000u)
1304/** Peripheral ADMA__ADC0 base pointer */
1305#define ADMA__ADC0 ((ADC_Type *)ADMA__ADC0_BASE)
1306/** Array initializer of ADC peripheral base addresses */
1307#define ADC_BASE_ADDRS { ADMA__ADC0_BASE }
1308/** Array initializer of ADC peripheral base pointers */
1309#define ADC_BASE_PTRS { ADMA__ADC0 }
1310/** Interrupt vectors for the ADC peripheral type */
1311#define ADC_IRQS { ADMA_ADC0_INT_IRQn }
1312
1313/*!
1314 * @}
1315 */ /* end of group ADC_Peripheral_Access_Layer */
1316
1317
1318/* ----------------------------------------------------------------------------
1319 -- APBH Peripheral Access Layer
1320 ---------------------------------------------------------------------------- */
1321
1322/*!
1323 * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer
1324 * @{
1325 */
1326
1327/** APBH - Register Layout Typedef */
1328typedef struct {
1329 struct { /* offset: 0x0 */
1330 __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */
1331 __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */
1332 __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */
1333 __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */
1334 } CTRL0;
1335 struct { /* offset: 0x10 */
1336 __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */
1337 __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */
1338 __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */
1339 __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */
1340 } CTRL1;
1341 struct { /* offset: 0x20 */
1342 __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */
1343 __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */
1344 __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */
1345 __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */
1346 } CTRL2;
1347 struct { /* offset: 0x30 */
1348 __IO uint32_t RW; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */
1349 __IO uint32_t SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */
1350 __IO uint32_t CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */
1351 __IO uint32_t TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */
1352 } CHANNEL_CTRL;
1353 uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */
1354 uint8_t RESERVED_0[12];
1355 __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */
1356 uint8_t RESERVED_1[12];
1357 __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */
1358 uint8_t RESERVED_2[156];
1359 struct { /* offset: 0x100, array step: 0x70 */
1360 __I uint32_t CH_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, array offset: 0x100, array step: 0x70 */
1361 uint8_t RESERVED_0[12];
1362 __IO uint32_t CH_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, array offset: 0x110, array step: 0x70 */
1363 uint8_t RESERVED_1[12];
1364 __I uint32_t CH_CMD; /**< APBH DMA Channel n Command Register, array offset: 0x120, array step: 0x70 */
1365 uint8_t RESERVED_2[12];
1366 __I uint32_t CH_BAR; /**< APBH DMA Channel n Buffer Address Register, array offset: 0x130, array step: 0x70 */
1367 uint8_t RESERVED_3[12];
1368 __IO uint32_t CH_SEMA; /**< APBH DMA Channel n Semaphore Register, array offset: 0x140, array step: 0x70 */
1369 uint8_t RESERVED_4[12];
1370 __I uint32_t CH_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x150, array step: 0x70 */
1371 uint8_t RESERVED_5[12];
1372 __I uint32_t CH_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */
1373 uint8_t RESERVED_6[12];
1374 } CH_CFGn[16];
1375 __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */
1376} APBH_Type;
1377
1378/* ----------------------------------------------------------------------------
1379 -- APBH Register Masks
1380 ---------------------------------------------------------------------------- */
1381
1382/*!
1383 * @addtogroup APBH_Register_Masks APBH Register Masks
1384 * @{
1385 */
1386
1387/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */
1388/*! @{ */
1389#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU)
1390#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U)
1391/*! CLKGATE_CHANNEL - CLKGATE_CHANNEL
1392 * 0b0000000000000001..
1393 * 0b0000000000000010..
1394 * 0b0000000000000100..
1395 * 0b0000000000001000..
1396 * 0b0000000000010000..
1397 * 0b0000000000100000..
1398 * 0b0000000001000000..
1399 * 0b0000000010000000..
1400 * 0b0000000100000000..
1401 */
1402#define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK)
1403#define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U)
1404#define APBH_CTRL0_APB_BURST_EN_SHIFT (28U)
1405/*! APB_BURST_EN - APB_BURST_EN
1406 */
1407#define APBH_CTRL0_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK)
1408#define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U)
1409#define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U)
1410/*! AHB_BURST8_EN - AHB_BURST8_EN
1411 */
1412#define APBH_CTRL0_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK)
1413#define APBH_CTRL0_CLKGATE_MASK (0x40000000U)
1414#define APBH_CTRL0_CLKGATE_SHIFT (30U)
1415/*! CLKGATE - CLKGATE
1416 */
1417#define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK)
1418#define APBH_CTRL0_SFTRST_MASK (0x80000000U)
1419#define APBH_CTRL0_SFTRST_SHIFT (31U)
1420/*! SFTRST - SFTRST
1421 */
1422#define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK)
1423/*! @} */
1424
1425/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */
1426/*! @{ */
1427#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1428#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1429/*! CH0_CMDCMPLT_IRQ - CH0_CMDCMPLT_IRQ
1430 */
1431#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK)
1432#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1433#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1434/*! CH1_CMDCMPLT_IRQ - CH1_CMDCMPLT_IRQ
1435 */
1436#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK)
1437#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1438#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1439/*! CH2_CMDCMPLT_IRQ - CH2_CMDCMPLT_IRQ
1440 */
1441#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK)
1442#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1443#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1444/*! CH3_CMDCMPLT_IRQ - CH3_CMDCMPLT_IRQ
1445 */
1446#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK)
1447#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1448#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1449/*! CH4_CMDCMPLT_IRQ - CH4_CMDCMPLT_IRQ
1450 */
1451#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK)
1452#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1453#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1454/*! CH5_CMDCMPLT_IRQ - CH5_CMDCMPLT_IRQ
1455 */
1456#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK)
1457#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1458#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1459/*! CH6_CMDCMPLT_IRQ - CH6_CMDCMPLT_IRQ
1460 */
1461#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK)
1462#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1463#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1464/*! CH7_CMDCMPLT_IRQ - CH7_CMDCMPLT_IRQ
1465 */
1466#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK)
1467#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1468#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1469/*! CH8_CMDCMPLT_IRQ - CH8_CMDCMPLT_IRQ
1470 */
1471#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK)
1472#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1473#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1474/*! CH9_CMDCMPLT_IRQ - CH9_CMDCMPLT_IRQ
1475 */
1476#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK)
1477#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1478#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1479/*! CH10_CMDCMPLT_IRQ - CH10_CMDCMPLT_IRQ
1480 */
1481#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK)
1482#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1483#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1484/*! CH11_CMDCMPLT_IRQ - CH11_CMDCMPLT_IRQ
1485 */
1486#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK)
1487#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1488#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1489/*! CH12_CMDCMPLT_IRQ - CH12_CMDCMPLT_IRQ
1490 */
1491#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK)
1492#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1493#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1494/*! CH13_CMDCMPLT_IRQ - CH13_CMDCMPLT_IRQ
1495 */
1496#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK)
1497#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1498#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1499/*! CH14_CMDCMPLT_IRQ - CH14_CMDCMPLT_IRQ
1500 */
1501#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK)
1502#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1503#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1504/*! CH15_CMDCMPLT_IRQ - CH15_CMDCMPLT_IRQ
1505 */
1506#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK)
1507#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1508#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
1509/*! CH0_CMDCMPLT_IRQ_EN - CH0_CMDCMPLT_IRQ_EN
1510 */
1511#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK)
1512#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
1513#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
1514/*! CH1_CMDCMPLT_IRQ_EN - CH1_CMDCMPLT_IRQ_EN
1515 */
1516#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK)
1517#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
1518#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
1519/*! CH2_CMDCMPLT_IRQ_EN - CH2_CMDCMPLT_IRQ_EN
1520 */
1521#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK)
1522#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
1523#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
1524/*! CH3_CMDCMPLT_IRQ_EN - CH3_CMDCMPLT_IRQ_EN
1525 */
1526#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK)
1527#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
1528#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
1529/*! CH4_CMDCMPLT_IRQ_EN - CH4_CMDCMPLT_IRQ_EN
1530 */
1531#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK)
1532#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
1533#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
1534/*! CH5_CMDCMPLT_IRQ_EN - CH5_CMDCMPLT_IRQ_EN
1535 */
1536#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK)
1537#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
1538#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
1539/*! CH6_CMDCMPLT_IRQ_EN - CH6_CMDCMPLT_IRQ_EN
1540 */
1541#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK)
1542#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
1543#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
1544/*! CH7_CMDCMPLT_IRQ_EN - CH7_CMDCMPLT_IRQ_EN
1545 */
1546#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK)
1547#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
1548#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
1549/*! CH8_CMDCMPLT_IRQ_EN - CH8_CMDCMPLT_IRQ_EN
1550 */
1551#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK)
1552#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
1553#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
1554/*! CH9_CMDCMPLT_IRQ_EN - CH9_CMDCMPLT_IRQ_EN
1555 */
1556#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK)
1557#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
1558#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
1559/*! CH10_CMDCMPLT_IRQ_EN - CH10_CMDCMPLT_IRQ_EN
1560 */
1561#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
1562#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
1563#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
1564/*! CH11_CMDCMPLT_IRQ_EN - CH11_CMDCMPLT_IRQ_EN
1565 */
1566#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK)
1567#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
1568#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
1569/*! CH12_CMDCMPLT_IRQ_EN - CH12_CMDCMPLT_IRQ_EN
1570 */
1571#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK)
1572#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
1573#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
1574/*! CH13_CMDCMPLT_IRQ_EN - CH13_CMDCMPLT_IRQ_EN
1575 */
1576#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK)
1577#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
1578#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
1579/*! CH14_CMDCMPLT_IRQ_EN - CH14_CMDCMPLT_IRQ_EN
1580 */
1581#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK)
1582#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
1583#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
1584/*! CH15_CMDCMPLT_IRQ_EN - CH15_CMDCMPLT_IRQ_EN
1585 */
1586#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK)
1587/*! @} */
1588
1589/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */
1590/*! @{ */
1591#define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U)
1592#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U)
1593/*! CH0_ERROR_IRQ - CH0_ERROR_IRQ
1594 */
1595#define APBH_CTRL2_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK)
1596#define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U)
1597#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U)
1598/*! CH1_ERROR_IRQ - CH1_ERROR_IRQ
1599 */
1600#define APBH_CTRL2_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK)
1601#define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U)
1602#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U)
1603/*! CH2_ERROR_IRQ - CH2_ERROR_IRQ
1604 */
1605#define APBH_CTRL2_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK)
1606#define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U)
1607#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U)
1608/*! CH3_ERROR_IRQ - CH3_ERROR_IRQ
1609 */
1610#define APBH_CTRL2_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK)
1611#define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U)
1612#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U)
1613/*! CH4_ERROR_IRQ - CH4_ERROR_IRQ
1614 */
1615#define APBH_CTRL2_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK)
1616#define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U)
1617#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U)
1618/*! CH5_ERROR_IRQ - CH5_ERROR_IRQ
1619 */
1620#define APBH_CTRL2_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK)
1621#define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U)
1622#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U)
1623/*! CH6_ERROR_IRQ - CH6_ERROR_IRQ
1624 */
1625#define APBH_CTRL2_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK)
1626#define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U)
1627#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U)
1628/*! CH7_ERROR_IRQ - CH7_ERROR_IRQ
1629 */
1630#define APBH_CTRL2_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK)
1631#define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U)
1632#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U)
1633/*! CH8_ERROR_IRQ - CH8_ERROR_IRQ
1634 */
1635#define APBH_CTRL2_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK)
1636#define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U)
1637#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U)
1638/*! CH9_ERROR_IRQ - CH9_ERROR_IRQ
1639 */
1640#define APBH_CTRL2_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK)
1641#define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U)
1642#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U)
1643/*! CH10_ERROR_IRQ - CH10_ERROR_IRQ
1644 */
1645#define APBH_CTRL2_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK)
1646#define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U)
1647#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U)
1648/*! CH11_ERROR_IRQ - CH11_ERROR_IRQ
1649 */
1650#define APBH_CTRL2_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK)
1651#define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U)
1652#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U)
1653/*! CH12_ERROR_IRQ - CH12_ERROR_IRQ
1654 */
1655#define APBH_CTRL2_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK)
1656#define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U)
1657#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U)
1658/*! CH13_ERROR_IRQ - CH13_ERROR_IRQ
1659 */
1660#define APBH_CTRL2_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK)
1661#define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U)
1662#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U)
1663/*! CH14_ERROR_IRQ - CH14_ERROR_IRQ
1664 */
1665#define APBH_CTRL2_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK)
1666#define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U)
1667#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U)
1668/*! CH15_ERROR_IRQ - CH15_ERROR_IRQ
1669 */
1670#define APBH_CTRL2_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK)
1671#define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U)
1672#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U)
1673/*! CH0_ERROR_STATUS - CH0_ERROR_STATUS
1674 * 0b0..An early termination from the device causes error IRQ.
1675 * 0b1..An AHB bus error causes error IRQ.
1676 */
1677#define APBH_CTRL2_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK)
1678#define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U)
1679#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U)
1680/*! CH1_ERROR_STATUS - CH1_ERROR_STATUS
1681 * 0b0..An early termination from the device causes error IRQ.
1682 * 0b1..An AHB bus error causes error IRQ.
1683 */
1684#define APBH_CTRL2_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK)
1685#define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U)
1686#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U)
1687/*! CH2_ERROR_STATUS - CH2_ERROR_STATUS
1688 * 0b0..An early termination from the device causes error IRQ.
1689 * 0b1..An AHB bus error causes error IRQ.
1690 */
1691#define APBH_CTRL2_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK)
1692#define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U)
1693#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U)
1694/*! CH3_ERROR_STATUS - CH3_ERROR_STATUS
1695 * 0b0..An early termination from the device causes error IRQ.
1696 * 0b1..An AHB bus error causes error IRQ.
1697 */
1698#define APBH_CTRL2_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK)
1699#define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U)
1700#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U)
1701/*! CH4_ERROR_STATUS - CH4_ERROR_STATUS
1702 * 0b0..An early termination from the device causes error IRQ.
1703 * 0b1..An AHB bus error causes error IRQ.
1704 */
1705#define APBH_CTRL2_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK)
1706#define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U)
1707#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U)
1708/*! CH5_ERROR_STATUS - CH5_ERROR_STATUS
1709 * 0b0..An early termination from the device causes error IRQ.
1710 * 0b1..An AHB bus error causes error IRQ.
1711 */
1712#define APBH_CTRL2_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK)
1713#define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U)
1714#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U)
1715/*! CH6_ERROR_STATUS - CH6_ERROR_STATUS
1716 * 0b0..An early termination from the device causes error IRQ.
1717 * 0b1..An AHB bus error causes error IRQ.
1718 */
1719#define APBH_CTRL2_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK)
1720#define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U)
1721#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U)
1722/*! CH7_ERROR_STATUS - CH7_ERROR_STATUS
1723 * 0b0..An early termination from the device causes error IRQ.
1724 * 0b1..An AHB bus error causes error IRQ.
1725 */
1726#define APBH_CTRL2_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK)
1727#define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U)
1728#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U)
1729/*! CH8_ERROR_STATUS - CH8_ERROR_STATUS
1730 * 0b0..An early termination from the device causes error IRQ.
1731 * 0b1..An AHB bus error causes error IRQ.
1732 */
1733#define APBH_CTRL2_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK)
1734#define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U)
1735#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U)
1736/*! CH9_ERROR_STATUS - CH9_ERROR_STATUS
1737 * 0b0..An early termination from the device causes error IRQ.
1738 * 0b1..An AHB bus error causes error IRQ.
1739 */
1740#define APBH_CTRL2_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK)
1741#define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U)
1742#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U)
1743/*! CH10_ERROR_STATUS - CH10_ERROR_STATUS
1744 * 0b0..An early termination from the device causes error IRQ.
1745 * 0b1..An AHB bus error causes error IRQ.
1746 */
1747#define APBH_CTRL2_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK)
1748#define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U)
1749#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U)
1750/*! CH11_ERROR_STATUS - CH11_ERROR_STATUS
1751 * 0b0..An early termination from the device causes error IRQ.
1752 * 0b1..An AHB bus error causes error IRQ.
1753 */
1754#define APBH_CTRL2_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK)
1755#define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U)
1756#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U)
1757/*! CH12_ERROR_STATUS - CH12_ERROR_STATUS
1758 * 0b0..An early termination from the device causes error IRQ.
1759 * 0b1..An AHB bus error causes error IRQ.
1760 */
1761#define APBH_CTRL2_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK)
1762#define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U)
1763#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U)
1764/*! CH13_ERROR_STATUS - CH13_ERROR_STATUS
1765 * 0b0..An early termination from the device causes error IRQ.
1766 * 0b1..An AHB bus error causes error IRQ.
1767 */
1768#define APBH_CTRL2_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK)
1769#define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U)
1770#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U)
1771/*! CH14_ERROR_STATUS - CH14_ERROR_STATUS
1772 * 0b0..An early termination from the device causes error IRQ.
1773 * 0b1..An AHB bus error causes error IRQ.
1774 */
1775#define APBH_CTRL2_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK)
1776#define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U)
1777#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U)
1778/*! CH15_ERROR_STATUS - CH15_ERROR_STATUS
1779 * 0b0..An early termination from the device causes error IRQ.
1780 * 0b1..An AHB bus error causes error IRQ.
1781 */
1782#define APBH_CTRL2_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK)
1783/*! @} */
1784
1785/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */
1786/*! @{ */
1787#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU)
1788#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U)
1789/*! FREEZE_CHANNEL - FREEZE_CHANNEL
1790 * 0b0000000000000001..
1791 * 0b0000000000000010..
1792 * 0b0000000000000100..
1793 * 0b0000000000001000..
1794 * 0b0000000000010000..
1795 * 0b0000000000100000..
1796 * 0b0000000001000000..
1797 * 0b0000000010000000..
1798 * 0b0000000100000000..
1799 */
1800#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK)
1801#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U)
1802#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U)
1803/*! RESET_CHANNEL - RESET_CHANNEL
1804 * 0b0000000000000001..
1805 * 0b0000000000000010..
1806 * 0b0000000000000100..
1807 * 0b0000000000001000..
1808 * 0b0000000000010000..
1809 * 0b0000000000100000..
1810 * 0b0000000001000000..
1811 * 0b0000000010000000..
1812 * 0b0000000100000000..
1813 */
1814#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK)
1815/*! @} */
1816
1817/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */
1818/*! @{ */
1819#define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U)
1820#define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U)
1821/*! CH0 - CH0
1822 */
1823#define APBH_DMA_BURST_SIZE_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK)
1824#define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU)
1825#define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U)
1826/*! CH1 - CH1
1827 */
1828#define APBH_DMA_BURST_SIZE_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK)
1829#define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U)
1830#define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U)
1831/*! CH2 - CH2
1832 */
1833#define APBH_DMA_BURST_SIZE_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK)
1834#define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U)
1835#define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U)
1836/*! CH3 - CH3
1837 */
1838#define APBH_DMA_BURST_SIZE_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK)
1839#define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U)
1840#define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U)
1841/*! CH4 - CH4
1842 */
1843#define APBH_DMA_BURST_SIZE_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK)
1844#define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U)
1845#define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U)
1846/*! CH5 - CH5
1847 */
1848#define APBH_DMA_BURST_SIZE_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK)
1849#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U)
1850#define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U)
1851/*! CH6 - CH6
1852 */
1853#define APBH_DMA_BURST_SIZE_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK)
1854#define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U)
1855#define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U)
1856/*! CH7 - CH7
1857 */
1858#define APBH_DMA_BURST_SIZE_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK)
1859#define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U)
1860#define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U)
1861/*! CH8 - CH8
1862 * 0b00..
1863 * 0b01..
1864 * 0b10..
1865 */
1866#define APBH_DMA_BURST_SIZE_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK)
1867/*! @} */
1868
1869/*! @name DEBUG - AHB to APBH DMA Debug Register */
1870/*! @{ */
1871#define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U)
1872#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U)
1873/*! GPMI_ONE_FIFO - GPMI_ONE_FIFO
1874 */
1875#define APBH_DEBUG_GPMI_ONE_FIFO(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK)
1876/*! @} */
1877
1878/*! @name CH_CURCMDAR - APBH DMA Channel n Current Command Address Register */
1879/*! @{ */
1880#define APBH_CH_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
1881#define APBH_CH_CURCMDAR_CMD_ADDR_SHIFT (0U)
1882/*! CMD_ADDR - CMD_ADDR
1883 */
1884#define APBH_CH_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_CURCMDAR_CMD_ADDR_MASK)
1885/*! @} */
1886
1887/* The count of APBH_CH_CURCMDAR */
1888#define APBH_CH_CURCMDAR_COUNT (16U)
1889
1890/*! @name CH_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
1891/*! @{ */
1892#define APBH_CH_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
1893#define APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT (0U)
1894/*! CMD_ADDR - CMD_ADDR
1895 */
1896#define APBH_CH_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_NXTCMDAR_CMD_ADDR_MASK)
1897/*! @} */
1898
1899/* The count of APBH_CH_NXTCMDAR */
1900#define APBH_CH_NXTCMDAR_COUNT (16U)
1901
1902/*! @name CH_CMD - APBH DMA Channel n Command Register */
1903/*! @{ */
1904#define APBH_CH_CMD_COMMAND_MASK (0x3U)
1905#define APBH_CH_CMD_COMMAND_SHIFT (0U)
1906/*! COMMAND - COMMAND
1907 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
1908 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
1909 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
1910 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained
1911 * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain
1912 * pointer if the peripheral sense line is false.
1913 */
1914#define APBH_CH_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_COMMAND_SHIFT)) & APBH_CH_CMD_COMMAND_MASK)
1915#define APBH_CH_CMD_CHAIN_MASK (0x4U)
1916#define APBH_CH_CMD_CHAIN_SHIFT (2U)
1917/*! CHAIN - CHAIN
1918 */
1919#define APBH_CH_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CHAIN_SHIFT)) & APBH_CH_CMD_CHAIN_MASK)
1920#define APBH_CH_CMD_IRQONCMPLT_MASK (0x8U)
1921#define APBH_CH_CMD_IRQONCMPLT_SHIFT (3U)
1922/*! IRQONCMPLT - IRQONCMPLT
1923 */
1924#define APBH_CH_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_IRQONCMPLT_SHIFT)) & APBH_CH_CMD_IRQONCMPLT_MASK)
1925#define APBH_CH_CMD_NANDLOCK_MASK (0x10U)
1926#define APBH_CH_CMD_NANDLOCK_SHIFT (4U)
1927/*! NANDLOCK - NANDLOCK
1928 */
1929#define APBH_CH_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDLOCK_SHIFT)) & APBH_CH_CMD_NANDLOCK_MASK)
1930#define APBH_CH_CMD_NANDWAIT4READY_MASK (0x20U)
1931#define APBH_CH_CMD_NANDWAIT4READY_SHIFT (5U)
1932/*! NANDWAIT4READY - NANDWAIT4READY
1933 */
1934#define APBH_CH_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH_CMD_NANDWAIT4READY_MASK)
1935#define APBH_CH_CMD_SEMAPHORE_MASK (0x40U)
1936#define APBH_CH_CMD_SEMAPHORE_SHIFT (6U)
1937/*! SEMAPHORE - SEMAPHORE
1938 */
1939#define APBH_CH_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_SEMAPHORE_SHIFT)) & APBH_CH_CMD_SEMAPHORE_MASK)
1940#define APBH_CH_CMD_WAIT4ENDCMD_MASK (0x80U)
1941#define APBH_CH_CMD_WAIT4ENDCMD_SHIFT (7U)
1942/*! WAIT4ENDCMD - WAIT4ENDCMD
1943 */
1944#define APBH_CH_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH_CMD_WAIT4ENDCMD_MASK)
1945#define APBH_CH_CMD_HALTONTERMINATE_MASK (0x100U)
1946#define APBH_CH_CMD_HALTONTERMINATE_SHIFT (8U)
1947/*! HALTONTERMINATE - HALTONTERMINATE
1948 */
1949#define APBH_CH_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH_CMD_HALTONTERMINATE_MASK)
1950#define APBH_CH_CMD_CMDWORDS_MASK (0xF000U)
1951#define APBH_CH_CMD_CMDWORDS_SHIFT (12U)
1952/*! CMDWORDS - CMDWORDS
1953 */
1954#define APBH_CH_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CMDWORDS_SHIFT)) & APBH_CH_CMD_CMDWORDS_MASK)
1955#define APBH_CH_CMD_XFER_COUNT_MASK (0xFFFF0000U)
1956#define APBH_CH_CMD_XFER_COUNT_SHIFT (16U)
1957/*! XFER_COUNT - XFER_COUNT
1958 */
1959#define APBH_CH_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_XFER_COUNT_SHIFT)) & APBH_CH_CMD_XFER_COUNT_MASK)
1960/*! @} */
1961
1962/* The count of APBH_CH_CMD */
1963#define APBH_CH_CMD_COUNT (16U)
1964
1965/*! @name CH_BAR - APBH DMA Channel n Buffer Address Register */
1966/*! @{ */
1967#define APBH_CH_BAR_ADDRESS_MASK (0xFFFFFFFFU)
1968#define APBH_CH_BAR_ADDRESS_SHIFT (0U)
1969/*! ADDRESS - ADDRESS
1970 */
1971#define APBH_CH_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_BAR_ADDRESS_SHIFT)) & APBH_CH_BAR_ADDRESS_MASK)
1972/*! @} */
1973
1974/* The count of APBH_CH_BAR */
1975#define APBH_CH_BAR_COUNT (16U)
1976
1977/*! @name CH_SEMA - APBH DMA Channel n Semaphore Register */
1978/*! @{ */
1979#define APBH_CH_SEMA_INCREMENT_SEMA_MASK (0xFFU)
1980#define APBH_CH_SEMA_INCREMENT_SEMA_SHIFT (0U)
1981/*! INCREMENT_SEMA - INCREMENT_SEMA
1982 */
1983#define APBH_CH_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH_SEMA_INCREMENT_SEMA_MASK)
1984#define APBH_CH_SEMA_PHORE_MASK (0xFF0000U)
1985#define APBH_CH_SEMA_PHORE_SHIFT (16U)
1986/*! PHORE - PHORE
1987 */
1988#define APBH_CH_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_PHORE_SHIFT)) & APBH_CH_SEMA_PHORE_MASK)
1989/*! @} */
1990
1991/* The count of APBH_CH_SEMA */
1992#define APBH_CH_SEMA_COUNT (16U)
1993
1994/*! @name CH_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
1995/*! @{ */
1996#define APBH_CH_DEBUG1_STATEMACHINE_MASK (0x1FU)
1997#define APBH_CH_DEBUG1_STATEMACHINE_SHIFT (0U)
1998/*! STATEMACHINE - STATEMACHINE
1999 * 0b00000..This is the idle state of the DMA state machine.
2000 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
2001 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
2002 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
2003 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
2004 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
2005 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the
2006 * PIO words when PIO count is greater than 1.
2007 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
2008 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
2009 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
2010 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
2011 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
2012 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
2013 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
2014 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
2015 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
2016 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
2017 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and
2018 * effectively halts. A channel reset is required to exit this state
2019 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
2020 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device
2021 * indicates that the external device is ready.
2022 */
2023#define APBH_CH_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH_DEBUG1_STATEMACHINE_MASK)
2024#define APBH_CH_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
2025#define APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
2026/*! WR_FIFO_FULL - WR_FIFO_FULL
2027 */
2028#define APBH_CH_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_FULL_MASK)
2029#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
2030#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
2031/*! WR_FIFO_EMPTY - WR_FIFO_EMPTY
2032 */
2033#define APBH_CH_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK)
2034#define APBH_CH_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
2035#define APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
2036/*! RD_FIFO_FULL - RD_FIFO_FULL
2037 */
2038#define APBH_CH_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_FULL_MASK)
2039#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
2040#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
2041/*! RD_FIFO_EMPTY - RD_FIFO_EMPTY
2042 */
2043#define APBH_CH_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK)
2044#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
2045#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
2046/*! NEXTCMDADDRVALID - NEXTCMDADDRVALID
2047 */
2048#define APBH_CH_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK)
2049#define APBH_CH_DEBUG1_READY_MASK (0x4000000U)
2050#define APBH_CH_DEBUG1_READY_SHIFT (26U)
2051/*! READY - READY
2052 */
2053#define APBH_CH_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_READY_SHIFT)) & APBH_CH_DEBUG1_READY_MASK)
2054#define APBH_CH_DEBUG1_END_MASK (0x10000000U)
2055#define APBH_CH_DEBUG1_END_SHIFT (28U)
2056/*! END - END
2057 */
2058#define APBH_CH_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_END_SHIFT)) & APBH_CH_DEBUG1_END_MASK)
2059#define APBH_CH_DEBUG1_KICK_MASK (0x20000000U)
2060#define APBH_CH_DEBUG1_KICK_SHIFT (29U)
2061/*! KICK - KICK
2062 */
2063#define APBH_CH_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_KICK_SHIFT)) & APBH_CH_DEBUG1_KICK_MASK)
2064#define APBH_CH_DEBUG1_BURST_MASK (0x40000000U)
2065#define APBH_CH_DEBUG1_BURST_SHIFT (30U)
2066/*! BURST - BURST
2067 */
2068#define APBH_CH_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_BURST_SHIFT)) & APBH_CH_DEBUG1_BURST_MASK)
2069#define APBH_CH_DEBUG1_REQ_MASK (0x80000000U)
2070#define APBH_CH_DEBUG1_REQ_SHIFT (31U)
2071/*! REQ - REQ
2072 */
2073#define APBH_CH_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_REQ_SHIFT)) & APBH_CH_DEBUG1_REQ_MASK)
2074/*! @} */
2075
2076/* The count of APBH_CH_DEBUG1 */
2077#define APBH_CH_DEBUG1_COUNT (16U)
2078
2079/*! @name CH_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
2080/*! @{ */
2081#define APBH_CH_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
2082#define APBH_CH_DEBUG2_AHB_BYTES_SHIFT (0U)
2083/*! AHB_BYTES - AHB_BYTES
2084 */
2085#define APBH_CH_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH_DEBUG2_AHB_BYTES_MASK)
2086#define APBH_CH_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
2087#define APBH_CH_DEBUG2_APB_BYTES_SHIFT (16U)
2088/*! APB_BYTES - APB_BYTES
2089 */
2090#define APBH_CH_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH_DEBUG2_APB_BYTES_MASK)
2091/*! @} */
2092
2093/* The count of APBH_CH_DEBUG2 */
2094#define APBH_CH_DEBUG2_COUNT (16U)
2095
2096/*! @name VERSION - APBH Bridge Version Register */
2097/*! @{ */
2098#define APBH_VERSION_STEP_MASK (0xFFFFU)
2099#define APBH_VERSION_STEP_SHIFT (0U)
2100/*! STEP - STEP
2101 */
2102#define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK)
2103#define APBH_VERSION_MINOR_MASK (0xFF0000U)
2104#define APBH_VERSION_MINOR_SHIFT (16U)
2105/*! MINOR - MINOR
2106 */
2107#define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK)
2108#define APBH_VERSION_MAJOR_MASK (0xFF000000U)
2109#define APBH_VERSION_MAJOR_SHIFT (24U)
2110/*! MAJOR - MAJOR
2111 */
2112#define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK)
2113/*! @} */
2114
2115
2116/*!
2117 * @}
2118 */ /* end of group APBH_Register_Masks */
2119
2120
2121/* APBH - Peripheral instance base addresses */
2122/** Peripheral CONNECTIVITY__APBH base address */
2123#define CONNECTIVITY__APBH_BASE (0x5B810000u)
2124/** Peripheral CONNECTIVITY__APBH base pointer */
2125#define CONNECTIVITY__APBH ((APBH_Type *)CONNECTIVITY__APBH_BASE)
2126/** Array initializer of APBH peripheral base addresses */
2127#define APBH_BASE_ADDRS { CONNECTIVITY__APBH_BASE }
2128/** Array initializer of APBH peripheral base pointers */
2129#define APBH_BASE_PTRS { CONNECTIVITY__APBH }
2130/** Interrupt vectors for the APBH peripheral type */
2131#define APBH_IRQS { CONNECTIVITY_APBHDMA_IRQn }
2132
2133/*!
2134 * @}
2135 */ /* end of group APBH_Peripheral_Access_Layer */
2136
2137
2138/* ----------------------------------------------------------------------------
2139 -- ASMC Peripheral Access Layer
2140 ---------------------------------------------------------------------------- */
2141
2142/*!
2143 * @addtogroup ASMC_Peripheral_Access_Layer ASMC Peripheral Access Layer
2144 * @{
2145 */
2146
2147/** ASMC - Register Layout Typedef */
2148typedef struct {
2149 __I uint32_t SRS; /**< System Reset Status Register, offset: 0x0 */
2150 uint8_t RESERVED_0[4];
2151 __IO uint32_t PMPROT; /**< Power Mode Protection register, offset: 0x8 */
2152 __IO uint32_t PMCTRL; /**< Power Mode Control register, offset: 0xC */
2153 __IO uint32_t STOPCTRL; /**< Stop Control Register, offset: 0x10 */
2154 __I uint32_t PMSTAT; /**< Power Mode Status register, offset: 0x14 */
2155} ASMC_Type;
2156
2157/* ----------------------------------------------------------------------------
2158 -- ASMC Register Masks
2159 ---------------------------------------------------------------------------- */
2160
2161/*!
2162 * @addtogroup ASMC_Register_Masks ASMC Register Masks
2163 * @{
2164 */
2165
2166/*! @name SRS - System Reset Status Register */
2167/*! @{ */
2168#define ASMC_SRS_WAKEUP_MASK (0x1U)
2169#define ASMC_SRS_WAKEUP_SHIFT (0U)
2170/*! WAKEUP - Low Leakage Wakeup Reset
2171 * 0b0..Reset not caused by LLWU module wakeup source
2172 * 0b1..Reset caused by LLWU module wakeup source
2173 */
2174#define ASMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WAKEUP_SHIFT)) & ASMC_SRS_WAKEUP_MASK)
2175#define ASMC_SRS_WDOG1_MASK (0x20U)
2176#define ASMC_SRS_WDOG1_SHIFT (5U)
2177/*! WDOG1 - Watchdog
2178 * 0b0..Reset not caused by watchdog timeout
2179 * 0b1..Reset caused by watchdog timeout
2180 */
2181#define ASMC_SRS_WDOG1(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WDOG1_SHIFT)) & ASMC_SRS_WDOG1_MASK)
2182#define ASMC_SRS_RES_MASK (0x40U)
2183#define ASMC_SRS_RES_SHIFT (6U)
2184/*! RES - Chip Reset not POR
2185 * 0b0..Chip Reset did not occur
2186 * 0b1..Chip Reset caused by a source other than POR occured
2187 */
2188#define ASMC_SRS_RES(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_RES_SHIFT)) & ASMC_SRS_RES_MASK)
2189#define ASMC_SRS_POR_MASK (0x80U)
2190#define ASMC_SRS_POR_SHIFT (7U)
2191/*! POR - Power-On Reset
2192 * 0b0..Reset not caused by POR
2193 * 0b1..Reset caused by POR
2194 */
2195#define ASMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_POR_SHIFT)) & ASMC_SRS_POR_MASK)
2196#define ASMC_SRS_LOCKUP_MASK (0x200U)
2197#define ASMC_SRS_LOCKUP_SHIFT (9U)
2198/*! LOCKUP - Core 1 Lockup
2199 * 0b0..Reset not caused by core LOCKUP event
2200 * 0b1..Reset caused by core LOCKUP event
2201 */
2202#define ASMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_LOCKUP_SHIFT)) & ASMC_SRS_LOCKUP_MASK)
2203#define ASMC_SRS_SW_MASK (0x400U)
2204#define ASMC_SRS_SW_SHIFT (10U)
2205/*! SW - Software
2206 * 0b0..Reset not caused by software setting of SYSRESETREQ bit
2207 * 0b1..Reset caused by software setting of SYSRESETREQ bit
2208 */
2209#define ASMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SW_SHIFT)) & ASMC_SRS_SW_MASK)
2210#define ASMC_SRS_SACKERR_MASK (0x1000U)
2211#define ASMC_SRS_SACKERR_SHIFT (12U)
2212/*! SACKERR - Stop Mode Acknowledge Error Reset
2213 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
2214 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
2215 */
2216#define ASMC_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SACKERR_SHIFT)) & ASMC_SRS_SACKERR_MASK)
2217/*! @} */
2218
2219/*! @name PMPROT - Power Mode Protection register */
2220/*! @{ */
2221#define ASMC_PMPROT_AVLLS_MASK (0x2U)
2222#define ASMC_PMPROT_AVLLS_SHIFT (1U)
2223/*! AVLLS - Allow Very-Low-Leakage Stop Mode
2224 * 0b0..Not Allowed
2225 * 0b1..Allowed
2226 */
2227#define ASMC_PMPROT_AVLLS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLLS_SHIFT)) & ASMC_PMPROT_AVLLS_MASK)
2228#define ASMC_PMPROT_ALLS_MASK (0x8U)
2229#define ASMC_PMPROT_ALLS_SHIFT (3U)
2230/*! ALLS - Allow Low-Leakage Stop Mode
2231 * 0b0..Not Allowed
2232 * 0b1..Allowed
2233 */
2234#define ASMC_PMPROT_ALLS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_ALLS_SHIFT)) & ASMC_PMPROT_ALLS_MASK)
2235#define ASMC_PMPROT_AVLP_MASK (0x20U)
2236#define ASMC_PMPROT_AVLP_SHIFT (5U)
2237/*! AVLP - Allow Very-Low-Power Modes
2238 * 0b0..VLPR, VLPW, and VLPS are not allowed.
2239 * 0b1..VLPR, VLPW, and VLPS are allowed.
2240 */
2241#define ASMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLP_SHIFT)) & ASMC_PMPROT_AVLP_MASK)
2242#define ASMC_PMPROT_AHSRUN_MASK (0x80U)
2243#define ASMC_PMPROT_AHSRUN_SHIFT (7U)
2244/*! AHSRUN - Allow High Speed Run mode
2245 * 0b0..HSRUN is not allowed
2246 * 0b1..HSRUN is allowed
2247 */
2248#define ASMC_PMPROT_AHSRUN(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AHSRUN_SHIFT)) & ASMC_PMPROT_AHSRUN_MASK)
2249/*! @} */
2250
2251/*! @name PMCTRL - Power Mode Control register */
2252/*! @{ */
2253#define ASMC_PMCTRL_STOPM_MASK (0x7U)
2254#define ASMC_PMCTRL_STOPM_SHIFT (0U)
2255/*! STOPM - Stop Mode Control
2256 * 0b000..Normal Stop (STOP)
2257 * 0b001..Reserved
2258 * 0b010..Very-Low-Power Stop (VLPS)
2259 * 0b011..Low-leakage stop
2260 * 0b100..Very-low-leakage stop
2261 * 0b101..Reserved
2262 * 0b110..Reseved
2263 * 0b111..Reserved
2264 */
2265#define ASMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_STOPM_SHIFT)) & ASMC_PMCTRL_STOPM_MASK)
2266#define ASMC_PMCTRL_RUNM_MASK (0x60U)
2267#define ASMC_PMCTRL_RUNM_SHIFT (5U)
2268/*! RUNM - Run Mode Control
2269 * 0b00..Normal Run mode (RUN)
2270 * 0b01..Reserved
2271 * 0b10..Very-Low-Power Run mode (VLPR)
2272 * 0b11..High Speed Run mode (HSRUN)
2273 */
2274#define ASMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_RUNM_SHIFT)) & ASMC_PMCTRL_RUNM_MASK)
2275/*! @} */
2276
2277/*! @name STOPCTRL - Stop Control Register */
2278/*! @{ */
2279#define ASMC_STOPCTRL_PSTOPO_MASK (0xC0U)
2280#define ASMC_STOPCTRL_PSTOPO_SHIFT (6U)
2281/*! PSTOPO - Partial Stop Option
2282 * 0b00..STOP - Normal Stop mode
2283 * 0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled
2284 * 0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
2285 * 0b11..Reserved
2286 */
2287#define ASMC_STOPCTRL_PSTOPO(x) (((uint32_t)(((uint32_t)(x)) << ASMC_STOPCTRL_PSTOPO_SHIFT)) & ASMC_STOPCTRL_PSTOPO_MASK)
2288/*! @} */
2289
2290/*! @name PMSTAT - Power Mode Status register */
2291/*! @{ */
2292#define ASMC_PMSTAT_PMSTAT_MASK (0xFFU) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */
2293#define ASMC_PMSTAT_PMSTAT_SHIFT (0U)
2294/*! PMSTAT - Power Mode Status
2295 * 0b00000001..Current power mode is RUN.
2296 * 0b00000010..Current power mode is STOP.
2297 * 0b00000100..Current power mode is VLPR.
2298 * 0b00001000..Current power mode is VLPW.
2299 * 0b00010000..Current power mode is VLPS.
2300 * 0b00100000..Current power mode is LLS.
2301 * 0b01000000..Current power mode is VLLS.
2302 * 0b10000000..Current power mode is HSRUN
2303 */
2304#define ASMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMSTAT_PMSTAT_SHIFT)) & ASMC_PMSTAT_PMSTAT_MASK) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */
2305/*! @} */
2306
2307
2308/*!
2309 * @}
2310 */ /* end of group ASMC_Register_Masks */
2311
2312
2313/* ASMC - Peripheral instance base addresses */
2314/** Peripheral CM4__ASMC base address */
2315#define CM4__ASMC_BASE (0x41410000u)
2316/** Peripheral CM4__ASMC base pointer */
2317#define CM4__ASMC ((ASMC_Type *)CM4__ASMC_BASE)
2318/** Peripheral SCU__ASMC base address */
2319#define SCU__ASMC_BASE (0x33410000u)
2320/** Peripheral SCU__ASMC base pointer */
2321#define SCU__ASMC ((ASMC_Type *)SCU__ASMC_BASE)
2322/** Array initializer of ASMC peripheral base addresses */
2323#define ASMC_BASE_ADDRS { CM4__ASMC_BASE, SCU__ASMC_BASE }
2324/** Array initializer of ASMC peripheral base pointers */
2325#define ASMC_BASE_PTRS { CM4__ASMC, SCU__ASMC }
2326
2327/*!
2328 * @}
2329 */ /* end of group ASMC_Peripheral_Access_Layer */
2330
2331
2332/* ----------------------------------------------------------------------------
2333 -- ASRC Peripheral Access Layer
2334 ---------------------------------------------------------------------------- */
2335
2336/*!
2337 * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
2338 * @{
2339 */
2340
2341/** ASRC - Register Layout Typedef */
2342typedef struct {
2343 __IO uint32_t ASRCTR; /**< ASRC Control Register, offset: 0x0 */
2344 __IO uint32_t ASRIER; /**< ASRC Interrupt Enable Register, offset: 0x4 */
2345 uint8_t RESERVED_0[4];
2346 __IO uint32_t ASRCNCR; /**< ASRC Channel Number Configuration Register, offset: 0xC */
2347 __IO uint32_t ASRCFG; /**< ASRC Filter Configuration Status Register, offset: 0x10 */
2348 __IO uint32_t ASRCSR; /**< ASRC Clock Source Register, offset: 0x14 */
2349 __IO uint32_t ASRCDR1; /**< ASRC Clock Divider Register 1, offset: 0x18 */
2350 __IO uint32_t ASRCDR2; /**< ASRC Clock Divider Register 2, offset: 0x1C */
2351 __I uint32_t ASRSTR; /**< ASRC Status Register, offset: 0x20 */
2352 uint8_t RESERVED_1[28];
2353 __IO uint32_t ASRPM[5]; /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */
2354 __IO uint32_t ASRTFR1; /**< ASRC ASRC Task Queue FIFO Register 1, offset: 0x54 */
2355 uint8_t RESERVED_2[4];
2356 __IO uint32_t ASRCCR; /**< ASRC Channel Counter Register, offset: 0x5C */
2357 __O uint32_t ASRDIA; /**< ASRC Data Input Register for Pair x, offset: 0x60 */
2358 __I uint32_t ASRDOA; /**< ASRC Data Output Register for Pair x, offset: 0x64 */
2359 __O uint32_t ASRDIB; /**< ASRC Data Input Register for Pair x, offset: 0x68 */
2360 __I uint32_t ASRDOB; /**< ASRC Data Output Register for Pair x, offset: 0x6C */
2361 __O uint32_t ASRDIC; /**< ASRC Data Input Register for Pair x, offset: 0x70 */
2362 __I uint32_t ASRDOC; /**< ASRC Data Output Register for Pair x, offset: 0x74 */
2363 uint8_t RESERVED_3[8];
2364 __IO uint32_t ASRIDRHA; /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */
2365 __IO uint32_t ASRIDRLA; /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */
2366 __IO uint32_t ASRIDRHB; /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */
2367 __IO uint32_t ASRIDRLB; /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */
2368 __IO uint32_t ASRIDRHC; /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */
2369 __IO uint32_t ASRIDRLC; /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */
2370 __IO uint32_t ASR76K; /**< ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98 */
2371 __IO uint32_t ASR56K; /**< ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C */
2372 __IO uint32_t ASRMCRA; /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */
2373 __I uint32_t ASRFSTA; /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */
2374 __IO uint32_t ASRMCRB; /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */
2375 __I uint32_t ASRFSTB; /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */
2376 __IO uint32_t ASRMCRC; /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */
2377 __I uint32_t ASRFSTC; /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */
2378 uint8_t RESERVED_4[8];
2379 __IO uint32_t ASRMCR1[3]; /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */
2380} ASRC_Type;
2381
2382/* ----------------------------------------------------------------------------
2383 -- ASRC Register Masks
2384 ---------------------------------------------------------------------------- */
2385
2386/*!
2387 * @addtogroup ASRC_Register_Masks ASRC Register Masks
2388 * @{
2389 */
2390
2391/*! @name ASRCTR - ASRC Control Register */
2392/*! @{ */
2393#define ASRC_ASRCTR_ASRCEN_MASK (0x1U)
2394#define ASRC_ASRCTR_ASRCEN_SHIFT (0U)
2395/*! ASRCEN - ASRCEN
2396 */
2397#define ASRC_ASRCTR_ASRCEN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK)
2398#define ASRC_ASRCTR_ASREA_MASK (0x2U)
2399#define ASRC_ASRCTR_ASREA_SHIFT (1U)
2400/*! ASREA - ASREA
2401 */
2402#define ASRC_ASRCTR_ASREA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK)
2403#define ASRC_ASRCTR_ASREB_MASK (0x4U)
2404#define ASRC_ASRCTR_ASREB_SHIFT (2U)
2405/*! ASREB - ASREB
2406 */
2407#define ASRC_ASRCTR_ASREB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK)
2408#define ASRC_ASRCTR_ASREC_MASK (0x8U)
2409#define ASRC_ASRCTR_ASREC_SHIFT (3U)
2410/*! ASREC - ASREC
2411 */
2412#define ASRC_ASRCTR_ASREC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK)
2413#define ASRC_ASRCTR_SRST_MASK (0x10U)
2414#define ASRC_ASRCTR_SRST_SHIFT (4U)
2415/*! SRST - SRST
2416 */
2417#define ASRC_ASRCTR_SRST(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK)
2418#define ASRC_ASRCTR_IDRA_MASK (0x2000U)
2419#define ASRC_ASRCTR_IDRA_SHIFT (13U)
2420/*! IDRA - IDRA
2421 */
2422#define ASRC_ASRCTR_IDRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK)
2423#define ASRC_ASRCTR_USRA_MASK (0x4000U)
2424#define ASRC_ASRCTR_USRA_SHIFT (14U)
2425/*! USRA - USRA
2426 */
2427#define ASRC_ASRCTR_USRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK)
2428#define ASRC_ASRCTR_IDRB_MASK (0x8000U)
2429#define ASRC_ASRCTR_IDRB_SHIFT (15U)
2430/*! IDRB - IDRB
2431 */
2432#define ASRC_ASRCTR_IDRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK)
2433#define ASRC_ASRCTR_USRB_MASK (0x10000U)
2434#define ASRC_ASRCTR_USRB_SHIFT (16U)
2435/*! USRB - USRB
2436 */
2437#define ASRC_ASRCTR_USRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK)
2438#define ASRC_ASRCTR_IDRC_MASK (0x20000U)
2439#define ASRC_ASRCTR_IDRC_SHIFT (17U)
2440/*! IDRC - IDRC
2441 */
2442#define ASRC_ASRCTR_IDRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK)
2443#define ASRC_ASRCTR_USRC_MASK (0x40000U)
2444#define ASRC_ASRCTR_USRC_SHIFT (18U)
2445/*! USRC - USRC
2446 */
2447#define ASRC_ASRCTR_USRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK)
2448#define ASRC_ASRCTR_ATSA_MASK (0x100000U)
2449#define ASRC_ASRCTR_ATSA_SHIFT (20U)
2450/*! ATSA - ATSA
2451 */
2452#define ASRC_ASRCTR_ATSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK)
2453#define ASRC_ASRCTR_ATSB_MASK (0x200000U)
2454#define ASRC_ASRCTR_ATSB_SHIFT (21U)
2455/*! ATSB - ATSB
2456 */
2457#define ASRC_ASRCTR_ATSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK)
2458#define ASRC_ASRCTR_ATSC_MASK (0x400000U)
2459#define ASRC_ASRCTR_ATSC_SHIFT (22U)
2460/*! ATSC - ATSC
2461 */
2462#define ASRC_ASRCTR_ATSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK)
2463/*! @} */
2464
2465/*! @name ASRIER - ASRC Interrupt Enable Register */
2466/*! @{ */
2467#define ASRC_ASRIER_ADIEA_MASK (0x1U)
2468#define ASRC_ASRIER_ADIEA_SHIFT (0U)
2469/*! ADIEA - ADIEA
2470 * 0b1..interrupt enabled
2471 * 0b0..interrupt disabled
2472 */
2473#define ASRC_ASRIER_ADIEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK)
2474#define ASRC_ASRIER_ADIEB_MASK (0x2U)
2475#define ASRC_ASRIER_ADIEB_SHIFT (1U)
2476/*! ADIEB - ADIEB
2477 * 0b1..interrupt enabled
2478 * 0b0..interrupt disabled
2479 */
2480#define ASRC_ASRIER_ADIEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK)
2481#define ASRC_ASRIER_ADIEC_MASK (0x4U)
2482#define ASRC_ASRIER_ADIEC_SHIFT (2U)
2483/*! ADIEC - ADIEC
2484 * 0b1..interrupt enabled
2485 * 0b0..interrupt disabled
2486 */
2487#define ASRC_ASRIER_ADIEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK)
2488#define ASRC_ASRIER_ADOEA_MASK (0x8U)
2489#define ASRC_ASRIER_ADOEA_SHIFT (3U)
2490/*! ADOEA - ADOEA
2491 * 0b1..interrupt enabled
2492 * 0b0..interrupt disabled
2493 */
2494#define ASRC_ASRIER_ADOEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK)
2495#define ASRC_ASRIER_ADOEB_MASK (0x10U)
2496#define ASRC_ASRIER_ADOEB_SHIFT (4U)
2497/*! ADOEB - ADOEB
2498 * 0b1..interrupt enabled
2499 * 0b0..interrupt disabled
2500 */
2501#define ASRC_ASRIER_ADOEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK)
2502#define ASRC_ASRIER_ADOEC_MASK (0x20U)
2503#define ASRC_ASRIER_ADOEC_SHIFT (5U)
2504/*! ADOEC - ADOEC
2505 * 0b1..interrupt enabled
2506 * 0b0..interrupt disabled
2507 */
2508#define ASRC_ASRIER_ADOEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK)
2509#define ASRC_ASRIER_AOLIE_MASK (0x40U)
2510#define ASRC_ASRIER_AOLIE_SHIFT (6U)
2511/*! AOLIE - AOLIE
2512 * 0b1..interrupt enabled
2513 * 0b0..interrupt disabled
2514 */
2515#define ASRC_ASRIER_AOLIE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK)
2516#define ASRC_ASRIER_AFPWE_MASK (0x80U)
2517#define ASRC_ASRIER_AFPWE_SHIFT (7U)
2518/*! AFPWE - AFPWE
2519 * 0b1..interrupt enabled
2520 * 0b0..interrupt disabled
2521 */
2522#define ASRC_ASRIER_AFPWE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK)
2523/*! @} */
2524
2525/*! @name ASRCNCR - ASRC Channel Number Configuration Register */
2526/*! @{ */
2527#define ASRC_ASRCNCR_ANCA_MASK (0xFU)
2528#define ASRC_ASRCNCR_ANCA_SHIFT (0U)
2529/*! ANCA - ANCA
2530 * 0b0000..0 channels in A (Pair A is disabled)
2531 * 0b0001..1 channel in A
2532 * 0b0010..2 channels in A
2533 * 0b0011..3 channels in A
2534 * 0b0100..4 channels in A
2535 * 0b0101..5 channels in A
2536 * 0b0110..6 channels in A
2537 * 0b0111..7 channels in A
2538 * 0b1000..8 channels in A
2539 * 0b1001..9 channels in A
2540 * 0b1010..10 channels in A
2541 * 0b1011-0b1111..Should not be used.
2542 */
2543#define ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK)
2544#define ASRC_ASRCNCR_ANCB_MASK (0xF0U)
2545#define ASRC_ASRCNCR_ANCB_SHIFT (4U)
2546/*! ANCB - ANCB
2547 * 0b0000..0 channels in B (Pair B is disabled)
2548 * 0b0001..1 channel in B
2549 * 0b0010..2 channels in B
2550 * 0b0011..3 channels in B
2551 * 0b0100..4 channels in B
2552 * 0b0101..5 channels in B
2553 * 0b0110..6 channels in B
2554 * 0b0111..7 channels in B
2555 * 0b1000..8 channels in B
2556 * 0b1001..9 channels in B
2557 * 0b1010..10 channels in B
2558 * 0b1011-0b1111..Should not be used.
2559 */
2560#define ASRC_ASRCNCR_ANCB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK)
2561#define ASRC_ASRCNCR_ANCC_MASK (0xF00U)
2562#define ASRC_ASRCNCR_ANCC_SHIFT (8U)
2563/*! ANCC - ANCC
2564 * 0b0000..0 channels in C (Pair C is disabled)
2565 * 0b0001..1 channel in C
2566 * 0b0010..2 channels in C
2567 * 0b0011..3 channels in C
2568 * 0b0100..4 channels in C
2569 * 0b0101..5 channels in C
2570 * 0b0110..6 channels in C
2571 * 0b0111..7 channels in C
2572 * 0b1000..8 channels in C
2573 * 0b1001..9 channels in C
2574 * 0b1010..10 channels in C
2575 * 0b1011-0b1111..Should not be used.
2576 */
2577#define ASRC_ASRCNCR_ANCC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK)
2578/*! @} */
2579
2580/*! @name ASRCFG - ASRC Filter Configuration Status Register */
2581/*! @{ */
2582#define ASRC_ASRCFG_PREMODA_MASK (0xC0U)
2583#define ASRC_ASRCFG_PREMODA_SHIFT (6U)
2584/*! PREMODA - PREMODA
2585 * 0b00..Select Upsampling-by-2 as defined in
2586 * 0b01..Select Direct-Connection as defined in
2587 * 0b10..Select Downsampling-by-2 as defined in
2588 * 0b11..Select passthrough mode. In this case, POSTMODA[1-0] have no use.
2589 */
2590#define ASRC_ASRCFG_PREMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK)
2591#define ASRC_ASRCFG_POSTMODA_MASK (0x300U)
2592#define ASRC_ASRCFG_POSTMODA_SHIFT (8U)
2593/*! POSTMODA - POSTMODA
2594 * 0b00..Select Upsampling-by-2 as defined in
2595 * 0b01..Select Direct-Connection as defined in
2596 * 0b10..Select Downsampling-by-2 as defined in
2597 */
2598#define ASRC_ASRCFG_POSTMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK)
2599#define ASRC_ASRCFG_PREMODB_MASK (0xC00U)
2600#define ASRC_ASRCFG_PREMODB_SHIFT (10U)
2601/*! PREMODB - PREMODB
2602 * 0b00..Select Upsampling-by-2 as defined in
2603 * 0b01..Select Direct-Connection as defined in
2604 * 0b10..Select Downsampling-by-2 as defined in
2605 * 0b11..Select passthrough mode. In this case, POSTMODB[1-0] have no use.
2606 */
2607#define ASRC_ASRCFG_PREMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK)
2608#define ASRC_ASRCFG_POSTMODB_MASK (0x3000U)
2609#define ASRC_ASRCFG_POSTMODB_SHIFT (12U)
2610/*! POSTMODB - POSTMODB
2611 * 0b00..Select Upsampling-by-2 as defined in
2612 * 0b01..Select Direct-Connection as defined in
2613 * 0b10..Select Downsampling-by-2 as defined in
2614 */
2615#define ASRC_ASRCFG_POSTMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK)
2616#define ASRC_ASRCFG_PREMODC_MASK (0xC000U)
2617#define ASRC_ASRCFG_PREMODC_SHIFT (14U)
2618/*! PREMODC - PREMODC
2619 * 0b00..Select Upsampling-by-2 as defined in
2620 * 0b01..Select Direct-Connection as defined in
2621 * 0b10..Select Downsampling-by-2 as defined in
2622 * 0b11..Select passthrough mode. In this case, POSTMODC[1-0] have no use.
2623 */
2624#define ASRC_ASRCFG_PREMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK)
2625#define ASRC_ASRCFG_POSTMODC_MASK (0x30000U)
2626#define ASRC_ASRCFG_POSTMODC_SHIFT (16U)
2627/*! POSTMODC - POSTMODC
2628 * 0b00..Select Upsampling-by-2 as defined in Signal Processing Flow.
2629 * 0b01..Select Direct-Connection as defined in Signal Processing Flow.
2630 * 0b10..Select Downsampling-by-2 as defined in Signal Processing Flow.
2631 */
2632#define ASRC_ASRCFG_POSTMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK)
2633#define ASRC_ASRCFG_NDPRA_MASK (0x40000U)
2634#define ASRC_ASRCFG_NDPRA_SHIFT (18U)
2635/*! NDPRA - NDPRA
2636 * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
2637 * 0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
2638 */
2639#define ASRC_ASRCFG_NDPRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK)
2640#define ASRC_ASRCFG_NDPRB_MASK (0x80000U)
2641#define ASRC_ASRCFG_NDPRB_SHIFT (19U)
2642/*! NDPRB - NDPRB
2643 * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
2644 * 0b1..Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM.
2645 */
2646#define ASRC_ASRCFG_NDPRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK)
2647#define ASRC_ASRCFG_NDPRC_MASK (0x100000U)
2648#define ASRC_ASRCFG_NDPRC_SHIFT (20U)
2649/*! NDPRC - NDPRC
2650 * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
2651 * 0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
2652 */
2653#define ASRC_ASRCFG_NDPRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK)
2654#define ASRC_ASRCFG_INIRQA_MASK (0x200000U)
2655#define ASRC_ASRCFG_INIRQA_SHIFT (21U)
2656/*! INIRQA - INIRQA
2657 */
2658#define ASRC_ASRCFG_INIRQA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK)
2659#define ASRC_ASRCFG_INIRQB_MASK (0x400000U)
2660#define ASRC_ASRCFG_INIRQB_SHIFT (22U)
2661/*! INIRQB - INIRQB
2662 */
2663#define ASRC_ASRCFG_INIRQB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK)
2664#define ASRC_ASRCFG_INIRQC_MASK (0x800000U)
2665#define ASRC_ASRCFG_INIRQC_SHIFT (23U)
2666/*! INIRQC - INIRQC
2667 */
2668#define ASRC_ASRCFG_INIRQC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK)
2669/*! @} */
2670
2671/*! @name ASRCSR - ASRC Clock Source Register */
2672/*! @{ */
2673#define ASRC_ASRCSR_AICSA_MASK (0xFU)
2674#define ASRC_ASRCSR_AICSA_SHIFT (0U)
2675/*! AICSA - AICSA
2676 * 0b0000..bit clock 0
2677 * 0b0001..bit clock 1
2678 * 0b0010..bit clock 2
2679 * 0b0011..bit clock 3
2680 * 0b0100..bit clock 4
2681 * 0b0101..bit clock 5
2682 * 0b0110..bit clock 6
2683 * 0b0111..bit clock 7
2684 * 0b1000..bit clock 8
2685 * 0b1001..bit clock 9
2686 * 0b1010..bit clock A
2687 * 0b1011..bit clock B
2688 * 0b1100..bit clock C
2689 * 0b1101..bit clock D
2690 * 0b1110..bit clock E
2691 * 0b1111..clock disabled, connected to zero
2692 */
2693#define ASRC_ASRCSR_AICSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK)
2694#define ASRC_ASRCSR_AICSB_MASK (0xF0U)
2695#define ASRC_ASRCSR_AICSB_SHIFT (4U)
2696/*! AICSB - AICSB
2697 * 0b0000..bit clock 0
2698 * 0b0001..bit clock 1
2699 * 0b0010..bit clock 2
2700 * 0b0011..bit clock 3
2701 * 0b0100..bit clock 4
2702 * 0b0101..bit clock 5
2703 * 0b0110..bit clock 6
2704 * 0b0111..bit clock 7
2705 * 0b1000..bit clock 8
2706 * 0b1001..bit clock 9
2707 * 0b1010..bit clock A
2708 * 0b1011..bit clock B
2709 * 0b1100..bit clock C
2710 * 0b1101..bit clock D
2711 * 0b1110..bit clock E
2712 * 0b1111..clock disabled, connected to zero
2713 */
2714#define ASRC_ASRCSR_AICSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK)
2715#define ASRC_ASRCSR_AICSC_MASK (0xF00U)
2716#define ASRC_ASRCSR_AICSC_SHIFT (8U)
2717/*! AICSC - AICSC
2718 * 0b0000..bit clock 0
2719 * 0b0001..bit clock 1
2720 * 0b0010..bit clock 2
2721 * 0b0011..bit clock 3
2722 * 0b0100..bit clock 4
2723 * 0b0101..bit clock 5
2724 * 0b0110..bit clock 6
2725 * 0b0111..bit clock 7
2726 * 0b1000..bit clock 8
2727 * 0b1001..bit clock 9
2728 * 0b1010..bit clock A
2729 * 0b1011..bit clock B
2730 * 0b1100..bit clock C
2731 * 0b1101..bit clock D
2732 * 0b1110..bit clock E
2733 * 0b1111..clock disabled, connected to zero
2734 */
2735#define ASRC_ASRCSR_AICSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK)
2736#define ASRC_ASRCSR_AOCSA_MASK (0xF000U)
2737#define ASRC_ASRCSR_AOCSA_SHIFT (12U)
2738/*! AOCSA - AOCSA
2739 * 0b0000..bit clock 0
2740 * 0b0001..bit clock 1
2741 * 0b0010..bit clock 2
2742 * 0b0011..bit clock 3
2743 * 0b0100..bit clock 4
2744 * 0b0101..bit clock 5
2745 * 0b0110..bit clock 6
2746 * 0b0111..bit clock 7
2747 * 0b1000..bit clock 8
2748 * 0b1001..bit clock 9
2749 * 0b1010..bit clock A
2750 * 0b1011..bit clock B
2751 * 0b1100..bit clock C
2752 * 0b1101..bit clock D
2753 * 0b1110..bit clock E
2754 * 0b1111..clock disabled, connected to zero
2755 */
2756#define ASRC_ASRCSR_AOCSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK)
2757#define ASRC_ASRCSR_AOCSB_MASK (0xF0000U)
2758#define ASRC_ASRCSR_AOCSB_SHIFT (16U)
2759/*! AOCSB - AOCSB
2760 * 0b0000..bit clock 0
2761 * 0b0001..bit clock 1
2762 * 0b0010..bit clock 2
2763 * 0b0011..bit clock 3
2764 * 0b0100..bit clock 4
2765 * 0b0101..bit clock 5
2766 * 0b0110..bit clock 6
2767 * 0b0111..bit clock 7
2768 * 0b1000..bit clock 8
2769 * 0b1001..bit clock 9
2770 * 0b1010..bit clock A
2771 * 0b1011..bit clock B
2772 * 0b1100..bit clock C
2773 * 0b1101..bit clock D
2774 * 0b1110..bit clock E
2775 * 0b1111..clock disabled, connected to zero
2776 */
2777#define ASRC_ASRCSR_AOCSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK)
2778#define ASRC_ASRCSR_AOCSC_MASK (0xF00000U)
2779#define ASRC_ASRCSR_AOCSC_SHIFT (20U)
2780/*! AOCSC - AOCSC
2781 * 0b0000..bit clock 0
2782 * 0b0001..bit clock 1
2783 * 0b0010..bit clock 2
2784 * 0b0011..bit clock 3
2785 * 0b0100..bit clock 4
2786 * 0b0101..bit clock 5
2787 * 0b0110..bit clock 6
2788 * 0b0111..bit clock 7
2789 * 0b1000..bit clock 8
2790 * 0b1001..bit clock 9
2791 * 0b1010..bit clock A
2792 * 0b1011..bit clock B
2793 * 0b1100..bit clock C
2794 * 0b1101..bit clock D
2795 * 0b1110..bit clock E
2796 * 0b1111..clock disabled, connected to zero
2797 */
2798#define ASRC_ASRCSR_AOCSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK)
2799/*! @} */
2800
2801/*! @name ASRCDR1 - ASRC Clock Divider Register 1 */
2802/*! @{ */
2803#define ASRC_ASRCDR1_AICPA_MASK (0x7U)
2804#define ASRC_ASRCDR1_AICPA_SHIFT (0U)
2805/*! AICPA - AICPA
2806 */
2807#define ASRC_ASRCDR1_AICPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK)
2808#define ASRC_ASRCDR1_AICDA_MASK (0x38U)
2809#define ASRC_ASRCDR1_AICDA_SHIFT (3U)
2810/*! AICDA - AICDA
2811 */
2812#define ASRC_ASRCDR1_AICDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK)
2813#define ASRC_ASRCDR1_AICPB_MASK (0x1C0U)
2814#define ASRC_ASRCDR1_AICPB_SHIFT (6U)
2815/*! AICPB - AICPB
2816 */
2817#define ASRC_ASRCDR1_AICPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK)
2818#define ASRC_ASRCDR1_AICDB_MASK (0xE00U)
2819#define ASRC_ASRCDR1_AICDB_SHIFT (9U)
2820/*! AICDB - AICDB
2821 */
2822#define ASRC_ASRCDR1_AICDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK)
2823#define ASRC_ASRCDR1_AOCPA_MASK (0x7000U)
2824#define ASRC_ASRCDR1_AOCPA_SHIFT (12U)
2825/*! AOCPA - AOCPA
2826 */
2827#define ASRC_ASRCDR1_AOCPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK)
2828#define ASRC_ASRCDR1_AOCDA_MASK (0x38000U)
2829#define ASRC_ASRCDR1_AOCDA_SHIFT (15U)
2830/*! AOCDA - AOCDA
2831 */
2832#define ASRC_ASRCDR1_AOCDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK)
2833#define ASRC_ASRCDR1_AOCPB_MASK (0x1C0000U)
2834#define ASRC_ASRCDR1_AOCPB_SHIFT (18U)
2835/*! AOCPB - AOCPB
2836 */
2837#define ASRC_ASRCDR1_AOCPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK)
2838#define ASRC_ASRCDR1_AOCDB_MASK (0xE00000U)
2839#define ASRC_ASRCDR1_AOCDB_SHIFT (21U)
2840/*! AOCDB - AOCDB
2841 */
2842#define ASRC_ASRCDR1_AOCDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK)
2843/*! @} */
2844
2845/*! @name ASRCDR2 - ASRC Clock Divider Register 2 */
2846/*! @{ */
2847#define ASRC_ASRCDR2_AICPC_MASK (0x7U)
2848#define ASRC_ASRCDR2_AICPC_SHIFT (0U)
2849/*! AICPC - AICPC
2850 */
2851#define ASRC_ASRCDR2_AICPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK)
2852#define ASRC_ASRCDR2_AICDC_MASK (0x38U)
2853#define ASRC_ASRCDR2_AICDC_SHIFT (3U)
2854/*! AICDC - AICDC
2855 */
2856#define ASRC_ASRCDR2_AICDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK)
2857#define ASRC_ASRCDR2_AOCPC_MASK (0x1C0U)
2858#define ASRC_ASRCDR2_AOCPC_SHIFT (6U)
2859/*! AOCPC - AOCPC
2860 */
2861#define ASRC_ASRCDR2_AOCPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK)
2862#define ASRC_ASRCDR2_AOCDC_MASK (0xE00U)
2863#define ASRC_ASRCDR2_AOCDC_SHIFT (9U)
2864/*! AOCDC - AOCDC
2865 */
2866#define ASRC_ASRCDR2_AOCDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK)
2867/*! @} */
2868
2869/*! @name ASRSTR - ASRC Status Register */
2870/*! @{ */
2871#define ASRC_ASRSTR_AIDEA_MASK (0x1U)
2872#define ASRC_ASRSTR_AIDEA_SHIFT (0U)
2873/*! AIDEA - AIDEA
2874 */
2875#define ASRC_ASRSTR_AIDEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK)
2876#define ASRC_ASRSTR_AIDEB_MASK (0x2U)
2877#define ASRC_ASRSTR_AIDEB_SHIFT (1U)
2878/*! AIDEB - AIDEB
2879 */
2880#define ASRC_ASRSTR_AIDEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK)
2881#define ASRC_ASRSTR_AIDEC_MASK (0x4U)
2882#define ASRC_ASRSTR_AIDEC_SHIFT (2U)
2883/*! AIDEC - AIDEC
2884 */
2885#define ASRC_ASRSTR_AIDEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK)
2886#define ASRC_ASRSTR_AODFA_MASK (0x8U)
2887#define ASRC_ASRSTR_AODFA_SHIFT (3U)
2888/*! AODFA - AODFA
2889 */
2890#define ASRC_ASRSTR_AODFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK)
2891#define ASRC_ASRSTR_AODFB_MASK (0x10U)
2892#define ASRC_ASRSTR_AODFB_SHIFT (4U)
2893/*! AODFB - AODFB
2894 */
2895#define ASRC_ASRSTR_AODFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK)
2896#define ASRC_ASRSTR_AODFC_MASK (0x20U)
2897#define ASRC_ASRSTR_AODFC_SHIFT (5U)
2898/*! AODFC - AODFC
2899 */
2900#define ASRC_ASRSTR_AODFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK)
2901#define ASRC_ASRSTR_AOLE_MASK (0x40U)
2902#define ASRC_ASRSTR_AOLE_SHIFT (6U)
2903/*! AOLE - AOLE
2904 */
2905#define ASRC_ASRSTR_AOLE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK)
2906#define ASRC_ASRSTR_FPWT_MASK (0x80U)
2907#define ASRC_ASRSTR_FPWT_SHIFT (7U)
2908/*! FPWT - FPWT
2909 */
2910#define ASRC_ASRSTR_FPWT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK)
2911#define ASRC_ASRSTR_AIDUA_MASK (0x100U)
2912#define ASRC_ASRSTR_AIDUA_SHIFT (8U)
2913/*! AIDUA - AIDUA
2914 */
2915#define ASRC_ASRSTR_AIDUA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK)
2916#define ASRC_ASRSTR_AIDUB_MASK (0x200U)
2917#define ASRC_ASRSTR_AIDUB_SHIFT (9U)
2918/*! AIDUB - AIDUB
2919 */
2920#define ASRC_ASRSTR_AIDUB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK)
2921#define ASRC_ASRSTR_AIDUC_MASK (0x400U)
2922#define ASRC_ASRSTR_AIDUC_SHIFT (10U)
2923/*! AIDUC - AIDUC
2924 */
2925#define ASRC_ASRSTR_AIDUC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK)
2926#define ASRC_ASRSTR_AODOA_MASK (0x800U)
2927#define ASRC_ASRSTR_AODOA_SHIFT (11U)
2928/*! AODOA - AODOA
2929 */
2930#define ASRC_ASRSTR_AODOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK)
2931#define ASRC_ASRSTR_AODOB_MASK (0x1000U)
2932#define ASRC_ASRSTR_AODOB_SHIFT (12U)
2933/*! AODOB - AODOB
2934 */
2935#define ASRC_ASRSTR_AODOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK)
2936#define ASRC_ASRSTR_AODOC_MASK (0x2000U)
2937#define ASRC_ASRSTR_AODOC_SHIFT (13U)
2938/*! AODOC - AODOC
2939 */
2940#define ASRC_ASRSTR_AODOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK)
2941#define ASRC_ASRSTR_AIOLA_MASK (0x4000U)
2942#define ASRC_ASRSTR_AIOLA_SHIFT (14U)
2943/*! AIOLA - AIOLA
2944 */
2945#define ASRC_ASRSTR_AIOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK)
2946#define ASRC_ASRSTR_AIOLB_MASK (0x8000U)
2947#define ASRC_ASRSTR_AIOLB_SHIFT (15U)
2948/*! AIOLB - AIOLB
2949 */
2950#define ASRC_ASRSTR_AIOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK)
2951#define ASRC_ASRSTR_AIOLC_MASK (0x10000U)
2952#define ASRC_ASRSTR_AIOLC_SHIFT (16U)
2953/*! AIOLC - AIOLC
2954 */
2955#define ASRC_ASRSTR_AIOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK)
2956#define ASRC_ASRSTR_AOOLA_MASK (0x20000U)
2957#define ASRC_ASRSTR_AOOLA_SHIFT (17U)
2958/*! AOOLA - AOOLA
2959 */
2960#define ASRC_ASRSTR_AOOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK)
2961#define ASRC_ASRSTR_AOOLB_MASK (0x40000U)
2962#define ASRC_ASRSTR_AOOLB_SHIFT (18U)
2963/*! AOOLB - AOOLB
2964 */
2965#define ASRC_ASRSTR_AOOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK)
2966#define ASRC_ASRSTR_AOOLC_MASK (0x80000U)
2967#define ASRC_ASRSTR_AOOLC_SHIFT (19U)
2968/*! AOOLC - AOOLC
2969 */
2970#define ASRC_ASRSTR_AOOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK)
2971#define ASRC_ASRSTR_ATQOL_MASK (0x100000U)
2972#define ASRC_ASRSTR_ATQOL_SHIFT (20U)
2973/*! ATQOL - ATQOL
2974 */
2975#define ASRC_ASRSTR_ATQOL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK)
2976#define ASRC_ASRSTR_DSLCNT_MASK (0x200000U)
2977#define ASRC_ASRSTR_DSLCNT_SHIFT (21U)
2978/*! DSLCNT - DSLCNT
2979 */
2980#define ASRC_ASRSTR_DSLCNT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK)
2981/*! @} */
2982
2983/*! @name ASRPM - ASRC Parameter Register n */
2984/*! @{ */
2985#define ASRC_ASRPM_PARAMETER_VALUE_MASK (0xFFFFFFU)
2986#define ASRC_ASRPM_PARAMETER_VALUE_SHIFT (0U)
2987/*! PARAMETER_VALUE - PARAMETER_VALUE
2988 */
2989#define ASRC_ASRPM_PARAMETER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPM_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPM_PARAMETER_VALUE_MASK)
2990/*! @} */
2991
2992/* The count of ASRC_ASRPM */
2993#define ASRC_ASRPM_COUNT (5U)
2994
2995/*! @name ASRTFR1 - ASRC ASRC Task Queue FIFO Register 1 */
2996/*! @{ */
2997#define ASRC_ASRTFR1_TF_BASE_MASK (0x1FC0U)
2998#define ASRC_ASRTFR1_TF_BASE_SHIFT (6U)
2999/*! TF_BASE - TF_BASE
3000 */
3001#define ASRC_ASRTFR1_TF_BASE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK)
3002#define ASRC_ASRTFR1_TF_FILL_MASK (0xFE000U)
3003#define ASRC_ASRTFR1_TF_FILL_SHIFT (13U)
3004/*! TF_FILL - TF_FILL
3005 */
3006#define ASRC_ASRTFR1_TF_FILL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK)
3007/*! @} */
3008
3009/*! @name ASRCCR - ASRC Channel Counter Register */
3010/*! @{ */
3011#define ASRC_ASRCCR_ACIA_MASK (0xFU)
3012#define ASRC_ASRCCR_ACIA_SHIFT (0U)
3013/*! ACIA - ACIA
3014 */
3015#define ASRC_ASRCCR_ACIA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK)
3016#define ASRC_ASRCCR_ACIB_MASK (0xF0U)
3017#define ASRC_ASRCCR_ACIB_SHIFT (4U)
3018/*! ACIB - ACIB
3019 */
3020#define ASRC_ASRCCR_ACIB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK)
3021#define ASRC_ASRCCR_ACIC_MASK (0xF00U)
3022#define ASRC_ASRCCR_ACIC_SHIFT (8U)
3023/*! ACIC - ACIC
3024 */
3025#define ASRC_ASRCCR_ACIC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK)
3026#define ASRC_ASRCCR_ACOA_MASK (0xF000U)
3027#define ASRC_ASRCCR_ACOA_SHIFT (12U)
3028/*! ACOA - ACOA
3029 */
3030#define ASRC_ASRCCR_ACOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK)
3031#define ASRC_ASRCCR_ACOB_MASK (0xF0000U)
3032#define ASRC_ASRCCR_ACOB_SHIFT (16U)
3033/*! ACOB - ACOB
3034 */
3035#define ASRC_ASRCCR_ACOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK)
3036#define ASRC_ASRCCR_ACOC_MASK (0xF00000U)
3037#define ASRC_ASRCCR_ACOC_SHIFT (20U)
3038/*! ACOC - ACOC
3039 */
3040#define ASRC_ASRCCR_ACOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK)
3041/*! @} */
3042
3043/*! @name ASRDIA - ASRC Data Input Register for Pair x */
3044/*! @{ */
3045#define ASRC_ASRDIA_DATA_MASK (0xFFFFFFU)
3046#define ASRC_ASRDIA_DATA_SHIFT (0U)
3047/*! DATA - DATA
3048 */
3049#define ASRC_ASRDIA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK)
3050/*! @} */
3051
3052/*! @name ASRDOA - ASRC Data Output Register for Pair x */
3053/*! @{ */
3054#define ASRC_ASRDOA_DATA_MASK (0xFFFFFFU)
3055#define ASRC_ASRDOA_DATA_SHIFT (0U)
3056/*! DATA - DATA
3057 */
3058#define ASRC_ASRDOA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK)
3059/*! @} */
3060
3061/*! @name ASRDIB - ASRC Data Input Register for Pair x */
3062/*! @{ */
3063#define ASRC_ASRDIB_DATA_MASK (0xFFFFFFU)
3064#define ASRC_ASRDIB_DATA_SHIFT (0U)
3065/*! DATA - DATA
3066 */
3067#define ASRC_ASRDIB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK)
3068/*! @} */
3069
3070/*! @name ASRDOB - ASRC Data Output Register for Pair x */
3071/*! @{ */
3072#define ASRC_ASRDOB_DATA_MASK (0xFFFFFFU)
3073#define ASRC_ASRDOB_DATA_SHIFT (0U)
3074/*! DATA - DATA
3075 */
3076#define ASRC_ASRDOB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK)
3077/*! @} */
3078
3079/*! @name ASRDIC - ASRC Data Input Register for Pair x */
3080/*! @{ */
3081#define ASRC_ASRDIC_DATA_MASK (0xFFFFFFU)
3082#define ASRC_ASRDIC_DATA_SHIFT (0U)
3083/*! DATA - DATA
3084 */
3085#define ASRC_ASRDIC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK)
3086/*! @} */
3087
3088/*! @name ASRDOC - ASRC Data Output Register for Pair x */
3089/*! @{ */
3090#define ASRC_ASRDOC_DATA_MASK (0xFFFFFFU)
3091#define ASRC_ASRDOC_DATA_SHIFT (0U)
3092/*! DATA - DATA
3093 */
3094#define ASRC_ASRDOC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK)
3095/*! @} */
3096
3097/*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */
3098/*! @{ */
3099#define ASRC_ASRIDRHA_IDRATIOA_H_MASK (0xFFU)
3100#define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT (0U)
3101/*! IDRATIOA_H - IDRATIOA_H
3102 */
3103#define ASRC_ASRIDRHA_IDRATIOA_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK)
3104/*! @} */
3105
3106/*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */
3107/*! @{ */
3108#define ASRC_ASRIDRLA_IDRATIOA_L_MASK (0xFFFFFFU)
3109#define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT (0U)
3110/*! IDRATIOA_L - IDRATIOA_L
3111 */
3112#define ASRC_ASRIDRLA_IDRATIOA_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK)
3113/*! @} */
3114
3115/*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */
3116/*! @{ */
3117#define ASRC_ASRIDRHB_IDRATIOB_H_MASK (0xFFU)
3118#define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT (0U)
3119/*! IDRATIOB_H - IDRATIOB_H
3120 */
3121#define ASRC_ASRIDRHB_IDRATIOB_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK)
3122/*! @} */
3123
3124/*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */
3125/*! @{ */
3126#define ASRC_ASRIDRLB_IDRATIOB_L_MASK (0xFFFFFFU)
3127#define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT (0U)
3128/*! IDRATIOB_L - IDRATIOB_L
3129 */
3130#define ASRC_ASRIDRLB_IDRATIOB_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK)
3131/*! @} */
3132
3133/*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */
3134/*! @{ */
3135#define ASRC_ASRIDRHC_IDRATIOC_H_MASK (0xFFU)
3136#define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT (0U)
3137/*! IDRATIOC_H - IDRATIOC_H
3138 */
3139#define ASRC_ASRIDRHC_IDRATIOC_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK)
3140/*! @} */
3141
3142/*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */
3143/*! @{ */
3144#define ASRC_ASRIDRLC_IDRATIOC_L_MASK (0xFFFFFFU)
3145#define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT (0U)
3146/*! IDRATIOC_L - IDRATIOC_L
3147 */
3148#define ASRC_ASRIDRLC_IDRATIOC_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK)
3149/*! @} */
3150
3151/*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */
3152/*! @{ */
3153#define ASRC_ASR76K_ASR76K_MASK (0x1FFFFU)
3154#define ASRC_ASR76K_ASR76K_SHIFT (0U)
3155/*! ASR76K - ASR76K
3156 */
3157#define ASRC_ASR76K_ASR76K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK)
3158/*! @} */
3159
3160/*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */
3161/*! @{ */
3162#define ASRC_ASR56K_ASR56K_MASK (0x1FFFFU)
3163#define ASRC_ASR56K_ASR56K_SHIFT (0U)
3164/*! ASR56K - ASR56K
3165 */
3166#define ASRC_ASR56K_ASR56K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK)
3167/*! @} */
3168
3169/*! @name ASRMCRA - ASRC Misc Control Register for Pair A */
3170/*! @{ */
3171#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK (0x3FU)
3172#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT (0U)
3173/*! INFIFO_THRESHOLDA - INFIFO_THRESHOLDA
3174 */
3175#define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK)
3176#define ASRC_ASRMCRA_RSYNOFA_MASK (0x400U)
3177#define ASRC_ASRMCRA_RSYNOFA_SHIFT (10U)
3178/*! RSYNOFA - RSYNOFA
3179 */
3180#define ASRC_ASRMCRA_RSYNOFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK)
3181#define ASRC_ASRMCRA_RSYNIFA_MASK (0x800U)
3182#define ASRC_ASRMCRA_RSYNIFA_SHIFT (11U)
3183/*! RSYNIFA - RSYNIFA
3184 */
3185#define ASRC_ASRMCRA_RSYNIFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK)
3186#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK (0x3F000U)
3187#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT (12U)
3188/*! OUTFIFO_THRESHOLDA - OUTFIFO_THRESHOLDA
3189 */
3190#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK)
3191#define ASRC_ASRMCRA_BYPASSPOLYA_MASK (0x100000U)
3192#define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT (20U)
3193/*! BYPASSPOLYA - BYPASSPOLYA
3194 * 0b1..Bypass polyphase filtering.
3195 * 0b0..Don't bypass polyphase filtering.
3196 */
3197#define ASRC_ASRMCRA_BYPASSPOLYA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK)
3198#define ASRC_ASRMCRA_BUFSTALLA_MASK (0x200000U)
3199#define ASRC_ASRMCRA_BUFSTALLA_SHIFT (21U)
3200/*! BUFSTALLA - BUFSTALLA
3201 * 0b1..Stall Pair A conversion in case of near empty/full FIFO conditions.
3202 * 0b0..Don't stall Pair A conversion even in case of near empty/full FIFO conditions.
3203 */
3204#define ASRC_ASRMCRA_BUFSTALLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK)
3205#define ASRC_ASRMCRA_EXTTHRSHA_MASK (0x400000U)
3206#define ASRC_ASRMCRA_EXTTHRSHA_SHIFT (22U)
3207/*! EXTTHRSHA - EXTTHRSHA
3208 * 0b1..Use external defined thresholds.
3209 * 0b0..Use default thresholds.
3210 */
3211#define ASRC_ASRMCRA_EXTTHRSHA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK)
3212#define ASRC_ASRMCRA_ZEROBUFA_MASK (0x800000U)
3213#define ASRC_ASRMCRA_ZEROBUFA_SHIFT (23U)
3214/*! ZEROBUFA - ZEROBUFA
3215 * 0b1..Don't zeroize the buffer
3216 * 0b0..Zeroize the buffer
3217 */
3218#define ASRC_ASRMCRA_ZEROBUFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK)
3219/*! @} */
3220
3221/*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */
3222/*! @{ */
3223#define ASRC_ASRFSTA_INFIFO_FILLA_MASK (0x7FU)
3224#define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT (0U)
3225/*! INFIFO_FILLA - INFIFO_FILLA
3226 */
3227#define ASRC_ASRFSTA_INFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK)
3228#define ASRC_ASRFSTA_IAEA_MASK (0x800U)
3229#define ASRC_ASRFSTA_IAEA_SHIFT (11U)
3230/*! IAEA - IAEA
3231 */
3232#define ASRC_ASRFSTA_IAEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK)
3233#define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK (0x7F000U)
3234#define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT (12U)
3235/*! OUTFIFO_FILLA - OUTFIFO_FILLA
3236 */
3237#define ASRC_ASRFSTA_OUTFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK)
3238#define ASRC_ASRFSTA_OAFA_MASK (0x800000U)
3239#define ASRC_ASRFSTA_OAFA_SHIFT (23U)
3240/*! OAFA - OAFA
3241 */
3242#define ASRC_ASRFSTA_OAFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK)
3243/*! @} */
3244
3245/*! @name ASRMCRB - ASRC Misc Control Register for Pair B */
3246/*! @{ */
3247#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK (0x3FU)
3248#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT (0U)
3249/*! INFIFO_THRESHOLDB - INFIFO_THRESHOLDB
3250 */
3251#define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK)
3252#define ASRC_ASRMCRB_RSYNOFB_MASK (0x400U)
3253#define ASRC_ASRMCRB_RSYNOFB_SHIFT (10U)
3254/*! RSYNOFB - RSYNOFB
3255 */
3256#define ASRC_ASRMCRB_RSYNOFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK)
3257#define ASRC_ASRMCRB_RSYNIFB_MASK (0x800U)
3258#define ASRC_ASRMCRB_RSYNIFB_SHIFT (11U)
3259/*! RSYNIFB - RSYNIFB
3260 */
3261#define ASRC_ASRMCRB_RSYNIFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK)
3262#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK (0x3F000U)
3263#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT (12U)
3264/*! OUTFIFO_THRESHOLDB - OUTFIFO_THRESHOLDB
3265 */
3266#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK)
3267#define ASRC_ASRMCRB_BYPASSPOLYB_MASK (0x100000U)
3268#define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT (20U)
3269/*! BYPASSPOLYB - BYPASSPOLYB
3270 * 0b1..Bypass polyphase filtering.
3271 * 0b0..Don't bypass polyphase filtering.
3272 */
3273#define ASRC_ASRMCRB_BYPASSPOLYB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK)
3274#define ASRC_ASRMCRB_BUFSTALLB_MASK (0x200000U)
3275#define ASRC_ASRMCRB_BUFSTALLB_SHIFT (21U)
3276/*! BUFSTALLB - BUFSTALLB
3277 * 0b1..Stall Pair B conversion in case of near empty/full FIFO conditions.
3278 * 0b0..Don't stall Pair B conversion even in case of near empty/full FIFO conditions.
3279 */
3280#define ASRC_ASRMCRB_BUFSTALLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK)
3281#define ASRC_ASRMCRB_EXTTHRSHB_MASK (0x400000U)
3282#define ASRC_ASRMCRB_EXTTHRSHB_SHIFT (22U)
3283/*! EXTTHRSHB - EXTTHRSHB
3284 * 0b1..Use external defined thresholds.
3285 * 0b0..Use default thresholds.
3286 */
3287#define ASRC_ASRMCRB_EXTTHRSHB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK)
3288#define ASRC_ASRMCRB_ZEROBUFB_MASK (0x800000U)
3289#define ASRC_ASRMCRB_ZEROBUFB_SHIFT (23U)
3290/*! ZEROBUFB - ZEROBUFB
3291 * 0b1..Don't zeroize the buffer
3292 * 0b0..Zeroize the buffer
3293 */
3294#define ASRC_ASRMCRB_ZEROBUFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK)
3295/*! @} */
3296
3297/*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */
3298/*! @{ */
3299#define ASRC_ASRFSTB_INFIFO_FILLB_MASK (0x7FU)
3300#define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT (0U)
3301/*! INFIFO_FILLB - INFIFO_FILLB
3302 */
3303#define ASRC_ASRFSTB_INFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK)
3304#define ASRC_ASRFSTB_IAEB_MASK (0x800U)
3305#define ASRC_ASRFSTB_IAEB_SHIFT (11U)
3306/*! IAEB - IAEB
3307 */
3308#define ASRC_ASRFSTB_IAEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK)
3309#define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK (0x7F000U)
3310#define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT (12U)
3311/*! OUTFIFO_FILLB - OUTFIFO_FILLB
3312 */
3313#define ASRC_ASRFSTB_OUTFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK)
3314#define ASRC_ASRFSTB_OAFB_MASK (0x800000U)
3315#define ASRC_ASRFSTB_OAFB_SHIFT (23U)
3316/*! OAFB - OAFB
3317 */
3318#define ASRC_ASRFSTB_OAFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK)
3319/*! @} */
3320
3321/*! @name ASRMCRC - ASRC Misc Control Register for Pair C */
3322/*! @{ */
3323#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK (0x3FU)
3324#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT (0U)
3325/*! INFIFO_THRESHOLDC - INFIFO_THRESHOLDC
3326 */
3327#define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK)
3328#define ASRC_ASRMCRC_RSYNOFC_MASK (0x400U)
3329#define ASRC_ASRMCRC_RSYNOFC_SHIFT (10U)
3330/*! RSYNOFC - RSYNOFC
3331 */
3332#define ASRC_ASRMCRC_RSYNOFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK)
3333#define ASRC_ASRMCRC_RSYNIFC_MASK (0x800U)
3334#define ASRC_ASRMCRC_RSYNIFC_SHIFT (11U)
3335/*! RSYNIFC - RSYNIFC
3336 */
3337#define ASRC_ASRMCRC_RSYNIFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK)
3338#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK (0x3F000U)
3339#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT (12U)
3340/*! OUTFIFO_THRESHOLDC - OUTFIFO_THRESHOLDC
3341 */
3342#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK)
3343#define ASRC_ASRMCRC_BYPASSPOLYC_MASK (0x100000U)
3344#define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT (20U)
3345/*! BYPASSPOLYC - BYPASSPOLYC
3346 * 0b1..Bypass polyphase filtering.
3347 * 0b0..Don't bypass polyphase filtering.
3348 */
3349#define ASRC_ASRMCRC_BYPASSPOLYC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK)
3350#define ASRC_ASRMCRC_BUFSTALLC_MASK (0x200000U)
3351#define ASRC_ASRMCRC_BUFSTALLC_SHIFT (21U)
3352/*! BUFSTALLC - BUFSTALLC
3353 * 0b1..Stall Pair C conversion in case of near empty/full FIFO conditions.
3354 * 0b0..Don't stall Pair C conversion even in case of near empty/full FIFO conditions.
3355 */
3356#define ASRC_ASRMCRC_BUFSTALLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK)
3357#define ASRC_ASRMCRC_EXTTHRSHC_MASK (0x400000U)
3358#define ASRC_ASRMCRC_EXTTHRSHC_SHIFT (22U)
3359/*! EXTTHRSHC - EXTTHRSHC
3360 * 0b1..Use external defined thresholds.
3361 * 0b0..Use default thresholds.
3362 */
3363#define ASRC_ASRMCRC_EXTTHRSHC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK)
3364#define ASRC_ASRMCRC_ZEROBUFC_MASK (0x800000U)
3365#define ASRC_ASRMCRC_ZEROBUFC_SHIFT (23U)
3366/*! ZEROBUFC - ZEROBUFC
3367 * 0b1..Don't zeroize the buffer
3368 * 0b0..Zeroize the buffer
3369 */
3370#define ASRC_ASRMCRC_ZEROBUFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK)
3371/*! @} */
3372
3373/*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */
3374/*! @{ */
3375#define ASRC_ASRFSTC_INFIFO_FILLC_MASK (0x7FU)
3376#define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT (0U)
3377/*! INFIFO_FILLC - INFIFO_FILLC
3378 */
3379#define ASRC_ASRFSTC_INFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK)
3380#define ASRC_ASRFSTC_IAEC_MASK (0x800U)
3381#define ASRC_ASRFSTC_IAEC_SHIFT (11U)
3382/*! IAEC - IAEC
3383 */
3384#define ASRC_ASRFSTC_IAEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK)
3385#define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK (0x7F000U)
3386#define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT (12U)
3387/*! OUTFIFO_FILLC - OUTFIFO_FILLC
3388 */
3389#define ASRC_ASRFSTC_OUTFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK)
3390#define ASRC_ASRFSTC_OAFC_MASK (0x800000U)
3391#define ASRC_ASRFSTC_OAFC_SHIFT (23U)
3392/*! OAFC - OAFC
3393 */
3394#define ASRC_ASRFSTC_OAFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK)
3395/*! @} */
3396
3397/*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */
3398/*! @{ */
3399#define ASRC_ASRMCR1_OW16_MASK (0x1U)
3400#define ASRC_ASRMCR1_OW16_SHIFT (0U)
3401/*! OW16 - OW16
3402 * 0b1..16-bit output data
3403 * 0b0..24-bit output data.
3404 */
3405#define ASRC_ASRMCR1_OW16(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK)
3406#define ASRC_ASRMCR1_OSGN_MASK (0x2U)
3407#define ASRC_ASRMCR1_OSGN_SHIFT (1U)
3408/*! OSGN - OSGN
3409 * 0b1..Sign extension.
3410 * 0b0..No sign extension.
3411 */
3412#define ASRC_ASRMCR1_OSGN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK)
3413#define ASRC_ASRMCR1_OMSB_MASK (0x4U)
3414#define ASRC_ASRMCR1_OMSB_SHIFT (2U)
3415/*! OMSB - OMSB
3416 * 0b1..MSB aligned.
3417 * 0b0..LSB aligned.
3418 */
3419#define ASRC_ASRMCR1_OMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK)
3420#define ASRC_ASRMCR1_IMSB_MASK (0x100U)
3421#define ASRC_ASRMCR1_IMSB_SHIFT (8U)
3422/*! IMSB - IMSB
3423 * 0b1..MSB aligned.
3424 * 0b0..LSB aligned.
3425 */
3426#define ASRC_ASRMCR1_IMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK)
3427#define ASRC_ASRMCR1_IWD_MASK (0xE00U)
3428#define ASRC_ASRMCR1_IWD_SHIFT (9U)
3429/*! IWD - IWD
3430 */
3431#define ASRC_ASRMCR1_IWD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK)
3432/*! @} */
3433
3434/* The count of ASRC_ASRMCR1 */
3435#define ASRC_ASRMCR1_COUNT (3U)
3436
3437
3438/*!
3439 * @}
3440 */ /* end of group ASRC_Register_Masks */
3441
3442
3443/* ASRC - Peripheral instance base addresses */
3444/** Peripheral ADMA__ASRC0 base address */
3445#define ADMA__ASRC0_BASE (0x59000000u)
3446/** Peripheral ADMA__ASRC0 base pointer */
3447#define ADMA__ASRC0 ((ASRC_Type *)ADMA__ASRC0_BASE)
3448/** Peripheral ADMA__ASRC1 base address */
3449#define ADMA__ASRC1_BASE (0x59800000u)
3450/** Peripheral ADMA__ASRC1 base pointer */
3451#define ADMA__ASRC1 ((ASRC_Type *)ADMA__ASRC1_BASE)
3452/** Array initializer of ASRC peripheral base addresses */
3453#define ASRC_BASE_ADDRS { ADMA__ASRC0_BASE, ADMA__ASRC1_BASE }
3454/** Array initializer of ASRC peripheral base pointers */
3455#define ASRC_BASE_PTRS { ADMA__ASRC0, ADMA__ASRC1 }
3456
3457/*!
3458 * @}
3459 */ /* end of group ASRC_Peripheral_Access_Layer */
3460
3461
3462/* ----------------------------------------------------------------------------
3463 -- BCH Peripheral Access Layer
3464 ---------------------------------------------------------------------------- */
3465
3466/*!
3467 * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer
3468 * @{
3469 */
3470
3471/** BCH - Register Layout Typedef */
3472typedef struct {
3473 struct { /* offset: 0x0 */
3474 __IO uint32_t RW; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */
3475 __IO uint32_t SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */
3476 __IO uint32_t CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */
3477 __IO uint32_t TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */
3478 } CTRL;
3479 struct { /* offset: 0x10 */
3480 __I uint32_t RW; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */
3481 __I uint32_t SET; /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */
3482 __I uint32_t CLR; /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */
3483 __I uint32_t TOG; /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */
3484 } STATUS0;
3485 struct { /* offset: 0x20 */
3486 __IO uint32_t RW; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */
3487 __IO uint32_t SET; /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */
3488 __IO uint32_t CLR; /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */
3489 __IO uint32_t TOG; /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */
3490 } MODE;
3491 struct { /* offset: 0x30 */
3492 __IO uint32_t RW; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */
3493 __IO uint32_t SET; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */
3494 __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */
3495 __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */
3496 } ENCODEPTR;
3497 struct { /* offset: 0x40 */
3498 __IO uint32_t RW; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */
3499 __IO uint32_t SET; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */
3500 __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */
3501 __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */
3502 } DATAPTR;
3503 struct { /* offset: 0x50 */
3504 __IO uint32_t RW; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */
3505 __IO uint32_t SET; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */
3506 __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */
3507 __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */
3508 } METAPTR;
3509 uint8_t RESERVED_0[16];
3510 struct { /* offset: 0x70 */
3511 __IO uint32_t RW; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */
3512 __IO uint32_t SET; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */
3513 __IO uint32_t CLR; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */
3514 __IO uint32_t TOG; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */
3515 } LAYOUTSELECT;
3516 struct { /* offset: 0x80 */
3517 __IO uint32_t RW; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */
3518 __IO uint32_t SET; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */
3519 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */
3520 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */
3521 } FLASH0LAYOUT0;
3522 struct { /* offset: 0x90 */
3523 __IO uint32_t RW; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */
3524 __IO uint32_t SET; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */
3525 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */
3526 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */
3527 } FLASH0LAYOUT1;
3528 struct { /* offset: 0xA0 */
3529 __IO uint32_t RW; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */
3530 __IO uint32_t SET; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */
3531 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */
3532 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */
3533 } FLASH1LAYOUT0;
3534 struct { /* offset: 0xB0 */
3535 __IO uint32_t RW; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */
3536 __IO uint32_t SET; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */
3537 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */
3538 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */
3539 } FLASH1LAYOUT1;
3540 struct { /* offset: 0xC0 */
3541 __IO uint32_t RW; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */
3542 __IO uint32_t SET; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */
3543 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */
3544 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */
3545 } FLASH2LAYOUT0;
3546 struct { /* offset: 0xD0 */
3547 __IO uint32_t RW; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */
3548 __IO uint32_t SET; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */
3549 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */
3550 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */
3551 } FLASH2LAYOUT1;
3552 struct { /* offset: 0xE0 */
3553 __IO uint32_t RW; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */
3554 __IO uint32_t SET; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */
3555 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */
3556 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */
3557 } FLASH3LAYOUT0;
3558 struct { /* offset: 0xF0 */
3559 __IO uint32_t RW; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */
3560 __IO uint32_t SET; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */
3561 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */
3562 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */
3563 } FLASH3LAYOUT1;
3564 struct { /* offset: 0x100 */
3565 __IO uint32_t RW; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */
3566 __IO uint32_t SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */
3567 __IO uint32_t CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */
3568 __IO uint32_t TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */
3569 } DEBUG0;
3570 struct { /* offset: 0x110 */
3571 __I uint32_t RW; /**< KES Debug Read Register, offset: 0x110 */
3572 __I uint32_t SET; /**< KES Debug Read Register, offset: 0x114 */
3573 __I uint32_t CLR; /**< KES Debug Read Register, offset: 0x118 */
3574 __I uint32_t TOG; /**< KES Debug Read Register, offset: 0x11C */
3575 } DBGKESREAD;
3576 struct { /* offset: 0x120 */
3577 __I uint32_t RW; /**< Chien Search Debug Read Register, offset: 0x120 */
3578 __I uint32_t SET; /**< Chien Search Debug Read Register, offset: 0x124 */
3579 __I uint32_t CLR; /**< Chien Search Debug Read Register, offset: 0x128 */
3580 __I uint32_t TOG; /**< Chien Search Debug Read Register, offset: 0x12C */
3581 } DBGCSFEREAD;
3582 struct { /* offset: 0x130 */
3583 __I uint32_t RW; /**< Syndrome Generator Debug Read Register, offset: 0x130 */
3584 __I uint32_t SET; /**< Syndrome Generator Debug Read Register, offset: 0x134 */
3585 __I uint32_t CLR; /**< Syndrome Generator Debug Read Register, offset: 0x138 */
3586 __I uint32_t TOG; /**< Syndrome Generator Debug Read Register, offset: 0x13C */
3587 } DBGSYNDGENREAD;
3588 struct { /* offset: 0x140 */
3589 __I uint32_t RW; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */
3590 __I uint32_t SET; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */
3591 __I uint32_t CLR; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */
3592 __I uint32_t TOG; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */
3593 } DBGAHBMREAD;
3594 struct { /* offset: 0x150 */
3595 __I uint32_t RW; /**< Block Name Register, offset: 0x150 */
3596 __I uint32_t SET; /**< Block Name Register, offset: 0x154 */
3597 __I uint32_t CLR; /**< Block Name Register, offset: 0x158 */
3598 __I uint32_t TOG; /**< Block Name Register, offset: 0x15C */
3599 } BLOCKNAME;
3600 struct { /* offset: 0x160 */
3601 __I uint32_t RW; /**< BCH Version Register, offset: 0x160 */
3602 __I uint32_t SET; /**< BCH Version Register, offset: 0x164 */
3603 __I uint32_t CLR; /**< BCH Version Register, offset: 0x168 */
3604 __I uint32_t TOG; /**< BCH Version Register, offset: 0x16C */
3605 } VERSION;
3606 struct { /* offset: 0x170 */
3607 __IO uint32_t RW; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */
3608 __IO uint32_t SET; /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */
3609 __IO uint32_t CLR; /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */
3610 __IO uint32_t TOG; /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */
3611 } DEBUG1;
3612} BCH_Type;
3613
3614/* ----------------------------------------------------------------------------
3615 -- BCH Register Masks
3616 ---------------------------------------------------------------------------- */
3617
3618/*!
3619 * @addtogroup BCH_Register_Masks BCH Register Masks
3620 * @{
3621 */
3622
3623/*! @name CTRL - Hardware BCH ECC Accelerator Control Register */
3624/*! @{ */
3625#define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U)
3626#define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U)
3627/*! COMPLETE_IRQ - COMPLETE_IRQ
3628 */
3629#define BCH_CTRL_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK)
3630#define BCH_CTRL_RSVD0_MASK (0x2U)
3631#define BCH_CTRL_RSVD0_SHIFT (1U)
3632/*! RSVD0 - This field is reserved.
3633 */
3634#define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK)
3635#define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U)
3636#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U)
3637/*! DEBUG_STALL_IRQ - DEBUG_STALL_IRQ
3638 */
3639#define BCH_CTRL_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK)
3640#define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U)
3641#define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U)
3642/*! BM_ERROR_IRQ - BM_ERROR_IRQ
3643 */
3644#define BCH_CTRL_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK)
3645#define BCH_CTRL_RSVD1_MASK (0xF0U)
3646#define BCH_CTRL_RSVD1_SHIFT (4U)
3647/*! RSVD1 - This field is reserved.
3648 */
3649#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK)
3650#define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U)
3651#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U)
3652/*! COMPLETE_IRQ_EN - COMPLETE_IRQ_EN
3653 */
3654#define BCH_CTRL_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK)
3655#define BCH_CTRL_RSVD2_MASK (0x200U)
3656#define BCH_CTRL_RSVD2_SHIFT (9U)
3657/*! RSVD2 - This field is reserved.
3658 */
3659#define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK)
3660#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U)
3661#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U)
3662/*! DEBUG_STALL_IRQ_EN - DEBUG_STALL_IRQ_EN
3663 */
3664#define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK)
3665#define BCH_CTRL_RSVD3_MASK (0xF800U)
3666#define BCH_CTRL_RSVD3_SHIFT (11U)
3667/*! RSVD3 - This field is reserved.
3668 */
3669#define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK)
3670#define BCH_CTRL_M2M_ENABLE_MASK (0x10000U)
3671#define BCH_CTRL_M2M_ENABLE_SHIFT (16U)
3672/*! M2M_ENABLE - M2M_ENABLE
3673 */
3674#define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK)
3675#define BCH_CTRL_M2M_ENCODE_MASK (0x20000U)
3676#define BCH_CTRL_M2M_ENCODE_SHIFT (17U)
3677/*! M2M_ENCODE - M2M_ENCODE
3678 */
3679#define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK)
3680#define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U)
3681#define BCH_CTRL_M2M_LAYOUT_SHIFT (18U)
3682/*! M2M_LAYOUT - M2M_LAYOUT
3683 */
3684#define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK)
3685#define BCH_CTRL_RSVD4_MASK (0x300000U)
3686#define BCH_CTRL_RSVD4_SHIFT (20U)
3687/*! RSVD4 - This field is reserved.
3688 */
3689#define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK)
3690#define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U)
3691#define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U)
3692/*! DEBUGSYNDROME - DEBUGSYNDROME
3693 */
3694#define BCH_CTRL_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK)
3695#define BCH_CTRL_RSVD5_MASK (0x3F800000U)
3696#define BCH_CTRL_RSVD5_SHIFT (23U)
3697/*! RSVD5 - This field is reserved.
3698 */
3699#define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK)
3700#define BCH_CTRL_CLKGATE_MASK (0x40000000U)
3701#define BCH_CTRL_CLKGATE_SHIFT (30U)
3702/*! CLKGATE - CLKGATE
3703 * 0b0..Allow BCH to operate normally.
3704 * 0b1..Do not clock BCH gates in order to minimize power consumption.
3705 */
3706#define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK)
3707#define BCH_CTRL_SFTRST_MASK (0x80000000U)
3708#define BCH_CTRL_SFTRST_SHIFT (31U)
3709/*! SFTRST - SFTRST
3710 * 0b0..Allow BCH to operate normally.
3711 * 0b1..Hold BCH in reset.
3712 */
3713#define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK)
3714/*! @} */
3715
3716/*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */
3717/*! @{ */
3718#define BCH_STATUS0_RSVD0_MASK (0x3U)
3719#define BCH_STATUS0_RSVD0_SHIFT (0U)
3720/*! RSVD0 - This field is reserved.
3721 */
3722#define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK)
3723#define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U)
3724#define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U)
3725/*! UNCORRECTABLE - UNCORRECTABLE
3726 */
3727#define BCH_STATUS0_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK)
3728#define BCH_STATUS0_CORRECTED_MASK (0x8U)
3729#define BCH_STATUS0_CORRECTED_SHIFT (3U)
3730/*! CORRECTED - CORRECTED
3731 */
3732#define BCH_STATUS0_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK)
3733#define BCH_STATUS0_ALLONES_MASK (0x10U)
3734#define BCH_STATUS0_ALLONES_SHIFT (4U)
3735/*! ALLONES - ALLONES
3736 */
3737#define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK)
3738#define BCH_STATUS0_RSVD1_MASK (0xE0U)
3739#define BCH_STATUS0_RSVD1_SHIFT (5U)
3740/*! RSVD1 - This field is reserved.
3741 */
3742#define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK)
3743#define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U)
3744#define BCH_STATUS0_STATUS_BLK0_SHIFT (8U)
3745/*! STATUS_BLK0 - STATUS_BLK0
3746 * 0b00000000..No errors found on block.
3747 * 0b00000001..One error found on block.
3748 * 0b00000010..One errors found on block.
3749 * 0b00000011..One errors found on block.
3750 * 0b00000100..One errors found on block.
3751 * 0b11111110..Block exhibited uncorrectable errors.
3752 * 0b11111111..Page is erased.
3753 */
3754#define BCH_STATUS0_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK)
3755#define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U)
3756#define BCH_STATUS0_COMPLETED_CE_SHIFT (16U)
3757/*! COMPLETED_CE - COMPLETED_CE
3758 */
3759#define BCH_STATUS0_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK)
3760#define BCH_STATUS0_HANDLE_MASK (0xFFF00000U)
3761#define BCH_STATUS0_HANDLE_SHIFT (20U)
3762/*! HANDLE - HANDLE
3763 */
3764#define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK)
3765/*! @} */
3766
3767/*! @name MODE - Hardware ECC Accelerator Mode Register */
3768/*! @{ */
3769#define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU)
3770#define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U)
3771/*! ERASE_THRESHOLD - ERASE_THRESHOLD
3772 */
3773#define BCH_MODE_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK)
3774#define BCH_MODE_RSVD_MASK (0xFFFFFF00U)
3775#define BCH_MODE_RSVD_SHIFT (8U)
3776/*! RSVD - This field is reserved.
3777 */
3778#define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK)
3779/*! @} */
3780
3781/*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */
3782/*! @{ */
3783#define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU)
3784#define BCH_ENCODEPTR_ADDR_SHIFT (0U)
3785/*! ADDR - ADDR
3786 */
3787#define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK)
3788/*! @} */
3789
3790/*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */
3791/*! @{ */
3792#define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU)
3793#define BCH_DATAPTR_ADDR_SHIFT (0U)
3794/*! ADDR - ADDR
3795 */
3796#define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK)
3797/*! @} */
3798
3799/*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */
3800/*! @{ */
3801#define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU)
3802#define BCH_METAPTR_ADDR_SHIFT (0U)
3803/*! ADDR - ADDR
3804 */
3805#define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK)
3806/*! @} */
3807
3808/*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */
3809/*! @{ */
3810#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U)
3811#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U)
3812/*! CS0_SELECT - CS0_SELECT
3813 */
3814#define BCH_LAYOUTSELECT_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK)
3815#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU)
3816#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U)
3817/*! CS1_SELECT - CS1_SELECT
3818 */
3819#define BCH_LAYOUTSELECT_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK)
3820#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U)
3821#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U)
3822/*! CS2_SELECT - CS2_SELECT
3823 */
3824#define BCH_LAYOUTSELECT_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK)
3825#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U)
3826#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U)
3827/*! CS3_SELECT - CS3_SELECT
3828 */
3829#define BCH_LAYOUTSELECT_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK)
3830#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U)
3831#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U)
3832/*! CS4_SELECT - CS4_SELECT
3833 */
3834#define BCH_LAYOUTSELECT_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK)
3835#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U)
3836#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U)
3837/*! CS5_SELECT - CS5_SELECT
3838 */
3839#define BCH_LAYOUTSELECT_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK)
3840#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U)
3841#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U)
3842/*! CS6_SELECT - CS6_SELECT
3843 */
3844#define BCH_LAYOUTSELECT_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK)
3845#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U)
3846#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U)
3847/*! CS7_SELECT - CS7_SELECT
3848 */
3849#define BCH_LAYOUTSELECT_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK)
3850#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U)
3851#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U)
3852/*! CS8_SELECT - CS8_SELECT
3853 */
3854#define BCH_LAYOUTSELECT_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK)
3855#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U)
3856#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U)
3857/*! CS9_SELECT - CS9_SELECT
3858 */
3859#define BCH_LAYOUTSELECT_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK)
3860#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U)
3861#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U)
3862/*! CS10_SELECT - CS10_SELECT
3863 */
3864#define BCH_LAYOUTSELECT_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK)
3865#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U)
3866#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U)
3867/*! CS11_SELECT - CS11_SELECT
3868 */
3869#define BCH_LAYOUTSELECT_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK)
3870#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U)
3871#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U)
3872/*! CS12_SELECT - CS12_SELECT
3873 */
3874#define BCH_LAYOUTSELECT_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK)
3875#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U)
3876#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U)
3877/*! CS13_SELECT - CS13_SELECT
3878 */
3879#define BCH_LAYOUTSELECT_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK)
3880#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U)
3881#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U)
3882/*! CS14_SELECT - CS14_SELECT
3883 */
3884#define BCH_LAYOUTSELECT_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK)
3885#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U)
3886#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U)
3887/*! CS15_SELECT - CS15_SELECT
3888 */
3889#define BCH_LAYOUTSELECT_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK)
3890/*! @} */
3891
3892/*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */
3893/*! @{ */
3894#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
3895#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U)
3896/*! DATA0_SIZE - DATA0_SIZE
3897 */
3898#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK)
3899#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
3900#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
3901/*! GF13_0_GF14_1 - GF13_0_GF14_1
3902 */
3903#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK)
3904#define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF800U)
3905#define BCH_FLASH0LAYOUT0_ECC0_SHIFT (11U)
3906/*! ECC0 - ECC0
3907 * 0b00000..No ECC to be performed
3908 * 0b00001..ECC 2 to be performed
3909 * 0b00010..ECC 4 to be performed
3910 * 0b11110..ECC 60 to be performed
3911 * 0b11111..ECC 62 to be performed
3912 */
3913#define BCH_FLASH0LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK)
3914#define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U)
3915#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U)
3916/*! META_SIZE - META_SIZE
3917 */
3918#define BCH_FLASH0LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK)
3919#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U)
3920#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U)
3921/*! NBLOCKS - NBLOCKS
3922 */
3923#define BCH_FLASH0LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK)
3924/*! @} */
3925
3926/*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */
3927/*! @{ */
3928#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
3929#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U)
3930/*! DATAN_SIZE - DATAN_SIZE
3931 */
3932#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK)
3933#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
3934#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
3935/*! GF13_0_GF14_1 - GF13_0_GF14_1
3936 */
3937#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK)
3938#define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF800U)
3939#define BCH_FLASH0LAYOUT1_ECCN_SHIFT (11U)
3940/*! ECCN - ECCN
3941 * 0b00000..No ECC to be performed
3942 * 0b00001..ECC 2 to be performed
3943 * 0b00010..ECC 4 to be performed
3944 * 0b11110..ECC 60 to be performed
3945 * 0b11111..ECC 62 to be performed
3946 */
3947#define BCH_FLASH0LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK)
3948#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
3949#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U)
3950/*! PAGE_SIZE - PAGE_SIZE
3951 */
3952#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK)
3953/*! @} */
3954
3955/*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */
3956/*! @{ */
3957#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
3958#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U)
3959/*! DATA0_SIZE - DATA0_SIZE
3960 */
3961#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK)
3962#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
3963#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
3964/*! GF13_0_GF14_1 - GF13_0_GF14_1
3965 */
3966#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK)
3967#define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF800U)
3968#define BCH_FLASH1LAYOUT0_ECC0_SHIFT (11U)
3969/*! ECC0 - ECC0
3970 * 0b00000..No ECC to be performed
3971 * 0b00001..ECC 2 to be performed
3972 * 0b00010..ECC 4 to be performed
3973 * 0b11110..ECC 60 to be performed
3974 * 0b11111..ECC 62 to be performed
3975 */
3976#define BCH_FLASH1LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK)
3977#define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U)
3978#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U)
3979/*! META_SIZE - META_SIZE
3980 */
3981#define BCH_FLASH1LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK)
3982#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U)
3983#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U)
3984/*! NBLOCKS - NBLOCKS
3985 */
3986#define BCH_FLASH1LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK)
3987/*! @} */
3988
3989/*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */
3990/*! @{ */
3991#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
3992#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U)
3993/*! DATAN_SIZE - DATAN_SIZE
3994 */
3995#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK)
3996#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
3997#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
3998/*! GF13_0_GF14_1 - GF13_0_GF14_1
3999 */
4000#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK)
4001#define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF800U)
4002#define BCH_FLASH1LAYOUT1_ECCN_SHIFT (11U)
4003/*! ECCN - ECCN
4004 * 0b00000..No ECC to be performed
4005 * 0b00001..ECC 2 to be performed
4006 * 0b00010..ECC 4 to be performed
4007 * 0b11110..ECC 60 to be performed
4008 * 0b11111..ECC 62 to be performed
4009 */
4010#define BCH_FLASH1LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK)
4011#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
4012#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U)
4013/*! PAGE_SIZE - PAGE_SIZE
4014 */
4015#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK)
4016/*! @} */
4017
4018/*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */
4019/*! @{ */
4020#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
4021#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U)
4022/*! DATA0_SIZE - DATA0_SIZE
4023 */
4024#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK)
4025#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
4026#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
4027/*! GF13_0_GF14_1 - GF13_0_GF14_1
4028 */
4029#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK)
4030#define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF800U)
4031#define BCH_FLASH2LAYOUT0_ECC0_SHIFT (11U)
4032/*! ECC0 - ECC0
4033 * 0b00000..No ECC to be performed
4034 * 0b00001..ECC 2 to be performed
4035 * 0b00010..ECC 4 to be performed
4036 * 0b11110..ECC 60 to be performed
4037 * 0b11111..ECC 62 to be performed
4038 */
4039#define BCH_FLASH2LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK)
4040#define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U)
4041#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U)
4042/*! META_SIZE - META_SIZE
4043 */
4044#define BCH_FLASH2LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK)
4045#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U)
4046#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U)
4047/*! NBLOCKS - NBLOCKS
4048 */
4049#define BCH_FLASH2LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK)
4050/*! @} */
4051
4052/*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */
4053/*! @{ */
4054#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
4055#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U)
4056/*! DATAN_SIZE - DATAN_SIZE
4057 */
4058#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK)
4059#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
4060#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
4061/*! GF13_0_GF14_1 - GF13_0_GF14_1
4062 */
4063#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK)
4064#define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF800U)
4065#define BCH_FLASH2LAYOUT1_ECCN_SHIFT (11U)
4066/*! ECCN - ECCN
4067 * 0b00000..No ECC to be performed
4068 * 0b00001..ECC 2 to be performed
4069 * 0b00010..ECC 4 to be performed
4070 * 0b11110..ECC 60 to be performed
4071 * 0b11111..ECC 62 to be performed
4072 */
4073#define BCH_FLASH2LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK)
4074#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
4075#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U)
4076/*! PAGE_SIZE - PAGE_SIZE
4077 */
4078#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK)
4079/*! @} */
4080
4081/*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */
4082/*! @{ */
4083#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
4084#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U)
4085/*! DATA0_SIZE - DATA0_SIZE
4086 */
4087#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK)
4088#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
4089#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
4090/*! GF13_0_GF14_1 - GF13_0_GF14_1
4091 */
4092#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK)
4093#define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF800U)
4094#define BCH_FLASH3LAYOUT0_ECC0_SHIFT (11U)
4095/*! ECC0 - ECC0
4096 * 0b00000..No ECC to be performed
4097 * 0b00001..ECC 2 to be performed
4098 * 0b00010..ECC 4 to be performed
4099 * 0b11110..ECC 60 to be performed
4100 * 0b11111..ECC 62 to be performed
4101 */
4102#define BCH_FLASH3LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK)
4103#define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U)
4104#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U)
4105/*! META_SIZE - META_SIZE
4106 */
4107#define BCH_FLASH3LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK)
4108#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U)
4109#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U)
4110/*! NBLOCKS - NBLOCKS
4111 */
4112#define BCH_FLASH3LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK)
4113/*! @} */
4114
4115/*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */
4116/*! @{ */
4117#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
4118#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U)
4119/*! DATAN_SIZE - DATAN_SIZE
4120 */
4121#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK)
4122#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
4123#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
4124/*! GF13_0_GF14_1 - GF13_0_GF14_1
4125 */
4126#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK)
4127#define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF800U)
4128#define BCH_FLASH3LAYOUT1_ECCN_SHIFT (11U)
4129/*! ECCN - ECCN
4130 * 0b00000..No ECC to be performed
4131 * 0b00001..ECC 2 to be performed
4132 * 0b00010..ECC 4 to be performed
4133 * 0b11110..ECC 60 to be performed
4134 * 0b11111..ECC 62 to be performed
4135 */
4136#define BCH_FLASH3LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK)
4137#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
4138#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U)
4139/*! PAGE_SIZE - PAGE_SIZE
4140 */
4141#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK)
4142/*! @} */
4143
4144/*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */
4145/*! @{ */
4146#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU)
4147#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U)
4148/*! DEBUG_REG_SELECT - DEBUG_REG_SELECT
4149 */
4150#define BCH_DEBUG0_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK)
4151#define BCH_DEBUG0_RSVD0_MASK (0xC0U)
4152#define BCH_DEBUG0_RSVD0_SHIFT (6U)
4153/*! RSVD0 - This field is reserved.