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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/MIMX8DX4_cm4.h144413
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/MIMX8DX4_cm4_features.h587
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/drivers/driver_reset.cmake14
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/drivers/fsl_clock.c389
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/drivers/fsl_clock.h526
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/drivers/fsl_memory.h108
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/fsl_device_registers.h35
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/gcc/MIMX8DX4xxxxx_cm4_ddr_ram.ld244
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/gcc/MIMX8DX4xxxxx_cm4_ram.ld223
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/gcc/startup_MIMX8DX4_cm4.S3044
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/project_template/board.c213
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/project_template/board.h56
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/project_template/clock_config.c73
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/project_template/clock_config.h29
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/project_template/peripherals.c24
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/project_template/peripherals.h25
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/project_template/pin_mux.c58
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/project_template/pin_mux.h47
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/main/imx8qx_pads.h225
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/main/ipc.h92
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/main/ipc_imx8qx.c159
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/main/rpc.h175
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/main/scfw.h60
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/main/types.h918
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/irq/irq_api.h200
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/irq/irq_rpc.h72
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/irq/irq_rpc_clnt.c105
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/misc/misc_api.h489
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/misc/misc_rpc.h92
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/misc/misc_rpc_clnt.c530
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/pad/pad_api.h596
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/pad/pad_rpc.h86
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/pad/pad_rpc_clnt.c512
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/pm/pm_api.h896
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/pm/pm_rpc.h99
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/pm/pm_rpc_clnt.c683
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/rm/rm_api.h888
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/rm/rm_rpc.h103
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/rm/rm_rpc_clnt.c775
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/seco/seco_api.h803
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/seco/seco_rpc.h97
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/seco/seco_rpc_clnt.c659
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/timer/timer_api.h413
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/timer/timer_rpc.h89
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/timer/timer_rpc_clnt.c479
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/system_MIMX8DX4_cm4.c172
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/system_MIMX8DX4_cm4.h124
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/template/RTE_Device.h212
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/utilities/fsl_notifier.c209
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/utilities/fsl_notifier.h237
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/utilities/fsl_shell.c1085
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/utilities/fsl_shell.h292
52 files changed, 162734 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/MIMX8DX4_cm4.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/MIMX8DX4_cm4.h
new file mode 100644
index 000000000..b90585083
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8DX4/MIMX8DX4_cm4.h
@@ -0,0 +1,144413 @@
1/*
2** ###################################################################
3** Processor: MIMX8DX4AVLFZ
4** Compilers: GNU C Compiler
5** IAR ANSI C/C++ Compiler for ARM
6** Keil ARM C/C++ Compiler
7**
8** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
9** Version: rev. 4.0, 2020-06-19
10** Build: b200825
11**
12** Abstract:
13** CMSIS Peripheral Access Layer for MIMX8DX4_cm4
14**
15** Copyright 1997-2016 Freescale Semiconductor, Inc.
16** Copyright 2016-2020 NXP
17** All rights reserved.
18**
19** SPDX-License-Identifier: BSD-3-Clause
20**
21** http: www.nxp.com
22** mail: [email protected]
23**
24** Revisions:
25** - rev. 1.0 (2016-06-02)
26** Initial version.
27** - rev. 2.0 (2017-08-23)
28** RevA Header EAR
29** - rev. 3.0 (2018-08-22)
30** RevB Header EAR
31** - rev. 4.0 (2020-06-19)
32** RevC Header RFP
33**
34** ###################################################################
35*/
36
37/*!
38 * @file MIMX8DX4_cm4.h
39 * @version 4.0
40 * @date 2020-06-19
41 * @brief CMSIS Peripheral Access Layer for MIMX8DX4_cm4
42 *
43 * CMSIS Peripheral Access Layer for MIMX8DX4_cm4
44 */
45
46#ifndef _MIMX8DX4_CM4_H_
47#define _MIMX8DX4_CM4_H_ /**< Symbol preventing repeated inclusion */
48
49/** Memory map major version (memory maps with equal major version number are
50 * compatible) */
51#define MCU_MEM_MAP_VERSION 0x0400U
52/** Memory map minor version */
53#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
54
55
56/* ----------------------------------------------------------------------------
57 -- Interrupt vector numbers
58 ---------------------------------------------------------------------------- */
59
60/*!
61 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
62 * @{
63 */
64
65/** Interrupt Number Definitions */
66#define NUMBER_OF_INT_VECTORS 611 /**< Number of interrupts in the Vector table */
67
68typedef enum IRQn {
69 /* Auxiliary constants */
70 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
71
72 /* Core interrupts */
73 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
74 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
75 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
76 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
77 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
78 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
79 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
80 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
81 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
82
83 /* Device specific interrupts */
84 Reserved16_IRQn = 0, /**< Reserved */
85 Reserved17_IRQn = 1, /**< Reserved */
86 Reserved18_IRQn = 2, /**< Reserved */
87 Reserved19_IRQn = 3, /**< Reserved */
88 Reserved20_IRQn = 4, /**< Reserved */
89 M4_MCM_IRQn = 5, /**< MCM IRQ */
90 Reserved22_IRQn = 6, /**< Reserved */
91 Reserved23_IRQn = 7, /**< Reserved */
92 Reserved24_IRQn = 8, /**< Reserved */
93 Reserved25_IRQn = 9, /**< Reserved */
94 Reserved26_IRQn = 10, /**< Reserved */
95 Reserved27_IRQn = 11, /**< Reserved */
96 Reserved28_IRQn = 12, /**< Reserved */
97 Reserved29_IRQn = 13, /**< Reserved */
98 Reserved30_IRQn = 14, /**< Reserved */
99 Reserved31_IRQn = 15, /**< Reserved */
100 Reserved32_IRQn = 16, /**< Reserved */
101 Reserved33_IRQn = 17, /**< Reserved */
102 Reserved34_IRQn = 18, /**< Reserved */
103 M4_TPM_IRQn = 19, /**< Timer PWM Module */
104 Reserved36_IRQn = 20, /**< Reserved */
105 Reserved37_IRQn = 21, /**< Reserved */
106 M4_LPIT_IRQn = 22, /**< Low-Power Periodic Interrupt Timer */
107 Reserved39_IRQn = 23, /**< Reserved */
108 Reserved40_IRQn = 24, /**< Reserved */
109 M4_LPUART_IRQn = 25, /**< Low Power UART */
110 Reserved42_IRQn = 26, /**< Reserved */
111 M4_LPI2C_IRQn = 27, /**< Low-Power I2C - Logical OR of master and slave interrupts */
112 Reserved44_IRQn = 28, /**< Reserved */
113 M4_MU0_B0_IRQn = 29, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 0, Logical OR of all general-purpose, TX, and RX interrupts */
114 Reserved46_IRQn = 30, /**< Reserved */
115 Reserved47_IRQn = 31, /**< Reserved */
116 IRQSTEER_0_IRQn = 32, /**< External interrupt 0 */
117 IRQSTEER_1_IRQn = 33, /**< External interrupt 1 */
118 IRQSTEER_2_IRQn = 34, /**< External interrupt 2 */
119 IRQSTEER_3_IRQn = 35, /**< External interrupt 3 */
120 IRQSTEER_4_IRQn = 36, /**< External interrupt 4 */
121 IRQSTEER_5_IRQn = 37, /**< External interrupt 5 */
122 IRQSTEER_6_IRQn = 38, /**< External interrupt 6 */
123 IRQSTEER_7_IRQn = 39, /**< External interrupt 7 */
124 Reserved56_IRQn = 40, /**< Reserved */
125 Reserved57_IRQn = 41, /**< Reserved */
126 Reserved58_IRQn = 42, /**< Reserved */
127 Reserved59_IRQn = 43, /**< Reserved */
128 M4_MU0_B1_IRQn = 44, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 1, Logical OR of all general-purpose, TX, and RX interrupts */
129 M4_MU0_B2_IRQn = 45, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 2, Logical OR of all general-purpose, TX, and RX interrupts */
130 M4_MU0_B3_IRQn = 46, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 3, Logical OR of all general-purpose, TX, and RX interrupts */
131 Reserved63_IRQn = 47, /**< Reserved */
132 Reserved64_IRQn = 48, /**< Reserved */
133 M4_MU1_A_IRQn = 49, /**< Messaging Unit 1 (IPC with System Controller) - Side A (MCU), Logical OR of all general-purpose, TX, and RX interrupts */
134 M4_SW_IRQn = 50, /**< Software interrupt (asserted/cleared via NVIC registers, INTISR[50] input tied low) */
135 A35_NINTERRIRQ_IRQn = 83, /**< Shared Int Source nINTERRIRQ from A35 Sub-System */
136 A35_NEXTERRIRQ_IRQn = 84, /**< Shared Int Source nEXTERRIRQ from A35 Sub-System */
137 M4_INT_OUT0_IRQn = 99, /**< Shared Int Source INT_OUT[0] from M4 Sub-System */
138 M4_INT_OUT1_IRQn = 100, /**< Shared Int Source INT_OUT[1] from M4 Sub-System */
139 M4_INT_OUT2_IRQn = 101, /**< Shared Int Source INT_OUT[2] from M4 Sub-System */
140 M4_INT_OUT3_IRQn = 102, /**< Shared Int Source INT_OUT[3] from M4 Sub-System */
141 M4_INT_OUT4_IRQn = 103, /**< Shared Int Source INT_OUT[4] from M4 Sub-System */
142 M4_INT_OUT5_IRQn = 104, /**< Shared Int Source INT_OUT[5] from M4 Sub-System */
143 M4_INT_OUT6_IRQn = 105, /**< Shared Int Source INT_OUT[6] from M4 Sub-System */
144 M4_INT_OUT7_IRQn = 106, /**< Shared Int Source INT_OUT[7] from M4 Sub-System */
145 DISPLAY0_INT_OUT0_IRQn = 123, /**< Shared Int Source INT_OUT[0] from Display0 Sub-System */
146 DISPLAY0_INT_OUT1_IRQn = 124, /**< Shared Int Source INT_OUT[1] from Display0 Sub-System */
147 DISPLAY0_INT_OUT2_IRQn = 125, /**< Shared Int Source INT_OUT[2] from Display0 Sub-System */
148 DISPLAY0_INT_OUT3_IRQn = 126, /**< Shared Int Source INT_OUT[3] from Display0 Sub-System */
149 DISPLAY0_INT_OUT4_IRQn = 127, /**< Shared Int Source INT_OUT[4] from Display0 Sub-System */
150 DISPLAY0_INT_OUT5_IRQn = 128, /**< Shared Int Source INT_OUT[5] from Display0 Sub-System */
151 DISPLAY0_INT_OUT6_IRQn = 129, /**< Shared Int Source INT_OUT[6] from Display0 Sub-System */
152 DISPLAY0_INT_OUT7_IRQn = 130, /**< Shared Int Source INT_OUT[7] from Display0 Sub-System */
153 DISPLAY0_RESERVED_IRQn = 131, /**< Shared Int Source Reserved from Display0 Sub-System */
154 DISPLAY0_INT_OUT9_IRQn = 132, /**< Shared Int Source INT_OUT[9] from Display0 Sub-System */
155 DISPLAY0_INT_OUT10_IRQn = 133, /**< Shared Int Source INT_OUT[10] from Display0 Sub-System */
156 DISPLAY0_INT_OUT11_IRQn = 134, /**< Shared Int Source INT_OUT[11] from Display0 Sub-System */
157 DISPLAY0_INT_OUT12_IRQn = 135, /**< Shared Int Source INT_OUT[12] from Display0 Sub-System */
158 MIPI_DSI0_INT_OUT_IRQn = 142, /**< Shared Int Source INT_OUT from MIPI_DSI0 Sub-System */
159 MIPI_DSI1_INT_OUT_IRQn = 143, /**< Shared Int Source INT_OUT from MIPI_DSI1 Sub-System */
160 LCD_MOD_INT_IRQn = 145, /**< Shared Int Source INT_OUT from ADMA Sub-System */
161 LCD_PWM_INT_IRQn = 146, /**< Shared Int Source INT_OUT from ADMA Sub-System */
162 GPU0_XAQ2_INTR_IRQn = 147, /**< Shared Int Source xaq2_intr from GPU0 Sub-System */
163 ADMA_EDMA2_INT_IRQn = 149, /**< Shared Int Source eDMA2_INT from ADMA Sub-System */
164 ADMA_EDMA2_ERR_INT_IRQn = 150, /**< Shared Int Source eDMA2_ERR_INT from ADMA Sub-System */
165 ADMA_EDMA3_INT_IRQn = 151, /**< Shared Int Source eDMA3_INT from ADMA Sub-System */
166 ADMA_EDMA3_ERR_INT_IRQn = 152, /**< Shared Int Source eDMA3_ERR_INT from ADMA Sub-System */
167 LSIO_GPT0_INT_IRQn = 163, /**< Shared Int Source GPT0_INT from LSIO Sub-System */
168 LSIO_GPT1_INT_IRQn = 164, /**< Shared Int Source GPT1_INT from LSIO Sub-System */
169 LSIO_GPT2_INT_IRQn = 165, /**< Shared Int Source GPT2_INT from LSIO Sub-System */
170 LSIO_GPT3_INT_IRQn = 166, /**< Shared Int Source GPT3_INT from LSIO Sub-System */
171 LSIO_GPT4_INT_IRQn = 167, /**< Shared Int Source GPT4_INT from LSIO Sub-System */
172 LSIO_KPP_INT_IRQn = 168, /**< Shared Int Source KPP_INT from LSIO Sub-System */
173 LSIO_OCTASPI0_INT_IRQn = 175, /**< Shared Int Source OctaSPI0_INT from LSIO Sub-System */
174 LSIO_OCTASPI1_INT_IRQn = 176, /**< Shared Int Source OctaSPI1_INT from LSIO Sub-System */
175 LSIO_PWM0_INT_IRQn = 177, /**< Shared Int Source PWM0_INT from LSIO Sub-System */
176 LSIO_PWM1_INT_IRQn = 178, /**< Shared Int Source PWM1_INT from LSIO Sub-System */
177 LSIO_PWM2_INT_IRQn = 179, /**< Shared Int Source PWM2_INT from LSIO Sub-System */
178 LSIO_PWM3_INT_IRQn = 180, /**< Shared Int Source PWM3_INT from LSIO Sub-System */
179 LSIO_PWM4_INT_IRQn = 181, /**< Shared Int Source PWM4_INT from LSIO Sub-System */
180 LSIO_PWM5_INT_IRQn = 182, /**< Shared Int Source PWM5_INT from LSIO Sub-System */
181 LSIO_PWM6_INT_IRQn = 183, /**< Shared Int Source PWM6_INT from LSIO Sub-System */
182 LSIO_PWM7_INT_IRQn = 184, /**< Shared Int Source PWM7_INT from LSIO Sub-System */
183 HSIO_PCIEB_MSI_CTRL_INT_IRQn = 185, /**< Shared Int Source PCIeB_MSI_CTRL_INT from HSIO Sub-System */
184 HSIO_PCIEB_CLK_REQ_INT_IRQn = 186, /**< Shared Int Source PCIeB_CLK_REQ_INT from HSIO Sub-System */
185 HSIO_PCIEB_DMA_INT_IRQn = 187, /**< Shared Int Source PCIeB_DMA_INT from HSIO Sub-System */
186 HSIO_PCIEB_INT_D_IRQn = 188, /**< Shared Int Source PCIeB_INT_D from HSIO Sub-System */
187 HSIO_PCIEB_INT_C_IRQn = 189, /**< Shared Int Source PCIeB_INT_C from HSIO Sub-System */
188 HSIO_PCIEB_INT_B_IRQn = 190, /**< Shared Int Source PCIeB_INT_B from HSIO Sub-System */
189 HSIO_PCIEB_INT_A_IRQn = 191, /**< Shared Int Source PCIeB_INT_A from HSIO Sub-System */
190 HSIO_PCIEB_SMLH_REQ_RST_IRQn = 192, /**< Shared Int Source PCIeB_SMLH_REQ_RST from HSIO Sub-System */
191 HSIO_PCIEB_GPIO_WAKEUP0_IRQn = 193, /**< Shared Int Source PCIeB_GPIO_WAKEUP[0] from HSIO Sub-System */
192 HSIO_PCIEB_GPIO_WAKEUP1_IRQn = 194, /**< Shared Int Source PCIeB_GPIO_WAKEUP[1] from HSIO Sub-System */
193 SCU_INT_OUT0_IRQn = 195, /**< Shared Int Source INT_OUT[0] from SCU Sub-System */
194 SCU_INT_OUT1_IRQn = 196, /**< Shared Int Source INT_OUT[1] from SCU Sub-System */
195 SCU_INT_OUT2_IRQn = 197, /**< Shared Int Source INT_OUT[2] from SCU Sub-System */
196 SCU_INT_OUT3_IRQn = 198, /**< Shared Int Source INT_OUT[3] from SCU Sub-System */
197 SCU_INT_OUT4_IRQn = 199, /**< Shared Int Source INT_OUT[4] from SCU Sub-System */
198 SCU_INT_OUT5_IRQn = 200, /**< Shared Int Source INT_OUT[5] from SCU Sub-System */
199 SCU_INT_OUT6_IRQn = 201, /**< Shared Int Source INT_OUT[6] from SCU Sub-System */
200 SCU_INT_OUT7_IRQn = 202, /**< Shared Int Source INT_OUT[7] from SCU Sub-System */
201 SCU_SYS_COUNT_INT0_IRQn = 203, /**< Shared Int Source SYS_COUNT_INT0 from SCU Sub-System */
202 SCU_SYS_COUNT_INT1_IRQn = 204, /**< Shared Int Source SYS_COUNT_INT1 from SCU Sub-System */
203 SCU_SYS_COUNT_INT2_IRQn = 205, /**< Shared Int Source SYS_COUNT_INT2 from SCU Sub-System */
204 SCU_SYS_COUNT_INT3_IRQn = 206, /**< Shared Int Source SYS_COUNT_INT3 from SCU Sub-System */
205 DRC_ECC_CORRECT_INT_IRQn = 211, /**< Shared Int Source ECC_CORRECT_INT from DRC Sub-System */
206 DRC_ECC_NCORRECT_INT_IRQn = 212, /**< Shared Int Source ECC_NCORRECT_INT from DRC Sub-System */
207 DRC_SBR_DONE_INT_IRQn = 213, /**< Shared Int Source SBR_DONE_INT from DRC Sub-System */
208 DRC_PERF_CNT_INT_IRQn = 214, /**< Shared Int Source PERF_CNT_INT from DRC Sub-System */
209 LSIO_GPIO_INT0_IRQn = 219, /**< Shared Int Source GPIO_INT[0] from LSIO Sub-System */
210 LSIO_GPIO_INT1_IRQn = 220, /**< Shared Int Source GPIO_INT[1] from LSIO Sub-System */
211 LSIO_GPIO_INT2_IRQn = 221, /**< Shared Int Source GPIO_INT[2] from LSIO Sub-System */
212 LSIO_GPIO_INT3_IRQn = 222, /**< Shared Int Source GPIO_INT[3] from LSIO Sub-System */
213 LSIO_GPIO_INT4_IRQn = 223, /**< Shared Int Source GPIO_INT[4] from LSIO Sub-System */
214 LSIO_GPIO_INT5_IRQn = 224, /**< Shared Int Source GPIO_INT[5] from LSIO Sub-System */
215 LSIO_GPIO_INT6_IRQn = 225, /**< Shared Int Source GPIO_INT[6] from LSIO Sub-System */
216 LSIO_GPIO_INT7_IRQn = 226, /**< Shared Int Source GPIO_INT[7] from LSIO Sub-System */
217 LSIO_MU0_INT_IRQn = 259, /**< Shared Int Source MU0_INT from LSIO Sub-System */
218 LSIO_MU1_INT_IRQn = 260, /**< Shared Int Source MU1_INT from LSIO Sub-System */
219 LSIO_MU2_INT_IRQn = 261, /**< Shared Int Source MU2_INT from LSIO Sub-System */
220 LSIO_MU3_INT_IRQn = 262, /**< Shared Int Source MU3_INT from LSIO Sub-System */
221 LSIO_MU4_INT_IRQn = 263, /**< Shared Int Source MU4_INT from LSIO Sub-System */
222 LSIO_MU5_INT_A_IRQn = 267, /**< Shared Int Source MU5_INT_A from LSIO Sub-System */
223 LSIO_MU6_INT_A_IRQn = 268, /**< Shared Int Source MU6_INT_A from LSIO Sub-System */
224 LSIO_MU7_INT_A_IRQn = 269, /**< Shared Int Source MU7_INT_A from LSIO Sub-System */
225 LSIO_MU8_INT_A_IRQn = 270, /**< Shared Int Source MU8_INT_A from LSIO Sub-System */
226 LSIO_MU9_INT_A_IRQn = 271, /**< Shared Int Source MU9_INT_A from LSIO Sub-System */
227 LSIO_MU10_INT_A_IRQn = 272, /**< Shared Int Source MU10_INT_A from LSIO Sub-System */
228 LSIO_MU11_INT_A_IRQn = 273, /**< Shared Int Source MU11_INT_A from LSIO Sub-System */
229 LSIO_MU12_INT_A_IRQn = 274, /**< Shared Int Source MU12_INT_A from LSIO Sub-System */
230 LSIO_MU13_INT_A_IRQn = 275, /**< Shared Int Source MU13_INT_A from LSIO Sub-System */
231 LSIO_MU5_INT_B_IRQn = 283, /**< Shared Int Source MU5_INT_B from LSIO Sub-System */
232 LSIO_MU6_INT_B_IRQn = 284, /**< Shared Int Source MU6_INT_B from LSIO Sub-System */
233 LSIO_MU7_INT_B_IRQn = 285, /**< Shared Int Source MU7_INT_B from LSIO Sub-System */
234 LSIO_MU8_INT_B_IRQn = 286, /**< Shared Int Source MU8_INT_B from LSIO Sub-System */
235 LSIO_MU9_INT_B_IRQn = 287, /**< Shared Int Source MU9_INT_B from LSIO Sub-System */
236 LSIO_MU10_INT_B_IRQn = 288, /**< Shared Int Source MU10_INT_B from LSIO Sub-System */
237 LSIO_MU11_INT_B_IRQn = 289, /**< Shared Int Source MU11_INT_B from LSIO Sub-System */
238 LSIO_MU12_INT_B_IRQn = 290, /**< Shared Int Source MU12_INT_B from LSIO Sub-System */
239 LSIO_MU13_INT_B_IRQn = 291, /**< Shared Int Source MU13_INT_B from LSIO Sub-System */
240 ADMA_SPI0_INT_IRQn = 299, /**< Shared Int Source SPI0_INT from ADMA Sub-System */
241 ADMA_SPI1_INT_IRQn = 300, /**< Shared Int Source SPI1_INT from ADMA Sub-System */
242 ADMA_SPI2_INT_IRQn = 301, /**< Shared Int Source SPI2_INT from ADMA Sub-System */
243 ADMA_SPI3_INT_IRQn = 302, /**< Shared Int Source SPI3_INT from ADMA Sub-System */
244 ADMA_I2C0_INT_IRQn = 303, /**< Shared Int Source I2C0_INT from ADMA Sub-System */
245 ADMA_I2C1_INT_IRQn = 304, /**< Shared Int Source I2C1_INT from ADMA Sub-System */
246 ADMA_I2C2_INT_IRQn = 305, /**< Shared Int Source I2C2_INT from ADMA Sub-System */
247 ADMA_I2C3_INT_IRQn = 306, /**< Shared Int Source I2C3_INT from ADMA Sub-System */
248 ADMA_UART0_INT_IRQn = 308, /**< Shared Int Source UART0_INT from ADMA Sub-System */
249 ADMA_UART1_INT_IRQn = 309, /**< Shared Int Source UART1_INT from ADMA Sub-System */
250 ADMA_UART2_INT_IRQn = 310, /**< Shared Int Source UART2_INT from ADMA Sub-System */
251 ADMA_UART3_INT_IRQn = 311, /**< Shared Int Source UART3_INT from ADMA Sub-System */
252 CONNECTIVITY_USDHC0_INT_IRQn = 315, /**< Shared Int Source uSDHC0_INT from Connectivity Sub-System */
253 CONNECTIVITY_USDHC1_INT_IRQn = 316, /**< Shared Int Source uSDHC1_INT from Connectivity Sub-System */
254 CONNECTIVITY_USDHC2_INT_IRQn = 317, /**< Shared Int Source uSDHC2_INT from Connectivity Sub-System */
255 ADMA_FLEXCAN0_INT_IRQn = 318, /**< Shared Int Source FlexCAN0_INT from ADMA Sub-System */
256 ADMA_FLEXCAN1_INT_IRQn = 319, /**< Shared Int Source FlexCAN1_INT from ADMA Sub-System */
257 ADMA_FLEXCAN2_INT_IRQn = 320, /**< Shared Int Source FlexCAN2_INT from ADMA Sub-System */
258 ADMA_FTM0_INT_IRQn = 321, /**< Shared Int Source FTM0_INT from ADMA Sub-System */
259 ADMA_FTM1_INT_IRQn = 322, /**< Shared Int Source FTM1_INT from ADMA Sub-System */
260 ADMA_ADC0_INT_IRQn = 323, /**< Shared Int Source ADC0_INT from ADMA Sub-System */
261 ADMA_EXTERNAL_DMA_INT_0_IRQn = 325, /**< Shared Int Source EXTERNAL_DMA_INT_0 from ADMA Sub-System */
262 ADMA_EXTERNAL_DMA_INT_1_IRQn = 326, /**< Shared Int Source EXTERNAL_DMA_INT_1 from ADMA Sub-System */
263 ADMA_EXTERNAL_DMA_INT_2_IRQn = 327, /**< Shared Int Source EXTERNAL_DMA_INT_2 from ADMA Sub-System */
264 ADMA_EXTERNAL_DMA_INT_3_IRQn = 328, /**< Shared Int Source EXTERNAL_DMA_INT_3 from ADMA Sub-System */
265 ADMA_EXTERNAL_DMA_INT_4_IRQn = 329, /**< Shared Int Source EXTERNAL_DMA_INT_4 from ADMA Sub-System */
266 ADMA_EXTERNAL_DMA_INT_5_IRQn = 330, /**< Shared Int Source EXTERNAL_DMA_INT_5 from ADMA Sub-System */
267 CONNECTIVITY_ENET0_FRAME1_INT_IRQn = 339, /**< Shared Int Source ENET0_FRAME1_INT from Connectivity Sub-System */
268 CONNECTIVITY_ENET0_FRAME2_INT_IRQn = 340, /**< Shared Int Source ENET0_FRAME2_INT from Connectivity Sub-System */
269 CONNECTIVITY_ENET0_FRAME0_EVENT_INT_IRQn = 341, /**< Shared Int Source ENET0_FRAME0_EVENT_INT from Connectivity Sub-System */
270 CONNECTIVITY_ENET0_TIMER_INT_IRQn = 342, /**< Shared Int Source ENET0_TIMER_INT from Connectivity Sub-System */
271 CONNECTIVITY_ENET1_FRAME1_INT_IRQn = 343, /**< Shared Int Source ENET1_FRAME1_INT from Connectivity Sub-System */
272 CONNECTIVITY_ENET1_FRAME2_INT_IRQn = 344, /**< Shared Int Source ENET1_FRAME2_INT from Connectivity Sub-System */
273 CONNECTIVITY_ENET1_FRAME0_EVENT_INT_IRQn = 345, /**< Shared Int Source ENET1_FRAME0_EVENT_INT from Connectivity Sub-System */
274 CONNECTIVITY_ENET1_TIMER_INT_IRQn = 346, /**< Shared Int Source ENET1_TIMER_INT from Connectivity Sub-System */
275 CONNECTIVITY_DTCP_INT_IRQn = 347, /**< Shared Int Source DTCP_INT from Connectivity Sub-System */
276 CONNECTIVITY_MLB_INT_IRQn = 348, /**< Shared Int Source MLB_INT from Connectivity Sub-System */
277 CONNECTIVITY_MLB_AHB_INT_IRQn = 349, /**< Shared Int Source MLB_AHB_INT from Connectivity Sub-System */
278 CONNECTIVITY_USB_OTG_INT_IRQn = 350, /**< Shared Int Source USB_OTG_INT from Connectivity Sub-System */
279 CONNECTIVITY_USB_HOST_INT_IRQn = 351, /**< Shared Int Source USB_HOST_INT from Connectivity Sub-System */
280 CONNECTIVITY_UTMI_INT_IRQn = 352, /**< Shared Int Source UTMI_INT from Connectivity Sub-System */
281 CONNECTIVITY_WAKEUP_INT_IRQn = 353, /**< Shared Int Source WAKEUP_INT from Connectivity Sub-System */
282 CONNECTIVITY_USB3_INT_IRQn = 354, /**< Shared Int Source USB3_INT from Connectivity Sub-System */
283 CONNECTIVITY_ND_FLASH_BCH_INT_IRQn = 355, /**< Shared Int Source ND_FLASH_BCH_INT from Connectivity Sub-System */
284 CONNECTIVITY_ND_FLASH_GPMI_INT_IRQn = 356, /**< Shared Int Source ND_FLASH_GPMI_INT from Connectivity Sub-System */
285 CONNECTIVITY_APBHDMA_IRQn = 357, /**< Shared Int Source APBHDMA from Connectivity Sub-System */
286 CONNECTIVITY_DMA_INT_IRQn = 358, /**< Shared Int Source DMA_INT from Connectivity Sub-System */
287 CONNECTIVITY_DMA_ERR_INT_IRQn = 359, /**< Shared Int Source DMA_ERR_INT from Connectivity Sub-System */
288 IMAGING_MSI_INT_IRQn = 371, /**< Shared Int Source MSI_INT from Imaging Sub-System */
289 IMAGING_PDMA_STREAM0_INT_IRQn = 380, /**< Shared Int Source PDMA_STREAM0_INT from Imaging Sub-System */
290 IMAGING_PDMA_STREAM1_INT_IRQn = 381, /**< Shared Int Source PDMA_STREAM1_INT from Imaging Sub-System */
291 IMAGING_PDMA_STREAM2_INT_IRQn = 382, /**< Shared Int Source PDMA_STREAM2_INT from Imaging Sub-System */
292 IMAGING_PDMA_STREAM3_INT_IRQn = 383, /**< Shared Int Source PDMA_STREAM3_INT from Imaging Sub-System */
293 IMAGING_PDMA_STREAM4_INT_IRQn = 384, /**< Shared Int Source PDMA_STREAM4_INT from Imaging Sub-System */
294 IMAGING_PDMA_STREAM5_INT_IRQn = 385, /**< Shared Int Source PDMA_STREAM5_INT from Imaging Sub-System */
295 IMAGING_PDMA_STREAM6_INT_IRQn = 386, /**< Shared Int Source PDMA_STREAM6_INT from Imaging Sub-System */
296 IMAGING_PDMA_STREAM7_INT_IRQn = 387, /**< Shared Int Source PDMA_STREAM7_INT from Imaging Sub-System */
297 IMAGING_MJPEG_ENC0_INT_IRQn = 388, /**< Shared Int Source MJPEG_ENC0_INT from Imaging Sub-System */
298 IMAGING_MJPEG_ENC1_INT_IRQn = 389, /**< Shared Int Source MJPEG_ENC1_INT from Imaging Sub-System */
299 IMAGING_MJPEG_ENC2_INT_IRQn = 390, /**< Shared Int Source MJPEG_ENC2_INT from Imaging Sub-System */
300 IMAGING_MJPEG_ENC3_INT_IRQn = 391, /**< Shared Int Source MJPEG_ENC3_INT from Imaging Sub-System */
301 IMAGING_MJPEG_DEC0_INT_IRQn = 392, /**< Shared Int Source MJPEG_DEC0_INT from Imaging Sub-System */
302 IMAGING_MJPEG_DEC1_INT_IRQn = 393, /**< Shared Int Source MJPEG_DEC1_INT from Imaging Sub-System */
303 IMAGING_MJPEG_DEC2_INT_IRQn = 394, /**< Shared Int Source MJPEG_DEC2_INT from Imaging Sub-System */
304 IMAGING_MJPEG_DEC3_INT_IRQn = 395, /**< Shared Int Source MJPEG_DEC3_INT from Imaging Sub-System */
305 ADMA_SAI0_MOD_INT_IRQn = 397, /**< Shared Int Source SAI0_MOD_INT from ADMA Sub-System */
306 ADMA_SAI0_DMA_INT_IRQn = 398, /**< Shared Int Source SAI0_DMA_INT from ADMA Sub-System */
307 ADMA_SAI1_MOD_INT_IRQn = 399, /**< Shared Int Source SAI1_MOD_INT from ADMA Sub-System */
308 ADMA_SAI1_DMA_INT_IRQn = 400, /**< Shared Int Source SAI1_DMA_INT from ADMA Sub-System */
309 ADMA_SAI2_MOD_INT_IRQn = 401, /**< Shared Int Source SAI2_MOD_INT from ADMA Sub-System */
310 ADMA_SAI2_DMA_INT_IRQn = 402, /**< Shared Int Source SAI2_DMA_INT from ADMA Sub-System */
311 MIPI_CSI0_OUT_INT_IRQn = 403, /**< Shared Int Source OUT_INT from MIPI_CSI0 Sub-System */
312 ADMA_SAI3_MOD_INT_IRQn = 406, /**< Shared Int Source SAI3_MOD_INT from ADMA Sub-System */
313 ADMA_SAI3_DMA_INT_IRQn = 407, /**< Shared Int Source SAI3_DMA_INT from ADMA Sub-System */
314 ADMA_SAI4_MOD_INT_IRQn = 412, /**< Shared Int Source SAI4_MOD_INT from ADMA Sub-System */
315 ADMA_SAI4_DMA_INT_IRQn = 413, /**< Shared Int Source SAI4_DMA_INT from ADMA Sub-System */
316 ADMA_SAI5_MOD_INT_IRQn = 414, /**< Shared Int Source SAI5_MOD_INT from ADMA Sub-System */
317 ADMA_SAI5_DMA_INT_IRQn = 415, /**< Shared Int Source SAI5_DMA_INT from ADMA Sub-System */
318 ADMA_SPI0_MOD_INT_IRQn = 419, /**< Shared Int Source SPI0_MOD_INT from ADMA Sub-System */
319 ADMA_SPI1_MOD_INT_IRQn = 420, /**< Shared Int Source SPI1_MOD_INT from ADMA Sub-System */
320 ADMA_SPI2_MOD_INT_IRQn = 421, /**< Shared Int Source SPI2_MOD_INT from ADMA Sub-System */
321 ADMA_SPI3_MOD_INT_IRQn = 422, /**< Shared Int Source SPI3_MOD_INT from ADMA Sub-System */
322 ADMA_I2C0_MOD_INT_IRQn = 423, /**< Shared Int Source I2C0_MOD_INT from ADMA Sub-System */
323 ADMA_I2C1_MOD_INT_IRQn = 424, /**< Shared Int Source I2C1_MOD_INT from ADMA Sub-System */
324 ADMA_I2C2_MOD_INT_IRQn = 425, /**< Shared Int Source I2C2_MOD_INT from ADMA Sub-System */
325 ADMA_I2C3_MOD_INT_IRQn = 426, /**< Shared Int Source I2C3_MOD_INT from ADMA Sub-System */
326 ADMA_UART0_MOD_INT_IRQn = 428, /**< Shared Int Source UART0_MOD_INT from ADMA Sub-System */
327 ADMA_UART1_MOD_INT_IRQn = 429, /**< Shared Int Source UART1_MOD_INT from ADMA Sub-System */
328 ADMA_UART2_MOD_INT_IRQn = 430, /**< Shared Int Source UART2_MOD_INT from ADMA Sub-System */
329 ADMA_UART3_MOD_INT_IRQn = 431, /**< Shared Int Source UART3_MOD_INT from ADMA Sub-System */
330 ADMA_FLEXCAN0_MOD_INT_IRQn = 435, /**< Shared Int Source FLEXCAN0_MOD_INT from ADMA Sub-System */
331 ADMA_FLEXCAN1_MOD_INT_IRQn = 436, /**< Shared Int Source FLEXCAN1_MOD_INT from ADMA Sub-System */
332 ADMA_FLEXCAN2_MOD_INT_IRQn = 437, /**< Shared Int Source FLEXCAN2_MOD_INT from ADMA Sub-System */
333 ADMA_FTM0_MOD_INT_IRQn = 438, /**< Shared Int Source FTM0_MOD_INT from ADMA Sub-System */
334 ADMA_FTM1_MOD_INT_IRQn = 439, /**< Shared Int Source FTM1_MOD_INT from ADMA Sub-System */
335 ADMA_ADC0_MOD_INT_IRQn = 440, /**< Shared Int Source ADC0_MOD_INT from ADMA Sub-System */
336 ADMA_FLEXCAN0_DMA_INT_IRQn = 442, /**< Shared Int Source FLEXCAN0_DMA_INT from ADMA Sub-System */
337 ADMA_FLEXCAN1_DMA_INT_IRQn = 443, /**< Shared Int Source FLEXCAN1_DMA_INT from ADMA Sub-System */
338 ADMA_FLEXCAN2_DMA_INT_IRQn = 444, /**< Shared Int Source FLEXCAN2_DMA_INT from ADMA Sub-System */
339 ADMA_FTM0_DMA_INT_IRQn = 445, /**< Shared Int Source FTM0_DMA_INT from ADMA Sub-System */
340 ADMA_FTM1_DMA_INT_IRQn = 446, /**< Shared Int Source FTM1_DMA_INT from ADMA Sub-System */
341 ADMA_ADC0_DMA_INT_IRQn = 447, /**< Shared Int Source ADC0_DMA_INT from ADMA Sub-System */
342 ADMA_EDMA0_INT_IRQn = 451, /**< Shared Int Source eDMA0_INT from ADMA Sub-System */
343 ADMA_EDMA0_ERR_INT_IRQn = 452, /**< Shared Int Source eDMA0_ERR_INT from ADMA Sub-System */
344 ADMA_EDMA1_INT_IRQn = 453, /**< Shared Int Source eDMA1_INT from ADMA Sub-System */
345 ADMA_EDMA1_ERR_INT_IRQn = 454, /**< Shared Int Source eDMA1_ERR_INT from ADMA Sub-System */
346 ADMA_ASRC0_INT1_IRQn = 455, /**< Shared Int Source ASRC0_INT1 from ADMA Sub-System */
347 ADMA_ASRC0_INT2_IRQn = 456, /**< Shared Int Source ASRC0_INT2 from ADMA Sub-System */
348 ADMA_DMA0_CH0_INT_IRQn = 457, /**< Shared Int Source DMA0_CH0_INT from ADMA Sub-System */
349 ADMA_DMA0_CH1_INT_IRQn = 458, /**< Shared Int Source DMA0_CH1_INT from ADMA Sub-System */
350 ADMA_DMA0_CH2_INT_IRQn = 459, /**< Shared Int Source DMA0_CH2_INT from ADMA Sub-System */
351 ADMA_DMA0_CH3_INT_IRQn = 460, /**< Shared Int Source DMA0_CH3_INT from ADMA Sub-System */
352 ADMA_DMA0_CH4_INT_IRQn = 461, /**< Shared Int Source DMA0_CH4_INT from ADMA Sub-System */
353 ADMA_DMA0_CH5_INT_IRQn = 462, /**< Shared Int Source DMA0_CH5_INT from ADMA Sub-System */
354 ADMA_ASRC1_INT1_IRQn = 463, /**< Shared Int Source ASRC1_INT1 from ADMA Sub-System */
355 ADMA_ASRC1_INT2_IRQn = 464, /**< Shared Int Source ASRC1_INT2 from ADMA Sub-System */
356 ADMA_DMA1_CH0_INT_IRQn = 465, /**< Shared Int Source DMA1_CH0_INT from ADMA Sub-System */
357 ADMA_DMA1_CH1_INT_IRQn = 466, /**< Shared Int Source DMA1_CH1_INT from ADMA Sub-System */
358 ADMA_DMA1_CH2_INT_IRQn = 467, /**< Shared Int Source DMA1_CH2_INT from ADMA Sub-System */
359 ADMA_DMA1_CH3_INT_IRQn = 468, /**< Shared Int Source DMA1_CH3_INT from ADMA Sub-System */
360 ADMA_DMA1_CH4_INT_IRQn = 469, /**< Shared Int Source DMA1_CH4_INT from ADMA Sub-System */
361 ADMA_DMA1_CH5_INT_IRQn = 470, /**< Shared Int Source DMA1_CH5_INT from ADMA Sub-System */
362 ADMA_ESAI0_INT_IRQn = 471, /**< Shared Int Source ESAI0_INT from ADMA Sub-System */
363 ADMA_GPT0_INT_IRQn = 474, /**< Shared Int Source GPT0_INT from ADMA Sub-System */
364 ADMA_GPT1_INT_IRQn = 475, /**< Shared Int Source GPT1_INT from ADMA Sub-System */
365 ADMA_GPT2_INT_IRQn = 476, /**< Shared Int Source GPT2_INT from ADMA Sub-System */
366 ADMA_GPT3_INT_IRQn = 477, /**< Shared Int Source GPT3_INT from ADMA Sub-System */
367 ADMA_GPT4_INT_IRQn = 478, /**< Shared Int Source GPT4_INT from ADMA Sub-System */
368 ADMA_GPT5_INT_IRQn = 479, /**< Shared Int Source GPT5_INT from ADMA Sub-System */
369 ADMA_SAI0_INT_IRQn = 480, /**< Shared Int Source SAI0_INT from ADMA Sub-System */
370 ADMA_SAI1_INT_IRQn = 481, /**< Shared Int Source SAI1_INT from ADMA Sub-System */
371 ADMA_SAI2_INT_IRQn = 482, /**< Shared Int Source SAI2_INT from ADMA Sub-System */
372 ADMA_SAI3_INT_IRQn = 483, /**< Shared Int Source SAI3_INT from ADMA Sub-System */
373 ADMA_SAI4_INT_IRQn = 486, /**< Shared Int Source SAI4_INT from ADMA Sub-System */
374 ADMA_SAI5_INT_IRQn = 487, /**< Shared Int Source SAI5_INT from ADMA Sub-System */
375 ADMA_SPDIF0_RX_INT_IRQn = 488, /**< Shared Int Source SPDIF0_RX_INT from ADMA Sub-System */
376 ADMA_SPDIF0_TX_INT_IRQn = 489, /**< Shared Int Source SPDIF0_TX_INT from ADMA Sub-System */
377 ADMA_ESAI0_MOD_INT_IRQn = 492, /**< Shared Int Source ESAI0_MOD_INT from ADMA Sub-System */
378 ADMA_ESAI0_DMA_INT_IRQn = 493, /**< Shared Int Source ESAI0_DMA_INT from ADMA Sub-System */
379 ADMA_SPI0_DMA_RX_INT_IRQn = 499, /**< Shared Int Source SPI0_DMA_RX_INT from ADMA Sub-System */
380 ADMA_SPI0_DMA_TX_INT_IRQn = 500, /**< Shared Int Source SPI0_DMA_TX_INT from ADMA Sub-System */
381 ADMA_SPI1_DMA_RX_INT_IRQn = 501, /**< Shared Int Source SPI1_DMA_RX_INT from ADMA Sub-System */
382 ADMA_SPI1_DMA_TX_INT_IRQn = 502, /**< Shared Int Source SPI1_DMA_TX_INT from ADMA Sub-System */
383 ADMA_SPI2_DMA_RX_INT_IRQn = 503, /**< Shared Int Source SPI2_DMA_RX_INT from ADMA Sub-System */
384 ADMA_SPI2_DMA_TX_INT_IRQn = 504, /**< Shared Int Source SPI2_DMA_TX_INT from ADMA Sub-System */
385 ADMA_SPI3_DMA_RX_INT_IRQn = 505, /**< Shared Int Source SPI3_DMA_RX_INT from ADMA Sub-System */
386 ADMA_SPI3_DMA_TX_INT_IRQn = 506, /**< Shared Int Source SPI3_DMA_TX_INT from ADMA Sub-System */
387 ADMA_I2C0_DMA_RX_INT_IRQn = 507, /**< Shared Int Source I2C0_DMA_RX_INT from ADMA Sub-System */
388 ADMA_I2C0_DMA_TX_INT_IRQn = 508, /**< Shared Int Source I2C0_DMA_TX_INT from ADMA Sub-System */
389 ADMA_I2C1_DMA_RX_INT_IRQn = 509, /**< Shared Int Source I2C1_DMA_RX_INT from ADMA Sub-System */
390 ADMA_I2C1_DMA_TX_INT_IRQn = 510, /**< Shared Int Source I2C1_DMA_TX_INT from ADMA Sub-System */
391 ADMA_I2C2_DMA_RX_INT_IRQn = 511, /**< Shared Int Source I2C2_DMA_RX_INT from ADMA Sub-System */
392 ADMA_I2C2_DMA_TX_INT_IRQn = 512, /**< Shared Int Source I2C2_DMA_TX_INT from ADMA Sub-System */
393 ADMA_I2C3_DMA_RX_INT_IRQn = 513, /**< Shared Int Source I2C3_DMA_RX_INT from ADMA Sub-System */
394 ADMA_I2C3_DMA_TX_INT_IRQn = 514, /**< Shared Int Source I2C3_DMA_TX_INT from ADMA Sub-System */
395 ADMA_UART0_DMA_RX_INT_IRQn = 517, /**< Shared Int Source UART0_DMA_RX_INT from ADMA Sub-System */
396 ADMA_UART0_DMA_TX_INT_IRQn = 518, /**< Shared Int Source UART0_DMA_TX_INT from ADMA Sub-System */
397 ADMA_UART1_DMA_RX_INT_IRQn = 519, /**< Shared Int Source UART1_DMA_RX_INT from ADMA Sub-System */
398 ADMA_UART1_DMA_TX_INT_IRQn = 520, /**< Shared Int Source UART1_DMA_TX_INT from ADMA Sub-System */
399 ADMA_UART2_DMA_RX_INT_IRQn = 521, /**< Shared Int Source UART2_DMA_RX_INT from ADMA Sub-System */
400 ADMA_UART2_DMA_TX_INT_IRQn = 522, /**< Shared Int Source UART2_DMA_TX_INT from ADMA Sub-System */
401 ADMA_UART3_DMA_RX_INT_IRQn = 523, /**< Shared Int Source UART3_DMA_RX_INT from ADMA Sub-System */
402 ADMA_UART3_DMA_TX_INT_IRQn = 524, /**< Shared Int Source UART3_DMA_TX_INT from ADMA Sub-System */
403 SECURITY_MU1_A_INT_IRQn = 531, /**< Shared Int Source MU1_A_INT from Security Sub-System */
404 SECURITY_MU2_A_INT_IRQn = 532, /**< Shared Int Source MU2_A_INT from Security Sub-System */
405 SECURITY_MU3_A_INT_IRQn = 533, /**< Shared Int Source MU3_A_INT from Security Sub-System */
406 SECURITY_CAAM_INT0_IRQn = 534, /**< Shared Int Source CAAM_INT0 from Security Sub-System */
407 SECURITY_CAAM_INT1_IRQn = 535, /**< Shared Int Source CAAM_INT1 from Security Sub-System */
408 SECURITY_CAAM_INT2_IRQn = 536, /**< Shared Int Source CAAM_INT2 from Security Sub-System */
409 SECURITY_CAAM_INT3_IRQn = 537, /**< Shared Int Source CAAM_INT3 from Security Sub-System */
410 SECURITY_CAAM_RTIC_INT_IRQn = 538, /**< Shared Int Source CAAM_RTIC_INT from Security Sub-System */
411 ADMA_SPDIF0_RX_MOD_INT_IRQn = 539, /**< Shared Int Source SPDIF0_RX_MOD_INT from ADMA Sub-System */
412 ADMA_SPDIF0_RX_DMA_INT_IRQn = 540, /**< Shared Int Source SPDIF0_RX_DMA_INT from ADMA Sub-System */
413 ADMA_SPDIF0_TX_MOD_INT_IRQn = 541, /**< Shared Int Source SPDIF0_TX_MOD_INT from ADMA Sub-System */
414 ADMA_SPDIF0_TX_DMA_INT_IRQn = 542, /**< Shared Int Source SPDIF0_TX_DMA_INT from ADMA Sub-System */
415 VPU_VPU_INT_0_IRQn = 547, /**< Shared Int Source VPU_INT_0 from VPU Sub-System */
416 VPU_VPU_INT_1_IRQn = 548, /**< Shared Int Source VPU_INT_1 from VPU Sub-System */
417 VPU_VPU_INT_2_IRQn = 549, /**< Shared Int Source VPU_INT_2 from VPU Sub-System */
418 VPU_VPU_INT_3_IRQn = 550, /**< Shared Int Source VPU_INT_3 from VPU Sub-System */
419 VPU_VPU_INT_4_IRQn = 551, /**< Shared Int Source VPU_INT_4 from VPU Sub-System */
420 M4_INTMUX_SOURCE_TPM_IRQn = 564, /**< INTMUX Input source: TPM Interrupt */
421 M4_INTMUX_SOURCE_LPIT_IRQn = 567, /**< INTMUX Input source: LPIT Interrupt */
422 M4_INTMUX_SOURCE_LPUART_IRQn = 570, /**< INTMUX Input source: LPUART Interrupt */
423 M4_INTMUX_SOURCE_LPI2C_IRQn = 572, /**< INTMUX Input source: LPI2C Interrupt */
424 M4_INTMUX_SOURCE_MU0_A3_IRQn = 591, /**< INTMUX Input source: MU0_A3 Interrupt */
425 M4_INTMUX_SOURCE_MU0_A2_IRQn = 592, /**< INTMUX Input source: MU0_A2 Interrupt */
426 M4_INTMUX_SOURCE_MU0_A1_IRQn = 593, /**< INTMUX Input source: MU0_A1 Interrupt */
427 M4_INTMUX_SOURCE_MU0_A0_IRQn = 594 /**< INTMUX Input source: MU0_A0 Interrupt */
428} IRQn_Type;
429
430/*!
431 * @}
432 */ /* end of group Interrupt_vector_numbers */
433
434
435/* ----------------------------------------------------------------------------
436 -- Configuration of the Cortex-M4 Processor and Core Peripherals
437 ---------------------------------------------------------------------------- */
438
439/*!
440 * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-M4 Processor and Core Peripherals
441 * @{
442 */
443
444#define __CM4_REV 0x0001 /**< Core revision r0p1 */
445#define __MPU_PRESENT 1 /**< MPU present or not */
446#define __NVIC_PRIO_BITS 4 /**< Number of Bits used for Priority Levels */
447#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
448#define __FPU_PRESENT 1 /**< FPU present or not */
449
450#include "core_cm4.h" /* Core Peripheral Access Layer */
451#include "system_MIMX8DX4_cm4.h" /* Device specific configuration file */
452
453/*!
454 * @}
455 */ /* end of group Cortex_Core_Configuration */
456
457
458/* ----------------------------------------------------------------------------
459 -- Device Peripheral Access Layer
460 ---------------------------------------------------------------------------- */
461
462/*!
463 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
464 * @{
465 */
466
467
468/*
469** Start of section using anonymous unions
470*/
471
472#if defined(__ARMCC_VERSION)
473 #if (__ARMCC_VERSION >= 6010050)
474 #pragma clang diagnostic push
475 #else
476 #pragma push
477 #pragma anon_unions
478 #endif
479#elif defined(__GNUC__)
480 /* anonymous unions are enabled by default */
481#elif defined(__IAR_SYSTEMS_ICC__)
482 #pragma language=extended
483#else
484 #error Not supported compiler type
485#endif
486
487/* ----------------------------------------------------------------------------
488 -- ACM Peripheral Access Layer
489 ---------------------------------------------------------------------------- */
490
491/*!
492 * @addtogroup ACM_Peripheral_Access_Layer ACM Peripheral Access Layer
493 * @{
494 */
495
496/** ACM - Register Layout Typedef */
497typedef struct {
498 uint8_t RESERVED_0[14680064];
499 __IO uint32_t AUD_CLK0; /**< ACM_AUD_CLK0 Register, offset: 0xE00000 */
500 uint8_t RESERVED_1[65532];
501 __IO uint32_t AUD_CLK1; /**< ACM_AUD_CLK1 Register, offset: 0xE10000 */
502 uint8_t RESERVED_2[65532];
503 __IO uint32_t MCLKOUT0; /**< ACM_MCLKOUT0 Register, offset: 0xE20000 */
504 uint8_t RESERVED_3[65532];
505 __IO uint32_t MCLKOUT1; /**< ACM_MCLKOUT1 Register, offset: 0xE30000 */
506 uint8_t RESERVED_4[196604];
507 __IO uint32_t ESAI0_CLK; /**< ACM_ESAI0_CLK Register, offset: 0xE60000 */
508 uint8_t RESERVED_5[131068];
509 struct { /* offset: 0xE80000, array step: 0x10000 */
510 __IO uint32_t GPT_CLK; /**< ACM_GPT_CLK Register, array offset: 0xE80000, array step: 0x10000 */
511 uint8_t RESERVED_0[65532];
512 } GPT_CLK[6];
513 struct { /* offset: 0xEE0000, array step: 0x10000 */
514 __IO uint32_t SAI_MCLK; /**< ACM_SAI_MCLK Register, array offset: 0xEE0000, array step: 0x10000 */
515 uint8_t RESERVED_0[65532];
516 } SAI_MCLK[8];
517 uint8_t RESERVED_6[262144];
518 __IO uint32_t SPDIF0_TX_CLK; /**< ACM_SPDIF0_TX_CLK Register, offset: 0xFA0000 */
519 uint8_t RESERVED_7[131068];
520 __IO uint32_t MQS_HMCLK_CLK; /**< ACM_MQS_HMCLK_CLK Register, offset: 0xFC0000 */
521} ACM_Type;
522
523/* ----------------------------------------------------------------------------
524 -- ACM Register Masks
525 ---------------------------------------------------------------------------- */
526
527/*!
528 * @addtogroup ACM_Register_Masks ACM Register Masks
529 * @{
530 */
531
532/*! @name AUD_CLK0 - ACM_AUD_CLK0 Register */
533/*! @{ */
534#define ACM_AUD_CLK0_SEL_MASK (0x1FU)
535#define ACM_AUD_CLK0_SEL_SHIFT (0U)
536/*! SEL - Select
537 * 0b00000..ADMA_SLSLICE2
538 * 0b00001..ADMA_SLSLICE3
539 * 0b00010..EXT_AUD_MCLK0
540 * 0b00011..EXT_AUD_MCLK1
541 * 0b00100..ESAI0_RX_CLK
542 * 0b00101..ESAI0_RX_HF_CLKK
543 * 0b00110..ESAI0_TX_CLK
544 * 0b00111..ESAI0_TX_HF_CLK
545 * 0b01000..SPDIF0_RX
546 * 0b01001..SAI0_RX_BCLK
547 * 0b01010..SAI0_TX_BCLK
548 * 0b01011..SAI1_RX_BCLK
549 * 0b01100..SAI1_TX_BCLK
550 * 0b01101..SAI2_RX_BCLK
551 * 0b01110..SAI3_RX_BCLK
552 */
553#define ACM_AUD_CLK0_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK0_SEL_SHIFT)) & ACM_AUD_CLK0_SEL_MASK)
554/*! @} */
555
556/*! @name AUD_CLK1 - ACM_AUD_CLK1 Register */
557/*! @{ */
558#define ACM_AUD_CLK1_SEL_MASK (0x1FU)
559#define ACM_AUD_CLK1_SEL_SHIFT (0U)
560/*! SEL - Select
561 * 0b00000..ADMA_SLSLICE2
562 * 0b00001..ADMA_SLSLICE3
563 * 0b00010..EXT_AUD_MCLK0
564 * 0b00011..EXT_AUD_MCLK1
565 * 0b00100..ESAI0_RX_CLK
566 * 0b00101..ESAI0_RX_HF_CLKK
567 * 0b00110..ESAI0_TX_CLK
568 * 0b00111..ESAI0_TX_HF_CLK
569 * 0b01000..SPDIF0_RX
570 * 0b01001..SAI0_RX_BCLK
571 * 0b01010..SAI0_TX_BCLK
572 * 0b01011..SAI1_RX_BCLK
573 * 0b01100..SAI1_TX_BCLK
574 * 0b01101..SAI2_RX_BCLK
575 * 0b01110..SAI3_RX_BCLK
576 */
577#define ACM_AUD_CLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK1_SEL_SHIFT)) & ACM_AUD_CLK1_SEL_MASK)
578/*! @} */
579
580/*! @name MCLKOUT0 - ACM_MCLKOUT0 Register */
581/*! @{ */
582#define ACM_MCLKOUT0_SEL_MASK (0x7U)
583#define ACM_MCLKOUT0_SEL_SHIFT (0U)
584/*! SEL - Select
585 * 0b000..ADMA_SLSLICE2
586 * 0b001..ADMA_SLSLICE3
587 * 0b010..Reserved
588 * 0b011..Reserved
589 * 0b100..SPDIF0_RX
590 * 0b101..Reserved
591 * 0b110..Reserved
592 * 0b111..SAI4_RX_BCLK
593 */
594#define ACM_MCLKOUT0_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT0_SEL_SHIFT)) & ACM_MCLKOUT0_SEL_MASK)
595/*! @} */
596
597/*! @name MCLKOUT1 - ACM_MCLKOUT1 Register */
598/*! @{ */
599#define ACM_MCLKOUT1_SEL_MASK (0x7U)
600#define ACM_MCLKOUT1_SEL_SHIFT (0U)
601/*! SEL - Select
602 * 0b000..ADMA_SLSLICE2
603 * 0b001..ADMA_SLSLICE3
604 * 0b010..Reserved
605 * 0b011..Reserved
606 * 0b100..SPDIF0_RX
607 * 0b101..Reserved
608 * 0b110..Reserved
609 * 0b111..SAI4_RX_BCLK
610 */
611#define ACM_MCLKOUT1_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT1_SEL_SHIFT)) & ACM_MCLKOUT1_SEL_MASK)
612/*! @} */
613
614/*! @name ESAI0_CLK - ACM_ESAI0_CLK Register */
615/*! @{ */
616#define ACM_ESAI0_CLK_SEL_MASK (0x3U)
617#define ACM_ESAI0_CLK_SEL_SHIFT (0U)
618/*! SEL - Select
619 * 0b00..AUD_PLL_DIV_CLK0
620 * 0b01..AUD_PLL_DIV_CLK1
621 * 0b10..AUD_CLK0
622 * 0b11..AUD_CLK1
623 */
624#define ACM_ESAI0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_ESAI0_CLK_SEL_SHIFT)) & ACM_ESAI0_CLK_SEL_MASK)
625/*! @} */
626
627/*! @name GPT_CLK - ACM_GPT_CLK Register */
628/*! @{ */
629#define ACM_GPT_CLK_SEL_MASK (0x7U)
630#define ACM_GPT_CLK_SEL_SHIFT (0U)
631/*! SEL - Select
632 * 0b000..AUD_PLL_DIV_CLK0
633 * 0b001..AUD_PLL_DIV_CLK1
634 * 0b010..AUD_CLK0
635 * 0b011..AUD_CLK1
636 * 0b100..24M_REF_CLK
637 */
638#define ACM_GPT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT_CLK_SEL_SHIFT)) & ACM_GPT_CLK_SEL_MASK)
639/*! @} */
640
641/* The count of ACM_GPT_CLK */
642#define ACM_GPT_CLK_COUNT (6U)
643
644/*! @name SAI_MCLK - ACM_SAI_MCLK Register */
645/*! @{ */
646#define ACM_SAI_MCLK_SEL_MASK (0x3U)
647#define ACM_SAI_MCLK_SEL_SHIFT (0U)
648/*! SEL - Select
649 * 0b00..AUD_PLL_DIV_CLK0
650 * 0b01..AUD_PLL_DIV_CLK1
651 * 0b10..AUD_CLK0
652 * 0b11..AUD_CLK1
653 */
654#define ACM_SAI_MCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SAI_MCLK_SEL_SHIFT)) & ACM_SAI_MCLK_SEL_MASK)
655/*! @} */
656
657/* The count of ACM_SAI_MCLK */
658#define ACM_SAI_MCLK_COUNT (8U)
659
660/*! @name SPDIF0_TX_CLK - ACM_SPDIF0_TX_CLK Register */
661/*! @{ */
662#define ACM_SPDIF0_TX_CLK_SEL_MASK (0x3U)
663#define ACM_SPDIF0_TX_CLK_SEL_SHIFT (0U)
664/*! SEL - Select
665 * 0b00..AUD_PLL_DIV_CLK0
666 * 0b01..AUD_PLL_DIV_CLK1
667 * 0b10..AUD_CLK0
668 * 0b11..AUD_CLK1
669 */
670#define ACM_SPDIF0_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SPDIF0_TX_CLK_SEL_SHIFT)) & ACM_SPDIF0_TX_CLK_SEL_MASK)
671/*! @} */
672
673/*! @name MQS_HMCLK_CLK - ACM_MQS_HMCLK_CLK Register */
674/*! @{ */
675#define ACM_MQS_HMCLK_CLK_SEL_MASK (0x3U)
676#define ACM_MQS_HMCLK_CLK_SEL_SHIFT (0U)
677/*! SEL - Select
678 * 0b00..AUD_PLL_DIV_CLK0
679 * 0b01..AUD_PLL_DIV_CLK1
680 * 0b10..AUD_CLK0
681 * 0b11..AUD_CLK1
682 */
683#define ACM_MQS_HMCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MQS_HMCLK_CLK_SEL_SHIFT)) & ACM_MQS_HMCLK_CLK_SEL_MASK)
684/*! @} */
685
686
687/*!
688 * @}
689 */ /* end of group ACM_Register_Masks */
690
691
692/* ACM - Peripheral instance base addresses */
693/** Peripheral ADMA__ACM base address */
694#define ADMA__ACM_BASE (0x59000000u)
695/** Peripheral ADMA__ACM base pointer */
696#define ADMA__ACM ((ACM_Type *)ADMA__ACM_BASE)
697/** Array initializer of ACM peripheral base addresses */
698#define ACM_BASE_ADDRS { ADMA__ACM_BASE }
699/** Array initializer of ACM peripheral base pointers */
700#define ACM_BASE_PTRS { ADMA__ACM }
701
702/*!
703 * @}
704 */ /* end of group ACM_Peripheral_Access_Layer */
705
706
707/* ----------------------------------------------------------------------------
708 -- ADC Peripheral Access Layer
709 ---------------------------------------------------------------------------- */
710
711/*!
712 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
713 * @{
714 */
715
716/** ADC - Register Layout Typedef */
717typedef struct {
718 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
719 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
720 uint8_t RESERVED_0[8];
721 __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */
722 __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */
723 __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */
724 __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */
725 __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */
726 __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */
727 uint8_t RESERVED_1[8];
728 __IO uint32_t FCTRL; /**< ADC FIFO Control Register, offset: 0x30 */
729 __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
730 uint8_t RESERVED_2[136];
731 __IO uint32_t TCTRL[8]; /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */
732 uint8_t RESERVED_3[32];
733 struct { /* offset: 0x100, array step: 0x8 */
734 __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
735 __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
736 } CMD[15];
737 uint8_t RESERVED_4[136];
738 __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
739 uint8_t RESERVED_5[240];
740 __I uint32_t RESFIFO; /**< ADC Data Result FIFO Register, offset: 0x300 */
741} ADC_Type;
742
743/* ----------------------------------------------------------------------------
744 -- ADC Register Masks
745 ---------------------------------------------------------------------------- */
746
747/*!
748 * @addtogroup ADC_Register_Masks ADC Register Masks
749 * @{
750 */
751
752/*! @name VERID - Version ID Register */
753/*! @{ */
754#define ADC_VERID_RES_MASK (0x1U)
755#define ADC_VERID_RES_SHIFT (0U)
756/*! RES - Resolution
757 * 0b0..Up to 13-bit differential/12-bit single ended resolution supported.
758 * 0b1..Up to 16-bit differential/15-bit single ended resolution supported.
759 */
760#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
761#define ADC_VERID_DIFFEN_MASK (0x2U)
762#define ADC_VERID_DIFFEN_SHIFT (1U)
763/*! DIFFEN - Differential Supported
764 * 0b0..Differential operation not supported.
765 * 0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
766 */
767#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
768#define ADC_VERID_MVI_MASK (0x8U)
769#define ADC_VERID_MVI_SHIFT (3U)
770/*! MVI - Multi Vref Implemented
771 * 0b0..Single voltage reference high (VREFH) input supported.
772 * 0b1..Multiple voltage reference high (VREFH) inputs supported.
773 */
774#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
775#define ADC_VERID_CSW_MASK (0x70U)
776#define ADC_VERID_CSW_SHIFT (4U)
777/*! CSW - Channel Scale Width
778 * 0b000..Channel scaling not supported.
779 * 0b001..Channel scaling supported. 1-bit CSCALE control field.
780 * 0b110..Channel scaling supported. 6-bit CSCALE control field.
781 */
782#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
783#define ADC_VERID_VR1RNGI_MASK (0x100U)
784#define ADC_VERID_VR1RNGI_SHIFT (8U)
785/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
786 * 0b0..Range control not required. CFG[VREF1RNG] is not implemented.
787 * 0b1..Range control required. CFG[VREF1RNG] is implemented.
788 */
789#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
790#define ADC_VERID_IADCKI_MASK (0x200U)
791#define ADC_VERID_IADCKI_SHIFT (9U)
792/*! IADCKI - Internal ADC Clock implemented
793 * 0b0..Internal clock source not implemented.
794 * 0b1..Internal clock source (and CFG[ADCKEN]) implemented.
795 */
796#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
797#define ADC_VERID_CALOFSI_MASK (0x400U)
798#define ADC_VERID_CALOFSI_SHIFT (10U)
799/*! CALOFSI - Calibration Offset Function Implemented
800 * 0b0..Offset calibration and offset trimming not implemented.
801 * 0b1..Offset calibration and offset trimming implemented.
802 */
803#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
804#define ADC_VERID_MINOR_MASK (0xFF0000U)
805#define ADC_VERID_MINOR_SHIFT (16U)
806/*! MINOR - Minor Version Number
807 */
808#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
809#define ADC_VERID_MAJOR_MASK (0xFF000000U)
810#define ADC_VERID_MAJOR_SHIFT (24U)
811/*! MAJOR - Major Version Number
812 */
813#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
814/*! @} */
815
816/*! @name PARAM - Parameter Register */
817/*! @{ */
818#define ADC_PARAM_TRIG_NUM_MASK (0xFFU)
819#define ADC_PARAM_TRIG_NUM_SHIFT (0U)
820/*! TRIG_NUM - Trigger Number
821 */
822#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
823#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U)
824#define ADC_PARAM_FIFOSIZE_SHIFT (8U)
825/*! FIFOSIZE - Result FIFO Depth
826 * 0b00000001..Result FIFO depth = 1 dataword.
827 * 0b00000100..Result FIFO depth = 4 datawords.
828 * 0b00001000..Result FIFO depth = 8 datawords.
829 * 0b00010000..Result FIFO depth = 16 datawords.
830 * 0b00100000..Result FIFO depth = 32 datawords.
831 * 0b01000000..Result FIFO depth = 64 datawords.
832 */
833#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
834#define ADC_PARAM_CV_NUM_MASK (0xFF0000U)
835#define ADC_PARAM_CV_NUM_SHIFT (16U)
836/*! CV_NUM - Compare Value Number
837 */
838#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
839#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U)
840#define ADC_PARAM_CMD_NUM_SHIFT (24U)
841/*! CMD_NUM - Command Buffer Number
842 */
843#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
844/*! @} */
845
846/*! @name CTRL - ADC Control Register */
847/*! @{ */
848#define ADC_CTRL_ADCEN_MASK (0x1U)
849#define ADC_CTRL_ADCEN_SHIFT (0U)
850/*! ADCEN - ADC Enable
851 * 0b0..ADC is disabled.
852 * 0b1..ADC is enabled.
853 */
854#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
855#define ADC_CTRL_RST_MASK (0x2U)
856#define ADC_CTRL_RST_SHIFT (1U)
857/*! RST - Software Reset
858 * 0b0..ADC logic is not reset.
859 * 0b1..ADC logic is reset.
860 */
861#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
862#define ADC_CTRL_DOZEN_MASK (0x4U)
863#define ADC_CTRL_DOZEN_SHIFT (2U)
864/*! DOZEN - Doze Enable
865 * 0b0..ADC is enabled in Doze mode.
866 * 0b1..ADC is disabled in Doze mode.
867 */
868#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
869#define ADC_CTRL_RSTFIFO_MASK (0x100U)
870#define ADC_CTRL_RSTFIFO_SHIFT (8U)
871/*! RSTFIFO - Reset FIFO
872 * 0b0..No effect.
873 * 0b1..FIFO is reset.
874 */
875#define ADC_CTRL_RSTFIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)
876/*! @} */
877
878/*! @name STAT - ADC Status Register */
879/*! @{ */
880#define ADC_STAT_RDY_MASK (0x1U)
881#define ADC_STAT_RDY_SHIFT (0U)
882/*! RDY - Result FIFO Ready Flag
883 * 0b0..Result FIFO data level not above watermark level.
884 * 0b1..Result FIFO holding data above watermark level.
885 */
886#define ADC_STAT_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
887#define ADC_STAT_FOF_MASK (0x2U)
888#define ADC_STAT_FOF_SHIFT (1U)
889/*! FOF - Result FIFO Overflow Flag
890 * 0b0..No result FIFO overflow has occurred since the last time the flag was cleared.
891 * 0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared.
892 */
893#define ADC_STAT_FOF(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
894#define ADC_STAT_ADC_ACTIVE_MASK (0x100U)
895#define ADC_STAT_ADC_ACTIVE_SHIFT (8U)
896/*! ADC_ACTIVE - ADC Active
897 * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
898 * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
899 */
900#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
901#define ADC_STAT_TRGACT_MASK (0x70000U)
902#define ADC_STAT_TRGACT_SHIFT (16U)
903/*! TRGACT - Trigger Active
904 * 0b000..Command (sequence) associated with Trigger 0 currently being executed.
905 * 0b001..Command (sequence) associated with Trigger 1 currently being executed.
906 * 0b010..Command (sequence) associated with Trigger 2 currently being executed.
907 * 0b011-0b111..Command (sequence) from the associated Trigger number is currently being executed.
908 */
909#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
910#define ADC_STAT_CMDACT_MASK (0xF000000U)
911#define ADC_STAT_CMDACT_SHIFT (24U)
912/*! CMDACT - Command Active
913 * 0b0000..No command is currently in progress.
914 * 0b0001..Command 1 currently being executed.
915 * 0b0010..Command 2 currently being executed.
916 * 0b0011-0b1111..Associated command number is currently being executed.
917 */
918#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
919/*! @} */
920
921/*! @name IE - Interrupt Enable Register */
922/*! @{ */
923#define ADC_IE_FWMIE_MASK (0x1U)
924#define ADC_IE_FWMIE_SHIFT (0U)
925/*! FWMIE - FIFO Watermark Interrupt Enable
926 * 0b0..FIFO watermark interrupts are not enabled.
927 * 0b1..FIFO watermark interrupts are enabled.
928 */
929#define ADC_IE_FWMIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
930#define ADC_IE_FOFIE_MASK (0x2U)
931#define ADC_IE_FOFIE_SHIFT (1U)
932/*! FOFIE - Result FIFO Overflow Interrupt Enable
933 * 0b0..FIFO overflow interrupts are not enabled.
934 * 0b1..FIFO overflow interrupts are enabled.
935 */
936#define ADC_IE_FOFIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)
937/*! @} */
938
939/*! @name DE - DMA Enable Register */
940/*! @{ */
941#define ADC_DE_FWMDE_MASK (0x1U)
942#define ADC_DE_FWMDE_SHIFT (0U)
943/*! FWMDE - FIFO Watermark DMA Enable
944 * 0b0..DMA request disabled.
945 * 0b1..DMA request enabled.
946 */
947#define ADC_DE_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)
948/*! @} */
949
950/*! @name CFG - ADC Configuration Register */
951/*! @{ */
952#define ADC_CFG_TPRICTRL_MASK (0x1U)
953#define ADC_CFG_TPRICTRL_SHIFT (0U)
954/*! TPRICTRL - ADC trigger priority control
955 * 0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and
956 * the new command specified by the trigger is started.
957 * 0b1..If a higher priority trigger is received during command processing, the current conversion is completed
958 * (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority
959 * trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true
960 * conversion.
961 */
962#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
963#define ADC_CFG_PWRSEL_MASK (0x30U)
964#define ADC_CFG_PWRSEL_SHIFT (4U)
965/*! PWRSEL - Power Configuration Select
966 * 0b00..Level 1 (Lowest power setting)
967 * 0b01..Level 2
968 * 0b10..Level 3
969 * 0b11..Level 4 (Highest power setting)
970 */
971#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
972#define ADC_CFG_REFSEL_MASK (0xC0U)
973#define ADC_CFG_REFSEL_SHIFT (6U)
974/*! REFSEL - Voltage Reference Selection
975 * 0b00..(Default) Option 1 setting.
976 * 0b01..Option 2 setting.
977 * 0b10..Option 3 setting.
978 * 0b11..Reserved
979 */
980#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
981#define ADC_CFG_PUDLY_MASK (0xFF0000U)
982#define ADC_CFG_PUDLY_SHIFT (16U)
983/*! PUDLY - Power Up Delay
984 */
985#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
986#define ADC_CFG_PWREN_MASK (0x10000000U)
987#define ADC_CFG_PWREN_SHIFT (28U)
988/*! PWREN - ADC Analog Pre-Enable
989 * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
990 * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
991 * of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any
992 * detected trigger does not begin ADC operation until the power up delay time has passed.
993 */
994#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
995/*! @} */
996
997/*! @name PAUSE - ADC Pause Register */
998/*! @{ */
999#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU)
1000#define ADC_PAUSE_PAUSEDLY_SHIFT (0U)
1001/*! PAUSEDLY - Pause Delay
1002 */
1003#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
1004#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U)
1005#define ADC_PAUSE_PAUSEEN_SHIFT (31U)
1006/*! PAUSEEN - PAUSE Option Enable
1007 * 0b0..Pause operation disabled
1008 * 0b1..Pause operation enabled
1009 */
1010#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
1011/*! @} */
1012
1013/*! @name FCTRL - ADC FIFO Control Register */
1014/*! @{ */
1015#define ADC_FCTRL_FCOUNT_MASK (0x1FU)
1016#define ADC_FCTRL_FCOUNT_SHIFT (0U)
1017/*! FCOUNT - Result FIFO counter
1018 */
1019#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
1020#define ADC_FCTRL_FWMARK_MASK (0xF0000U)
1021#define ADC_FCTRL_FWMARK_SHIFT (16U)
1022/*! FWMARK - Watermark level selection
1023 */
1024#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
1025/*! @} */
1026
1027/*! @name SWTRIG - Software Trigger Register */
1028/*! @{ */
1029#define ADC_SWTRIG_SWT0_MASK (0x1U)
1030#define ADC_SWTRIG_SWT0_SHIFT (0U)
1031/*! SWT0 - Software trigger 0 event
1032 * 0b0..No trigger 0 event generated.
1033 * 0b1..Trigger 0 event generated.
1034 */
1035#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
1036#define ADC_SWTRIG_SWT1_MASK (0x2U)
1037#define ADC_SWTRIG_SWT1_SHIFT (1U)
1038/*! SWT1 - Software trigger 1 event
1039 * 0b0..No trigger 1 event generated.
1040 * 0b1..Trigger 1 event generated.
1041 */
1042#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
1043#define ADC_SWTRIG_SWT2_MASK (0x4U)
1044#define ADC_SWTRIG_SWT2_SHIFT (2U)
1045/*! SWT2 - Software trigger 2 event
1046 * 0b0..No trigger 2 event generated.
1047 * 0b1..Trigger 2 event generated.
1048 */
1049#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
1050#define ADC_SWTRIG_SWT3_MASK (0x8U)
1051#define ADC_SWTRIG_SWT3_SHIFT (3U)
1052/*! SWT3 - Software trigger 3 event
1053 * 0b0..No trigger 3 event generated.
1054 * 0b1..Trigger 3 event generated.
1055 */
1056#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
1057#define ADC_SWTRIG_SWT4_MASK (0x10U)
1058#define ADC_SWTRIG_SWT4_SHIFT (4U)
1059/*! SWT4 - Software trigger 4 event
1060 * 0b0..No trigger 4 event generated.
1061 * 0b1..Trigger 4 event generated.
1062 */
1063#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
1064#define ADC_SWTRIG_SWT5_MASK (0x20U)
1065#define ADC_SWTRIG_SWT5_SHIFT (5U)
1066/*! SWT5 - Software trigger 5 event
1067 * 0b0..No trigger 5 event generated.
1068 * 0b1..Trigger 5 event generated.
1069 */
1070#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
1071#define ADC_SWTRIG_SWT6_MASK (0x40U)
1072#define ADC_SWTRIG_SWT6_SHIFT (6U)
1073/*! SWT6 - Software trigger 6 event
1074 * 0b0..No trigger 6 event generated.
1075 * 0b1..Trigger 6 event generated.
1076 */
1077#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
1078#define ADC_SWTRIG_SWT7_MASK (0x80U)
1079#define ADC_SWTRIG_SWT7_SHIFT (7U)
1080/*! SWT7 - Software trigger 7 event
1081 * 0b0..No trigger 7 event generated.
1082 * 0b1..Trigger 7 event generated.
1083 */
1084#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
1085/*! @} */
1086
1087/*! @name TCTRL - Trigger Control Register */
1088/*! @{ */
1089#define ADC_TCTRL_HTEN_MASK (0x1U)
1090#define ADC_TCTRL_HTEN_SHIFT (0U)
1091/*! HTEN - Trigger enable
1092 * 0b0..Hardware trigger source disabled
1093 * 0b1..Hardware trigger source enabled
1094 */
1095#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
1096#define ADC_TCTRL_TPRI_MASK (0x700U)
1097#define ADC_TCTRL_TPRI_SHIFT (8U)
1098/*! TPRI - Trigger priority setting
1099 * 0b000..Set to highest priority, Level 1
1100 * 0b001-0b110..Set to corresponding priority level
1101 * 0b111..Set to lowest priority, Level 8
1102 */
1103#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
1104#define ADC_TCTRL_TDLY_MASK (0xF0000U)
1105#define ADC_TCTRL_TDLY_SHIFT (16U)
1106/*! TDLY - Trigger delay select
1107 */
1108#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
1109#define ADC_TCTRL_TCMD_MASK (0xF000000U)
1110#define ADC_TCTRL_TCMD_SHIFT (24U)
1111/*! TCMD - Trigger command select
1112 * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
1113 * 0b0001..CMD1 is executed
1114 * 0b0010-0b1110..Corresponding CMD is executed
1115 * 0b1111..CMD15 is executed
1116 */
1117#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
1118/*! @} */
1119
1120/* The count of ADC_TCTRL */
1121#define ADC_TCTRL_COUNT (8U)
1122
1123/*! @name CMDL - ADC Command Low Buffer Register */
1124/*! @{ */
1125#define ADC_CMDL_ADCH_MASK (0x1FU)
1126#define ADC_CMDL_ADCH_SHIFT (0U)
1127/*! ADCH - Input channel select
1128 * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
1129 * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
1130 * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
1131 * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
1132 * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
1133 * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
1134 * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
1135 */
1136#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
1137#define ADC_CMDL_ABSEL_MASK (0x20U)
1138#define ADC_CMDL_ABSEL_SHIFT (5U)
1139/*! ABSEL - A-side vs. B-side Select
1140 * 0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB).
1141 * 0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA).
1142 */
1143#define ADC_CMDL_ABSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
1144#define ADC_CMDL_DIFF_MASK (0x40U)
1145#define ADC_CMDL_DIFF_SHIFT (6U)
1146/*! DIFF - Differential Mode Enable
1147 * 0b0..Single-ended mode.
1148 * 0b1..Differential mode.
1149 */
1150#define ADC_CMDL_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)
1151#define ADC_CMDL_CSCALE_MASK (0x2000U)
1152#define ADC_CMDL_CSCALE_SHIFT (13U)
1153/*! CSCALE - Channel Scale
1154 * 0b0..Scale selected analog channel (Factor of 30/64)
1155 * 0b1..(Default) Full scale (Factor of 1)
1156 */
1157#define ADC_CMDL_CSCALE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)
1158/*! @} */
1159
1160/* The count of ADC_CMDL */
1161#define ADC_CMDL_COUNT (15U)
1162
1163/*! @name CMDH - ADC Command High Buffer Register */
1164/*! @{ */
1165#define ADC_CMDH_CMPEN_MASK (0x3U)
1166#define ADC_CMDH_CMPEN_SHIFT (0U)
1167/*! CMPEN - Compare Function Enable
1168 * 0b00..Compare disabled.
1169 * 0b01..Reserved
1170 * 0b10..Compare enabled. Store on true.
1171 * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
1172 */
1173#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
1174#define ADC_CMDH_LWI_MASK (0x80U)
1175#define ADC_CMDH_LWI_SHIFT (7U)
1176/*! LWI - Loop with Increment
1177 * 0b0..Auto channel increment disabled
1178 * 0b1..Auto channel increment enabled
1179 */
1180#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
1181#define ADC_CMDH_STS_MASK (0x700U)
1182#define ADC_CMDH_STS_SHIFT (8U)
1183/*! STS - Sample Time Select
1184 * 0b000..Minimum sample time of 3 ADCK cycles.
1185 * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
1186 * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
1187 * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
1188 * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
1189 * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
1190 * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
1191 * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
1192 */
1193#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
1194#define ADC_CMDH_AVGS_MASK (0x7000U)
1195#define ADC_CMDH_AVGS_SHIFT (12U)
1196/*! AVGS - Hardware Average Select
1197 * 0b000..Single conversion.
1198 * 0b001..2 conversions averaged.
1199 * 0b010..4 conversions averaged.
1200 * 0b011..8 conversions averaged.
1201 * 0b100..16 conversions averaged.
1202 * 0b101..32 conversions averaged.
1203 * 0b110..64 conversions averaged.
1204 * 0b111..128 conversions averaged.
1205 */
1206#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
1207#define ADC_CMDH_LOOP_MASK (0xF0000U)
1208#define ADC_CMDH_LOOP_SHIFT (16U)
1209/*! LOOP - Loop Count Select
1210 * 0b0000..Looping not enabled. Command executes 1 time.
1211 * 0b0001..Loop 1 time. Command executes 2 times.
1212 * 0b0010..Loop 2 times. Command executes 3 times.
1213 * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
1214 * 0b1111..Loop 15 times. Command executes 16 times.
1215 */
1216#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
1217#define ADC_CMDH_NEXT_MASK (0xF000000U)
1218#define ADC_CMDH_NEXT_SHIFT (24U)
1219/*! NEXT - Next Command Select
1220 * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
1221 * trigger pending, begin command associated with lower priority trigger.
1222 * 0b0001..Select CMD1 command buffer register as next command.
1223 * 0b0010-0b1110..Select corresponding CMD command buffer register as next command
1224 * 0b1111..Select CMD15 command buffer register as next command.
1225 */
1226#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
1227/*! @} */
1228
1229/* The count of ADC_CMDH */
1230#define ADC_CMDH_COUNT (15U)
1231
1232/*! @name CV - Compare Value Register */
1233/*! @{ */
1234#define ADC_CV_CVL_MASK (0xFFFFU)
1235#define ADC_CV_CVL_SHIFT (0U)
1236/*! CVL - Compare Value Low.
1237 */
1238#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
1239#define ADC_CV_CVH_MASK (0xFFFF0000U)
1240#define ADC_CV_CVH_SHIFT (16U)
1241/*! CVH - Compare Value High.
1242 */
1243#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
1244/*! @} */
1245
1246/* The count of ADC_CV */
1247#define ADC_CV_COUNT (4U)
1248
1249/*! @name RESFIFO - ADC Data Result FIFO Register */
1250/*! @{ */
1251#define ADC_RESFIFO_D_MASK (0xFFFFU)
1252#define ADC_RESFIFO_D_SHIFT (0U)
1253/*! D - Data result
1254 */
1255#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
1256#define ADC_RESFIFO_TSRC_MASK (0x70000U)
1257#define ADC_RESFIFO_TSRC_SHIFT (16U)
1258/*! TSRC - Trigger Source
1259 * 0b000..Trigger source 0 initiated this conversion.
1260 * 0b001..Trigger source 1 initiated this conversion.
1261 * 0b010-0b110..Corresponding trigger source initiated this conversion.
1262 * 0b111..Trigger source 7 initiated this conversion.
1263 */
1264#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
1265#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U)
1266#define ADC_RESFIFO_LOOPCNT_SHIFT (20U)
1267/*! LOOPCNT - Loop count value
1268 * 0b0000..Result is from initial conversion in command.
1269 * 0b0001..Result is from second conversion in command.
1270 * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
1271 * 0b1111..Result is from 16th conversion in command.
1272 */
1273#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
1274#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U)
1275#define ADC_RESFIFO_CMDSRC_SHIFT (24U)
1276/*! CMDSRC - Command Buffer Source
1277 * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
1278 * prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
1279 * 0b0001..CMD1 buffer used as control settings for this conversion.
1280 * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
1281 * 0b1111..CMD15 buffer used as control settings for this conversion.
1282 */
1283#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
1284#define ADC_RESFIFO_VALID_MASK (0x80000000U)
1285#define ADC_RESFIFO_VALID_SHIFT (31U)
1286/*! VALID - FIFO entry is valid
1287 * 0b0..FIFO is empty. Discard any read from RESFIFO.
1288 * 0b1..FIFO record read from RESFIFO is valid.
1289 */
1290#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
1291/*! @} */
1292
1293
1294/*!
1295 * @}
1296 */ /* end of group ADC_Register_Masks */
1297
1298
1299/* ADC - Peripheral instance base addresses */
1300/** Peripheral ADMA__ADC0 base address */
1301#define ADMA__ADC0_BASE (0x5A880000u)
1302/** Peripheral ADMA__ADC0 base pointer */
1303#define ADMA__ADC0 ((ADC_Type *)ADMA__ADC0_BASE)
1304/** Array initializer of ADC peripheral base addresses */
1305#define ADC_BASE_ADDRS { ADMA__ADC0_BASE }
1306/** Array initializer of ADC peripheral base pointers */
1307#define ADC_BASE_PTRS { ADMA__ADC0 }
1308/** Interrupt vectors for the ADC peripheral type */
1309#define ADC_IRQS { ADMA_ADC0_INT_IRQn }
1310
1311/*!
1312 * @}
1313 */ /* end of group ADC_Peripheral_Access_Layer */
1314
1315
1316/* ----------------------------------------------------------------------------
1317 -- APBH Peripheral Access Layer
1318 ---------------------------------------------------------------------------- */
1319
1320/*!
1321 * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer
1322 * @{
1323 */
1324
1325/** APBH - Register Layout Typedef */
1326typedef struct {
1327 struct { /* offset: 0x0 */
1328 __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */
1329 __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */
1330 __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */
1331 __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */
1332 } CTRL0;
1333 struct { /* offset: 0x10 */
1334 __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */
1335 __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */
1336 __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */
1337 __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */
1338 } CTRL1;
1339 struct { /* offset: 0x20 */
1340 __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */
1341 __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */
1342 __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */
1343 __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */
1344 } CTRL2;
1345 struct { /* offset: 0x30 */
1346 __IO uint32_t RW; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */
1347 __IO uint32_t SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */
1348 __IO uint32_t CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */
1349 __IO uint32_t TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */
1350 } CHANNEL_CTRL;
1351 uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */
1352 uint8_t RESERVED_0[12];
1353 __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */
1354 uint8_t RESERVED_1[12];
1355 __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */
1356 uint8_t RESERVED_2[156];
1357 struct { /* offset: 0x100, array step: 0x70 */
1358 __I uint32_t CH_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, array offset: 0x100, array step: 0x70 */
1359 uint8_t RESERVED_0[12];
1360 __IO uint32_t CH_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, array offset: 0x110, array step: 0x70 */
1361 uint8_t RESERVED_1[12];
1362 __I uint32_t CH_CMD; /**< APBH DMA Channel n Command Register, array offset: 0x120, array step: 0x70 */
1363 uint8_t RESERVED_2[12];
1364 __I uint32_t CH_BAR; /**< APBH DMA Channel n Buffer Address Register, array offset: 0x130, array step: 0x70 */
1365 uint8_t RESERVED_3[12];
1366 __IO uint32_t CH_SEMA; /**< APBH DMA Channel n Semaphore Register, array offset: 0x140, array step: 0x70 */
1367 uint8_t RESERVED_4[12];
1368 __I uint32_t CH_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x150, array step: 0x70 */
1369 uint8_t RESERVED_5[12];
1370 __I uint32_t CH_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */
1371 uint8_t RESERVED_6[12];
1372 } CH_CFGn[16];
1373 __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */
1374} APBH_Type;
1375
1376/* ----------------------------------------------------------------------------
1377 -- APBH Register Masks
1378 ---------------------------------------------------------------------------- */
1379
1380/*!
1381 * @addtogroup APBH_Register_Masks APBH Register Masks
1382 * @{
1383 */
1384
1385/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */
1386/*! @{ */
1387#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU)
1388#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U)
1389/*! CLKGATE_CHANNEL - CLKGATE_CHANNEL
1390 * 0b0000000000000001..
1391 * 0b0000000000000010..
1392 * 0b0000000000000100..
1393 * 0b0000000000001000..
1394 * 0b0000000000010000..
1395 * 0b0000000000100000..
1396 * 0b0000000001000000..
1397 * 0b0000000010000000..
1398 * 0b0000000100000000..
1399 */
1400#define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK)
1401#define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U)
1402#define APBH_CTRL0_APB_BURST_EN_SHIFT (28U)
1403/*! APB_BURST_EN - APB_BURST_EN
1404 */
1405#define APBH_CTRL0_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK)
1406#define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U)
1407#define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U)
1408/*! AHB_BURST8_EN - AHB_BURST8_EN
1409 */
1410#define APBH_CTRL0_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK)
1411#define APBH_CTRL0_CLKGATE_MASK (0x40000000U)
1412#define APBH_CTRL0_CLKGATE_SHIFT (30U)
1413/*! CLKGATE - CLKGATE
1414 */
1415#define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK)
1416#define APBH_CTRL0_SFTRST_MASK (0x80000000U)
1417#define APBH_CTRL0_SFTRST_SHIFT (31U)
1418/*! SFTRST - SFTRST
1419 */
1420#define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK)
1421/*! @} */
1422
1423/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */
1424/*! @{ */
1425#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1426#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1427/*! CH0_CMDCMPLT_IRQ - CH0_CMDCMPLT_IRQ
1428 */
1429#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK)
1430#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1431#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1432/*! CH1_CMDCMPLT_IRQ - CH1_CMDCMPLT_IRQ
1433 */
1434#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK)
1435#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1436#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1437/*! CH2_CMDCMPLT_IRQ - CH2_CMDCMPLT_IRQ
1438 */
1439#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK)
1440#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1441#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1442/*! CH3_CMDCMPLT_IRQ - CH3_CMDCMPLT_IRQ
1443 */
1444#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK)
1445#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1446#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1447/*! CH4_CMDCMPLT_IRQ - CH4_CMDCMPLT_IRQ
1448 */
1449#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK)
1450#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1451#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1452/*! CH5_CMDCMPLT_IRQ - CH5_CMDCMPLT_IRQ
1453 */
1454#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK)
1455#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1456#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1457/*! CH6_CMDCMPLT_IRQ - CH6_CMDCMPLT_IRQ
1458 */
1459#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK)
1460#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1461#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1462/*! CH7_CMDCMPLT_IRQ - CH7_CMDCMPLT_IRQ
1463 */
1464#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK)
1465#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1466#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1467/*! CH8_CMDCMPLT_IRQ - CH8_CMDCMPLT_IRQ
1468 */
1469#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK)
1470#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1471#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1472/*! CH9_CMDCMPLT_IRQ - CH9_CMDCMPLT_IRQ
1473 */
1474#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK)
1475#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1476#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1477/*! CH10_CMDCMPLT_IRQ - CH10_CMDCMPLT_IRQ
1478 */
1479#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK)
1480#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1481#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1482/*! CH11_CMDCMPLT_IRQ - CH11_CMDCMPLT_IRQ
1483 */
1484#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK)
1485#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1486#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1487/*! CH12_CMDCMPLT_IRQ - CH12_CMDCMPLT_IRQ
1488 */
1489#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK)
1490#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1491#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1492/*! CH13_CMDCMPLT_IRQ - CH13_CMDCMPLT_IRQ
1493 */
1494#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK)
1495#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1496#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1497/*! CH14_CMDCMPLT_IRQ - CH14_CMDCMPLT_IRQ
1498 */
1499#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK)
1500#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1501#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1502/*! CH15_CMDCMPLT_IRQ - CH15_CMDCMPLT_IRQ
1503 */
1504#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK)
1505#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1506#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
1507/*! CH0_CMDCMPLT_IRQ_EN - CH0_CMDCMPLT_IRQ_EN
1508 */
1509#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK)
1510#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
1511#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
1512/*! CH1_CMDCMPLT_IRQ_EN - CH1_CMDCMPLT_IRQ_EN
1513 */
1514#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK)
1515#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
1516#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
1517/*! CH2_CMDCMPLT_IRQ_EN - CH2_CMDCMPLT_IRQ_EN
1518 */
1519#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK)
1520#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
1521#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
1522/*! CH3_CMDCMPLT_IRQ_EN - CH3_CMDCMPLT_IRQ_EN
1523 */
1524#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK)
1525#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
1526#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
1527/*! CH4_CMDCMPLT_IRQ_EN - CH4_CMDCMPLT_IRQ_EN
1528 */
1529#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK)
1530#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
1531#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
1532/*! CH5_CMDCMPLT_IRQ_EN - CH5_CMDCMPLT_IRQ_EN
1533 */
1534#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK)
1535#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
1536#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
1537/*! CH6_CMDCMPLT_IRQ_EN - CH6_CMDCMPLT_IRQ_EN
1538 */
1539#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK)
1540#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
1541#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
1542/*! CH7_CMDCMPLT_IRQ_EN - CH7_CMDCMPLT_IRQ_EN
1543 */
1544#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK)
1545#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
1546#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
1547/*! CH8_CMDCMPLT_IRQ_EN - CH8_CMDCMPLT_IRQ_EN
1548 */
1549#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK)
1550#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
1551#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
1552/*! CH9_CMDCMPLT_IRQ_EN - CH9_CMDCMPLT_IRQ_EN
1553 */
1554#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK)
1555#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
1556#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
1557/*! CH10_CMDCMPLT_IRQ_EN - CH10_CMDCMPLT_IRQ_EN
1558 */
1559#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
1560#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
1561#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
1562/*! CH11_CMDCMPLT_IRQ_EN - CH11_CMDCMPLT_IRQ_EN
1563 */
1564#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK)
1565#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
1566#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
1567/*! CH12_CMDCMPLT_IRQ_EN - CH12_CMDCMPLT_IRQ_EN
1568 */
1569#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK)
1570#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
1571#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
1572/*! CH13_CMDCMPLT_IRQ_EN - CH13_CMDCMPLT_IRQ_EN
1573 */
1574#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK)
1575#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
1576#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
1577/*! CH14_CMDCMPLT_IRQ_EN - CH14_CMDCMPLT_IRQ_EN
1578 */
1579#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK)
1580#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
1581#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
1582/*! CH15_CMDCMPLT_IRQ_EN - CH15_CMDCMPLT_IRQ_EN
1583 */
1584#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK)
1585/*! @} */
1586
1587/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */
1588/*! @{ */
1589#define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U)
1590#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U)
1591/*! CH0_ERROR_IRQ - CH0_ERROR_IRQ
1592 */
1593#define APBH_CTRL2_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK)
1594#define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U)
1595#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U)
1596/*! CH1_ERROR_IRQ - CH1_ERROR_IRQ
1597 */
1598#define APBH_CTRL2_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK)
1599#define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U)
1600#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U)
1601/*! CH2_ERROR_IRQ - CH2_ERROR_IRQ
1602 */
1603#define APBH_CTRL2_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK)
1604#define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U)
1605#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U)
1606/*! CH3_ERROR_IRQ - CH3_ERROR_IRQ
1607 */
1608#define APBH_CTRL2_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK)
1609#define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U)
1610#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U)
1611/*! CH4_ERROR_IRQ - CH4_ERROR_IRQ
1612 */
1613#define APBH_CTRL2_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK)
1614#define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U)
1615#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U)
1616/*! CH5_ERROR_IRQ - CH5_ERROR_IRQ
1617 */
1618#define APBH_CTRL2_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK)
1619#define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U)
1620#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U)
1621/*! CH6_ERROR_IRQ - CH6_ERROR_IRQ
1622 */
1623#define APBH_CTRL2_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK)
1624#define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U)
1625#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U)
1626/*! CH7_ERROR_IRQ - CH7_ERROR_IRQ
1627 */
1628#define APBH_CTRL2_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK)
1629#define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U)
1630#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U)
1631/*! CH8_ERROR_IRQ - CH8_ERROR_IRQ
1632 */
1633#define APBH_CTRL2_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK)
1634#define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U)
1635#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U)
1636/*! CH9_ERROR_IRQ - CH9_ERROR_IRQ
1637 */
1638#define APBH_CTRL2_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK)
1639#define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U)
1640#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U)
1641/*! CH10_ERROR_IRQ - CH10_ERROR_IRQ
1642 */
1643#define APBH_CTRL2_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK)
1644#define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U)
1645#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U)
1646/*! CH11_ERROR_IRQ - CH11_ERROR_IRQ
1647 */
1648#define APBH_CTRL2_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK)
1649#define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U)
1650#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U)
1651/*! CH12_ERROR_IRQ - CH12_ERROR_IRQ
1652 */
1653#define APBH_CTRL2_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK)
1654#define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U)
1655#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U)
1656/*! CH13_ERROR_IRQ - CH13_ERROR_IRQ
1657 */
1658#define APBH_CTRL2_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK)
1659#define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U)
1660#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U)
1661/*! CH14_ERROR_IRQ - CH14_ERROR_IRQ
1662 */
1663#define APBH_CTRL2_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK)
1664#define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U)
1665#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U)
1666/*! CH15_ERROR_IRQ - CH15_ERROR_IRQ
1667 */
1668#define APBH_CTRL2_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK)
1669#define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U)
1670#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U)
1671/*! CH0_ERROR_STATUS - CH0_ERROR_STATUS
1672 * 0b0..An early termination from the device causes error IRQ.
1673 * 0b1..An AHB bus error causes error IRQ.
1674 */
1675#define APBH_CTRL2_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK)
1676#define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U)
1677#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U)
1678/*! CH1_ERROR_STATUS - CH1_ERROR_STATUS
1679 * 0b0..An early termination from the device causes error IRQ.
1680 * 0b1..An AHB bus error causes error IRQ.
1681 */
1682#define APBH_CTRL2_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK)
1683#define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U)
1684#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U)
1685/*! CH2_ERROR_STATUS - CH2_ERROR_STATUS
1686 * 0b0..An early termination from the device causes error IRQ.
1687 * 0b1..An AHB bus error causes error IRQ.
1688 */
1689#define APBH_CTRL2_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK)
1690#define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U)
1691#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U)
1692/*! CH3_ERROR_STATUS - CH3_ERROR_STATUS
1693 * 0b0..An early termination from the device causes error IRQ.
1694 * 0b1..An AHB bus error causes error IRQ.
1695 */
1696#define APBH_CTRL2_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK)
1697#define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U)
1698#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U)
1699/*! CH4_ERROR_STATUS - CH4_ERROR_STATUS
1700 * 0b0..An early termination from the device causes error IRQ.
1701 * 0b1..An AHB bus error causes error IRQ.
1702 */
1703#define APBH_CTRL2_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK)
1704#define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U)
1705#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U)
1706/*! CH5_ERROR_STATUS - CH5_ERROR_STATUS
1707 * 0b0..An early termination from the device causes error IRQ.
1708 * 0b1..An AHB bus error causes error IRQ.
1709 */
1710#define APBH_CTRL2_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK)
1711#define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U)
1712#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U)
1713/*! CH6_ERROR_STATUS - CH6_ERROR_STATUS
1714 * 0b0..An early termination from the device causes error IRQ.
1715 * 0b1..An AHB bus error causes error IRQ.
1716 */
1717#define APBH_CTRL2_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK)
1718#define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U)
1719#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U)
1720/*! CH7_ERROR_STATUS - CH7_ERROR_STATUS
1721 * 0b0..An early termination from the device causes error IRQ.
1722 * 0b1..An AHB bus error causes error IRQ.
1723 */
1724#define APBH_CTRL2_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK)
1725#define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U)
1726#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U)
1727/*! CH8_ERROR_STATUS - CH8_ERROR_STATUS
1728 * 0b0..An early termination from the device causes error IRQ.
1729 * 0b1..An AHB bus error causes error IRQ.
1730 */
1731#define APBH_CTRL2_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK)
1732#define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U)
1733#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U)
1734/*! CH9_ERROR_STATUS - CH9_ERROR_STATUS
1735 * 0b0..An early termination from the device causes error IRQ.
1736 * 0b1..An AHB bus error causes error IRQ.
1737 */
1738#define APBH_CTRL2_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK)
1739#define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U)
1740#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U)
1741/*! CH10_ERROR_STATUS - CH10_ERROR_STATUS
1742 * 0b0..An early termination from the device causes error IRQ.
1743 * 0b1..An AHB bus error causes error IRQ.
1744 */
1745#define APBH_CTRL2_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK)
1746#define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U)
1747#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U)
1748/*! CH11_ERROR_STATUS - CH11_ERROR_STATUS
1749 * 0b0..An early termination from the device causes error IRQ.
1750 * 0b1..An AHB bus error causes error IRQ.
1751 */
1752#define APBH_CTRL2_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK)
1753#define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U)
1754#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U)
1755/*! CH12_ERROR_STATUS - CH12_ERROR_STATUS
1756 * 0b0..An early termination from the device causes error IRQ.
1757 * 0b1..An AHB bus error causes error IRQ.
1758 */
1759#define APBH_CTRL2_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK)
1760#define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U)
1761#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U)
1762/*! CH13_ERROR_STATUS - CH13_ERROR_STATUS
1763 * 0b0..An early termination from the device causes error IRQ.
1764 * 0b1..An AHB bus error causes error IRQ.
1765 */
1766#define APBH_CTRL2_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK)
1767#define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U)
1768#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U)
1769/*! CH14_ERROR_STATUS - CH14_ERROR_STATUS
1770 * 0b0..An early termination from the device causes error IRQ.
1771 * 0b1..An AHB bus error causes error IRQ.
1772 */
1773#define APBH_CTRL2_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK)
1774#define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U)
1775#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U)
1776/*! CH15_ERROR_STATUS - CH15_ERROR_STATUS
1777 * 0b0..An early termination from the device causes error IRQ.
1778 * 0b1..An AHB bus error causes error IRQ.
1779 */
1780#define APBH_CTRL2_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK)
1781/*! @} */
1782
1783/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */
1784/*! @{ */
1785#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU)
1786#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U)
1787/*! FREEZE_CHANNEL - FREEZE_CHANNEL
1788 * 0b0000000000000001..
1789 * 0b0000000000000010..
1790 * 0b0000000000000100..
1791 * 0b0000000000001000..
1792 * 0b0000000000010000..
1793 * 0b0000000000100000..
1794 * 0b0000000001000000..
1795 * 0b0000000010000000..
1796 * 0b0000000100000000..
1797 */
1798#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK)
1799#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U)
1800#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U)
1801/*! RESET_CHANNEL - RESET_CHANNEL
1802 * 0b0000000000000001..
1803 * 0b0000000000000010..
1804 * 0b0000000000000100..
1805 * 0b0000000000001000..
1806 * 0b0000000000010000..
1807 * 0b0000000000100000..
1808 * 0b0000000001000000..
1809 * 0b0000000010000000..
1810 * 0b0000000100000000..
1811 */
1812#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK)
1813/*! @} */
1814
1815/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */
1816/*! @{ */
1817#define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U)
1818#define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U)
1819/*! CH0 - CH0
1820 */
1821#define APBH_DMA_BURST_SIZE_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK)
1822#define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU)
1823#define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U)
1824/*! CH1 - CH1
1825 */
1826#define APBH_DMA_BURST_SIZE_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK)
1827#define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U)
1828#define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U)
1829/*! CH2 - CH2
1830 */
1831#define APBH_DMA_BURST_SIZE_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK)
1832#define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U)
1833#define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U)
1834/*! CH3 - CH3
1835 */
1836#define APBH_DMA_BURST_SIZE_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK)
1837#define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U)
1838#define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U)
1839/*! CH4 - CH4
1840 */
1841#define APBH_DMA_BURST_SIZE_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK)
1842#define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U)
1843#define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U)
1844/*! CH5 - CH5
1845 */
1846#define APBH_DMA_BURST_SIZE_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK)
1847#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U)
1848#define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U)
1849/*! CH6 - CH6
1850 */
1851#define APBH_DMA_BURST_SIZE_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK)
1852#define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U)
1853#define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U)
1854/*! CH7 - CH7
1855 */
1856#define APBH_DMA_BURST_SIZE_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK)
1857#define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U)
1858#define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U)
1859/*! CH8 - CH8
1860 * 0b00..
1861 * 0b01..
1862 * 0b10..
1863 */
1864#define APBH_DMA_BURST_SIZE_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK)
1865/*! @} */
1866
1867/*! @name DEBUG - AHB to APBH DMA Debug Register */
1868/*! @{ */
1869#define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U)
1870#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U)
1871/*! GPMI_ONE_FIFO - GPMI_ONE_FIFO
1872 */
1873#define APBH_DEBUG_GPMI_ONE_FIFO(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK)
1874/*! @} */
1875
1876/*! @name CH_CURCMDAR - APBH DMA Channel n Current Command Address Register */
1877/*! @{ */
1878#define APBH_CH_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
1879#define APBH_CH_CURCMDAR_CMD_ADDR_SHIFT (0U)
1880/*! CMD_ADDR - CMD_ADDR
1881 */
1882#define APBH_CH_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_CURCMDAR_CMD_ADDR_MASK)
1883/*! @} */
1884
1885/* The count of APBH_CH_CURCMDAR */
1886#define APBH_CH_CURCMDAR_COUNT (16U)
1887
1888/*! @name CH_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
1889/*! @{ */
1890#define APBH_CH_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
1891#define APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT (0U)
1892/*! CMD_ADDR - CMD_ADDR
1893 */
1894#define APBH_CH_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_NXTCMDAR_CMD_ADDR_MASK)
1895/*! @} */
1896
1897/* The count of APBH_CH_NXTCMDAR */
1898#define APBH_CH_NXTCMDAR_COUNT (16U)
1899
1900/*! @name CH_CMD - APBH DMA Channel n Command Register */
1901/*! @{ */
1902#define APBH_CH_CMD_COMMAND_MASK (0x3U)
1903#define APBH_CH_CMD_COMMAND_SHIFT (0U)
1904/*! COMMAND - COMMAND
1905 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
1906 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
1907 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
1908 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained
1909 * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain
1910 * pointer if the peripheral sense line is false.
1911 */
1912#define APBH_CH_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_COMMAND_SHIFT)) & APBH_CH_CMD_COMMAND_MASK)
1913#define APBH_CH_CMD_CHAIN_MASK (0x4U)
1914#define APBH_CH_CMD_CHAIN_SHIFT (2U)
1915/*! CHAIN - CHAIN
1916 */
1917#define APBH_CH_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CHAIN_SHIFT)) & APBH_CH_CMD_CHAIN_MASK)
1918#define APBH_CH_CMD_IRQONCMPLT_MASK (0x8U)
1919#define APBH_CH_CMD_IRQONCMPLT_SHIFT (3U)
1920/*! IRQONCMPLT - IRQONCMPLT
1921 */
1922#define APBH_CH_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_IRQONCMPLT_SHIFT)) & APBH_CH_CMD_IRQONCMPLT_MASK)
1923#define APBH_CH_CMD_NANDLOCK_MASK (0x10U)
1924#define APBH_CH_CMD_NANDLOCK_SHIFT (4U)
1925/*! NANDLOCK - NANDLOCK
1926 */
1927#define APBH_CH_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDLOCK_SHIFT)) & APBH_CH_CMD_NANDLOCK_MASK)
1928#define APBH_CH_CMD_NANDWAIT4READY_MASK (0x20U)
1929#define APBH_CH_CMD_NANDWAIT4READY_SHIFT (5U)
1930/*! NANDWAIT4READY - NANDWAIT4READY
1931 */
1932#define APBH_CH_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH_CMD_NANDWAIT4READY_MASK)
1933#define APBH_CH_CMD_SEMAPHORE_MASK (0x40U)
1934#define APBH_CH_CMD_SEMAPHORE_SHIFT (6U)
1935/*! SEMAPHORE - SEMAPHORE
1936 */
1937#define APBH_CH_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_SEMAPHORE_SHIFT)) & APBH_CH_CMD_SEMAPHORE_MASK)
1938#define APBH_CH_CMD_WAIT4ENDCMD_MASK (0x80U)
1939#define APBH_CH_CMD_WAIT4ENDCMD_SHIFT (7U)
1940/*! WAIT4ENDCMD - WAIT4ENDCMD
1941 */
1942#define APBH_CH_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH_CMD_WAIT4ENDCMD_MASK)
1943#define APBH_CH_CMD_HALTONTERMINATE_MASK (0x100U)
1944#define APBH_CH_CMD_HALTONTERMINATE_SHIFT (8U)
1945/*! HALTONTERMINATE - HALTONTERMINATE
1946 */
1947#define APBH_CH_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH_CMD_HALTONTERMINATE_MASK)
1948#define APBH_CH_CMD_CMDWORDS_MASK (0xF000U)
1949#define APBH_CH_CMD_CMDWORDS_SHIFT (12U)
1950/*! CMDWORDS - CMDWORDS
1951 */
1952#define APBH_CH_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CMDWORDS_SHIFT)) & APBH_CH_CMD_CMDWORDS_MASK)
1953#define APBH_CH_CMD_XFER_COUNT_MASK (0xFFFF0000U)
1954#define APBH_CH_CMD_XFER_COUNT_SHIFT (16U)
1955/*! XFER_COUNT - XFER_COUNT
1956 */
1957#define APBH_CH_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_XFER_COUNT_SHIFT)) & APBH_CH_CMD_XFER_COUNT_MASK)
1958/*! @} */
1959
1960/* The count of APBH_CH_CMD */
1961#define APBH_CH_CMD_COUNT (16U)
1962
1963/*! @name CH_BAR - APBH DMA Channel n Buffer Address Register */
1964/*! @{ */
1965#define APBH_CH_BAR_ADDRESS_MASK (0xFFFFFFFFU)
1966#define APBH_CH_BAR_ADDRESS_SHIFT (0U)
1967/*! ADDRESS - ADDRESS
1968 */
1969#define APBH_CH_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_BAR_ADDRESS_SHIFT)) & APBH_CH_BAR_ADDRESS_MASK)
1970/*! @} */
1971
1972/* The count of APBH_CH_BAR */
1973#define APBH_CH_BAR_COUNT (16U)
1974
1975/*! @name CH_SEMA - APBH DMA Channel n Semaphore Register */
1976/*! @{ */
1977#define APBH_CH_SEMA_INCREMENT_SEMA_MASK (0xFFU)
1978#define APBH_CH_SEMA_INCREMENT_SEMA_SHIFT (0U)
1979/*! INCREMENT_SEMA - INCREMENT_SEMA
1980 */
1981#define APBH_CH_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH_SEMA_INCREMENT_SEMA_MASK)
1982#define APBH_CH_SEMA_PHORE_MASK (0xFF0000U)
1983#define APBH_CH_SEMA_PHORE_SHIFT (16U)
1984/*! PHORE - PHORE
1985 */
1986#define APBH_CH_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_PHORE_SHIFT)) & APBH_CH_SEMA_PHORE_MASK)
1987/*! @} */
1988
1989/* The count of APBH_CH_SEMA */
1990#define APBH_CH_SEMA_COUNT (16U)
1991
1992/*! @name CH_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
1993/*! @{ */
1994#define APBH_CH_DEBUG1_STATEMACHINE_MASK (0x1FU)
1995#define APBH_CH_DEBUG1_STATEMACHINE_SHIFT (0U)
1996/*! STATEMACHINE - STATEMACHINE
1997 * 0b00000..This is the idle state of the DMA state machine.
1998 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
1999 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
2000 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
2001 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
2002 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
2003 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the
2004 * PIO words when PIO count is greater than 1.
2005 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
2006 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
2007 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
2008 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
2009 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
2010 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
2011 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
2012 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
2013 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
2014 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
2015 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and
2016 * effectively halts. A channel reset is required to exit this state
2017 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
2018 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device
2019 * indicates that the external device is ready.
2020 */
2021#define APBH_CH_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH_DEBUG1_STATEMACHINE_MASK)
2022#define APBH_CH_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
2023#define APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
2024/*! WR_FIFO_FULL - WR_FIFO_FULL
2025 */
2026#define APBH_CH_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_FULL_MASK)
2027#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
2028#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
2029/*! WR_FIFO_EMPTY - WR_FIFO_EMPTY
2030 */
2031#define APBH_CH_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK)
2032#define APBH_CH_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
2033#define APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
2034/*! RD_FIFO_FULL - RD_FIFO_FULL
2035 */
2036#define APBH_CH_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_FULL_MASK)
2037#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
2038#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
2039/*! RD_FIFO_EMPTY - RD_FIFO_EMPTY
2040 */
2041#define APBH_CH_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK)
2042#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
2043#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
2044/*! NEXTCMDADDRVALID - NEXTCMDADDRVALID
2045 */
2046#define APBH_CH_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK)
2047#define APBH_CH_DEBUG1_READY_MASK (0x4000000U)
2048#define APBH_CH_DEBUG1_READY_SHIFT (26U)
2049/*! READY - READY
2050 */
2051#define APBH_CH_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_READY_SHIFT)) & APBH_CH_DEBUG1_READY_MASK)
2052#define APBH_CH_DEBUG1_END_MASK (0x10000000U)
2053#define APBH_CH_DEBUG1_END_SHIFT (28U)
2054/*! END - END
2055 */
2056#define APBH_CH_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_END_SHIFT)) & APBH_CH_DEBUG1_END_MASK)
2057#define APBH_CH_DEBUG1_KICK_MASK (0x20000000U)
2058#define APBH_CH_DEBUG1_KICK_SHIFT (29U)
2059/*! KICK - KICK
2060 */
2061#define APBH_CH_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_KICK_SHIFT)) & APBH_CH_DEBUG1_KICK_MASK)
2062#define APBH_CH_DEBUG1_BURST_MASK (0x40000000U)
2063#define APBH_CH_DEBUG1_BURST_SHIFT (30U)
2064/*! BURST - BURST
2065 */
2066#define APBH_CH_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_BURST_SHIFT)) & APBH_CH_DEBUG1_BURST_MASK)
2067#define APBH_CH_DEBUG1_REQ_MASK (0x80000000U)
2068#define APBH_CH_DEBUG1_REQ_SHIFT (31U)
2069/*! REQ - REQ
2070 */
2071#define APBH_CH_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_REQ_SHIFT)) & APBH_CH_DEBUG1_REQ_MASK)
2072/*! @} */
2073
2074/* The count of APBH_CH_DEBUG1 */
2075#define APBH_CH_DEBUG1_COUNT (16U)
2076
2077/*! @name CH_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
2078/*! @{ */
2079#define APBH_CH_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
2080#define APBH_CH_DEBUG2_AHB_BYTES_SHIFT (0U)
2081/*! AHB_BYTES - AHB_BYTES
2082 */
2083#define APBH_CH_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH_DEBUG2_AHB_BYTES_MASK)
2084#define APBH_CH_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
2085#define APBH_CH_DEBUG2_APB_BYTES_SHIFT (16U)
2086/*! APB_BYTES - APB_BYTES
2087 */
2088#define APBH_CH_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH_DEBUG2_APB_BYTES_MASK)
2089/*! @} */
2090
2091/* The count of APBH_CH_DEBUG2 */
2092#define APBH_CH_DEBUG2_COUNT (16U)
2093
2094/*! @name VERSION - APBH Bridge Version Register */
2095/*! @{ */
2096#define APBH_VERSION_STEP_MASK (0xFFFFU)
2097#define APBH_VERSION_STEP_SHIFT (0U)
2098/*! STEP - STEP
2099 */
2100#define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK)
2101#define APBH_VERSION_MINOR_MASK (0xFF0000U)
2102#define APBH_VERSION_MINOR_SHIFT (16U)
2103/*! MINOR - MINOR
2104 */
2105#define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK)
2106#define APBH_VERSION_MAJOR_MASK (0xFF000000U)
2107#define APBH_VERSION_MAJOR_SHIFT (24U)
2108/*! MAJOR - MAJOR
2109 */
2110#define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK)
2111/*! @} */
2112
2113
2114/*!
2115 * @}
2116 */ /* end of group APBH_Register_Masks */
2117
2118
2119/* APBH - Peripheral instance base addresses */
2120/** Peripheral CONNECTIVITY__APBH base address */
2121#define CONNECTIVITY__APBH_BASE (0x5B810000u)
2122/** Peripheral CONNECTIVITY__APBH base pointer */
2123#define CONNECTIVITY__APBH ((APBH_Type *)CONNECTIVITY__APBH_BASE)
2124/** Array initializer of APBH peripheral base addresses */
2125#define APBH_BASE_ADDRS { CONNECTIVITY__APBH_BASE }
2126/** Array initializer of APBH peripheral base pointers */
2127#define APBH_BASE_PTRS { CONNECTIVITY__APBH }
2128/** Interrupt vectors for the APBH peripheral type */
2129#define APBH_IRQS { CONNECTIVITY_APBHDMA_IRQn }
2130
2131/*!
2132 * @}
2133 */ /* end of group APBH_Peripheral_Access_Layer */
2134
2135
2136/* ----------------------------------------------------------------------------
2137 -- ASMC Peripheral Access Layer
2138 ---------------------------------------------------------------------------- */
2139
2140/*!
2141 * @addtogroup ASMC_Peripheral_Access_Layer ASMC Peripheral Access Layer
2142 * @{
2143 */
2144
2145/** ASMC - Register Layout Typedef */
2146typedef struct {
2147 __I uint32_t SRS; /**< System Reset Status Register, offset: 0x0 */
2148 uint8_t RESERVED_0[4];
2149 __IO uint32_t PMPROT; /**< Power Mode Protection register, offset: 0x8 */
2150 __IO uint32_t PMCTRL; /**< Power Mode Control register, offset: 0xC */
2151 __IO uint32_t STOPCTRL; /**< Stop Control Register, offset: 0x10 */
2152 __I uint32_t PMSTAT; /**< Power Mode Status register, offset: 0x14 */
2153} ASMC_Type;
2154
2155/* ----------------------------------------------------------------------------
2156 -- ASMC Register Masks
2157 ---------------------------------------------------------------------------- */
2158
2159/*!
2160 * @addtogroup ASMC_Register_Masks ASMC Register Masks
2161 * @{
2162 */
2163
2164/*! @name SRS - System Reset Status Register */
2165/*! @{ */
2166#define ASMC_SRS_WAKEUP_MASK (0x1U)
2167#define ASMC_SRS_WAKEUP_SHIFT (0U)
2168/*! WAKEUP - Low Leakage Wakeup Reset
2169 * 0b0..Reset not caused by LLWU module wakeup source
2170 * 0b1..Reset caused by LLWU module wakeup source
2171 */
2172#define ASMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WAKEUP_SHIFT)) & ASMC_SRS_WAKEUP_MASK)
2173#define ASMC_SRS_WDOG1_MASK (0x20U)
2174#define ASMC_SRS_WDOG1_SHIFT (5U)
2175/*! WDOG1 - Watchdog
2176 * 0b0..Reset not caused by watchdog timeout
2177 * 0b1..Reset caused by watchdog timeout
2178 */
2179#define ASMC_SRS_WDOG1(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WDOG1_SHIFT)) & ASMC_SRS_WDOG1_MASK)
2180#define ASMC_SRS_RES_MASK (0x40U)
2181#define ASMC_SRS_RES_SHIFT (6U)
2182/*! RES - Chip Reset not POR
2183 * 0b0..Chip Reset did not occur
2184 * 0b1..Chip Reset caused by a source other than POR occured
2185 */
2186#define ASMC_SRS_RES(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_RES_SHIFT)) & ASMC_SRS_RES_MASK)
2187#define ASMC_SRS_POR_MASK (0x80U)
2188#define ASMC_SRS_POR_SHIFT (7U)
2189/*! POR - Power-On Reset
2190 * 0b0..Reset not caused by POR
2191 * 0b1..Reset caused by POR
2192 */
2193#define ASMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_POR_SHIFT)) & ASMC_SRS_POR_MASK)
2194#define ASMC_SRS_LOCKUP_MASK (0x200U)
2195#define ASMC_SRS_LOCKUP_SHIFT (9U)
2196/*! LOCKUP - Core 1 Lockup
2197 * 0b0..Reset not caused by core LOCKUP event
2198 * 0b1..Reset caused by core LOCKUP event
2199 */
2200#define ASMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_LOCKUP_SHIFT)) & ASMC_SRS_LOCKUP_MASK)
2201#define ASMC_SRS_SW_MASK (0x400U)
2202#define ASMC_SRS_SW_SHIFT (10U)
2203/*! SW - Software
2204 * 0b0..Reset not caused by software setting of SYSRESETREQ bit
2205 * 0b1..Reset caused by software setting of SYSRESETREQ bit
2206 */
2207#define ASMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SW_SHIFT)) & ASMC_SRS_SW_MASK)
2208#define ASMC_SRS_SACKERR_MASK (0x1000U)
2209#define ASMC_SRS_SACKERR_SHIFT (12U)
2210/*! SACKERR - Stop Mode Acknowledge Error Reset
2211 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
2212 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
2213 */
2214#define ASMC_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SACKERR_SHIFT)) & ASMC_SRS_SACKERR_MASK)
2215/*! @} */
2216
2217/*! @name PMPROT - Power Mode Protection register */
2218/*! @{ */
2219#define ASMC_PMPROT_AVLLS_MASK (0x2U)
2220#define ASMC_PMPROT_AVLLS_SHIFT (1U)
2221/*! AVLLS - Allow Very-Low-Leakage Stop Mode
2222 * 0b0..Not Allowed
2223 * 0b1..Allowed
2224 */
2225#define ASMC_PMPROT_AVLLS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLLS_SHIFT)) & ASMC_PMPROT_AVLLS_MASK)
2226#define ASMC_PMPROT_ALLS_MASK (0x8U)
2227#define ASMC_PMPROT_ALLS_SHIFT (3U)
2228/*! ALLS - Allow Low-Leakage Stop Mode
2229 * 0b0..Not Allowed
2230 * 0b1..Allowed
2231 */
2232#define ASMC_PMPROT_ALLS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_ALLS_SHIFT)) & ASMC_PMPROT_ALLS_MASK)
2233#define ASMC_PMPROT_AVLP_MASK (0x20U)
2234#define ASMC_PMPROT_AVLP_SHIFT (5U)
2235/*! AVLP - Allow Very-Low-Power Modes
2236 * 0b0..VLPR, VLPW, and VLPS are not allowed.
2237 * 0b1..VLPR, VLPW, and VLPS are allowed.
2238 */
2239#define ASMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLP_SHIFT)) & ASMC_PMPROT_AVLP_MASK)
2240#define ASMC_PMPROT_AHSRUN_MASK (0x80U)
2241#define ASMC_PMPROT_AHSRUN_SHIFT (7U)
2242/*! AHSRUN - Allow High Speed Run mode
2243 * 0b0..HSRUN is not allowed
2244 * 0b1..HSRUN is allowed
2245 */
2246#define ASMC_PMPROT_AHSRUN(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AHSRUN_SHIFT)) & ASMC_PMPROT_AHSRUN_MASK)
2247/*! @} */
2248
2249/*! @name PMCTRL - Power Mode Control register */
2250/*! @{ */
2251#define ASMC_PMCTRL_STOPM_MASK (0x7U)
2252#define ASMC_PMCTRL_STOPM_SHIFT (0U)
2253/*! STOPM - Stop Mode Control
2254 * 0b000..Normal Stop (STOP)
2255 * 0b001..Reserved
2256 * 0b010..Very-Low-Power Stop (VLPS)
2257 * 0b011..Low-leakage stop
2258 * 0b100..Very-low-leakage stop
2259 * 0b101..Reserved
2260 * 0b110..Reseved
2261 * 0b111..Reserved
2262 */
2263#define ASMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_STOPM_SHIFT)) & ASMC_PMCTRL_STOPM_MASK)
2264#define ASMC_PMCTRL_RUNM_MASK (0x60U)
2265#define ASMC_PMCTRL_RUNM_SHIFT (5U)
2266/*! RUNM - Run Mode Control
2267 * 0b00..Normal Run mode (RUN)
2268 * 0b01..Reserved
2269 * 0b10..Very-Low-Power Run mode (VLPR)
2270 * 0b11..High Speed Run mode (HSRUN)
2271 */
2272#define ASMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_RUNM_SHIFT)) & ASMC_PMCTRL_RUNM_MASK)
2273/*! @} */
2274
2275/*! @name STOPCTRL - Stop Control Register */
2276/*! @{ */
2277#define ASMC_STOPCTRL_PSTOPO_MASK (0xC0U)
2278#define ASMC_STOPCTRL_PSTOPO_SHIFT (6U)
2279/*! PSTOPO - Partial Stop Option
2280 * 0b00..STOP - Normal Stop mode
2281 * 0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled
2282 * 0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
2283 * 0b11..Reserved
2284 */
2285#define ASMC_STOPCTRL_PSTOPO(x) (((uint32_t)(((uint32_t)(x)) << ASMC_STOPCTRL_PSTOPO_SHIFT)) & ASMC_STOPCTRL_PSTOPO_MASK)
2286/*! @} */
2287
2288/*! @name PMSTAT - Power Mode Status register */
2289/*! @{ */
2290#define ASMC_PMSTAT_PMSTAT_MASK (0xFFU) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */
2291#define ASMC_PMSTAT_PMSTAT_SHIFT (0U)
2292/*! PMSTAT - Power Mode Status
2293 * 0b00000001..Current power mode is RUN.
2294 * 0b00000010..Current power mode is STOP.
2295 * 0b00000100..Current power mode is VLPR.
2296 * 0b00001000..Current power mode is VLPW.
2297 * 0b00010000..Current power mode is VLPS.
2298 * 0b00100000..Current power mode is LLS.
2299 * 0b01000000..Current power mode is VLLS.
2300 * 0b10000000..Current power mode is HSRUN
2301 */
2302#define ASMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMSTAT_PMSTAT_SHIFT)) & ASMC_PMSTAT_PMSTAT_MASK) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */
2303/*! @} */
2304
2305
2306/*!
2307 * @}
2308 */ /* end of group ASMC_Register_Masks */
2309
2310
2311/* ASMC - Peripheral instance base addresses */
2312/** Peripheral CM4__ASMC base address */
2313#define CM4__ASMC_BASE (0x41410000u)
2314/** Peripheral CM4__ASMC base pointer */
2315#define CM4__ASMC ((ASMC_Type *)CM4__ASMC_BASE)
2316/** Peripheral SCU__ASMC base address */
2317#define SCU__ASMC_BASE (0x33410000u)
2318/** Peripheral SCU__ASMC base pointer */
2319#define SCU__ASMC ((ASMC_Type *)SCU__ASMC_BASE)
2320/** Array initializer of ASMC peripheral base addresses */
2321#define ASMC_BASE_ADDRS { CM4__ASMC_BASE, SCU__ASMC_BASE }
2322/** Array initializer of ASMC peripheral base pointers */
2323#define ASMC_BASE_PTRS { CM4__ASMC, SCU__ASMC }
2324
2325/*!
2326 * @}
2327 */ /* end of group ASMC_Peripheral_Access_Layer */
2328
2329
2330/* ----------------------------------------------------------------------------
2331 -- ASRC Peripheral Access Layer
2332 ---------------------------------------------------------------------------- */
2333
2334/*!
2335 * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
2336 * @{
2337 */
2338
2339/** ASRC - Register Layout Typedef */
2340typedef struct {
2341 __IO uint32_t ASRCTR; /**< ASRC Control Register, offset: 0x0 */
2342 __IO uint32_t ASRIER; /**< ASRC Interrupt Enable Register, offset: 0x4 */
2343 uint8_t RESERVED_0[4];
2344 __IO uint32_t ASRCNCR; /**< ASRC Channel Number Configuration Register, offset: 0xC */
2345 __IO uint32_t ASRCFG; /**< ASRC Filter Configuration Status Register, offset: 0x10 */
2346 __IO uint32_t ASRCSR; /**< ASRC Clock Source Register, offset: 0x14 */
2347 __IO uint32_t ASRCDR1; /**< ASRC Clock Divider Register 1, offset: 0x18 */
2348 __IO uint32_t ASRCDR2; /**< ASRC Clock Divider Register 2, offset: 0x1C */
2349 __I uint32_t ASRSTR; /**< ASRC Status Register, offset: 0x20 */
2350 uint8_t RESERVED_1[28];
2351 __IO uint32_t ASRPM[5]; /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */
2352 __IO uint32_t ASRTFR1; /**< ASRC ASRC Task Queue FIFO Register 1, offset: 0x54 */
2353 uint8_t RESERVED_2[4];
2354 __IO uint32_t ASRCCR; /**< ASRC Channel Counter Register, offset: 0x5C */
2355 __O uint32_t ASRDIA; /**< ASRC Data Input Register for Pair x, offset: 0x60 */
2356 __I uint32_t ASRDOA; /**< ASRC Data Output Register for Pair x, offset: 0x64 */
2357 __O uint32_t ASRDIB; /**< ASRC Data Input Register for Pair x, offset: 0x68 */
2358 __I uint32_t ASRDOB; /**< ASRC Data Output Register for Pair x, offset: 0x6C */
2359 __O uint32_t ASRDIC; /**< ASRC Data Input Register for Pair x, offset: 0x70 */
2360 __I uint32_t ASRDOC; /**< ASRC Data Output Register for Pair x, offset: 0x74 */
2361 uint8_t RESERVED_3[8];
2362 __IO uint32_t ASRIDRHA; /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */
2363 __IO uint32_t ASRIDRLA; /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */
2364 __IO uint32_t ASRIDRHB; /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */
2365 __IO uint32_t ASRIDRLB; /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */
2366 __IO uint32_t ASRIDRHC; /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */
2367 __IO uint32_t ASRIDRLC; /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */
2368 __IO uint32_t ASR76K; /**< ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98 */
2369 __IO uint32_t ASR56K; /**< ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C */
2370 __IO uint32_t ASRMCRA; /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */
2371 __I uint32_t ASRFSTA; /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */
2372 __IO uint32_t ASRMCRB; /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */
2373 __I uint32_t ASRFSTB; /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */
2374 __IO uint32_t ASRMCRC; /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */
2375 __I uint32_t ASRFSTC; /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */
2376 uint8_t RESERVED_4[8];
2377 __IO uint32_t ASRMCR1[3]; /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */
2378} ASRC_Type;
2379
2380/* ----------------------------------------------------------------------------
2381 -- ASRC Register Masks
2382 ---------------------------------------------------------------------------- */
2383
2384/*!
2385 * @addtogroup ASRC_Register_Masks ASRC Register Masks
2386 * @{
2387 */
2388
2389/*! @name ASRCTR - ASRC Control Register */
2390/*! @{ */
2391#define ASRC_ASRCTR_ASRCEN_MASK (0x1U)
2392#define ASRC_ASRCTR_ASRCEN_SHIFT (0U)
2393/*! ASRCEN - ASRCEN
2394 */
2395#define ASRC_ASRCTR_ASRCEN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK)
2396#define ASRC_ASRCTR_ASREA_MASK (0x2U)
2397#define ASRC_ASRCTR_ASREA_SHIFT (1U)
2398/*! ASREA - ASREA
2399 */
2400#define ASRC_ASRCTR_ASREA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK)
2401#define ASRC_ASRCTR_ASREB_MASK (0x4U)
2402#define ASRC_ASRCTR_ASREB_SHIFT (2U)
2403/*! ASREB - ASREB
2404 */
2405#define ASRC_ASRCTR_ASREB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK)
2406#define ASRC_ASRCTR_ASREC_MASK (0x8U)
2407#define ASRC_ASRCTR_ASREC_SHIFT (3U)
2408/*! ASREC - ASREC
2409 */
2410#define ASRC_ASRCTR_ASREC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK)
2411#define ASRC_ASRCTR_SRST_MASK (0x10U)
2412#define ASRC_ASRCTR_SRST_SHIFT (4U)
2413/*! SRST - SRST
2414 */
2415#define ASRC_ASRCTR_SRST(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK)
2416#define ASRC_ASRCTR_IDRA_MASK (0x2000U)
2417#define ASRC_ASRCTR_IDRA_SHIFT (13U)
2418/*! IDRA - IDRA
2419 */
2420#define ASRC_ASRCTR_IDRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK)
2421#define ASRC_ASRCTR_USRA_MASK (0x4000U)
2422#define ASRC_ASRCTR_USRA_SHIFT (14U)
2423/*! USRA - USRA
2424 */
2425#define ASRC_ASRCTR_USRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK)
2426#define ASRC_ASRCTR_IDRB_MASK (0x8000U)
2427#define ASRC_ASRCTR_IDRB_SHIFT (15U)
2428/*! IDRB - IDRB
2429 */
2430#define ASRC_ASRCTR_IDRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK)
2431#define ASRC_ASRCTR_USRB_MASK (0x10000U)
2432#define ASRC_ASRCTR_USRB_SHIFT (16U)
2433/*! USRB - USRB
2434 */
2435#define ASRC_ASRCTR_USRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK)
2436#define ASRC_ASRCTR_IDRC_MASK (0x20000U)
2437#define ASRC_ASRCTR_IDRC_SHIFT (17U)
2438/*! IDRC - IDRC
2439 */
2440#define ASRC_ASRCTR_IDRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK)
2441#define ASRC_ASRCTR_USRC_MASK (0x40000U)
2442#define ASRC_ASRCTR_USRC_SHIFT (18U)
2443/*! USRC - USRC
2444 */
2445#define ASRC_ASRCTR_USRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK)
2446#define ASRC_ASRCTR_ATSA_MASK (0x100000U)
2447#define ASRC_ASRCTR_ATSA_SHIFT (20U)
2448/*! ATSA - ATSA
2449 */
2450#define ASRC_ASRCTR_ATSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK)
2451#define ASRC_ASRCTR_ATSB_MASK (0x200000U)
2452#define ASRC_ASRCTR_ATSB_SHIFT (21U)
2453/*! ATSB - ATSB
2454 */
2455#define ASRC_ASRCTR_ATSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK)
2456#define ASRC_ASRCTR_ATSC_MASK (0x400000U)
2457#define ASRC_ASRCTR_ATSC_SHIFT (22U)
2458/*! ATSC - ATSC
2459 */
2460#define ASRC_ASRCTR_ATSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK)
2461/*! @} */
2462
2463/*! @name ASRIER - ASRC Interrupt Enable Register */
2464/*! @{ */
2465#define ASRC_ASRIER_ADIEA_MASK (0x1U)
2466#define ASRC_ASRIER_ADIEA_SHIFT (0U)
2467/*! ADIEA - ADIEA
2468 * 0b1..interrupt enabled
2469 * 0b0..interrupt disabled
2470 */
2471#define ASRC_ASRIER_ADIEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK)
2472#define ASRC_ASRIER_ADIEB_MASK (0x2U)
2473#define ASRC_ASRIER_ADIEB_SHIFT (1U)
2474/*! ADIEB - ADIEB
2475 * 0b1..interrupt enabled
2476 * 0b0..interrupt disabled
2477 */
2478#define ASRC_ASRIER_ADIEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK)
2479#define ASRC_ASRIER_ADIEC_MASK (0x4U)
2480#define ASRC_ASRIER_ADIEC_SHIFT (2U)
2481/*! ADIEC - ADIEC
2482 * 0b1..interrupt enabled
2483 * 0b0..interrupt disabled
2484 */
2485#define ASRC_ASRIER_ADIEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK)
2486#define ASRC_ASRIER_ADOEA_MASK (0x8U)
2487#define ASRC_ASRIER_ADOEA_SHIFT (3U)
2488/*! ADOEA - ADOEA
2489 * 0b1..interrupt enabled
2490 * 0b0..interrupt disabled
2491 */
2492#define ASRC_ASRIER_ADOEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK)
2493#define ASRC_ASRIER_ADOEB_MASK (0x10U)
2494#define ASRC_ASRIER_ADOEB_SHIFT (4U)
2495/*! ADOEB - ADOEB
2496 * 0b1..interrupt enabled
2497 * 0b0..interrupt disabled
2498 */
2499#define ASRC_ASRIER_ADOEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK)
2500#define ASRC_ASRIER_ADOEC_MASK (0x20U)
2501#define ASRC_ASRIER_ADOEC_SHIFT (5U)
2502/*! ADOEC - ADOEC
2503 * 0b1..interrupt enabled
2504 * 0b0..interrupt disabled
2505 */
2506#define ASRC_ASRIER_ADOEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK)
2507#define ASRC_ASRIER_AOLIE_MASK (0x40U)
2508#define ASRC_ASRIER_AOLIE_SHIFT (6U)
2509/*! AOLIE - AOLIE
2510 * 0b1..interrupt enabled
2511 * 0b0..interrupt disabled
2512 */
2513#define ASRC_ASRIER_AOLIE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK)
2514#define ASRC_ASRIER_AFPWE_MASK (0x80U)
2515#define ASRC_ASRIER_AFPWE_SHIFT (7U)
2516/*! AFPWE - AFPWE
2517 * 0b1..interrupt enabled
2518 * 0b0..interrupt disabled
2519 */
2520#define ASRC_ASRIER_AFPWE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK)
2521/*! @} */
2522
2523/*! @name ASRCNCR - ASRC Channel Number Configuration Register */
2524/*! @{ */
2525#define ASRC_ASRCNCR_ANCA_MASK (0xFU)
2526#define ASRC_ASRCNCR_ANCA_SHIFT (0U)
2527/*! ANCA - ANCA
2528 * 0b0000..0 channels in A (Pair A is disabled)
2529 * 0b0001..1 channel in A
2530 * 0b0010..2 channels in A
2531 * 0b0011..3 channels in A
2532 * 0b0100..4 channels in A
2533 * 0b0101..5 channels in A
2534 * 0b0110..6 channels in A
2535 * 0b0111..7 channels in A
2536 * 0b1000..8 channels in A
2537 * 0b1001..9 channels in A
2538 * 0b1010..10 channels in A
2539 * 0b1011-0b1111..Should not be used.
2540 */
2541#define ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK)
2542#define ASRC_ASRCNCR_ANCB_MASK (0xF0U)
2543#define ASRC_ASRCNCR_ANCB_SHIFT (4U)
2544/*! ANCB - ANCB
2545 * 0b0000..0 channels in B (Pair B is disabled)
2546 * 0b0001..1 channel in B
2547 * 0b0010..2 channels in B
2548 * 0b0011..3 channels in B
2549 * 0b0100..4 channels in B
2550 * 0b0101..5 channels in B
2551 * 0b0110..6 channels in B
2552 * 0b0111..7 channels in B
2553 * 0b1000..8 channels in B
2554 * 0b1001..9 channels in B
2555 * 0b1010..10 channels in B
2556 * 0b1011-0b1111..Should not be used.
2557 */
2558#define ASRC_ASRCNCR_ANCB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK)
2559#define ASRC_ASRCNCR_ANCC_MASK (0xF00U)
2560#define ASRC_ASRCNCR_ANCC_SHIFT (8U)
2561/*! ANCC - ANCC
2562 * 0b0000..0 channels in C (Pair C is disabled)
2563 * 0b0001..1 channel in C
2564 * 0b0010..2 channels in C
2565 * 0b0011..3 channels in C
2566 * 0b0100..4 channels in C
2567 * 0b0101..5 channels in C
2568 * 0b0110..6 channels in C
2569 * 0b0111..7 channels in C
2570 * 0b1000..8 channels in C
2571 * 0b1001..9 channels in C
2572 * 0b1010..10 channels in C
2573 * 0b1011-0b1111..Should not be used.
2574 */
2575#define ASRC_ASRCNCR_ANCC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK)
2576/*! @} */
2577
2578/*! @name ASRCFG - ASRC Filter Configuration Status Register */
2579/*! @{ */
2580#define ASRC_ASRCFG_PREMODA_MASK (0xC0U)
2581#define ASRC_ASRCFG_PREMODA_SHIFT (6U)
2582/*! PREMODA - PREMODA
2583 * 0b00..Select Upsampling-by-2 as defined in
2584 * 0b01..Select Direct-Connection as defined in
2585 * 0b10..Select Downsampling-by-2 as defined in
2586 * 0b11..Select passthrough mode. In this case, POSTMODA[1-0] have no use.
2587 */
2588#define ASRC_ASRCFG_PREMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK)
2589#define ASRC_ASRCFG_POSTMODA_MASK (0x300U)
2590#define ASRC_ASRCFG_POSTMODA_SHIFT (8U)
2591/*! POSTMODA - POSTMODA
2592 * 0b00..Select Upsampling-by-2 as defined in
2593 * 0b01..Select Direct-Connection as defined in
2594 * 0b10..Select Downsampling-by-2 as defined in
2595 */
2596#define ASRC_ASRCFG_POSTMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK)
2597#define ASRC_ASRCFG_PREMODB_MASK (0xC00U)
2598#define ASRC_ASRCFG_PREMODB_SHIFT (10U)
2599/*! PREMODB - PREMODB
2600 * 0b00..Select Upsampling-by-2 as defined in
2601 * 0b01..Select Direct-Connection as defined in
2602 * 0b10..Select Downsampling-by-2 as defined in
2603 * 0b11..Select passthrough mode. In this case, POSTMODB[1-0] have no use.
2604 */
2605#define ASRC_ASRCFG_PREMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK)
2606#define ASRC_ASRCFG_POSTMODB_MASK (0x3000U)
2607#define ASRC_ASRCFG_POSTMODB_SHIFT (12U)
2608/*! POSTMODB - POSTMODB
2609 * 0b00..Select Upsampling-by-2 as defined in
2610 * 0b01..Select Direct-Connection as defined in
2611 * 0b10..Select Downsampling-by-2 as defined in
2612 */
2613#define ASRC_ASRCFG_POSTMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK)
2614#define ASRC_ASRCFG_PREMODC_MASK (0xC000U)
2615#define ASRC_ASRCFG_PREMODC_SHIFT (14U)
2616/*! PREMODC - PREMODC
2617 * 0b00..Select Upsampling-by-2 as defined in
2618 * 0b01..Select Direct-Connection as defined in
2619 * 0b10..Select Downsampling-by-2 as defined in
2620 * 0b11..Select passthrough mode. In this case, POSTMODC[1-0] have no use.
2621 */
2622#define ASRC_ASRCFG_PREMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK)
2623#define ASRC_ASRCFG_POSTMODC_MASK (0x30000U)
2624#define ASRC_ASRCFG_POSTMODC_SHIFT (16U)
2625/*! POSTMODC - POSTMODC
2626 * 0b00..Select Upsampling-by-2 as defined in Signal Processing Flow.
2627 * 0b01..Select Direct-Connection as defined in Signal Processing Flow.
2628 * 0b10..Select Downsampling-by-2 as defined in Signal Processing Flow.
2629 */
2630#define ASRC_ASRCFG_POSTMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK)
2631#define ASRC_ASRCFG_NDPRA_MASK (0x40000U)
2632#define ASRC_ASRCFG_NDPRA_SHIFT (18U)
2633/*! NDPRA - NDPRA
2634 * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
2635 * 0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
2636 */
2637#define ASRC_ASRCFG_NDPRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK)
2638#define ASRC_ASRCFG_NDPRB_MASK (0x80000U)
2639#define ASRC_ASRCFG_NDPRB_SHIFT (19U)
2640/*! NDPRB - NDPRB
2641 * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
2642 * 0b1..Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM.
2643 */
2644#define ASRC_ASRCFG_NDPRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK)
2645#define ASRC_ASRCFG_NDPRC_MASK (0x100000U)
2646#define ASRC_ASRCFG_NDPRC_SHIFT (20U)
2647/*! NDPRC - NDPRC
2648 * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
2649 * 0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
2650 */
2651#define ASRC_ASRCFG_NDPRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK)
2652#define ASRC_ASRCFG_INIRQA_MASK (0x200000U)
2653#define ASRC_ASRCFG_INIRQA_SHIFT (21U)
2654/*! INIRQA - INIRQA
2655 */
2656#define ASRC_ASRCFG_INIRQA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK)
2657#define ASRC_ASRCFG_INIRQB_MASK (0x400000U)
2658#define ASRC_ASRCFG_INIRQB_SHIFT (22U)
2659/*! INIRQB - INIRQB
2660 */
2661#define ASRC_ASRCFG_INIRQB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK)
2662#define ASRC_ASRCFG_INIRQC_MASK (0x800000U)
2663#define ASRC_ASRCFG_INIRQC_SHIFT (23U)
2664/*! INIRQC - INIRQC
2665 */
2666#define ASRC_ASRCFG_INIRQC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK)
2667/*! @} */
2668
2669/*! @name ASRCSR - ASRC Clock Source Register */
2670/*! @{ */
2671#define ASRC_ASRCSR_AICSA_MASK (0xFU)
2672#define ASRC_ASRCSR_AICSA_SHIFT (0U)
2673/*! AICSA - AICSA
2674 * 0b0000..bit clock 0
2675 * 0b0001..bit clock 1
2676 * 0b0010..bit clock 2
2677 * 0b0011..bit clock 3
2678 * 0b0100..bit clock 4
2679 * 0b0101..bit clock 5
2680 * 0b0110..bit clock 6
2681 * 0b0111..bit clock 7
2682 * 0b1000..bit clock 8
2683 * 0b1001..bit clock 9
2684 * 0b1010..bit clock A
2685 * 0b1011..bit clock B
2686 * 0b1100..bit clock C
2687 * 0b1101..bit clock D
2688 * 0b1110..bit clock E
2689 * 0b1111..clock disabled, connected to zero
2690 */
2691#define ASRC_ASRCSR_AICSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK)
2692#define ASRC_ASRCSR_AICSB_MASK (0xF0U)
2693#define ASRC_ASRCSR_AICSB_SHIFT (4U)
2694/*! AICSB - AICSB
2695 * 0b0000..bit clock 0
2696 * 0b0001..bit clock 1
2697 * 0b0010..bit clock 2
2698 * 0b0011..bit clock 3
2699 * 0b0100..bit clock 4
2700 * 0b0101..bit clock 5
2701 * 0b0110..bit clock 6
2702 * 0b0111..bit clock 7
2703 * 0b1000..bit clock 8
2704 * 0b1001..bit clock 9
2705 * 0b1010..bit clock A
2706 * 0b1011..bit clock B
2707 * 0b1100..bit clock C
2708 * 0b1101..bit clock D
2709 * 0b1110..bit clock E
2710 * 0b1111..clock disabled, connected to zero
2711 */
2712#define ASRC_ASRCSR_AICSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK)
2713#define ASRC_ASRCSR_AICSC_MASK (0xF00U)
2714#define ASRC_ASRCSR_AICSC_SHIFT (8U)
2715/*! AICSC - AICSC
2716 * 0b0000..bit clock 0
2717 * 0b0001..bit clock 1
2718 * 0b0010..bit clock 2
2719 * 0b0011..bit clock 3
2720 * 0b0100..bit clock 4
2721 * 0b0101..bit clock 5
2722 * 0b0110..bit clock 6
2723 * 0b0111..bit clock 7
2724 * 0b1000..bit clock 8
2725 * 0b1001..bit clock 9
2726 * 0b1010..bit clock A
2727 * 0b1011..bit clock B
2728 * 0b1100..bit clock C
2729 * 0b1101..bit clock D
2730 * 0b1110..bit clock E
2731 * 0b1111..clock disabled, connected to zero
2732 */
2733#define ASRC_ASRCSR_AICSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK)
2734#define ASRC_ASRCSR_AOCSA_MASK (0xF000U)
2735#define ASRC_ASRCSR_AOCSA_SHIFT (12U)
2736/*! AOCSA - AOCSA
2737 * 0b0000..bit clock 0
2738 * 0b0001..bit clock 1
2739 * 0b0010..bit clock 2
2740 * 0b0011..bit clock 3
2741 * 0b0100..bit clock 4
2742 * 0b0101..bit clock 5
2743 * 0b0110..bit clock 6
2744 * 0b0111..bit clock 7
2745 * 0b1000..bit clock 8
2746 * 0b1001..bit clock 9
2747 * 0b1010..bit clock A
2748 * 0b1011..bit clock B
2749 * 0b1100..bit clock C
2750 * 0b1101..bit clock D
2751 * 0b1110..bit clock E
2752 * 0b1111..clock disabled, connected to zero
2753 */
2754#define ASRC_ASRCSR_AOCSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK)
2755#define ASRC_ASRCSR_AOCSB_MASK (0xF0000U)
2756#define ASRC_ASRCSR_AOCSB_SHIFT (16U)
2757/*! AOCSB - AOCSB
2758 * 0b0000..bit clock 0
2759 * 0b0001..bit clock 1
2760 * 0b0010..bit clock 2
2761 * 0b0011..bit clock 3
2762 * 0b0100..bit clock 4
2763 * 0b0101..bit clock 5
2764 * 0b0110..bit clock 6
2765 * 0b0111..bit clock 7
2766 * 0b1000..bit clock 8
2767 * 0b1001..bit clock 9
2768 * 0b1010..bit clock A
2769 * 0b1011..bit clock B
2770 * 0b1100..bit clock C
2771 * 0b1101..bit clock D
2772 * 0b1110..bit clock E
2773 * 0b1111..clock disabled, connected to zero
2774 */
2775#define ASRC_ASRCSR_AOCSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK)
2776#define ASRC_ASRCSR_AOCSC_MASK (0xF00000U)
2777#define ASRC_ASRCSR_AOCSC_SHIFT (20U)
2778/*! AOCSC - AOCSC
2779 * 0b0000..bit clock 0
2780 * 0b0001..bit clock 1
2781 * 0b0010..bit clock 2
2782 * 0b0011..bit clock 3
2783 * 0b0100..bit clock 4
2784 * 0b0101..bit clock 5
2785 * 0b0110..bit clock 6
2786 * 0b0111..bit clock 7
2787 * 0b1000..bit clock 8
2788 * 0b1001..bit clock 9
2789 * 0b1010..bit clock A
2790 * 0b1011..bit clock B
2791 * 0b1100..bit clock C
2792 * 0b1101..bit clock D
2793 * 0b1110..bit clock E
2794 * 0b1111..clock disabled, connected to zero
2795 */
2796#define ASRC_ASRCSR_AOCSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK)
2797/*! @} */
2798
2799/*! @name ASRCDR1 - ASRC Clock Divider Register 1 */
2800/*! @{ */
2801#define ASRC_ASRCDR1_AICPA_MASK (0x7U)
2802#define ASRC_ASRCDR1_AICPA_SHIFT (0U)
2803/*! AICPA - AICPA
2804 */
2805#define ASRC_ASRCDR1_AICPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK)
2806#define ASRC_ASRCDR1_AICDA_MASK (0x38U)
2807#define ASRC_ASRCDR1_AICDA_SHIFT (3U)
2808/*! AICDA - AICDA
2809 */
2810#define ASRC_ASRCDR1_AICDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK)
2811#define ASRC_ASRCDR1_AICPB_MASK (0x1C0U)
2812#define ASRC_ASRCDR1_AICPB_SHIFT (6U)
2813/*! AICPB - AICPB
2814 */
2815#define ASRC_ASRCDR1_AICPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK)
2816#define ASRC_ASRCDR1_AICDB_MASK (0xE00U)
2817#define ASRC_ASRCDR1_AICDB_SHIFT (9U)
2818/*! AICDB - AICDB
2819 */
2820#define ASRC_ASRCDR1_AICDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK)
2821#define ASRC_ASRCDR1_AOCPA_MASK (0x7000U)
2822#define ASRC_ASRCDR1_AOCPA_SHIFT (12U)
2823/*! AOCPA - AOCPA
2824 */
2825#define ASRC_ASRCDR1_AOCPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK)
2826#define ASRC_ASRCDR1_AOCDA_MASK (0x38000U)
2827#define ASRC_ASRCDR1_AOCDA_SHIFT (15U)
2828/*! AOCDA - AOCDA
2829 */
2830#define ASRC_ASRCDR1_AOCDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK)
2831#define ASRC_ASRCDR1_AOCPB_MASK (0x1C0000U)
2832#define ASRC_ASRCDR1_AOCPB_SHIFT (18U)
2833/*! AOCPB - AOCPB
2834 */
2835#define ASRC_ASRCDR1_AOCPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK)
2836#define ASRC_ASRCDR1_AOCDB_MASK (0xE00000U)
2837#define ASRC_ASRCDR1_AOCDB_SHIFT (21U)
2838/*! AOCDB - AOCDB
2839 */
2840#define ASRC_ASRCDR1_AOCDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK)
2841/*! @} */
2842
2843/*! @name ASRCDR2 - ASRC Clock Divider Register 2 */
2844/*! @{ */
2845#define ASRC_ASRCDR2_AICPC_MASK (0x7U)
2846#define ASRC_ASRCDR2_AICPC_SHIFT (0U)
2847/*! AICPC - AICPC
2848 */
2849#define ASRC_ASRCDR2_AICPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK)
2850#define ASRC_ASRCDR2_AICDC_MASK (0x38U)
2851#define ASRC_ASRCDR2_AICDC_SHIFT (3U)
2852/*! AICDC - AICDC
2853 */
2854#define ASRC_ASRCDR2_AICDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK)
2855#define ASRC_ASRCDR2_AOCPC_MASK (0x1C0U)
2856#define ASRC_ASRCDR2_AOCPC_SHIFT (6U)
2857/*! AOCPC - AOCPC
2858 */
2859#define ASRC_ASRCDR2_AOCPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK)
2860#define ASRC_ASRCDR2_AOCDC_MASK (0xE00U)
2861#define ASRC_ASRCDR2_AOCDC_SHIFT (9U)
2862/*! AOCDC - AOCDC
2863 */
2864#define ASRC_ASRCDR2_AOCDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK)
2865/*! @} */
2866
2867/*! @name ASRSTR - ASRC Status Register */
2868/*! @{ */
2869#define ASRC_ASRSTR_AIDEA_MASK (0x1U)
2870#define ASRC_ASRSTR_AIDEA_SHIFT (0U)
2871/*! AIDEA - AIDEA
2872 */
2873#define ASRC_ASRSTR_AIDEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK)
2874#define ASRC_ASRSTR_AIDEB_MASK (0x2U)
2875#define ASRC_ASRSTR_AIDEB_SHIFT (1U)
2876/*! AIDEB - AIDEB
2877 */
2878#define ASRC_ASRSTR_AIDEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK)
2879#define ASRC_ASRSTR_AIDEC_MASK (0x4U)
2880#define ASRC_ASRSTR_AIDEC_SHIFT (2U)
2881/*! AIDEC - AIDEC
2882 */
2883#define ASRC_ASRSTR_AIDEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK)
2884#define ASRC_ASRSTR_AODFA_MASK (0x8U)
2885#define ASRC_ASRSTR_AODFA_SHIFT (3U)
2886/*! AODFA - AODFA
2887 */
2888#define ASRC_ASRSTR_AODFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK)
2889#define ASRC_ASRSTR_AODFB_MASK (0x10U)
2890#define ASRC_ASRSTR_AODFB_SHIFT (4U)
2891/*! AODFB - AODFB
2892 */
2893#define ASRC_ASRSTR_AODFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK)
2894#define ASRC_ASRSTR_AODFC_MASK (0x20U)
2895#define ASRC_ASRSTR_AODFC_SHIFT (5U)
2896/*! AODFC - AODFC
2897 */
2898#define ASRC_ASRSTR_AODFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK)
2899#define ASRC_ASRSTR_AOLE_MASK (0x40U)
2900#define ASRC_ASRSTR_AOLE_SHIFT (6U)
2901/*! AOLE - AOLE
2902 */
2903#define ASRC_ASRSTR_AOLE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK)
2904#define ASRC_ASRSTR_FPWT_MASK (0x80U)
2905#define ASRC_ASRSTR_FPWT_SHIFT (7U)
2906/*! FPWT - FPWT
2907 */
2908#define ASRC_ASRSTR_FPWT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK)
2909#define ASRC_ASRSTR_AIDUA_MASK (0x100U)
2910#define ASRC_ASRSTR_AIDUA_SHIFT (8U)
2911/*! AIDUA - AIDUA
2912 */
2913#define ASRC_ASRSTR_AIDUA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK)
2914#define ASRC_ASRSTR_AIDUB_MASK (0x200U)
2915#define ASRC_ASRSTR_AIDUB_SHIFT (9U)
2916/*! AIDUB - AIDUB
2917 */
2918#define ASRC_ASRSTR_AIDUB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK)
2919#define ASRC_ASRSTR_AIDUC_MASK (0x400U)
2920#define ASRC_ASRSTR_AIDUC_SHIFT (10U)
2921/*! AIDUC - AIDUC
2922 */
2923#define ASRC_ASRSTR_AIDUC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK)
2924#define ASRC_ASRSTR_AODOA_MASK (0x800U)
2925#define ASRC_ASRSTR_AODOA_SHIFT (11U)
2926/*! AODOA - AODOA
2927 */
2928#define ASRC_ASRSTR_AODOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK)
2929#define ASRC_ASRSTR_AODOB_MASK (0x1000U)
2930#define ASRC_ASRSTR_AODOB_SHIFT (12U)
2931/*! AODOB - AODOB
2932 */
2933#define ASRC_ASRSTR_AODOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK)
2934#define ASRC_ASRSTR_AODOC_MASK (0x2000U)
2935#define ASRC_ASRSTR_AODOC_SHIFT (13U)
2936/*! AODOC - AODOC
2937 */
2938#define ASRC_ASRSTR_AODOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK)
2939#define ASRC_ASRSTR_AIOLA_MASK (0x4000U)
2940#define ASRC_ASRSTR_AIOLA_SHIFT (14U)
2941/*! AIOLA - AIOLA
2942 */
2943#define ASRC_ASRSTR_AIOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK)
2944#define ASRC_ASRSTR_AIOLB_MASK (0x8000U)
2945#define ASRC_ASRSTR_AIOLB_SHIFT (15U)
2946/*! AIOLB - AIOLB
2947 */
2948#define ASRC_ASRSTR_AIOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK)
2949#define ASRC_ASRSTR_AIOLC_MASK (0x10000U)
2950#define ASRC_ASRSTR_AIOLC_SHIFT (16U)
2951/*! AIOLC - AIOLC
2952 */
2953#define ASRC_ASRSTR_AIOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK)
2954#define ASRC_ASRSTR_AOOLA_MASK (0x20000U)
2955#define ASRC_ASRSTR_AOOLA_SHIFT (17U)
2956/*! AOOLA - AOOLA
2957 */
2958#define ASRC_ASRSTR_AOOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK)
2959#define ASRC_ASRSTR_AOOLB_MASK (0x40000U)
2960#define ASRC_ASRSTR_AOOLB_SHIFT (18U)
2961/*! AOOLB - AOOLB
2962 */
2963#define ASRC_ASRSTR_AOOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK)
2964#define ASRC_ASRSTR_AOOLC_MASK (0x80000U)
2965#define ASRC_ASRSTR_AOOLC_SHIFT (19U)
2966/*! AOOLC - AOOLC
2967 */
2968#define ASRC_ASRSTR_AOOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK)
2969#define ASRC_ASRSTR_ATQOL_MASK (0x100000U)
2970#define ASRC_ASRSTR_ATQOL_SHIFT (20U)
2971/*! ATQOL - ATQOL
2972 */
2973#define ASRC_ASRSTR_ATQOL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK)
2974#define ASRC_ASRSTR_DSLCNT_MASK (0x200000U)
2975#define ASRC_ASRSTR_DSLCNT_SHIFT (21U)
2976/*! DSLCNT - DSLCNT
2977 */
2978#define ASRC_ASRSTR_DSLCNT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK)
2979/*! @} */
2980
2981/*! @name ASRPM - ASRC Parameter Register n */
2982/*! @{ */
2983#define ASRC_ASRPM_PARAMETER_VALUE_MASK (0xFFFFFFU)
2984#define ASRC_ASRPM_PARAMETER_VALUE_SHIFT (0U)
2985/*! PARAMETER_VALUE - PARAMETER_VALUE
2986 */
2987#define ASRC_ASRPM_PARAMETER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPM_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPM_PARAMETER_VALUE_MASK)
2988/*! @} */
2989
2990/* The count of ASRC_ASRPM */
2991#define ASRC_ASRPM_COUNT (5U)
2992
2993/*! @name ASRTFR1 - ASRC ASRC Task Queue FIFO Register 1 */
2994/*! @{ */
2995#define ASRC_ASRTFR1_TF_BASE_MASK (0x1FC0U)
2996#define ASRC_ASRTFR1_TF_BASE_SHIFT (6U)
2997/*! TF_BASE - TF_BASE
2998 */
2999#define ASRC_ASRTFR1_TF_BASE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK)
3000#define ASRC_ASRTFR1_TF_FILL_MASK (0xFE000U)
3001#define ASRC_ASRTFR1_TF_FILL_SHIFT (13U)
3002/*! TF_FILL - TF_FILL
3003 */
3004#define ASRC_ASRTFR1_TF_FILL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK)
3005/*! @} */
3006
3007/*! @name ASRCCR - ASRC Channel Counter Register */
3008/*! @{ */
3009#define ASRC_ASRCCR_ACIA_MASK (0xFU)
3010#define ASRC_ASRCCR_ACIA_SHIFT (0U)
3011/*! ACIA - ACIA
3012 */
3013#define ASRC_ASRCCR_ACIA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK)
3014#define ASRC_ASRCCR_ACIB_MASK (0xF0U)
3015#define ASRC_ASRCCR_ACIB_SHIFT (4U)
3016/*! ACIB - ACIB
3017 */
3018#define ASRC_ASRCCR_ACIB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK)
3019#define ASRC_ASRCCR_ACIC_MASK (0xF00U)
3020#define ASRC_ASRCCR_ACIC_SHIFT (8U)
3021/*! ACIC - ACIC
3022 */
3023#define ASRC_ASRCCR_ACIC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK)
3024#define ASRC_ASRCCR_ACOA_MASK (0xF000U)
3025#define ASRC_ASRCCR_ACOA_SHIFT (12U)
3026/*! ACOA - ACOA
3027 */
3028#define ASRC_ASRCCR_ACOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK)
3029#define ASRC_ASRCCR_ACOB_MASK (0xF0000U)
3030#define ASRC_ASRCCR_ACOB_SHIFT (16U)
3031/*! ACOB - ACOB
3032 */
3033#define ASRC_ASRCCR_ACOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK)
3034#define ASRC_ASRCCR_ACOC_MASK (0xF00000U)
3035#define ASRC_ASRCCR_ACOC_SHIFT (20U)
3036/*! ACOC - ACOC
3037 */
3038#define ASRC_ASRCCR_ACOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK)
3039/*! @} */
3040
3041/*! @name ASRDIA - ASRC Data Input Register for Pair x */
3042/*! @{ */
3043#define ASRC_ASRDIA_DATA_MASK (0xFFFFFFU)
3044#define ASRC_ASRDIA_DATA_SHIFT (0U)
3045/*! DATA - DATA
3046 */
3047#define ASRC_ASRDIA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK)
3048/*! @} */
3049
3050/*! @name ASRDOA - ASRC Data Output Register for Pair x */
3051/*! @{ */
3052#define ASRC_ASRDOA_DATA_MASK (0xFFFFFFU)
3053#define ASRC_ASRDOA_DATA_SHIFT (0U)
3054/*! DATA - DATA
3055 */
3056#define ASRC_ASRDOA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK)
3057/*! @} */
3058
3059/*! @name ASRDIB - ASRC Data Input Register for Pair x */
3060/*! @{ */
3061#define ASRC_ASRDIB_DATA_MASK (0xFFFFFFU)
3062#define ASRC_ASRDIB_DATA_SHIFT (0U)
3063/*! DATA - DATA
3064 */
3065#define ASRC_ASRDIB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK)
3066/*! @} */
3067
3068/*! @name ASRDOB - ASRC Data Output Register for Pair x */
3069/*! @{ */
3070#define ASRC_ASRDOB_DATA_MASK (0xFFFFFFU)
3071#define ASRC_ASRDOB_DATA_SHIFT (0U)
3072/*! DATA - DATA
3073 */
3074#define ASRC_ASRDOB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK)
3075/*! @} */
3076
3077/*! @name ASRDIC - ASRC Data Input Register for Pair x */
3078/*! @{ */
3079#define ASRC_ASRDIC_DATA_MASK (0xFFFFFFU)
3080#define ASRC_ASRDIC_DATA_SHIFT (0U)
3081/*! DATA - DATA
3082 */
3083#define ASRC_ASRDIC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK)
3084/*! @} */
3085
3086/*! @name ASRDOC - ASRC Data Output Register for Pair x */
3087/*! @{ */
3088#define ASRC_ASRDOC_DATA_MASK (0xFFFFFFU)
3089#define ASRC_ASRDOC_DATA_SHIFT (0U)
3090/*! DATA - DATA
3091 */
3092#define ASRC_ASRDOC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK)
3093/*! @} */
3094
3095/*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */
3096/*! @{ */
3097#define ASRC_ASRIDRHA_IDRATIOA_H_MASK (0xFFU)
3098#define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT (0U)
3099/*! IDRATIOA_H - IDRATIOA_H
3100 */
3101#define ASRC_ASRIDRHA_IDRATIOA_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK)
3102/*! @} */
3103
3104/*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */
3105/*! @{ */
3106#define ASRC_ASRIDRLA_IDRATIOA_L_MASK (0xFFFFFFU)
3107#define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT (0U)
3108/*! IDRATIOA_L - IDRATIOA_L
3109 */
3110#define ASRC_ASRIDRLA_IDRATIOA_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK)
3111/*! @} */
3112
3113/*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */
3114/*! @{ */
3115#define ASRC_ASRIDRHB_IDRATIOB_H_MASK (0xFFU)
3116#define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT (0U)
3117/*! IDRATIOB_H - IDRATIOB_H
3118 */
3119#define ASRC_ASRIDRHB_IDRATIOB_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK)
3120/*! @} */
3121
3122/*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */
3123/*! @{ */
3124#define ASRC_ASRIDRLB_IDRATIOB_L_MASK (0xFFFFFFU)
3125#define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT (0U)
3126/*! IDRATIOB_L - IDRATIOB_L
3127 */
3128#define ASRC_ASRIDRLB_IDRATIOB_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK)
3129/*! @} */
3130
3131/*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */
3132/*! @{ */
3133#define ASRC_ASRIDRHC_IDRATIOC_H_MASK (0xFFU)
3134#define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT (0U)
3135/*! IDRATIOC_H - IDRATIOC_H
3136 */
3137#define ASRC_ASRIDRHC_IDRATIOC_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK)
3138/*! @} */
3139
3140/*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */
3141/*! @{ */
3142#define ASRC_ASRIDRLC_IDRATIOC_L_MASK (0xFFFFFFU)
3143#define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT (0U)
3144/*! IDRATIOC_L - IDRATIOC_L
3145 */
3146#define ASRC_ASRIDRLC_IDRATIOC_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK)
3147/*! @} */
3148
3149/*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */
3150/*! @{ */
3151#define ASRC_ASR76K_ASR76K_MASK (0x1FFFFU)
3152#define ASRC_ASR76K_ASR76K_SHIFT (0U)
3153/*! ASR76K - ASR76K
3154 */
3155#define ASRC_ASR76K_ASR76K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK)
3156/*! @} */
3157
3158/*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */
3159/*! @{ */
3160#define ASRC_ASR56K_ASR56K_MASK (0x1FFFFU)
3161#define ASRC_ASR56K_ASR56K_SHIFT (0U)
3162/*! ASR56K - ASR56K
3163 */
3164#define ASRC_ASR56K_ASR56K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK)
3165/*! @} */
3166
3167/*! @name ASRMCRA - ASRC Misc Control Register for Pair A */
3168/*! @{ */
3169#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK (0x3FU)
3170#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT (0U)
3171/*! INFIFO_THRESHOLDA - INFIFO_THRESHOLDA
3172 */
3173#define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK)
3174#define ASRC_ASRMCRA_RSYNOFA_MASK (0x400U)
3175#define ASRC_ASRMCRA_RSYNOFA_SHIFT (10U)
3176/*! RSYNOFA - RSYNOFA
3177 */
3178#define ASRC_ASRMCRA_RSYNOFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK)
3179#define ASRC_ASRMCRA_RSYNIFA_MASK (0x800U)
3180#define ASRC_ASRMCRA_RSYNIFA_SHIFT (11U)
3181/*! RSYNIFA - RSYNIFA
3182 */
3183#define ASRC_ASRMCRA_RSYNIFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK)
3184#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK (0x3F000U)
3185#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT (12U)
3186/*! OUTFIFO_THRESHOLDA - OUTFIFO_THRESHOLDA
3187 */
3188#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK)
3189#define ASRC_ASRMCRA_BYPASSPOLYA_MASK (0x100000U)
3190#define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT (20U)
3191/*! BYPASSPOLYA - BYPASSPOLYA
3192 * 0b1..Bypass polyphase filtering.
3193 * 0b0..Don't bypass polyphase filtering.
3194 */
3195#define ASRC_ASRMCRA_BYPASSPOLYA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK)
3196#define ASRC_ASRMCRA_BUFSTALLA_MASK (0x200000U)
3197#define ASRC_ASRMCRA_BUFSTALLA_SHIFT (21U)
3198/*! BUFSTALLA - BUFSTALLA
3199 * 0b1..Stall Pair A conversion in case of near empty/full FIFO conditions.
3200 * 0b0..Don't stall Pair A conversion even in case of near empty/full FIFO conditions.
3201 */
3202#define ASRC_ASRMCRA_BUFSTALLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK)
3203#define ASRC_ASRMCRA_EXTTHRSHA_MASK (0x400000U)
3204#define ASRC_ASRMCRA_EXTTHRSHA_SHIFT (22U)
3205/*! EXTTHRSHA - EXTTHRSHA
3206 * 0b1..Use external defined thresholds.
3207 * 0b0..Use default thresholds.
3208 */
3209#define ASRC_ASRMCRA_EXTTHRSHA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK)
3210#define ASRC_ASRMCRA_ZEROBUFA_MASK (0x800000U)
3211#define ASRC_ASRMCRA_ZEROBUFA_SHIFT (23U)
3212/*! ZEROBUFA - ZEROBUFA
3213 * 0b1..Don't zeroize the buffer
3214 * 0b0..Zeroize the buffer
3215 */
3216#define ASRC_ASRMCRA_ZEROBUFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK)
3217/*! @} */
3218
3219/*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */
3220/*! @{ */
3221#define ASRC_ASRFSTA_INFIFO_FILLA_MASK (0x7FU)
3222#define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT (0U)
3223/*! INFIFO_FILLA - INFIFO_FILLA
3224 */
3225#define ASRC_ASRFSTA_INFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK)
3226#define ASRC_ASRFSTA_IAEA_MASK (0x800U)
3227#define ASRC_ASRFSTA_IAEA_SHIFT (11U)
3228/*! IAEA - IAEA
3229 */
3230#define ASRC_ASRFSTA_IAEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK)
3231#define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK (0x7F000U)
3232#define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT (12U)
3233/*! OUTFIFO_FILLA - OUTFIFO_FILLA
3234 */
3235#define ASRC_ASRFSTA_OUTFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK)
3236#define ASRC_ASRFSTA_OAFA_MASK (0x800000U)
3237#define ASRC_ASRFSTA_OAFA_SHIFT (23U)
3238/*! OAFA - OAFA
3239 */
3240#define ASRC_ASRFSTA_OAFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK)
3241/*! @} */
3242
3243/*! @name ASRMCRB - ASRC Misc Control Register for Pair B */
3244/*! @{ */
3245#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK (0x3FU)
3246#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT (0U)
3247/*! INFIFO_THRESHOLDB - INFIFO_THRESHOLDB
3248 */
3249#define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK)
3250#define ASRC_ASRMCRB_RSYNOFB_MASK (0x400U)
3251#define ASRC_ASRMCRB_RSYNOFB_SHIFT (10U)
3252/*! RSYNOFB - RSYNOFB
3253 */
3254#define ASRC_ASRMCRB_RSYNOFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK)
3255#define ASRC_ASRMCRB_RSYNIFB_MASK (0x800U)
3256#define ASRC_ASRMCRB_RSYNIFB_SHIFT (11U)
3257/*! RSYNIFB - RSYNIFB
3258 */
3259#define ASRC_ASRMCRB_RSYNIFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK)
3260#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK (0x3F000U)
3261#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT (12U)
3262/*! OUTFIFO_THRESHOLDB - OUTFIFO_THRESHOLDB
3263 */
3264#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK)
3265#define ASRC_ASRMCRB_BYPASSPOLYB_MASK (0x100000U)
3266#define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT (20U)
3267/*! BYPASSPOLYB - BYPASSPOLYB
3268 * 0b1..Bypass polyphase filtering.
3269 * 0b0..Don't bypass polyphase filtering.
3270 */
3271#define ASRC_ASRMCRB_BYPASSPOLYB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK)
3272#define ASRC_ASRMCRB_BUFSTALLB_MASK (0x200000U)
3273#define ASRC_ASRMCRB_BUFSTALLB_SHIFT (21U)
3274/*! BUFSTALLB - BUFSTALLB
3275 * 0b1..Stall Pair B conversion in case of near empty/full FIFO conditions.
3276 * 0b0..Don't stall Pair B conversion even in case of near empty/full FIFO conditions.
3277 */
3278#define ASRC_ASRMCRB_BUFSTALLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK)
3279#define ASRC_ASRMCRB_EXTTHRSHB_MASK (0x400000U)
3280#define ASRC_ASRMCRB_EXTTHRSHB_SHIFT (22U)
3281/*! EXTTHRSHB - EXTTHRSHB
3282 * 0b1..Use external defined thresholds.
3283 * 0b0..Use default thresholds.
3284 */
3285#define ASRC_ASRMCRB_EXTTHRSHB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK)
3286#define ASRC_ASRMCRB_ZEROBUFB_MASK (0x800000U)
3287#define ASRC_ASRMCRB_ZEROBUFB_SHIFT (23U)
3288/*! ZEROBUFB - ZEROBUFB
3289 * 0b1..Don't zeroize the buffer
3290 * 0b0..Zeroize the buffer
3291 */
3292#define ASRC_ASRMCRB_ZEROBUFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK)
3293/*! @} */
3294
3295/*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */
3296/*! @{ */
3297#define ASRC_ASRFSTB_INFIFO_FILLB_MASK (0x7FU)
3298#define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT (0U)
3299/*! INFIFO_FILLB - INFIFO_FILLB
3300 */
3301#define ASRC_ASRFSTB_INFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK)
3302#define ASRC_ASRFSTB_IAEB_MASK (0x800U)
3303#define ASRC_ASRFSTB_IAEB_SHIFT (11U)
3304/*! IAEB - IAEB
3305 */
3306#define ASRC_ASRFSTB_IAEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK)
3307#define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK (0x7F000U)
3308#define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT (12U)
3309/*! OUTFIFO_FILLB - OUTFIFO_FILLB
3310 */
3311#define ASRC_ASRFSTB_OUTFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK)
3312#define ASRC_ASRFSTB_OAFB_MASK (0x800000U)
3313#define ASRC_ASRFSTB_OAFB_SHIFT (23U)
3314/*! OAFB - OAFB
3315 */
3316#define ASRC_ASRFSTB_OAFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK)
3317/*! @} */
3318
3319/*! @name ASRMCRC - ASRC Misc Control Register for Pair C */
3320/*! @{ */
3321#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK (0x3FU)
3322#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT (0U)
3323/*! INFIFO_THRESHOLDC - INFIFO_THRESHOLDC
3324 */
3325#define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK)
3326#define ASRC_ASRMCRC_RSYNOFC_MASK (0x400U)
3327#define ASRC_ASRMCRC_RSYNOFC_SHIFT (10U)
3328/*! RSYNOFC - RSYNOFC
3329 */
3330#define ASRC_ASRMCRC_RSYNOFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK)
3331#define ASRC_ASRMCRC_RSYNIFC_MASK (0x800U)
3332#define ASRC_ASRMCRC_RSYNIFC_SHIFT (11U)
3333/*! RSYNIFC - RSYNIFC
3334 */
3335#define ASRC_ASRMCRC_RSYNIFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK)
3336#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK (0x3F000U)
3337#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT (12U)
3338/*! OUTFIFO_THRESHOLDC - OUTFIFO_THRESHOLDC
3339 */
3340#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK)
3341#define ASRC_ASRMCRC_BYPASSPOLYC_MASK (0x100000U)
3342#define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT (20U)
3343/*! BYPASSPOLYC - BYPASSPOLYC
3344 * 0b1..Bypass polyphase filtering.
3345 * 0b0..Don't bypass polyphase filtering.
3346 */
3347#define ASRC_ASRMCRC_BYPASSPOLYC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK)
3348#define ASRC_ASRMCRC_BUFSTALLC_MASK (0x200000U)
3349#define ASRC_ASRMCRC_BUFSTALLC_SHIFT (21U)
3350/*! BUFSTALLC - BUFSTALLC
3351 * 0b1..Stall Pair C conversion in case of near empty/full FIFO conditions.
3352 * 0b0..Don't stall Pair C conversion even in case of near empty/full FIFO conditions.
3353 */
3354#define ASRC_ASRMCRC_BUFSTALLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK)
3355#define ASRC_ASRMCRC_EXTTHRSHC_MASK (0x400000U)
3356#define ASRC_ASRMCRC_EXTTHRSHC_SHIFT (22U)
3357/*! EXTTHRSHC - EXTTHRSHC
3358 * 0b1..Use external defined thresholds.
3359 * 0b0..Use default thresholds.
3360 */
3361#define ASRC_ASRMCRC_EXTTHRSHC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK)
3362#define ASRC_ASRMCRC_ZEROBUFC_MASK (0x800000U)
3363#define ASRC_ASRMCRC_ZEROBUFC_SHIFT (23U)
3364/*! ZEROBUFC - ZEROBUFC
3365 * 0b1..Don't zeroize the buffer
3366 * 0b0..Zeroize the buffer
3367 */
3368#define ASRC_ASRMCRC_ZEROBUFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK)
3369/*! @} */
3370
3371/*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */
3372/*! @{ */
3373#define ASRC_ASRFSTC_INFIFO_FILLC_MASK (0x7FU)
3374#define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT (0U)
3375/*! INFIFO_FILLC - INFIFO_FILLC
3376 */
3377#define ASRC_ASRFSTC_INFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK)
3378#define ASRC_ASRFSTC_IAEC_MASK (0x800U)
3379#define ASRC_ASRFSTC_IAEC_SHIFT (11U)
3380/*! IAEC - IAEC
3381 */
3382#define ASRC_ASRFSTC_IAEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK)
3383#define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK (0x7F000U)
3384#define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT (12U)
3385/*! OUTFIFO_FILLC - OUTFIFO_FILLC
3386 */
3387#define ASRC_ASRFSTC_OUTFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK)
3388#define ASRC_ASRFSTC_OAFC_MASK (0x800000U)
3389#define ASRC_ASRFSTC_OAFC_SHIFT (23U)
3390/*! OAFC - OAFC
3391 */
3392#define ASRC_ASRFSTC_OAFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK)
3393/*! @} */
3394
3395/*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */
3396/*! @{ */
3397#define ASRC_ASRMCR1_OW16_MASK (0x1U)
3398#define ASRC_ASRMCR1_OW16_SHIFT (0U)
3399/*! OW16 - OW16
3400 * 0b1..16-bit output data
3401 * 0b0..24-bit output data.
3402 */
3403#define ASRC_ASRMCR1_OW16(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK)
3404#define ASRC_ASRMCR1_OSGN_MASK (0x2U)
3405#define ASRC_ASRMCR1_OSGN_SHIFT (1U)
3406/*! OSGN - OSGN
3407 * 0b1..Sign extension.
3408 * 0b0..No sign extension.
3409 */
3410#define ASRC_ASRMCR1_OSGN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK)
3411#define ASRC_ASRMCR1_OMSB_MASK (0x4U)
3412#define ASRC_ASRMCR1_OMSB_SHIFT (2U)
3413/*! OMSB - OMSB
3414 * 0b1..MSB aligned.
3415 * 0b0..LSB aligned.
3416 */
3417#define ASRC_ASRMCR1_OMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK)
3418#define ASRC_ASRMCR1_IMSB_MASK (0x100U)
3419#define ASRC_ASRMCR1_IMSB_SHIFT (8U)
3420/*! IMSB - IMSB
3421 * 0b1..MSB aligned.
3422 * 0b0..LSB aligned.
3423 */
3424#define ASRC_ASRMCR1_IMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK)
3425#define ASRC_ASRMCR1_IWD_MASK (0xE00U)
3426#define ASRC_ASRMCR1_IWD_SHIFT (9U)
3427/*! IWD - IWD
3428 */
3429#define ASRC_ASRMCR1_IWD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK)
3430/*! @} */
3431
3432/* The count of ASRC_ASRMCR1 */
3433#define ASRC_ASRMCR1_COUNT (3U)
3434
3435
3436/*!
3437 * @}
3438 */ /* end of group ASRC_Register_Masks */
3439
3440
3441/* ASRC - Peripheral instance base addresses */
3442/** Peripheral ADMA__ASRC0 base address */
3443#define ADMA__ASRC0_BASE (0x59000000u)
3444/** Peripheral ADMA__ASRC0 base pointer */
3445#define ADMA__ASRC0 ((ASRC_Type *)ADMA__ASRC0_BASE)
3446/** Peripheral ADMA__ASRC1 base address */
3447#define ADMA__ASRC1_BASE (0x59800000u)
3448/** Peripheral ADMA__ASRC1 base pointer */
3449#define ADMA__ASRC1 ((ASRC_Type *)ADMA__ASRC1_BASE)
3450/** Array initializer of ASRC peripheral base addresses */
3451#define ASRC_BASE_ADDRS { ADMA__ASRC0_BASE, ADMA__ASRC1_BASE }
3452/** Array initializer of ASRC peripheral base pointers */
3453#define ASRC_BASE_PTRS { ADMA__ASRC0, ADMA__ASRC1 }
3454
3455/*!
3456 * @}
3457 */ /* end of group ASRC_Peripheral_Access_Layer */
3458
3459
3460/* ----------------------------------------------------------------------------
3461 -- BCH Peripheral Access Layer
3462 ---------------------------------------------------------------------------- */
3463
3464/*!
3465 * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer
3466 * @{
3467 */
3468
3469/** BCH - Register Layout Typedef */
3470typedef struct {
3471 struct { /* offset: 0x0 */
3472 __IO uint32_t RW; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */
3473 __IO uint32_t SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */
3474 __IO uint32_t CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */
3475 __IO uint32_t TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */
3476 } CTRL;
3477 struct { /* offset: 0x10 */
3478 __I uint32_t RW; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */
3479 __I uint32_t SET; /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */
3480 __I uint32_t CLR; /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */
3481 __I uint32_t TOG; /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */
3482 } STATUS0;
3483 struct { /* offset: 0x20 */
3484 __IO uint32_t RW; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */
3485 __IO uint32_t SET; /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */
3486 __IO uint32_t CLR; /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */
3487 __IO uint32_t TOG; /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */
3488 } MODE;
3489 struct { /* offset: 0x30 */
3490 __IO uint32_t RW; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */
3491 __IO uint32_t SET; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */
3492 __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */
3493 __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */
3494 } ENCODEPTR;
3495 struct { /* offset: 0x40 */
3496 __IO uint32_t RW; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */
3497 __IO uint32_t SET; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */
3498 __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */
3499 __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */
3500 } DATAPTR;
3501 struct { /* offset: 0x50 */
3502 __IO uint32_t RW; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */
3503 __IO uint32_t SET; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */
3504 __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */
3505 __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */
3506 } METAPTR;
3507 uint8_t RESERVED_0[16];
3508 struct { /* offset: 0x70 */
3509 __IO uint32_t RW; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */
3510 __IO uint32_t SET; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */
3511 __IO uint32_t CLR; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */
3512 __IO uint32_t TOG; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */
3513 } LAYOUTSELECT;
3514 struct { /* offset: 0x80 */
3515 __IO uint32_t RW; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */
3516 __IO uint32_t SET; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */
3517 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */
3518 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */
3519 } FLASH0LAYOUT0;
3520 struct { /* offset: 0x90 */
3521 __IO uint32_t RW; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */
3522 __IO uint32_t SET; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */
3523 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */
3524 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */
3525 } FLASH0LAYOUT1;
3526 struct { /* offset: 0xA0 */
3527 __IO uint32_t RW; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */
3528 __IO uint32_t SET; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */
3529 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */
3530 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */
3531 } FLASH1LAYOUT0;
3532 struct { /* offset: 0xB0 */
3533 __IO uint32_t RW; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */
3534 __IO uint32_t SET; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */
3535 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */
3536 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */
3537 } FLASH1LAYOUT1;
3538 struct { /* offset: 0xC0 */
3539 __IO uint32_t RW; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */
3540 __IO uint32_t SET; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */
3541 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */
3542 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */
3543 } FLASH2LAYOUT0;
3544 struct { /* offset: 0xD0 */
3545 __IO uint32_t RW; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */
3546 __IO uint32_t SET; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */
3547 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */
3548 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */
3549 } FLASH2LAYOUT1;
3550 struct { /* offset: 0xE0 */
3551 __IO uint32_t RW; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */
3552 __IO uint32_t SET; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */
3553 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */
3554 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */
3555 } FLASH3LAYOUT0;
3556 struct { /* offset: 0xF0 */
3557 __IO uint32_t RW; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */
3558 __IO uint32_t SET; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */
3559 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */
3560 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */
3561 } FLASH3LAYOUT1;
3562 struct { /* offset: 0x100 */
3563 __IO uint32_t RW; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */
3564 __IO uint32_t SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */
3565 __IO uint32_t CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */
3566 __IO uint32_t TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */
3567 } DEBUG0;
3568 struct { /* offset: 0x110 */
3569 __I uint32_t RW; /**< KES Debug Read Register, offset: 0x110 */
3570 __I uint32_t SET; /**< KES Debug Read Register, offset: 0x114 */
3571 __I uint32_t CLR; /**< KES Debug Read Register, offset: 0x118 */
3572 __I uint32_t TOG; /**< KES Debug Read Register, offset: 0x11C */
3573 } DBGKESREAD;
3574 struct { /* offset: 0x120 */
3575 __I uint32_t RW; /**< Chien Search Debug Read Register, offset: 0x120 */
3576 __I uint32_t SET; /**< Chien Search Debug Read Register, offset: 0x124 */
3577 __I uint32_t CLR; /**< Chien Search Debug Read Register, offset: 0x128 */
3578 __I uint32_t TOG; /**< Chien Search Debug Read Register, offset: 0x12C */
3579 } DBGCSFEREAD;
3580 struct { /* offset: 0x130 */
3581 __I uint32_t RW; /**< Syndrome Generator Debug Read Register, offset: 0x130 */
3582 __I uint32_t SET; /**< Syndrome Generator Debug Read Register, offset: 0x134 */
3583 __I uint32_t CLR; /**< Syndrome Generator Debug Read Register, offset: 0x138 */
3584 __I uint32_t TOG; /**< Syndrome Generator Debug Read Register, offset: 0x13C */
3585 } DBGSYNDGENREAD;
3586 struct { /* offset: 0x140 */
3587 __I uint32_t RW; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */
3588 __I uint32_t SET; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */
3589 __I uint32_t CLR; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */
3590 __I uint32_t TOG; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */
3591 } DBGAHBMREAD;
3592 struct { /* offset: 0x150 */
3593 __I uint32_t RW; /**< Block Name Register, offset: 0x150 */
3594 __I uint32_t SET; /**< Block Name Register, offset: 0x154 */
3595 __I uint32_t CLR; /**< Block Name Register, offset: 0x158 */
3596 __I uint32_t TOG; /**< Block Name Register, offset: 0x15C */
3597 } BLOCKNAME;
3598 struct { /* offset: 0x160 */
3599 __I uint32_t RW; /**< BCH Version Register, offset: 0x160 */
3600 __I uint32_t SET; /**< BCH Version Register, offset: 0x164 */
3601 __I uint32_t CLR; /**< BCH Version Register, offset: 0x168 */
3602 __I uint32_t TOG; /**< BCH Version Register, offset: 0x16C */
3603 } VERSION;
3604 struct { /* offset: 0x170 */
3605 __IO uint32_t RW; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */
3606 __IO uint32_t SET; /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */
3607 __IO uint32_t CLR; /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */
3608 __IO uint32_t TOG; /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */
3609 } DEBUG1;
3610} BCH_Type;
3611
3612/* ----------------------------------------------------------------------------
3613 -- BCH Register Masks
3614 ---------------------------------------------------------------------------- */
3615
3616/*!
3617 * @addtogroup BCH_Register_Masks BCH Register Masks
3618 * @{
3619 */
3620
3621/*! @name CTRL - Hardware BCH ECC Accelerator Control Register */
3622/*! @{ */
3623#define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U)
3624#define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U)
3625/*! COMPLETE_IRQ - COMPLETE_IRQ
3626 */
3627#define BCH_CTRL_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK)
3628#define BCH_CTRL_RSVD0_MASK (0x2U)
3629#define BCH_CTRL_RSVD0_SHIFT (1U)
3630/*! RSVD0 - This field is reserved.
3631 */
3632#define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK)
3633#define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U)
3634#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U)
3635/*! DEBUG_STALL_IRQ - DEBUG_STALL_IRQ
3636 */
3637#define BCH_CTRL_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK)
3638#define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U)
3639#define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U)
3640/*! BM_ERROR_IRQ - BM_ERROR_IRQ
3641 */
3642#define BCH_CTRL_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK)
3643#define BCH_CTRL_RSVD1_MASK (0xF0U)
3644#define BCH_CTRL_RSVD1_SHIFT (4U)
3645/*! RSVD1 - This field is reserved.
3646 */
3647#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK)
3648#define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U)
3649#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U)
3650/*! COMPLETE_IRQ_EN - COMPLETE_IRQ_EN
3651 */
3652#define BCH_CTRL_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK)
3653#define BCH_CTRL_RSVD2_MASK (0x200U)
3654#define BCH_CTRL_RSVD2_SHIFT (9U)
3655/*! RSVD2 - This field is reserved.
3656 */
3657#define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK)
3658#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U)
3659#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U)
3660/*! DEBUG_STALL_IRQ_EN - DEBUG_STALL_IRQ_EN
3661 */
3662#define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK)
3663#define BCH_CTRL_RSVD3_MASK (0xF800U)
3664#define BCH_CTRL_RSVD3_SHIFT (11U)
3665/*! RSVD3 - This field is reserved.
3666 */
3667#define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK)
3668#define BCH_CTRL_M2M_ENABLE_MASK (0x10000U)
3669#define BCH_CTRL_M2M_ENABLE_SHIFT (16U)
3670/*! M2M_ENABLE - M2M_ENABLE
3671 */
3672#define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK)
3673#define BCH_CTRL_M2M_ENCODE_MASK (0x20000U)
3674#define BCH_CTRL_M2M_ENCODE_SHIFT (17U)
3675/*! M2M_ENCODE - M2M_ENCODE
3676 */
3677#define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK)
3678#define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U)
3679#define BCH_CTRL_M2M_LAYOUT_SHIFT (18U)
3680/*! M2M_LAYOUT - M2M_LAYOUT
3681 */
3682#define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK)
3683#define BCH_CTRL_RSVD4_MASK (0x300000U)
3684#define BCH_CTRL_RSVD4_SHIFT (20U)
3685/*! RSVD4 - This field is reserved.
3686 */
3687#define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK)
3688#define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U)
3689#define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U)
3690/*! DEBUGSYNDROME - DEBUGSYNDROME
3691 */
3692#define BCH_CTRL_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK)
3693#define BCH_CTRL_RSVD5_MASK (0x3F800000U)
3694#define BCH_CTRL_RSVD5_SHIFT (23U)
3695/*! RSVD5 - This field is reserved.
3696 */
3697#define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK)
3698#define BCH_CTRL_CLKGATE_MASK (0x40000000U)
3699#define BCH_CTRL_CLKGATE_SHIFT (30U)
3700/*! CLKGATE - CLKGATE
3701 * 0b0..Allow BCH to operate normally.
3702 * 0b1..Do not clock BCH gates in order to minimize power consumption.
3703 */
3704#define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK)
3705#define BCH_CTRL_SFTRST_MASK (0x80000000U)
3706#define BCH_CTRL_SFTRST_SHIFT (31U)
3707/*! SFTRST - SFTRST
3708 * 0b0..Allow BCH to operate normally.
3709 * 0b1..Hold BCH in reset.
3710 */
3711#define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK)
3712/*! @} */
3713
3714/*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */
3715/*! @{ */
3716#define BCH_STATUS0_RSVD0_MASK (0x3U)
3717#define BCH_STATUS0_RSVD0_SHIFT (0U)
3718/*! RSVD0 - This field is reserved.
3719 */
3720#define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK)
3721#define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U)
3722#define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U)
3723/*! UNCORRECTABLE - UNCORRECTABLE
3724 */
3725#define BCH_STATUS0_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK)
3726#define BCH_STATUS0_CORRECTED_MASK (0x8U)
3727#define BCH_STATUS0_CORRECTED_SHIFT (3U)
3728/*! CORRECTED - CORRECTED
3729 */
3730#define BCH_STATUS0_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK)
3731#define BCH_STATUS0_ALLONES_MASK (0x10U)
3732#define BCH_STATUS0_ALLONES_SHIFT (4U)
3733/*! ALLONES - ALLONES
3734 */
3735#define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK)
3736#define BCH_STATUS0_RSVD1_MASK (0xE0U)
3737#define BCH_STATUS0_RSVD1_SHIFT (5U)
3738/*! RSVD1 - This field is reserved.
3739 */
3740#define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK)
3741#define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U)
3742#define BCH_STATUS0_STATUS_BLK0_SHIFT (8U)
3743/*! STATUS_BLK0 - STATUS_BLK0
3744 * 0b00000000..No errors found on block.
3745 * 0b00000001..One error found on block.
3746 * 0b00000010..One errors found on block.
3747 * 0b00000011..One errors found on block.
3748 * 0b00000100..One errors found on block.
3749 * 0b11111110..Block exhibited uncorrectable errors.
3750 * 0b11111111..Page is erased.
3751 */
3752#define BCH_STATUS0_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK)
3753#define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U)
3754#define BCH_STATUS0_COMPLETED_CE_SHIFT (16U)
3755/*! COMPLETED_CE - COMPLETED_CE
3756 */
3757#define BCH_STATUS0_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK)
3758#define BCH_STATUS0_HANDLE_MASK (0xFFF00000U)
3759#define BCH_STATUS0_HANDLE_SHIFT (20U)
3760/*! HANDLE - HANDLE
3761 */
3762#define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK)
3763/*! @} */
3764
3765/*! @name MODE - Hardware ECC Accelerator Mode Register */
3766/*! @{ */
3767#define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU)
3768#define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U)
3769/*! ERASE_THRESHOLD - ERASE_THRESHOLD
3770 */
3771#define BCH_MODE_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK)
3772#define BCH_MODE_RSVD_MASK (0xFFFFFF00U)
3773#define BCH_MODE_RSVD_SHIFT (8U)
3774/*! RSVD - This field is reserved.
3775 */
3776#define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK)
3777/*! @} */
3778
3779/*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */
3780/*! @{ */
3781#define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU)
3782#define BCH_ENCODEPTR_ADDR_SHIFT (0U)
3783/*! ADDR - ADDR
3784 */
3785#define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK)
3786/*! @} */
3787
3788/*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */
3789/*! @{ */
3790#define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU)
3791#define BCH_DATAPTR_ADDR_SHIFT (0U)
3792/*! ADDR - ADDR
3793 */
3794#define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK)
3795/*! @} */
3796
3797/*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */
3798/*! @{ */
3799#define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU)
3800#define BCH_METAPTR_ADDR_SHIFT (0U)
3801/*! ADDR - ADDR
3802 */
3803#define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK)
3804/*! @} */
3805
3806/*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */
3807/*! @{ */
3808#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U)
3809#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U)
3810/*! CS0_SELECT - CS0_SELECT
3811 */
3812#define BCH_LAYOUTSELECT_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK)
3813#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU)
3814#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U)
3815/*! CS1_SELECT - CS1_SELECT
3816 */
3817#define BCH_LAYOUTSELECT_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK)
3818#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U)
3819#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U)
3820/*! CS2_SELECT - CS2_SELECT
3821 */
3822#define BCH_LAYOUTSELECT_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK)
3823#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U)
3824#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U)
3825/*! CS3_SELECT - CS3_SELECT
3826 */
3827#define BCH_LAYOUTSELECT_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK)
3828#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U)
3829#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U)
3830/*! CS4_SELECT - CS4_SELECT
3831 */
3832#define BCH_LAYOUTSELECT_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK)
3833#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U)
3834#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U)
3835/*! CS5_SELECT - CS5_SELECT
3836 */
3837#define BCH_LAYOUTSELECT_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK)
3838#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U)
3839#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U)
3840/*! CS6_SELECT - CS6_SELECT
3841 */
3842#define BCH_LAYOUTSELECT_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK)
3843#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U)
3844#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U)
3845/*! CS7_SELECT - CS7_SELECT
3846 */
3847#define BCH_LAYOUTSELECT_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK)
3848#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U)
3849#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U)
3850/*! CS8_SELECT - CS8_SELECT
3851 */
3852#define BCH_LAYOUTSELECT_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK)
3853#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U)
3854#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U)
3855/*! CS9_SELECT - CS9_SELECT
3856 */
3857#define BCH_LAYOUTSELECT_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK)
3858#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U)
3859#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U)
3860/*! CS10_SELECT - CS10_SELECT
3861 */
3862#define BCH_LAYOUTSELECT_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK)
3863#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U)
3864#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U)
3865/*! CS11_SELECT - CS11_SELECT
3866 */
3867#define BCH_LAYOUTSELECT_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK)
3868#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U)
3869#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U)
3870/*! CS12_SELECT - CS12_SELECT
3871 */
3872#define BCH_LAYOUTSELECT_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK)
3873#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U)
3874#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U)
3875/*! CS13_SELECT - CS13_SELECT
3876 */
3877#define BCH_LAYOUTSELECT_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK)
3878#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U)
3879#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U)
3880/*! CS14_SELECT - CS14_SELECT
3881 */
3882#define BCH_LAYOUTSELECT_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK)
3883#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U)
3884#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U)
3885/*! CS15_SELECT - CS15_SELECT
3886 */
3887#define BCH_LAYOUTSELECT_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK)
3888/*! @} */
3889
3890/*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */
3891/*! @{ */
3892#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
3893#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U)
3894/*! DATA0_SIZE - DATA0_SIZE
3895 */
3896#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK)
3897#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
3898#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
3899/*! GF13_0_GF14_1 - GF13_0_GF14_1
3900 */
3901#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK)
3902#define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF800U)
3903#define BCH_FLASH0LAYOUT0_ECC0_SHIFT (11U)
3904/*! ECC0 - ECC0
3905 * 0b00000..No ECC to be performed
3906 * 0b00001..ECC 2 to be performed
3907 * 0b00010..ECC 4 to be performed
3908 * 0b11110..ECC 60 to be performed
3909 * 0b11111..ECC 62 to be performed
3910 */
3911#define BCH_FLASH0LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK)
3912#define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U)
3913#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U)
3914/*! META_SIZE - META_SIZE
3915 */
3916#define BCH_FLASH0LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK)
3917#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U)
3918#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U)
3919/*! NBLOCKS - NBLOCKS
3920 */
3921#define BCH_FLASH0LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK)
3922/*! @} */
3923
3924/*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */
3925/*! @{ */
3926#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
3927#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U)
3928/*! DATAN_SIZE - DATAN_SIZE
3929 */
3930#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK)
3931#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
3932#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
3933/*! GF13_0_GF14_1 - GF13_0_GF14_1
3934 */
3935#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK)
3936#define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF800U)
3937#define BCH_FLASH0LAYOUT1_ECCN_SHIFT (11U)
3938/*! ECCN - ECCN
3939 * 0b00000..No ECC to be performed
3940 * 0b00001..ECC 2 to be performed
3941 * 0b00010..ECC 4 to be performed
3942 * 0b11110..ECC 60 to be performed
3943 * 0b11111..ECC 62 to be performed
3944 */
3945#define BCH_FLASH0LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK)
3946#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
3947#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U)
3948/*! PAGE_SIZE - PAGE_SIZE
3949 */
3950#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK)
3951/*! @} */
3952
3953/*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */
3954/*! @{ */
3955#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
3956#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U)
3957/*! DATA0_SIZE - DATA0_SIZE
3958 */
3959#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK)
3960#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
3961#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
3962/*! GF13_0_GF14_1 - GF13_0_GF14_1
3963 */
3964#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK)
3965#define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF800U)
3966#define BCH_FLASH1LAYOUT0_ECC0_SHIFT (11U)
3967/*! ECC0 - ECC0
3968 * 0b00000..No ECC to be performed
3969 * 0b00001..ECC 2 to be performed
3970 * 0b00010..ECC 4 to be performed
3971 * 0b11110..ECC 60 to be performed
3972 * 0b11111..ECC 62 to be performed
3973 */
3974#define BCH_FLASH1LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK)
3975#define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U)
3976#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U)
3977/*! META_SIZE - META_SIZE
3978 */
3979#define BCH_FLASH1LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK)
3980#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U)
3981#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U)
3982/*! NBLOCKS - NBLOCKS
3983 */
3984#define BCH_FLASH1LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK)
3985/*! @} */
3986
3987/*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */
3988/*! @{ */
3989#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
3990#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U)
3991/*! DATAN_SIZE - DATAN_SIZE
3992 */
3993#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK)
3994#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
3995#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
3996/*! GF13_0_GF14_1 - GF13_0_GF14_1
3997 */
3998#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK)
3999#define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF800U)
4000#define BCH_FLASH1LAYOUT1_ECCN_SHIFT (11U)
4001/*! ECCN - ECCN
4002 * 0b00000..No ECC to be performed
4003 * 0b00001..ECC 2 to be performed
4004 * 0b00010..ECC 4 to be performed
4005 * 0b11110..ECC 60 to be performed
4006 * 0b11111..ECC 62 to be performed
4007 */
4008#define BCH_FLASH1LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK)
4009#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
4010#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U)
4011/*! PAGE_SIZE - PAGE_SIZE
4012 */
4013#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK)
4014/*! @} */
4015
4016/*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */
4017/*! @{ */
4018#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
4019#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U)
4020/*! DATA0_SIZE - DATA0_SIZE
4021 */
4022#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK)
4023#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
4024#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
4025/*! GF13_0_GF14_1 - GF13_0_GF14_1
4026 */
4027#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK)
4028#define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF800U)
4029#define BCH_FLASH2LAYOUT0_ECC0_SHIFT (11U)
4030/*! ECC0 - ECC0
4031 * 0b00000..No ECC to be performed
4032 * 0b00001..ECC 2 to be performed
4033 * 0b00010..ECC 4 to be performed
4034 * 0b11110..ECC 60 to be performed
4035 * 0b11111..ECC 62 to be performed
4036 */
4037#define BCH_FLASH2LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK)
4038#define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U)
4039#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U)
4040/*! META_SIZE - META_SIZE
4041 */
4042#define BCH_FLASH2LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK)
4043#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U)
4044#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U)
4045/*! NBLOCKS - NBLOCKS
4046 */
4047#define BCH_FLASH2LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK)
4048/*! @} */
4049
4050/*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */
4051/*! @{ */
4052#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
4053#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U)
4054/*! DATAN_SIZE - DATAN_SIZE
4055 */
4056#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK)
4057#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
4058#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
4059/*! GF13_0_GF14_1 - GF13_0_GF14_1
4060 */
4061#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK)
4062#define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF800U)
4063#define BCH_FLASH2LAYOUT1_ECCN_SHIFT (11U)
4064/*! ECCN - ECCN
4065 * 0b00000..No ECC to be performed
4066 * 0b00001..ECC 2 to be performed
4067 * 0b00010..ECC 4 to be performed
4068 * 0b11110..ECC 60 to be performed
4069 * 0b11111..ECC 62 to be performed
4070 */
4071#define BCH_FLASH2LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK)
4072#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
4073#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U)
4074/*! PAGE_SIZE - PAGE_SIZE
4075 */
4076#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK)
4077/*! @} */
4078
4079/*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */
4080/*! @{ */
4081#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
4082#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U)
4083/*! DATA0_SIZE - DATA0_SIZE
4084 */
4085#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK)
4086#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
4087#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
4088/*! GF13_0_GF14_1 - GF13_0_GF14_1
4089 */
4090#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK)
4091#define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF800U)
4092#define BCH_FLASH3LAYOUT0_ECC0_SHIFT (11U)
4093/*! ECC0 - ECC0
4094 * 0b00000..No ECC to be performed
4095 * 0b00001..ECC 2 to be performed
4096 * 0b00010..ECC 4 to be performed
4097 * 0b11110..ECC 60 to be performed
4098 * 0b11111..ECC 62 to be performed
4099 */
4100#define BCH_FLASH3LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK)
4101#define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U)
4102#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U)
4103/*! META_SIZE - META_SIZE
4104 */
4105#define BCH_FLASH3LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK)
4106#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U)
4107#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U)
4108/*! NBLOCKS - NBLOCKS
4109 */
4110#define BCH_FLASH3LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK)
4111/*! @} */
4112
4113/*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */
4114/*! @{ */
4115#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
4116#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U)
4117/*! DATAN_SIZE - DATAN_SIZE
4118 */
4119#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK)
4120#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
4121#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
4122/*! GF13_0_GF14_1 - GF13_0_GF14_1
4123 */
4124#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK)
4125#define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF800U)
4126#define BCH_FLASH3LAYOUT1_ECCN_SHIFT (11U)
4127/*! ECCN - ECCN
4128 * 0b00000..No ECC to be performed
4129 * 0b00001..ECC 2 to be performed
4130 * 0b00010..ECC 4 to be performed
4131 * 0b11110..ECC 60 to be performed
4132 * 0b11111..ECC 62 to be performed
4133 */
4134#define BCH_FLASH3LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK)
4135#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
4136#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U)
4137/*! PAGE_SIZE - PAGE_SIZE
4138 */
4139#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK)
4140/*! @} */
4141
4142/*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */
4143/*! @{ */
4144#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU)
4145#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U)
4146/*! DEBUG_REG_SELECT - DEBUG_REG_SELECT
4147 */
4148#define BCH_DEBUG0_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK)
4149#define BCH_DEBUG0_RSVD0_MASK (0xC0U)
4150#define BCH_DEBUG0_RSVD0_SHIFT (6U)
4151/*! RSVD0 - This field is reserved.
4152 */
4153#define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK)
4154#define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK (0x100U)
4155#define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT (8U)
4156/*! BM_KES_TEST_BYPASS - BM_KES_TEST_BYPASS
4157 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
4158 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
4159 */
4160#define BCH_DEBUG0_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK)
4161#define BCH_DEBUG0_KES_DEBUG_STALL_MASK (0x200U)
4162#define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT (9U)
4163/*! KES_DEBUG_STALL - KES_DEBUG_STALL
4164 * 0b0..KES FSM proceeds to next block supplied by bus master.
4165 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
4166 */
4167#define BCH_DEBUG0_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK)
4168#define BCH_DEBUG0_KES_DEBUG_STEP_MASK (0x400U)
4169#define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT (10U)
4170/*! KES_DEBUG_STEP - KES_DEBUG_STEP
4171 */
4172#define BCH_DEBUG0_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK)
4173#define BCH_DEBUG0_KES_STANDALONE_MASK (0x800U)
4174#define BCH_DEBUG0_KES_STANDALONE_SHIFT (11U)
4175/*! KES_STANDALONE - KES_STANDALONE
4176 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
4177 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
4178 */
4179#define BCH_DEBUG0_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK)
4180#define BCH_DEBUG0_KES_DEBUG_KICK_MASK (0x1000U)
4181#define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT (12U)
4182/*! KES_DEBUG_KICK - KES_DEBUG_KICK
4183 */
4184#define BCH_DEBUG0_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK)
4185#define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK (0x2000U)
4186#define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT (13U)
4187/*! KES_DEBUG_MODE4K - KES_DEBUG_MODE4K
4188 * 0b1..Mode is set for 4K NAND pages.
4189 * 0b1..Mode is set for 2K NAND pages.
4190 */
4191#define BCH_DEBUG0_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK)
4192#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
4193#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
4194/*! KES_DEBUG_PAYLOAD_FLAG - KES_DEBUG_PAYLOAD_FLAG
4195 * 0b1..Payload is set for 512 bytes data block.
4196 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
4197 */
4198#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK)
4199#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
4200#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
4201/*! KES_DEBUG_SHIFT_SYND - KES_DEBUG_SHIFT_SYND
4202 */
4203#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK)
4204#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
4205#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
4206/*! KES_DEBUG_SYNDROME_SYMBOL - KES_DEBUG_SYNDROME_SYMBOL
4207 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
4208 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
4209 */
4210#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK)
4211#define BCH_DEBUG0_RSVD1_MASK (0xFE000000U)
4212#define BCH_DEBUG0_RSVD1_SHIFT (25U)
4213/*! RSVD1 - This field is reserved.
4214 */
4215#define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK)
4216/*! @} */
4217
4218/*! @name DBGKESREAD - KES Debug Read Register */
4219/*! @{ */
4220#define BCH_DBGKESREAD_VALUES_MASK (0xFFFFFFFFU)
4221#define BCH_DBGKESREAD_VALUES_SHIFT (0U)
4222/*! VALUES - VALUES
4223 */
4224#define BCH_DBGKESREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK)
4225/*! @} */
4226
4227/*! @name DBGCSFEREAD - Chien Search Debug Read Register */
4228/*! @{ */
4229#define BCH_DBGCSFEREAD_VALUES_MASK (0xFFFFFFFFU)
4230#define BCH_DBGCSFEREAD_VALUES_SHIFT (0U)
4231/*! VALUES - VALUES
4232 */
4233#define BCH_DBGCSFEREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK)
4234/*! @} */
4235
4236/*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */
4237/*! @{ */
4238#define BCH_DBGSYNDGENREAD_VALUES_MASK (0xFFFFFFFFU)
4239#define BCH_DBGSYNDGENREAD_VALUES_SHIFT (0U)
4240/*! VALUES - VALUES
4241 */
4242#define BCH_DBGSYNDGENREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK)
4243/*! @} */
4244
4245/*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */
4246/*! @{ */
4247#define BCH_DBGAHBMREAD_VALUES_MASK (0xFFFFFFFFU)
4248#define BCH_DBGAHBMREAD_VALUES_SHIFT (0U)
4249/*! VALUES - VALUES
4250 */
4251#define BCH_DBGAHBMREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK)
4252/*! @} */
4253
4254/*! @name BLOCKNAME - Block Name Register */
4255/*! @{ */
4256#define BCH_BLOCKNAME_NAME_MASK (0xFFFFFFFFU)
4257#define BCH_BLOCKNAME_NAME_SHIFT (0U)
4258/*! NAME - NAME
4259 */
4260#define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK)
4261/*! @} */
4262
4263/*! @name VERSION - BCH Version Register */
4264/*! @{ */
4265#define BCH_VERSION_STEP_MASK (0xFFFFU)
4266#define BCH_VERSION_STEP_SHIFT (0U)
4267/*! STEP - STEP
4268 */
4269#define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK)
4270#define BCH_VERSION_MINOR_MASK (0xFF0000U)
4271#define BCH_VERSION_MINOR_SHIFT (16U)
4272/*! MINOR - MINOR
4273 */
4274#define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK)
4275#define BCH_VERSION_MAJOR_MASK (0xFF000000U)
4276#define BCH_VERSION_MAJOR_SHIFT (24U)
4277/*! MAJOR - MAJOR
4278 */
4279#define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK)
4280/*! @} */
4281
4282/*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */
4283/*! @{ */
4284#define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK (0x1FFU)
4285#define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT (0U)
4286/*! ERASED_ZERO_COUNT - ERASED_ZERO_COUNT
4287 */
4288#define BCH_DEBUG1_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK)
4289#define BCH_DEBUG1_RSVD_MASK (0x7FFFFE00U)
4290#define BCH_DEBUG1_RSVD_SHIFT (9U)
4291/*! RSVD - This field is reserved.
4292 */
4293#define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK)
4294#define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK (0x80000000U)
4295#define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT (31U)
4296/*! DEBUG1_PREERASECHK - DEBUG1_PREERASECHK
4297 * 0b0..Turn off pre-erase check
4298 * 0b1..Turn on pre-erase check
4299 */
4300#define BCH_DEBUG1_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK)
4301/*! @} */
4302
4303
4304/*!
4305 * @}
4306 */ /* end of group BCH_Register_Masks */
4307
4308
4309/* BCH - Peripheral instance base addresses */
4310/** Peripheral CONNECTIVITY__BCH base address */
4311#define CONNECTIVITY__BCH_BASE (0x5B814000u)
4312/** Peripheral CONNECTIVITY__BCH base pointer */
4313#define CONNECTIVITY__BCH ((BCH_Type *)CONNECTIVITY__BCH_BASE)
4314/** Array initializer of BCH peripheral base addresses */
4315#define BCH_BASE_ADDRS { CONNECTIVITY__BCH_BASE }
4316/** Array initializer of BCH peripheral base pointers */
4317#define BCH_BASE_PTRS { CONNECTIVITY__BCH }
4318
4319/*!
4320 * @}
4321 */ /* end of group BCH_Peripheral_Access_Layer */
4322
4323
4324/* ----------------------------------------------------------------------------
4325 -- CAN Peripheral Access Layer
4326 ---------------------------------------------------------------------------- */
4327
4328/*!
4329 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
4330 * @{
4331 */
4332
4333/** CAN - Register Layout Typedef */
4334typedef struct {
4335 __IO uint32_t MCR; /**< Module Configuration register, offset: 0x0 */
4336 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
4337 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
4338 uint8_t RESERVED_0[4];
4339 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask register, offset: 0x10 */
4340 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
4341 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
4342 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
4343 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
4344 __IO uint32_t IMASK2; /**< Interrupt Masks 2 register, offset: 0x24 */
4345 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
4346 __IO uint32_t IFLAG2; /**< Interrupt Flags 2 register, offset: 0x2C */
4347 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
4348 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
4349 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
4350 uint8_t RESERVED_1[8];
4351 __I uint32_t CRCR; /**< CRC register, offset: 0x44 */
4352 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
4353 __I uint32_t RXFIR; /**< Rx FIFO Information register, offset: 0x4C */
4354 __IO uint32_t CBT; /**< CAN Bit Timing register, offset: 0x50 */
4355 uint8_t RESERVED_2[4];
4356 __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */
4357 __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */
4358 uint8_t RESERVED_3[32];
4359 struct { /* offset: 0x80, array step: 0x10 */
4360 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
4361 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
4362 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
4363 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
4364 } MB[64];
4365 uint8_t RESERVED_4[1024];
4366 __IO uint32_t RXIMR[64]; /**< Rx Individual Mask registers, array offset: 0x880, array step: 0x4 */
4367 uint8_t RESERVED_5[640];
4368 __IO uint32_t FDCTRL; /**< CAN FD Control register, offset: 0xC00 */
4369 __IO uint32_t FDCBT; /**< CAN FD Bit Timing register, offset: 0xC04 */
4370 __I uint32_t FDCRC; /**< CAN FD CRC register, offset: 0xC08 */
4371} CAN_Type;
4372
4373/* ----------------------------------------------------------------------------
4374 -- CAN Register Masks
4375 ---------------------------------------------------------------------------- */
4376
4377/*!
4378 * @addtogroup CAN_Register_Masks CAN Register Masks
4379 * @{
4380 */
4381
4382/*! @name MCR - Module Configuration register */
4383/*! @{ */
4384#define CAN_MCR_MAXMB_MASK (0x7FU)
4385#define CAN_MCR_MAXMB_SHIFT (0U)
4386/*! MAXMB - Number Of The Last Message Buffer
4387 */
4388#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
4389#define CAN_MCR_IDAM_MASK (0x300U)
4390#define CAN_MCR_IDAM_SHIFT (8U)
4391/*! IDAM - ID Acceptance Mode
4392 * 0b00..Format A: One full ID (standard and extended) per ID filter table element.
4393 * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element.
4394 * 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element.
4395 * 0b11..Format D: All frames rejected.
4396 */
4397#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
4398#define CAN_MCR_FDEN_MASK (0x800U)
4399#define CAN_MCR_FDEN_SHIFT (11U)
4400/*! FDEN - CAN FD operation enable
4401 * 0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
4402 * 0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
4403 */
4404#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
4405#define CAN_MCR_AEN_MASK (0x1000U)
4406#define CAN_MCR_AEN_SHIFT (12U)
4407/*! AEN - Abort Enable
4408 * 0b0..Abort disabled.
4409 * 0b1..Abort enabled.
4410 */
4411#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
4412#define CAN_MCR_LPRIOEN_MASK (0x2000U)
4413#define CAN_MCR_LPRIOEN_SHIFT (13U)
4414/*! LPRIOEN - Local Priority Enable
4415 * 0b0..Local Priority disabled.
4416 * 0b1..Local Priority enabled.
4417 */
4418#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
4419#define CAN_MCR_DMA_MASK (0x8000U)
4420#define CAN_MCR_DMA_SHIFT (15U)
4421/*! DMA - DMA Enable
4422 * 0b0..DMA feature for RX FIFO disabled.
4423 * 0b1..DMA feature for RX FIFO enabled.
4424 */
4425#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
4426#define CAN_MCR_IRMQ_MASK (0x10000U)
4427#define CAN_MCR_IRMQ_SHIFT (16U)
4428/*! IRMQ - Individual Rx Masking And Queue Enable
4429 * 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy
4430 * applications, the reading of C/S word locks the MB even if it is EMPTY.
4431 * 0b1..Individual Rx masking and queue feature are enabled.
4432 */
4433#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
4434#define CAN_MCR_SRXDIS_MASK (0x20000U)
4435#define CAN_MCR_SRXDIS_SHIFT (17U)
4436/*! SRXDIS - Self Reception Disable
4437 * 0b0..Self-reception enabled.
4438 * 0b1..Self-reception disabled.
4439 */
4440#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
4441#define CAN_MCR_DOZE_MASK (0x40000U)
4442#define CAN_MCR_DOZE_SHIFT (18U)
4443/*! DOZE - Doze Mode Enable
4444 * 0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested.
4445 * 0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.
4446 */
4447#define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
4448#define CAN_MCR_WAKSRC_MASK (0x80000U)
4449#define CAN_MCR_WAKSRC_SHIFT (19U)
4450/*! WAKSRC - Wake Up Source
4451 * 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
4452 * 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
4453 */
4454#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
4455#define CAN_MCR_LPMACK_MASK (0x100000U)
4456#define CAN_MCR_LPMACK_SHIFT (20U)
4457/*! LPMACK - Low-Power Mode Acknowledge
4458 * 0b0..FlexCAN is not in a low-power mode.
4459 * 0b1..FlexCAN is in a low-power mode.
4460 */
4461#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
4462#define CAN_MCR_WRNEN_MASK (0x200000U)
4463#define CAN_MCR_WRNEN_SHIFT (21U)
4464/*! WRNEN - Warning Interrupt Enable
4465 * 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
4466 * 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
4467 */
4468#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
4469#define CAN_MCR_SLFWAK_MASK (0x400000U)
4470#define CAN_MCR_SLFWAK_SHIFT (22U)
4471/*! SLFWAK - Self Wake Up
4472 * 0b0..FlexCAN Self Wake Up feature is disabled.
4473 * 0b1..FlexCAN Self Wake Up feature is enabled.
4474 */
4475#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
4476#define CAN_MCR_FRZACK_MASK (0x1000000U)
4477#define CAN_MCR_FRZACK_SHIFT (24U)
4478/*! FRZACK - Freeze Mode Acknowledge
4479 * 0b0..FlexCAN not in Freeze mode, prescaler running.
4480 * 0b1..FlexCAN in Freeze mode, prescaler stopped.
4481 */
4482#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
4483#define CAN_MCR_SOFTRST_MASK (0x2000000U)
4484#define CAN_MCR_SOFTRST_SHIFT (25U)
4485/*! SOFTRST - Soft Reset
4486 * 0b0..No reset request.
4487 * 0b1..Resets the registers affected by soft reset.
4488 */
4489#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
4490#define CAN_MCR_WAKMSK_MASK (0x4000000U)
4491#define CAN_MCR_WAKMSK_SHIFT (26U)
4492/*! WAKMSK - Wake Up Interrupt Mask
4493 * 0b0..Wake Up interrupt is disabled.
4494 * 0b1..Wake Up interrupt is enabled.
4495 */
4496#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
4497#define CAN_MCR_NOTRDY_MASK (0x8000000U)
4498#define CAN_MCR_NOTRDY_SHIFT (27U)
4499/*! NOTRDY - FlexCAN Not Ready
4500 * 0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode.
4501 * 0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode.
4502 */
4503#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
4504#define CAN_MCR_HALT_MASK (0x10000000U)
4505#define CAN_MCR_HALT_SHIFT (28U)
4506/*! HALT - Halt FlexCAN
4507 * 0b0..No Freeze mode request.
4508 * 0b1..Enters Freeze mode if the FRZ bit is asserted.
4509 */
4510#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
4511#define CAN_MCR_RFEN_MASK (0x20000000U)
4512#define CAN_MCR_RFEN_SHIFT (29U)
4513/*! RFEN - Rx FIFO Enable
4514 * 0b0..Rx FIFO not enabled.
4515 * 0b1..Rx FIFO enabled.
4516 */
4517#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
4518#define CAN_MCR_FRZ_MASK (0x40000000U)
4519#define CAN_MCR_FRZ_SHIFT (30U)
4520/*! FRZ - Freeze Enable
4521 * 0b0..Not enabled to enter Freeze mode.
4522 * 0b1..Enabled to enter Freeze mode.
4523 */
4524#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
4525#define CAN_MCR_MDIS_MASK (0x80000000U)
4526#define CAN_MCR_MDIS_SHIFT (31U)
4527/*! MDIS - Module Disable
4528 * 0b0..Enable the FlexCAN module.
4529 * 0b1..Disable the FlexCAN module.
4530 */
4531#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
4532/*! @} */
4533
4534/*! @name CTRL1 - Control 1 register */
4535/*! @{ */
4536#define CAN_CTRL1_PROPSEG_MASK (0x7U)
4537#define CAN_CTRL1_PROPSEG_SHIFT (0U)
4538/*! PROPSEG - Propagation Segment
4539 */
4540#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
4541#define CAN_CTRL1_LOM_MASK (0x8U)
4542#define CAN_CTRL1_LOM_SHIFT (3U)
4543/*! LOM - Listen-Only Mode
4544 * 0b0..Listen-Only mode is deactivated.
4545 * 0b1..FlexCAN module operates in Listen-Only mode.
4546 */
4547#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
4548#define CAN_CTRL1_LBUF_MASK (0x10U)
4549#define CAN_CTRL1_LBUF_SHIFT (4U)
4550/*! LBUF - Lowest Buffer Transmitted First
4551 * 0b0..Buffer with highest priority is transmitted first.
4552 * 0b1..Lowest number buffer is transmitted first.
4553 */
4554#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
4555#define CAN_CTRL1_TSYN_MASK (0x20U)
4556#define CAN_CTRL1_TSYN_SHIFT (5U)
4557/*! TSYN - Timer Sync
4558 * 0b0..Timer sync feature disabled
4559 * 0b1..Timer sync feature enabled
4560 */
4561#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
4562#define CAN_CTRL1_BOFFREC_MASK (0x40U)
4563#define CAN_CTRL1_BOFFREC_SHIFT (6U)
4564/*! BOFFREC - Bus Off Recovery
4565 * 0b0..Automatic recovering from Bus Off state enabled.
4566 * 0b1..Automatic recovering from Bus Off state disabled.
4567 */
4568#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
4569#define CAN_CTRL1_SMP_MASK (0x80U)
4570#define CAN_CTRL1_SMP_SHIFT (7U)
4571/*! SMP - CAN Bit Sampling
4572 * 0b0..Just one sample is used to determine the bit value.
4573 * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two
4574 * preceding samples; a majority rule is used.
4575 */
4576#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
4577#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
4578#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
4579/*! RWRNMSK - Rx Warning Interrupt Mask
4580 * 0b0..Rx Warning interrupt disabled.
4581 * 0b1..Rx Warning interrupt enabled.
4582 */
4583#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
4584#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
4585#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
4586/*! TWRNMSK - Tx Warning Interrupt Mask
4587 * 0b0..Tx Warning interrupt disabled.
4588 * 0b1..Tx Warning interrupt enabled.
4589 */
4590#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
4591#define CAN_CTRL1_LPB_MASK (0x1000U)
4592#define CAN_CTRL1_LPB_SHIFT (12U)
4593/*! LPB - Loop Back Mode
4594 * 0b0..Loop Back disabled.
4595 * 0b1..Loop Back enabled.
4596 */
4597#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
4598#define CAN_CTRL1_CLKSRC_MASK (0x2000U)
4599#define CAN_CTRL1_CLKSRC_SHIFT (13U)
4600/*! CLKSRC - CAN Engine Clock Source
4601 * 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
4602 * 0b1..The CAN engine clock source is the peripheral clock.
4603 */
4604#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
4605#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
4606#define CAN_CTRL1_ERRMSK_SHIFT (14U)
4607/*! ERRMSK - Error Interrupt Mask
4608 * 0b0..Error interrupt disabled.
4609 * 0b1..Error interrupt enabled.
4610 */
4611#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
4612#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
4613#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
4614/*! BOFFMSK - Bus Off Interrupt Mask
4615 * 0b0..Bus Off interrupt disabled.
4616 * 0b1..Bus Off interrupt enabled.
4617 */
4618#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
4619#define CAN_CTRL1_PSEG2_MASK (0x70000U)
4620#define CAN_CTRL1_PSEG2_SHIFT (16U)
4621/*! PSEG2 - Phase Segment 2
4622 */
4623#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
4624#define CAN_CTRL1_PSEG1_MASK (0x380000U)
4625#define CAN_CTRL1_PSEG1_SHIFT (19U)
4626/*! PSEG1 - Phase Segment 1
4627 */
4628#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
4629#define CAN_CTRL1_RJW_MASK (0xC00000U)
4630#define CAN_CTRL1_RJW_SHIFT (22U)
4631/*! RJW - Resync Jump Width
4632 */
4633#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
4634#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
4635#define CAN_CTRL1_PRESDIV_SHIFT (24U)
4636/*! PRESDIV - Prescaler Division Factor
4637 */
4638#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
4639/*! @} */
4640
4641/*! @name TIMER - Free Running Timer */
4642/*! @{ */
4643#define CAN_TIMER_TIMER_MASK (0xFFFFU)
4644#define CAN_TIMER_TIMER_SHIFT (0U)
4645/*! TIMER - Timer Value
4646 */
4647#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
4648/*! @} */
4649
4650/*! @name RXMGMASK - Rx Mailboxes Global Mask register */
4651/*! @{ */
4652#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
4653#define CAN_RXMGMASK_MG_SHIFT (0U)
4654/*! MG - Rx Mailboxes Global Mask Bits
4655 */
4656#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
4657/*! @} */
4658
4659/*! @name RX14MASK - Rx 14 Mask register */
4660/*! @{ */
4661#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
4662#define CAN_RX14MASK_RX14M_SHIFT (0U)
4663/*! RX14M - Rx Buffer 14 Mask Bits
4664 */
4665#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
4666/*! @} */
4667
4668/*! @name RX15MASK - Rx 15 Mask register */
4669/*! @{ */
4670#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
4671#define CAN_RX15MASK_RX15M_SHIFT (0U)
4672/*! RX15M - Rx Buffer 15 Mask Bits
4673 */
4674#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
4675/*! @} */
4676
4677/*! @name ECR - Error Counter */
4678/*! @{ */
4679#define CAN_ECR_TXERRCNT_MASK (0xFFU)
4680#define CAN_ECR_TXERRCNT_SHIFT (0U)
4681/*! TXERRCNT - Transmit Error Counter
4682 */
4683#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
4684#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
4685#define CAN_ECR_RXERRCNT_SHIFT (8U)
4686/*! RXERRCNT - Receive Error Counter
4687 */
4688#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
4689#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U)
4690#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U)
4691/*! TXERRCNT_FAST - Transmit Error Counter for fast bits
4692 */
4693#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
4694#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U)
4695#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U)
4696/*! RXERRCNT_FAST - Receive Error Counter for fast bits
4697 */
4698#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
4699/*! @} */
4700
4701/*! @name ESR1 - Error and Status 1 register */
4702/*! @{ */
4703#define CAN_ESR1_WAKINT_MASK (0x1U)
4704#define CAN_ESR1_WAKINT_SHIFT (0U)
4705/*! WAKINT - Wake-Up Interrupt
4706 * 0b0..No such occurrence.
4707 * 0b1..Indicates a recessive to dominant transition was received on the CAN bus.
4708 */
4709#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
4710#define CAN_ESR1_ERRINT_MASK (0x2U)
4711#define CAN_ESR1_ERRINT_SHIFT (1U)
4712/*! ERRINT - Error Interrupt
4713 * 0b0..No such occurrence.
4714 * 0b1..Indicates setting of any error bit in the Error and Status register.
4715 */
4716#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
4717#define CAN_ESR1_BOFFINT_MASK (0x4U)
4718#define CAN_ESR1_BOFFINT_SHIFT (2U)
4719/*! BOFFINT - Bus Off Interrupt
4720 * 0b0..No such occurrence.
4721 * 0b1..FlexCAN module entered Bus Off state.
4722 */
4723#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
4724#define CAN_ESR1_RX_MASK (0x8U)
4725#define CAN_ESR1_RX_SHIFT (3U)
4726/*! RX - FlexCAN In Reception
4727 * 0b0..FlexCAN is not receiving a message.
4728 * 0b1..FlexCAN is receiving a message.
4729 */
4730#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
4731#define CAN_ESR1_FLTCONF_MASK (0x30U)
4732#define CAN_ESR1_FLTCONF_SHIFT (4U)
4733/*! FLTCONF - Fault Confinement State
4734 * 0b00..Error Active
4735 * 0b01..Error Passive
4736 * 0b1x..Bus Off
4737 */
4738#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
4739#define CAN_ESR1_TX_MASK (0x40U)
4740#define CAN_ESR1_TX_SHIFT (6U)
4741/*! TX - FlexCAN In Transmission
4742 * 0b0..FlexCAN is not transmitting a message.
4743 * 0b1..FlexCAN is transmitting a message.
4744 */
4745#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
4746#define CAN_ESR1_IDLE_MASK (0x80U)
4747#define CAN_ESR1_IDLE_SHIFT (7U)
4748/*! IDLE - IDLE
4749 * 0b0..No such occurrence.
4750 * 0b1..CAN bus is now IDLE.
4751 */
4752#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
4753#define CAN_ESR1_RXWRN_MASK (0x100U)
4754#define CAN_ESR1_RXWRN_SHIFT (8U)
4755/*! RXWRN - Rx Error Warning
4756 * 0b0..No such occurrence.
4757 * 0b1..RXERRCNT is greater than or equal to 96.
4758 */
4759#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
4760#define CAN_ESR1_TXWRN_MASK (0x200U)
4761#define CAN_ESR1_TXWRN_SHIFT (9U)
4762/*! TXWRN - TX Error Warning
4763 * 0b0..No such occurrence.
4764 * 0b1..TXERRCNT is greater than or equal to 96.
4765 */
4766#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
4767#define CAN_ESR1_STFERR_MASK (0x400U)
4768#define CAN_ESR1_STFERR_SHIFT (10U)
4769/*! STFERR - Stuffing Error
4770 * 0b0..No such occurrence.
4771 * 0b1..A stuffing error occurred since last read of this register.
4772 */
4773#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
4774#define CAN_ESR1_FRMERR_MASK (0x800U)
4775#define CAN_ESR1_FRMERR_SHIFT (11U)
4776/*! FRMERR - Form Error
4777 * 0b0..No such occurrence.
4778 * 0b1..A Form Error occurred since last read of this register.
4779 */
4780#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
4781#define CAN_ESR1_CRCERR_MASK (0x1000U)
4782#define CAN_ESR1_CRCERR_SHIFT (12U)
4783/*! CRCERR - Cyclic Redundancy Check Error
4784 * 0b0..No such occurrence.
4785 * 0b1..A CRC error occurred since last read of this register.
4786 */
4787#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
4788#define CAN_ESR1_ACKERR_MASK (0x2000U)
4789#define CAN_ESR1_ACKERR_SHIFT (13U)
4790/*! ACKERR - Acknowledge Error
4791 * 0b0..No such occurrence.
4792 * 0b1..An ACK error occurred since last read of this register.
4793 */
4794#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
4795#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
4796#define CAN_ESR1_BIT0ERR_SHIFT (14U)
4797/*! BIT0ERR - Bit0 Error
4798 * 0b0..No such occurrence.
4799 * 0b1..At least one bit sent as dominant is received as recessive.
4800 */
4801#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
4802#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
4803#define CAN_ESR1_BIT1ERR_SHIFT (15U)
4804/*! BIT1ERR - Bit1 Error
4805 * 0b0..No such occurrence.
4806 * 0b1..At least one bit sent as recessive is received as dominant.
4807 */
4808#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
4809#define CAN_ESR1_RWRNINT_MASK (0x10000U)
4810#define CAN_ESR1_RWRNINT_SHIFT (16U)
4811/*! RWRNINT - Rx Warning Interrupt Flag
4812 * 0b0..No such occurrence.
4813 * 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.
4814 */
4815#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
4816#define CAN_ESR1_TWRNINT_MASK (0x20000U)
4817#define CAN_ESR1_TWRNINT_SHIFT (17U)
4818/*! TWRNINT - Tx Warning Interrupt Flag
4819 * 0b0..No such occurrence.
4820 * 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.
4821 */
4822#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
4823#define CAN_ESR1_SYNCH_MASK (0x40000U)
4824#define CAN_ESR1_SYNCH_SHIFT (18U)
4825/*! SYNCH - CAN Synchronization Status
4826 * 0b0..FlexCAN is not synchronized to the CAN bus.
4827 * 0b1..FlexCAN is synchronized to the CAN bus.
4828 */
4829#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
4830#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U)
4831#define CAN_ESR1_BOFFDONEINT_SHIFT (19U)
4832/*! BOFFDONEINT - Bus Off Done Interrupt
4833 * 0b0..No such occurrence.
4834 * 0b1..FlexCAN module has completed Bus Off process.
4835 */
4836#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
4837#define CAN_ESR1_ERRINT_FAST_MASK (0x100000U)
4838#define CAN_ESR1_ERRINT_FAST_SHIFT (20U)
4839/*! ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set
4840 * 0b0..No such occurrence.
4841 * 0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set.
4842 */
4843#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
4844#define CAN_ESR1_ERROVR_MASK (0x200000U)
4845#define CAN_ESR1_ERROVR_SHIFT (21U)
4846/*! ERROVR - Error Overrun
4847 * 0b0..Overrun has not occurred.
4848 * 0b1..Overrun has occurred.
4849 */
4850#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
4851#define CAN_ESR1_STFERR_FAST_MASK (0x4000000U)
4852#define CAN_ESR1_STFERR_FAST_SHIFT (26U)
4853/*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
4854 * 0b0..No such occurrence.
4855 * 0b1..A stuffing error occurred since last read of this register.
4856 */
4857#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
4858#define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U)
4859#define CAN_ESR1_FRMERR_FAST_SHIFT (27U)
4860/*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set
4861 * 0b0..No such occurrence.
4862 * 0b1..A form error occurred since last read of this register.
4863 */
4864#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
4865#define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U)
4866#define CAN_ESR1_CRCERR_FAST_SHIFT (28U)
4867/*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
4868 * 0b0..No such occurrence.
4869 * 0b1..A CRC error occurred since last read of this register.
4870 */
4871#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
4872#define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U)
4873#define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U)
4874/*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
4875 * 0b0..No such occurrence.
4876 * 0b1..At least one bit sent as dominant is received as recessive.
4877 */
4878#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
4879#define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U)
4880#define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U)
4881/*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
4882 * 0b0..No such occurrence.
4883 * 0b1..At least one bit sent as recessive is received as dominant.
4884 */
4885#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
4886/*! @} */
4887
4888/*! @name IMASK2 - Interrupt Masks 2 register */
4889/*! @{ */
4890#define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU)
4891#define CAN_IMASK2_BUF63TO32M_SHIFT (0U)
4892/*! BUF63TO32M - Buffer MBi Mask
4893 */
4894#define CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
4895/*! @} */
4896
4897/*! @name IMASK1 - Interrupt Masks 1 register */
4898/*! @{ */
4899#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU)
4900#define CAN_IMASK1_BUF31TO0M_SHIFT (0U)
4901/*! BUF31TO0M - Buffer MBi Mask
4902 */
4903#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
4904/*! @} */
4905
4906/*! @name IFLAG2 - Interrupt Flags 2 register */
4907/*! @{ */
4908#define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU)
4909#define CAN_IFLAG2_BUF63TO32I_SHIFT (0U)
4910/*! BUF63TO32I - Buffer MBi Interrupt
4911 */
4912#define CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
4913/*! @} */
4914
4915/*! @name IFLAG1 - Interrupt Flags 1 register */
4916/*! @{ */
4917#define CAN_IFLAG1_BUF0I_MASK (0x1U)
4918#define CAN_IFLAG1_BUF0I_SHIFT (0U)
4919/*! BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit
4920 * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
4921 * 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
4922 */
4923#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
4924#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
4925#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
4926/*! BUF4TO1I - Buffer MBi Interrupt Or Reserved
4927 */
4928#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
4929#define CAN_IFLAG1_BUF5I_MASK (0x20U)
4930#define CAN_IFLAG1_BUF5I_SHIFT (5U)
4931/*! BUF5I - Buffer MB5 Interrupt Or Frames available in Rx FIFO
4932 * 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
4933 * 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when
4934 * MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.
4935 */
4936#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
4937#define CAN_IFLAG1_BUF6I_MASK (0x40U)
4938#define CAN_IFLAG1_BUF6I_SHIFT (6U)
4939/*! BUF6I - Buffer MB6 Interrupt Or Rx FIFO Warning
4940 * 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
4941 * 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1
4942 */
4943#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
4944#define CAN_IFLAG1_BUF7I_MASK (0x80U)
4945#define CAN_IFLAG1_BUF7I_SHIFT (7U)
4946/*! BUF7I - Buffer MB7 Interrupt Or Rx FIFO Overflow
4947 * 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
4948 * 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1
4949 */
4950#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
4951#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
4952#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
4953/*! BUF31TO8I - Buffer MBi Interrupt
4954 */
4955#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
4956/*! @} */
4957
4958/*! @name CTRL2 - Control 2 register */
4959/*! @{ */
4960#define CAN_CTRL2_EDFLTDIS_MASK (0x800U)
4961#define CAN_CTRL2_EDFLTDIS_SHIFT (11U)
4962/*! EDFLTDIS - Edge Filter Disable
4963 * 0b0..Edge filter is enabled
4964 * 0b1..Edge filter is disabled
4965 */
4966#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
4967#define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U)
4968#define CAN_CTRL2_ISOCANFDEN_SHIFT (12U)
4969/*! ISOCANFDEN - ISO CAN FD Enable
4970 * 0b0..FlexCAN operates using the non-ISO CAN FD protocol.
4971 * 0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1).
4972 */
4973#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
4974#define CAN_CTRL2_PREXCEN_MASK (0x4000U)
4975#define CAN_CTRL2_PREXCEN_SHIFT (14U)
4976/*! PREXCEN - Protocol Exception Enable
4977 * 0b0..Protocol exception is disabled.
4978 * 0b1..Protocol exception is enabled.
4979 */
4980#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
4981#define CAN_CTRL2_EACEN_MASK (0x10000U)
4982#define CAN_CTRL2_EACEN_SHIFT (16U)
4983/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
4984 * 0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
4985 * 0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within
4986 * the incoming frame. Mask bits do apply.
4987 */
4988#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
4989#define CAN_CTRL2_RRS_MASK (0x20000U)
4990#define CAN_CTRL2_RRS_SHIFT (17U)
4991/*! RRS - Remote Request Storing
4992 * 0b0..Remote response frame is generated.
4993 * 0b1..Remote request frame is stored.
4994 */
4995#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
4996#define CAN_CTRL2_MRP_MASK (0x40000U)
4997#define CAN_CTRL2_MRP_SHIFT (18U)
4998/*! MRP - Mailboxes Reception Priority
4999 * 0b0..Matching starts from Rx FIFO and continues on mailboxes.
5000 * 0b1..Matching starts from mailboxes and continues on Rx FIFO.
5001 */
5002#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
5003#define CAN_CTRL2_TASD_MASK (0xF80000U)
5004#define CAN_CTRL2_TASD_SHIFT (19U)
5005/*! TASD - Tx Arbitration Start Delay
5006 */
5007#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
5008#define CAN_CTRL2_RFFN_MASK (0xF000000U)
5009#define CAN_CTRL2_RFFN_SHIFT (24U)
5010/*! RFFN - Number Of Rx FIFO Filters
5011 */
5012#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
5013#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U)
5014#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U)
5015/*! BOFFDONEMSK - Bus Off Done Interrupt Mask
5016 * 0b0..Bus off done interrupt disabled.
5017 * 0b1..Bus off done interrupt enabled.
5018 */
5019#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
5020#define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U)
5021#define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U)
5022/*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames
5023 * 0b0..ERRINT_FAST error interrupt disabled.
5024 * 0b1..ERRINT_FAST error interrupt enabled.
5025 */
5026#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
5027/*! @} */
5028
5029/*! @name ESR2 - Error and Status 2 register */
5030/*! @{ */
5031#define CAN_ESR2_IMB_MASK (0x2000U)
5032#define CAN_ESR2_IMB_SHIFT (13U)
5033/*! IMB - Inactive Mailbox
5034 * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox.
5035 * 0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one.
5036 */
5037#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
5038#define CAN_ESR2_VPS_MASK (0x4000U)
5039#define CAN_ESR2_VPS_SHIFT (14U)
5040/*! VPS - Valid Priority Status
5041 * 0b0..Contents of IMB and LPTM are invalid.
5042 * 0b1..Contents of IMB and LPTM are valid.
5043 */
5044#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
5045#define CAN_ESR2_LPTM_MASK (0x7F0000U)
5046#define CAN_ESR2_LPTM_SHIFT (16U)
5047/*! LPTM - Lowest Priority Tx Mailbox
5048 */
5049#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
5050/*! @} */
5051
5052/*! @name CRCR - CRC register */
5053/*! @{ */
5054#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
5055#define CAN_CRCR_TXCRC_SHIFT (0U)
5056/*! TXCRC - Transmitted CRC value
5057 */
5058#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
5059#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
5060#define CAN_CRCR_MBCRC_SHIFT (16U)
5061/*! MBCRC - CRC Mailbox
5062 */
5063#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
5064/*! @} */
5065
5066/*! @name RXFGMASK - Rx FIFO Global Mask register */
5067/*! @{ */
5068#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
5069#define CAN_RXFGMASK_FGM_SHIFT (0U)
5070/*! FGM - Rx FIFO Global Mask Bits
5071 */
5072#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
5073/*! @} */
5074
5075/*! @name RXFIR - Rx FIFO Information register */
5076/*! @{ */
5077#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
5078#define CAN_RXFIR_IDHIT_SHIFT (0U)
5079/*! IDHIT - Identifier Acceptance Filter Hit Indicator
5080 */
5081#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
5082/*! @} */
5083
5084/*! @name CBT - CAN Bit Timing register */
5085/*! @{ */
5086#define CAN_CBT_EPSEG2_MASK (0x1FU)
5087#define CAN_CBT_EPSEG2_SHIFT (0U)
5088/*! EPSEG2 - Extended Phase Segment 2
5089 */
5090#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
5091#define CAN_CBT_EPSEG1_MASK (0x3E0U)
5092#define CAN_CBT_EPSEG1_SHIFT (5U)
5093/*! EPSEG1 - Extended Phase Segment 1
5094 */
5095#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
5096#define CAN_CBT_EPROPSEG_MASK (0xFC00U)
5097#define CAN_CBT_EPROPSEG_SHIFT (10U)
5098/*! EPROPSEG - Extended Propagation Segment
5099 */
5100#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
5101#define CAN_CBT_ERJW_MASK (0x1F0000U)
5102#define CAN_CBT_ERJW_SHIFT (16U)
5103/*! ERJW - Extended Resync Jump Width
5104 */
5105#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
5106#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U)
5107#define CAN_CBT_EPRESDIV_SHIFT (21U)
5108/*! EPRESDIV - Extended Prescaler Division Factor
5109 */
5110#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
5111#define CAN_CBT_BTF_MASK (0x80000000U)
5112#define CAN_CBT_BTF_SHIFT (31U)
5113/*! BTF - Bit Timing Format Enable
5114 * 0b0..Extended bit time definitions disabled.
5115 * 0b1..Extended bit time definitions enabled.
5116 */
5117#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
5118/*! @} */
5119
5120/*! @name DBG1 - Debug 1 register */
5121/*! @{ */
5122#define CAN_DBG1_CFSM_MASK (0x7FU)
5123#define CAN_DBG1_CFSM_SHIFT (0U)
5124/*! CFSM - CAN Finite State Machine
5125 */
5126#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
5127#define CAN_DBG1_CBN_MASK (0x3FF0000U)
5128#define CAN_DBG1_CBN_SHIFT (16U)
5129/*! CBN - CAN Bit Number
5130 */
5131#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
5132/*! @} */
5133
5134/*! @name DBG2 - Debug 2 register */
5135/*! @{ */
5136#define CAN_DBG2_RMP_MASK (0x7FU)
5137#define CAN_DBG2_RMP_SHIFT (0U)
5138/*! RMP - Rx Matching Pointer
5139 */
5140#define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
5141#define CAN_DBG2_MPP_MASK (0x80U)
5142#define CAN_DBG2_MPP_SHIFT (7U)
5143/*! MPP - Matching Process in Progress
5144 * 0b0..No matching process ongoing
5145 * 0b1..Matching process is in progress.
5146 */
5147#define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
5148#define CAN_DBG2_TAP_MASK (0x7F00U)
5149#define CAN_DBG2_TAP_SHIFT (8U)
5150/*! TAP - Tx Arbitration Pointer
5151 */
5152#define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
5153#define CAN_DBG2_APP_MASK (0x8000U)
5154#define CAN_DBG2_APP_SHIFT (15U)
5155/*! APP - Arbitration Process in Progress
5156 * 0b0..No arbitration process ongoing
5157 * 0b1..Arbitration process is in progress.
5158 */
5159#define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
5160/*! @} */
5161
5162/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */
5163/*! @{ */
5164#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
5165#define CAN_CS_TIME_STAMP_SHIFT (0U)
5166/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
5167 * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
5168 * appears on the CAN bus.
5169 */
5170#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
5171#define CAN_CS_DLC_MASK (0xF0000U)
5172#define CAN_CS_DLC_SHIFT (16U)
5173/*! DLC - Length of the data to be stored/transmitted.
5174 */
5175#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
5176#define CAN_CS_RTR_MASK (0x100000U)
5177#define CAN_CS_RTR_SHIFT (20U)
5178/*! RTR - Remote Transmission Request. One/zero for remote/data frame.
5179 */
5180#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
5181#define CAN_CS_IDE_MASK (0x200000U)
5182#define CAN_CS_IDE_SHIFT (21U)
5183/*! IDE - ID Extended. One/zero for extended/standard format frame.
5184 */
5185#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
5186#define CAN_CS_SRR_MASK (0x400000U)
5187#define CAN_CS_SRR_SHIFT (22U)
5188/*! SRR - Substitute Remote Request. Contains a fixed recessive bit.
5189 */
5190#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
5191#define CAN_CS_CODE_MASK (0xF000000U)
5192#define CAN_CS_CODE_SHIFT (24U)
5193/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
5194 * the FlexCAN module itself, as part of the message buffer matching and arbitration process.
5195 */
5196#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
5197#define CAN_CS_ESI_MASK (0x20000000U)
5198#define CAN_CS_ESI_SHIFT (29U)
5199/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive.
5200 */
5201#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
5202#define CAN_CS_BRS_MASK (0x40000000U)
5203#define CAN_CS_BRS_SHIFT (30U)
5204/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.
5205 */
5206#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
5207#define CAN_CS_EDL_MASK (0x80000000U)
5208#define CAN_CS_EDL_SHIFT (31U)
5209/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
5210 * The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
5211 */
5212#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
5213/*! @} */
5214
5215/* The count of CAN_CS */
5216#define CAN_CS_COUNT (64U)
5217
5218/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */
5219/*! @{ */
5220#define CAN_ID_EXT_MASK (0x3FFFFU)
5221#define CAN_ID_EXT_SHIFT (0U)
5222/*! EXT - Contains extended (LOW word) identifier of message buffer.
5223 */
5224#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
5225#define CAN_ID_STD_MASK (0x1FFC0000U)
5226#define CAN_ID_STD_SHIFT (18U)
5227/*! STD - Contains standard/extended (HIGH word) identifier of message buffer.
5228 */
5229#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
5230#define CAN_ID_PRIO_MASK (0xE0000000U)
5231#define CAN_ID_PRIO_SHIFT (29U)
5232/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
5233 * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
5234 * ID to define the transmission priority.
5235 */
5236#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
5237/*! @} */
5238
5239/* The count of CAN_ID */
5240#define CAN_ID_COUNT (64U)
5241
5242/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
5243/*! @{ */
5244#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
5245#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
5246/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
5247 */
5248#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
5249#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
5250#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
5251/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
5252 */
5253#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
5254#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
5255#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
5256/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
5257 */
5258#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
5259#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
5260#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
5261/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
5262 */
5263#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
5264/*! @} */
5265
5266/* The count of CAN_WORD0 */
5267#define CAN_WORD0_COUNT (64U)
5268
5269/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
5270/*! @{ */
5271#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
5272#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
5273/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
5274 */
5275#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
5276#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
5277#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
5278/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
5279 */
5280#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
5281#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
5282#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
5283/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
5284 */
5285#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
5286#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
5287#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
5288/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
5289 */
5290#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
5291/*! @} */
5292
5293/* The count of CAN_WORD1 */
5294#define CAN_WORD1_COUNT (64U)
5295
5296/*! @name RXIMR - Rx Individual Mask registers */
5297/*! @{ */
5298#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
5299#define CAN_RXIMR_MI_SHIFT (0U)
5300/*! MI - Individual Mask Bits
5301 */
5302#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
5303/*! @} */
5304
5305/* The count of CAN_RXIMR */
5306#define CAN_RXIMR_COUNT (64U)
5307
5308/*! @name FDCTRL - CAN FD Control register */
5309/*! @{ */
5310#define CAN_FDCTRL_TDCVAL_MASK (0x3FU)
5311#define CAN_FDCTRL_TDCVAL_SHIFT (0U)
5312/*! TDCVAL - Transceiver Delay Compensation Value
5313 */
5314#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
5315#define CAN_FDCTRL_TDCOFF_MASK (0x1F00U)
5316#define CAN_FDCTRL_TDCOFF_SHIFT (8U)
5317/*! TDCOFF - Transceiver Delay Compensation Offset
5318 */
5319#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
5320#define CAN_FDCTRL_TDCFAIL_MASK (0x4000U)
5321#define CAN_FDCTRL_TDCFAIL_SHIFT (14U)
5322/*! TDCFAIL - Transceiver Delay Compensation Fail
5323 * 0b0..Measured loop delay is in range.
5324 * 0b1..Measured loop delay is out of range.
5325 */
5326#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
5327#define CAN_FDCTRL_TDCEN_MASK (0x8000U)
5328#define CAN_FDCTRL_TDCEN_SHIFT (15U)
5329/*! TDCEN - Transceiver Delay Compensation Enable
5330 * 0b0..TDC is disabled
5331 * 0b1..TDC is enabled
5332 */
5333#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
5334#define CAN_FDCTRL_MBDSR0_MASK (0x30000U)
5335#define CAN_FDCTRL_MBDSR0_SHIFT (16U)
5336/*! MBDSR0 - Message Buffer Data Size for Region 0
5337 * 0b00..Selects 8 bytes per message buffer.
5338 * 0b01..Selects 16 bytes per message buffer.
5339 * 0b10..Selects 32 bytes per message buffer.
5340 * 0b11..Selects 64 bytes per message buffer.
5341 */
5342#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
5343#define CAN_FDCTRL_MBDSR1_MASK (0x180000U)
5344#define CAN_FDCTRL_MBDSR1_SHIFT (19U)
5345/*! MBDSR1 - Message Buffer Data Size for Region 1
5346 * 0b00..Selects 8 bytes per message buffer.
5347 * 0b01..Selects 16 bytes per message buffer.
5348 * 0b10..Selects 32 bytes per message buffer.
5349 * 0b11..Selects 64 bytes per message buffer.
5350 */
5351#define CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
5352#define CAN_FDCTRL_FDRATE_MASK (0x80000000U)
5353#define CAN_FDCTRL_FDRATE_SHIFT (31U)
5354/*! FDRATE - Bit Rate Switch Enable
5355 * 0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect.
5356 * 0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.
5357 */
5358#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
5359/*! @} */
5360
5361/*! @name FDCBT - CAN FD Bit Timing register */
5362/*! @{ */
5363#define CAN_FDCBT_FPSEG2_MASK (0x7U)
5364#define CAN_FDCBT_FPSEG2_SHIFT (0U)
5365/*! FPSEG2 - Fast Phase Segment 2
5366 */
5367#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
5368#define CAN_FDCBT_FPSEG1_MASK (0xE0U)
5369#define CAN_FDCBT_FPSEG1_SHIFT (5U)
5370/*! FPSEG1 - Fast Phase Segment 1
5371 */
5372#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
5373#define CAN_FDCBT_FPROPSEG_MASK (0x7C00U)
5374#define CAN_FDCBT_FPROPSEG_SHIFT (10U)
5375/*! FPROPSEG - Fast Propagation Segment
5376 */
5377#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
5378#define CAN_FDCBT_FRJW_MASK (0x70000U)
5379#define CAN_FDCBT_FRJW_SHIFT (16U)
5380/*! FRJW - Fast Resync Jump Width
5381 */
5382#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
5383#define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U)
5384#define CAN_FDCBT_FPRESDIV_SHIFT (20U)
5385/*! FPRESDIV - Fast Prescaler Division Factor
5386 */
5387#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
5388/*! @} */
5389
5390/*! @name FDCRC - CAN FD CRC register */
5391/*! @{ */
5392#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU)
5393#define CAN_FDCRC_FD_TXCRC_SHIFT (0U)
5394/*! FD_TXCRC - Extended Transmitted CRC value
5395 */
5396#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
5397#define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U)
5398#define CAN_FDCRC_FD_MBCRC_SHIFT (24U)
5399/*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC
5400 */
5401#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
5402/*! @} */
5403
5404
5405/*!
5406 * @}
5407 */ /* end of group CAN_Register_Masks */
5408
5409
5410/* CAN - Peripheral instance base addresses */
5411/** Peripheral ADMA__CAN0 base address */
5412#define ADMA__CAN0_BASE (0x5A8D0000u)
5413/** Peripheral ADMA__CAN0 base pointer */
5414#define ADMA__CAN0 ((CAN_Type *)ADMA__CAN0_BASE)
5415/** Peripheral ADMA__CAN1 base address */
5416#define ADMA__CAN1_BASE (0x5A8E0000u)
5417/** Peripheral ADMA__CAN1 base pointer */
5418#define ADMA__CAN1 ((CAN_Type *)ADMA__CAN1_BASE)
5419/** Peripheral ADMA__CAN2 base address */
5420#define ADMA__CAN2_BASE (0x5A8F0000u)
5421/** Peripheral ADMA__CAN2 base pointer */
5422#define ADMA__CAN2 ((CAN_Type *)ADMA__CAN2_BASE)
5423/** Array initializer of CAN peripheral base addresses */
5424#define CAN_BASE_ADDRS { ADMA__CAN0_BASE, ADMA__CAN1_BASE, ADMA__CAN2_BASE }
5425/** Array initializer of CAN peripheral base pointers */
5426#define CAN_BASE_PTRS { ADMA__CAN0, ADMA__CAN1, ADMA__CAN2 }
5427/** Interrupt vectors for the CAN peripheral type */
5428#define CAN_Rx_Warning_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5429#define CAN_Tx_Warning_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5430#define CAN_Wake_Up_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5431#define CAN_Error_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5432#define CAN_Bus_Off_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5433#define CAN_ORed_Message_buffer_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5434
5435/*!
5436 * @}
5437 */ /* end of group CAN_Peripheral_Access_Layer */
5438
5439
5440/* ----------------------------------------------------------------------------
5441 -- CI_PI_CSR Peripheral Access Layer
5442 ---------------------------------------------------------------------------- */
5443
5444/*!
5445 * @addtogroup CI_PI_CSR_Peripheral_Access_Layer CI_PI_CSR Peripheral Access Layer
5446 * @{
5447 */
5448
5449/** CI_PI_CSR - Register Layout Typedef */
5450typedef struct {
5451 struct { /* offset: 0x0 */
5452 __IO uint32_t RW; /**< CI_PI Interface Control Register, offset: 0x0 */
5453 __IO uint32_t SET; /**< CI_PI Interface Control Register, offset: 0x4 */
5454 __IO uint32_t CLR; /**< CI_PI Interface Control Register, offset: 0x8 */
5455 __IO uint32_t TOG; /**< CI_PI Interface Control Register, offset: 0xC */
5456 } IF_CTRL_REG;
5457 struct { /* offset: 0x10 */
5458 __IO uint32_t RW; /**< CSI Interface Control Register, offset: 0x10 */
5459 __IO uint32_t SET; /**< CSI Interface Control Register, offset: 0x14 */
5460 __IO uint32_t CLR; /**< CSI Interface Control Register, offset: 0x18 */
5461 __IO uint32_t TOG; /**< CSI Interface Control Register, offset: 0x1C */
5462 } CSI_CTRL_REG;
5463 struct { /* offset: 0x20 */
5464 __I uint32_t RW; /**< CSI Interface Status Register, offset: 0x20 */
5465 __I uint32_t SET; /**< CSI Interface Status Register, offset: 0x24 */
5466 __I uint32_t CLR; /**< CSI Interface Status Register, offset: 0x28 */
5467 __I uint32_t TOG; /**< CSI Interface Status Register, offset: 0x2C */
5468 } CSI_STATUS;
5469 struct { /* offset: 0x30 */
5470 __IO uint32_t RW; /**< CSI Interface Control Register1, offset: 0x30 */
5471 __IO uint32_t SET; /**< CSI Interface Control Register1, offset: 0x34 */
5472 __IO uint32_t CLR; /**< CSI Interface Control Register1, offset: 0x38 */
5473 __IO uint32_t TOG; /**< CSI Interface Control Register1, offset: 0x3C */
5474 } CSI_CTRL_REG1;
5