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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD6/drivers/driver_reset.cmake14
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD6/drivers/fsl_clock.c967
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD6/drivers/fsl_clock.h1349
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD6/drivers/fsl_iomuxc.h606
4 files changed, 2936 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD6/drivers/driver_reset.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD6/drivers/driver_reset.cmake
new file mode 100644
index 000000000..989530f6f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD6/drivers/driver_reset.cmake
@@ -0,0 +1,14 @@
1if(NOT DRIVER_RESET_INCLUDED)
2
3 set(DRIVER_RESET_INCLUDED true CACHE BOOL "driver_reset component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 )
7
8 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
9 ${CMAKE_CURRENT_LIST_DIR}/.
10 )
11
12
13
14endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD6/drivers/fsl_clock.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD6/drivers/fsl_clock.c
new file mode 100644
index 000000000..d7c8b735c
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD6/drivers/fsl_clock.c
@@ -0,0 +1,967 @@
1/*
2 * Copyright 2017 - 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7#include "fsl_common.h"
8#include "fsl_clock.h"
9
10/*******************************************************************************
11 * Definitions
12 ******************************************************************************/
13/* Component ID definition, used by tools. */
14#ifndef FSL_COMPONENT_ID
15#define FSL_COMPONENT_ID "platform.drivers.clock"
16#endif
17/*! @brief SSCG PLL FLITER range value */
18#define SSCG_PLL1_FILTER_RANGE (35000000U)
19/*******************************************************************************
20 * Prototypes
21 ******************************************************************************/
22
23/*******************************************************************************
24 * Variables
25 ******************************************************************************/
26
27/*******************************************************************************
28 * Code
29 ******************************************************************************/
30/*!
31 * brief Gets the clock frequency for a specific clock name.
32 *
33 * This function checks the current clock configurations and then calculates
34 * the clock frequency for a specific clock name defined in clock_name_t.
35 *
36 * param clockName Clock names defined in clock_name_t
37 * return Clock frequency value in hertz
38 */
39uint32_t CLOCK_GetFreq(clock_name_t clockName)
40{
41 uint32_t freq;
42
43 switch (clockName)
44 {
45 case kCLOCK_CoreM4Clk:
46 freq = CLOCK_GetCoreM4Freq();
47 break;
48 case kCLOCK_AxiClk:
49 freq = CLOCK_GetAxiFreq();
50 break;
51 case kCLOCK_AhbClk:
52 freq = CLOCK_GetAhbFreq();
53 break;
54 case kCLOCK_IpgClk:
55 freq = CLOCK_GetAhbFreq();
56 break;
57 default:
58 freq = 0U;
59 break;
60 }
61 return freq;
62}
63
64/*!
65 * brief Get the CCM Cortex M4 core frequency.
66 *
67 * return Clock frequency; If the clock is invalid, returns 0.
68 */
69uint32_t CLOCK_GetCoreM4Freq(void)
70{
71 uint32_t freq;
72 uint32_t pre = CLOCK_GetRootPreDivider(kCLOCK_RootM4);
73 uint32_t post = CLOCK_GetRootPostDivider(kCLOCK_RootM4);
74
75 switch (CLOCK_GetRootMux(kCLOCK_RootM4))
76 {
77 case (uint32_t)kCLOCK_M4RootmuxOsc25m:
78 freq = OSC25M_CLK_FREQ;
79 break;
80 case (uint32_t)kCLOCK_M4RootmuxSysPll2Div5:
81 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 5U;
82 break;
83 case (uint32_t)kCLOCK_M4RootmuxSysPll2Div4:
84 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 4U;
85 break;
86 case (uint32_t)kCLOCK_M4RootmuxSysPll1Div3:
87 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / 3U;
88 break;
89 case (uint32_t)kCLOCK_M4RootmuxSysPll1:
90 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl);
91 break;
92 case (uint32_t)kCLOCK_M4RootmuxAudioPll1:
93 freq = CLOCK_GetPllFreq(kCLOCK_AudioPll1Ctrl);
94 break;
95 case (uint32_t)kCLOCK_M4RootmuxVideoPll1:
96 freq = CLOCK_GetPllFreq(kCLOCK_VideoPll1Ctrl);
97 break;
98 case (uint32_t)kCLOCK_M4RootmuxSysPll3:
99 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll3Ctrl);
100 break;
101 default:
102 freq = 0U;
103 break;
104 }
105
106 return freq / pre / post;
107}
108
109/*!
110 * brief Get the CCM Axi bus frequency.
111 *
112 * return Clock frequency; If the clock is invalid, returns 0.
113 */
114uint32_t CLOCK_GetAxiFreq(void)
115{
116 uint32_t freq;
117 uint32_t pre = CLOCK_GetRootPreDivider(kCLOCK_RootAxi);
118 uint32_t post = CLOCK_GetRootPostDivider(kCLOCK_RootAxi);
119
120 switch (CLOCK_GetRootMux(kCLOCK_RootAxi))
121 {
122 case (uint32_t)kCLOCK_AxiRootmuxOsc25m:
123 freq = OSC25M_CLK_FREQ;
124 break;
125 case (uint32_t)kCLOCK_AxiRootmuxSysPll2Div3:
126 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 3U;
127 break;
128 case (uint32_t)kCLOCK_AxiRootmuxSysPll2Div4:
129 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 4U;
130 break;
131 case (uint32_t)kCLOCK_AxiRootmuxSysPll2:
132 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl);
133 break;
134 case (uint32_t)kCLOCK_AxiRootmuxAudioPll1:
135 freq = CLOCK_GetPllFreq(kCLOCK_AudioPll1Ctrl);
136 break;
137 case (uint32_t)kCLOCK_AxiRootmuxVideoPll1:
138 freq = CLOCK_GetPllFreq(kCLOCK_VideoPll1Ctrl);
139 break;
140 case (uint32_t)kCLOCK_AxiRootmuxSysPll1Div8:
141 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / 8U;
142 break;
143 case (uint32_t)kCLOCK_AxiRootmuxSysPll1:
144 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl);
145 break;
146 default:
147 freq = 0U;
148 break;
149 }
150
151 return freq / pre / post;
152}
153
154/*!
155 * brief Get the CCM Ahb bus frequency.
156 *
157 * return Clock frequency; If the clock is invalid, returns 0.
158 */
159uint32_t CLOCK_GetAhbFreq(void)
160{
161 uint32_t freq;
162 uint32_t pre = CLOCK_GetRootPreDivider(kCLOCK_RootAhb);
163 uint32_t post = CLOCK_GetRootPostDivider(kCLOCK_RootAhb);
164
165 switch (CLOCK_GetRootMux(kCLOCK_RootAhb))
166 {
167 case (uint32_t)kCLOCK_AhbRootmuxOsc25m:
168 freq = OSC25M_CLK_FREQ;
169 break;
170 case (uint32_t)kCLOCK_AhbRootmuxSysPll1Div6:
171 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / 6U;
172 break;
173 case (uint32_t)kCLOCK_AhbRootmuxSysPll1Div2:
174 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / 2U;
175 break;
176 case (uint32_t)kCLOCK_AhbRootmuxSysPll1:
177 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl);
178 break;
179 case (uint32_t)kCLOCK_AhbRootmuxSysPll2Div8:
180 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 8U;
181 break;
182 case (uint32_t)kCLOCK_AhbRootmuxSysPll3:
183 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll3Ctrl);
184 break;
185 case (uint32_t)kCLOCK_AhbRootmuxAudioPll1:
186 freq = CLOCK_GetPllFreq(kCLOCK_AudioPll1Ctrl);
187 break;
188 case (uint32_t)kCLOCK_AhbRootmuxVideoPll1:
189 freq = CLOCK_GetPllFreq(kCLOCK_VideoPll1Ctrl);
190 break;
191 default:
192 freq = 0U;
193 break;
194 }
195
196 return freq / pre / post;
197}
198
199/*!
200 * brief Gets PLL reference clock frequency.
201 *
202 * param type fractional pll type.
203
204 * return Clock frequency
205 */
206uint32_t CLOCK_GetPllRefClkFreq(clock_pll_ctrl_t ctrl)
207{
208 uint32_t refClkFreq = 0U;
209 uint8_t clkSel = 0U;
210
211 if (ctrl <= kCLOCK_ArmPllCtrl)
212 {
213 clkSel = (uint8_t)CCM_BIT_FIELD_EXTRACTION(CCM_ANALOG_TUPLE_REG(CCM_ANALOG, ctrl),
214 CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_MASK,
215 CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT);
216 }
217 else
218 {
219 clkSel = (uint8_t)(CCM_ANALOG_TUPLE_REG(CCM_ANALOG, ctrl) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_MASK);
220 }
221
222 switch (clkSel)
223 {
224 case (uint8_t)kANALOG_PllRefOsc25M:
225 refClkFreq = OSC25M_CLK_FREQ /
226 (CCM_BIT_FIELD_EXTRACTION(XTALOSC->OSC25M_CTL_CFG, XTALOSC_OSC25M_CTL_CFG_OSC_DIV_MASK,
227 XTALOSC_OSC25M_CTL_CFG_OSC_DIV_SHIFT) +
228 1U);
229 break;
230
231 case (uint8_t)kANALOG_PllRefOsc27M:
232 refClkFreq = OSC27M_CLK_FREQ /
233 (CCM_BIT_FIELD_EXTRACTION(XTALOSC->OSC27M_CTL_CFG, XTALOSC_OSC27M_CTL_CFG_OSC_DIV_MASK,
234 XTALOSC_OSC27M_CTL_CFG_OSC_DIV_SHIFT) +
235 1U);
236 break;
237
238 case (uint8_t)kANALOG_PllRefOscHdmiPhy27M:
239 refClkFreq = HDMI_PHY_27M_FREQ;
240 break;
241
242 case (uint8_t)kANALOG_PllRefClkPN:
243 refClkFreq = CLKPN_FREQ;
244 break;
245 default:
246 refClkFreq = 0U;
247 break;
248 }
249
250 return refClkFreq;
251}
252
253/*!
254 * brief Gets PLL clock frequency.
255 *
256 * param type fractional pll type.
257
258 * return Clock frequency
259 */
260uint32_t CLOCK_GetPllFreq(clock_pll_ctrl_t pll)
261{
262 uint32_t pllFreq = 0U;
263 uint32_t pllRefFreq = 0U;
264 bool sscgPll1Bypass = false;
265 bool sscgPll2Bypass = false;
266 bool fracPllBypass = false;
267
268 pllRefFreq = CLOCK_GetPllRefClkFreq(pll);
269
270 switch (pll)
271 {
272 /* SSCG PLL frequency */
273 case kCLOCK_SystemPll1Ctrl:
274 sscgPll1Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll1InternalPll1BypassCtrl);
275 sscgPll2Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll1InternalPll2BypassCtrl);
276 break;
277 case kCLOCK_SystemPll2Ctrl:
278 sscgPll1Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll2InternalPll1BypassCtrl);
279 sscgPll2Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll2InternalPll2BypassCtrl);
280 break;
281 case kCLOCK_SystemPll3Ctrl:
282 sscgPll1Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll3InternalPll1BypassCtrl);
283 sscgPll2Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll3InternalPll2BypassCtrl);
284 break;
285 case kCLOCK_VideoPll2Ctrl:
286 sscgPll1Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_VideoPll2InternalPll1BypassCtrl);
287 sscgPll2Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_VideoPll2InternalPll2BypassCtrl);
288 break;
289 case kCLOCK_DramPllCtrl:
290 sscgPll1Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_DramPllInternalPll1BypassCtrl);
291 sscgPll2Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_DramPllInternalPll2BypassCtrl);
292 break;
293 case kCLOCK_AudioPll1Ctrl:
294 fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_AudioPll1BypassCtrl);
295 break;
296 case kCLOCK_AudioPll2Ctrl:
297 fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_AudioPll2BypassCtrl);
298 break;
299 case kCLOCK_VideoPll1Ctrl:
300 fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_VideoPll1BypassCtrl);
301 break;
302 case kCLOCK_GpuPllCtrl:
303 fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_GpuPLLPwrBypassCtrl);
304 break;
305 case kCLOCK_VpuPllCtrl:
306 fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_VpuPllPwrBypassCtrl);
307 break;
308 case kCLOCK_ArmPllCtrl:
309 fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_ArmPllPwrBypassCtrl);
310 break;
311 default:
312 fracPllBypass = false;
313 break;
314 }
315 if (pll <= kCLOCK_ArmPllCtrl)
316 {
317 if (fracPllBypass)
318 {
319 pllFreq = pllRefFreq;
320 }
321 else
322 {
323 pllFreq = CLOCK_GetFracPllFreq(CCM_ANALOG, pll, pllRefFreq);
324 }
325 }
326 else
327 {
328 if (sscgPll2Bypass)
329 {
330 /* if PLL2 is bypass, return reference clock directly */
331 pllFreq = pllRefFreq;
332 }
333 else
334 {
335 pllFreq = CLOCK_GetSSCGPllFreq(CCM_ANALOG, pll, pllRefFreq, sscgPll1Bypass);
336 }
337 }
338
339 return pllFreq;
340}
341
342/*!
343 * brief Initializes the ANALOG ARM PLL.
344 *
345 * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration).
346 *
347 * note This function can't detect whether the Arm PLL has been enabled and
348 * used by some IPs.
349 */
350void CLOCK_InitArmPll(const ccm_analog_frac_pll_config_t *config)
351{
352 assert(config != NULL);
353
354 /* Disable PLL bypass */
355 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_ArmPllPwrBypassCtrl, false);
356 /* Fractional pll configuration */
357 CLOCK_InitFracPll(CCM_ANALOG, config, kCLOCK_ArmPllCtrl);
358 /* Enable and power up PLL clock. */
359 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_ArmPllClke);
360
361 /* Wait for PLL to be locked. */
362 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_ArmPllCtrl))
363 {
364 }
365}
366
367/*!
368 * brief De-initialize the ARM PLL.
369 */
370void CLOCK_DeinitArmPll(void)
371{
372 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_ArmPllCtrl);
373}
374
375/*!
376 * brief Initializes the ANALOG AUDIO PLL1.
377 *
378 * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration).
379 *
380 * note This function can't detect whether the AUDIO PLL has been enabled and
381 * used by some IPs.
382 */
383void CLOCK_InitAudioPll1(const ccm_analog_frac_pll_config_t *config)
384{
385 assert(config != NULL);
386
387 /* Disable PLL bypass */
388 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_AudioPll1BypassCtrl, false);
389 /* Fractional pll configuration */
390 CLOCK_InitFracPll(CCM_ANALOG, config, kCLOCK_AudioPll1Ctrl);
391 /* Enable and power up PLL clock. */
392 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_AudioPll1Clke);
393
394 /* Wait for PLL to be locked. */
395 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_AudioPll1Ctrl))
396 {
397 }
398}
399
400/*!
401 * brief De-initialize the Audio PLL1.
402 */
403void CLOCK_DeinitAudioPll1(void)
404{
405 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_AudioPll1Ctrl);
406}
407
408/*!
409 * brief Initializes the ANALOG AUDIO PLL2.
410 *
411 * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration).
412 *
413 * note This function can't detect whether the AUDIO PLL has been enabled and
414 * used by some IPs.
415 */
416void CLOCK_InitAudioPll2(const ccm_analog_frac_pll_config_t *config)
417{
418 assert(config != NULL);
419
420 /* Disable PLL bypass */
421 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_AudioPll2BypassCtrl, false);
422 /* Fractional pll configuration */
423 CLOCK_InitFracPll(CCM_ANALOG, config, kCLOCK_AudioPll2Ctrl);
424 /* Enable and power up PLL clock. */
425 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_AudioPll2Clke);
426
427 /* Wait for PLL to be locked. */
428 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_AudioPll2Ctrl))
429 {
430 }
431}
432
433/*!
434 * brief De-initialize the Audio PLL2.
435 */
436void CLOCK_DeinitAudioPll2(void)
437{
438 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_AudioPll2Ctrl);
439}
440
441/*!
442 * brief Initializes the ANALOG VIDEO PLL1.
443 *
444 * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration).
445 *
446 */
447void CLOCK_InitVideoPll1(const ccm_analog_frac_pll_config_t *config)
448{
449 assert(config != NULL);
450
451 /* Disable PLL bypass */
452 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_VideoPll1BypassCtrl, false);
453 /* Fractional pll configuration */
454 CLOCK_InitFracPll(CCM_ANALOG, config, kCLOCK_VideoPll1Ctrl);
455 /* Enable and power up PLL clock. */
456 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_VideoPll1Clke);
457
458 /* Wait for PLL to be locked. */
459 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_VideoPll1Ctrl))
460 {
461 }
462}
463
464/*!
465 * brief De-initialize the Video PLL1.
466 */
467void CLOCK_DeinitVideoPll1(void)
468{
469 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_VideoPll1Ctrl);
470}
471
472/*!
473 * brief Initializes the ANALOG SYS PLL1.
474 *
475 * param config Pointer to the configuration structure(see ref ccm_analog_sscg_pll_config_t enumeration).
476 *
477 * note This function can't detect whether the SYS PLL has been enabled and
478 * used by some IPs.
479 */
480void CLOCK_InitSysPll1(const ccm_analog_sscg_pll_config_t *config)
481{
482 assert(config != NULL);
483
484 /* SSCG PLL configuration */
485 CLOCK_InitSSCGPll(CCM_ANALOG, config, kCLOCK_SystemPll1Ctrl);
486 /* Disable PLL bypass */
487 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll1InternalPll1BypassCtrl, false);
488 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll1InternalPll2BypassCtrl, false);
489 /* Enable and power up PLL clock. */
490 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_SystemPll1Clke);
491
492 /* Wait for PLL to be locked. */
493 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_SystemPll1Ctrl))
494 {
495 }
496}
497
498/*!
499 * brief De-initialize the System PLL1.
500 */
501void CLOCK_DeinitSysPll1(void)
502{
503 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_SystemPll1Ctrl);
504}
505
506/*!
507 * brief Initializes the ANALOG SYS PLL2.
508 *
509 * param config Pointer to the configuration structure(see ref ccm_analog_sscg_pll_config_t enumeration).
510 *
511 * note This function can't detect whether the SYS PLL has been enabled and
512 * used by some IPs.
513 */
514void CLOCK_InitSysPll2(const ccm_analog_sscg_pll_config_t *config)
515{
516 assert(config != NULL);
517
518 /* SSCG PLL configuration */
519 CLOCK_InitSSCGPll(CCM_ANALOG, config, kCLOCK_SystemPll2Ctrl);
520 /* Disable PLL bypass */
521 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll2InternalPll1BypassCtrl, false);
522 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll2InternalPll2BypassCtrl, false);
523 /* Enable and power up PLL clock. */
524 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_SystemPll2Clke);
525
526 /* Wait for PLL to be locked. */
527 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_SystemPll2Ctrl))
528 {
529 }
530}
531
532/*!
533 * brief De-initialize the System PLL2.
534 */
535void CLOCK_DeinitSysPll2(void)
536{
537 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_SystemPll2Ctrl);
538}
539
540/*!
541 * brief Initializes the ANALOG SYS PLL3.
542 *
543 * param config Pointer to the configuration structure(see ref ccm_analog_sscg_pll_config_t enumeration).
544 *
545 * note This function can't detect whether the SYS PLL has been enabled and
546 * used by some IPs.
547 */
548void CLOCK_InitSysPll3(const ccm_analog_sscg_pll_config_t *config)
549{
550 assert(config != NULL);
551
552 /* SSCG PLL configuration */
553 CLOCK_InitSSCGPll(CCM_ANALOG, config, kCLOCK_SystemPll3Ctrl);
554 /* Disable PLL bypass */
555 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll3InternalPll1BypassCtrl, false);
556 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll3InternalPll2BypassCtrl, false);
557 /* Enable and power up PLL clock. */
558 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_SystemPll3Clke);
559
560 /* Wait for PLL to be locked. */
561 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_SystemPll3Ctrl))
562 {
563 }
564}
565
566/*!
567 * brief De-initialize the System PLL3.
568 */
569void CLOCK_DeinitSysPll3(void)
570{
571 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_SystemPll3Ctrl);
572}
573
574/*!
575 * brief Initializes the ANALOG DDR PLL.
576 *
577 * param config Pointer to the configuration structure(see ref ccm_analog_sscg_pll_config_t enumeration).
578 *
579 * note This function can't detect whether the DDR PLL has been enabled and
580 * used by some IPs.
581 */
582void CLOCK_InitDramPll(const ccm_analog_sscg_pll_config_t *config)
583{
584 assert(config != NULL);
585
586 /* init SSCG pll */
587 CLOCK_InitSSCGPll(CCM_ANALOG, config, kCLOCK_DramPllCtrl);
588 /* Disable PLL bypass */
589 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_DramPllInternalPll1BypassCtrl, false);
590 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_DramPllInternalPll2BypassCtrl, false);
591 /* Enable and power up PLL clock. */
592 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_DramPllClke);
593
594 /* make sure DDR is release from reset, DDR1 should be assigned to special domain first */
595 /* trigger the DDR1 power up */
596 GPC->PU_PGC_SW_PUP_REQ |= GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_MASK;
597 /* release DDR1 from reset status */
598 SRC->DDRC2_RCR = (SRC->DDRC2_RCR & (~(SRC_DDRC2_RCR_DDRC1_PHY_PWROKIN_MASK | SRC_DDRC2_RCR_DDRC1_PHY_RESET_MASK |
599 SRC_DDRC2_RCR_DDRC2_CORE_RST_MASK | SRC_DDRC2_RCR_DDRC2_PRST_MASK))) |
600 SRC_DDRC2_RCR_DOM_EN_MASK | SRC_DDRC2_RCR_DOMAIN3_MASK | SRC_DDRC2_RCR_DOMAIN2_MASK |
601 SRC_DDRC2_RCR_DOMAIN1_MASK | SRC_DDRC2_RCR_DOMAIN0_MASK;
602
603 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_DramPllCtrl))
604 {
605 }
606}
607
608/*!
609 * brief De-initialize the Dram PLL.
610 */
611void CLOCK_DeinitDramPll(void)
612{
613 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_DramPllCtrl);
614}
615
616/*!
617 * brief Initializes the ANALOG VIDEO PLL2.
618 *
619 * param config Pointer to the configuration structure(see ref ccm_analog_sscg_pll_config_t enumeration).
620 *
621 * note This function can't detect whether the VIDEO PLL has been enabled and
622 * used by some IPs.
623 */
624void CLOCK_InitVideoPll2(const ccm_analog_sscg_pll_config_t *config)
625{
626 assert(config != NULL);
627
628 /* init SSCG pll */
629 CLOCK_InitSSCGPll(CCM_ANALOG, config, kCLOCK_VideoPll2Ctrl);
630
631 /* Disable PLL bypass */
632 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_VideoPll2InternalPll1BypassCtrl, false);
633 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_VideoPll2InternalPll2BypassCtrl, false);
634 /* Enable and power up PLL clock. */
635 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_VideoPll2Clke);
636
637 /* Wait for PLL to be locked. */
638 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_VideoPll2Ctrl))
639 {
640 }
641}
642
643/*!
644 * brief De-initialize the Video PLL2.
645 */
646void CLOCK_DeinitVideoPll2(void)
647{
648 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_VideoPll2Ctrl);
649}
650
651/*!
652 * brief Initializes the ANALOG Fractional PLL.
653 *
654 * param base CCM ANALOG base address.
655 * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration).
656 * param type fractional pll type.
657 *
658 */
659void CLOCK_InitFracPll(CCM_ANALOG_Type *base, const ccm_analog_frac_pll_config_t *config, clock_pll_ctrl_t type)
660{
661 assert(config != NULL);
662 assert((config->refDiv != 0U) && (config->outDiv != 0U));
663 assert((config->outDiv % 2U) == 0U);
664 assert(type <= kCLOCK_ArmPllCtrl);
665
666 uint32_t fracCfg0 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) | CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_MASK;
667 uint32_t fracCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 4U);
668
669 /* power down the fractional PLL first */
670 CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) = fracCfg0;
671
672 CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) =
673 (fracCfg0 &
674 (~(CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK | CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK |
675 CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_MASK | CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL_MASK))) |
676 (CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL((uint32_t)(config->outDiv) / 2U - 1U)) |
677 (CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL((uint32_t)(config->refDiv) - 1U)) |
678 CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL(config->refSel);
679
680 CCM_ANALOG_TUPLE_REG_OFF(base, type, 4U) =
681 (fracCfg1 &
682 (~(CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK | CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK))) |
683 CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL(config->intDiv) |
684 CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL(config->fractionDiv);
685
686 /* NEW_DIV_VAL */
687 CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) |= CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL_MASK;
688
689 /* power up the fractional pll */
690 CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) &= ~CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_MASK;
691
692 /* need to check NEW_DIV_ACK */
693 while ((CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_ACK_MASK) == 0U)
694 {
695 }
696}
697
698/*!
699 * brief Gets the ANALOG Fractional PLL clock frequency.
700 *
701 * param base CCM_ANALOG base pointer.
702 * param type fractional pll type.
703 * param fractional pll reference clock frequency
704 *
705 * return Clock frequency
706 */
707uint32_t CLOCK_GetFracPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq)
708{
709 assert(type <= kCLOCK_ArmPllCtrl);
710
711 uint32_t fracCfg0 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U);
712 uint32_t fracCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 4U);
713 uint64_t fracClk = 0U;
714
715 uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK,
716 CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_SHIFT);
717 uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK,
718 CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT);
719 uint32_t fracDiv = CCM_BIT_FIELD_EXTRACTION(fracCfg1, CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK,
720 CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_SHIFT);
721 uint8_t intDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg1, CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK,
722 CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_SHIFT);
723
724 refClkFreq /= (uint32_t)refDiv + 1UL;
725 fracClk = (uint64_t)refClkFreq * 8U * (1U + intDiv) + (((uint64_t)refClkFreq * 8U * fracDiv) >> 24U);
726
727 return (uint32_t)(fracClk / (((uint64_t)outDiv + 1U) * 2U));
728}
729
730/*!
731 * brief Initializes the ANALOG SSCG PLL.
732 *
733 * param base CCM ANALOG base address
734 * param config Pointer to the configuration structure(see ref ccm_analog_sscg_pll_config_t enumeration).
735 * param type sscg pll type
736 *
737 */
738void CLOCK_InitSSCGPll(CCM_ANALOG_Type *base, const ccm_analog_sscg_pll_config_t *config, clock_pll_ctrl_t type)
739{
740 assert(config != NULL);
741 assert(config->refDiv1 != 0U);
742 assert(config->refDiv2 != 0U);
743 assert(config->outDiv != 0U);
744 assert(config->loopDivider1 != 0U);
745 assert(config->loopDivider2 != 0U);
746 assert(type >= kCLOCK_SystemPll1Ctrl);
747
748 uint32_t sscgCfg0 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) | CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_MASK;
749 uint32_t sscgCfg2 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 8U);
750 uint32_t pll1Filter = 0U;
751
752 /* power down the SSCG PLL first */
753 CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) = sscgCfg0;
754
755 /* pll mux configuration */
756 CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) =
757 (sscgCfg0 & (~CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_MASK)) | config->refSel;
758
759 /* reserve CFG1, spread spectrum */
760
761 /* match the PLL1 input clock range with PLL filter range */
762 if ((CLOCK_GetPllRefClkFreq(type) / (config->refDiv1)) > SSCG_PLL1_FILTER_RANGE)
763 {
764 pll1Filter = 1U;
765 }
766 /* divider configuration */
767 CCM_ANALOG_TUPLE_REG_OFF(base, type, 8U) =
768 (sscgCfg2 &
769 (~(CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_MASK | CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_MASK |
770 CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_MASK | CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK |
771 CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_MASK))) |
772 CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL((uint32_t)(config->outDiv) - 1U) |
773 CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2(config->loopDivider2 - 1U) |
774 CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1(config->loopDivider1 - 1U) |
775 CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2((uint32_t)(config->refDiv2) - 1U) |
776 CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1((uint32_t)(config->refDiv1) - 1U) | pll1Filter;
777
778 /* power up the SSCG PLL */
779 CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) &= ~CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_MASK;
780}
781
782/*!
783 * brief Get the ANALOG SSCG PLL clock frequency.
784 *
785 * param base CCM ANALOG base address.
786 * param type sscg pll type
787 * param pll1Bypass pll1 bypass flag
788 *
789 * return Clock frequency
790 */
791uint32_t CLOCK_GetSSCGPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq, bool pll1Bypass)
792{
793 assert(type >= kCLOCK_SystemPll1Ctrl);
794
795 uint32_t sscgCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 4U);
796 uint32_t sscgCfg2 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 8U);
797 uint64_t pll2InputClock = 0U;
798
799 uint8_t refDiv1 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_MASK,
800 CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_SHIFT) +
801 1U;
802 uint8_t refDiv2 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK,
803 CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_SHIFT) +
804 1U;
805 uint8_t divf1 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_MASK,
806 CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_SHIFT) +
807 1U;
808 uint8_t divf2 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_MASK,
809 CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_SHIFT) +
810 1U;
811 uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_MASK,
812 CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT) +
813 1U;
814
815 refClkFreq /= refDiv1;
816
817 if (pll1Bypass)
818 {
819 pll2InputClock = refClkFreq;
820 }
821 else if ((sscgCfg1 & CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE_MASK) != 0U)
822 {
823 pll2InputClock = (uint64_t)refClkFreq * 8U * divf1 / refDiv2;
824 }
825 else
826 {
827 pll2InputClock = (uint64_t)refClkFreq * 2U * divf1 / refDiv2;
828 }
829
830 return (uint32_t)(pll2InputClock * divf2 / outDiv);
831}
832
833/*!
834 * brief Set root clock divider
835 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
836 *
837 * param ccmRootClk Root control (see ref clock_root_control_t enumeration)
838 * param pre Pre divider value (1-8)
839 * param post Post divider value (1-64)
840 */
841void CLOCK_SetRootDivider(clock_root_control_t ccmRootClk, uint32_t pre, uint32_t post)
842{
843 assert((pre <= 8U) && (pre != 0U));
844 assert((post <= 64U) && (post != 0U));
845
846 CCM_REG(ccmRootClk) = (CCM_REG(ccmRootClk) & (~(CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_POST_PODF_MASK))) |
847 CCM_TARGET_ROOT_PRE_PODF(pre - 1U) | CCM_TARGET_ROOT_POST_PODF(post - 1U);
848}
849
850/*!
851 * brief Update clock root in one step, for dynamical clock switching
852 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
853 *
854 * param ccmRootClk Root control (see ref clock_root_control_t enumeration)
855 * param root mux value (see ref _ccm_rootmux_xxx enumeration)
856 * param pre Pre divider value (0-7, divider=n+1)
857 * param post Post divider value (0-63, divider=n+1)
858 */
859void CLOCK_UpdateRoot(clock_root_control_t ccmRootClk, uint32_t mux, uint32_t pre, uint32_t post)
860{
861 assert((pre <= 8U) && (pre != 0U));
862 assert((post <= 64U) && (post != 0U));
863
864 CCM_REG(ccmRootClk) =
865 (CCM_REG(ccmRootClk) &
866 (~(CCM_TARGET_ROOT_MUX_MASK | CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_POST_PODF_MASK))) |
867 CCM_TARGET_ROOT_MUX(mux) | CCM_TARGET_ROOT_PRE_PODF(pre - 1U) | CCM_TARGET_ROOT_POST_PODF(post - 1U);
868}
869
870/*!
871 * brief OSC25M init
872 *
873 * param config osc configuration
874 */
875void CLOCK_InitOSC25M(const osc_config_t *config)
876{
877 assert(config != NULL);
878 assert(config->oscDiv != 0U);
879
880 XTALOSC->OSC25M_CTL_CFG =
881 (XTALOSC->OSC25M_CTL_CFG & (~(XTALOSC_OSC25M_CTL_CFG_OSC_DIV_MASK | XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS_MASK))) |
882 XTALOSC_OSC25M_CTL_CFG_OSC_DIV((uint32_t)(config->oscDiv) - 1U) |
883 XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS(config->oscMode);
884
885 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_OSC25MClke);
886}
887
888/*!
889 * brief OSC25M deinit
890 *
891 */
892void CLOCK_DeinitOSC25M(void)
893{
894 CLOCK_DisableAnalogClock(CCM_ANALOG, kCLOCK_OSC25MClke);
895}
896
897/*!
898 * brief OSC27M init
899 *
900 */
901void CLOCK_InitOSC27M(const osc_config_t *config)
902{
903 assert(config != NULL);
904 assert(config->oscDiv != 0U);
905
906 XTALOSC->OSC27M_CTL_CFG =
907 (XTALOSC->OSC27M_CTL_CFG & (~(XTALOSC_OSC27M_CTL_CFG_OSC_DIV_MASK | XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS_MASK))) |
908 XTALOSC_OSC27M_CTL_CFG_OSC_DIV((uint32_t)(config->oscDiv) - 1U) |
909 XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS(config->oscMode);
910
911 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_OSC27MClke);
912}
913
914/*!
915 * brief OSC27M deinit
916 *
917 * param config osc configuration
918 */
919void CLOCK_DeinitOSC27M(void)
920{
921 CLOCK_DisableAnalogClock(CCM_ANALOG, kCLOCK_OSC27MClke);
922}
923
924/*!
925 * brief Enable CCGR clock gate and root clock gate for each module
926 * User should set specific gate for each module according to the description
927 * of the table of system clocks, gating and override in CCM chapter of
928 * reference manual. Take care of that one module may need to set more than
929 * one clock gate.
930 *
931 * param ccmGate Gate control for each module (see ref clock_ip_name_t enumeration).
932 */
933void CLOCK_EnableClock(clock_ip_name_t ccmGate)
934{
935 uint32_t ccgr = CCM_TUPLE_CCGR(ccmGate);
936 uint32_t rootClk = CCM_TUPLE_ROOT(ccmGate);
937
938 CCM_REG_SET(ccgr) = (uint32_t)kCLOCK_ClockNeededAll;
939 /* if root clock is 0xFFFFU, then skip enable root clock */
940 if (rootClk != 0xFFFFU)
941 {
942 CCM_REG_SET(rootClk) = CCM_TARGET_ROOT_SET_ENABLE_MASK;
943 }
944}
945
946/*!
947 * brief Disable CCGR clock gate for the each module
948 * User should set specific gate for each module according to the description
949 * of the table of system clocks, gating and override in CCM chapter of
950 * reference manual. Take care of that one module may need to set more than
951 * one clock gate.
952 *
953 * param ccmGate Gate control for each module (see ref clock_ip_name_t enumeration).
954 */
955void CLOCK_DisableClock(clock_ip_name_t ccmGate)
956{
957 uint32_t ccgr = CCM_TUPLE_CCGR(ccmGate);
958 uint32_t rootClk = CCM_TUPLE_ROOT(ccmGate);
959
960 CCM_REG(ccgr) = (uint32_t)kCLOCK_ClockNotNeeded;
961
962 /* if root clock is 0xFFFFU, then skip disable root clock */
963 if (rootClk != 0xFFFFU)
964 {
965 CCM_REG_CLR(rootClk) = CCM_TARGET_ROOT_CLR_ENABLE_MASK;
966 }
967}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD6/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD6/drivers/fsl_clock.h
new file mode 100644
index 000000000..4deb75ae3
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD6/drivers/fsl_clock.h
@@ -0,0 +1,1349 @@
1/*
2 * Copyright 2017 - 2020, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_device_registers.h"
12#include <stdint.h>
13#include <stdbool.h>
14#include <stddef.h>
15#include <assert.h>
16
17/*!
18 * @addtogroup clock
19 * @{
20 */
21
22/*******************************************************************************
23 * Definitions
24 ******************************************************************************/
25
26/*! @name Driver version */
27/*@{*/
28/*! @brief CLOCK driver version 2.3.2. */
29#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
30/*@}*/
31
32/* Definition for delay API in clock driver, users can redefine it to the real application. */
33#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
34#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (400000000UL)
35#endif
36
37/*!
38 * @brief XTAL 25M clock frequency.
39 */
40#define OSC25M_CLK_FREQ 25000000U
41
42/*!
43 * @brief XTAL 27M clock frequency.
44 */
45#define OSC27M_CLK_FREQ 27000000U
46
47/*!
48 * @brief HDMI PHY 27M clock frequency.
49 */
50#define HDMI_PHY_27M_FREQ 27000000U
51
52/*!
53 * @brief clock1PN frequency.
54 */
55#define CLKPN_FREQ 0U
56
57/*! @brief Clock ip name array for ECSPI. */
58#define ECSPI_CLOCKS \
59 { \
60 kCLOCK_IpInvalid, kCLOCK_Ecspi1, kCLOCK_Ecspi2, kCLOCK_Ecspi3, \
61 }
62
63/*! @brief Clock ip name array for GPIO. */
64#define GPIO_CLOCKS \
65 { \
66 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5, \
67 }
68
69/*! @brief Clock ip name array for GPT. */
70#define GPT_CLOCKS \
71 { \
72 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6, \
73 }
74
75/*! @brief Clock ip name array for I2C. */
76#define I2C_CLOCKS \
77 { \
78 kCLOCK_IpInvalid, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, kCLOCK_I2c4, \
79 }
80
81/*! @brief Clock ip name array for IOMUX. */
82#define IOMUX_CLOCKS \
83 { \
84 kCLOCK_Iomux, \
85 }
86
87/*! @brief Clock ip name array for IPMUX. */
88#define IPMUX_CLOCKS \
89 { \
90 kCLOCK_Ipmux1, kCLOCK_Ipmux2, kCLOCK_Ipmux3, kCLOCK_Ipmux4, \
91 }
92
93/*! @brief Clock ip name array for PWM. */
94#define PWM_CLOCKS \
95 { \
96 kCLOCK_IpInvalid, kCLOCK_Pwm1, kCLOCK_Pwm2, kCLOCK_Pwm3, kCLOCK_Pwm4, \
97 }
98
99/*! @brief Clock ip name array for RDC. */
100#define RDC_CLOCKS \
101 { \
102 kCLOCK_Rdc, \
103 }
104
105/*! @brief Clock ip name array for SAI. */
106#define SAI_CLOCKS \
107 { \
108 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_Sai4, kCLOCK_Sai5, kCLOCK_Sai6, \
109 }
110
111/*! @brief Clock ip name array for RDC SEMA42. */
112#define RDC_SEMA42_CLOCKS \
113 { \
114 kCLOCK_IpInvalid, kCLOCK_Sema42_1, kCLOCK_Sema42_2 \
115 }
116
117/*! @brief Clock ip name array for UART. */
118#define UART_CLOCKS \
119 { \
120 kCLOCK_IpInvalid, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, \
121 }
122
123/*! @brief Clock ip name array for USDHC. */
124#define USDHC_CLOCKS \
125 { \
126 kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
127 }
128
129/*! @brief Clock ip name array for WDOG. */
130#define WDOG_CLOCKS \
131 { \
132 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3 \
133 }
134
135/*! @brief Clock ip name array for TEMPSENSOR. */
136#define TMU_CLOCKS \
137 { \
138 kCLOCK_TempSensor, \
139 }
140
141/*! @brief Clock ip name array for SDMA. */
142#define SDMA_CLOCKS \
143 { \
144 kCLOCK_Sdma1, kCLOCK_Sdma2 \
145 }
146
147/*! @brief Clock ip name array for MU. */
148#define MU_CLOCKS \
149 { \
150 kCLOCK_Mu \
151 }
152
153/*! @brief Clock ip name array for QSPI. */
154#define QSPI_CLOCKS \
155 { \
156 kCLOCK_Qspi \
157 }
158
159/*!
160 * @brief CCM reg macros to extract corresponding registers bit field.
161 */
162#define CCM_BIT_FIELD_EXTRACTION(val, mask, shift) (((val) & (mask)) >> (shift))
163
164/*!
165 * @brief CCM reg macros to map corresponding registers.
166 */
167#define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uint32_t)(root) + (off))))
168#define CCM_REG(root) CCM_REG_OFF(root, 0U)
169#define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
170#define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
171
172/*!
173 * @brief CCM Analog registers offset.
174 */
175#define AUDIO_PLL1_CFG0_OFFSET 0x00
176#define AUDIO_PLL2_CFG0_OFFSET 0x08
177#define VIDEO_PLL1_CFG0_OFFSET 0x10
178#define GPU_PLL_CFG0_OFFSET 0x18
179#define VPU_PLL_CFG0_OFFSET 0x20
180#define ARM_PLL_CFG0_OFFSET 0x28
181#define SYS_PLL1_CFG0_OFFSET 0x30
182#define SYS_PLL2_CFG0_OFFSET 0x3C
183#define SYS_PLL3_CFG0_OFFSET 0x48
184#define VIDEO_PLL2_CFG0_OFFSET 0x54
185#define DRAM_PLL_CFG0_OFFSET 0x60
186#define OSC_MISC_CFG_OFFSET 0x70
187
188/*!
189 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
190 */
191#define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFFU) << 16U) | (shift))
192#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)(tuple)) & 0x1FU)
193#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
194 (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFFU) + (off))))
195#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
196
197/*!
198 * @brief CCM CCGR and root tuple
199 */
200#define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root))
201#define CCM_TUPLE_CCGR(tuple) ((uint32_t)(&(CCM)->CCGR[(uint32_t)(tuple) >> 16U].CCGR))
202#define CCM_TUPLE_ROOT(tuple) ((uint32_t)(&(CCM)->ROOT[(uint32_t)(tuple)&0xFFFFU].TARGET_ROOT))
203
204/*! @brief Clock name used to get clock frequency. */
205typedef enum _clock_name
206{
207 kCLOCK_CoreM4Clk, /*!< ARM M4 Core clock */
208
209 kCLOCK_AxiClk, /*!< Main AXI bus clock. */
210 kCLOCK_AhbClk, /*!< AHB bus clock. */
211 kCLOCK_IpgClk, /*!< IPG bus clock. */
212
213 /* -------------------------------- Other clock --------------------------*/
214} clock_name_t;
215
216#define kCLOCK_CoreSysClk kCLOCK_CoreM4Clk /*!< For compatible with other platforms without CCM. */
217#define CLOCK_GetCoreSysClkFreq CLOCK_GetCoreM4Freq /*!< For compatible with other platforms without CCM. */
218
219/*! @brief CCM CCGR gate control. */
220typedef enum _clock_ip_name
221{
222 kCLOCK_IpInvalid = -1,
223
224 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
225
226 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
227
228 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
229 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
230 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
231
232 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
233 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
234 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
235 kCLOCK_Gpio4 = CCM_TUPLE(14U, 33U), /*!< GPIO4 Clock Gate.*/
236 kCLOCK_Gpio5 = CCM_TUPLE(15U, 33U), /*!< GPIO5 Clock Gate.*/
237
238 kCLOCK_Gpt1 = CCM_TUPLE(16U, 107U), /*!< GPT1 Clock Gate.*/
239 kCLOCK_Gpt2 = CCM_TUPLE(17U, 108U), /*!< GPT2 Clock Gate.*/
240 kCLOCK_Gpt3 = CCM_TUPLE(18U, 109U), /*!< GPT3 Clock Gate.*/
241 kCLOCK_Gpt4 = CCM_TUPLE(19U, 110U), /*!< GPT4 Clock Gate.*/
242 kCLOCK_Gpt5 = CCM_TUPLE(20U, 111U), /*!< GPT5 Clock Gate.*/
243 kCLOCK_Gpt6 = CCM_TUPLE(21U, 112U), /*!< GPT6 Clock Gate.*/
244
245 kCLOCK_I2c1 = CCM_TUPLE(23U, 90U), /*!< I2C1 Clock Gate.*/
246 kCLOCK_I2c2 = CCM_TUPLE(24U, 91U), /*!< I2C2 Clock Gate.*/
247 kCLOCK_I2c3 = CCM_TUPLE(25U, 92U), /*!< I2C3 Clock Gate.*/
248 kCLOCK_I2c4 = CCM_TUPLE(26U, 93U), /*!< I2C4 Clock Gate.*/
249
250 kCLOCK_Iomux = CCM_TUPLE(27U, 33U), /*!< IOMUX Clock Gate.*/
251 kCLOCK_Ipmux1 = CCM_TUPLE(28U, 33U), /*!< IPMUX1 Clock Gate.*/
252 kCLOCK_Ipmux2 = CCM_TUPLE(29U, 33U), /*!< IPMUX2 Clock Gate.*/
253 kCLOCK_Ipmux3 = CCM_TUPLE(30U, 33U), /*!< IPMUX3 Clock Gate.*/
254 kCLOCK_Ipmux4 = CCM_TUPLE(31U, 33U), /*!< IPMUX4 Clock Gate.*/
255
256 kCLOCK_M4 = CCM_TUPLE(32U, 1U), /*!< M4 Clock Gate.*/
257
258 kCLOCK_Mu = CCM_TUPLE(33U, 33U), /*!< MU Clock Gate.*/
259
260 kCLOCK_Ocram = CCM_TUPLE(35U, 16U), /*!< OCRAM Clock Gate.*/
261 kCLOCK_OcramS = CCM_TUPLE(36U, 32U), /*!< OCRAM S Clock Gate.*/
262
263 kCLOCK_Pwm1 = CCM_TUPLE(40U, 103U), /*!< PWM1 Clock Gate.*/
264 kCLOCK_Pwm2 = CCM_TUPLE(41U, 104U), /*!< PWM2 Clock Gate.*/
265 kCLOCK_Pwm3 = CCM_TUPLE(42U, 105U), /*!< PWM3 Clock Gate.*/
266 kCLOCK_Pwm4 = CCM_TUPLE(43U, 106U), /*!< PWM4 Clock Gate.*/
267
268 kCLOCK_Qspi = CCM_TUPLE(47U, 87U), /*!< QSPI Clock Gate.*/
269
270 kCLOCK_Rdc = CCM_TUPLE(49U, 33U), /*!< RDC Clock Gate.*/
271
272 kCLOCK_Sai1 = CCM_TUPLE(51U, 75U), /*!< SAI1 Clock Gate.*/
273 kCLOCK_Sai2 = CCM_TUPLE(52U, 76U), /*!< SAI2 Clock Gate.*/
274 kCLOCK_Sai3 = CCM_TUPLE(53U, 77U), /*!< SAI3 Clock Gate.*/
275 kCLOCK_Sai4 = CCM_TUPLE(54U, 78U), /*!< SAI4 Clock Gate.*/
276 kCLOCK_Sai5 = CCM_TUPLE(55U, 79U), /*!< SAI5 Clock Gate.*/
277 kCLOCK_Sai6 = CCM_TUPLE(56U, 80U), /*!< SAI6 Clock Gate.*/
278
279 kCLOCK_Sdma1 = CCM_TUPLE(58U, 33U), /*!< SDMA1 Clock Gate.*/
280 kCLOCK_Sdma2 = CCM_TUPLE(59U, 35U), /*!< SDMA2 Clock Gate.*/
281
282 kCLOCK_Sec_Debug = CCM_TUPLE(60U, 33U), /*!< SEC_DEBUG Clock Gate.*/
283
284 kCLOCK_Sema42_1 = CCM_TUPLE(61U, 33U), /*!< RDC SEMA42 Clock Gate.*/
285 kCLOCK_Sema42_2 = CCM_TUPLE(62U, 33U), /*!< RDC SEMA42 Clock Gate.*/
286
287 kCLOCK_Sim_display = CCM_TUPLE(63U, 16U), /*!< SIM_Display Clock Gate.*/
288 kCLOCK_Sim_m = CCM_TUPLE(65U, 32U), /*!< SIM_M Clock Gate.*/
289 kCLOCK_Sim_main = CCM_TUPLE(66U, 16U), /*!< SIM_MAIN Clock Gate.*/
290 kCLOCK_Sim_s = CCM_TUPLE(67U, 32U), /*!< SIM_S Clock Gate.*/
291 kCLOCK_Sim_wakeup = CCM_TUPLE(68U, 32U), /*!< SIM_WAKEUP Clock Gate.*/
292
293 kCLOCK_Uart1 = CCM_TUPLE(73U, 94U), /*!< UART1 Clock Gate.*/
294 kCLOCK_Uart2 = CCM_TUPLE(74U, 95U), /*!< UART2 Clock Gate.*/
295 kCLOCK_Uart3 = CCM_TUPLE(75U, 96U), /*!< UART3 Clock Gate.*/
296 kCLOCK_Uart4 = CCM_TUPLE(76U, 97U), /*!< UART4 Clock Gate.*/
297
298 kCLOCK_Wdog1 = CCM_TUPLE(83U, 114U), /*!< WDOG1 Clock Gate.*/
299 kCLOCK_Wdog2 = CCM_TUPLE(84U, 114U), /*!< WDOG2 Clock Gate.*/
300 kCLOCK_Wdog3 = CCM_TUPLE(85U, 114U), /*!< WDOG3 Clock Gate.*/
301
302 kCLOCK_TempSensor = CCM_TUPLE(98U, 0xFFFF), /*!< TempSensor Clock Gate.*/
303
304} clock_ip_name_t;
305
306/*! @brief ccm root name used to get clock frequency. */
307typedef enum _clock_root_control
308{
309 kCLOCK_RootM4 = (uint32_t)(&(CCM)->ROOT[1].TARGET_ROOT), /*!< ARM Cortex-M4 Clock control name.*/
310 kCLOCK_RootAxi = (uint32_t)(&(CCM)->ROOT[16].TARGET_ROOT), /*!< AXI Clock control name.*/
311 kCLOCK_RootNoc = (uint32_t)(&(CCM)->ROOT[26].TARGET_ROOT), /*!< NOC Clock control name.*/
312 kCLOCK_RootAhb = (uint32_t)(&(CCM)->ROOT[32].TARGET_ROOT), /*!< AHB Clock control name.*/
313 kCLOCK_RootIpg = (uint32_t)(&(CCM)->ROOT[33].TARGET_ROOT), /*!< IPG Clock control name.*/
314 kCLOCK_RootDramAlt = (uint32_t)(&(CCM)->ROOT[64].TARGET_ROOT), /*!< DRAM ALT Clock control name.*/
315
316 kCLOCK_RootSai1 = (uint32_t)(&(CCM)->ROOT[75].TARGET_ROOT), /*!< SAI1 Clock control name.*/
317 kCLOCK_RootSai2 = (uint32_t)(&(CCM)->ROOT[76].TARGET_ROOT), /*!< SAI2 Clock control name.*/
318 kCLOCK_RootSai3 = (uint32_t)(&(CCM)->ROOT[77].TARGET_ROOT), /*!< SAI3 Clock control name.*/
319 kCLOCK_RootSai4 = (uint32_t)(&(CCM)->ROOT[78].TARGET_ROOT), /*!< SAI4 Clock control name.*/
320 kCLOCK_RootSai5 = (uint32_t)(&(CCM)->ROOT[79].TARGET_ROOT), /*!< SAI5 Clock control name.*/
321 kCLOCK_RootSai6 = (uint32_t)(&(CCM)->ROOT[80].TARGET_ROOT), /*!< SAI6 Clock control name.*/
322
323 kCLOCK_RootQspi = (uint32_t)(&(CCM)->ROOT[87].TARGET_ROOT), /*!< QSPI Clock control name.*/
324
325 kCLOCK_RootI2c1 = (uint32_t)(&(CCM)->ROOT[90].TARGET_ROOT), /*!< I2C1 Clock control name.*/
326 kCLOCK_RootI2c2 = (uint32_t)(&(CCM)->ROOT[91].TARGET_ROOT), /*!< I2C2 Clock control name.*/
327 kCLOCK_RootI2c3 = (uint32_t)(&(CCM)->ROOT[92].TARGET_ROOT), /*!< I2C3 Clock control name.*/
328 kCLOCK_RootI2c4 = (uint32_t)(&(CCM)->ROOT[93].TARGET_ROOT), /*!< I2C4 Clock control name.*/
329
330 kCLOCK_RootUart1 = (uint32_t)(&(CCM)->ROOT[94].TARGET_ROOT), /*!< UART1 Clock control name.*/
331 kCLOCK_RootUart2 = (uint32_t)(&(CCM)->ROOT[95].TARGET_ROOT), /*!< UART2 Clock control name.*/
332 kCLOCK_RootUart3 = (uint32_t)(&(CCM)->ROOT[96].TARGET_ROOT), /*!< UART3 Clock control name.*/
333 kCLOCK_RootUart4 = (uint32_t)(&(CCM)->ROOT[97].TARGET_ROOT), /*!< UART4 Clock control name.*/
334
335 kCLOCK_RootEcspi1 = (uint32_t)(&(CCM)->ROOT[101].TARGET_ROOT), /*!< ECSPI1 Clock control name.*/
336 kCLOCK_RootEcspi2 = (uint32_t)(&(CCM)->ROOT[102].TARGET_ROOT), /*!< ECSPI2 Clock control name.*/
337 kCLOCK_RootEcspi3 = (uint32_t)(&(CCM)->ROOT[131].TARGET_ROOT), /*!< ECSPI3 Clock control name.*/
338
339 kCLOCK_RootPwm1 = (uint32_t)(&(CCM)->ROOT[103].TARGET_ROOT), /*!< PWM1 Clock control name.*/
340 kCLOCK_RootPwm2 = (uint32_t)(&(CCM)->ROOT[104].TARGET_ROOT), /*!< PWM2 Clock control name.*/
341 kCLOCK_RootPwm3 = (uint32_t)(&(CCM)->ROOT[105].TARGET_ROOT), /*!< PWM3 Clock control name.*/
342 kCLOCK_RootPwm4 = (uint32_t)(&(CCM)->ROOT[106].TARGET_ROOT), /*!< PWM4 Clock control name.*/
343
344 kCLOCK_RootGpt1 = (uint32_t)(&(CCM)->ROOT[107].TARGET_ROOT), /*!< GPT1 Clock control name.*/
345 kCLOCK_RootGpt2 = (uint32_t)(&(CCM)->ROOT[108].TARGET_ROOT), /*!< GPT2 Clock control name.*/
346 kCLOCK_RootGpt3 = (uint32_t)(&(CCM)->ROOT[109].TARGET_ROOT), /*!< GPT3 Clock control name.*/
347 kCLOCK_RootGpt4 = (uint32_t)(&(CCM)->ROOT[110].TARGET_ROOT), /*!< GPT4 Clock control name.*/
348 kCLOCK_RootGpt5 = (uint32_t)(&(CCM)->ROOT[111].TARGET_ROOT), /*!< GPT5 Clock control name.*/
349 kCLOCK_RootGpt6 = (uint32_t)(&(CCM)->ROOT[112].TARGET_ROOT), /*!< GPT6 Clock control name.*/
350
351 kCLOCK_RootWdog = (uint32_t)(&(CCM)->ROOT[114].TARGET_ROOT), /*!< WDOG Clock control name.*/
352} clock_root_control_t;
353
354/*! @brief Root clock select enumeration for ARM Cortex-M4 core. */
355typedef enum _clock_rootmux_m4_clk_sel
356{
357 kCLOCK_M4RootmuxOsc25m = 0U, /*!< ARM Cortex-M4 Clock from OSC 25M.*/
358 kCLOCK_M4RootmuxSysPll2Div5 = 1U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL2 divided by 5.*/
359 kCLOCK_M4RootmuxSysPll2Div4 = 2U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL2 divided by 4.*/
360 kCLOCK_M4RootmuxSysPll1Div3 = 3U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL1 divided by 3.*/
361 kCLOCK_M4RootmuxSysPll1 = 4U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL1.*/
362 kCLOCK_M4RootmuxAudioPll1 = 5U, /*!< ARM Cortex-M4 Clock from AUDIO PLL1.*/
363 kCLOCK_M4RootmuxVideoPll1 = 6U, /*!< ARM Cortex-M4 Clock from VIDEO PLL1.*/
364 kCLOCK_M4RootmuxSysPll3 = 7U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL3.*/
365} clock_rootmux_m4_clk_sel_t;
366
367/*! @brief Root clock select enumeration for AXI bus. */
368typedef enum _clock_rootmux_axi_clk_sel
369{
370 kCLOCK_AxiRootmuxOsc25m = 0U, /*!< ARM AXI Clock from OSC 25M.*/
371 kCLOCK_AxiRootmuxSysPll2Div3 = 1U, /*!< ARM AXI Clock from SYSTEM PLL2 divided by 3.*/
372 kCLOCK_AxiRootmuxSysPll1 = 2U, /*!< ARM AXI Clock from SYSTEM PLL1.*/
373 kCLOCK_AxiRootmuxSysPll2Div4 = 3U, /*!< ARM AXI Clock from SYSTEM PLL2 divided by 4.*/
374 kCLOCK_AxiRootmuxSysPll2 = 4U, /*!< ARM AXI Clock from SYSTEM PLL2.*/
375 kCLOCK_AxiRootmuxAudioPll1 = 5U, /*!< ARM AXI Clock from AUDIO PLL1.*/
376 kCLOCK_AxiRootmuxVideoPll1 = 6U, /*!< ARM AXI Clock from VIDEO PLL1.*/
377 kCLOCK_AxiRootmuxSysPll1Div8 = 7U, /*!< ARM AXI Clock from SYSTEM PLL1 divided by 8.*/
378} clock_rootmux_axi_clk_sel_t;
379
380/*! @brief Root clock select enumeration for AHB bus. */
381typedef enum _clock_rootmux_ahb_clk_sel
382{
383 kCLOCK_AhbRootmuxOsc25m = 0U, /*!< ARM AHB Clock from OSC 25M.*/
384 kCLOCK_AhbRootmuxSysPll1Div6 = 1U, /*!< ARM AHB Clock from SYSTEM PLL1 divided by 6.*/
385 kCLOCK_AhbRootmuxSysPll1 = 2U, /*!< ARM AHB Clock from SYSTEM PLL1.*/
386 kCLOCK_AhbRootmuxSysPll1Div2 = 3U, /*!< ARM AHB Clock from SYSTEM PLL1 divided by 2.*/
387 kCLOCK_AhbRootmuxSysPll2Div8 = 4U, /*!< ARM AHB Clock from SYSTEM PLL2 divided by 8.*/
388 kCLOCK_AhbRootmuxSysPll3 = 5U, /*!< ARM AHB Clock from SYSTEM PLL3.*/
389 kCLOCK_AhbRootmuxAudioPll1 = 6U, /*!< ARM AHB Clock from AUDIO PLL1.*/
390 kCLOCK_AhbRootmuxVideoPll1 = 7U, /*!< ARM AHB Clock from VIDEO PLL1.*/
391} clock_rootmux_ahb_clk_sel_t;
392
393/*! @brief Root clock select enumeration for QSPI peripheral. */
394typedef enum _clock_rootmux_qspi_clk_sel
395{
396 kCLOCK_QspiRootmuxOsc25m = 0U, /*!< ARM QSPI Clock from OSC 25M.*/
397 kCLOCK_QspiRootmuxSysPll1Div2 = 1U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 2.*/
398 kCLOCK_QspiRootmuxSysPll1 = 2U, /*!< ARM QSPI Clock from SYSTEM PLL1.*/
399 kCLOCK_QspiRootmuxSysPll2Div2 = 3U, /*!< ARM QSPI Clock from SYSTEM PLL2 divided by 2.*/
400 kCLOCK_QspiRootmuxAudioPll2 = 4, /*!< ARM QSPI Clock from AUDIO PLL2.*/
401 kCLOCK_QspiRootmuxSysPll1Div3 = 5U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 3 */
402 kCLOCK_QspiRootmuxSysPll3 = 6U, /*!< ARM QSPI Clock from SYSTEM PLL3.*/
403 kCLOCK_QspiRootmuxSysPll1Div8 = 7U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 8.*/
404} clock_rootmux_qspi_clk_sel_t;
405
406/*! @brief Root clock select enumeration for ECSPI peripheral. */
407typedef enum _clock_rootmux_ecspi_clk_sel
408{
409 kCLOCK_EcspiRootmuxOsc25m = 0U, /*!< ECSPI Clock from OSC 25M.*/
410 kCLOCK_EcspiRootmuxSysPll2Div5 = 1U, /*!< ECSPI Clock from SYSTEM PLL2 divided by 5.*/
411 kCLOCK_EcspiRootmuxSysPll1Div20 = 2U, /*!< ECSPI Clock from SYSTEM PLL1 divided by 20.*/
412 kCLOCK_EcspiRootmuxSysPll1Div5 = 3U, /*!< ECSPI Clock from SYSTEM PLL1 divided by 5.*/
413 kCLOCK_EcspiRootmuxSysPll1 = 4U, /*!< ECSPI Clock from SYSTEM PLL1.*/
414 kCLOCK_EcspiRootmuxSysPll3 = 5U, /*!< ECSPI Clock from SYSTEM PLL3.*/
415 kCLOCK_EcspiRootmuxSysPll2Div4 = 6U, /*!< ECSPI Clock from SYSTEM PLL2 divided by 4.*/
416 kCLOCK_EcspiRootmuxAudioPll2 = 7U, /*!< ECSPI Clock from AUDIO PLL2.*/
417} clock_rootmux_ecspi_clk_sel_t;
418
419/*! @brief Root clock select enumeration for I2C peripheral. */
420typedef enum _clock_rootmux_i2c_clk_sel
421{
422 kCLOCK_I2cRootmuxOsc25m = 0U, /*!< I2C Clock from OSC 25M.*/
423 kCLOCK_I2cRootmuxSysPll1Div5 = 1U, /*!< I2C Clock from SYSTEM PLL1 divided by 5.*/
424 kCLOCK_I2cRootmuxSysPll2Div20 = 2U, /*!< I2C Clock from SYSTEM PLL2 divided by 20.*/
425 kCLOCK_I2cRootmuxSysPll3 = 3U, /*!< I2C Clock from SYSTEM PLL3 .*/
426 kCLOCK_I2cRootmuxAudioPll1 = 4U, /*!< I2C Clock from AUDIO PLL1.*/
427 kCLOCK_I2cRootmuxVideoPll1 = 5U, /*!< I2C Clock from VIDEO PLL1.*/
428 kCLOCK_I2cRootmuxAudioPll2 = 6U, /*!< I2C Clock from AUDIO PLL2.*/
429 kCLOCK_I2cRootmuxSysPll1Div6 = 7U, /*!< I2C Clock from SYSTEM PLL1 divided by 6.*/
430} clock_rootmux_i2c_clk_sel_t;
431
432/*! @brief Root clock select enumeration for UART peripheral. */
433typedef enum _clock_rootmux_uart_clk_sel
434{
435 kCLOCK_UartRootmuxOsc25m = 0U, /*!< UART Clock from OSC 25M.*/
436 kCLOCK_UartRootmuxSysPll1Div10 = 1U, /*!< UART Clock from SYSTEM PLL1 divided by 10.*/
437 kCLOCK_UartRootmuxSysPll2Div5 = 2U, /*!< UART Clock from SYSTEM PLL2 divided by 5.*/
438 kCLOCK_UartRootmuxSysPll2Div10 = 3U, /*!< UART Clock from SYSTEM PLL2 divided by 10.*/
439 kCLOCK_UartRootmuxSysPll3 = 4U, /*!< UART Clock from SYSTEM PLL3.*/
440 kCLOCK_UartRootmuxExtClk2 = 5U, /*!< UART Clock from External Clock 2.*/
441 kCLOCK_UartRootmuxExtClk34 = 6U, /*!< UART Clock from External Clock 3, External Clock 4.*/
442 kCLOCK_UartRootmuxAudioPll2 = 7U, /*!< UART Clock from Audio PLL2.*/
443} clock_rootmux_uart_clk_sel_t;
444
445/*! @brief Root clock select enumeration for GPT peripheral. */
446typedef enum _clock_rootmux_gpt
447{
448 kCLOCK_GptRootmuxOsc25m = 0U, /*!< GPT Clock from OSC 25M.*/
449 kCLOCK_GptRootmuxSystemPll2Div10 = 1U, /*!< GPT Clock from SYSTEM PLL2 divided by 10.*/
450 kCLOCK_GptRootmuxSysPll1Div2 = 2U, /*!< GPT Clock from SYSTEM PLL1 divided by 2.*/
451 kCLOCK_GptRootmuxSysPll1Div20 = 3U, /*!< GPT Clock from SYSTEM PLL1 divided by 20.*/
452 kCLOCK_GptRootmuxVideoPll1 = 4U, /*!< GPT Clock from VIDEO PLL1.*/
453 kCLOCK_GptRootmuxSystemPll1Div10 = 5U, /*!< GPT Clock from SYSTEM PLL1 divided by 10.*/
454 kCLOCK_GptRootmuxAudioPll1 = 6U, /*!< GPT Clock from AUDIO PLL1.*/
455 kCLOCK_GptRootmuxExtClk123 = 7U, /*!< GPT Clock from External Clock1, External Clock2, External Clock3.*/
456} clock_rootmux_gpt_t;
457
458/*! @brief Root clock select enumeration for WDOG peripheral. */
459typedef enum _clock_rootmux_wdog_clk_sel
460{
461 kCLOCK_WdogRootmuxOsc25m = 0U, /*!< WDOG Clock from OSC 25M.*/
462 kCLOCK_WdogRootmuxSysPll1Div6 = 1U, /*!< WDOG Clock from SYSTEM PLL1 divided by 6.*/
463 kCLOCK_WdogRootmuxSysPll1Div5 = 2U, /*!< WDOG Clock from SYSTEM PLL1 divided by 5.*/
464 kCLOCK_WdogRootmuxVpuPll = 3U, /*!< WDOG Clock from VPU DLL.*/
465 kCLOCK_WdogRootmuxSystemPll2Div8 = 4U, /*!< WDOG Clock from SYSTEM PLL2 divided by 8.*/
466 kCLOCK_WdogRootmuxSystemPll3 = 5U, /*!< WDOG Clock from SYSTEM PLL3.*/
467 kCLOCK_WdogRootmuxSystemPll1Div10 = 6U, /*!< WDOG Clock from SYSTEM PLL1 divided by 10.*/
468 kCLOCK_WdogRootmuxSystemPll2Div6 = 7U, /*!< WDOG Clock from SYSTEM PLL2 divided by 6.*/
469} clock_rootmux_wdog_clk_sel_t;
470
471/*! @brief Root clock select enumeration for PWM peripheral. */
472typedef enum _clock_rootmux_pwm_clk_sel
473{
474 kCLOCK_PwmRootmuxOsc25m = 0U, /*!< PWM Clock from OSC 25M.*/
475 kCLOCK_PwmRootmuxSysPll2Div10 = 1U, /*!< PWM Clock from SYSTEM PLL2 divided by 10.*/
476 kCLOCK_PwmRootmuxSysPll1Div5 = 2U, /*!< PWM Clock from SYSTEM PLL1 divided by 5.*/
477 kCLOCK_PwmRootmuxSysPll1Div20 = 3U, /*!< PWM Clock from SYSTEM PLL1 divided by 20.*/
478 kCLOCK_PwmRootmuxSystemPll3 = 4U, /*!< PWM Clock from SYSTEM PLL3.*/
479 kCLOCK_PwmRootmuxExtClk12 = 5U, /*!< PWM Clock from External Clock1, External Clock2.*/
480 kCLOCK_PwmRootmuxSystemPll1Div10 = 6U, /*!< PWM Clock from SYSTEM PLL1 divided by 10.*/
481 kCLOCK_PwmRootmuxVideoPll1 = 7U, /*!< PWM Clock from VIDEO PLL1.*/
482} clock_rootmux_Pwm_clk_sel_t;
483
484/*! @brief Root clock select enumeration for SAI peripheral. */
485typedef enum _clock_rootmux_sai_clk_sel
486{
487 kCLOCK_SaiRootmuxOsc25m = 0U, /*!< SAI Clock from OSC 25M.*/
488 kCLOCK_SaiRootmuxAudioPll1 = 1U, /*!< SAI Clock from AUDIO PLL1.*/
489 kCLOCK_SaiRootmuxAudioPll2 = 2U, /*!< SAI Clock from AUDIO PLL2.*/
490 kCLOCK_SaiRootmuxVideoPll1 = 3U, /*!< SAI Clock from VIDEO PLL1.*/
491 kCLOCK_SaiRootmuxSysPll1Div6 = 4U, /*!< SAI Clock from SYSTEM PLL1 divided by 6.*/
492 kCLOCK_SaiRootmuxOsc27m = 5U, /*!< SAI Clock from OSC 27M.*/
493 kCLOCK_SaiRootmuxExtClk123 = 6U, /*!< SAI Clock from External Clock1, External Clock2, External Clock3.*/
494 kCLOCK_SaiRootmuxExtClk234 = 7U, /*!< SAI Clock from External Clock2, External Clock3, External Clock4.*/
495} clock_rootmux_sai_clk_sel_t;
496
497/*! @brief Root clock select enumeration for NOC CLK. */
498typedef enum _clock_rootmux_noc_clk_sel
499{
500 kCLOCK_NocRootmuxOsc25m = 0U, /*!< NOC Clock from OSC 25M.*/
501 kCLOCK_NocRootmuxSysPll1 = 1U, /*!< NOC Clock from SYSTEM PLL1.*/
502 kCLOCK_NocRootmuxSysPll3 = 2U, /*!< NOC Clock from SYSTEM PLL3.*/
503 kCLOCK_NocRootmuxSysPll2 = 3U, /*!< NOC Clock from SYSTEM PLL2.*/
504 kCLOCK_NocRootmuxSysPll2Div2 = 4U, /*!< NOC Clock from SYSTEM PLL2 divided by 2.*/
505 kCLOCK_NocRootmuxAudioPll1 = 5U, /*!< NOC Clock from AUDIO PLL1.*/
506 kCLOCK_NocRootmuxVideoPll1 = 6U, /*!< NOC Clock from VIDEO PLL1.*/
507 kCLOCK_NocRootmuxAudioPll2 = 7U, /*!< NOC Clock from AUDIO PLL2.*/
508
509} clock_rootmux_noc_clk_sel_t;
510
511/*! @brief CCM PLL gate control. */
512typedef enum _clock_pll_gate
513{
514 kCLOCK_ArmPllGate = (uint32_t)(&(CCM)->PLL_CTRL[12].PLL_CTRL), /*!< ARM PLL Gate.*/
515
516 kCLOCK_GpuPllGate = (uint32_t)(&(CCM)->PLL_CTRL[13].PLL_CTRL), /*!< GPU PLL Gate.*/
517 kCLOCK_VpuPllGate = (uint32_t)(&(CCM)->PLL_CTRL[14].PLL_CTRL), /*!< VPU PLL Gate.*/
518 kCLOCK_DramPllGate = (uint32_t)(&(CCM)->PLL_CTRL[15].PLL_CTRL), /*!< DRAM PLL1 Gate.*/
519
520 kCLOCK_SysPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[16].PLL_CTRL), /*!< SYSTEM PLL1 Gate.*/
521 kCLOCK_SysPll1Div2Gate = (uint32_t)(&(CCM)->PLL_CTRL[17].PLL_CTRL), /*!< SYSTEM PLL1 Div2 Gate.*/
522 kCLOCK_SysPll1Div3Gate = (uint32_t)(&(CCM)->PLL_CTRL[18].PLL_CTRL), /*!< SYSTEM PLL1 Div3 Gate.*/
523 kCLOCK_SysPll1Div4Gate = (uint32_t)(&(CCM)->PLL_CTRL[19].PLL_CTRL), /*!< SYSTEM PLL1 Div4 Gate.*/
524 kCLOCK_SysPll1Div5Gate = (uint32_t)(&(CCM)->PLL_CTRL[20].PLL_CTRL), /*!< SYSTEM PLL1 Div5 Gate.*/
525 kCLOCK_SysPll1Div6Gate = (uint32_t)(&(CCM)->PLL_CTRL[21].PLL_CTRL), /*!< SYSTEM PLL1 Div6 Gate.*/
526 kCLOCK_SysPll1Div8Gate = (uint32_t)(&(CCM)->PLL_CTRL[22].PLL_CTRL), /*!< SYSTEM PLL1 Div8 Gate.*/
527 kCLOCK_SysPll1Div10Gate = (uint32_t)(&(CCM)->PLL_CTRL[23].PLL_CTRL), /*!< SYSTEM PLL1 Div10 Gate.*/
528 kCLOCK_SysPll1Div20Gate = (uint32_t)(&(CCM)->PLL_CTRL[24].PLL_CTRL), /*!< SYSTEM PLL1 Div20 Gate.*/
529
530 kCLOCK_SysPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[25].PLL_CTRL), /*!< SYSTEM PLL2 Gate.*/
531 kCLOCK_SysPll2Div2Gate = (uint32_t)(&(CCM)->PLL_CTRL[26].PLL_CTRL), /*!< SYSTEM PLL2 Div2 Gate.*/
532 kCLOCK_SysPll2Div3Gate = (uint32_t)(&(CCM)->PLL_CTRL[27].PLL_CTRL), /*!< SYSTEM PLL2 Div3 Gate.*/
533 kCLOCK_SysPll2Div4Gate = (uint32_t)(&(CCM)->PLL_CTRL[28].PLL_CTRL), /*!< SYSTEM PLL2 Div4 Gate.*/
534 kCLOCK_SysPll2Div5Gate = (uint32_t)(&(CCM)->PLL_CTRL[29].PLL_CTRL), /*!< SYSTEM PLL2 Div5 Gate.*/
535 kCLOCK_SysPll2Div6Gate = (uint32_t)(&(CCM)->PLL_CTRL[30].PLL_CTRL), /*!< SYSTEM PLL2 Div6 Gate.*/
536 kCLOCK_SysPll2Div8Gate = (uint32_t)(&(CCM)->PLL_CTRL[31].PLL_CTRL), /*!< SYSTEM PLL2 Div8 Gate.*/
537 kCLOCK_SysPll2Div10Gate = (uint32_t)(&(CCM)->PLL_CTRL[32].PLL_CTRL), /*!< SYSTEM PLL2 Div10 Gate.*/
538 kCLOCK_SysPll2Div20Gate = (uint32_t)(&(CCM)->PLL_CTRL[33].PLL_CTRL), /*!< SYSTEM PLL2 Div20 Gate.*/
539
540 kCLOCK_SysPll3Gate = (uint32_t)(&(CCM)->PLL_CTRL[34].PLL_CTRL), /*!< SYSTEM PLL3 Gate.*/
541
542 kCLOCK_AudioPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[35].PLL_CTRL), /*!< AUDIO PLL1 Gate.*/
543 kCLOCK_AudioPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[36].PLL_CTRL), /*!< AUDIO PLL2 Gate.*/
544 kCLOCK_VideoPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[37].PLL_CTRL), /*!< VIDEO PLL1 Gate.*/
545 kCLOCK_VideoPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[38].PLL_CTRL), /*!< VIDEO PLL2 Gate.*/
546} clock_pll_gate_t;
547
548/*! @brief CCM gate control value. */
549typedef enum _clock_gate_value
550{
551 kCLOCK_ClockNotNeeded = 0x0U, /*!< Clock always disabled.*/
552 kCLOCK_ClockNeededRun = 0x1111U, /*!< Clock enabled when CPU is running.*/
553 kCLOCK_ClockNeededRunWait = 0x2222U, /*!< Clock enabled when CPU is running or in WAIT mode.*/
554 kCLOCK_ClockNeededAll = 0x3333U, /*!< Clock always enabled.*/
555} clock_gate_value_t;
556
557/*!
558 * @brief PLL control names for PLL bypass.
559 *
560 * These constants define the PLL control names for PLL bypass.\n
561 * - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
562 * - 16:20: bypass bit shift.
563 */
564typedef enum _clock_pll_bypass_ctrl
565{
566 kCLOCK_AudioPll1BypassCtrl = CCM_ANALOG_TUPLE(
567 AUDIO_PLL1_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Audio PLL1 bypass Control.*/
568 kCLOCK_AudioPll2BypassCtrl = CCM_ANALOG_TUPLE(
569 AUDIO_PLL2_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Audio PLL2 bypass Control.*/
570 kCLOCK_VideoPll1BypassCtrl = CCM_ANALOG_TUPLE(
571 VIDEO_PLL1_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Video Pll1 bypass Control.*/
572 kCLOCK_GpuPLLPwrBypassCtrl = CCM_ANALOG_TUPLE(
573 GPU_PLL_CFG0_OFFSET, CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Gpu PLL bypass Control.*/
574 kCLOCK_VpuPllPwrBypassCtrl = CCM_ANALOG_TUPLE(
575 VPU_PLL_CFG0_OFFSET, CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Vpu PLL bypass Control.*/
576 kCLOCK_ArmPllPwrBypassCtrl = CCM_ANALOG_TUPLE(
577 ARM_PLL_CFG0_OFFSET, CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Arm PLL bypass Control.*/
578
579 kCLOCK_SysPll1InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
580 SYS_PLL1_CFG0_OFFSET,
581 CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM System PLL1 internal pll1 bypass Control.*/
582 kCLOCK_SysPll1InternalPll2BypassCtrl = CCM_ANALOG_TUPLE(
583 SYS_PLL1_CFG0_OFFSET,
584 CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM System PLL1 internal pll2 bypass Control.*/
585
586 kCLOCK_SysPll2InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
587 SYS_PLL2_CFG0_OFFSET,
588 CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM Analog System PLL1 internal pll1 bypass Control.*/
589 kCLOCK_SysPll2InternalPll2BypassCtrl = CCM_ANALOG_TUPLE(
590 SYS_PLL2_CFG0_OFFSET,
591 CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM Analog VIDEO System PLL1 internal pll1 bypass Control.*/
592
593 kCLOCK_SysPll3InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
594 SYS_PLL3_CFG0_OFFSET, CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM Analog VIDEO PLL bypass Control.*/
595 kCLOCK_SysPll3InternalPll2BypassCtrl = CCM_ANALOG_TUPLE(
596 SYS_PLL3_CFG0_OFFSET, CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM Analog VIDEO PLL bypass Control.*/
597
598 kCLOCK_VideoPll2InternalPll1BypassCtrl =
599 CCM_ANALOG_TUPLE(VIDEO_PLL2_CFG0_OFFSET,
600 CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM Analog 480M PLL bypass Control.*/
601 kCLOCK_VideoPll2InternalPll2BypassCtrl =
602 CCM_ANALOG_TUPLE(VIDEO_PLL2_CFG0_OFFSET,
603 CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM Analog 480M PLL bypass Control.*/
604
605 kCLOCK_DramPllInternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
606 DRAM_PLL_CFG0_OFFSET, CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM Analog 480M PLL bypass Control.*/
607 kCLOCK_DramPllInternalPll2BypassCtrl = CCM_ANALOG_TUPLE(
608 DRAM_PLL_CFG0_OFFSET, CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM Analog 480M PLL bypass Control.*/
609} clock_pll_bypass_ctrl_t;
610
611/*!
612 * @brief PLL clock names for clock enable/disable settings.
613 *
614 * These constants define the PLL clock names for PLL clock enable/disable operations.\n
615 * - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
616 * - 16:20: Clock enable bit shift.
617 */
618typedef enum _ccm_analog_pll_clke
619{
620 kCLOCK_AudioPll1Clke =
621 CCM_ANALOG_TUPLE(AUDIO_PLL1_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_SHIFT), /*!< Audio pll1 clke */
622 kCLOCK_AudioPll2Clke =
623 CCM_ANALOG_TUPLE(AUDIO_PLL2_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_SHIFT), /*!< Audio pll2 clke */
624 kCLOCK_VideoPll1Clke =
625 CCM_ANALOG_TUPLE(VIDEO_PLL1_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_SHIFT), /*!< Video pll1 clke */
626 kCLOCK_GpuPllClke =
627 CCM_ANALOG_TUPLE(GPU_PLL_CFG0_OFFSET, CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_SHIFT), /*!< Gpu pll clke */
628 kCLOCK_VpuPllClke =
629 CCM_ANALOG_TUPLE(VPU_PLL_CFG0_OFFSET, CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_SHIFT), /*!< Vpu pll clke */
630 kCLOCK_ArmPllClke =
631 CCM_ANALOG_TUPLE(ARM_PLL_CFG0_OFFSET, CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_SHIFT), /*!< Arm pll clke */
632
633 kCLOCK_SystemPll1Clke =
634 CCM_ANALOG_TUPLE(SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_SHIFT), /*!< System pll1 clke */
635 kCLOCK_SystemPll1Div2Clke = CCM_ANALOG_TUPLE(
636 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE_SHIFT), /*!< System pll1 Div2 clke */
637 kCLOCK_SystemPll1Div3Clke = CCM_ANALOG_TUPLE(
638 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE_SHIFT), /*!< System pll1 Div3 clke */
639 kCLOCK_SystemPll1Div4Clke = CCM_ANALOG_TUPLE(
640 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE_SHIFT), /*!< System pll1 Div4 clke */
641 kCLOCK_SystemPll1Div5Clke = CCM_ANALOG_TUPLE(
642 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE_SHIFT), /*!< System pll1 Div5 clke */
643 kCLOCK_SystemPll1Div6Clke = CCM_ANALOG_TUPLE(
644 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE_SHIFT), /*!< System pll1 Div6 clke */
645 kCLOCK_SystemPll1Div8Clke = CCM_ANALOG_TUPLE(
646 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE_SHIFT), /*!< System pll1 Div8 clke */
647 kCLOCK_SystemPll1Div10Clke = CCM_ANALOG_TUPLE(
648 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE_SHIFT), /*!< System pll1 Div10 clke */
649 kCLOCK_SystemPll1Div20Clke = CCM_ANALOG_TUPLE(
650 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE_SHIFT), /*!< System pll1 Div20 clke */
651
652 kCLOCK_SystemPll2Clke =
653 CCM_ANALOG_TUPLE(SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_SHIFT), /*!< System pll2 clke */
654 kCLOCK_SystemPll2Div2Clke = CCM_ANALOG_TUPLE(
655 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE_SHIFT), /*!< System pll2 Div2 clke */
656 kCLOCK_SystemPll2Div3Clke = CCM_ANALOG_TUPLE(
657 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE_SHIFT), /*!< System pll2 Div3 clke */
658 kCLOCK_SystemPll2Div4Clke = CCM_ANALOG_TUPLE(
659 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE_SHIFT), /*!< System pll2 Div4 clke */
660 kCLOCK_SystemPll2Div5Clke = CCM_ANALOG_TUPLE(
661 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE_SHIFT), /*!< System pll2 Div5 clke */
662 kCLOCK_SystemPll2Div6Clke = CCM_ANALOG_TUPLE(
663 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE_SHIFT), /*!< System pll2 Div6 clke */
664 kCLOCK_SystemPll2Div8Clke = CCM_ANALOG_TUPLE(
665 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE_SHIFT), /*!< System pll2 Div8 clke */
666 kCLOCK_SystemPll2Div10Clke = CCM_ANALOG_TUPLE(
667 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE_SHIFT), /*!< System pll2 Div10 clke */
668 kCLOCK_SystemPll2Div20Clke = CCM_ANALOG_TUPLE(
669 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE_SHIFT), /*!< System pll2 Div20 clke */
670
671 kCLOCK_SystemPll3Clke =
672 CCM_ANALOG_TUPLE(SYS_PLL3_CFG0_OFFSET, CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_SHIFT), /*!< System pll3 clke */
673 kCLOCK_VideoPll2Clke =
674 CCM_ANALOG_TUPLE(VIDEO_PLL2_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_SHIFT), /*!< Video pll2 clke */
675 kCLOCK_DramPllClke =
676 CCM_ANALOG_TUPLE(DRAM_PLL_CFG0_OFFSET, CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_SHIFT), /*!< Dram pll clke */
677 kCLOCK_OSC25MClke =
678 CCM_ANALOG_TUPLE(OSC_MISC_CFG_OFFSET, CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_SHIFT), /*!< OSC25M clke */
679 kCLOCK_OSC27MClke =
680 CCM_ANALOG_TUPLE(OSC_MISC_CFG_OFFSET, CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_SHIFT), /*!< OSC27M clke */
681
682} clock_pll_clke_t;
683
684/*!
685 * @brief ANALOG Power down override control.
686 */
687typedef enum _clock_pll_ctrl
688{
689 kCLOCK_AudioPll1Ctrl = CCM_ANALOG_TUPLE(AUDIO_PLL1_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_SHIFT),
690 kCLOCK_AudioPll2Ctrl = CCM_ANALOG_TUPLE(AUDIO_PLL2_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_SHIFT),
691 kCLOCK_VideoPll1Ctrl = CCM_ANALOG_TUPLE(VIDEO_PLL1_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_SHIFT),
692 kCLOCK_GpuPllCtrl = CCM_ANALOG_TUPLE(GPU_PLL_CFG0_OFFSET, CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_SHIFT),
693 kCLOCK_VpuPllCtrl = CCM_ANALOG_TUPLE(VPU_PLL_CFG0_OFFSET, CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_SHIFT),
694 kCLOCK_ArmPllCtrl = CCM_ANALOG_TUPLE(ARM_PLL_CFG0_OFFSET, CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_SHIFT),
695
696 kCLOCK_SystemPll1Ctrl = CCM_ANALOG_TUPLE(SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_SHIFT),
697 kCLOCK_SystemPll2Ctrl = CCM_ANALOG_TUPLE(SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_SHIFT),
698 kCLOCK_SystemPll3Ctrl = CCM_ANALOG_TUPLE(SYS_PLL3_CFG0_OFFSET, CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_SHIFT),
699 kCLOCK_VideoPll2Ctrl = CCM_ANALOG_TUPLE(VIDEO_PLL2_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_SHIFT),
700 kCLOCK_DramPllCtrl = CCM_ANALOG_TUPLE(DRAM_PLL_CFG0_OFFSET, CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_SHIFT),
701
702} clock_pll_ctrl_t;
703
704/*! @brief OSC work mode. */
705enum _osc_mode
706{
707 kOSC_OscMode = 0U, /*!< OSC oscillator mode */
708 kOSC_ExtMode = 1U, /*!< OSC external mode */
709};
710
711/*! @brief OSC 32K input select. */
712typedef enum _osc32_src
713{
714 kOSC32_Src25MDiv800 = 0U, /*!< source from 25M divide 800 */
715 kOSC32_SrcRTC, /*!< source from RTC */
716} osc32_src_t;
717
718/*! @brief PLL reference clock select. */
719enum _ccm_analog_pll_ref_clk
720{
721 kANALOG_PllRefOsc25M = 0U, /*!< reference OSC 25M */
722 kANALOG_PllRefOsc27M = 1U, /*!< reference OSC 27M */
723 kANALOG_PllRefOscHdmiPhy27M = 2U, /*!< reference HDMI PHY 27M */
724 kANALOG_PllRefClkPN = 3U, /*!< reference CLK_P_N */
725};
726
727/*!
728 * @brief OSC configuration structure.
729 */
730typedef struct _osc_config
731{
732 uint8_t oscMode; /*!< ext or osc mode */
733 uint8_t oscDiv; /*!< osc divider */
734} osc_config_t;
735
736/*!
737 * @brief Fractional-N PLL configuration.
738 * Note: all the dividers in this configuration structure are the actually divider, software will map it to register
739 * value
740 */
741typedef struct _ccm_analog_frac_pll_config
742{
743 uint8_t refSel; /*!< pll reference clock sel */
744
745 uint8_t refDiv; /*!< A 6bit divider to make sure the REF must be within the range 10MHZ~300MHZ */
746
747 uint32_t fractionDiv; /*!< Inlcude fraction divider(divider:1:2^24) output clock
748 range is 2000MHZ-4000MHZ */
749 uint8_t intDiv; /*and integer divide(divider: 1:32)*/
750 uint8_t outDiv; /*!< output clock divide, output clock range is 30MHZ to 2000MHZ, must be a even value */
751
752} ccm_analog_frac_pll_config_t;
753
754/*!
755 * @brief SSCG PLL configuration.
756 * Note: all the dividers in this configuration structure are the actually divider, software will map it to register
757 * value
758 */
759typedef struct _ccm_analog_sscg_pll_config
760{
761 uint8_t refSel; /*!< pll reference clock sel */
762
763 uint8_t refDiv1; /*!< A 3bit divider to make sure the REF must be within the range 25MHZ~235MHZ ,post_divide REF
764 must be within the range 25MHZ~54MHZ */
765 uint8_t refDiv2; /*!< A 6bit divider to make sure the post_divide REF must be within the range 54MHZ~75MHZ */
766
767 uint32_t loopDivider1; /*!< A 6bit internal PLL1 feedback clock divider, output clock range must be within the range
768 1600MHZ-2400MHZ */
769 uint32_t loopDivider2; /*!< A 6bit internal PLL2 feedback clock divider, output clock range must be within the range
770 1200MHZ-2400MHZ */
771
772 uint8_t outDiv; /*!< A 6bit output clock divide, output clock range is 20MHZ to 1200MHZ */
773
774} ccm_analog_sscg_pll_config_t;
775
776/*******************************************************************************
777 * API
778 ******************************************************************************/
779
780#if defined(__cplusplus)
781extern "C" {
782#endif
783
784/*!
785 * @name CCM Root Clock Setting
786 * @{
787 */
788
789/*!
790 * @brief Set clock root mux.
791 * User maybe need to set more than one mux ROOT according to the clock tree
792 * description in the reference manual.
793 *
794 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration).
795 * @param mux Root mux value (see _ccm_rootmux_xxx enumeration).
796 */
797static inline void CLOCK_SetRootMux(clock_root_control_t rootClk, uint32_t mux)
798{
799 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux);
800}
801
802/*!
803 * @brief Get clock root mux.
804 * In order to get the clock source of root, user maybe need to get more than one
805 * ROOT's mux value to obtain the final clock source of root.
806 *
807 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration).
808 * @return Root mux value (see _ccm_rootmux_xxx enumeration).
809 */
810static inline uint32_t CLOCK_GetRootMux(clock_root_control_t rootClk)
811{
812 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT;
813}
814
815/*!
816 * @brief Enable clock root
817 *
818 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration)
819 */
820static inline void CLOCK_EnableRoot(clock_root_control_t rootClk)
821{
822 CCM_REG_SET(rootClk) = CCM_TARGET_ROOT_SET_ENABLE_MASK;
823}
824
825/*!
826 * @brief Disable clock root
827 *
828 * @param rootClk Root control (see @ref clock_root_control_t enumeration)
829 */
830static inline void CLOCK_DisableRoot(clock_root_control_t rootClk)
831{
832 CCM_REG_CLR(rootClk) = CCM_TARGET_ROOT_CLR_ENABLE_MASK;
833}
834
835/*!
836 * @brief Check whether clock root is enabled
837 *
838 * @param rootClk Root control (see @ref clock_root_control_t enumeration)
839 * @return CCM root enabled or not.
840 * - true: Clock root is enabled.
841 * - false: Clock root is disabled.
842 */
843static inline bool CLOCK_IsRootEnabled(clock_root_control_t rootClk)
844{
845 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK);
846}
847
848/*!
849 * @brief Update clock root in one step, for dynamical clock switching
850 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
851 *
852 * @param ccmRootClk Root control (see @ref clock_root_control_t enumeration)
853 * @param mux root mux value (see _ccm_rootmux_xxx enumeration)
854 * @param pre Pre divider value (0-7, divider=n+1)
855 * @param post Post divider value (0-63, divider=n+1)
856 */
857void CLOCK_UpdateRoot(clock_root_control_t ccmRootClk, uint32_t mux, uint32_t pre, uint32_t post);
858
859/*!
860 * @brief Set root clock divider
861 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
862 *
863 * @param ccmRootClk Root control (see @ref clock_root_control_t enumeration)
864 * @param pre Pre divider value (1-8)
865 * @param post Post divider value (1-64)
866 */
867void CLOCK_SetRootDivider(clock_root_control_t ccmRootClk, uint32_t pre, uint32_t post);
868
869/*!
870 * @brief Get clock root PRE_PODF.
871 * In order to get the clock source of root, user maybe need to get more than one
872 * ROOT's mux value to obtain the final clock source of root.
873 *
874 * @param rootClk Root clock name (see @ref clock_root_control_t enumeration).
875 * @return Root Pre divider value.
876 */
877static inline uint32_t CLOCK_GetRootPreDivider(clock_root_control_t rootClk)
878{
879 return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U;
880}
881
882/*!
883 * @brief Get clock root POST_PODF.
884 * In order to get the clock source of root, user maybe need to get more than one
885 * ROOT's mux value to obtain the final clock source of root.
886 *
887 * @param rootClk Root clock name (see @ref clock_root_control_t enumeration).
888 * @return Root Post divider value.
889 */
890static inline uint32_t CLOCK_GetRootPostDivider(clock_root_control_t rootClk)
891{
892 return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + 1U;
893}
894
895/*!
896 * @name OSC setting
897 * @{
898 */
899/*!
900 * @brief OSC25M init
901 *
902 * @param config osc configuration.
903 */
904void CLOCK_InitOSC25M(const osc_config_t *config);
905
906/*!
907 * @brief OSC25M deinit
908 *
909 */
910void CLOCK_DeinitOSC25M(void);
911
912/*!
913 * @brief OSC27M init
914 * @param config osc configuration.
915 *
916 */
917void CLOCK_InitOSC27M(const osc_config_t *config);
918
919/*!
920 * @brief OSC27M deinit
921 *
922 */
923void CLOCK_DeinitOSC27M(void);
924
925/*!
926 * @brief switch 32KHZ OSC input
927 * @param sel OSC32 input clock select
928 */
929static inline void CLOCK_SwitchOSC32Src(osc32_src_t sel)
930{
931 CCM_ANALOG->OSC_MISC_CFG = (CCM_ANALOG->OSC_MISC_CFG & (~CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK)) | (uint32_t)sel;
932}
933
934/*!
935 * @name CCM Gate Control
936 * @{
937 */
938
939/*!
940 * @brief Set PLL or CCGR gate control
941 *
942 * @param ccmGate Gate control (see @ref clock_pll_gate_t and @ref clock_ip_name_t enumeration)
943 * @param control Gate control value (see @ref clock_gate_value_t)
944 */
945static inline void CLOCK_ControlGate(uint32_t ccmGate, clock_gate_value_t control)
946{
947 CCM_REG(ccmGate) = (uint32_t)control;
948}
949
950/*!
951 * @brief Enable CCGR clock gate and root clock gate for each module
952 * User should set specific gate for each module according to the description
953 * of the table of system clocks, gating and override in CCM chapter of
954 * reference manual. Take care of that one module may need to set more than
955 * one clock gate.
956 *
957 * @param ccmGate Gate control for each module (see @ref clock_ip_name_t enumeration).
958 */
959void CLOCK_EnableClock(clock_ip_name_t ccmGate);
960
961/*!
962 * @brief Disable CCGR clock gate for the each module
963 * User should set specific gate for each module according to the description
964 * of the table of system clocks, gating and override in CCM chapter of
965 * reference manual. Take care of that one module may need to set more than
966 * one clock gate.
967 *
968 * @param ccmGate Gate control for each module (see @ref clock_ip_name_t enumeration).
969 */
970void CLOCK_DisableClock(clock_ip_name_t ccmGate);
971
972/*!
973 * @name CCM Analog PLL Operatoin Functions
974 * @{
975 */
976
977/*!
978 * @brief Power up PLL
979 *
980 * @param base CCM_ANALOG base pointer.
981 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
982 */
983static inline void CLOCK_PowerUpPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
984{
985 CCM_ANALOG_TUPLE_REG(base, pllControl) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
986}
987
988/*!
989 * @brief Power down PLL
990 *
991 * @param base CCM_ANALOG base pointer.
992 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
993 */
994static inline void CLOCK_PowerDownPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
995{
996 CCM_ANALOG_TUPLE_REG(base, pllControl) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl);
997}
998
999/*!
1000 * @brief PLL bypass setting
1001 *
1002 * @param base CCM_ANALOG base pointer.
1003 * @param pllControl PLL control name (see ccm_analog_pll_control_t enumeration)
1004 * @param bypass Bypass the PLL.
1005 * - true: Bypass the PLL.
1006 * - false: Do not bypass the PLL.
1007 */
1008static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl, bool bypass)
1009{
1010 if (bypass)
1011 {
1012 CCM_ANALOG_TUPLE_REG(base, pllControl) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl);
1013 }
1014 else
1015 {
1016 CCM_ANALOG_TUPLE_REG(base, pllControl) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
1017 }
1018}
1019
1020/*!
1021 * @brief Check if PLL is bypassed
1022 *
1023 * @param base CCM_ANALOG base pointer.
1024 * @param pllControl PLL control name (see ccm_analog_pll_control_t enumeration)
1025 * @return PLL bypass status.
1026 * - true: The PLL is bypassed.
1027 * - false: The PLL is not bypassed.
1028 */
1029static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl)
1030{
1031 return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl)));
1032}
1033
1034/*!
1035 * @brief Check if PLL clock is locked
1036 *
1037 * @param base CCM_ANALOG base pointer.
1038 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
1039 * @return PLL lock status.
1040 * - true: The PLL clock is locked.
1041 * - false: The PLL clock is not locked.
1042 */
1043static inline bool CLOCK_IsPllLocked(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
1044{
1045 return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_MASK);
1046}
1047
1048/*!
1049 * @brief Enable PLL clock
1050 *
1051 * @param base CCM_ANALOG base pointer.
1052 * @param pllClock PLL clock name (see ccm_analog_pll_clock_t enumeration)
1053 */
1054static inline void CLOCK_EnableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
1055{
1056 CCM_ANALOG_TUPLE_REG(base, pllClock) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllClock);
1057}
1058
1059/*!
1060 * @brief Disable PLL clock
1061 *
1062 * @param base CCM_ANALOG base pointer.
1063 * @param pllClock PLL clock name (see ccm_analog_pll_clock_t enumeration)
1064 */
1065static inline void CLOCK_DisableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
1066{
1067 CCM_ANALOG_TUPLE_REG(base, pllClock) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllClock));
1068}
1069
1070/*!
1071 * @brief Override PLL clock output enable
1072 *
1073 * @param base CCM_ANALOG base pointer.
1074 * @param ovClock PLL clock name (see @ref clock_pll_clke_t enumeration)
1075 * @param override Override the PLL.
1076 * - true: Override the PLL clke, CCM will handle it.
1077 * - false: Do not override the PLL clke.
1078 */
1079static inline void CLOCK_OverrideAnalogClke(CCM_ANALOG_Type *base, clock_pll_clke_t ovClock, bool override)
1080{
1081 if (override)
1082 {
1083 CCM_ANALOG_TUPLE_REG(base, ovClock) |= 1UL << (CCM_ANALOG_TUPLE_SHIFT(ovClock) - 1UL);
1084 }
1085 else
1086 {
1087 CCM_ANALOG_TUPLE_REG(base, ovClock) &= ~(1UL << (CCM_ANALOG_TUPLE_SHIFT(ovClock) - 1UL));
1088 }
1089}
1090
1091/*!
1092 * @brief Override PLL power down
1093 *
1094 * @param base CCM_ANALOG base pointer.
1095 * @param pdClock PLL clock name (see @ref clock_pll_ctrl_t enumeration)
1096 * @param override Override the PLL.
1097 * - true: Override the PLL clke, CCM will handle it.
1098 * - false: Do not override the PLL clke.
1099 */
1100static inline void CLOCK_OverridePllPd(CCM_ANALOG_Type *base, clock_pll_ctrl_t pdClock, bool override)
1101{
1102 if (override)
1103 {
1104 CCM_ANALOG_TUPLE_REG(base, pdClock) |= 1UL << (CCM_ANALOG_TUPLE_SHIFT(pdClock) - 1UL);
1105 }
1106 else
1107 {
1108 CCM_ANALOG_TUPLE_REG(base, pdClock) &= ~(1UL << (CCM_ANALOG_TUPLE_SHIFT(pdClock) - 1UL));
1109 }
1110}
1111
1112/*!
1113 * @brief Initializes the ANALOG ARM PLL.
1114 *
1115 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1116 *
1117 * @note This function can't detect whether the Arm PLL has been enabled and
1118 * used by some IPs.
1119 */
1120void CLOCK_InitArmPll(const ccm_analog_frac_pll_config_t *config);
1121
1122/*!
1123 * @brief De-initialize the ARM PLL.
1124 */
1125void CLOCK_DeinitArmPll(void);
1126
1127/*!
1128 * @brief Initializes the ANALOG SYS PLL1.
1129 *
1130 * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration).
1131 *
1132 * @note This function can't detect whether the SYS PLL has been enabled and
1133 * used by some IPs.
1134 */
1135void CLOCK_InitSysPll1(const ccm_analog_sscg_pll_config_t *config);
1136
1137/*!
1138 * @brief De-initialize the System PLL1.
1139 */
1140void CLOCK_DeinitSysPll1(void);
1141
1142/*!
1143 * @brief Initializes the ANALOG SYS PLL2.
1144 *
1145 * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration).
1146 *
1147 * @note This function can't detect whether the SYS PLL has been enabled and
1148 * used by some IPs.
1149 */
1150void CLOCK_InitSysPll2(const ccm_analog_sscg_pll_config_t *config);
1151
1152/*!
1153 * @brief De-initialize the System PLL2.
1154 */
1155void CLOCK_DeinitSysPll2(void);
1156
1157/*!
1158 * @brief Initializes the ANALOG SYS PLL3.
1159 *
1160 * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration).
1161 *
1162 * @note This function can't detect whether the SYS PLL has been enabled and
1163 * used by some IPs.
1164 */
1165void CLOCK_InitSysPll3(const ccm_analog_sscg_pll_config_t *config);
1166
1167/*!
1168 * @brief De-initialize the System PLL3.
1169 */
1170void CLOCK_DeinitSysPll3(void);
1171
1172/*!
1173 * @brief Initializes the ANALOG DDR PLL.
1174 *
1175 * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration).
1176 *
1177 * @note This function can't detect whether the DDR PLL has been enabled and
1178 * used by some IPs.
1179 */
1180void CLOCK_InitDramPll(const ccm_analog_sscg_pll_config_t *config);
1181
1182/*!
1183 * @brief De-initialize the Dram PLL.
1184 */
1185void CLOCK_DeinitDramPll(void);
1186
1187/*!
1188 * @brief Initializes the ANALOG AUDIO PLL1.
1189 *
1190 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1191 *
1192 * @note This function can't detect whether the AUDIO PLL has been enabled and
1193 * used by some IPs.
1194 */
1195void CLOCK_InitAudioPll1(const ccm_analog_frac_pll_config_t *config);
1196
1197/*!
1198 * @brief De-initialize the Audio PLL1.
1199 */
1200void CLOCK_DeinitAudioPll1(void);
1201
1202/*!
1203 * @brief Initializes the ANALOG AUDIO PLL2.
1204 *
1205 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1206 *
1207 * @note This function can't detect whether the AUDIO PLL has been enabled and
1208 * used by some IPs.
1209 */
1210void CLOCK_InitAudioPll2(const ccm_analog_frac_pll_config_t *config);
1211
1212/*!
1213 * @brief De-initialize the Audio PLL2.
1214 */
1215void CLOCK_DeinitAudioPll2(void);
1216
1217/*!
1218 * @brief Initializes the ANALOG VIDEO PLL1.
1219 *
1220 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1221 *
1222 */
1223void CLOCK_InitVideoPll1(const ccm_analog_frac_pll_config_t *config);
1224
1225/*!
1226 * @brief De-initialize the Video PLL1.
1227 */
1228void CLOCK_DeinitVideoPll1(void);
1229
1230/*!
1231 * @brief Initializes the ANALOG VIDEO PLL2.
1232 *
1233 * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration).
1234 *
1235 * @note This function can't detect whether the VIDEO PLL has been enabled and
1236 * used by some IPs.
1237 */
1238void CLOCK_InitVideoPll2(const ccm_analog_sscg_pll_config_t *config);
1239
1240/*!
1241 * @brief De-initialize the Video PLL2.
1242 */
1243void CLOCK_DeinitVideoPll2(void);
1244
1245/*!
1246 * @brief Initializes the ANALOG SSCG PLL.
1247 *
1248 * @param base CCM ANALOG base address
1249 * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration).
1250 * @param type sscg pll type
1251 *
1252 */
1253void CLOCK_InitSSCGPll(CCM_ANALOG_Type *base, const ccm_analog_sscg_pll_config_t *config, clock_pll_ctrl_t type);
1254
1255/*!
1256 * @brief Get the ANALOG SSCG PLL clock frequency.
1257 *
1258 * @param base CCM ANALOG base address.
1259 * @param type sscg pll type
1260 * @param refClkFreq reference clock frequency
1261 * @param pll1Bypass pll1 bypass flag
1262 *
1263 * @return Clock frequency
1264 */
1265uint32_t CLOCK_GetSSCGPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq, bool pll1Bypass);
1266
1267/*!
1268 * @brief Initializes the ANALOG Fractional PLL.
1269 *
1270 * @param base CCM ANALOG base address.
1271 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1272 * @param type fractional pll type.
1273 *
1274 */
1275void CLOCK_InitFracPll(CCM_ANALOG_Type *base, const ccm_analog_frac_pll_config_t *config, clock_pll_ctrl_t type);
1276
1277/*!
1278 * @brief Gets the ANALOG Fractional PLL clock frequency.
1279 *
1280 * @param base CCM_ANALOG base pointer.
1281 * @param type fractional pll type.
1282 * @param refClkFreq reference clock frequency
1283 *
1284 * @return Clock frequency
1285 */
1286uint32_t CLOCK_GetFracPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq);
1287
1288/*!
1289 * @brief Gets PLL clock frequency.
1290 *
1291 * @param pll fractional pll type.
1292
1293 * @return Clock frequency
1294 */
1295uint32_t CLOCK_GetPllFreq(clock_pll_ctrl_t pll);
1296
1297/*!
1298 * @brief Gets PLL reference clock frequency.
1299 *
1300 * @param ctrl fractional pll type.
1301
1302 * @return Clock frequency
1303 */
1304uint32_t CLOCK_GetPllRefClkFreq(clock_pll_ctrl_t ctrl);
1305
1306/*!
1307 * @name CCM Get frequency
1308 * @{
1309 */
1310
1311/*!
1312 * @brief Gets the clock frequency for a specific clock name.
1313 *
1314 * This function checks the current clock configurations and then calculates
1315 * the clock frequency for a specific clock name defined in clock_name_t.
1316 *
1317 * @param clockName Clock names defined in clock_name_t
1318 * @return Clock frequency value in hertz
1319 */
1320uint32_t CLOCK_GetFreq(clock_name_t clockName);
1321
1322/*!
1323 * @brief Get the CCM Cortex M4 core frequency.
1324 *
1325 * @return Clock frequency; If the clock is invalid, returns 0.
1326 */
1327uint32_t CLOCK_GetCoreM4Freq(void);
1328
1329/*!
1330 * @brief Get the CCM Axi bus frequency.
1331 *
1332 * @return Clock frequency; If the clock is invalid, returns 0.
1333 */
1334uint32_t CLOCK_GetAxiFreq(void);
1335
1336/*!
1337 * @brief Get the CCM Ahb bus frequency.
1338 *
1339 * @return Clock frequency; If the clock is invalid, returns 0.
1340 */
1341uint32_t CLOCK_GetAhbFreq(void);
1342
1343/* @} */
1344
1345#if defined(__cplusplus)
1346}
1347#endif
1348/* @} */
1349#endif
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD6/drivers/fsl_iomuxc.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD6/drivers/fsl_iomuxc.h
new file mode 100644
index 000000000..c668299a3
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD6/drivers/fsl_iomuxc.h
@@ -0,0 +1,606 @@
1/*
2 * Copyright 2016 Freescale Semiconductor, Inc.
3 * Copyright 2016-2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8#ifndef _FSL_IOMUXC_H_
9#define _FSL_IOMUXC_H_
10
11#include "fsl_common.h"
12
13/*!
14 * @addtogroup iomuxc_driver
15 * @{
16 */
17
18/*! @file */
19
20/*******************************************************************************
21 * Definitions
22 ******************************************************************************/
23/* Component ID definition, used by tools. */
24#ifndef FSL_COMPONENT_ID
25#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
26#endif
27
28/*! @name Driver version */
29/*@{*/
30/*! @brief IOMUXC driver version 2.0.1. */
31#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
32/*@}*/
33
34/*!
35 * @name Pin function ID
36 * The pin function ID is a tuple of \<muxRegister muxMode inputRegister inputDaisy configRegister\>
37 *
38 * @{
39 */
40#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
41#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
42#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
43#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
44#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
45#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
46#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
47#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
48#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
49#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
50#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
51#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
52#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
53#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
54#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
55#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
56#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
57#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
58#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
59#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
60#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
61#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
62#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
63#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
64#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
65#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
66#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
67#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
68#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
69#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
70#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
71#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
72#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
73#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
74#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
75#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
76#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
77#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
78#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
79#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
80#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
81#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
82#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
83#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
84#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
85#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
86#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
87#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
88#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
89#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
90#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
91#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
92#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
93#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
94#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
95#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
96#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
97#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
98#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
99#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
100#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
101#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
102#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
103#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
104#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
105#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
106#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
107#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
108#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
109#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
110#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
111#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
112#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
113#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
114#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
115#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
116#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
117#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
118#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
119#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
120#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
121#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
122#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
123#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
124#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
125#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
126#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
127#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
128#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
129#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
130#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
131#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
132#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
133#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
134#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
135#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
136#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
137#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
138#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
139#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
140#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
141#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
142#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
143#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
144#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
145#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
146#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
147#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
148#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
149#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
150#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
151#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
152#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
153#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
154#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
155#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
156#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
157#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
158#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
159#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
160#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
161#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
162#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
163#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
164#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
165#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
166#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
167#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
168#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
169#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
170#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
171#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
172#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
173#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
174#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
175#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
176#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
177#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
178#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
179#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
180#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
181#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
182#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
183#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
184#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
185#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
186#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
187#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
188#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
189#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
190#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
191#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
192#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
193#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
194#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
195#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
196#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
197#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
198#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
199#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
200#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
201#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
202#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
203#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
204#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
205#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
206#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
207#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
208#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
209#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
210#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
211#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
212#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
213#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
214#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
215#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
216#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
217#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
218#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
219#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
220#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
221#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
222#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
223#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
224#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
225#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
226#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
227#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
228#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
229#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
230#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
231#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
232#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
233#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
234#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
235#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
236#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
237#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
238#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
239#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
240#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
241#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
242#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
243#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
244#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
245#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
246#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
247#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
248#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
249#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
250#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
251#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0
252#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
253#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
254#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
255#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
256#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
257#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
258#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
259#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
260#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
261#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
262#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
263#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
264#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
265#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
266#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
267#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
268#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
269#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
270#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
271#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
272#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
273#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
274#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
275#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
276#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
277#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
278#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
279#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
280#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
281#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
282#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
283#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
284#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
285#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
286#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
287#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
288#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
289#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
290#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
291#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
292#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
293#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
294#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
295#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
296#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
297#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
298#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
299#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
300#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
301#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
302#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
303#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
304#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
305#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
306#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
307#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
308#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
309#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
310#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
311#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
312#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
313#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
314#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
315#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
316#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
317#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
318#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
319#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
320#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
321#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
322#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
323#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
324#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
325#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
326#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
327#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
328#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
329#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
330#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
331#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
332#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
333#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
334#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
335#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
336#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
337#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
338#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
339#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
340#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
341#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
342#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
343#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
344#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
345#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
346#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
347#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
348#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
349#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
350#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
351#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
352#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
353#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
354#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
355#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
356#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
357#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
358#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
359#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
360#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
361#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
362#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
363#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
364#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
365#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
366#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
367#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
368#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
369#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
370#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
371#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
372#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
373#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
374#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
375#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
376#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
377#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
378#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
379#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
380#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
381#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
382#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
383#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
384#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
385#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
386#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
387#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
388#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
389#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
390#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
391#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
392#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
393#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
394#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
395#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
396#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
397#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
398#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
399#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
400#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
401#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
402#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
403#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
404#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
405#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
406#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
407#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
408#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
409#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
410#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
411#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
412#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
413#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
414#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
415#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
416#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
417#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
418#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
419#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
420#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
421#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
422#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
423#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
424#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
425#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
426#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
427#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
428#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
429#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
430#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
431#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
432#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
433#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
434#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
435#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
436#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
437#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
438#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
439#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
440#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
441#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
442#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
443#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
444#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
445#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
446#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
447#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
448#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
449#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
450#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
451#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
452#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
453#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
454#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
455#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
456#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
457#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
458#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
459#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
460#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
461#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
462#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
463#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
464#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
465#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
466#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
467#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
468#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
469#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
470#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
471#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
472#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
473#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
474#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
475#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
476#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
477#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
478#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498
479#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
480#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
481#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
482#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
483#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
484#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
485#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
486#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
487#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
488#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
489#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
490#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
491#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
492#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
493#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
494#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
495#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
496#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
497#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
498#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
499#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
500#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
501#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
502#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
503#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
504#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
505#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
506#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
507#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
508#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
509#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
510#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
511#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
512#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
513#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
514#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
515#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
516#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8
517#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
518#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
519#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
520#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
521#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
522#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
523#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
524#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
525#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
526#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
527#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
528
529/*@}*/
530
531#if defined(__cplusplus)
532extern "C" {
533#endif /*__cplusplus */
534
535/*! @name Configuration */
536/*@{*/
537
538/*!
539 * @brief Sets the IOMUXC pin mux mode.
540 * @note The first five parameters can be filled with the pin function ID macros.
541 *
542 * This is an example to set the I2C4_SDA as the pwm1_OUT:
543 * @code
544 * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
545 * @endcode
546 *
547 *
548 * @param muxRegister The pin mux register_
549 * @param muxMode The pin mux mode_
550 * @param inputRegister The select input register_
551 * @param inputDaisy The input daisy_
552 * @param configRegister The config register_
553 * @param inputOnfield The pad->module input inversion_
554 */
555static inline void IOMUXC_SetPinMux(uint32_t muxRegister,
556 uint32_t muxMode,
557 uint32_t inputRegister,
558 uint32_t inputDaisy,
559 uint32_t configRegister,
560 uint32_t inputOnfield)
561{
562 *((volatile uint32_t *)muxRegister) =
563 IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
564
565 if (inputRegister)
566 {
567 *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
568 }
569}
570/*!
571 * @brief Sets the IOMUXC pin configuration.
572 * @note The previous five parameters can be filled with the pin function ID macros.
573 *
574 * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
575 * @code
576 * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
577 * @endcode
578 *
579 * @param muxRegister The pin mux register_
580 * @param muxMode The pin mux mode_
581 * @param inputRegister The select input register_
582 * @param inputDaisy The input daisy_
583 * @param configRegister The config register_
584 * @param configValue The pin config value_
585 */
586static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
587 uint32_t muxMode,
588 uint32_t inputRegister,
589 uint32_t inputDaisy,
590 uint32_t configRegister,
591 uint32_t configValue)
592{
593 if (configRegister)
594 {
595 *((volatile uint32_t *)configRegister) = configValue;
596 }
597}
598/*@}*/
599
600#if defined(__cplusplus)
601}
602#endif /*__cplusplus */
603
604/*! @}*/
605
606#endif /* _FSL_IOMUXC_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 08:24:56 +0100