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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/gcc/startup_MIMX8MM6_cm4.S b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/gcc/startup_MIMX8MM6_cm4.S
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index 000000000..6ec82b2b4
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+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/gcc/startup_MIMX8MM6_cm4.S
@@ -0,0 +1,751 @@
1/* ------------------------------------------------------------------------- */
2/* @file: startup_MIMX8MM6_cm4.s */
3/* @purpose: CMSIS Cortex-M4 Core Device Startup File */
4/* MIMX8MM6_cm4 */
5/* @version: 4.0 */
6/* @date: 2019-2-18 */
7/* @build: b190228 */
8/* ------------------------------------------------------------------------- */
9/* */
10/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
11/* Copyright 2016-2019 NXP */
12/* All rights reserved. */
13/* */
14/* SPDX-License-Identifier: BSD-3-Clause */
15/*****************************************************************************/
16/* Version: GCC for ARM Embedded Processors */
17/*****************************************************************************/
18 .syntax unified
19 .arch armv7-m
20
21 .section .isr_vector, "a"
22 .align 2
23 .globl __isr_vector
24__isr_vector:
25 .long __StackTop /* Top of Stack */
26 .long Reset_Handler /* Reset Handler */
27 .long NMI_Handler /* NMI Handler*/
28 .long HardFault_Handler /* Hard Fault Handler*/
29 .long MemManage_Handler /* MPU Fault Handler*/
30 .long BusFault_Handler /* Bus Fault Handler*/
31 .long UsageFault_Handler /* Usage Fault Handler*/
32 .long 0 /* Reserved*/
33 .long 0 /* Reserved*/
34 .long 0 /* Reserved*/
35 .long 0 /* Reserved*/
36 .long SVC_Handler /* SVCall Handler*/
37 .long DebugMon_Handler /* Debug Monitor Handler*/
38 .long 0 /* Reserved*/
39 .long PendSV_Handler /* PendSV Handler*/
40 .long SysTick_Handler /* SysTick Handler*/
41
42 /* External Interrupts*/
43 .long GPR_IRQ_IRQHandler /* GPR Interrupt. Used to notify cores on exception condition while boot.*/
44 .long DAP_IRQHandler /* DAP Interrupt*/
45 .long SDMA1_IRQHandler /* AND of all 48 SDMA1 interrupts (events) from all the channels*/
46 .long GPU3D_IRQHandler /* GPU3D Interrupt*/
47 .long SNVS_IRQHandler /* ON-OFF button press shorter than 5 seconds (pulse event)*/
48 .long LCDIF_IRQHandler /* LCDIF Interrupt*/
49 .long SPDIF1_IRQHandler /* SPDIF1 RZX/TX Interrupt*/
50 .long VPU_G1_IRQHandler /* VPU G1 Decoder Interrupt*/
51 .long VPU_G2_IRQHandler /* VPU G2 Decoder Interrupt*/
52 .long QOS_IRQHandler /* QOS interrupt*/
53 .long WDOG3_IRQHandler /* Watchdog Timer reset*/
54 .long HS_CP1_IRQHandler /* HS Interrupt Request*/
55 .long APBHDMA_IRQHandler /* GPMI operation channel 0-3 description complete interrupt*/
56 .long Reserved29_IRQHandler /* Reserved*/
57 .long BCH_IRQHandler /* BCH operation complete interrupt*/
58 .long GPMI_IRQHandler /* GPMI operation TIMEOUT ERROR interrupt*/
59 .long CSI1_IRQHandler /* CSI Interrupt*/
60 .long MIPI_CSI1_IRQHandler /* MIPI CSI Interrupt*/
61 .long MIPI_DSI_IRQHandler /* MIPI DSI Interrupt*/
62 .long SNVS_Consolidated_IRQHandler /* SRTC Consolidated Interrupt. Non TZ.*/
63 .long SNVS_Security_IRQHandler /* SRTC Security Interrupt. TZ.*/
64 .long CSU_IRQHandler /* CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted.*/
65 .long USDHC1_IRQHandler /* uSDHC1 Enhanced SDHC Interrupt Request*/
66 .long USDHC2_IRQHandler /* uSDHC2 Enhanced SDHC Interrupt Request*/
67 .long USDHC3_IRQHandler /* uSDHC3 Enhanced SDHC Interrupt Request*/
68 .long GPU2D_IRQHandler /* GPU2D Interrupt*/
69 .long UART1_IRQHandler /* UART-1 ORed interrupt*/
70 .long UART2_IRQHandler /* UART-2 ORed interrupt*/
71 .long UART3_IRQHandler /* UART-3 ORed interrupt*/
72 .long UART4_IRQHandler /* UART-4 ORed interrupt*/
73 .long VPU_H1_IRQHandler /* VPU H1 Encoder Interrupt*/
74 .long ECSPI1_IRQHandler /* ECSPI1 interrupt request line to the core.*/
75 .long ECSPI2_IRQHandler /* ECSPI2 interrupt request line to the core.*/
76 .long ECSPI3_IRQHandler /* ECSPI3 interrupt request line to the core.*/
77 .long SDMA3_IRQHandler /* AND of all 48 SDMA3 interrupts (events) from all the channels*/
78 .long I2C1_IRQHandler /* I2C-1 Interrupt*/
79 .long I2C2_IRQHandler /* I2C-2 Interrupt*/
80 .long I2C3_IRQHandler /* I2C-3 Interrupt*/
81 .long I2C4_IRQHandler /* I2C-4 Interrupt*/
82 .long RDC_IRQHandler /* RDC interrupt*/
83 .long USB1_IRQHandler /* USB1 Interrupt*/
84 .long USB2_IRQHandler /* USB1 Interrupt*/
85 .long Reserved58_IRQHandler /* Reserved interrupt*/
86 .long Reserved59_IRQHandler /* Reserved interrupt*/
87 .long PDM_HWVAD_EVENT_IRQHandler /* Digital Microphone interface voice activity detector event interrupt*/
88 .long PDM_HWVAD_ERROR_IRQHandler /* Digital Microphone interface voice activity detector error interrupt*/
89 .long GPT6_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/
90 .long SCTR_IRQ0_IRQHandler /* System Counter Interrupt 0*/
91 .long SCTR_IRQ1_IRQHandler /* System Counter Interrupt 1*/
92 .long TEMPMON_LOW_IRQHandler /* TempSensor (Temperature low alarm).*/
93 .long I2S3_IRQHandler /* SAI3 Receive / Transmit Interrupt*/
94 .long GPT5_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/
95 .long GPT4_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/
96 .long GPT3_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/
97 .long GPT2_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/
98 .long GPT1_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/
99 .long GPIO1_INT7_IRQHandler /* Active HIGH Interrupt from INT7 from GPIO*/
100 .long GPIO1_INT6_IRQHandler /* Active HIGH Interrupt from INT6 from GPIO*/
101 .long GPIO1_INT5_IRQHandler /* Active HIGH Interrupt from INT5 from GPIO*/
102 .long GPIO1_INT4_IRQHandler /* Active HIGH Interrupt from INT4 from GPIO*/
103 .long GPIO1_INT3_IRQHandler /* Active HIGH Interrupt from INT3 from GPIO*/
104 .long GPIO1_INT2_IRQHandler /* Active HIGH Interrupt from INT2 from GPIO*/
105 .long GPIO1_INT1_IRQHandler /* Active HIGH Interrupt from INT1 from GPIO*/
106 .long GPIO1_INT0_IRQHandler /* Active HIGH Interrupt from INT0 from GPIO*/
107 .long GPIO1_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO1 signal 0 throughout 15*/
108 .long GPIO1_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO1 signal 16 throughout 31*/
109 .long GPIO2_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO2 signal 0 throughout 15*/
110 .long GPIO2_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO2 signal 16 throughout 31*/
111 .long GPIO3_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO3 signal 0 throughout 15*/
112 .long GPIO3_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO3 signal 16 throughout 31*/
113 .long GPIO4_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO4 signal 0 throughout 15*/
114 .long GPIO4_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO4 signal 16 throughout 31*/
115 .long GPIO5_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO5 signal 0 throughout 15*/
116 .long GPIO5_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO5 signal 16 throughout 31*/
117 .long Reserved90_IRQHandler /* Reserved interrupt*/
118 .long Reserved91_IRQHandler /* Reserved interrupt*/
119 .long Reserved92_IRQHandler /* Reserved interrupt*/
120 .long Reserved93_IRQHandler /* Reserved interrupt*/
121 .long WDOG1_IRQHandler /* Watchdog Timer reset*/
122 .long WDOG2_IRQHandler /* Watchdog Timer reset*/
123 .long Reserved96_IRQHandler /* Reserved interrupt*/
124 .long PWM1_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/
125 .long PWM2_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/
126 .long PWM3_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/
127 .long PWM4_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/
128 .long CCM_IRQ1_IRQHandler /* CCM Interrupt Request 1*/
129 .long CCM_IRQ2_IRQHandler /* CCM Interrupt Request 2*/
130 .long GPC_IRQHandler /* GPC Interrupt Request 1*/
131 .long MU_A53_IRQHandler /* Interrupt to A53*/
132 .long SRC_IRQHandler /* SRC interrupt request*/
133 .long I2S56_IRQHandler /* SAI5/6 Receive / Transmit Interrupt*/
134 .long RTIC_IRQHandler /* RTIC Interrupt*/
135 .long CPU_PerformanceUnit_IRQHandler /* Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n]*/
136 .long CPU_CTI_Trigger_IRQHandler /* CTI trigger outputs (internal: nCTIIRQ[n]*/
137 .long SRC_Combined_IRQHandler /* Combined CPU wdog interrupts (4x) out of SRC.*/
138 .long I2S1_IRQHandler /* SAI1 Receive / Transmit Interrupt*/
139 .long I2S2_IRQHandler /* SAI2 Receive / Transmit Interrupt*/
140 .long MU_M4_IRQHandler /* Interrupt to M4*/
141 .long DDR_PerformanceMonitor_IRQHandler /* ddr Interrupt for performance monitor*/
142 .long DDR_IRQHandler /* ddr Interrupt*/
143 .long Reserved116_IRQHandler /* Reserved interrupt*/
144 .long CPU_Error_AXI_IRQHandler /* CPU Error indicator for AXI transaction with a write response error condition*/
145 .long CPU_Error_L2RAM_IRQHandler /* CPU Error indicator for L2 RAM double-bit ECC error*/
146 .long SDMA2_IRQHandler /* AND of all 48 SDMA2 interrupts (events) from all the channels*/
147 .long SJC_IRQHandler /* Interrupt triggered by SJC register*/
148 .long CAAM_IRQ0_IRQHandler /* CAAM interrupt queue for JQ*/
149 .long CAAM_IRQ1_IRQHandler /* CAAM interrupt queue for JQ*/
150 .long QSPI_IRQHandler /* QSPI Interrupt*/
151 .long TZASC_IRQHandler /* TZASC (PL380) interrupt*/
152 .long PDM_EVENT_IRQHandler /* Digital Microphone interface interrupt*/
153 .long PDM_ERROR_IRQHandler /* Digital Microphone interface error interrupt*/
154 .long Reserved127_IRQHandler /* Reserved interrupt*/
155 .long PERFMON1_IRQHandler /* General Interrupt*/
156 .long PERFMON2_IRQHandler /* General Interrupt*/
157 .long CAAM_IRQ2_IRQHandler /* CAAM interrupt queue for JQ*/
158 .long CAAM_ERROR_IRQHandler /* Recoverable error interrupt*/
159 .long HS_CP0_IRQHandler /* HS Interrupt Request*/
160 .long Reserved133_IRQHandler /* Reserved interrupt*/
161 .long ENET_MAC0_Rx_Tx_Done1_IRQHandler /* MAC 0 Receive / Trasmit Frame / Buffer Done*/
162 .long ENET_MAC0_Rx_Tx_Done2_IRQHandler /* MAC 0 Receive / Trasmit Frame / Buffer Done*/
163 .long ENET_IRQHandler /* MAC 0 IRQ*/
164 .long ENET_1588_IRQHandler /* MAC 0 1588 Timer Interrupt - synchronous*/
165 .long PCIE_CTRL1_IRQ0_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/
166 .long PCIE_CTRL1_IRQ1_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/
167 .long PCIE_CTRL1_IRQ2_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/
168 .long PCIE_CTRL1_IRQ3_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/
169 .long Reserved142_IRQHandler /* Reserved*/
170 .long PCIE_CTRL1_IRQHandler /* Channels [63:32] interrupts requests*/
171
172 .size __isr_vector, . - __isr_vector
173
174 .text
175 .thumb
176
177/* Reset Handler */
178
179 .thumb_func
180 .align 2
181 .globl Reset_Handler
182 .weak Reset_Handler
183 .type Reset_Handler, %function
184Reset_Handler:
185 cpsid i /* Mask interrupts */
186 .equ VTOR, 0xE000ED08
187 ldr r0, =VTOR
188 ldr r1, =__isr_vector
189 str r1, [r0]
190 ldr r2, [r1]
191 msr msp, r2
192#ifndef __NO_SYSTEM_INIT
193 ldr r0,=SystemInit
194 blx r0
195#endif
196/* Loop to copy data from read only memory to RAM. The ranges
197 * of copy from/to are specified by following symbols evaluated in
198 * linker script.
199 * __etext: End of code section, i.e., begin of data sections to copy from.
200 * __data_start__/__data_end__: RAM address range that data should be
201 * __noncachedata_start__/__noncachedata_end__ : none cachable region
202 * copied to. Both must be aligned to 4 bytes boundary. */
203
204 ldr r1, =__etext
205 ldr r2, =__data_start__
206 ldr r3, =__data_end__
207
208#if 1
209/* Here are two copies of loop implemenations. First one favors code size
210 * and the second one favors performance. Default uses the first one.
211 * Change to "#if 0" to use the second one */
212.LC0:
213 cmp r2, r3
214 ittt lt
215 ldrlt r0, [r1], #4
216 strlt r0, [r2], #4
217 blt .LC0
218#else
219 subs r3, r2
220 ble .LC1
221.LC0:
222 subs r3, #4
223 ldr r0, [r1, r3]
224 str r0, [r2, r3]
225 bgt .LC0
226.LC1:
227#endif
228#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
229 ldr r2, =__noncachedata_start__
230 ldr r3, =__noncachedata_init_end__
231#if 1
232.LC2:
233 cmp r2, r3
234 ittt lt
235 ldrlt r0, [r1], #4
236 strlt r0, [r2], #4
237 blt .LC2
238#else
239 subs r3, r2
240 ble .LC3
241.LC2:
242 subs r3, #4
243 ldr r0, [r1, r3]
244 str r0, [r2, r3]
245 bgt .LC2
246.LC3:
247#endif
248/* zero inited ncache section initialization */
249 ldr r3, =__noncachedata_end__
250 movs r0,0
251.LC4:
252 cmp r2,r3
253 itt lt
254 strlt r0,[r2],#4
255 blt .LC4
256#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */
257
258#ifdef __STARTUP_CLEAR_BSS
259/* This part of work usually is done in C library startup code. Otherwise,
260 * define this macro to enable it in this startup.
261 *
262 * Loop to zero out BSS section, which uses following symbols
263 * in linker script:
264 * __bss_start__: start of BSS section. Must align to 4
265 * __bss_end__: end of BSS section. Must align to 4
266 */
267 ldr r1, =__bss_start__
268 ldr r2, =__bss_end__
269
270 movs r0, 0
271.LC5:
272 cmp r1, r2
273 itt lt
274 strlt r0, [r1], #4
275 blt .LC5
276#endif /* __STARTUP_CLEAR_BSS */
277
278 cpsie i /* Unmask interrupts */
279#ifndef __START
280#define __START _start
281#endif
282#ifndef __ATOLLIC__
283 ldr r0,=__START
284 blx r0
285#else
286 ldr r0,=__libc_init_array
287 blx r0
288 ldr r0,=main
289 bx r0
290#endif
291 .pool
292 .size Reset_Handler, . - Reset_Handler
293
294 .align 1
295 .thumb_func
296 .weak DefaultISR
297 .type DefaultISR, %function
298DefaultISR:
299 b DefaultISR
300 .size DefaultISR, . - DefaultISR
301
302 .align 1
303 .thumb_func
304 .weak NMI_Handler
305 .type NMI_Handler, %function
306NMI_Handler:
307 ldr r0,=NMI_Handler
308 bx r0
309 .size NMI_Handler, . - NMI_Handler
310
311 .align 1
312 .thumb_func
313 .weak HardFault_Handler
314 .type HardFault_Handler, %function
315HardFault_Handler:
316 ldr r0,=HardFault_Handler
317 bx r0
318 .size HardFault_Handler, . - HardFault_Handler
319
320 .align 1
321 .thumb_func
322 .weak SVC_Handler
323 .type SVC_Handler, %function
324SVC_Handler:
325 ldr r0,=SVC_Handler
326 bx r0
327 .size SVC_Handler, . - SVC_Handler
328
329 .align 1
330 .thumb_func
331 .weak PendSV_Handler
332 .type PendSV_Handler, %function
333PendSV_Handler:
334 ldr r0,=PendSV_Handler
335 bx r0
336 .size PendSV_Handler, . - PendSV_Handler
337
338 .align 1
339 .thumb_func
340 .weak SysTick_Handler
341 .type SysTick_Handler, %function
342SysTick_Handler:
343 ldr r0,=SysTick_Handler
344 bx r0
345 .size SysTick_Handler, . - SysTick_Handler
346
347 .align 1
348 .thumb_func
349 .weak SDMA1_IRQHandler
350 .type SDMA1_IRQHandler, %function
351SDMA1_IRQHandler:
352 ldr r0,=SDMA1_DriverIRQHandler
353 bx r0
354 .size SDMA1_IRQHandler, . - SDMA1_IRQHandler
355
356 .align 1
357 .thumb_func
358 .weak SPDIF1_IRQHandler
359 .type SPDIF1_IRQHandler, %function
360SPDIF1_IRQHandler:
361 ldr r0,=SPDIF1_DriverIRQHandler
362 bx r0
363 .size SPDIF1_IRQHandler, . - SPDIF1_IRQHandler
364
365 .align 1
366 .thumb_func
367 .weak APBHDMA_IRQHandler
368 .type APBHDMA_IRQHandler, %function
369APBHDMA_IRQHandler:
370 ldr r0,=APBHDMA_DriverIRQHandler
371 bx r0
372 .size APBHDMA_IRQHandler, . - APBHDMA_IRQHandler
373
374 .align 1
375 .thumb_func
376 .weak USDHC1_IRQHandler
377 .type USDHC1_IRQHandler, %function
378USDHC1_IRQHandler:
379 ldr r0,=USDHC1_DriverIRQHandler
380 bx r0
381 .size USDHC1_IRQHandler, . - USDHC1_IRQHandler
382
383 .align 1
384 .thumb_func
385 .weak USDHC2_IRQHandler
386 .type USDHC2_IRQHandler, %function
387USDHC2_IRQHandler:
388 ldr r0,=USDHC2_DriverIRQHandler
389 bx r0
390 .size USDHC2_IRQHandler, . - USDHC2_IRQHandler
391
392 .align 1
393 .thumb_func
394 .weak USDHC3_IRQHandler
395 .type USDHC3_IRQHandler, %function
396USDHC3_IRQHandler:
397 ldr r0,=USDHC3_DriverIRQHandler
398 bx r0
399 .size USDHC3_IRQHandler, . - USDHC3_IRQHandler
400
401 .align 1
402 .thumb_func
403 .weak UART1_IRQHandler
404 .type UART1_IRQHandler, %function
405UART1_IRQHandler:
406 ldr r0,=UART1_DriverIRQHandler
407 bx r0
408 .size UART1_IRQHandler, . - UART1_IRQHandler
409
410 .align 1
411 .thumb_func
412 .weak UART2_IRQHandler
413 .type UART2_IRQHandler, %function
414UART2_IRQHandler:
415 ldr r0,=UART2_DriverIRQHandler
416 bx r0
417 .size UART2_IRQHandler, . - UART2_IRQHandler
418
419 .align 1
420 .thumb_func
421 .weak UART3_IRQHandler
422 .type UART3_IRQHandler, %function
423UART3_IRQHandler:
424 ldr r0,=UART3_DriverIRQHandler
425 bx r0
426 .size UART3_IRQHandler, . - UART3_IRQHandler
427
428 .align 1
429 .thumb_func
430 .weak UART4_IRQHandler
431 .type UART4_IRQHandler, %function
432UART4_IRQHandler:
433 ldr r0,=UART4_DriverIRQHandler
434 bx r0
435 .size UART4_IRQHandler, . - UART4_IRQHandler
436
437 .align 1
438 .thumb_func
439 .weak ECSPI1_IRQHandler
440 .type ECSPI1_IRQHandler, %function
441ECSPI1_IRQHandler:
442 ldr r0,=ECSPI1_DriverIRQHandler
443 bx r0
444 .size ECSPI1_IRQHandler, . - ECSPI1_IRQHandler
445
446 .align 1
447 .thumb_func
448 .weak ECSPI2_IRQHandler
449 .type ECSPI2_IRQHandler, %function
450ECSPI2_IRQHandler:
451 ldr r0,=ECSPI2_DriverIRQHandler
452 bx r0
453 .size ECSPI2_IRQHandler, . - ECSPI2_IRQHandler
454
455 .align 1
456 .thumb_func
457 .weak ECSPI3_IRQHandler
458 .type ECSPI3_IRQHandler, %function
459ECSPI3_IRQHandler:
460 ldr r0,=ECSPI3_DriverIRQHandler
461 bx r0
462 .size ECSPI3_IRQHandler, . - ECSPI3_IRQHandler
463
464 .align 1
465 .thumb_func
466 .weak SDMA3_IRQHandler
467 .type SDMA3_IRQHandler, %function
468SDMA3_IRQHandler:
469 ldr r0,=SDMA3_DriverIRQHandler
470 bx r0
471 .size SDMA3_IRQHandler, . - SDMA3_IRQHandler
472
473 .align 1
474 .thumb_func
475 .weak I2C1_IRQHandler
476 .type I2C1_IRQHandler, %function
477I2C1_IRQHandler:
478 ldr r0,=I2C1_DriverIRQHandler
479 bx r0
480 .size I2C1_IRQHandler, . - I2C1_IRQHandler
481
482 .align 1
483 .thumb_func
484 .weak I2C2_IRQHandler
485 .type I2C2_IRQHandler, %function
486I2C2_IRQHandler:
487 ldr r0,=I2C2_DriverIRQHandler
488 bx r0
489 .size I2C2_IRQHandler, . - I2C2_IRQHandler
490
491 .align 1
492 .thumb_func
493 .weak I2C3_IRQHandler
494 .type I2C3_IRQHandler, %function
495I2C3_IRQHandler:
496 ldr r0,=I2C3_DriverIRQHandler
497 bx r0
498 .size I2C3_IRQHandler, . - I2C3_IRQHandler
499
500 .align 1
501 .thumb_func
502 .weak I2C4_IRQHandler
503 .type I2C4_IRQHandler, %function
504I2C4_IRQHandler:
505 ldr r0,=I2C4_DriverIRQHandler
506 bx r0
507 .size I2C4_IRQHandler, . - I2C4_IRQHandler
508
509 .align 1
510 .thumb_func
511 .weak I2S3_IRQHandler
512 .type I2S3_IRQHandler, %function
513I2S3_IRQHandler:
514 ldr r0,=I2S3_DriverIRQHandler
515 bx r0
516 .size I2S3_IRQHandler, . - I2S3_IRQHandler
517
518 .align 1
519 .thumb_func
520 .weak I2S56_IRQHandler
521 .type I2S56_IRQHandler, %function
522I2S56_IRQHandler:
523 ldr r0,=I2S56_DriverIRQHandler
524 bx r0
525 .size I2S56_IRQHandler, . - I2S56_IRQHandler
526
527 .align 1
528 .thumb_func
529 .weak I2S1_IRQHandler
530 .type I2S1_IRQHandler, %function
531I2S1_IRQHandler:
532 ldr r0,=I2S1_DriverIRQHandler
533 bx r0
534 .size I2S1_IRQHandler, . - I2S1_IRQHandler
535
536 .align 1
537 .thumb_func
538 .weak I2S2_IRQHandler
539 .type I2S2_IRQHandler, %function
540I2S2_IRQHandler:
541 ldr r0,=I2S2_DriverIRQHandler
542 bx r0
543 .size I2S2_IRQHandler, . - I2S2_IRQHandler
544
545 .align 1
546 .thumb_func
547 .weak SDMA2_IRQHandler
548 .type SDMA2_IRQHandler, %function
549SDMA2_IRQHandler:
550 ldr r0,=SDMA2_DriverIRQHandler
551 bx r0
552 .size SDMA2_IRQHandler, . - SDMA2_IRQHandler
553
554 .align 1
555 .thumb_func
556 .weak QSPI_IRQHandler
557 .type QSPI_IRQHandler, %function
558QSPI_IRQHandler:
559 ldr r0,=QSPI_DriverIRQHandler
560 bx r0
561 .size QSPI_IRQHandler, . - QSPI_IRQHandler
562
563 .align 1
564 .thumb_func
565 .weak PDM_EVENT_IRQHandler
566 .type PDM_EVENT_IRQHandler, %function
567PDM_EVENT_IRQHandler:
568 ldr r0,=PDM_EVENT_DriverIRQHandler
569 bx r0
570 .size PDM_EVENT_IRQHandler, . - PDM_EVENT_IRQHandler
571
572 .align 1
573 .thumb_func
574 .weak ENET_MAC0_Rx_Tx_Done1_IRQHandler
575 .type ENET_MAC0_Rx_Tx_Done1_IRQHandler, %function
576ENET_MAC0_Rx_Tx_Done1_IRQHandler:
577 ldr r0,=ENET_MAC0_Rx_Tx_Done1_DriverIRQHandler
578 bx r0
579 .size ENET_MAC0_Rx_Tx_Done1_IRQHandler, . - ENET_MAC0_Rx_Tx_Done1_IRQHandler
580
581 .align 1
582 .thumb_func
583 .weak ENET_MAC0_Rx_Tx_Done2_IRQHandler
584 .type ENET_MAC0_Rx_Tx_Done2_IRQHandler, %function
585ENET_MAC0_Rx_Tx_Done2_IRQHandler:
586 ldr r0,=ENET_MAC0_Rx_Tx_Done2_DriverIRQHandler
587 bx r0
588 .size ENET_MAC0_Rx_Tx_Done2_IRQHandler, . - ENET_MAC0_Rx_Tx_Done2_IRQHandler
589
590 .align 1
591 .thumb_func
592 .weak ENET_IRQHandler
593 .type ENET_IRQHandler, %function
594ENET_IRQHandler:
595 ldr r0,=ENET_DriverIRQHandler
596 bx r0
597 .size ENET_IRQHandler, . - ENET_IRQHandler
598
599 .align 1
600 .thumb_func
601 .weak ENET_1588_IRQHandler
602 .type ENET_1588_IRQHandler, %function
603ENET_1588_IRQHandler:
604 ldr r0,=ENET_1588_DriverIRQHandler
605 bx r0
606 .size ENET_1588_IRQHandler, . - ENET_1588_IRQHandler
607
608
609/* Macro to define default handlers. Default handler
610 * will be weak symbol and just dead loops. They can be
611 * overwritten by other handlers */
612 .macro def_irq_handler handler_name
613 .weak \handler_name
614 .set \handler_name, DefaultISR
615 .endm
616
617/* Exception Handlers */
618 def_irq_handler MemManage_Handler
619 def_irq_handler BusFault_Handler
620 def_irq_handler UsageFault_Handler
621 def_irq_handler DebugMon_Handler
622 def_irq_handler GPR_IRQ_IRQHandler
623 def_irq_handler DAP_IRQHandler
624 def_irq_handler SDMA1_DriverIRQHandler
625 def_irq_handler GPU3D_IRQHandler
626 def_irq_handler SNVS_IRQHandler
627 def_irq_handler LCDIF_IRQHandler
628 def_irq_handler SPDIF1_DriverIRQHandler
629 def_irq_handler VPU_G1_IRQHandler
630 def_irq_handler VPU_G2_IRQHandler
631 def_irq_handler QOS_IRQHandler
632 def_irq_handler WDOG3_IRQHandler
633 def_irq_handler HS_CP1_IRQHandler
634 def_irq_handler APBHDMA_DriverIRQHandler
635 def_irq_handler Reserved29_IRQHandler
636 def_irq_handler BCH_IRQHandler
637 def_irq_handler GPMI_IRQHandler
638 def_irq_handler CSI1_IRQHandler
639 def_irq_handler MIPI_CSI1_IRQHandler
640 def_irq_handler MIPI_DSI_IRQHandler
641 def_irq_handler SNVS_Consolidated_IRQHandler
642 def_irq_handler SNVS_Security_IRQHandler
643 def_irq_handler CSU_IRQHandler
644 def_irq_handler USDHC1_DriverIRQHandler
645 def_irq_handler USDHC2_DriverIRQHandler
646 def_irq_handler USDHC3_DriverIRQHandler
647 def_irq_handler GPU2D_IRQHandler
648 def_irq_handler UART1_DriverIRQHandler
649 def_irq_handler UART2_DriverIRQHandler
650 def_irq_handler UART3_DriverIRQHandler
651 def_irq_handler UART4_DriverIRQHandler
652 def_irq_handler VPU_H1_IRQHandler
653 def_irq_handler ECSPI1_DriverIRQHandler
654 def_irq_handler ECSPI2_DriverIRQHandler
655 def_irq_handler ECSPI3_DriverIRQHandler
656 def_irq_handler SDMA3_DriverIRQHandler
657 def_irq_handler I2C1_DriverIRQHandler
658 def_irq_handler I2C2_DriverIRQHandler
659 def_irq_handler I2C3_DriverIRQHandler
660 def_irq_handler I2C4_DriverIRQHandler
661 def_irq_handler RDC_IRQHandler
662 def_irq_handler USB1_IRQHandler
663 def_irq_handler USB2_IRQHandler
664 def_irq_handler Reserved58_IRQHandler
665 def_irq_handler Reserved59_IRQHandler
666 def_irq_handler PDM_HWVAD_EVENT_IRQHandler
667 def_irq_handler PDM_HWVAD_ERROR_IRQHandler
668 def_irq_handler GPT6_IRQHandler
669 def_irq_handler SCTR_IRQ0_IRQHandler
670 def_irq_handler SCTR_IRQ1_IRQHandler
671 def_irq_handler TEMPMON_LOW_IRQHandler
672 def_irq_handler I2S3_DriverIRQHandler
673 def_irq_handler GPT5_IRQHandler
674 def_irq_handler GPT4_IRQHandler
675 def_irq_handler GPT3_IRQHandler
676 def_irq_handler GPT2_IRQHandler
677 def_irq_handler GPT1_IRQHandler
678 def_irq_handler GPIO1_INT7_IRQHandler
679 def_irq_handler GPIO1_INT6_IRQHandler
680 def_irq_handler GPIO1_INT5_IRQHandler
681 def_irq_handler GPIO1_INT4_IRQHandler
682 def_irq_handler GPIO1_INT3_IRQHandler
683 def_irq_handler GPIO1_INT2_IRQHandler
684 def_irq_handler GPIO1_INT1_IRQHandler
685 def_irq_handler GPIO1_INT0_IRQHandler
686 def_irq_handler GPIO1_Combined_0_15_IRQHandler
687 def_irq_handler GPIO1_Combined_16_31_IRQHandler
688 def_irq_handler GPIO2_Combined_0_15_IRQHandler
689 def_irq_handler GPIO2_Combined_16_31_IRQHandler
690 def_irq_handler GPIO3_Combined_0_15_IRQHandler
691 def_irq_handler GPIO3_Combined_16_31_IRQHandler
692 def_irq_handler GPIO4_Combined_0_15_IRQHandler
693 def_irq_handler GPIO4_Combined_16_31_IRQHandler
694 def_irq_handler GPIO5_Combined_0_15_IRQHandler
695 def_irq_handler GPIO5_Combined_16_31_IRQHandler
696 def_irq_handler Reserved90_IRQHandler
697 def_irq_handler Reserved91_IRQHandler
698 def_irq_handler Reserved92_IRQHandler
699 def_irq_handler Reserved93_IRQHandler
700 def_irq_handler WDOG1_IRQHandler
701 def_irq_handler WDOG2_IRQHandler
702 def_irq_handler Reserved96_IRQHandler
703 def_irq_handler PWM1_IRQHandler
704 def_irq_handler PWM2_IRQHandler
705 def_irq_handler PWM3_IRQHandler
706 def_irq_handler PWM4_IRQHandler
707 def_irq_handler CCM_IRQ1_IRQHandler
708 def_irq_handler CCM_IRQ2_IRQHandler
709 def_irq_handler GPC_IRQHandler
710 def_irq_handler MU_A53_IRQHandler
711 def_irq_handler SRC_IRQHandler
712 def_irq_handler I2S56_DriverIRQHandler
713 def_irq_handler RTIC_IRQHandler
714 def_irq_handler CPU_PerformanceUnit_IRQHandler
715 def_irq_handler CPU_CTI_Trigger_IRQHandler
716 def_irq_handler SRC_Combined_IRQHandler
717 def_irq_handler I2S1_DriverIRQHandler
718 def_irq_handler I2S2_DriverIRQHandler
719 def_irq_handler MU_M4_IRQHandler
720 def_irq_handler DDR_PerformanceMonitor_IRQHandler
721 def_irq_handler DDR_IRQHandler
722 def_irq_handler Reserved116_IRQHandler
723 def_irq_handler CPU_Error_AXI_IRQHandler
724 def_irq_handler CPU_Error_L2RAM_IRQHandler
725 def_irq_handler SDMA2_DriverIRQHandler
726 def_irq_handler SJC_IRQHandler
727 def_irq_handler CAAM_IRQ0_IRQHandler
728 def_irq_handler CAAM_IRQ1_IRQHandler
729 def_irq_handler QSPI_DriverIRQHandler
730 def_irq_handler TZASC_IRQHandler
731 def_irq_handler PDM_EVENT_DriverIRQHandler
732 def_irq_handler PDM_ERROR_IRQHandler
733 def_irq_handler Reserved127_IRQHandler
734 def_irq_handler PERFMON1_IRQHandler
735 def_irq_handler PERFMON2_IRQHandler
736 def_irq_handler CAAM_IRQ2_IRQHandler
737 def_irq_handler CAAM_ERROR_IRQHandler
738 def_irq_handler HS_CP0_IRQHandler
739 def_irq_handler Reserved133_IRQHandler
740 def_irq_handler ENET_MAC0_Rx_Tx_Done1_DriverIRQHandler
741 def_irq_handler ENET_MAC0_Rx_Tx_Done2_DriverIRQHandler
742 def_irq_handler ENET_DriverIRQHandler
743 def_irq_handler ENET_1588_DriverIRQHandler
744 def_irq_handler PCIE_CTRL1_IRQ0_IRQHandler
745 def_irq_handler PCIE_CTRL1_IRQ1_IRQHandler
746 def_irq_handler PCIE_CTRL1_IRQ2_IRQHandler
747 def_irq_handler PCIE_CTRL1_IRQ3_IRQHandler
748 def_irq_handler Reserved142_IRQHandler
749 def_irq_handler PCIE_CTRL1_IRQHandler
750
751 .end
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 21:54:27 +0100