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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/board.c180
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/board.h48
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/clock_config.c119
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/clock_config.h27
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/peripherals.c24
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/peripherals.h24
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/pin_mux.c69
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/pin_mux.h56
8 files changed, 547 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/board.c
new file mode 100644
index 000000000..693f36c49
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/board.c
@@ -0,0 +1,180 @@
1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "fsl_debug_console.h"
10#include "fsl_rdc.h"
11#include "fsl_iomuxc.h"
12#include "pin_mux.h"
13#include "board.h"
14#include "fsl_clock.h"
15/*******************************************************************************
16 * Variables
17 ******************************************************************************/
18
19/*******************************************************************************
20 * Code
21 ******************************************************************************/
22/* Initialize debug console. */
23void BOARD_InitDebugConsole(void)
24{
25 uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
26 CLOCK_EnableClock(kCLOCK_Uart4);
27 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
28}
29/* Initialize MPU, configure non-cacheable memory */
30void BOARD_InitMemory(void)
31{
32#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
33 extern uint32_t Load$$LR$$LR_cache_region$$Base[];
34 extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
35 uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
36 uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
37#else
38 extern uint32_t __CACHE_REGION_START[];
39 extern uint32_t __CACHE_REGION_SIZE[];
40 uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
41 uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
42#endif
43 uint32_t i = 0;
44 /* Make sure outstanding transfers are done. */
45 __DMB();
46 /* Disable the MPU. */
47 MPU->CTRL = 0;
48
49 /*
50 * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
51 * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
52 * change the default memory attributes.
53 * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
54 * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
55 * 0x27FFFFFF) to use the
56 * background memory attributes.
57 */
58
59 /* Select Region 0 and set its base address to the M4 code bus start address. */
60 MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
61
62 /* Region 0 setting:
63 * 1) Disable Instruction Access;
64 * 2) AP = 011b, full access;
65 * 3) Non-shared device;
66 * 4) Region Not Shared;
67 * 5) Sub-Region 0,1 Disabled;
68 * 6) MPU Protection Region size = 512M byte;
69 * 7) Enable Region 0.
70 */
71 MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
72 (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
73
74 /*
75 * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
76 * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
77 * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
78 * region size,
79 * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
80 * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
81 * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
82 * needs.
83 */
84
85 /* Select Region 1 and set its base address to the DDR start address. */
86 MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
87
88 /* Region 1 setting:
89 * 1) Enable Instruction Access;
90 * 2) AP = 011b, full access;
91 * 3) Shared Device;
92 * 4) MPU Protection Region size = 1024M byte;
93 * 5) Enable Region 1.
94 */
95 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
96
97 /* Select Region 2 and set its base address to the DDR start address. */
98 MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
99
100 /* Region 2 setting:
101 * 1) Enable Instruction Access;
102 * 2) AP = 011b, full access;
103 * 3) Shared Device;
104 * 4) MPU Protection Region size = 1024M byte;
105 * 5) Enable Region 2.
106 */
107 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
108
109 while ((size >> i) > 0x1U)
110 {
111 i++;
112 }
113
114 /* If run on DDR, configure text and data section to be cacheable */
115 if (i != 0)
116 {
117 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
118 assert((size & (size - 1)) == 0);
119 assert(!(cacheStart % size));
120 assert(size == (uint32_t)(1 << i));
121 assert(i >= 5);
122
123 /* Select Region 3 and set its base address to the cache able region start address. */
124 MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
125
126 /* Region 3 setting:
127 * 1) Enable Instruction Access;
128 * 2) AP = 011b, full access;
129 * 3) Outer and inner Cacheable, write and read allocate;
130 * 4) Region Not Shared;
131 * 5) All Sub-Region Enabled;
132 * 6) MPU Protection Region size get from linker file;
133 * 7) Enable Region 3.
134 */
135 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
136 (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
137 }
138
139 /* Enable Privileged default memory map and the MPU. */
140 MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
141 /* Memory barriers to ensure subsequence data & instruction
142 * transfers using updated MPU settings.
143 */
144 __DSB();
145 __ISB();
146}
147
148void BOARD_RdcInit(void)
149{
150 /* Move M4 core to specific RDC domain 1 */
151 rdc_domain_assignment_t assignment = {0};
152
153 assignment.domainId = BOARD_DOMAIN_ID;
154 RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
155
156 /*
157 * The M4 core is running at domain 1, enable clock gate for Iomux to run at domain 1.
158 */
159 CLOCK_EnableClock(kCLOCK_Iomux0);
160 CLOCK_EnableClock(kCLOCK_Iomux1);
161 CLOCK_EnableClock(kCLOCK_Iomux2);
162 CLOCK_EnableClock(kCLOCK_Iomux3);
163 CLOCK_EnableClock(kCLOCK_Iomux4);
164
165 /*
166 * The M4 core is running at domain 1, enable the QSPI clock sources to domain 1 for flash target.
167 */
168#if defined(FLASH_TARGET)
169 CLOCK_EnableClock(kCLOCK_Qspi);
170#endif
171 /*
172 * The M4 core is running at domain 1, enable the PLL clock sources to domain 1.
173 */
174 CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enabel SysPLL1 to Domain 1 */
175 CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable SysPLL2 to Domain 1 */
176 CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable SysPLL3 to Domain 1 */
177 CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable AudioPLL1 to Domain 1 */
178 CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable AudioPLL2 to Domain 1 */
179 CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable VideoPLL1 to Domain 1 */
180}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/board.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/board.h
new file mode 100644
index 000000000..e078d8c4f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/board.h
@@ -0,0 +1,48 @@
1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _BOARD_H_
9#define _BOARD_H_
10#include "clock_config.h"
11#include "fsl_clock.h"
12/*******************************************************************************
13 * Definitions
14 ******************************************************************************/
15/*! @brief The board name */
16#define BOARD_NAME "MIMX8MM-EVK"
17#define MANUFACTURER_NAME "NXP"
18#define BOARD_DOMAIN_ID (1)
19/* The UART to use for debug messages. */
20#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
21#define BOARD_DEBUG_UART_BAUDRATE 115200u
22#define BOARD_DEBUG_UART_BASEADDR UART4_BASE
23#define BOARD_DEBUG_UART_INSTANCE 4U
24#define BOARD_DEBUG_UART_CLK_FREQ \
25 CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart4)) / \
26 (CLOCK_GetRootPostDivider(kCLOCK_RootUart4)) / 10
27#define BOARD_UART_IRQ UART4_IRQn
28#define BOARD_UART_IRQ_HANDLER UART4_IRQHandler
29
30#define BOARD_GPC_BASEADDR GPC
31#define BOARD_MU_IRQ_NUM MU_M4_IRQn
32#if defined(__cplusplus)
33extern "C" {
34#endif /* __cplusplus */
35
36/*******************************************************************************
37 * API
38 ******************************************************************************/
39
40void BOARD_InitDebugConsole(void);
41void BOARD_InitMemory(void);
42void BOARD_RdcInit(void);
43
44#if defined(__cplusplus)
45}
46#endif /* __cplusplus */
47
48#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/clock_config.c
new file mode 100644
index 000000000..584eb138b
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/clock_config.c
@@ -0,0 +1,119 @@
1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "clock_config.h"
10
11/*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
15/* AUDIO PLL1 configuration */
16const ccm_analog_frac_pll_config_t g_audioPll1Config = {
17 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
18 .mainDiv = 655U,
19 .dsm = 23593U,
20 .preDiv = 5U,
21 .postDiv = 2U, /*!< AUDIO PLL1 frequency = 786432000HZ */
22};
23
24/* AUDIO PLL2 configuration */
25const ccm_analog_frac_pll_config_t g_audioPll2Config = {
26 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
27 .mainDiv = 301U,
28 .dsm = 3670U,
29 .preDiv = 5U,
30 .postDiv = 1U, /*!< AUDIO PLL2 frequency = 722534399HZ */
31};
32
33/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
34/* SYSTEM PLL1 configuration */
35const ccm_analog_integer_pll_config_t g_sysPll1Config = {
36 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
37 .mainDiv = 400U,
38 .preDiv = 3U,
39 .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
40};
41
42/* SYSTEM PLL2 configuration */
43const ccm_analog_integer_pll_config_t g_sysPll2Config = {
44 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
45 .mainDiv = 250U,
46 .preDiv = 3U,
47 .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
48};
49
50/* SYSTEM PLL3 configuration */
51const ccm_analog_integer_pll_config_t g_sysPll3Config = {
52 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
53 .mainDiv = 250,
54 .preDiv = 2U,
55 .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
56};
57
58/*******************************************************************************
59 * Variables
60 ******************************************************************************/
61
62/*******************************************************************************
63 * Code
64 ******************************************************************************/
65void BOARD_BootClockRUN(void)
66{
67 /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
68 * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
69 * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
70 * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
71 * the SOC hang.
72 */
73
74 /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
75 CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
76 // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
77 /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
78 // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
79 CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
80
81 // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
82 // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
83 // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
84
85 CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 786432000HZ */
86 CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 722534399HZ */
87
88 CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
89 CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
90
91 // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
92
93 CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
94 CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
95
96 CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
97 CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
98
99 // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
100 // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
101
102 CLOCK_SetRootMux(kCLOCK_RootUart4, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
103 CLOCK_SetRootDivider(kCLOCK_RootUart4, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
104
105 CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
106 /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
107 * enters the low power status.*/
108 CLOCK_EnableClock(kCLOCK_Sim_display);
109 CLOCK_EnableClock(kCLOCK_Sim_m);
110 CLOCK_EnableClock(kCLOCK_Sim_main);
111 CLOCK_EnableClock(kCLOCK_Sim_s);
112 CLOCK_EnableClock(kCLOCK_Sim_wakeup);
113 CLOCK_EnableClock(kCLOCK_Debug);
114 CLOCK_EnableClock(kCLOCK_Dram);
115 CLOCK_EnableClock(kCLOCK_Sec_Debug);
116
117 /* Update core clock */
118 SystemCoreClockUpdate();
119}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/clock_config.h
@@ -0,0 +1,27 @@
1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7#ifndef _CLOCK_CONFIG_H_
8#define _CLOCK_CONFIG_H_
9
10/*******************************************************************************
11 * Definitions
12 ******************************************************************************/
13
14/*******************************************************************************
15 * API
16 ******************************************************************************/
17#if defined(__cplusplus)
18extern "C" {
19#endif /* __cplusplus*/
20
21void BOARD_BootClockRUN(void);
22
23#if defined(__cplusplus)
24}
25#endif /* __cplusplus*/
26
27#endif /* _CLOCK_CONFIG_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/peripherals.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/peripherals.c
new file mode 100644
index 000000000..c6db6966f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/peripherals.c
@@ -0,0 +1,24 @@
1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 */
8
9/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
10!!GlobalInfo
11product: Peripherals v1.0
12 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
13
14/*******************************************************************************
15 * Included files
16 ******************************************************************************/
17#include "peripherals.h"
18
19/*******************************************************************************
20 * BOARD_InitBootPeripherals function
21 ******************************************************************************/
22void BOARD_InitBootPeripherals(void)
23{
24}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/peripherals.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/peripherals.h
new file mode 100644
index 000000000..aa53cd347
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/peripherals.h
@@ -0,0 +1,24 @@
1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 */
8
9#ifndef _PERIPHERALS_H_
10#define _PERIPHERALS_H_
11
12#if defined(__cplusplus)
13extern "C" {
14#endif /*_cplusplus. */
15 /*******************************************************************************
16 * BOARD_InitBootPeripherals function
17 ******************************************************************************/
18void BOARD_InitBootPeripherals(void);
19
20#if defined(__cplusplus)
21}
22#endif /*_cplusplus. */
23
24#endif /* _PERIPHERALS_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/pin_mux.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/pin_mux.c
new file mode 100644
index 000000000..93c0c3c93
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/pin_mux.c
@@ -0,0 +1,69 @@
1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 */
8
9
10/***********************************************************************************************************************
11 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
12 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
13 **********************************************************************************************************************/
14
15/*
16 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
17!!GlobalInfo
18product: Pins v4.1
19processor: MIMX8MM6xxxLZ
20package_id: MIMX8MM6DVTLZ
21mcu_data: ksdk2_0
22processor_version: 0.0.0
23 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
24 */
25
26#include "fsl_common.h"
27#include "fsl_iomuxc.h"
28#include "pin_mux.h"
29
30/* FUNCTION ************************************************************************************************************
31 *
32 * Function Name : BOARD_InitBootPins
33 * Description : Calls initialization functions.
34 *
35 * END ****************************************************************************************************************/
36void BOARD_InitBootPins(void)
37{
38}
39
40/*
41 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
42BOARD_InitPins:
43- options: {callFromInitBoot: 'false', coreID: m4}
44- pin_list:
45 - {pin_num: F19, peripheral: UART4, signal: uart_rx, pin_signal: UART4_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
46 - {pin_num: F18, peripheral: UART4, signal: uart_tx, pin_signal: UART4_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
47 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
48 */
49
50/* FUNCTION ************************************************************************************************************
51 *
52 * Function Name : BOARD_InitPins
53 * Description : Configures pin routing and optionally pin electrical features.
54 *
55 * END ****************************************************************************************************************/
56void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
57 IOMUXC_SetPinMux(IOMUXC_UART4_RXD_UART4_RX, 0U);
58 IOMUXC_SetPinConfig(IOMUXC_UART4_RXD_UART4_RX,
59 IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
60 IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
61 IOMUXC_SetPinMux(IOMUXC_UART4_TXD_UART4_TX, 0U);
62 IOMUXC_SetPinConfig(IOMUXC_UART4_TXD_UART4_TX,
63 IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
64 IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
65}
66
67/***********************************************************************************************************************
68 * EOF
69 **********************************************************************************************************************/
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/pin_mux.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/pin_mux.h
new file mode 100644
index 000000000..1d906205a
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM6/project_template/pin_mux.h
@@ -0,0 +1,56 @@
1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 */
8
9
10#ifndef _PIN_MUX_H_
11#define _PIN_MUX_H_
12
13#include "board.h"
14
15/***********************************************************************************************************************
16 * Definitions
17 **********************************************************************************************************************/
18
19/*!
20 * @addtogroup pin_mux
21 * @{
22 */
23
24/***********************************************************************************************************************
25 * API
26 **********************************************************************************************************************/
27
28#if defined(__cplusplus)
29extern "C" {
30#endif
31
32
33/*!
34 * @brief Calls initialization functions.
35 *
36 */
37void BOARD_InitBootPins(void);
38
39/*!
40 * @brief Configures pin routing and optionally pin electrical features.
41 *
42 */
43void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
44
45#if defined(__cplusplus)
46}
47#endif
48
49/*!
50 * @}
51 */
52#endif /* _PIN_MUX_H_ */
53
54/***********************************************************************************************************************
55 * EOF
56 **********************************************************************************************************************/
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 21:12:02 +0100