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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN1/system_MIMX8MN1_cm7.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN1/system_MIMX8MN1_cm7.c
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1/*
2** ###################################################################
3** Processors: MIMX8MN1CVTIZ
4** MIMX8MN1DVTJZ
5**
6** Compilers: GNU C Compiler
7** IAR ANSI C/C++ Compiler for ARM
8** Keil ARM C/C++ Compiler
9**
10** Reference manual: MX8MNRM, Rev.A, 04/2019
11** Version: rev. 2.0, 2019-09-23
12** Build: b190830
13**
14** Abstract:
15** Provides a system configuration function and a global variable that
16** contains the system frequency. It configures the device and initializes
17** the oscillator (PLL) that is part of the microcontroller device.
18**
19** Copyright 2016 Freescale Semiconductor, Inc.
20** Copyright 2016-2019 NXP
21** All rights reserved.
22**
23** SPDX-License-Identifier: BSD-3-Clause
24**
25** http: www.nxp.com
26** mail: [email protected]
27**
28** Revisions:
29** - rev. 1.0 (2019-04-22)
30** Initial version.
31** - rev. 2.0 (2019-09-23)
32** Rev.B Header RFP
33**
34** ###################################################################
35*/
36
37/*!
38 * @file MIMX8MN1_cm7
39 * @version 2.0
40 * @date 2019-09-23
41 * @brief Device specific configuration file for MIMX8MN1_cm7 (implementation
42 * file)
43 *
44 * Provides a system configuration function and a global variable that contains
45 * the system frequency. It configures the device and initializes the oscillator
46 * (PLL) that is part of the microcontroller device.
47 */
48
49#include <stdint.h>
50#include "fsl_device_registers.h"
51
52/*!
53 * @brief CCM reg macros to extract corresponding registers bit field.
54 */
55#define CCM_BIT_FIELD_VAL(val, mask, shift) (((val)&mask) >> shift)
56
57/*!
58 * @brief CCM reg macros to get corresponding registers values.
59 */
60#define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off))))
61
62/*******************************************************************************
63 * Prototypes
64 ******************************************************************************/
65uint32_t GetFracPllFreq(const volatile uint32_t *base);
66uint32_t GetIntegerPllFreq(const volatile uint32_t *base);
67
68uint32_t GetFracPllFreq(const volatile uint32_t *base)
69{
70 uint32_t fracCfg0 = CCM_ANALOG_REG_VAL(base, 0U);
71 uint32_t fracCfg1 = CCM_ANALOG_REG_VAL(base, 4U);
72 uint32_t fracCfg2 = CCM_ANALOG_REG_VAL(base, 8U);
73 uint32_t refClkFreq = 0U;
74 uint64_t fracClk = 0U;
75
76 uint8_t refSel = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK,
77 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT);
78 uint32_t mainDiv = CCM_BIT_FIELD_VAL(fracCfg1, CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK,
79 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT);
80 uint8_t preDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg1, CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK,
81 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT);
82 uint8_t postDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg1, CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK,
83 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT);
84 uint32_t dsm = CCM_BIT_FIELD_VAL(fracCfg2, CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_MASK,
85 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT);
86
87 if (refSel == 0U) /* OSC 24M Clock */
88 {
89 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ;
90 }
91 else
92 {
93 refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it could be set at
94 system_MIMX8MNx_cm7.h :96 */
95 }
96 fracClk = (uint64_t)refClkFreq * ((uint64_t)mainDiv * 65536UL + (uint64_t)dsm) /
97 ((uint64_t)65536UL * preDiv * (1UL << postDiv));
98
99 return (uint32_t)fracClk;
100}
101
102uint32_t GetIntegerPllFreq(const volatile uint32_t *base)
103{
104 uint32_t integerCfg0 = CCM_ANALOG_REG_VAL(base, 0U);
105 uint32_t integerCfg1 = CCM_ANALOG_REG_VAL(base, 4U);
106 uint32_t refClkFreq = 0U;
107 uint64_t pllOutClock = 0U;
108
109 uint8_t pllBypass = (uint8_t)CCM_BIT_FIELD_VAL(integerCfg0, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_MASK,
110 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT);
111 uint8_t refSel = (uint8_t)CCM_BIT_FIELD_VAL(integerCfg0, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK,
112 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT);
113 uint32_t mainDiv = CCM_BIT_FIELD_VAL(integerCfg1, CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK,
114 CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT);
115 uint8_t preDiv = (uint8_t)CCM_BIT_FIELD_VAL(integerCfg1, CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK,
116 CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT);
117 uint8_t postDiv = (uint8_t)CCM_BIT_FIELD_VAL(integerCfg1, CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK,
118 CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT);
119
120 if (refSel == 0U) /* OSC 24M Clock */
121 {
122 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ;
123 }
124 else
125 {
126 refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it could be set at
127 system_MIMX8MNx_cm7.h :96 */
128 }
129
130 if (pllBypass != 0U)
131 {
132 pllOutClock = refClkFreq;
133 }
134
135 else
136 {
137 pllOutClock = (uint64_t)refClkFreq * mainDiv / (((uint64_t)(1U) << postDiv) * preDiv);
138 }
139
140 return (uint32_t)pllOutClock;
141}
142
143/* ----------------------------------------------------------------------------
144 -- Core clock
145 ---------------------------------------------------------------------------- */
146
147uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
148
149/* ----------------------------------------------------------------------------
150 -- SystemInit()
151 ---------------------------------------------------------------------------- */
152
153void SystemInit(void)
154{
155#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
156 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
157#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
158
159 SystemInitHook();
160}
161
162/* ----------------------------------------------------------------------------
163 -- SystemCoreClockUpdate()
164 ---------------------------------------------------------------------------- */
165
166void SystemCoreClockUpdate(void)
167{
168 volatile uint32_t *M7_ClockRoot = (volatile uint32_t *)(&(CCM)->ROOT[1].TARGET_ROOT);
169 uint32_t pre = ((*M7_ClockRoot & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U;
170 uint32_t post = ((*M7_ClockRoot & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + 1U;
171
172 uint32_t freq = 0U;
173
174 switch ((*M7_ClockRoot & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT)
175 {
176 case 0U: /* OSC 24M Clock */
177 freq = CPU_XTAL_SOSC_CLK_24MHZ;
178 break;
179 case 1U: /* System PLL2 DIV5 */
180 freq = GetIntegerPllFreq(&(CCM_ANALOG->SYS_PLL2_GEN_CTRL)) / 5U; /* Get System PLL2 DIV5 freq */
181 break;
182 case 2U: /* System PLL2 DIV4 */
183 freq = GetIntegerPllFreq(&(CCM_ANALOG->SYS_PLL2_GEN_CTRL)) / 4U; /* Get System PLL2 DIV4 freq */
184 break;
185 case 3U: /* System PLL1 DIV3 */
186 freq = GetIntegerPllFreq(&(CCM_ANALOG->SYS_PLL1_GEN_CTRL)) / 3U; /* Get System PLL1 DIV3 freq */
187 break;
188 case 4U: /* System PLL1 */
189 freq = GetIntegerPllFreq(&(CCM_ANALOG->SYS_PLL1_GEN_CTRL)); /* Get System PLL1 freq */
190 break;
191 case 5U: /* AUDIO PLL1 */
192 freq = GetFracPllFreq(&(CCM_ANALOG->AUDIO_PLL1_GEN_CTRL)); /* Get AUDIO PLL1 freq */
193 break;
194 case 6U: /* VIDEO PLL1 */
195 freq = GetFracPllFreq(&(CCM_ANALOG->VIDEO_PLL1_GEN_CTRL)); /* Get VIDEO PLL1 freq */
196 break;
197 case 7U: /* System PLL3 */
198 freq = GetIntegerPllFreq(&(CCM_ANALOG->SYS_PLL3_GEN_CTRL)); /* Get System PLL3 freq */
199 break;
200 default:
201 freq = CPU_XTAL_SOSC_CLK_24MHZ;
202 break;
203 }
204
205 SystemCoreClock = freq / pre / post;
206}
207
208/* ----------------------------------------------------------------------------
209 -- SystemInitHook()
210 ---------------------------------------------------------------------------- */
211
212__attribute__((weak)) void SystemInitHook(void)
213{
214 /* Void implementation of the weak function. */
215}
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